@W: CG360 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\fftSm.v":502:7:502:15|Removing wire load_over, as there is no assignment to it.
@W: CL265 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\fftSm.v":675:2:675:7|Removing unused bit 6 of mask1_r[6:0]. Either assign all bits or reduce the width of the signal.
@W: CG133 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":412:13:412:17|Object tick2 is declared but not assigned. Either assign a value or remove the declaration.
@W: CL168 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\fftSm.v":234:61:234:72|Removing instance wStage_dly_2 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\fftSm.v":118:38:118:50|Removing instance edge_detect_0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CG133 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFFT_0\rtl\in_place\vlog\core\fftDp.v":267:19:267:27|Object wA_bfly_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFFT_0\rtl\in_place\vlog\core\fftDp.v":268:19:268:27|Object wA_load_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFFT_0\rtl\in_place\vlog\core\fftDp.v":270:6:270:15|Object wEn_bfly_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFFT_0\rtl\in_place\vlog\core\fftDp.v":270:18:270:26|Object wEn_odd_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFFT_0\rtl\in_place\vlog\core\fftDp.v":270:29:270:38|Object wEn_even_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\mac_lib.v":69:13:69:20|Removing wire sel_cdin, as there is no assignment to it.
@W: CG133 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":590:22:590:32|Object scale_exp_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":590:35:590:49|Object scale_exp_count is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFFT_0\rtl\in_place\vlog\core\COREFFT.v":86:20:86:24|Removing wire outPQ, as there is no assignment to it.
@W: CG360 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFFT_0\rtl\in_place\vlog\core\COREFFT.v":87:16:87:24|Removing wire ctrl_outp, as there is no assignment to it.
@W: CL318 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFFT_0\rtl\in_place\vlog\core\COREFFT_TOP.v":86:34:86:36|*Output RFS has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFFT_0\rtl\in_place\vlog\core\COREFFT_TOP.v":86:39:86:49|*Output OVFLOW_FLAG has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CG133 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\COREFIR\8.6.101\rtl\vlog\core\kit.v":192:13:192:17|Object tick2 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFIR_0\rtl\vlog\core\enum_SmFu4\mac.v":90:23:90:31|Removing wire cdout_ext, as there is no assignment to it.
@W: CG360 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFIR_0\rtl\vlog\core\enum_SmFu4\mac.v":90:34:90:41|Removing wire cdin_ext, as there is no assignment to it.
@W: CG360 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFIR_0\rtl\vlog\core\enum_SmFu4\mac.v":91:23:91:30|Removing wire pre_pout, as there is no assignment to it.
@W: CG360 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFIR_0\rtl\vlog\core\enum_SmFu4\mac.v":92:14:92:17|Removing wire dumb, as there is no assignment to it.
@W: CG360 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFIR_0\rtl\vlog\core\enum_SmFu4\mac.v":168:23:168:30|Removing wire coef_val, as there is no assignment to it.
@W: CG360 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFIR_0\rtl\vlog\core\enum_SmFu4\mac.v":266:23:266:30|Removing wire coef_val, as there is no assignment to it.
@W: CG133 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFIR_0\rtl\vlog\core\enum_SmFu4\enum_fir.v":108:7:108:12|Object filled is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFIR_0\rtl\vlog\core\enum_SmFu4\enum_fir.v":110:7:110:20|Object add_valid_tick is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFIR_0\rtl\vlog\core\enum_SmFu4\enum_fir.v":110:23:110:37|Object add_valid_tick2 is declared but not assigned. Either assign a value or remove the declaration.
@W: CL318 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\top\COREFIR_0\rtl\vlog\core\top\COREFIR.v":96:62:96:66|*Output DATAO has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CG296 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\hdl\DATA_HANDLE_FSM.v":109:8:109:12|Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list.
@W: CG290 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\hdl\DATA_HANDLE_FSM.v":111:6:111:7|Referenced variable FIR_ENABLE is not in sensitivity list.
@W: CG290 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\hdl\DATA_HANDLE_FSM.v":119:19:119:29|Referenced variable FFT_RE_DATA is not in sensitivity list.
@W: CG290 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\hdl\DATA_HANDLE_FSM.v":114:19:114:30|Referenced variable FIR_DATA_OUT is not in sensitivity list.
@W: CG290 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\hdl\DATA_HANDLE_FSM.v":124:19:124:29|Referenced variable FFT_IM_DATA is not in sensitivity list.
@W: CL118 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\hdl\DATA_HANDLE_FSM.v":111:6:111:7|Latch generated from always block for signal PRDATA[15:0]; possible missing assignment in an if or case statement.
@W: CL118 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\hdl\DATA_HANDLE_FSM.v":111:6:111:7|Latch generated from always block for signal FIR_RADDR[9:0]; possible missing assignment in an if or case statement.
@W: CL118 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\hdl\DATA_HANDLE_FSM.v":111:6:111:7|Latch generated from always block for signal FFT_RE_RADDR[9:0]; possible missing assignment in an if or case statement.
@W: CL118 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\hdl\DATA_HANDLE_FSM.v":111:6:111:7|Latch generated from always block for signal FFT_IM_RADDR[9:0]; possible missing assignment in an if or case statement.
@W: CL190 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\hdl\DATA_HANDLE_FSM.v":128:0:128:5|Optimizing register bit PREADY to a constant 1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\hdl\DATA_HANDLE_FSM.v":128:0:128:5|Pruning unused register PREADY. Make sure that there are no unused intermediate registers.
@W: CG360 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":244:12:244:20|Removing wire IA_PRDATA, as there is no assignment to it.
@W: CL169 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Pruning unused register count_ddr[13:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1581:4:1581:9|Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1517:4:1517:9|Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1485:4:1485:9|Pruning unused register count_sdif0[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif0_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif0_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_ddr_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning unused register count_ddr_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Pruning unused register count_sdif0_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning unused register count_ddr_enable. Make sure that there are no unused intermediate registers.
@W: CL177 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif0_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL190 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers.
@W: CL318 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\FIR_FILTER\FABOSC_0\FIR_FILTER_FABOSC_0_OSC.v":17:7:17:20|*Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\FIR_FILTER\FABOSC_0\FIR_FILTER_FABOSC_0_OSC.v":18:7:18:20|*Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\FIR_FILTER\FABOSC_0\FIR_FILTER_FABOSC_0_OSC.v":19:7:19:16|*Output XTLOSC_CCC has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\work\FIR_FILTER\FABOSC_0\FIR_FILTER_FABOSC_0_OSC.v":20:7:20:16|*Output XTLOSC_O2F has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL177 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif0_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL246 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\hdl\DATA_HANDLE_FSM.v":60:24:60:28|Input port bits 15 to 12 of PADDR[15:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\hdl\DATA_HANDLE_FSM.v":60:24:60:28|Input port bits 1 to 0 of PADDR[15:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL260 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":560:2:560:7|Pruning register bit 16 of outQ[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL246 :"C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":369:22:369:24|Input port bits 42 to 32 of inp[43:0] are unused. Assign logic for all port bits or change the input port size.

