@W: BN132 :"e:\libero_11p7_updates\downloaded\sf2_eval_fir_filter_demo_df\design files\fir_filter_demo\component\actel\directcore\corefft\6.4.105\rtl\in_place\vlog\core\fftsm.v":675:2:675:7|Removing sequential instance COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_wA_0.timer1_r[6:0],  because it is equivalent to instance COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_wA_0.timer_r[6:0]
@W: BN132 :"e:\libero_11p7_updates\downloaded\sf2_eval_fir_filter_demo_df\design files\fir_filter_demo\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance FIR_FILTER_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int,  because it is equivalent to instance FIR_FILTER_0.CORERESETP_0.FDDR_CORE_RESET_N_int
@W: MT462 :"e:\libero_11p7_updates\downloaded\sf2_eval_fir_filter_demo_df\design files\fir_filter_demo\hdl\data_handle_fsm.v":111:9:121:33|Net DATAHANDLE_FSM_0.FIR_RADDR6 appears to be an unidentified clock source. Assuming default frequency. 
@W: MT462 :"e:\libero_11p7_updates\downloaded\sf2_eval_fir_filter_demo_df\design files\fir_filter_demo\hdl\data_handle_fsm.v":111:9:116:33|Net DATAHANDLE_FSM_0.FIR_RADDR5 appears to be an unidentified clock source. Assuming default frequency. 
@W: MT462 :"e:\libero_11p7_updates\downloaded\sf2_eval_fir_filter_demo_df\design files\fir_filter_demo\hdl\data_handle_fsm.v":111:9:111:28|Net DATAHANDLE_FSM_0.FIR_RADDR4 appears to be an unidentified clock source. Assuming default frequency. 
@W: MT462 :"e:\libero_11p7_updates\downloaded\sf2_eval_fir_filter_demo_df\design files\fir_filter_demo\hdl\data_handle_fsm.v":111:9:121:33|Net DATAHANDLE_FSM_0.un1_FIR_ENABLE_2 appears to be an unidentified clock source. Assuming default frequency. 
@W: MT532 :"e:\libero_11p7_updates\downloaded\sf2_eval_fir_filter_demo_df\design files\fir_filter_demo\hdl\data_handle_fsm.v":111:6:111:7|Found signal identified as System clock which controls 46 sequential elements including DATAHANDLE_FSM_0.PRDATA[15:0].  Using this clock, which has no specified timing constraint, can adversely impact design performance. 
@W: MT530 :"e:\libero_11p7_updates\downloaded\sf2_eval_fir_filter_demo_df\design files\fir_filter_demo\component\work\fir_filter_top\coef_buffer\fir_filter_top_coef_buffer_tpsram.v":31:12:31:49|Found inferred clock FIR_FILTER_CCC_0_FCCC|GL0_net_inferred_clock which controls 2291 sequential elements including Coef_Buffer.FIR_FILTER_top_Coef_Buffer_TPSRAM_R0C0. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"e:\libero_11p7_updates\downloaded\sf2_eval_fir_filter_demo_df\design files\fir_filter_demo\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":912:4:912:9|Found inferred clock FIR_FILTER_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 15 sequential elements including FIR_FILTER_0.CORERESETP_0.sdif3_areset_n_rcosc_q1. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"e:\libero_11p7_updates\downloaded\sf2_eval_fir_filter_demo_df\design files\fir_filter_demo\component\actel\directcore\corefft\6.4.105\rtl\in_place\vlog\core\kit.v":203:6:203:11|Found inferred clock fft_inpl_slowClock|divider_inferred_clock[2] which controls 16 sequential elements including COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.ngrst2rst_0.sync_ngrst_0.genblk1\.delayLine_3_. This clock has no specified timing constraint which may adversely impact design performance. 
