Timing Multi Corner Report Max Delay Analysis

SmartTime Version 2021.1.0.17

Microsemi Corporation - Microsemi Libero Software Release v2021.1 (Version 2021.1.0.17)

Date: Sun May 30 19:11:45 2021

Design top
Family SmartFusion2
Die M2S090TS
Package 484 FBGA
Temperature Range 0 - 85 C
Voltage Range 1.14 - 1.26 V
Speed Grade -1
Design State Post-Layout
Data source Production
Multi Corner Report Operating Conditions BEST, TYPICAL, WORST
Scenario for Timing Analysis timing_analysis

Summary

Clock Domain Required Period (ns) Required Frequency (MHz) Worst Slack (ns) Operating Conditions
COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q N/A N/A
FIR_FILTER_0/CCC_0/GL0 10.000 100.000 5.293 WORST
FIR_FILTER_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 20.000 50.000

Worst Slack (ns) Operating Conditions
Input to Output

Clock Domain COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:CLK COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:B_DIN[7] 8.032 13.120 0.290 8.184 WORST
Path 2 COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:CLK COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:A_DIN[7] 8.010 13.098 0.279 8.151 WORST
Path 3 COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:CLK COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:B_DIN[7] 7.588 12.667 0.290 7.731 WORST
Path 4 COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:CLK COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:A_DIN[7] 7.611 12.690 0.236 7.700 WORST
Path 5 COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:CLK COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:A_DIN[0] 7.461 12.549 0.307 7.630 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:CLK
To: COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:B_DIN[7]
data required time N/C
data arrival time - 13.120
slack N/C
Data arrival time calculation
COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q 0.000 0.000
COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q Clock source + 0.000 0.000 f
COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]:A net COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2] + 0.310 0.310 f
COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]:Y cell ADLIB:CFG1 + 0.221 0.531 1 r
COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]:An net COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2] + 2.752 3.283 f
COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]:YEn cell ADLIB:GBM + 0.374 3.657 2 f
COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1:An net COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_YWn_GEast + 0.614 4.271 f
COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1:YR cell ADLIB:RGB + 0.316 4.587 16 r
COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:CLK net COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_YR + 0.501 5.088 r
COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:Q cell ADLIB:SLE + 0.087 5.175 72 r
COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m2_i:B net COREFFT_0/genblk1.DUT_INPLACE/twid_wA_w[1] + 1.434 6.609 r
COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m2_i:Y cell ADLIB:CFG2 + 0.225 6.834 2 f
COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m188_1:C net COREFFT_0/genblk1.DUT_INPLACE/lut_0/N_3_i + 0.647 7.481 f
COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m188_1:Y cell ADLIB:CFG4 + 0.164 7.645 1 f
COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m188_2_1_1:A net COREFFT_0/genblk1.DUT_INPLACE/lut_0/m188_1 + 0.656 8.301 f
COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m188_2_1_1:Y cell ADLIB:CFG4 + 0.319 8.620 2 r
COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m188_2_1_1_0:C net COREFFT_0/genblk1.DUT_INPLACE/lut_0/m188_2_1_1 + 0.608 9.228 r
COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m188_2_1_1_0:Y cell ADLIB:CFG4 + 0.158 9.386 1 r
COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m188_2_1:B net COREFFT_0/genblk1.DUT_INPLACE/lut_0/m188_2_1_1_0 + 0.222 9.608 r
COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m188_2_1:Y cell ADLIB:CFG4 + 0.158 9.766 1 r
COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m193:C net COREFFT_0/genblk1.DUT_INPLACE/lut_0/m188_2_1 + 0.625 10.391 r
COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m193:Y cell ADLIB:CFG3 + 0.143 10.534 2 f
COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m194:A net COREFFT_0/genblk1.DUT_INPLACE/lut_0/m193 + 0.811 11.345 f
COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_31_0_.m194:Y cell ADLIB:CFG3 + 0.164 11.509 1 f
COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/top_COREFFT_0_ram_smGen_R0C0/CFG_29:B net COREFFT_0/genblk1.DUT_INPLACE/twidData_w[7] + 1.345 12.854 f
COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/top_COREFFT_0_ram_smGen_R0C0/CFG_29:IPB cell ADLIB:CFG2_IP_BC + 0.201 13.055 1 f
COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:B_DIN[7] net COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/top_COREFFT_0_ram_smGen_R0C0/B_DIN_net[7] + 0.065 13.120 f
data arrival time 13.120
Data required time calculation
COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q N/C N/C
COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q Clock source + 0.000 N/C f
COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]:A net COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2] + 0.310 N/C f
COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2]:Y cell ADLIB:CFG1 + 0.221 N/C 1 r
COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]:An net COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME[2] + 2.752 N/C f
COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]:YEn cell ADLIB:GBM + 0.374 N/C 2 f
COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_RGB0:An net COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_YWn_GEast + 0.621 N/C f
COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_RGB0:YL cell ADLIB:RGB + 0.317 N/C 1 r
COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/top_COREFFT_0_ram_smGen_R0C0/FF_24:CLK net COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNI6AME_0[2]/U0_RGB1_RGB0_rgbl_net_1 + 0.487 N/C r
COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/top_COREFFT_0_ram_smGen_R0C0/FF_24:IPCLKn cell ADLIB:SLE_IP_CLK + 0.059 N/C 1 f
COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:B_CLK net COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/top_COREFFT_0_ram_smGen_R0C0/B_CLK_net + 0.085 N/C r
COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/SmFu4_sram.smGen_RAM_0/top_COREFFT_0_ram_smGen_R0C0/INST_RAM1K18_IP:B_DIN[7] Library setup time ADLIB:RAM1K18_IP - 0.290 N/C
Operating Conditions WORST

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET FIR_FILTER_0/CCC_0/GL0 to COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q

No Path

Clock Domain FIR_FILTER_0/CCC_0/GL0

Info: The maximum frequency of this clock domain is limited by the period of pin FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[14] 3.768 5.293 10.034 15.327 0.939 4.707 WORST
Path 2 FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[6] 3.845 5.321 10.111 15.432 0.834 4.679 WORST
Path 3 FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[11] 3.781 5.367 10.047 15.414 0.852 4.633 WORST
Path 4 FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[5] 3.757 5.380 10.023 15.403 0.863 4.620 WORST
Path 5 FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[12] 3.752 5.385 10.018 15.403 0.863 4.615 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE
To: FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[14]
data required time 15.327
data arrival time - 10.034
slack 5.293
Data arrival time calculation
FIR_FILTER_0/CCC_0/GL0 0.000 0.000
FIR_FILTER_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 3.859 3.859
FIR_FILTER_0/CCC_0/GL0_INST:An net FIR_FILTER_0/CCC_0/GL0_net + 0.461 4.320 r
FIR_FILTER_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 4.498 29 f
FIR_FILTER_0/CCC_0/GL0_INST/U0_RGB1:An net FIR_FILTER_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.620 5.118 f
FIR_FILTER_0/CCC_0/GL0_INST/U0_RGB1:YR cell ADLIB:RGB + 0.316 5.434 1 r
FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B net FIR_FILTER_0/CCC_0/GL0_INST/U0_RGB1_YR + 0.407 5.841 r
FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB cell ADLIB:IP_INTERFACE + 0.209 6.050 1 r
FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE net FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/CLK_BASE_net + 0.216 6.266 r
FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_SEL cell ADLIB:MSS_075_IP + 1.328 7.594 1 r
FIR_FILTER_0/CoreAPB3_0/iPSELS[0]:C net FIR_FILTER_0/FIR_FILTER_MSS_TMP_0_FIC_0_APB_MASTER_PSELx + 0.698 8.292 r
FIR_FILTER_0/CoreAPB3_0/iPSELS[0]:Y cell ADLIB:CFG4 + 0.158 8.450 18 r
FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST_RNO_13:A net FIR_FILTER_0_AMBA_SLAVE_0_PSELx + 0.420 8.870 r
FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST_RNO_13:Y cell ADLIB:CFG2 + 0.074 8.944 1 r
FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_9:B net FIR_FILTER_0/FIR_FILTER_MSS_0/FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_m[14] + 0.645 9.589 r
FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_9:IPB cell ADLIB:IP_INTERFACE + 0.209 9.798 1 r
FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[14] net FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/F_HM0_RDATA_net[14] + 0.236 10.034 r
data arrival time 10.034
Data required time calculation
FIR_FILTER_0/CCC_0/GL0 Clock Constraint 10.000 10.000
FIR_FILTER_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 10.000 r
Clock generation + 3.859 13.859
FIR_FILTER_0/CCC_0/GL0_INST:An net FIR_FILTER_0/CCC_0/GL0_net + 0.461 14.320 r
FIR_FILTER_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 14.498 29 f
FIR_FILTER_0/CCC_0/GL0_INST/U0_RGB1:An net FIR_FILTER_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.620 15.118 f
FIR_FILTER_0/CCC_0/GL0_INST/U0_RGB1:YR cell ADLIB:RGB + 0.316 15.434 1 r
FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B net FIR_FILTER_0/CCC_0/GL0_INST/U0_RGB1_YR + 0.407 15.841 r
FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB cell ADLIB:IP_INTERFACE + 0.209 16.050 1 r
FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE net FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/CLK_BASE_net + 0.216 16.266 r
FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:F_HM0_RDATA[14] Library setup time ADLIB:MSS_075_IP - 0.939 15.327
data required time 15.327
Operating Conditions WORST

SET External Setup

No Path

SET Clock to Output

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Clock to Out (ns) Operating Conditions
Path 1 FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE MMUART_1_TXD 6.004 12.270 12.270 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE
To: MMUART_1_TXD
data required time N/C
data arrival time - 12.270
slack N/C
Data arrival time calculation
FIR_FILTER_0/CCC_0/GL0 0.000 0.000
FIR_FILTER_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 3.859 3.859
FIR_FILTER_0/CCC_0/GL0_INST:An net FIR_FILTER_0/CCC_0/GL0_net + 0.461 4.320 r
FIR_FILTER_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 4.498 29 f
FIR_FILTER_0/CCC_0/GL0_INST/U0_RGB1:An net FIR_FILTER_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.620 5.118 f
FIR_FILTER_0/CCC_0/GL0_INST/U0_RGB1:YR cell ADLIB:RGB + 0.316 5.434 1 r
FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B net FIR_FILTER_0/CCC_0/GL0_INST/U0_RGB1_YR + 0.407 5.841 r
FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB cell ADLIB:IP_INTERFACE + 0.209 6.050 1 r
FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE net FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/CLK_BASE_net + 0.216 6.266 r
FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT cell ADLIB:MSS_075_IP + 2.019 8.285 1 f
FIR_FILTER_0/FIR_FILTER_MSS_0/MMUART_1_TXD_PAD/U_IOPAD:D net FIR_FILTER_0/FIR_FILTER_MSS_0/MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT + 1.319 9.604 f
FIR_FILTER_0/FIR_FILTER_MSS_0/MMUART_1_TXD_PAD/U_IOPAD:PAD cell ADLIB:IOPAD_TRI + 2.666 12.270 0 f
MMUART_1_TXD net MMUART_1_TXD + 0.000 12.270 f
data arrival time 12.270
Data required time calculation
FIR_FILTER_0/CCC_0/GL0 N/C N/C
FIR_FILTER_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 N/C r
Clock generation + 3.859 N/C
MMUART_1_TXD N/C f
Operating Conditions WORST

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 FIR_FILTER_0/CORERESETP_0/MSS_HPMS_READY_int_rep:CLK COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[14].a_tap/symm_tap.pipe_reg_0/genblk1.delayLine[0][8]:ALn 3.182 6.429 9.151 15.580 0.353 3.571 0.036 WORST
Path 2 FIR_FILTER_0/CORERESETP_0/MSS_HPMS_READY_int_rep:CLK COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[14].a_tap/symm_tap.pipe_reg_0/genblk1.delayLine[0][6]:ALn 3.182 6.429 9.151 15.580 0.353 3.571 0.036 WORST
Path 3 FIR_FILTER_0/CORERESETP_0/MSS_HPMS_READY_int_rep:CLK COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[14].a_tap/symm_tap.pipe_reg_0/genblk1.delayLine[0][4]:ALn 3.182 6.429 9.151 15.580 0.353 3.571 0.036 WORST
Path 4 FIR_FILTER_0/CORERESETP_0/MSS_HPMS_READY_int_rep:CLK COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[14].a_tap/symm_tap.pipe_reg_0/genblk1.delayLine[0][2]:ALn 3.182 6.429 9.151 15.580 0.353 3.571 0.036 WORST
Path 5 FIR_FILTER_0/CORERESETP_0/MSS_HPMS_READY_int_rep:CLK COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[14].a_tap/symm_tap.pipe_reg_0/genblk1.delayLine[0][12]:ALn 3.182 6.429 9.151 15.580 0.353 3.571 0.036 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: FIR_FILTER_0/CORERESETP_0/MSS_HPMS_READY_int_rep:CLK
To: COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[14].a_tap/symm_tap.pipe_reg_0/genblk1.delayLine[0][8]:ALn
data required time 15.580
data arrival time - 9.151
slack 6.429
Data arrival time calculation
FIR_FILTER_0/CCC_0/GL0 0.000 0.000
FIR_FILTER_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 3.859 3.859
FIR_FILTER_0/CCC_0/GL0_INST:An net FIR_FILTER_0/CCC_0/GL0_net + 0.461 4.320 r
FIR_FILTER_0/CCC_0/GL0_INST:YWn cell ADLIB:GBM + 0.177 4.497 7 f
FIR_FILTER_0/CCC_0/GL0_INST/U0_RGB1_RGB22:An net FIR_FILTER_0/CCC_0/GL0_INST/U0_YWn + 0.620 5.117 f
FIR_FILTER_0/CCC_0/GL0_INST/U0_RGB1_RGB22:YR cell ADLIB:RGB + 0.316 5.433 14 r
FIR_FILTER_0/CORERESETP_0/MSS_HPMS_READY_int_rep:CLK net FIR_FILTER_0/CCC_0/GL0_INST/U0_RGB1_RGB22_rgbr_net_1 + 0.536 5.969 r
FIR_FILTER_0/CORERESETP_0/MSS_HPMS_READY_int_rep:Q cell ADLIB:SLE + 0.087 6.056 17 r
FIR_FILTER_0/CORERESETP_0/MSS_HPMS_READY_int_rep_RNIA38B:An net FIR_FILTER_0/CORERESETP_0/MSS_HPMS_READY_int_rep + 1.225 7.281 f
FIR_FILTER_0/CORERESETP_0/MSS_HPMS_READY_int_rep_RNIA38B:YEn cell ADLIB:GBM + 0.374 7.655 23 f
FIR_FILTER_0/CORERESETP_0/MSS_HPMS_READY_int_rep_RNIA38B/U0_RGB1_RGB18:An net FIR_FILTER_0/CORERESETP_0/MSS_HPMS_READY_int_rep_RNIA38B/U0_YWn_GEast + 0.617 8.272 f
FIR_FILTER_0/CORERESETP_0/MSS_HPMS_READY_int_rep_RNIA38B/U0_RGB1_RGB18:YR cell ADLIB:RGB + 0.316 8.588 40 r
COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[14].a_tap/symm_tap.pipe_reg_0/genblk1.delayLine[0][8]:ALn net FIR_FILTER_0/CORERESETP_0/MSS_HPMS_READY_int_rep_RNIA38B/U0_RGB1_RGB18_rgbr_net_1 + 0.563 9.151 r
data arrival time 9.151
Data required time calculation
FIR_FILTER_0/CCC_0/GL0 Clock Constraint 10.000 10.000
FIR_FILTER_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 10.000 r
Clock generation + 3.859 13.859
FIR_FILTER_0/CCC_0/GL0_INST:An net FIR_FILTER_0/CCC_0/GL0_net + 0.461 14.320 r
FIR_FILTER_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 14.498 29 f
FIR_FILTER_0/CCC_0/GL0_INST/U0_RGB1_RGB21:An net FIR_FILTER_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.610 15.108 f
FIR_FILTER_0/CCC_0/GL0_INST/U0_RGB1_RGB21:YR cell ADLIB:RGB + 0.316 15.424 59 r
COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[14].a_tap/symm_tap.pipe_reg_0/genblk1.delayLine[0][8]:CLK net FIR_FILTER_0/CCC_0/GL0_INST/U0_RGB1_RGB21_rgbr_net_1 + 0.509 15.933 r
COREFIR_0/enum_g4.enum_fir_g4/fir_enum_g4_0/taps.tap[14].a_tap/symm_tap.pipe_reg_0/genblk1.delayLine[0][8]:ALn Library recovery time ADLIB:SLE - 0.353 15.580
data required time 15.580
Operating Conditions WORST

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q to FIR_FILTER_0/CCC_0/GL0

No Path

Clock Domain FIR_FILTER_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Path Set Pin to Pin

SET Input to Output

No Path

Path Set User Sets