#--  Synopsys, Inc.
#--  Version R-2020.09M-SP1-1
#--  Project file C:\WFH_Tasks\IGLOO2_SF2_v12.6_QR\DG0438\Libero_Project\synthesis\run_options.txt
#--  Written on Sun May 30 18:57:24 2021


#project files
add_file -include "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/work/top/COREFIR_0/rtl/vlog/core/enum_SmFu4/top_COREFIR_0_coef.v"
add_file -verilog "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/hdl/DATA_HANDLE_FSM.v"
add_file -verilog "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/hdl/FILTER_CONTROL_FSM.v"
add_file -verilog "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/work/FIR_FILTER/CCC_0/FIR_FILTER_CCC_0_FCCC.v"
add_file -verilog "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/Actel/SgCore/OSC/2.0.101/osc_comps.v"
add_file -verilog "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/work/FIR_FILTER/FABOSC_0/FIR_FILTER_FABOSC_0_OSC.v"
add_file -verilog "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/work/FIR_FILTER_MSS/FIR_FILTER_MSS_syn.v"
add_file -verilog "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/work/FIR_FILTER_MSS/FIR_FILTER_MSS.v"
add_file -verilog "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/Actel/DirectCore/CoreResetP/7.1.100/rtl/vlog/core/coreresetp_pcie_hotreset.v"
add_file -verilog "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/Actel/DirectCore/CoreResetP/7.1.100/rtl/vlog/core/coreresetp.v"
add_file -verilog -lib COREAPB3_LIB "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3_muxptob3.v"
add_file -verilog -lib COREAPB3_LIB "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3_iaddr_reg.v"
add_file -verilog -lib COREAPB3_LIB "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3.v"
add_file -verilog "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/work/FIR_FILTER/FIR_FILTER.v"
add_file -verilog "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/work/top/Coef_Buffer/top_Coef_Buffer_TPSRAM.v"
add_file -verilog "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/work/top/FFT_IM_Buffer/top_FFT_IM_Buffer_TPSRAM.v"
add_file -verilog "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/work/top/FFT_RE_Buffer/top_FFT_RE_Buffer_TPSRAM.v"
add_file -verilog "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/work/top/FIR_IN_Buffer/top_FIR_IN_Buffer_TPSRAM.v"
add_file -verilog "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/work/top/FIR_OUT_Buffer/top_FIR_OUT_Buffer_TPSRAM.v"
add_file -verilog -lib COREFFT_LIB "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/Actel/DirectCore/COREFFT/7.1.100/rtl/in_place/vlog/core/kit.v"
add_file -verilog -lib COREFFT_LIB "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/Actel/DirectCore/COREFFT/7.1.100/rtl/in_place/vlog/core/mac_lib.v"
add_file -verilog -lib COREFFT_LIB "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/Actel/DirectCore/COREFFT/7.1.100/rtl/in_place/vlog/core/cmplx.v"
add_file -verilog -lib COREFFT_LIB "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/Actel/DirectCore/COREFFT/7.1.100/rtl/in_place/vlog/core/fftSm.v"
add_file -verilog -lib COREFFT_LIB "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/work/top/COREFFT_0/rtl/in_place/vlog/core/top_COREFFT_0_ram_smGen.v"
add_file -verilog -lib COREFFT_LIB "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/work/top/COREFFT_0/rtl/in_place/vlog/core/fftDp.v"
add_file -verilog -lib COREFFT_LIB "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/work/top/COREFFT_0/twiddle32.v"
add_file -verilog -lib COREFFT_LIB "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/work/top/COREFFT_0/rtl/in_place/vlog/core/COREFFT.v"
add_file -verilog -lib COREFFT_LIB "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/work/top/COREFFT_0/rtl/in_place/vlog/core/COREFFT_TOP.v"
add_file -verilog -lib COREFIR_LIB "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/Actel/DirectCore/COREFIR/8.6.101/rtl/vlog/core/kit.v"
add_file -verilog -lib COREFIR_LIB "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/work/top/COREFIR_0/rtl/vlog/core/enum_SmFu4/mac_lib.v"
add_file -verilog -lib COREFIR_LIB "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/work/top/COREFIR_0/rtl/vlog/core/enum_SmFu4/mac.v"
add_file -verilog -lib COREFIR_LIB "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/work/top/COREFIR_0/rtl/vlog/core/enum_SmFu4/coef_store.v"
add_file -verilog -lib COREFIR_LIB "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/work/top/COREFIR_0/rtl/vlog/core/enum_SmFu4/enum_fir.v"
add_file -verilog -lib COREFIR_LIB "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/work/top/COREFIR_0/rtl/vlog/core/enum_SmFu4/enum_COREFIR.v"
add_file -verilog -lib COREFIR_LIB "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/work/top/COREFIR_0/rtl/vlog/core/top/COREFIR.v"
add_file -verilog "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/component/work/top/top.v"
add_file -fpga_constraint "C:/WFH_Tasks/IGLOO2_SF2_v12.6_QR/DG0438/Libero_Project/designer/top/synthesis.fdc"


#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std v2001

#device options
set_option -technology SmartFusion2
set_option -part M2S090TS
set_option -package FBGA484
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0

# hdl_compiler_options
set_option -distributed_compile 0
set_option -hdl_strict_syntax 0

# mapper_without_write_options
set_option -frequency 100.000
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 0
set_option -write_structural_verilog 0
set_option -write_vhdl 0

# actel_options
set_option -rw_check_on_ram 0

# Microchip G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 12
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -seqshift_to_uram 0
set_option -disable_io_insertion 0
set_option -opcond COMTC
set_option -retiming 0
set_option -report_path 4000
set_option -update_models_cp 0
set_option -preserve_registers 0
set_option -disable_ramindex 0
set_option -rep_clkint_driver 1
set_option -microsemi_enhanced_flow 1
set_option -ternary_adder_decomp 66
set_option -pack_uram_addr_reg 1

# Microchip SmartFusion2
set_option -min_cdc_sync_flops 2
set_option -unsafe_cdc_netlist_property 0

# NFilter
set_option -no_sequential_opt 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./top.edn"
impl -active "synthesis"
