//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Fri May 28 16:30:18 2021
// Version: v2021.1 2021.1.0.17
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

// top
module top(
    // Inputs
    DEVRST_N,
    MMUART_1_RXD,
    // Outputs
    MMUART_1_TXD
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input  DEVRST_N;
input  MMUART_1_RXD;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output MMUART_1_TXD;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire   [15:0]  Coef_Buffer_RD;
wire   [15:0]  COREFFT_0_DATAO_IM;
wire   [15:0]  COREFFT_0_DATAO_RE;
wire           COREFFT_0_OUTP_READY;
wire           COREFIR_0_DATAO_VALID;
wire   [30:15] COREFIR_0_FIRO30to15;
wire   [5:0]   DATAHANDLE_FSM_0_COEF_WADDR;
wire           DATAHANDLE_FSM_0_COEF_WR_EN;
wire   [9:0]   DATAHANDLE_FSM_0_FFT_IM_RADDR;
wire   [9:0]   DATAHANDLE_FSM_0_FFT_RE_RADDR;
wire   [15:0]  DATAHANDLE_FSM_0_FIR_COEF_DATA_IN;
wire           DATAHANDLE_FSM_0_FIR_FFT_RD_ENABLE_0;
wire   [9:0]   DATAHANDLE_FSM_0_FIR_RADDR;
wire   [9:0]   DATAHANDLE_FSM_0_FIR_WADDR;
wire           DATAHANDLE_FSM_0_FIR_WR_ENABLE;
wire           DATAHANDLE_FSM_0_RCLK;
wire           DATAHANDLE_FSM_0_SEL;
wire           DATAHANDLE_FSM_0_WCLK;
wire           DEVRST_N;
wire   [15:0]  FFT_IM_Buffer_RD;
wire   [15:0]  FFT_RE_Buffer_RD;
wire           FILTERCONTROL_FSM_0_COEF_ON;
wire   [5:0]   FILTERCONTROL_FSM_0_COEF_RADDR;
wire           FILTERCONTROL_FSM_0_COEF_RD_ENABLE;
wire   [9:0]   FILTERCONTROL_FSM_0_FFT_WADDR;
wire           FILTERCONTROL_FSM_0_FILTER_COMPLETE;
wire   [9:0]   FILTERCONTROL_FSM_0_FIR_WR_ADDR;
wire           FILTERCONTROL_FSM_0_FIR_WR_ENABLE;
wire           FILTERCONTROL_FSM_0_RCLK;
wire           FILTERCONTROL_FSM_0_WCLK;
wire           FIR_FILTER_0_AMBA_SLAVE_0_PENABLE;
wire           FIR_FILTER_0_AMBA_SLAVE_0_PREADY;
wire           FIR_FILTER_0_AMBA_SLAVE_0_PSELx;
wire           FIR_FILTER_0_AMBA_SLAVE_0_PSLVERR;
wire           FIR_FILTER_0_AMBA_SLAVE_0_PWRITE;
wire           FIR_FILTER_0_FIC_0_CLK;
wire           FIR_FILTER_0_GPIO_0_M2F;
wire           FIR_FILTER_0_GPIO_1_M2F;
wire           FIR_FILTER_0_GPIO_2_M2F;
wire           FIR_FILTER_0_MSS_READY;
wire   [15:0]  FIR_IN_Buffer_RD;
wire   [15:0]  FIR_OUT_Buffer_RD;
wire           MMUART_1_RXD;
wire           MMUART_1_TXD_net_0;
wire           MMUART_1_TXD_net_1;
wire   [14:0]  FIRO_slice_0;
wire   [36:31] FIRO_slice_1;
wire   [36:0]  FIRO_net_0;
wire   [1:0]   FIR_ENABLE_net_0;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire   [15:0]  DATAI_IM_const_net_0;
wire           VCC_net;
wire           GND_net;
wire   [3:0]   COEF_SEL_const_net_0;
wire   [11:0]  SAMPLE_ID_const_net_0;
//--------------------------------------------------------------------
// Bus Interface Nets Declarations - Unequal Pin Widths
//--------------------------------------------------------------------
wire   [31:0]  FIR_FILTER_0_AMBA_SLAVE_0_PADDR;
wire   [15:0]  FIR_FILTER_0_AMBA_SLAVE_0_PADDR_0;
wire   [15:0]  FIR_FILTER_0_AMBA_SLAVE_0_PADDR_0_15to0;
wire   [15:0]  FIR_FILTER_0_AMBA_SLAVE_0_PRDATA;
wire   [31:0]  FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_0;
wire   [15:0]  FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_0_15to0;
wire   [31:16] FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_0_31to16;
wire   [31:0]  FIR_FILTER_0_AMBA_SLAVE_0_PWDATA;
wire   [15:0]  FIR_FILTER_0_AMBA_SLAVE_0_PWDATA_0;
wire   [15:0]  FIR_FILTER_0_AMBA_SLAVE_0_PWDATA_0_15to0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign DATAI_IM_const_net_0  = 16'h0000;
assign VCC_net               = 1'b1;
assign GND_net               = 1'b0;
assign COEF_SEL_const_net_0  = 4'h0;
assign SAMPLE_ID_const_net_0 = 12'h000;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign MMUART_1_TXD_net_1 = MMUART_1_TXD_net_0;
assign MMUART_1_TXD       = MMUART_1_TXD_net_1;
//--------------------------------------------------------------------
// Slices assignments
//--------------------------------------------------------------------
assign COREFIR_0_FIRO30to15 = FIRO_net_0[30:15];
assign FIRO_slice_0         = FIRO_net_0[14:0];
assign FIRO_slice_1         = FIRO_net_0[36:31];
//--------------------------------------------------------------------
// Concatenation assignments
//--------------------------------------------------------------------
assign FIR_ENABLE_net_0 = { FIR_FILTER_0_GPIO_1_M2F , FIR_FILTER_0_GPIO_0_M2F };
//--------------------------------------------------------------------
// Bus Interface Nets Assignments - Unequal Pin Widths
//--------------------------------------------------------------------
assign FIR_FILTER_0_AMBA_SLAVE_0_PADDR_0 = { FIR_FILTER_0_AMBA_SLAVE_0_PADDR_0_15to0 };
assign FIR_FILTER_0_AMBA_SLAVE_0_PADDR_0_15to0 = FIR_FILTER_0_AMBA_SLAVE_0_PADDR[15:0];

assign FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_0 = { FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_0_31to16, FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_0_15to0 };
assign FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_0_15to0 = FIR_FILTER_0_AMBA_SLAVE_0_PRDATA[15:0];
assign FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_0_31to16 = 16'h0;

assign FIR_FILTER_0_AMBA_SLAVE_0_PWDATA_0 = { FIR_FILTER_0_AMBA_SLAVE_0_PWDATA_0_15to0 };
assign FIR_FILTER_0_AMBA_SLAVE_0_PWDATA_0_15to0 = FIR_FILTER_0_AMBA_SLAVE_0_PWDATA[15:0];

//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------top_Coef_Buffer_TPSRAM   -   Actel:SgCore:TPSRAM:1.0.102
top_Coef_Buffer_TPSRAM Coef_Buffer(
        // Inputs
        .WD    ( DATAHANDLE_FSM_0_FIR_COEF_DATA_IN ),
        .WADDR ( DATAHANDLE_FSM_0_COEF_WADDR ),
        .RADDR ( FILTERCONTROL_FSM_0_COEF_RADDR ),
        .WEN   ( DATAHANDLE_FSM_0_COEF_WR_EN ),
        .REN   ( FILTERCONTROL_FSM_0_COEF_RD_ENABLE ),
        .WCLK  ( DATAHANDLE_FSM_0_WCLK ),
        .RCLK  ( FILTERCONTROL_FSM_0_RCLK ),
        // Outputs
        .RD    ( Coef_Buffer_RD ) 
        );

//--------top_COREFFT_0_COREFFT   -   Actel:DirectCore:COREFFT:7.1.100
top_COREFFT_0_COREFFT #( 
        .CFG_ARCH      ( 1 ),
        .DATA_BITS     ( 18 ),
        .FFT_SIZE      ( 256 ),
        .FPGA_FAMILY   ( 19 ),
        .INVERSE       ( 0 ),
        .MEMBUF        ( 1 ),
        .ORDER         ( 0 ),
        .POINTS        ( 256 ),
        .SCALE         ( 0 ),
        .SCALE_EXP_ON  ( 0 ),
        .SCALE_ON      ( 1 ),
        .SCALE_SCH     ( 255 ),
        .TWID_BITS     ( 18 ),
        .URAM_MAXDEPTH ( 0 ),
        .WIDTH         ( 16 ) )
COREFFT_0(
        // Inputs
        .CLK          ( FILTERCONTROL_FSM_0_RCLK ),
        .NGRST        ( FIR_FILTER_0_MSS_READY ),
        .DATAI_VALID  ( COREFIR_0_DATAO_VALID ),
        .READ_OUTP    ( VCC_net ), // tied to 1'b1 from definition
        .START        ( VCC_net ), // tied to 1'b1 from definition
        .INVERSE_STRM ( GND_net ), // tied to 1'b0 from definition
        .REFRESH      ( GND_net ), // tied to 1'b0 from definition
        .CLKEN        ( VCC_net ), // tied to 1'b1 from definition
        .RST          ( GND_net ), // tied to 1'b0 from definition
        .DATAI_IM     ( DATAI_IM_const_net_0 ),
        .DATAI_RE     ( COREFIR_0_FIRO30to15 ),
        // Outputs
        .DATAO_VALID  (  ),
        .BUF_READY    (  ),
        .OUTP_READY   ( COREFFT_0_OUTP_READY ),
        .PONG         (  ),
        .OVFLOW_FLAG  (  ),
        .RFS          (  ),
        .DATAO_IM     ( COREFFT_0_DATAO_IM ),
        .DATAO_RE     ( COREFFT_0_DATAO_RE ),
        .SCALE_EXP    (  ) 
        );

//--------top_COREFIR_0_COREFIR   -   Actel:DirectCore:COREFIR:8.6.101
top_COREFIR_0_COREFIR #( 
        .CFG_ARCH      ( 1 ),
        .CLOCK_RATE    ( 10000000 ),
        .COEF_RAM      ( 0 ),
        .COEF_SETS     ( 1 ),
        .COEF_SYMM     ( 1 ),
        .COEF_TYPE     ( 1 ),
        .COEF_UNSIGN   ( 0 ),
        .COEF_WIDTH    ( 16 ),
        .DATA_RAM      ( 0 ),
        .DATA_UNSIGN   ( 0 ),
        .DATA_WIDTH    ( 16 ),
        .DIE_SIZE      ( 25 ),
        .FPGA_FAMILY   ( 19 ),
        .ID_WIDTH      ( 12 ),
        .INP_REG       ( 1 ),
        .L             ( 2 ),
        .M             ( 2 ),
        .RADIX         ( 10 ),
        .SAMPLE_RATE   ( 1000000 ),
        .SAMPLEID      ( 0 ),
        .SYSTOLIC      ( 0 ),
        .TAPS          ( 31 ),
        .URAM_MAXDEPTH ( 0 ) )
COREFIR_0(
        // Inputs
        .NGRST         ( FIR_FILTER_0_MSS_READY ),
        .RSTN          ( VCC_net ),
        .CLK           ( FILTERCONTROL_FSM_0_RCLK ),
        .DATAI_VALID   ( FILTERCONTROL_FSM_0_FIR_WR_ENABLE ),
        .COEFI_VALID   ( FILTERCONTROL_FSM_0_COEF_RD_ENABLE ),
        .COEF_ON       ( FILTERCONTROL_FSM_0_COEF_ON ),
        .COEF_REF      ( GND_net ), // tied to 1'b0 from definition
        .RCLK          ( VCC_net ), // tied to 1'b1 from definition
        .DATAI         ( FIR_IN_Buffer_RD ),
        .COEFI         ( Coef_Buffer_RD ),
        .COEF_SEL      ( COEF_SEL_const_net_0 ), // tied to 4'h0 from definition
        .SAMPLE_ID     ( SAMPLE_ID_const_net_0 ), // tied to 12'h000 from definition
        // Outputs
        .COEF_REF_DONE (  ),
        .READY         (  ),
        .DATAO_VALID   ( COREFIR_0_DATAO_VALID ),
        .COEF_ON_SLOT  (  ),
        .DATAO         (  ),
        .FIRO_ID       (  ),
        .FIRO          ( FIRO_net_0 ) 
        );

//--------DATAHANDLE_FSM
DATAHANDLE_FSM #( 
        .ADDR_WIDTH ( 16 ),
        .DATA_WIDTH ( 16 ) )
DATAHANDLE_FSM_0(
        // Inputs
        .PCLK              ( FIR_FILTER_0_FIC_0_CLK ),
        .PENABLE           ( FIR_FILTER_0_AMBA_SLAVE_0_PENABLE ),
        .PSEL              ( FIR_FILTER_0_AMBA_SLAVE_0_PSELx ),
        .PRESETN           ( FIR_FILTER_0_MSS_READY ),
        .PWRITE            ( FIR_FILTER_0_AMBA_SLAVE_0_PWRITE ),
        .FILTER_COMPLETE   ( FILTERCONTROL_FSM_0_FILTER_COMPLETE ),
        .COEF_LOAD         ( FIR_FILTER_0_GPIO_2_M2F ),
        .PADDR             ( FIR_FILTER_0_AMBA_SLAVE_0_PADDR_0 ),
        .PWDATA            ( FIR_FILTER_0_AMBA_SLAVE_0_PWDATA_0 ),
        .FIR_DATA_OUT      ( FIR_OUT_Buffer_RD ),
        .FIR_ENABLE        ( FIR_ENABLE_net_0 ),
        .FFT_IM_DATA       ( FFT_IM_Buffer_RD ),
        .FFT_RE_DATA       ( FFT_RE_Buffer_RD ),
        // Outputs
        .PREADY            ( FIR_FILTER_0_AMBA_SLAVE_0_PREADY ),
        .PSLVERR           ( FIR_FILTER_0_AMBA_SLAVE_0_PSLVERR ),
        .FIR_FFT_RD_ENABLE ( DATAHANDLE_FSM_0_FIR_FFT_RD_ENABLE_0 ),
        .FIR_WR_ENABLE     ( DATAHANDLE_FSM_0_FIR_WR_ENABLE ),
        .WCLK              ( DATAHANDLE_FSM_0_WCLK ),
        .RCLK              ( DATAHANDLE_FSM_0_RCLK ),
        .SEL               ( DATAHANDLE_FSM_0_SEL ),
        .COEF_WR_EN        ( DATAHANDLE_FSM_0_COEF_WR_EN ),
        .PRDATA            ( FIR_FILTER_0_AMBA_SLAVE_0_PRDATA ),
        .FFT_RE_RADDR      ( DATAHANDLE_FSM_0_FFT_RE_RADDR ),
        .FIR_WADDR         ( DATAHANDLE_FSM_0_FIR_WADDR ),
        .FIR_RADDR         ( DATAHANDLE_FSM_0_FIR_RADDR ),
        .FFT_IM_RADDR      ( DATAHANDLE_FSM_0_FFT_IM_RADDR ),
        .COEF_WADDR        ( DATAHANDLE_FSM_0_COEF_WADDR ),
        .FIR_COEF_DATA_IN  ( DATAHANDLE_FSM_0_FIR_COEF_DATA_IN ) 
        );

//--------top_FFT_IM_Buffer_TPSRAM   -   Actel:SgCore:TPSRAM:1.0.102
top_FFT_IM_Buffer_TPSRAM FFT_IM_Buffer(
        // Inputs
        .WD    ( COREFFT_0_DATAO_IM ),
        .WADDR ( FILTERCONTROL_FSM_0_FFT_WADDR ),
        .RADDR ( DATAHANDLE_FSM_0_FFT_IM_RADDR ),
        .WEN   ( COREFFT_0_OUTP_READY ),
        .REN   ( DATAHANDLE_FSM_0_FIR_FFT_RD_ENABLE_0 ),
        .WCLK  ( FILTERCONTROL_FSM_0_WCLK ),
        .RCLK  ( DATAHANDLE_FSM_0_RCLK ),
        // Outputs
        .RD    ( FFT_IM_Buffer_RD ) 
        );

//--------top_FFT_RE_Buffer_TPSRAM   -   Actel:SgCore:TPSRAM:1.0.102
top_FFT_RE_Buffer_TPSRAM FFT_RE_Buffer(
        // Inputs
        .WD    ( COREFFT_0_DATAO_RE ),
        .WADDR ( FILTERCONTROL_FSM_0_FFT_WADDR ),
        .RADDR ( DATAHANDLE_FSM_0_FFT_RE_RADDR ),
        .WEN   ( COREFFT_0_OUTP_READY ),
        .REN   ( DATAHANDLE_FSM_0_FIR_FFT_RD_ENABLE_0 ),
        .WCLK  ( FILTERCONTROL_FSM_0_WCLK ),
        .RCLK  ( DATAHANDLE_FSM_0_RCLK ),
        // Outputs
        .RD    ( FFT_RE_Buffer_RD ) 
        );

//--------FILTERCONTROL_FSM
FILTERCONTROL_FSM FILTERCONTROL_FSM_0(
        // Inputs
        .PCLK            ( FIR_FILTER_0_FIC_0_CLK ),
        .PRESETN         ( FIR_FILTER_0_MSS_READY ),
        .FFT_START       ( COREFFT_0_OUTP_READY ),
        .SEL             ( DATAHANDLE_FSM_0_SEL ),
        // Outputs
        .FILTER_COMPLETE ( FILTERCONTROL_FSM_0_FILTER_COMPLETE ),
        .FIR_WR_ENABLE   ( FILTERCONTROL_FSM_0_FIR_WR_ENABLE ),
        .WCLK            ( FILTERCONTROL_FSM_0_WCLK ),
        .RCLK            ( FILTERCONTROL_FSM_0_RCLK ),
        .COEF_RD_ENABLE  ( FILTERCONTROL_FSM_0_COEF_RD_ENABLE ),
        .COEF_ON         ( FILTERCONTROL_FSM_0_COEF_ON ),
        .FIR_WR_ADDR     ( FILTERCONTROL_FSM_0_FIR_WR_ADDR ),
        .FFT_WADDR       ( FILTERCONTROL_FSM_0_FFT_WADDR ),
        .COEF_RADDR      ( FILTERCONTROL_FSM_0_COEF_RADDR ) 
        );

//--------FIR_FILTER
FIR_FILTER FIR_FILTER_0(
        // Inputs
        .MMUART_1_RXD           ( MMUART_1_RXD ),
        .FAB_RESET_N            ( VCC_net ),
        .AMBA_SLAVE_0_PREADYS0  ( FIR_FILTER_0_AMBA_SLAVE_0_PREADY ),
        .AMBA_SLAVE_0_PSLVERRS0 ( FIR_FILTER_0_AMBA_SLAVE_0_PSLVERR ),
        .DEVRST_N               ( DEVRST_N ),
        .AMBA_SLAVE_0_PRDATAS0  ( FIR_FILTER_0_AMBA_SLAVE_0_PRDATA_0 ),
        // Outputs
        .MMUART_1_TXD           ( MMUART_1_TXD_net_0 ),
        .POWER_ON_RESET_N       (  ),
        .INIT_DONE              (  ),
        .AMBA_SLAVE_0_PSELS0    ( FIR_FILTER_0_AMBA_SLAVE_0_PSELx ),
        .AMBA_SLAVE_0_PENABLES  ( FIR_FILTER_0_AMBA_SLAVE_0_PENABLE ),
        .AMBA_SLAVE_0_PWRITES   ( FIR_FILTER_0_AMBA_SLAVE_0_PWRITE ),
        .FIC_0_CLK              ( FIR_FILTER_0_FIC_0_CLK ),
        .FIC_0_LOCK             (  ),
        .MSS_READY              ( FIR_FILTER_0_MSS_READY ),
        .GPIO_0_M2F             ( FIR_FILTER_0_GPIO_0_M2F ),
        .GPIO_1_M2F             ( FIR_FILTER_0_GPIO_1_M2F ),
        .GPIO_2_M2F             ( FIR_FILTER_0_GPIO_2_M2F ),
        .AMBA_SLAVE_0_PADDRS    ( FIR_FILTER_0_AMBA_SLAVE_0_PADDR ),
        .AMBA_SLAVE_0_PWDATAS   ( FIR_FILTER_0_AMBA_SLAVE_0_PWDATA ) 
        );

//--------top_FIR_IN_Buffer_TPSRAM   -   Actel:SgCore:TPSRAM:1.0.102
top_FIR_IN_Buffer_TPSRAM FIR_IN_Buffer(
        // Inputs
        .WD    ( DATAHANDLE_FSM_0_FIR_COEF_DATA_IN ),
        .WADDR ( DATAHANDLE_FSM_0_FIR_WADDR ),
        .RADDR ( FILTERCONTROL_FSM_0_FIR_WR_ADDR ),
        .WEN   ( DATAHANDLE_FSM_0_FIR_WR_ENABLE ),
        .REN   ( FILTERCONTROL_FSM_0_FIR_WR_ENABLE ),
        .WCLK  ( DATAHANDLE_FSM_0_WCLK ),
        .RCLK  ( FILTERCONTROL_FSM_0_RCLK ),
        // Outputs
        .RD    ( FIR_IN_Buffer_RD ) 
        );

//--------top_FIR_OUT_Buffer_TPSRAM   -   Actel:SgCore:TPSRAM:1.0.102
top_FIR_OUT_Buffer_TPSRAM FIR_OUT_Buffer(
        // Inputs
        .WD    ( COREFIR_0_FIRO30to15 ),
        .WADDR ( FILTERCONTROL_FSM_0_FIR_WR_ADDR ),
        .RADDR ( DATAHANDLE_FSM_0_FIR_RADDR ),
        .WEN   ( FILTERCONTROL_FSM_0_FIR_WR_ENABLE ),
        .REN   ( DATAHANDLE_FSM_0_FIR_FFT_RD_ENABLE_0 ),
        .WCLK  ( FILTERCONTROL_FSM_0_RCLK ),
        .RCLK  ( DATAHANDLE_FSM_0_RCLK ),
        // Outputs
        .RD    ( FIR_OUT_Buffer_RD ) 
        );


endmodule
