Power Report for design top with the following settings:

Vendor: Microsemi Corporation
Program: Microsemi Libero Software, Release v12.6 (Version 12.900.20.24)
Copyright (C) 1989-
Date: Fri Mar 19 18:43:40 2021
Version: 3.0

Design: top
Family: SmartFusion2
Die: M2S090TS
Package: 484 FBGA
Temperature Range: COM
Voltage Range: COM
Operating Conditions: Typical
Operating Mode: Active
Process: Typical
Data Source: Production

Power Summary

Power (mW) Percentage
Total Power 422.707 100.0%
Static Power 238.719 56.5%
Dynamic Power 183.988 43.5%

Breakdown by Rail

Power (mW) Voltage (V) Current (mA)
Rail VDD 177.936 1.200 148.280
Rail VDDI 1.5 212.565 1.500 141.710
Rail VDDI 2.5 4.881 2.500 1.952
Rail CCC_NW1_PLL_VDDA 9.000 3.300 2.727
Rail MDDR_PLL_VDDA 5.000 3.300 1.515
Rail VPP 13.325 3.300 4.038

Breakdown by Clock

Power (mW) Percentage
EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (clocks) 147.719 96.0%
EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (register outputs) 0.071 0.0%
EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (primary inputs) 0.000 0.0%
EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (combinational outputs) 0.152 0.1%
EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (set/reset nets) 0.000 0.0%
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:DRAM_CLK (clocks) 0.000 0.0%
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:DRAM_CLK (register outputs) 0.000 0.0%
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:DRAM_CLK (primary inputs) 0.000 0.0%
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:DRAM_CLK (combinational outputs) 0.000 0.0%
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:DRAM_CLK (set/reset nets) 0.000 0.0%
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB (clocks) 0.614 0.4%
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB (register outputs) 0.189 0.1%
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB (primary inputs) 0.000 0.0%
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB (combinational outputs) 4.489 2.9%
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB (set/reset nets) 0.000 0.0%
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (clocks) 0.502 0.3%
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (register outputs) 0.039 0.0%
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (primary inputs) 0.000 0.0%
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (combinational outputs) 0.047 0.0%
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (set/reset nets) 0.000 0.0%
Input to Output 0.000 0.0%

Breakdown by Type

Power (mW) Percentage
Type Net 1.384 0.3%
Type Gate 11.303 2.7%
Type I/O 220.409 52.1%
Type Core Static 18.535 4.4%
Type Banks Static 3.332 0.8%
Type VPP Static 0.825 0.2%
Type Built-in Blocks 166.918 39.5%