Timing Multi Corner Report Max Delay Analysis

SmartTime Version 12.900.20.24

Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)

Date: Fri Mar 19 19:30:26 2021

Design top
Family SmartFusion2
Die M2S090TS
Package 484 FBGA
Temperature Range 0 - 85 C
Voltage Range 1.14 - 1.26 V
Speed Grade -1
Design State Post-Layout
Data source Production
Multi Corner Report Operating Conditions BEST, TYPICAL, WORST
Scenario for Timing Analysis timing_analysis

Summary

Clock Domain Required Period (ns) Required Frequency (MHz) Worst Slack (ns) Operating Conditions
EDAC_0/CCC_0/GL0 10.000 100.000 5.799 WORST
EDAC_0/EDAC_MSS_0/CLK_CONFIG_APB 36.036 27.750 1.754 BEST
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 20.000 50.000 8.951 WORST

Worst Slack (ns) Operating Conditions
Input to Output

Clock Domain EDAC_0/CCC_0/GL0

Info: The maximum frequency of this clock domain is limited by the period of pin EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 EDAC_0/CORERESETP_0/sm0_state[3]:CLK EDAC_0/CORERESETP_0/count_ddr_enable:EN 1.607 8.069 7.580 15.649 0.308 1.931 WORST
Path 2 EDAC_0/CORERESETP_0/sm0_state[4]:CLK EDAC_0/CORERESETP_0/count_ddr_enable:EN 1.555 8.109 7.540 15.649 0.308 1.891 WORST
Path 3 EDAC_0/CORERESETP_0/release_sdif3_core_clk_base:CLK EDAC_0/CORERESETP_0/sm0_state[5]:D 1.633 8.148 7.567 15.715 0.254 1.852 WORST
Path 4 EDAC_0/CORERESETP_0/release_sdif3_core_clk_base:CLK EDAC_0/CORERESETP_0/sm0_state[4]:D 1.551 8.229 7.485 15.714 0.254 1.771 WORST
Path 5 EDAC_0/CORERESETP_0/ddr_settled_clk_base:CLK EDAC_0/CORERESETP_0/count_ddr_enable:EN 1.467 8.246 7.403 15.649 0.308 1.754 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: EDAC_0/CORERESETP_0/sm0_state[3]:CLK
To: EDAC_0/CORERESETP_0/count_ddr_enable:EN
data required time 15.649
data arrival time - 7.580
slack 8.069
Data arrival time calculation
EDAC_0/CCC_0/GL0 0.000 0.000
EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 3.859 3.859
EDAC_0/CCC_0/GL0_INST:An net EDAC_0/CCC_0/GL0_net + 0.461 4.320 r
EDAC_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 4.498 7 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB0:An net EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.609 5.107 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB0:YR cell ADLIB:RGB + 0.316 5.423 20 r
EDAC_0/CORERESETP_0/sm0_state[3]:CLK net EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB0_rgbr_net_1 + 0.550 5.973 r
EDAC_0/CORERESETP_0/sm0_state[3]:Q cell ADLIB:SLE + 0.110 6.083 3 f
EDAC_0/CORERESETP_0/un1_next_ddr_ready_0_sqmuxa:D net EDAC_0/CORERESETP_0/sm0_state_Z[3] + 0.377 6.460 f
EDAC_0/CORERESETP_0/un1_next_ddr_ready_0_sqmuxa:Y cell ADLIB:CFG4 + 0.198 6.658 1 f
EDAC_0/CORERESETP_0/count_ddr_enable:EN net EDAC_0/CORERESETP_0/un1_next_ddr_ready_0_sqmuxa_Z + 0.922 7.580 f
data arrival time 7.580
Data required time calculation
EDAC_0/CCC_0/GL0 Clock Constraint 10.000 10.000
EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 10.000 r
Clock generation + 3.859 13.859
EDAC_0/CCC_0/GL0_INST:An net EDAC_0/CCC_0/GL0_net + 0.461 14.320 r
EDAC_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 14.498 7 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB0:An net EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.609 15.107 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB0:YR cell ADLIB:RGB + 0.316 15.423 20 r
EDAC_0/CORERESETP_0/count_ddr_enable:CLK net EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB0_rgbr_net_1 + 0.534 15.957 r
EDAC_0/CORERESETP_0/count_ddr_enable:EN Library setup time ADLIB:SLE - 0.308 15.649
data required time 15.649
Operating Conditions WORST

SET External Setup

No Path

SET Clock to Output

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Clock to Out (ns) Operating Conditions
Path 1 EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE MMUART_1_TXD 5.967 12.227 12.227 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE
To: MMUART_1_TXD
data required time N/C
data arrival time - 12.227
slack N/C
Data arrival time calculation
EDAC_0/CCC_0/GL0 0.000 0.000
EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 3.859 3.859
EDAC_0/CCC_0/GL0_INST:An net EDAC_0/CCC_0/GL0_net + 0.461 4.320 r
EDAC_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 4.498 7 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1:An net EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.620 5.118 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1:YR cell ADLIB:RGB + 0.316 5.434 1 r
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B net EDAC_0/CCC_0/GL0_INST/U0_RGB1_YR + 0.401 5.835 r
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB cell ADLIB:IP_INTERFACE + 0.209 6.044 1 r
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE net EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/CLK_BASE_net + 0.216 6.260 r
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT cell ADLIB:MSS_075_IP + 1.982 8.242 1 f
EDAC_0/EDAC_MSS_0/MMUART_1_TXD_PAD/U_IOPAD:D net EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT + 1.319 9.561 f
EDAC_0/EDAC_MSS_0/MMUART_1_TXD_PAD/U_IOPAD:PAD cell ADLIB:IOPAD_TRI + 2.666 12.227 0 f
MMUART_1_TXD net MMUART_1_TXD + 0.000 12.227 f
data arrival time 12.227
Data required time calculation
EDAC_0/CCC_0/GL0 N/C N/C
EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 N/C r
Clock generation + 3.859 N/C
MMUART_1_TXD N/C f
Operating Conditions WORST

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:CLK EDAC_0/CORERESETP_0/sm0_areset_n_q1:ALn 3.811 5.799 9.765 15.564 0.353 4.201 0.037 WORST
Path 2 EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:CLK EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:ALn 3.811 5.799 9.765 15.564 0.353 4.201 0.037 WORST
Path 3 EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:CLK EDAC_0/CORERESETP_0/release_sdif3_core_q1:ALn 3.689 5.936 9.621 15.557 0.353 4.064 0.022 WORST
Path 4 EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:CLK EDAC_0/CORERESETP_0/CONFIG1_DONE_q1:ALn 3.689 5.936 9.621 15.557 0.353 4.064 0.022 WORST
Path 5 EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:CLK EDAC_0/CORERESETP_0/CONFIG1_DONE_clk_base:ALn 3.689 5.945 9.621 15.566 0.353 4.055 0.013 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:CLK
To: EDAC_0/CORERESETP_0/sm0_areset_n_q1:ALn
data required time 15.564
data arrival time - 9.765
slack 5.799
Data arrival time calculation
EDAC_0/CCC_0/GL0 0.000 0.000
EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 3.859 3.859
EDAC_0/CCC_0/GL0_INST:An net EDAC_0/CCC_0/GL0_net + 0.461 4.320 r
EDAC_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 4.498 7 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB4:An net EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.631 5.129 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB4:YL cell ADLIB:RGB + 0.317 5.446 5 r
EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:CLK net EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB4_rgbl_net_1 + 0.508 5.954 r
EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:Q cell ADLIB:SLE + 0.087 6.041 1 r
EDAC_0/CORERESETP_0/sdif0_areset_n:A net EDAC_0/CORERESETP_0/MSS_HPMS_READY_int_Z + 0.313 6.354 r
EDAC_0/CORERESETP_0/sdif0_areset_n:Y cell ADLIB:CFG2 + 0.074 6.428 1 r
EDAC_0/CORERESETP_0/sdif0_areset_n_RNI934D:An net EDAC_0/CORERESETP_0/sm0_areset_n + 1.517 7.945 f
EDAC_0/CORERESETP_0/sdif0_areset_n_RNI934D:YEn cell ADLIB:GBM + 0.374 8.319 2 f
EDAC_0/CORERESETP_0/sdif0_areset_n_RNI934D/U0_RGB1_RGB0:An net EDAC_0/CORERESETP_0/sdif0_areset_n_RNI934D/U0_YWn_GEast + 0.617 8.936 f
EDAC_0/CORERESETP_0/sdif0_areset_n_RNI934D/U0_RGB1_RGB0:YL cell ADLIB:RGB + 0.317 9.253 2 r
EDAC_0/CORERESETP_0/sm0_areset_n_q1:ALn net EDAC_0/CORERESETP_0/sdif0_areset_n_RNI934D/U0_RGB1_RGB0_rgbl_net_1 + 0.512 9.765 r
data arrival time 9.765
Data required time calculation
EDAC_0/CCC_0/GL0 Clock Constraint 10.000 10.000
EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 10.000 r
Clock generation + 3.859 13.859
EDAC_0/CCC_0/GL0_INST:An net EDAC_0/CCC_0/GL0_net + 0.461 14.320 r
EDAC_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 14.498 7 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3:An net EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.622 15.120 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3:YL cell ADLIB:RGB + 0.317 15.437 2 r
EDAC_0/CORERESETP_0/sm0_areset_n_q1:CLK net EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3_rgbl_net_1 + 0.480 15.917 r
EDAC_0/CORERESETP_0/sm0_areset_n_q1:ALn Library recovery time ADLIB:SLE - 0.353 15.564
data required time 15.564
Operating Conditions WORST

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET EDAC_0/EDAC_MSS_0/CLK_CONFIG_APB to EDAC_0/CCC_0/GL0

No Path

SET EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT to EDAC_0/CCC_0/GL0

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Operating Conditions
Path 1 EDAC_0/CORERESETP_0/ddr_settled:CLK EDAC_0/CORERESETP_0/ddr_settled_q1:D 0.809 6.185 9.474 15.659 0.254 WORST
Path 2 EDAC_0/CORERESETP_0/release_sdif0_core:CLK EDAC_0/CORERESETP_0/release_sdif0_core_q1:D 0.622 6.381 9.278 15.659 0.254 WORST
Path 3 EDAC_0/CORERESETP_0/release_sdif3_core:CLK EDAC_0/CORERESETP_0/release_sdif3_core_q1:D 0.608 6.393 9.263 15.656 0.254 WORST
Path 4 EDAC_0/CORERESETP_0/release_sdif1_core:CLK EDAC_0/CORERESETP_0/release_sdif1_core_q1:D 0.601 6.454 9.230 15.684 0.254 WORST
Path 5 EDAC_0/CORERESETP_0/release_sdif2_core:CLK EDAC_0/CORERESETP_0/release_sdif2_core_q1:D 0.587 6.459 9.216 15.675 0.254 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: EDAC_0/CORERESETP_0/ddr_settled:CLK
To: EDAC_0/CORERESETP_0/ddr_settled_q1:D
data required time 15.659
data arrival time - 9.474
slack 6.185
Data arrival time calculation
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 0.000 0.000
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 0.000 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 3.101 3.101 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 3.253 1 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 3.578 6.831 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.374 7.205 2 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An net EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.600 7.805 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YR cell ADLIB:RGB + 0.316 8.121 29 r
EDAC_0/CORERESETP_0/ddr_settled:CLK net EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbr_net_1 + 0.544 8.665 r
EDAC_0/CORERESETP_0/ddr_settled:Q cell ADLIB:SLE + 0.087 8.752 1 r
EDAC_0/CORERESETP_0/ddr_settled_q1:D net EDAC_0/CORERESETP_0/ddr_settled_Z + 0.722 9.474 r
data arrival time 9.474
Data required time calculation
EDAC_0/CCC_0/GL0 Clock Constraint 10.000 10.000
EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 10.000 r
Clock generation + 3.859 13.859
EDAC_0/CCC_0/GL0_INST:An net EDAC_0/CCC_0/GL0_net + 0.461 14.320 r
EDAC_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 14.498 7 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB0:An net EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.609 15.107 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB0:YR cell ADLIB:RGB + 0.316 15.423 20 r
EDAC_0/CORERESETP_0/ddr_settled_q1:CLK net EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB0_rgbr_net_1 + 0.490 15.913 r
EDAC_0/CORERESETP_0/ddr_settled_q1:D Library setup time ADLIB:SLE - 0.254 15.659
data required time 15.659
Operating Conditions WORST

Clock Domain EDAC_0/EDAC_MSS_0/CLK_CONFIG_APB

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN 1.788 1.754 1.788 3.542 0.245 -1.754 BEST
Path 2 EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB EDAC_0/CORECONFIGP_0/state[0]:D 1.307 2.257 1.307 3.564 0.201 -2.257 BEST
Path 3 EDAC_0/CORECONFIGP_0/psel:CLK EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[0]:D 2.761 14.817 8.410 23.227 0.254 6.402 WORST
Path 4 EDAC_0/CORECONFIGP_0/psel:CLK EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN 2.445 15.104 8.094 23.198 0.308 5.828 WORST
Path 5 EDAC_0/CORECONFIGP_0/psel:CLK EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PSEL 2.254 15.295 7.903 23.198 0.602 5.446 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB
To: EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN
data required time 3.542
data arrival time - 1.788
slack 1.754
Data arrival time calculation
EDAC_0/EDAC_MSS_0/CLK_CONFIG_APB 0.000 0.000
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB Clock source + 0.000 0.000 r
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PENABLE cell ADLIB:MSS_075_IP + 0.587 0.587 2 r
EDAC_0/CORECONFIGP_0/next_state4:A net EDAC_0/EDAC_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE + 0.481 1.068 r
EDAC_0/CORECONFIGP_0/next_state4:Y cell ADLIB:CFG2 + 0.098 1.166 2 f
EDAC_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_0:C net EDAC_0/CORECONFIGP_0/next_state4_Z + 0.069 1.235 f
EDAC_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_0:Y cell ADLIB:CFG4 + 0.060 1.295 1 f
EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN net EDAC_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_0_Z + 0.493 1.788 f
data arrival time 1.788
Data required time calculation
EDAC_0/EDAC_MSS_0/CLK_CONFIG_APB Max Delay Constraint 0.000 0.000
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB Clock source + 0.000 0.000 r
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6:An net EDAC_0/EDAC_MSS_0/CLK_CONFIG_APB + 2.532 2.532 f
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6:YEn cell ADLIB:GBM + 0.257 2.789 7 f
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6/U0_RGB1_RGB2:An net EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6/U0_YWn_GEast + 0.414 3.203 f
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6/U0_RGB1_RGB2:YR cell ADLIB:RGB + 0.218 3.421 18 r
EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:CLK net EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6/U0_RGB1_RGB2_rgbr_net_1 + 0.366 3.787 r
EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN Library setup time ADLIB:SLE - 0.245 3.542
data required time 3.542
Operating Conditions BEST

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET EDAC_0/CCC_0/GL0 to EDAC_0/EDAC_MSS_0/CLK_CONFIG_APB

No Path

Clock Domain EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 EDAC_0/CORERESETP_0/count_ddr[2]:CLK EDAC_0/CORERESETP_0/ddr_settled:EN 2.244 17.448 10.893 28.341 0.308 2.552 WORST
Path 2 EDAC_0/CORERESETP_0/count_ddr[9]:CLK EDAC_0/CORERESETP_0/ddr_settled:EN 2.164 17.513 10.828 28.341 0.308 2.487 WORST
Path 3 EDAC_0/CORERESETP_0/count_ddr[13]:CLK EDAC_0/CORERESETP_0/ddr_settled:EN 2.155 17.521 10.820 28.341 0.308 2.479 WORST
Path 4 EDAC_0/CORERESETP_0/count_ddr[5]:CLK EDAC_0/CORERESETP_0/ddr_settled:EN 2.039 17.645 10.696 28.341 0.308 2.355 WORST
Path 5 EDAC_0/CORERESETP_0/count_ddr[8]:CLK EDAC_0/CORERESETP_0/ddr_settled:EN 1.989 17.697 10.644 28.341 0.308 2.303 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: EDAC_0/CORERESETP_0/count_ddr[2]:CLK
To: EDAC_0/CORERESETP_0/ddr_settled:EN
data required time 28.341
data arrival time - 10.893
slack 17.448
Data arrival time calculation
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 0.000 0.000
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 0.000 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 3.101 3.101 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 3.253 1 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 3.578 6.831 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.374 7.205 2 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An net EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.600 7.805 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YR cell ADLIB:RGB + 0.316 8.121 29 r
EDAC_0/CORERESETP_0/count_ddr[2]:CLK net EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbr_net_1 + 0.528 8.649 r
EDAC_0/CORERESETP_0/count_ddr[2]:Q cell ADLIB:SLE + 0.087 8.736 2 r
EDAC_0/CORERESETP_0/ddr_settled4_8:C net EDAC_0/CORERESETP_0/count_ddr_Z[2] + 0.440 9.176 r
EDAC_0/CORERESETP_0/ddr_settled4_8:Y cell ADLIB:CFG4 + 0.326 9.502 1 f
EDAC_0/CORERESETP_0/ddr_settled4:C net EDAC_0/CORERESETP_0/ddr_settled4_8_Z + 0.423 9.925 f
EDAC_0/CORERESETP_0/ddr_settled4:Y cell ADLIB:CFG4 + 0.209 10.134 1 f
EDAC_0/CORERESETP_0/ddr_settled:EN net EDAC_0/CORERESETP_0/ddr_settled4_Z + 0.759 10.893 f
data arrival time 10.893
Data required time calculation
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Clock Constraint 20.000 20.000
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 20.000 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 3.101 23.101 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 23.253 1 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 3.578 26.831 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.374 27.205 2 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An net EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.600 27.805 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YR cell ADLIB:RGB + 0.316 28.121 29 r
EDAC_0/CORERESETP_0/ddr_settled:CLK net EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbr_net_1 + 0.528 28.649 r
EDAC_0/CORERESETP_0/ddr_settled:EN Library setup time ADLIB:SLE - 0.308 28.341
data required time 28.341
Operating Conditions WORST

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK EDAC_0/CORERESETP_0/count_ddr_enable_q1:ALn 5.391 14.239 14.047 28.286 0.353 5.761 0.017 WORST
Path 2 EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK EDAC_0/CORERESETP_0/count_ddr[8]:ALn 5.391 14.239 14.047 28.286 0.353 5.761 0.017 WORST
Path 3 EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK EDAC_0/CORERESETP_0/count_ddr[12]:ALn 5.391 14.239 14.047 28.286 0.353 5.761 0.017 WORST
Path 4 EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK EDAC_0/CORERESETP_0/count_ddr[10]:ALn 5.391 14.239 14.047 28.286 0.353 5.761 0.017 WORST
Path 5 EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK EDAC_0/CORERESETP_0/count_ddr[2]:ALn 5.378 14.246 14.034 28.280 0.353 5.754 0.023 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK
To: EDAC_0/CORERESETP_0/count_ddr_enable_q1:ALn
data required time 28.286
data arrival time - 14.047
slack 14.239
Data arrival time calculation
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 0.000 0.000
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 0.000 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 3.101 3.101 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 3.253 1 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 3.578 6.831 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.374 7.205 2 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An net EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.600 7.805 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YR cell ADLIB:RGB + 0.316 8.121 29 r
EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK net EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbr_net_1 + 0.535 8.656 r
EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:Q cell ADLIB:SLE + 0.087 8.743 1 r
EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683:An net EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_0 + 3.453 12.196 f
EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683:YEn cell ADLIB:GBM + 0.374 12.570 1 f
EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683/U0_RGB1:An net EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683/U0_YWn_GEast + 0.605 13.175 f
EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683/U0_RGB1:YR cell ADLIB:RGB + 0.316 13.491 17 r
EDAC_0/CORERESETP_0/count_ddr_enable_q1:ALn net EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683/U0_RGB1_YR + 0.556 14.047 r
data arrival time 14.047
Data required time calculation
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Clock Constraint 20.000 20.000
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 20.000 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 3.101 23.101 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 23.253 1 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 3.578 26.831 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.374 27.205 2 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An net EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.600 27.805 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YR cell ADLIB:RGB + 0.316 28.121 29 r
EDAC_0/CORERESETP_0/count_ddr_enable_q1:CLK net EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbr_net_1 + 0.518 28.639 r
EDAC_0/CORERESETP_0/count_ddr_enable_q1:ALn Library recovery time ADLIB:SLE - 0.353 28.286
data required time 28.286
Operating Conditions WORST

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET EDAC_0/CCC_0/GL0 to EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Operating Conditions
Path 1 EDAC_0/CORERESETP_0/count_ddr_enable:CLK EDAC_0/CORERESETP_0/count_ddr_enable_q1:D 3.461 8.951 9.434 18.385 0.254 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: EDAC_0/CORERESETP_0/count_ddr_enable:CLK
To: EDAC_0/CORERESETP_0/count_ddr_enable_q1:D
data required time 18.385
data arrival time - 9.434
slack 8.951
Data arrival time calculation
EDAC_0/CCC_0/GL0 0.000 0.000
EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 3.859 3.859
EDAC_0/CCC_0/GL0_INST:An net EDAC_0/CCC_0/GL0_net + 0.461 4.320 r
EDAC_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 4.498 7 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB0:An net EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.609 5.107 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB0:YR cell ADLIB:RGB + 0.316 5.423 20 r
EDAC_0/CORERESETP_0/count_ddr_enable:CLK net EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB0_rgbr_net_1 + 0.550 5.973 r
EDAC_0/CORERESETP_0/count_ddr_enable:Q cell ADLIB:SLE + 0.092 6.065 1 r
mdr_EDAC_0/CORERESETP_0/count_ddr_enable_q1_CFG1C_TEST:A net EDAC_0/CORERESETP_0/count_ddr_enable_Z + 0.564 6.629 r
mdr_EDAC_0/CORERESETP_0/count_ddr_enable_q1_CFG1C_TEST:Y cell ADLIB:CFG1C_TEST + 0.202 6.831 1 r
mdr_EDAC_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST1:A net mdr_EDAC_0/CORERESETP_0/count_ddr_enable_q1_CFG1C_TEST_net + 0.193 7.024 r
mdr_EDAC_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST1:Y cell ADLIB:CFG1D_TEST + 0.345 7.369 1 r
mdr_EDAC_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST0:A net mdr_EDAC_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST_net1 + 0.309 7.678 r
mdr_EDAC_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST0:Y cell ADLIB:CFG1D_TEST + 0.345 8.023 1 r
mdr_EDAC_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST:A net mdr_EDAC_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST_net0 + 0.194 8.217 r
mdr_EDAC_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST:Y cell ADLIB:CFG1D_TEST + 0.345 8.562 1 r
EDAC_0/CORERESETP_0/count_ddr_enable_q1:D net mdr_EDAC_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST_net + 0.872 9.434 r
data arrival time 9.434
Data required time calculation
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Clock Constraint 10.000 10.000
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 10.000 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 3.101 13.101 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 13.253 1 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 3.578 16.831 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.374 17.205 2 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An net EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.600 17.805 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YR cell ADLIB:RGB + 0.316 18.121 29 r
EDAC_0/CORERESETP_0/count_ddr_enable_q1:CLK net EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbr_net_1 + 0.518 18.639 r
EDAC_0/CORERESETP_0/count_ddr_enable_q1:D Library setup time ADLIB:SLE - 0.254 18.385
data required time 18.385
Operating Conditions WORST

Path Set Pin to Pin

SET Input to Output

No Path

Path Set User Sets