Project Settings
Project Name top_syn Device Name synthesis: Microchip SmartFusion2 : M2S090TS
Implementation Name synthesis Top Module top
Retiming 0 Resource Sharing 1
Fanout Guide 10000 Disable I/O Insertion 0
Disable Sequential Optimizations 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 52 36 0 - 00m:06s - 19-03-2021
19:27:42
(premap)Complete 37 19 0 0m:01s 0m:01s 170MB 19-03-2021
19:27:46
(fpga_mapper)Complete 39 21 0 0m:04s 0m:04s 172MB 19-03-2021
19:27:51
Multi-srs Generator Complete19-03-2021
19:27:43

Area Summary
Carry Cells 14 Sequential Cells 141
DSP Blocks (dsp_used) 0 I/O Cells 59
Global Clock Buffers 7 LUTs (total_luts) 79

Timing Summary
Clock NameReq FreqEst FreqSlack
EDAC_0/CCC_0/GL0100.0 MHz522.4 MHz8.086
EDAC_0/EDAC_MSS_0/CLK_CONFIG_APB27.8 MHz127.4 MHz14.094
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT50.0 MHz502.7 MHz18.011

Optimizations Summary
Combined Clock Conversion 2 / 1