@W: MO160 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\v12.5_igloo2\v12.6_updates\sf2\dg0388\dg0388_sf2_esram0_edac_demo\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":255:4:255:9|Register bit CORECONFIGP_0.paddr[16] (in view view:work.EDAC(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\v12.5_igloo2\v12.6_updates\sf2\dg0388\dg0388_sf2_esram0_edac_demo\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[31] (in view view:work.EDAC(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\v12.5_igloo2\v12.6_updates\sf2\dg0388\dg0388_sf2_esram0_edac_demo\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[30] (in view view:work.EDAC(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\v12.5_igloo2\v12.6_updates\sf2\dg0388\dg0388_sf2_esram0_edac_demo\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[29] (in view view:work.EDAC(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\v12.5_igloo2\v12.6_updates\sf2\dg0388\dg0388_sf2_esram0_edac_demo\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[28] (in view view:work.EDAC(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\v12.5_igloo2\v12.6_updates\sf2\dg0388\dg0388_sf2_esram0_edac_demo\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[27] (in view view:work.EDAC(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\v12.5_igloo2\v12.6_updates\sf2\dg0388\dg0388_sf2_esram0_edac_demo\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[26] (in view view:work.EDAC(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\v12.5_igloo2\v12.6_updates\sf2\dg0388\dg0388_sf2_esram0_edac_demo\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[25] (in view view:work.EDAC(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\v12.5_igloo2\v12.6_updates\sf2\dg0388\dg0388_sf2_esram0_edac_demo\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[24] (in view view:work.EDAC(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\v12.5_igloo2\v12.6_updates\sf2\dg0388\dg0388_sf2_esram0_edac_demo\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[23] (in view view:work.EDAC(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\v12.5_igloo2\v12.6_updates\sf2\dg0388\dg0388_sf2_esram0_edac_demo\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[22] (in view view:work.EDAC(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\v12.5_igloo2\v12.6_updates\sf2\dg0388\dg0388_sf2_esram0_edac_demo\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[21] (in view view:work.EDAC(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\v12.5_igloo2\v12.6_updates\sf2\dg0388\dg0388_sf2_esram0_edac_demo\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[20] (in view view:work.EDAC(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\v12.5_igloo2\v12.6_updates\sf2\dg0388\dg0388_sf2_esram0_edac_demo\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Register bit CORECONFIGP_0.FIC_2_APB_M_PRDATA[19] (in view view:work.EDAC(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\v12.5_igloo2\v12.6_updates\sf2\dg0388\dg0388_sf2_esram0_edac_demo\libero_project\component\actel\directcore\coreconfigp\7.1.100\rtl\vlog\core\coreconfigp.v":546:4:546:9|Removing instance EDAC_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[18] because it is equivalent to instance EDAC_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[17]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MT246 :"c:\wfh_tasks\igloo2_sf2_v12.6_qr\v12.5_igloo2\v12.6_updates\sf2\dg0388\dg0388_sf2_esram0_edac_demo\libero_project\component\work\edac\ccc_0\edac_ccc_0_fccc.v":20:36:20:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT447 :"c:/wfh_tasks/igloo2_sf2_v12.6_qr/v12.5_igloo2/v12.6_updates/sf2/dg0388/dg0388_sf2_esram0_edac_demo/libero_project/designer/top/synthesis.fdc":12:0:12:0|Timing constraint (from [get_cells { EDAC_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { EDAC_0.CORERESETP_0.sm0_areset_n_rcosc EDAC_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"c:/wfh_tasks/igloo2_sf2_v12.6_qr/v12.5_igloo2/v12.6_updates/sf2/dg0388/dg0388_sf2_esram0_edac_demo/libero_project/designer/top/synthesis.fdc":13:0:13:0|Timing constraint (from [get_cells { EDAC_0.CORERESETP_0.MSS_HPMS_READY_int EDAC_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { EDAC_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"c:/wfh_tasks/igloo2_sf2_v12.6_qr/v12.5_igloo2/v12.6_updates/sf2/dg0388/dg0388_sf2_esram0_edac_demo/libero_project/designer/top/synthesis.fdc":15:0:15:0|Timing constraint (through [get_pins { EDAC_0.EDAC_MSS_0.MSS_ADLIB_INST.CONFIG_PRESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"c:/wfh_tasks/igloo2_sf2_v12.6_qr/v12.5_igloo2/v12.6_updates/sf2/dg0388/dg0388_sf2_esram0_edac_demo/libero_project/designer/top/synthesis.fdc":16:0:16:0|Timing constraint (through [get_pins { EDAC_0.SYSRESET_POR.POWER_ON_RESET_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT443 :"c:/wfh_tasks/igloo2_sf2_v12.6_qr/v12.5_igloo2/v12.6_updates/sf2/dg0388/dg0388_sf2_esram0_edac_demo/libero_project/designer/top/synthesis.fdc":17:0:17:0|Timing constraint (through [get_nets { EDAC_0.CORECONFIGP_0.FIC_2_APB_M_PSEL EDAC_0.CORECONFIGP_0.FIC_2_APB_M_PENABLE }] to [get_cells { EDAC_0.CORECONFIGP_0.FIC_2_APB_M_PREADY* EDAC_0.CORECONFIGP_0.state[0] }]) (max delay 0.000000) was not applied to the design because none of the paths specified by the constraint exist in the design 
