SmartTime Version 12.900.20.24
Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)
Date: Fri Mar 19 16:36:00 2021
| Design | top |
| Family | SmartFusion2 |
| Die | M2S090TS |
| Package | 484 FBGA |
| Temperature Range | 0 - 85 C |
| Voltage Range | 1.14 - 1.26 V |
| Speed Grade | -1 |
| Design State | Post-Layout |
| Data source | Production |
| Min Operating Conditions | WORST - 1.14 V - 85 C |
| Max Operating Conditions | BEST - 1.26 V - 0 C |
| Scenario for Timing Analysis | timing_analysis |
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | |
|---|---|---|---|---|---|---|
| Path 1 | EDAC_0/CORERESETP_0/count_ddr_enable:CLK | EDAC_0/CORERESETP_0/count_ddr_enable_q1:D | 0.579 | -2.025 | 6.370 | 8.395 |
| Path 2 | EDAC_0/CORECONFIGP_0/pwdata[8]:CLK | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[8] | 1.367 | -0.649 | 6.699 | 7.348 |
| Path 3 | EDAC_0/CORECONFIGP_0/pwdata[7]:CLK | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[7] | 1.382 | -0.628 | 6.697 | 7.325 |
| Path 4 | EDAC_0/CORECONFIGP_0/pwdata[12]:CLK | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[12] | 1.375 | -0.626 | 6.700 | 7.326 |
| Path 5 | EDAC_0/CORECONFIGP_0/paddr[4]:CLK | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PADDR[4] | 1.380 | -0.606 | 6.692 | 7.298 |
| Path 6 | EDAC_0/CORECONFIGP_0/paddr[6]:CLK | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PADDR[6] | 1.474 | -0.601 | 6.792 | 7.393 |
| Path 7 | EDAC_0/CORECONFIGP_0/pwdata[11]:CLK | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[11] | 1.512 | -0.482 | 6.829 | 7.311 |
| Path 8 | EDAC_0/CORECONFIGP_0/paddr[5]:CLK | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PADDR[5] | 1.502 | -0.474 | 6.820 | 7.294 |
| Path 9 | EDAC_0/CORECONFIGP_0/pwdata[5]:CLK | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[5] | 1.345 | -0.468 | 6.677 | 7.145 |
| Path 10 | EDAC_0/CORECONFIGP_0/pwdata[0]:CLK | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[0] | 1.535 | -0.466 | 6.858 | 7.324 |
| Path 11 | EDAC_0/CORECONFIGP_0/paddr[7]:CLK | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PADDR[7] | 1.481 | -0.434 | 6.799 | 7.233 |
| Path 12 | EDAC_0/CORECONFIGP_0/pwdata[2]:CLK | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[2] | 1.505 | -0.429 | 6.827 | 7.256 |
| Path 13 | EDAC_0/CORECONFIGP_0/pwdata[4]:CLK | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[4] | 1.496 | -0.398 | 6.821 | 7.219 |
| Path 14 | EDAC_0/CORECONFIGP_0/pwdata[15]:CLK | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[15] | 1.489 | -0.362 | 6.811 | 7.173 |
| Path 15 | EDAC_0/CORECONFIGP_0/pwdata[3]:CLK | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[3] | 1.504 | -0.354 | 6.833 | 7.187 |
| Path 16 | EDAC_0/CORECONFIGP_0/pwdata[1]:CLK | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[1] | 1.477 | -0.351 | 6.809 | 7.160 |
| Path 17 | EDAC_0/CORECONFIGP_0/pwdata[6]:CLK | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[6] | 1.597 | -0.348 | 6.926 | 7.274 |
| Path 18 | EDAC_0/CORECONFIGP_0/paddr[3]:CLK | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PADDR[3] | 1.727 | -0.295 | 7.051 | 7.346 |
| Path 19 | EDAC_0/CORECONFIGP_0/pwrite:CLK | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWRITE | 1.340 | -0.285 | 6.664 | 6.949 |
| Path 20 | EDAC_0/CORECONFIGP_0/pwdata[9]:CLK | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[9] | 1.507 | -0.281 | 6.822 | 7.103 |