SmartTime Version 12.900.20.24
Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)
Date: Fri Mar 19 16:36:01 2021
| Design | top |
| Family | SmartFusion2 |
| Die | M2S090TS |
| Package | 484 FBGA |
| Temperature Range | 0 - 85 C |
| Voltage Range | 1.14 - 1.26 V |
| Speed Grade | -1 |
| Design State | Post-Layout |
| Data source | Production |
| Multi Corner Report Operating Conditions | BEST, TYPICAL, WORST |
| Scenario for Timing Analysis | timing_analysis |
| Clock Domain | Required Period (ns) | Required Frequency (MHz) | Worst Slack (ns) | Operating Conditions |
|---|---|---|---|---|
| EDAC_0/CCC_0/GL0 | 10.000 | 100.000 | 0.300 | BEST |
| EDAC_0/EDAC_MSS_0/CLK_CONFIG_APB | 36.036 | 27.750 | -0.649 | WORST |
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 20.000 | 50.000 | -2.025 | WORST |
| Worst Slack (ns) | Operating Conditions | |
|---|---|---|
| Input to Output |
Info: The maximum frequency of this clock domain is limited by the period of pin EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Hold (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|
| Path 1 | EDAC_0/CORERESETP_0/sm0_state[0]:CLK | EDAC_0/CORERESETP_0/sm0_state[1]:D | 0.319 | 0.300 | 4.304 | 4.004 | 0.000 | BEST |
| Path 2 | EDAC_0/CORERESETP_0/RESET_N_M2F_q1:CLK | EDAC_0/CORERESETP_0/RESET_N_M2F_clk_base:D | 0.319 | 0.302 | 4.285 | 3.983 | 0.000 | BEST |
| Path 3 | EDAC_0/CORERESETP_0/CONFIG1_DONE_q1:CLK | EDAC_0/CORERESETP_0/CONFIG1_DONE_clk_base:D | 0.322 | 0.302 | 4.312 | 4.010 | 0.000 | BEST |
| Path 4 | EDAC_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_q1:CLK | EDAC_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_clk_base:D | 0.319 | 0.303 | 4.288 | 3.985 | 0.000 | BEST |
| Path 5 | EDAC_0/CORERESETP_0/sm0_areset_n_q1:CLK | EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:D | 0.320 | 0.304 | 4.290 | 3.986 | 0.000 | BEST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: EDAC_0/CORERESETP_0/sm0_state[0]:CLK | ||||||||
| To: EDAC_0/CORERESETP_0/sm0_state[1]:D | ||||||||
| data arrival time | 4.304 | |||||||
| data required time | - | 4.004 | ||||||
| slack | 0.300 | |||||||
| Data arrival time calculation | ||||||||
| EDAC_0/CCC_0/GL0 | 0.000 | 0.000 | ||||||
| EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 2.587 | 2.587 | |||||
| EDAC_0/CCC_0/GL0_INST:An | net | EDAC_0/CCC_0/GL0_net | + | 0.309 | 2.896 | r | ||
| EDAC_0/CCC_0/GL0_INST:YEn | cell | ADLIB:GBM | + | 0.118 | 3.014 | 6 | f | |
| EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3:An | net | EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast | + | 0.401 | 3.415 | f | ||
| EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3:YR | cell | ADLIB:RGB | + | 0.212 | 3.627 | 12 | r | |
| EDAC_0/CORERESETP_0/sm0_state[0]:CLK | net | EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3_rgbr_net_1 | + | 0.358 | 3.985 | r | ||
| EDAC_0/CORERESETP_0/sm0_state[0]:Q | cell | ADLIB:SLE | + | 0.058 | 4.043 | 1 | r | |
| EDAC_0/CORERESETP_0/sm0_state[1]:D | net | EDAC_0/CORERESETP_0/sm0_state_Z[0] | + | 0.261 | 4.304 | r | ||
| data arrival time | 4.304 | |||||||
| Data required time calculation | ||||||||
| EDAC_0/CCC_0/GL0 | Clock Constraint | 0.000 | 0.000 | |||||
| EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 2.587 | 2.587 | |||||
| EDAC_0/CCC_0/GL0_INST:An | net | EDAC_0/CCC_0/GL0_net | + | 0.309 | 2.896 | r | ||
| EDAC_0/CCC_0/GL0_INST:YEn | cell | ADLIB:GBM | + | 0.118 | 3.014 | 6 | f | |
| EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3:An | net | EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast | + | 0.401 | 3.415 | f | ||
| EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3:YR | cell | ADLIB:RGB | + | 0.212 | 3.627 | 12 | r | |
| EDAC_0/CORERESETP_0/sm0_state[1]:CLK | net | EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3_rgbr_net_1 | + | 0.377 | 4.004 | r | ||
| EDAC_0/CORERESETP_0/sm0_state[1]:D | Library hold time | ADLIB:SLE | + | 0.000 | 4.004 | |||
| data required time | 4.004 | |||||||
| Operating Conditions | BEST |
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Clock to Out (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|
| Path 1 | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE | MMUART_1_TXD | 3.769 | 7.964 | 7.964 | BEST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE | ||||||||
| To: MMUART_1_TXD | ||||||||
| data arrival time | 7.964 | |||||||
| data required time | - | N/C | ||||||
| slack | N/C | |||||||
| Data arrival time calculation | ||||||||
| EDAC_0/CCC_0/GL0 | 0.000 | 0.000 | ||||||
| EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 2.587 | 2.587 | |||||
| EDAC_0/CCC_0/GL0_INST:An | net | EDAC_0/CCC_0/GL0_net | + | 0.309 | 2.896 | r | ||
| EDAC_0/CCC_0/GL0_INST:YEn | cell | ADLIB:GBM | + | 0.118 | 3.014 | 6 | f | |
| EDAC_0/CCC_0/GL0_INST/U0_RGB1:An | net | EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast | + | 0.413 | 3.427 | f | ||
| EDAC_0/CCC_0/GL0_INST/U0_RGB1:YR | cell | ADLIB:RGB | + | 0.212 | 3.639 | 1 | r | |
| EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B | net | EDAC_0/CCC_0/GL0_INST/U0_RGB1_YR | + | 0.271 | 3.910 | r | ||
| EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB | cell | ADLIB:IP_INTERFACE | + | 0.140 | 4.050 | 1 | r | |
| EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE | net | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/CLK_BASE_net | + | 0.145 | 4.195 | r | ||
| EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT | cell | ADLIB:MSS_075_IP | + | 1.289 | 5.484 | 1 | r | |
| EDAC_0/EDAC_MSS_0/MMUART_1_TXD_PAD/U_IOPAD:D | net | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT | + | 0.881 | 6.365 | r | ||
| EDAC_0/EDAC_MSS_0/MMUART_1_TXD_PAD/U_IOPAD:PAD | cell | ADLIB:IOPAD_TRI | + | 1.599 | 7.964 | 0 | r | |
| MMUART_1_TXD | net | MMUART_1_TXD | + | 0.000 | 7.964 | r | ||
| data arrival time | 7.964 | |||||||
| Data required time calculation | ||||||||
| EDAC_0/CCC_0/GL0 | N/C | N/C | ||||||
| EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | N/C | r | |||
| Clock generation | + | 2.587 | N/C | |||||
| MMUART_1_TXD | N/C | r | ||||||
| Operating Conditions | BEST |
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Removal (ns) | Skew (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | EDAC_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK | EDAC_0/CORERESETP_0/mss_ready_select:ALn | 0.692 | 0.690 | 4.661 | 3.971 | 0.000 | -0.002 | BEST |
| Path 2 | EDAC_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK | EDAC_0/CORERESETP_0/mss_ready_state:ALn | 0.803 | 0.803 | 4.772 | 3.969 | 0.000 | 0.000 | BEST |
| Path 3 | EDAC_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK | EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:ALn | 1.546 | 1.529 | 5.515 | 3.986 | 0.000 | -0.017 | BEST |
| Path 4 | EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:CLK | EDAC_0/CORERESETP_0/INIT_DONE_int:ALn | 2.566 | 2.558 | 6.541 | 3.983 | 0.000 | -0.008 | BEST |
| Path 5 | EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:CLK | EDAC_0/CORERESETP_0/CONFIG1_DONE_clk_base:ALn | 2.606 | 2.571 | 6.581 | 4.010 | 0.000 | -0.035 | BEST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: EDAC_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK | ||||||||
| To: EDAC_0/CORERESETP_0/mss_ready_select:ALn | ||||||||
| data arrival time | 4.661 | |||||||
| data required time | - | 3.971 | ||||||
| slack | 0.690 | |||||||
| Data arrival time calculation | ||||||||
| EDAC_0/CCC_0/GL0 | 0.000 | 0.000 | ||||||
| EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 2.587 | 2.587 | |||||
| EDAC_0/CCC_0/GL0_INST:An | net | EDAC_0/CCC_0/GL0_net | + | 0.309 | 2.896 | r | ||
| EDAC_0/CCC_0/GL0_INST:YEn | cell | ADLIB:GBM | + | 0.118 | 3.014 | 6 | f | |
| EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB0:An | net | EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast | + | 0.407 | 3.421 | f | ||
| EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB0:YR | cell | ADLIB:RGB | + | 0.212 | 3.633 | 8 | r | |
| EDAC_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:CLK | net | EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB0_rgbr_net_1 | + | 0.336 | 3.969 | r | ||
| EDAC_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:Q | cell | ADLIB:SLE | + | 0.058 | 4.027 | 3 | r | |
| EDAC_0/CORERESETP_0/mss_ready_select:ALn | net | EDAC_0/CORERESETP_0/POWER_ON_RESET_N_clk_base_Z | + | 0.634 | 4.661 | r | ||
| data arrival time | 4.661 | |||||||
| Data required time calculation | ||||||||
| EDAC_0/CCC_0/GL0 | Clock Constraint | 0.000 | 0.000 | |||||
| EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 2.587 | 2.587 | |||||
| EDAC_0/CCC_0/GL0_INST:An | net | EDAC_0/CCC_0/GL0_net | + | 0.309 | 2.896 | r | ||
| EDAC_0/CCC_0/GL0_INST:YEn | cell | ADLIB:GBM | + | 0.118 | 3.014 | 6 | f | |
| EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB0:An | net | EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast | + | 0.407 | 3.421 | f | ||
| EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB0:YR | cell | ADLIB:RGB | + | 0.212 | 3.633 | 8 | r | |
| EDAC_0/CORERESETP_0/mss_ready_select:CLK | net | EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB0_rgbr_net_1 | + | 0.338 | 3.971 | r | ||
| EDAC_0/CORERESETP_0/mss_ready_select:ALn | Library removal time | ADLIB:SLE | + | 0.000 | 3.971 | |||
| data required time | 3.971 | |||||||
| Operating Conditions | BEST |
No Path
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Hold (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|
| Path 1 | EDAC_0/CORERESETP_0/release_sdif2_core:CLK | EDAC_0/CORERESETP_0/release_sdif2_core_q1:D | 0.413 | 2.179 | 6.183 | 4.004 | 0.000 | BEST |
| Path 2 | EDAC_0/CORERESETP_0/release_sdif3_core:CLK | EDAC_0/CORERESETP_0/release_sdif3_core_q1:D | 0.406 | 2.190 | 6.186 | 3.996 | 0.000 | BEST |
| Path 3 | EDAC_0/CORERESETP_0/ddr_settled:CLK | EDAC_0/CORERESETP_0/ddr_settled_q1:D | 0.409 | 2.191 | 6.187 | 3.996 | 0.000 | BEST |
| Path 4 | EDAC_0/CORERESETP_0/release_sdif0_core:CLK | EDAC_0/CORERESETP_0/release_sdif0_core_q1:D | 0.518 | 2.280 | 6.284 | 4.004 | 0.000 | BEST |
| Path 5 | EDAC_0/CORERESETP_0/release_sdif1_core:CLK | EDAC_0/CORERESETP_0/release_sdif1_core_q1:D | 0.521 | 2.316 | 6.313 | 3.997 | 0.000 | BEST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: EDAC_0/CORERESETP_0/release_sdif2_core:CLK | ||||||||
| To: EDAC_0/CORERESETP_0/release_sdif2_core_q1:D | ||||||||
| data arrival time | 6.183 | |||||||
| data required time | - | 4.004 | ||||||
| slack | 2.179 | |||||||
| Data arrival time calculation | ||||||||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 0.000 | 0.000 | ||||||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source | + | 0.000 | 0.000 | r | |||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC | + | 2.078 | 2.078 | r | ||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.102 | 2.180 | 1 | r | |
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT | + | 2.398 | 4.578 | f | ||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn | cell | ADLIB:GBM | + | 0.250 | 4.828 | 2 | f | |
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An | net | EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast | + | 0.395 | 5.223 | f | ||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YR | cell | ADLIB:RGB | + | 0.212 | 5.435 | 2 | r | |
| EDAC_0/CORERESETP_0/release_sdif2_core:CLK | net | EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbr_net_1 | + | 0.335 | 5.770 | r | ||
| EDAC_0/CORERESETP_0/release_sdif2_core:Q | cell | ADLIB:SLE | + | 0.058 | 5.828 | 1 | r | |
| EDAC_0/CORERESETP_0/release_sdif2_core_q1:D | net | EDAC_0/CORERESETP_0/release_sdif2_core_Z | + | 0.355 | 6.183 | r | ||
| data arrival time | 6.183 | |||||||
| Data required time calculation | ||||||||
| EDAC_0/CCC_0/GL0 | Clock Constraint | 0.000 | 0.000 | |||||
| EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 2.587 | 2.587 | |||||
| EDAC_0/CCC_0/GL0_INST:An | net | EDAC_0/CCC_0/GL0_net | + | 0.309 | 2.896 | r | ||
| EDAC_0/CCC_0/GL0_INST:YEn | cell | ADLIB:GBM | + | 0.118 | 3.014 | 6 | f | |
| EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3:An | net | EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast | + | 0.401 | 3.415 | f | ||
| EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3:YR | cell | ADLIB:RGB | + | 0.212 | 3.627 | 12 | r | |
| EDAC_0/CORERESETP_0/release_sdif2_core_q1:CLK | net | EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3_rgbr_net_1 | + | 0.377 | 4.004 | r | ||
| EDAC_0/CORERESETP_0/release_sdif2_core_q1:D | Library hold time | ADLIB:SLE | + | 0.000 | 4.004 | |||
| data required time | 4.004 | |||||||
| Operating Conditions | BEST |
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Hold (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|
| Path 1 | EDAC_0/CORECONFIGP_0/pwdata[8]:CLK | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[8] | 1.367 | -0.649 | 6.699 | 7.348 | 1.734 | WORST |
| Path 2 | EDAC_0/CORECONFIGP_0/pwdata[7]:CLK | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[7] | 1.382 | -0.628 | 6.697 | 7.325 | 1.711 | WORST |
| Path 3 | EDAC_0/CORECONFIGP_0/pwdata[12]:CLK | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[12] | 1.375 | -0.626 | 6.700 | 7.326 | 1.712 | WORST |
| Path 4 | EDAC_0/CORECONFIGP_0/paddr[4]:CLK | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PADDR[4] | 1.380 | -0.606 | 6.692 | 7.298 | 1.684 | WORST |
| Path 5 | EDAC_0/CORECONFIGP_0/paddr[6]:CLK | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PADDR[6] | 1.474 | -0.601 | 6.792 | 7.393 | 1.779 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: EDAC_0/CORECONFIGP_0/pwdata[8]:CLK | ||||||||
| To: EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[8] | ||||||||
| data arrival time | 6.699 | |||||||
| data required time | - | 7.348 | ||||||
| slack | -0.649 | |||||||
| Data arrival time calculation | ||||||||
| EDAC_0/EDAC_MSS_0/CLK_CONFIG_APB | 0.000 | 0.000 | ||||||
| EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB | Clock source | + | 0.000 | 0.000 | r | |||
| EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6:An | net | EDAC_0/EDAC_MSS_0/CLK_CONFIG_APB | + | 3.551 | 3.551 | f | ||
| EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6:YEn | cell | ADLIB:GBM | + | 0.363 | 3.914 | 5 | f | |
| EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6/U0_RGB1_RGB1:An | net | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6/U0_YWn_GEast | + | 0.585 | 4.499 | f | ||
| EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6/U0_RGB1_RGB1:YR | cell | ADLIB:RGB | + | 0.307 | 4.806 | 18 | r | |
| EDAC_0/CORECONFIGP_0/pwdata[8]:CLK | net | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6/U0_RGB1_RGB1_rgbr_net_1 | + | 0.526 | 5.332 | r | ||
| EDAC_0/CORECONFIGP_0/pwdata[8]:Q | cell | ADLIB:SLE | + | 0.105 | 5.437 | 1 | f | |
| EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_281:B | net | EDAC_0/CORECONFIGP_0_MDDR_APBmslave_PWDATA[8] | + | 0.865 | 6.302 | f | ||
| EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_281:IPB | cell | ADLIB:IP_INTERFACE | + | 0.217 | 6.519 | 1 | f | |
| EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[8] | net | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/MDDR_FABRIC_PWDATA_net[8] | + | 0.180 | 6.699 | f | ||
| data arrival time | 6.699 | |||||||
| Data required time calculation | ||||||||
| EDAC_0/EDAC_MSS_0/CLK_CONFIG_APB | Clock Constraint | 0.000 | 0.000 | |||||
| EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB | Clock source | + | 0.000 | 0.000 | r | |||
| EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6:An | net | EDAC_0/EDAC_MSS_0/CLK_CONFIG_APB | + | 3.551 | 3.551 | f | ||
| EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6:YEn | cell | ADLIB:GBM | + | 0.363 | 3.914 | 5 | f | |
| EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6/U0_RGB1:An | net | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6/U0_YWn_GEast | + | 0.590 | 4.504 | f | ||
| EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6/U0_RGB1:YR | cell | ADLIB:RGB | + | 0.307 | 4.811 | 1 | r | |
| EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_274:B | net | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6/U0_RGB1_YR | + | 0.393 | 5.204 | r | ||
| EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_274:IPB | cell | ADLIB:IP_INTERFACE | + | 0.203 | 5.407 | 1 | r | |
| EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_MDDR_APB | net | EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/CLK_MDDR_APB_net | + | 0.207 | 5.614 | r | ||
| EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MDDR_FABRIC_PWDATA[8] | Library hold time | ADLIB:MSS_075_IP | + | 1.734 | 7.348 | |||
| data required time | 7.348 | |||||||
| Operating Conditions | WORST |
No Path
No Path
No Path
No Path
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Hold (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|
| Path 1 | EDAC_0/CORERESETP_0/sdif3_areset_n_rcosc_q1:CLK | EDAC_0/CORERESETP_0/sdif3_areset_n_rcosc:D | 0.317 | 0.306 | 6.116 | 5.810 | 0.000 | BEST |
| Path 2 | EDAC_0/CORERESETP_0/sdif2_areset_n_rcosc_q1:CLK | EDAC_0/CORERESETP_0/sdif2_areset_n_rcosc:D | 0.310 | 0.307 | 6.108 | 5.801 | 0.000 | BEST |
| Path 3 | EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc_q1:CLK | EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc:D | 0.319 | 0.308 | 6.109 | 5.801 | 0.000 | BEST |
| Path 4 | EDAC_0/CORERESETP_0/count_ddr_enable_q1:CLK | EDAC_0/CORERESETP_0/count_ddr_enable_rcosc:D | 0.319 | 0.316 | 6.105 | 5.789 | 0.000 | BEST |
| Path 5 | EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_q1:CLK | EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:D | 0.319 | 0.317 | 6.118 | 5.801 | 0.000 | BEST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: EDAC_0/CORERESETP_0/sdif3_areset_n_rcosc_q1:CLK | ||||||||
| To: EDAC_0/CORERESETP_0/sdif3_areset_n_rcosc:D | ||||||||
| data arrival time | 6.116 | |||||||
| data required time | - | 5.810 | ||||||
| slack | 0.306 | |||||||
| Data arrival time calculation | ||||||||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 0.000 | 0.000 | ||||||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source | + | 0.000 | 0.000 | r | |||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC | + | 2.078 | 2.078 | r | ||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.102 | 2.180 | 1 | r | |
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT | + | 2.398 | 4.578 | f | ||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn | cell | ADLIB:GBM | + | 0.250 | 4.828 | 2 | f | |
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An | net | EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast | + | 0.396 | 5.224 | f | ||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR | cell | ADLIB:RGB | + | 0.212 | 5.436 | 29 | r | |
| EDAC_0/CORERESETP_0/sdif3_areset_n_rcosc_q1:CLK | net | EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR | + | 0.363 | 5.799 | r | ||
| EDAC_0/CORERESETP_0/sdif3_areset_n_rcosc_q1:Q | cell | ADLIB:SLE | + | 0.058 | 5.857 | 1 | r | |
| EDAC_0/CORERESETP_0/sdif3_areset_n_rcosc:D | net | EDAC_0/CORERESETP_0/sdif3_areset_n_rcosc_q1_Z | + | 0.259 | 6.116 | r | ||
| data arrival time | 6.116 | |||||||
| Data required time calculation | ||||||||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | Clock Constraint | 0.000 | 0.000 | |||||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source | + | 0.000 | 0.000 | r | |||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC | + | 2.078 | 2.078 | r | ||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.102 | 2.180 | 1 | r | |
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT | + | 2.398 | 4.578 | f | ||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn | cell | ADLIB:GBM | + | 0.250 | 4.828 | 2 | f | |
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An | net | EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast | + | 0.396 | 5.224 | f | ||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR | cell | ADLIB:RGB | + | 0.212 | 5.436 | 29 | r | |
| EDAC_0/CORERESETP_0/sdif3_areset_n_rcosc:CLK | net | EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR | + | 0.374 | 5.810 | r | ||
| EDAC_0/CORERESETP_0/sdif3_areset_n_rcosc:D | Library hold time | ADLIB:SLE | + | 0.000 | 5.810 | |||
| data required time | 5.810 | |||||||
| Operating Conditions | BEST |
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Removal (ns) | Skew (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | EDAC_0/CORERESETP_0/sdif2_areset_n_rcosc:CLK | EDAC_0/CORERESETP_0/release_sdif2_core:ALn | 0.534 | 0.544 | 6.324 | 5.780 | 0.000 | 0.010 | BEST |
| Path 2 | EDAC_0/CORERESETP_0/sdif3_areset_n_rcosc:CLK | EDAC_0/CORERESETP_0/release_sdif3_core:ALn | 0.638 | 0.646 | 6.437 | 5.791 | 0.000 | 0.008 | BEST |
| Path 3 | EDAC_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK | EDAC_0/CORERESETP_0/release_sdif0_core:ALn | 0.772 | 0.786 | 6.562 | 5.776 | 0.000 | 0.014 | BEST |
| Path 4 | EDAC_0/CORERESETP_0/sdif1_areset_n_rcosc:CLK | EDAC_0/CORERESETP_0/release_sdif1_core:ALn | 0.867 | 0.854 | 6.657 | 5.803 | 0.000 | -0.013 | BEST |
| Path 5 | EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK | EDAC_0/CORERESETP_0/count_ddr[0]:ALn | 3.351 | 3.344 | 9.141 | 5.797 | 0.000 | -0.007 | BEST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: EDAC_0/CORERESETP_0/sdif2_areset_n_rcosc:CLK | ||||||||
| To: EDAC_0/CORERESETP_0/release_sdif2_core:ALn | ||||||||
| data arrival time | 6.324 | |||||||
| data required time | - | 5.780 | ||||||
| slack | 0.544 | |||||||
| Data arrival time calculation | ||||||||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 0.000 | 0.000 | ||||||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source | + | 0.000 | 0.000 | r | |||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC | + | 2.078 | 2.078 | r | ||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.102 | 2.180 | 1 | r | |
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT | + | 2.398 | 4.578 | f | ||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn | cell | ADLIB:GBM | + | 0.250 | 4.828 | 2 | f | |
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An | net | EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast | + | 0.396 | 5.224 | f | ||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR | cell | ADLIB:RGB | + | 0.212 | 5.436 | 29 | r | |
| EDAC_0/CORERESETP_0/sdif2_areset_n_rcosc:CLK | net | EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR | + | 0.354 | 5.790 | r | ||
| EDAC_0/CORERESETP_0/sdif2_areset_n_rcosc:Q | cell | ADLIB:SLE | + | 0.058 | 5.848 | 1 | r | |
| EDAC_0/CORERESETP_0/release_sdif2_core:ALn | net | EDAC_0/CORERESETP_0/sdif2_areset_n_rcosc_Z | + | 0.476 | 6.324 | r | ||
| data arrival time | 6.324 | |||||||
| Data required time calculation | ||||||||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | Clock Constraint | 0.000 | 0.000 | |||||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source | + | 0.000 | 0.000 | r | |||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC | + | 2.078 | 2.078 | r | ||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.102 | 2.180 | 1 | r | |
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT | + | 2.398 | 4.578 | f | ||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn | cell | ADLIB:GBM | + | 0.250 | 4.828 | 2 | f | |
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An | net | EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast | + | 0.395 | 5.223 | f | ||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YR | cell | ADLIB:RGB | + | 0.212 | 5.435 | 2 | r | |
| EDAC_0/CORERESETP_0/release_sdif2_core:CLK | net | EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbr_net_1 | + | 0.345 | 5.780 | r | ||
| EDAC_0/CORERESETP_0/release_sdif2_core:ALn | Library removal time | ADLIB:SLE | + | 0.000 | 5.780 | |||
| data required time | 5.780 | |||||||
| Operating Conditions | BEST |
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Hold (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|
| Path 1 | EDAC_0/CORERESETP_0/count_ddr_enable:CLK | EDAC_0/CORERESETP_0/count_ddr_enable_q1:D | 0.579 | -2.025 | 6.370 | 8.395 | 0.000 | WORST |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: EDAC_0/CORERESETP_0/count_ddr_enable:CLK | ||||||||
| To: EDAC_0/CORERESETP_0/count_ddr_enable_q1:D | ||||||||
| data arrival time | 6.370 | |||||||
| data required time | - | 8.395 | ||||||
| slack | -2.025 | |||||||
| Data arrival time calculation | ||||||||
| EDAC_0/CCC_0/GL0 | 0.000 | 0.000 | ||||||
| EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 3.743 | 3.743 | |||||
| EDAC_0/CCC_0/GL0_INST:An | net | EDAC_0/CCC_0/GL0_net | + | 0.447 | 4.190 | r | ||
| EDAC_0/CCC_0/GL0_INST:YEn | cell | ADLIB:GBM | + | 0.173 | 4.363 | 6 | f | |
| EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An | net | EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast | + | 0.593 | 4.956 | f | ||
| EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YR | cell | ADLIB:RGB | + | 0.307 | 5.263 | 12 | r | |
| EDAC_0/CORERESETP_0/count_ddr_enable:CLK | net | EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbr_net_1 | + | 0.528 | 5.791 | r | ||
| EDAC_0/CORERESETP_0/count_ddr_enable:Q | cell | ADLIB:SLE | + | 0.084 | 5.875 | 1 | r | |
| EDAC_0/CORERESETP_0/count_ddr_enable_q1:D | net | EDAC_0/CORERESETP_0/count_ddr_enable_Z | + | 0.495 | 6.370 | r | ||
| data arrival time | 6.370 | |||||||
| Data required time calculation | ||||||||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | Clock Constraint | 0.000 | 0.000 | |||||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT | Clock source | + | 0.000 | 0.000 | r | |||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A | net | EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC | + | 3.008 | 3.008 | r | ||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT | cell | ADLIB:RCOSC_25_50MHZ_FAB | + | 0.147 | 3.155 | 1 | r | |
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An | net | EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT | + | 3.471 | 6.626 | f | ||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn | cell | ADLIB:GBM | + | 0.363 | 6.989 | 2 | f | |
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An | net | EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast | + | 0.576 | 7.565 | f | ||
| EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR | cell | ADLIB:RGB | + | 0.307 | 7.872 | 29 | r | |
| EDAC_0/CORERESETP_0/count_ddr_enable_q1:CLK | net | EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR | + | 0.523 | 8.395 | r | ||
| EDAC_0/CORERESETP_0/count_ddr_enable_q1:D | Library hold time | ADLIB:SLE | + | 0.000 | 8.395 | |||
| data required time | 8.395 | |||||||
| Operating Conditions | WORST |
No Path