Timing Multi Corner Report Max Delay Analysis

SmartTime Version 12.900.20.24

Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)

Date: Fri Mar 19 19:32:30 2021

Design top
Family SmartFusion2
Die M2S090TS
Package 484 FBGA
Temperature Range 0 - 85 C
Voltage Range 1.14 - 1.26 V
Speed Grade -1
Design State Post-Layout
Data source Production
Multi Corner Report Operating Conditions BEST, TYPICAL, WORST
Scenario for Timing Analysis timing_analysis

Summary

Clock Domain Required Period (ns) Required Frequency (MHz) Worst Slack (ns) Operating Conditions
EDAC_0/CCC_0/GL0 10.000 100.000 5.516 WORST
EDAC_0/EDAC_MSS_0/CLK_CONFIG_APB 36.036 27.750 1.876 BEST
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 20.000 50.000 9.063 WORST

Worst Slack (ns) Operating Conditions
Input to Output

Clock Domain EDAC_0/CCC_0/GL0

Info: The maximum frequency of this clock domain is limited by the period of pin EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 EDAC_0/CORERESETP_0/RESET_N_M2F_clk_base:CLK EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:D 2.955 6.777 8.891 15.668 0.254 3.223 WORST
Path 2 EDAC_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_clk_base:CLK EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:D 2.913 6.821 8.847 15.668 0.254 3.179 WORST
Path 3 EDAC_0/CORERESETP_0/mss_ready_select:CLK EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:D 2.792 6.958 8.710 15.668 0.254 3.042 WORST
Path 4 EDAC_0/CORERESETP_0/ddr_settled_clk_base:CLK EDAC_0/CORERESETP_0/count_ddr_enable:EN 1.890 7.789 7.852 15.641 0.308 2.211 WORST
Path 5 EDAC_0/CORERESETP_0/sm0_state[5]:CLK EDAC_0/CORERESETP_0/sm0_state[6]:EN 1.686 7.964 7.639 15.603 0.308 2.036 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: EDAC_0/CORERESETP_0/RESET_N_M2F_clk_base:CLK
To: EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:D
data required time 15.668
data arrival time - 8.891
slack 6.777
Data arrival time calculation
EDAC_0/CCC_0/GL0 0.000 0.000
EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 3.859 3.859
EDAC_0/CCC_0/GL0_INST:An net EDAC_0/CCC_0/GL0_net + 0.461 4.320 r
EDAC_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 4.498 6 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB0:An net EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.611 5.109 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB0:YR cell ADLIB:RGB + 0.316 5.425 6 r
EDAC_0/CORERESETP_0/RESET_N_M2F_clk_base:CLK net EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB0_rgbr_net_1 + 0.511 5.936 r
EDAC_0/CORERESETP_0/RESET_N_M2F_clk_base:Q cell ADLIB:SLE + 0.087 6.023 2 r
EDAC_0/CORERESETP_0/MSS_HPMS_READY_int_4:B net EDAC_0/CORERESETP_0/RESET_N_M2F_clk_base_Z + 0.443 6.466 r
EDAC_0/CORERESETP_0/MSS_HPMS_READY_int_4:Y cell ADLIB:CFG3 + 0.202 6.668 1 r
EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:D net EDAC_0/CORERESETP_0/MSS_HPMS_READY_int_4_Z + 2.223 8.891 r
data arrival time 8.891
Data required time calculation
EDAC_0/CCC_0/GL0 Clock Constraint 10.000 10.000
EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 10.000 r
Clock generation + 3.859 13.859
EDAC_0/CCC_0/GL0_INST:An net EDAC_0/CCC_0/GL0_net + 0.461 14.320 r
EDAC_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 14.498 6 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB4:An net EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.626 15.124 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB4:YL cell ADLIB:RGB + 0.317 15.441 3 r
EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:CLK net EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB4_rgbl_net_1 + 0.481 15.922 r
EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:D Library setup time ADLIB:SLE - 0.254 15.668
data required time 15.668
Operating Conditions WORST

SET External Setup

No Path

SET Clock to Output

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Clock to Out (ns) Operating Conditions
Path 1 EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE MMUART_1_TXD 5.967 12.230 12.230 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE
To: MMUART_1_TXD
data required time N/C
data arrival time - 12.230
slack N/C
Data arrival time calculation
EDAC_0/CCC_0/GL0 0.000 0.000
EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 3.859 3.859
EDAC_0/CCC_0/GL0_INST:An net EDAC_0/CCC_0/GL0_net + 0.461 4.320 r
EDAC_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 4.498 6 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1:An net EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.620 5.118 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1:YR cell ADLIB:RGB + 0.316 5.434 1 r
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B net EDAC_0/CCC_0/GL0_INST/U0_RGB1_YR + 0.404 5.838 r
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB cell ADLIB:IP_INTERFACE + 0.209 6.047 1 r
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE net EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/CLK_BASE_net + 0.216 6.263 r
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT cell ADLIB:MSS_075_IP + 1.982 8.245 1 f
EDAC_0/EDAC_MSS_0/MMUART_1_TXD_PAD/U_IOPAD:D net EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT + 1.319 9.564 f
EDAC_0/EDAC_MSS_0/MMUART_1_TXD_PAD/U_IOPAD:PAD cell ADLIB:IOPAD_TRI + 2.666 12.230 0 f
MMUART_1_TXD net MMUART_1_TXD + 0.000 12.230 f
data arrival time 12.230
Data required time calculation
EDAC_0/CCC_0/GL0 N/C N/C
EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 N/C r
Clock generation + 3.859 N/C
MMUART_1_TXD N/C f
Operating Conditions WORST

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:CLK EDAC_0/CORERESETP_0/sm0_areset_n_q1:ALn 4.116 5.516 10.053 15.569 0.353 4.484 0.015 WORST
Path 2 EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:CLK EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:ALn 4.116 5.516 10.053 15.569 0.353 4.484 0.015 WORST
Path 3 EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:CLK EDAC_0/CORERESETP_0/release_sdif3_core_clk_base:ALn 3.891 5.752 9.828 15.580 0.353 4.248 0.004 WORST
Path 4 EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:CLK EDAC_0/CORERESETP_0/release_sdif0_core_clk_base:ALn 3.891 5.752 9.828 15.580 0.353 4.248 0.004 WORST
Path 5 EDAC_0/CORERESETP_0/sm0_areset_n_clk_base:CLK EDAC_0/CORERESETP_0/ddr_settled_q1:ALn 3.891 5.752 9.828 15.580 0.353 4.248 0.004 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:CLK
To: EDAC_0/CORERESETP_0/sm0_areset_n_q1:ALn
data required time 15.569
data arrival time - 10.053
slack 5.516
Data arrival time calculation
EDAC_0/CCC_0/GL0 0.000 0.000
EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 3.859 3.859
EDAC_0/CCC_0/GL0_INST:An net EDAC_0/CCC_0/GL0_net + 0.461 4.320 r
EDAC_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 4.498 6 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB4:An net EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.626 5.124 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB4:YL cell ADLIB:RGB + 0.317 5.441 3 r
EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:CLK net EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB4_rgbl_net_1 + 0.496 5.937 r
EDAC_0/CORERESETP_0/MSS_HPMS_READY_int:Q cell ADLIB:SLE + 0.087 6.024 1 r
EDAC_0/CORERESETP_0/sdif0_areset_n:A net EDAC_0/CORERESETP_0/MSS_HPMS_READY_int_Z + 0.308 6.332 r
EDAC_0/CORERESETP_0/sdif0_areset_n:Y cell ADLIB:CFG2 + 0.074 6.406 1 r
EDAC_0/CORERESETP_0/sdif0_areset_n_RNI934D:An net EDAC_0/CORERESETP_0/sm0_areset_n + 1.826 8.232 f
EDAC_0/CORERESETP_0/sdif0_areset_n_RNI934D:YEn cell ADLIB:GBM + 0.374 8.606 2 f
EDAC_0/CORERESETP_0/sdif0_areset_n_RNI934D/U0_RGB1_RGB0:An net EDAC_0/CORERESETP_0/sdif0_areset_n_RNI934D/U0_YWn_GEast + 0.621 9.227 f
EDAC_0/CORERESETP_0/sdif0_areset_n_RNI934D/U0_RGB1_RGB0:YL cell ADLIB:RGB + 0.317 9.544 2 r
EDAC_0/CORERESETP_0/sm0_areset_n_q1:ALn net EDAC_0/CORERESETP_0/sdif0_areset_n_RNI934D/U0_RGB1_RGB0_rgbl_net_1 + 0.509 10.053 r
data arrival time 10.053
Data required time calculation
EDAC_0/CCC_0/GL0 Clock Constraint 10.000 10.000
EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 10.000 r
Clock generation + 3.859 13.859
EDAC_0/CCC_0/GL0_INST:An net EDAC_0/CCC_0/GL0_net + 0.461 14.320 r
EDAC_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 14.498 6 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB4:An net EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.626 15.124 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB4:YL cell ADLIB:RGB + 0.317 15.441 3 r
EDAC_0/CORERESETP_0/sm0_areset_n_q1:CLK net EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB4_rgbl_net_1 + 0.481 15.922 r
EDAC_0/CORERESETP_0/sm0_areset_n_q1:ALn Library recovery time ADLIB:SLE - 0.353 15.569
data required time 15.569
Operating Conditions WORST

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET EDAC_0/EDAC_MSS_0/CLK_CONFIG_APB to EDAC_0/CCC_0/GL0

No Path

SET EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT to EDAC_0/CCC_0/GL0

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Operating Conditions
Path 1 EDAC_0/CORERESETP_0/release_sdif1_core:CLK EDAC_0/CORERESETP_0/release_sdif1_core_q1:D 0.781 6.252 9.428 15.680 0.254 WORST
Path 2 EDAC_0/CORERESETP_0/release_sdif0_core:CLK EDAC_0/CORERESETP_0/release_sdif0_core_q1:D 0.773 6.311 9.380 15.691 0.254 WORST
Path 3 EDAC_0/CORERESETP_0/release_sdif3_core:CLK EDAC_0/CORERESETP_0/release_sdif3_core_q1:D 0.607 6.443 9.236 15.679 0.254 WORST
Path 4 EDAC_0/CORERESETP_0/ddr_settled:CLK EDAC_0/CORERESETP_0/ddr_settled_q1:D 0.610 6.443 9.236 15.679 0.254 WORST
Path 5 EDAC_0/CORERESETP_0/release_sdif2_core:CLK EDAC_0/CORERESETP_0/release_sdif2_core_q1:D 0.617 6.461 9.231 15.692 0.254 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: EDAC_0/CORERESETP_0/release_sdif1_core:CLK
To: EDAC_0/CORERESETP_0/release_sdif1_core_q1:D
data required time 15.680
data arrival time - 9.428
slack 6.252
Data arrival time calculation
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 0.000 0.000
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 0.000 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 3.101 3.101 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 3.253 1 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 3.578 6.831 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.374 7.205 2 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An net EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.594 7.799 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR cell ADLIB:RGB + 0.316 8.115 29 r
EDAC_0/CORERESETP_0/release_sdif1_core:CLK net EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR + 0.532 8.647 r
EDAC_0/CORERESETP_0/release_sdif1_core:Q cell ADLIB:SLE + 0.087 8.734 1 r
EDAC_0/CORERESETP_0/release_sdif1_core_q1:D net EDAC_0/CORERESETP_0/release_sdif1_core_Z + 0.694 9.428 r
data arrival time 9.428
Data required time calculation
EDAC_0/CCC_0/GL0 Clock Constraint 10.000 10.000
EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 10.000 r
Clock generation + 3.859 13.859
EDAC_0/CCC_0/GL0_INST:An net EDAC_0/CCC_0/GL0_net + 0.461 14.320 r
EDAC_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 14.498 6 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3:An net EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.601 15.099 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3:YR cell ADLIB:RGB + 0.316 15.415 12 r
EDAC_0/CORERESETP_0/release_sdif1_core_q1:CLK net EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB3_rgbr_net_1 + 0.519 15.934 r
EDAC_0/CORERESETP_0/release_sdif1_core_q1:D Library setup time ADLIB:SLE - 0.254 15.680
data required time 15.680
Operating Conditions WORST

Clock Domain EDAC_0/EDAC_MSS_0/CLK_CONFIG_APB

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN 1.664 1.876 1.664 3.540 0.245 -1.876 BEST
Path 2 EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB EDAC_0/CORECONFIGP_0/state[0]:D 1.431 2.153 1.431 3.584 0.201 -2.153 BEST
Path 3 EDAC_0/CORECONFIGP_0/psel:CLK EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN 2.942 14.605 8.589 23.194 0.308 6.826 WORST
Path 4 EDAC_0/CORECONFIGP_0/psel:CLK EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[5]:D 2.543 15.058 8.190 23.248 0.254 5.920 WORST
Path 5 EDAC_0/CORECONFIGP_0/psel:CLK EDAC_0/CORECONFIGP_0/state[1]:D 2.492 15.099 8.139 23.238 0.254 5.838 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB
To: EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN
data required time 3.540
data arrival time - 1.664
slack 1.876
Data arrival time calculation
EDAC_0/EDAC_MSS_0/CLK_CONFIG_APB 0.000 0.000
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB Clock source + 0.000 0.000 r
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:PER2_FABRIC_PENABLE cell ADLIB:MSS_075_IP + 0.587 0.587 2 r
EDAC_0/CORECONFIGP_0/next_state4:A net EDAC_0/EDAC_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE + 0.483 1.070 r
EDAC_0/CORECONFIGP_0/next_state4:Y cell ADLIB:CFG2 + 0.098 1.168 2 f
EDAC_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_0:C net EDAC_0/CORECONFIGP_0/next_state4_Z + 0.066 1.234 f
EDAC_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_0:Y cell ADLIB:CFG4 + 0.060 1.294 1 f
EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN net EDAC_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_0_Z + 0.370 1.664 f
data arrival time 1.664
Data required time calculation
EDAC_0/EDAC_MSS_0/CLK_CONFIG_APB Max Delay Constraint 0.000 0.000
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_CONFIG_APB Clock source + 0.000 0.000 r
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6:An net EDAC_0/EDAC_MSS_0/CLK_CONFIG_APB + 2.530 2.530 f
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6:YEn cell ADLIB:GBM + 0.257 2.787 5 f
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6/U0_RGB1_RGB1:An net EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6/U0_YWn_GEast + 0.414 3.201 f
EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6/U0_RGB1_RGB1:YR cell ADLIB:RGB + 0.218 3.419 18 r
EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:CLK net EDAC_0/EDAC_MSS_0/MSS_ADLIB_INST_RNIHGA6/U0_RGB1_RGB1_rgbr_net_1 + 0.366 3.785 r
EDAC_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN Library setup time ADLIB:SLE - 0.245 3.540
data required time 3.540
Operating Conditions BEST

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET EDAC_0/CCC_0/GL0 to EDAC_0/EDAC_MSS_0/CLK_CONFIG_APB

No Path

Clock Domain EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 EDAC_0/CORERESETP_0/count_ddr[10]:CLK EDAC_0/CORERESETP_0/ddr_settled:EN 2.732 16.927 11.376 28.303 0.308 3.073 WORST
Path 2 EDAC_0/CORERESETP_0/count_ddr[9]:CLK EDAC_0/CORERESETP_0/ddr_settled:EN 2.572 17.075 11.228 28.303 0.308 2.925 WORST
Path 3 EDAC_0/CORERESETP_0/count_ddr[1]:CLK EDAC_0/CORERESETP_0/ddr_settled:EN 2.535 17.112 11.191 28.303 0.308 2.888 WORST
Path 4 EDAC_0/CORERESETP_0/count_ddr[4]:CLK EDAC_0/CORERESETP_0/ddr_settled:EN 2.534 17.125 11.178 28.303 0.308 2.875 WORST
Path 5 EDAC_0/CORERESETP_0/count_ddr[7]:CLK EDAC_0/CORERESETP_0/ddr_settled:EN 2.410 17.237 11.066 28.303 0.308 2.763 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: EDAC_0/CORERESETP_0/count_ddr[10]:CLK
To: EDAC_0/CORERESETP_0/ddr_settled:EN
data required time 28.303
data arrival time - 11.376
slack 16.927
Data arrival time calculation
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 0.000 0.000
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 0.000 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 3.101 3.101 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 3.253 1 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 3.578 6.831 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.374 7.205 2 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An net EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.594 7.799 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR cell ADLIB:RGB + 0.316 8.115 29 r
EDAC_0/CORERESETP_0/count_ddr[10]:CLK net EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR + 0.529 8.644 r
EDAC_0/CORERESETP_0/count_ddr[10]:Q cell ADLIB:SLE + 0.108 8.752 2 f
EDAC_0/CORERESETP_0/ddr_settled4_7:A net EDAC_0/CORERESETP_0/count_ddr_Z[10] + 0.677 9.429 f
EDAC_0/CORERESETP_0/ddr_settled4_7:Y cell ADLIB:CFG4 + 0.287 9.716 1 f
EDAC_0/CORERESETP_0/ddr_settled4:B net EDAC_0/CORERESETP_0/ddr_settled4_7_Z + 0.224 9.940 f
EDAC_0/CORERESETP_0/ddr_settled4:Y cell ADLIB:CFG4 + 0.209 10.149 1 f
EDAC_0/CORERESETP_0/ddr_settled:EN net EDAC_0/CORERESETP_0/ddr_settled4_Z + 1.227 11.376 f
data arrival time 11.376
Data required time calculation
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Clock Constraint 20.000 20.000
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 20.000 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 3.101 23.101 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 23.253 1 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 3.578 26.831 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.374 27.205 2 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An net EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.594 27.799 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR cell ADLIB:RGB + 0.316 28.115 29 r
EDAC_0/CORERESETP_0/ddr_settled:CLK net EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR + 0.496 28.611 r
EDAC_0/CORERESETP_0/ddr_settled:EN Library setup time ADLIB:SLE - 0.308 28.303
data required time 28.303
Operating Conditions WORST

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK EDAC_0/CORERESETP_0/count_ddr[6]:ALn 5.029 14.603 13.672 28.275 0.353 5.397 0.015 WORST
Path 2 EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK EDAC_0/CORERESETP_0/count_ddr[4]:ALn 5.029 14.603 13.672 28.275 0.353 5.397 0.015 WORST
Path 3 EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK EDAC_0/CORERESETP_0/count_ddr[2]:ALn 5.029 14.603 13.672 28.275 0.353 5.397 0.015 WORST
Path 4 EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK EDAC_0/CORERESETP_0/count_ddr[10]:ALn 5.029 14.603 13.672 28.275 0.353 5.397 0.015 WORST
Path 5 EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK EDAC_0/CORERESETP_0/count_ddr[8]:ALn 5.029 14.604 13.672 28.276 0.353 5.396 0.014 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK
To: EDAC_0/CORERESETP_0/count_ddr[6]:ALn
data required time 28.275
data arrival time - 13.672
slack 14.603
Data arrival time calculation
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT 0.000 0.000
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 0.000 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 3.101 3.101 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 3.253 1 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 3.578 6.831 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.374 7.205 2 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An net EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.594 7.799 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR cell ADLIB:RGB + 0.316 8.115 29 r
EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:CLK net EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR + 0.528 8.643 r
EDAC_0/CORERESETP_0/sm0_areset_n_rcosc:Q cell ADLIB:SLE + 0.087 8.730 1 r
EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683:An net EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_0 + 3.090 11.820 f
EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683:YEn cell ADLIB:GBM + 0.374 12.194 1 f
EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683/U0_RGB1:An net EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683/U0_YWn_GEast + 0.599 12.793 f
EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683/U0_RGB1:YR cell ADLIB:RGB + 0.316 13.109 17 r
EDAC_0/CORERESETP_0/count_ddr[6]:ALn net EDAC_0/CORERESETP_0/sm0_areset_n_rcosc_RNIS683/U0_RGB1_YR + 0.563 13.672 r
data arrival time 13.672
Data required time calculation
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Clock Constraint 20.000 20.000
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 20.000 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 3.101 23.101 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 23.253 1 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 3.578 26.831 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.374 27.205 2 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An net EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.594 27.799 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR cell ADLIB:RGB + 0.316 28.115 29 r
EDAC_0/CORERESETP_0/count_ddr[6]:CLK net EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR + 0.513 28.628 r
EDAC_0/CORERESETP_0/count_ddr[6]:ALn Library recovery time ADLIB:SLE - 0.353 28.275
data required time 28.275
Operating Conditions WORST

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET EDAC_0/CCC_0/GL0 to EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Operating Conditions
Path 1 EDAC_0/CORERESETP_0/count_ddr_enable:CLK EDAC_0/CORERESETP_0/count_ddr_enable_q1:D 3.420 9.063 9.385 18.448 0.174 WORST

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: EDAC_0/CORERESETP_0/count_ddr_enable:CLK
To: EDAC_0/CORERESETP_0/count_ddr_enable_q1:D
data required time 18.448
data arrival time - 9.385
slack 9.063
Data arrival time calculation
EDAC_0/CCC_0/GL0 0.000 0.000
EDAC_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 Clock source + 0.000 0.000 r
Clock generation + 3.859 3.859
EDAC_0/CCC_0/GL0_INST:An net EDAC_0/CCC_0/GL0_net + 0.461 4.320 r
EDAC_0/CCC_0/GL0_INST:YEn cell ADLIB:GBM + 0.178 4.498 6 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An net EDAC_0/CCC_0/GL0_INST/U0_YWn_GEast + 0.611 5.109 f
EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YR cell ADLIB:RGB + 0.316 5.425 11 r
EDAC_0/CORERESETP_0/count_ddr_enable:CLK net EDAC_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbr_net_1 + 0.540 5.965 r
EDAC_0/CORERESETP_0/count_ddr_enable:Q cell ADLIB:SLE + 0.108 6.073 1 f
mdr_EDAC_0/CORERESETP_0/count_ddr_enable_q1_CFG1C_TEST:A net EDAC_0/CORERESETP_0/count_ddr_enable_Z + 0.612 6.685 f
mdr_EDAC_0/CORERESETP_0/count_ddr_enable_q1_CFG1C_TEST:Y cell ADLIB:CFG1C_TEST + 0.209 6.894 1 f
mdr_EDAC_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST1:A net mdr_EDAC_0/CORERESETP_0/count_ddr_enable_q1_CFG1C_TEST_net + 0.204 7.098 f
mdr_EDAC_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST1:Y cell ADLIB:CFG1D_TEST + 0.372 7.470 1 f
mdr_EDAC_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST0:A net mdr_EDAC_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST_net1 + 0.301 7.771 f
mdr_EDAC_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST0:Y cell ADLIB:CFG1D_TEST + 0.372 8.143 1 f
mdr_EDAC_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST:A net mdr_EDAC_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST_net0 + 0.205 8.348 f
mdr_EDAC_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST:Y cell ADLIB:CFG1D_TEST + 0.372 8.720 1 f
EDAC_0/CORERESETP_0/count_ddr_enable_q1:D net mdr_EDAC_0/CORERESETP_0/count_ddr_enable_q1_CFG1D_TEST_net + 0.665 9.385 f
data arrival time 9.385
Data required time calculation
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT Clock Constraint 10.000 10.000
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT Clock source + 0.000 10.000 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A net EDAC_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC + 3.101 13.101 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT cell ADLIB:RCOSC_25_50MHZ_FAB + 0.152 13.253 1 r
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An net EDAC_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT + 3.578 16.831 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn cell ADLIB:GBM + 0.374 17.205 2 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An net EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast + 0.594 17.799 f
EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR cell ADLIB:RGB + 0.316 18.115 29 r
EDAC_0/CORERESETP_0/count_ddr_enable_q1:CLK net EDAC_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR + 0.507 18.622 r
EDAC_0/CORERESETP_0/count_ddr_enable_q1:D Library setup time ADLIB:SLE - 0.174 18.448
data required time 18.448
Operating Conditions WORST

Path Set Pin to Pin

SET Input to Output

No Path

Path Set User Sets