| Project Settings |
|---|
| Project Name | CodeShadowing_DDR3_top_syn | Implementation Name | synthesis |
| Top Module | CodeShadowing_DDR3_top | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 10000 |
| Disable I/O Insertion | 0 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
39 |
45 |
0 |
- |
0m:02s |
- |
15-Mar-16
12:40:28 PM |
| (premap) | Complete |
31 |
4 |
0 |
0m:00s |
0m:00s |
138MB |
15-Mar-16
12:40:32 PM |
| (fpga_mapper) | Complete |
31 |
47 |
0 |
0m:01s |
0m:01s |
137MB |
15-Mar-16
12:40:34 PM |
| Multi-srs Generator |
Complete | | | | 0m:01s | | | 15-Mar-16
12:40:30 PM |
| Area Summary |
|---|
| |
| Carry Cells | 14 |
Sequential Cells | 125 |
| DSP Blocks (MACC)
(dsp_used) | 0 |
I/O Cells | 65 |
| Global Clock Buffers | 6 |
LUTs
(total_luts) | 78 |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| CodeShadowing_DDR3_CCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | 499.9 MHz | 8.000 |
| CodeShadowing_DDR3_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | 100.0 MHz | 428.6 MHz | 7.667 |
| CodeShadowing_DDR3_MSS|FIC_2_APB_M_PCLK_inferred_clock | 100.0 MHz | 109.6 MHz | 0.875 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 2 / 1 |
| |
|