@W: BN132 :"f:\11.7\codeshadowing_spi_ddr\sf2_codeshadowing_ddr3_df\libero\multistageboot_method\codeshadowing_ddr3\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance CodeShadowing_DDR3_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int,  because it is equivalent to instance CodeShadowing_DDR3_0.CORERESETP_0.FDDR_CORE_RESET_N_int
@W: MT530 :"f:\11.7\codeshadowing_spi_ddr\sf2_codeshadowing_ddr3_df\libero\multistageboot_method\codeshadowing_ddr3\component\work\codeshadowing_ddr3_mss\codeshadowing_ddr3_mss.v":1312:0:1312:13|Found inferred clock CodeShadowing_DDR3_CCC_0_FCCC|GL0_net_inferred_clock which controls 56 sequential elements including CodeShadowing_DDR3_0.CodeShadowing_DDR3_MSS_0.MSS_ADLIB_INST. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"f:\11.7\codeshadowing_spi_ddr\sf2_codeshadowing_ddr3_df\libero\multistageboot_method\codeshadowing_ddr3\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Found inferred clock CodeShadowing_DDR3_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 31 sequential elements including CodeShadowing_DDR3_0.CORERESETP_0.count_ddr[13:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"f:\11.7\codeshadowing_spi_ddr\sf2_codeshadowing_ddr3_df\libero\multistageboot_method\codeshadowing_ddr3\component\work\codeshadowing_ddr3_mss\codeshadowing_ddr3_mss.v":1312:0:1312:13|Found inferred clock CodeShadowing_DDR3_MSS|FIC_2_APB_M_PCLK_inferred_clock which controls 110 sequential elements including CodeShadowing_DDR3_0.CodeShadowing_DDR3_MSS_0.MSS_ADLIB_INST. This clock has no specified timing constraint which may adversely impact design performance. 
