@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG364 :"D:\Microsemi\Libero_v11.7\Synplify\lib\generic\smartfusion2.v":376:7:376:9|Synthesizing module VCC
@N: CG364 :"D:\Microsemi\Libero_v11.7\Synplify\lib\generic\smartfusion2.v":372:7:372:9|Synthesizing module GND
@N: CG364 :"D:\Microsemi\Libero_v11.7\Synplify\lib\generic\smartfusion2.v":362:7:362:12|Synthesizing module CLKINT
@N: CG364 :"D:\Microsemi\Libero_v11.7\Synplify\lib\generic\smartfusion2.v":727:7:727:9|Synthesizing module CCC
@N: CG364 :"F:\11.7\CodeShadowing_SPI_DDR\SF2_CodeShadowing_DDR3_DF\Libero\MultiStageBoot_method\CodeShadowing_DDR3\component\work\CodeShadowing_DDR3\CCC_0\CodeShadowing_DDR3_CCC_0_FCCC.v":5:7:5:35|Synthesizing module CodeShadowing_DDR3_CCC_0_FCCC
@N: CG364 :"D:\Microsemi\Libero_v11.7\Synplify\lib\generic\smartfusion2.v":274:7:274:12|Synthesizing module OUTBUF
@N: CG364 :"D:\Microsemi\Libero_v11.7\Synplify\lib\generic\smartfusion2.v":326:7:326:17|Synthesizing module OUTBUF_DIFF
@N: CG364 :"D:\Microsemi\Libero_v11.7\Synplify\lib\generic\smartfusion2.v":286:7:286:11|Synthesizing module BIBUF
@N: CG364 :"D:\Microsemi\Libero_v11.7\Synplify\lib\generic\smartfusion2.v":338:7:338:16|Synthesizing module BIBUF_DIFF
@N: CG364 :"D:\Microsemi\Libero_v11.7\Synplify\lib\generic\smartfusion2.v":268:7:268:11|Synthesizing module INBUF
@N: CG364 :"D:\Microsemi\Libero_v11.7\Synplify\lib\generic\smartfusion2.v":280:7:280:13|Synthesizing module TRIBUFF
@N: CG364 :"F:\11.7\CodeShadowing_SPI_DDR\SF2_CodeShadowing_DDR3_DF\Libero\MultiStageBoot_method\CodeShadowing_DDR3\component\work\CodeShadowing_DDR3_MSS\CodeShadowing_DDR3_MSS_syn.v":5:7:5:13|Synthesizing module MSS_120
@N: CG364 :"F:\11.7\CodeShadowing_SPI_DDR\SF2_CodeShadowing_DDR3_DF\Libero\MultiStageBoot_method\CodeShadowing_DDR3\component\work\CodeShadowing_DDR3_MSS\CodeShadowing_DDR3_MSS.v":9:7:9:28|Synthesizing module CodeShadowing_DDR3_MSS
@N: CG364 :"F:\11.7\CodeShadowing_SPI_DDR\SF2_CodeShadowing_DDR3_DF\Libero\MultiStageBoot_method\CodeShadowing_DDR3\component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v":22:7:22:17|Synthesizing module CoreConfigP
@N: CG364 :"F:\11.7\CodeShadowing_SPI_DDR\SF2_CodeShadowing_DDR3_DF\Libero\MultiStageBoot_method\CodeShadowing_DDR3\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":23:7:23:16|Synthesizing module CoreResetP
@N: CL177 :"F:\11.7\CodeShadowing_SPI_DDR\SF2_CodeShadowing_DDR3_DF\Libero\MultiStageBoot_method\CodeShadowing_DDR3\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sharing sequential element M3_RESET_N_int.
@N: CL177 :"F:\11.7\CodeShadowing_SPI_DDR\SF2_CodeShadowing_DDR3_DF\Libero\MultiStageBoot_method\CodeShadowing_DDR3\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q1.
@N: CL177 :"F:\11.7\CodeShadowing_SPI_DDR\SF2_CodeShadowing_DDR3_DF\Libero\MultiStageBoot_method\CodeShadowing_DDR3\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q1.
@N: CL177 :"F:\11.7\CodeShadowing_SPI_DDR\SF2_CodeShadowing_DDR3_DF\Libero\MultiStageBoot_method\CodeShadowing_DDR3\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif0_spll_lock_q1.
@N: CL177 :"F:\11.7\CodeShadowing_SPI_DDR\SF2_CodeShadowing_DDR3_DF\Libero\MultiStageBoot_method\CodeShadowing_DDR3\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q1.
@N: CG364 :"F:\11.7\CodeShadowing_SPI_DDR\SF2_CodeShadowing_DDR3_DF\Libero\MultiStageBoot_method\CodeShadowing_DDR3\component\Actel\SgCore\OSC\2.0.101\osc_comps.v":51:7:51:24|Synthesizing module RCOSC_25_50MHZ_FAB
@N: CG364 :"F:\11.7\CodeShadowing_SPI_DDR\SF2_CodeShadowing_DDR3_DF\Libero\MultiStageBoot_method\CodeShadowing_DDR3\component\Actel\SgCore\OSC\2.0.101\osc_comps.v":11:7:11:20|Synthesizing module RCOSC_25_50MHZ
@N: CG364 :"F:\11.7\CodeShadowing_SPI_DDR\SF2_CodeShadowing_DDR3_DF\Libero\MultiStageBoot_method\CodeShadowing_DDR3\component\work\CodeShadowing_DDR3\FABOSC_0\CodeShadowing_DDR3_FABOSC_0_OSC.v":5:7:5:37|Synthesizing module CodeShadowing_DDR3_FABOSC_0_OSC
@N: CG364 :"D:\Microsemi\Libero_v11.7\Synplify\lib\generic\smartfusion2.v":718:7:718:14|Synthesizing module SYSRESET
@N: CG364 :"F:\11.7\CodeShadowing_SPI_DDR\SF2_CodeShadowing_DDR3_DF\Libero\MultiStageBoot_method\CodeShadowing_DDR3\component\work\CodeShadowing_DDR3\CodeShadowing_DDR3.v":9:7:9:24|Synthesizing module CodeShadowing_DDR3
@N: CG364 :"F:\11.7\CodeShadowing_SPI_DDR\SF2_CodeShadowing_DDR3_DF\Libero\MultiStageBoot_method\CodeShadowing_DDR3\component\work\CodeShadowing_DDR3_top\CodeShadowing_DDR3_top.v":9:7:9:28|Synthesizing module CodeShadowing_DDR3_top
@N: CL177 :"F:\11.7\CodeShadowing_SPI_DDR\SF2_CodeShadowing_DDR3_DF\Libero\MultiStageBoot_method\CodeShadowing_DDR3\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif0_spll_lock_q2.
@N: CL177 :"F:\11.7\CodeShadowing_SPI_DDR\SF2_CodeShadowing_DDR3_DF\Libero\MultiStageBoot_method\CodeShadowing_DDR3\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q2.
@N: CL177 :"F:\11.7\CodeShadowing_SPI_DDR\SF2_CodeShadowing_DDR3_DF\Libero\MultiStageBoot_method\CodeShadowing_DDR3\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q2.
@N: CL177 :"F:\11.7\CodeShadowing_SPI_DDR\SF2_CodeShadowing_DDR3_DF\Libero\MultiStageBoot_method\CodeShadowing_DDR3\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q2.
@N: CL201 :"F:\11.7\CodeShadowing_SPI_DDR\SF2_CodeShadowing_DDR3_DF\Libero\MultiStageBoot_method\CodeShadowing_DDR3\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Trying to extract state machine for register sdif3_state
@N: CL201 :"F:\11.7\CodeShadowing_SPI_DDR\SF2_CodeShadowing_DDR3_DF\Libero\MultiStageBoot_method\CodeShadowing_DDR3\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Trying to extract state machine for register sdif2_state
@N: CL201 :"F:\11.7\CodeShadowing_SPI_DDR\SF2_CodeShadowing_DDR3_DF\Libero\MultiStageBoot_method\CodeShadowing_DDR3\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Trying to extract state machine for register sdif1_state
@N: CL201 :"F:\11.7\CodeShadowing_SPI_DDR\SF2_CodeShadowing_DDR3_DF\Libero\MultiStageBoot_method\CodeShadowing_DDR3\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Trying to extract state machine for register sdif0_state
@N: CL201 :"F:\11.7\CodeShadowing_SPI_DDR\SF2_CodeShadowing_DDR3_DF\Libero\MultiStageBoot_method\CodeShadowing_DDR3\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Trying to extract state machine for register sm0_state
@N: CL201 :"F:\11.7\CodeShadowing_SPI_DDR\SF2_CodeShadowing_DDR3_DF\Libero\MultiStageBoot_method\CodeShadowing_DDR3\component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v":447:4:447:9|Trying to extract state machine for register state
@N|Running in 64-bit mode

