
SPI_Flash_Loader:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .vector_table 00000190  00000000  60000000  00008000  2**4
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  1 .boot_code    000008d0  00000190  60000190  00008190  2**4
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .text         00009540  00000a60  60000a60  00008a60  2**4
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  3 .data         00000130  20000000  60009fa0  00018000  2**4
                  CONTENTS, ALLOC, LOAD, DATA
  4 .bss          00000210  20000130  6000a0d0  00018130  2**4
                  ALLOC
  5 .heap         0000ecc0  20000340  6000a0d0  00018340  2**4
                  ALLOC
  6 .stack        00001000  2000f000  6000a0d0  0001f000  2**4
                  ALLOC
  7 .comment      0000022f  00000000  00000000  00018130  2**0
                  CONTENTS, READONLY
  8 .debug_aranges 00000180  00000000  00000000  0001835f  2**0
                  CONTENTS, READONLY, DEBUGGING
  9 .debug_pubnames 00001254  00000000  00000000  000184df  2**0
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_info   0000eb4b  00000000  00000000  00019733  2**0
                  CONTENTS, READONLY, DEBUGGING
 11 .debug_abbrev 00001599  00000000  00000000  0002827e  2**0
                  CONTENTS, READONLY, DEBUGGING
 12 .debug_line   000034fd  00000000  00000000  00029817  2**0
                  CONTENTS, READONLY, DEBUGGING
 13 .debug_frame  00001d34  00000000  00000000  0002cd14  2**2
                  CONTENTS, READONLY, DEBUGGING
 14 .debug_str    00004fd8  00000000  00000000  0002ea48  2**0
                  CONTENTS, READONLY, DEBUGGING
 15 .debug_loc    00003162  00000000  00000000  00033a20  2**0
                  CONTENTS, READONLY, DEBUGGING
 16 .debug_macinfo 00062031  00000000  00000000  00036b82  2**0
                  CONTENTS, READONLY, DEBUGGING
 17 .ARM.attributes 00000025  00000000  00000000  00098bb3  2**0
                  CONTENTS, READONLY
 18 .debug_ranges 00000098  00000000  00000000  00098bd8  2**0
                  CONTENTS, READONLY, DEBUGGING

Disassembly of section .vector_table:

00000000 <__vector_table_start>:
   0:	20010000 	.word	0x20010000
   4:	00000191 	.word	0x00000191
   8:	0000037f 	.word	0x0000037f
   c:	00000381 	.word	0x00000381
  10:	00000383 	.word	0x00000383
  14:	00000385 	.word	0x00000385
  18:	00000387 	.word	0x00000387
	...
  2c:	00000389 	.word	0x00000389
  30:	0000038b 	.word	0x0000038b
  34:	00000000 	.word	0x00000000
  38:	0000038d 	.word	0x0000038d
  3c:	0000038f 	.word	0x0000038f
  40:	00000391 	.word	0x00000391
  44:	00000393 	.word	0x00000393
  48:	000072e9 	.word	0x000072e9
  4c:	0000730d 	.word	0x0000730d
  50:	00000399 	.word	0x00000399
  54:	0000039b 	.word	0x0000039b
  58:	0000039d 	.word	0x0000039d
  5c:	0000039f 	.word	0x0000039f
  60:	000003a1 	.word	0x000003a1
  64:	000003a3 	.word	0x000003a3
  68:	00001bc1 	.word	0x00001bc1
  6c:	00001be5 	.word	0x00001be5
  70:	000003a9 	.word	0x000003a9
  74:	000003ab 	.word	0x000003ab
  78:	000003ad 	.word	0x000003ad
  7c:	000003af 	.word	0x000003af
  80:	000003b1 	.word	0x000003b1
  84:	000003b3 	.word	0x000003b3
  88:	000003b5 	.word	0x000003b5
  8c:	000037d9 	.word	0x000037d9
  90:	000003b9 	.word	0x000003b9
  94:	000003bb 	.word	0x000003bb
  98:	000003bd 	.word	0x000003bd
  9c:	000003bf 	.word	0x000003bf
  a0:	000003c1 	.word	0x000003c1
  a4:	000003c3 	.word	0x000003c3
  a8:	000003c5 	.word	0x000003c5
  ac:	00008a69 	.word	0x00008a69
  b0:	00008c0d 	.word	0x00008c0d
  b4:	000003cb 	.word	0x000003cb
  b8:	000003cd 	.word	0x000003cd
  bc:	000003cf 	.word	0x000003cf
  c0:	000003d1 	.word	0x000003d1
  c4:	000003d3 	.word	0x000003d3
  c8:	000003d5 	.word	0x000003d5
  cc:	000003d7 	.word	0x000003d7
  d0:	000003d9 	.word	0x000003d9
  d4:	000003db 	.word	0x000003db
  d8:	000003dd 	.word	0x000003dd
  dc:	000003df 	.word	0x000003df
  e0:	000003e1 	.word	0x000003e1
  e4:	000003e3 	.word	0x000003e3
  e8:	000003e5 	.word	0x000003e5
  ec:	000003e7 	.word	0x000003e7
  f0:	000003e9 	.word	0x000003e9
  f4:	000003eb 	.word	0x000003eb
  f8:	000003ed 	.word	0x000003ed
  fc:	000003ef 	.word	0x000003ef
 100:	000003f1 	.word	0x000003f1
 104:	000003f3 	.word	0x000003f3
 108:	000003f5 	.word	0x000003f5
 10c:	000003f7 	.word	0x000003f7
 110:	000003f9 	.word	0x000003f9
 114:	000003fb 	.word	0x000003fb
 118:	000003fd 	.word	0x000003fd
 11c:	000003ff 	.word	0x000003ff
 120:	00000401 	.word	0x00000401
 124:	00000403 	.word	0x00000403
 128:	00000405 	.word	0x00000405
 12c:	00000407 	.word	0x00000407
 130:	00000409 	.word	0x00000409
 134:	0000040b 	.word	0x0000040b
 138:	0000040d 	.word	0x0000040d
 13c:	0000040f 	.word	0x0000040f
 140:	00000411 	.word	0x00000411
 144:	00000413 	.word	0x00000413
 148:	00000415 	.word	0x00000415
 14c:	00000417 	.word	0x00000417
 150:	00000419 	.word	0x00000419
 154:	0000041b 	.word	0x0000041b
 158:	0000041d 	.word	0x0000041d
 15c:	0000041f 	.word	0x0000041f
 160:	00000421 	.word	0x00000421
 164:	00000423 	.word	0x00000423
 168:	00000425 	.word	0x00000425
 16c:	00000427 	.word	0x00000427
 170:	00000429 	.word	0x00000429
 174:	0000042b 	.word	0x0000042b
 178:	0000042d 	.word	0x0000042d
 17c:	0000042f 	.word	0x0000042f
 180:	00000431 	.word	0x00000431
 184:	00000433 	.word	0x00000433
	...

Disassembly of section .boot_code:

00000190 <Reset_Handler>:
 190:	f04f 0b00 	mov.w	fp, #0
 194:	f8df 02be 	ldr.w	r0, [pc, #702]	; 456 <SF2_MDDR_MODE_CR>
 198:	6800      	ldr	r0, [r0, #0]
 19a:	f8df 12b6 	ldr.w	r1, [pc, #694]	; 452 <SF2_EDAC_CR>
 19e:	6809      	ldr	r1, [r1, #0]
 1a0:	f001 0103 	and.w	r1, r1, #3
 1a4:	f000 001c 	and.w	r0, r0, #28
 1a8:	2814      	cmp	r0, #20
 1aa:	d101      	bne.n	1b0 <check_esram_edac>
 1ac:	f04b 0b02 	orr.w	fp, fp, #2

000001b0 <check_esram_edac>:
 1b0:	2900      	cmp	r1, #0
 1b2:	d001      	beq.n	1b8 <check_stack_init>
 1b4:	f04b 0b01 	orr.w	fp, fp, #1

000001b8 <check_stack_init>:
 1b8:	f1bb 0f00 	cmp.w	fp, #0
 1bc:	d005      	beq.n	1ca <system_init>

000001be <clear_stack>:
 1be:	48a7      	ldr	r0, [pc, #668]	; (45c <SF2_MDDR_MODE_CR+0x6>)
 1c0:	49a7      	ldr	r1, [pc, #668]	; (460 <SF2_MDDR_MODE_CR+0xa>)
 1c2:	f8df 2272 	ldr.w	r2, [pc, #626]	; 436 <RAM_INIT_PATTERN>
 1c6:	f000 f89f 	bl	308 <fill_memory>

000001ca <system_init>:
 1ca:	48a6      	ldr	r0, [pc, #664]	; (464 <SF2_MDDR_MODE_CR+0xe>)
 1cc:	4780      	blx	r0
 1ce:	f00b 0a02 	and.w	sl, fp, #2
 1d2:	f1ba 0f00 	cmp.w	sl, #0
 1d6:	d00c      	beq.n	1f2 <remap_memory>
 1d8:	f8df 026e 	ldr.w	r0, [pc, #622]	; 44a <SF2_DDRB_NB_SIZE>
 1dc:	f8df 126e 	ldr.w	r1, [pc, #622]	; 44e <SF2_DDRB_CR>
 1e0:	6802      	ldr	r2, [r0, #0]
 1e2:	680b      	ldr	r3, [r1, #0]
 1e4:	b40f      	push	{r0, r1, r2, r3}
 1e6:	f04f 0200 	mov.w	r2, #0
 1ea:	f04f 03ff 	mov.w	r3, #255	; 0xff
 1ee:	6002      	str	r2, [r0, #0]
 1f0:	600b      	str	r3, [r1, #0]

000001f2 <remap_memory>:
 1f2:	489d      	ldr	r0, [pc, #628]	; (468 <SF2_MDDR_MODE_CR+0x12>)
 1f4:	4a9d      	ldr	r2, [pc, #628]	; (46c <SF2_MDDR_MODE_CR+0x16>)
 1f6:	4b9e      	ldr	r3, [pc, #632]	; (470 <SF2_MDDR_MODE_CR+0x1a>)
 1f8:	2802      	cmp	r0, #2
 1fa:	d108      	bne.n	20e <check_esram_remap>
 1fc:	f8df 123e 	ldr.w	r1, [pc, #574]	; 43e <SF2_ESRAM_CR>
 200:	600a      	str	r2, [r1, #0]
 202:	f8df 1242 	ldr.w	r1, [pc, #578]	; 446 <SF2_ENVM_REMAP_CR>
 206:	600a      	str	r2, [r1, #0]
 208:	f8df 1236 	ldr.w	r1, [pc, #566]	; 442 <SF2_DDR_CR>
 20c:	600b      	str	r3, [r1, #0]

0000020e <check_esram_remap>:
 20e:	2801      	cmp	r0, #1
 210:	d108      	bne.n	224 <check_mirrored_nvm>
 212:	f8df 122e 	ldr.w	r1, [pc, #558]	; 442 <SF2_DDR_CR>
 216:	600a      	str	r2, [r1, #0]
 218:	f8df 122a 	ldr.w	r1, [pc, #554]	; 446 <SF2_ENVM_REMAP_CR>
 21c:	600a      	str	r2, [r1, #0]
 21e:	f8df 121e 	ldr.w	r1, [pc, #542]	; 43e <SF2_ESRAM_CR>
 222:	600b      	str	r3, [r1, #0]

00000224 <check_mirrored_nvm>:
 224:	4893      	ldr	r0, [pc, #588]	; (474 <SF2_MDDR_MODE_CR+0x1e>)
 226:	2800      	cmp	r0, #0
 228:	d109      	bne.n	23e <copy_data>
 22a:	4893      	ldr	r0, [pc, #588]	; (478 <SF2_MDDR_MODE_CR+0x22>)
 22c:	4993      	ldr	r1, [pc, #588]	; (47c <SF2_MDDR_MODE_CR+0x26>)
 22e:	4a94      	ldr	r2, [pc, #592]	; (480 <SF2_MDDR_MODE_CR+0x2a>)
 230:	f000 f832 	bl	298 <block_copy>

00000234 <copy_text>:
 234:	4893      	ldr	r0, [pc, #588]	; (484 <SF2_MDDR_MODE_CR+0x2e>)
 236:	4994      	ldr	r1, [pc, #592]	; (488 <SF2_MDDR_MODE_CR+0x32>)
 238:	4a94      	ldr	r2, [pc, #592]	; (48c <SF2_MDDR_MODE_CR+0x36>)
 23a:	f000 f82d 	bl	298 <block_copy>

0000023e <copy_data>:
 23e:	4894      	ldr	r0, [pc, #592]	; (490 <SF2_MDDR_MODE_CR+0x3a>)
 240:	4994      	ldr	r1, [pc, #592]	; (494 <SF2_MDDR_MODE_CR+0x3e>)
 242:	4a95      	ldr	r2, [pc, #596]	; (498 <SF2_MDDR_MODE_CR+0x42>)
 244:	f000 f828 	bl	298 <block_copy>

00000248 <clear_bss>:
 248:	4894      	ldr	r0, [pc, #592]	; (49c <SF2_MDDR_MODE_CR+0x46>)
 24a:	4995      	ldr	r1, [pc, #596]	; (4a0 <SF2_MDDR_MODE_CR+0x4a>)
 24c:	f8df 21e6 	ldr.w	r2, [pc, #486]	; 436 <RAM_INIT_PATTERN>
 250:	f000 f85a 	bl	308 <fill_memory>

00000254 <clear_heap>:
 254:	f1bb 0f00 	cmp.w	fp, #0
 258:	d012      	beq.n	280 <call_glob_ctor>
 25a:	4892      	ldr	r0, [pc, #584]	; (4a4 <SF2_MDDR_MODE_CR+0x4e>)
 25c:	4992      	ldr	r1, [pc, #584]	; (4a8 <SF2_MDDR_MODE_CR+0x52>)
 25e:	f8df 21da 	ldr.w	r2, [pc, #474]	; 43a <HEAP_INIT_PATTERN>
 262:	f000 f851 	bl	308 <fill_memory>
 266:	f00b 0a02 	and.w	sl, fp, #2
 26a:	f1ba 0f00 	cmp.w	sl, #0
 26e:	d007      	beq.n	280 <call_glob_ctor>
 270:	bc0f      	pop	{r0, r1, r2, r3}
 272:	6002      	str	r2, [r0, #0]
 274:	600b      	str	r3, [r1, #0]
 276:	bf00      	nop
 278:	f3af 8000 	nop.w
 27c:	f3af 8000 	nop.w

00000280 <call_glob_ctor>:
 280:	f8df 0228 	ldr.w	r0, [pc, #552]	; 4ac <SF2_MDDR_MODE_CR+0x56>
 284:	f20f 0e03 	addw	lr, pc, #3
 288:	4700      	bx	r0

0000028a <branch_to_main>:
 28a:	f04f 0000 	mov.w	r0, #0
 28e:	f04f 0100 	mov.w	r1, #0
 292:	f8df f21c 	ldr.w	pc, [pc, #540]	; 4b0 <SF2_MDDR_MODE_CR+0x5a>

00000296 <ExitLoop>:
 296:	e7fe      	b.n	296 <ExitLoop>

00000298 <block_copy>:
 298:	e92d 41f8 	stmdb	sp!, {r3, r4, r5, r6, r7, r8, lr}
 29c:	4288      	cmp	r0, r1
 29e:	d025      	beq.n	2ec <block_copy_exit>
 2a0:	ebb2 0201 	subs.w	r2, r2, r1
 2a4:	d500      	bpl.n	2a8 <block_copy_address_ok>
 2a6:	e7fe      	b.n	2a6 <block_copy+0xe>

000002a8 <block_copy_address_ok>:
 2a8:	ea40 0301 	orr.w	r3, r0, r1
 2ac:	f013 0303 	ands.w	r3, r3, #3
 2b0:	d002      	beq.n	2b8 <block_copy_continue>

000002b2 <block_copy_byte_copy>:
 2b2:	f000 f81d 	bl	2f0 <block_copy_byte>
 2b6:	e019      	b.n	2ec <block_copy_exit>

000002b8 <block_copy_continue>:
 2b8:	f04f 0300 	mov.w	r3, #0
 2bc:	4690      	mov	r8, r2
 2be:	1112      	asrs	r2, r2, #4
 2c0:	d0f7      	beq.n	2b2 <block_copy_byte_copy>

000002c2 <block_copy_loop>:
 2c2:	429a      	cmp	r2, r3
 2c4:	bf1c      	itt	ne
 2c6:	c8f0      	ldmiane	r0!, {r4, r5, r6, r7}
 2c8:	c1f0      	stmiane	r1!, {r4, r5, r6, r7}
 2ca:	f103 0301 	add.w	r3, r3, #1
 2ce:	d1f8      	bne.n	2c2 <block_copy_loop>
 2d0:	f008 080f 	and.w	r8, r8, #15
 2d4:	f1b8 0f00 	cmp.w	r8, #0
 2d8:	d008      	beq.n	2ec <block_copy_exit>

000002da <copy_spare_bytes>:
 2da:	7804      	ldrb	r4, [r0, #0]
 2dc:	700c      	strb	r4, [r1, #0]
 2de:	f100 0001 	add.w	r0, r0, #1
 2e2:	f101 0101 	add.w	r1, r1, #1
 2e6:	f1b8 0801 	subs.w	r8, r8, #1
 2ea:	d1f6      	bne.n	2da <copy_spare_bytes>

000002ec <block_copy_exit>:
 2ec:	e8bd 81f8 	ldmia.w	sp!, {r3, r4, r5, r6, r7, r8, pc}

000002f0 <block_copy_byte>:
 2f0:	b508      	push	{r3, lr}
 2f2:	f04f 0300 	mov.w	r3, #0

000002f6 <block_copy_byte_loop>:
 2f6:	7803      	ldrb	r3, [r0, #0]
 2f8:	700b      	strb	r3, [r1, #0]
 2fa:	f100 0001 	add.w	r0, r0, #1
 2fe:	f101 0101 	add.w	r1, r1, #1
 302:	3a01      	subs	r2, #1
 304:	d1f7      	bne.n	2f6 <block_copy_byte_loop>
 306:	bd08      	pop	{r3, pc}

00000308 <fill_memory>:
 308:	4288      	cmp	r0, r1
 30a:	d037      	beq.n	37c <fill_memory_exit>
 30c:	f000 0603 	and.w	r6, r0, #3
 310:	2e00      	cmp	r6, #0
 312:	d014      	beq.n	33e <fill_memory_end_start>
 314:	f04f 0504 	mov.w	r5, #4
 318:	eba5 0406 	sub.w	r4, r5, r6
 31c:	f04f 0708 	mov.w	r7, #8
 320:	fb07 f806 	mul.w	r8, r7, r6
 324:	4691      	mov	r9, r2
 326:	fa69 f908 	ror.w	r9, r9, r8

0000032a <fill_memory_spare_bytes_start>:
 32a:	2c00      	cmp	r4, #0
 32c:	d007      	beq.n	33e <fill_memory_end_start>
 32e:	f880 9000 	strb.w	r9, [r0]
 332:	fa69 f907 	ror.w	r9, r9, r7
 336:	f100 0001 	add.w	r0, r0, #1
 33a:	3c01      	subs	r4, #1
 33c:	e7f5      	b.n	32a <fill_memory_spare_bytes_start>

0000033e <fill_memory_end_start>:
 33e:	f04f 0600 	mov.w	r6, #0
 342:	460f      	mov	r7, r1
 344:	1a09      	subs	r1, r1, r0
 346:	4688      	mov	r8, r1
 348:	1109      	asrs	r1, r1, #4
 34a:	4691      	mov	r9, r2
 34c:	4614      	mov	r4, r2
 34e:	4615      	mov	r5, r2
 350:	42b1      	cmp	r1, r6
 352:	d006      	beq.n	362 <fill_memory_spare_bytes_end>

00000354 <fill_memory_loop>:
 354:	bf18      	it	ne
 356:	e8a0 0234 	stmiane.w	r0!, {r2, r4, r5, r9}
 35a:	f106 0601 	add.w	r6, r6, #1
 35e:	42b1      	cmp	r1, r6
 360:	d1f8      	bne.n	354 <fill_memory_loop>

00000362 <fill_memory_spare_bytes_end>:
 362:	f008 080f 	and.w	r8, r8, #15

00000366 <fill_memory_spare_end_loop>:
 366:	f1b8 0f00 	cmp.w	r8, #0
 36a:	d007      	beq.n	37c <fill_memory_exit>
 36c:	7002      	strb	r2, [r0, #0]
 36e:	ea4f 2232 	mov.w	r2, r2, ror #8
 372:	f100 0001 	add.w	r0, r0, #1
 376:	f1b8 0801 	subs.w	r8, r8, #1
 37a:	e7f4      	b.n	366 <fill_memory_spare_end_loop>

0000037c <fill_memory_exit>:
 37c:	4770      	bx	lr

0000037e <NMI_Handler>:
 37e:	e7fe      	b.n	37e <NMI_Handler>

00000380 <HardFault_Handler>:
 380:	e7fe      	b.n	380 <HardFault_Handler>

00000382 <MemManage_Handler>:
 382:	e7fe      	b.n	382 <MemManage_Handler>

00000384 <BusFault_Handler>:
 384:	e7fe      	b.n	384 <BusFault_Handler>

00000386 <UsageFault_Handler>:
 386:	e7fe      	b.n	386 <UsageFault_Handler>

00000388 <SVC_Handler>:
 388:	e7fe      	b.n	388 <SVC_Handler>

0000038a <DebugMon_Handler>:
 38a:	e7fe      	b.n	38a <DebugMon_Handler>

0000038c <PendSV_Handler>:
 38c:	e7fe      	b.n	38c <PendSV_Handler>

0000038e <SysTick_Handler>:
 38e:	e7fe      	b.n	38e <SysTick_Handler>

00000390 <WdogWakeup_IRQHandler>:
 390:	e7fe      	b.n	390 <WdogWakeup_IRQHandler>

00000392 <RTC_Wakeup_IRQHandler>:
 392:	e7fe      	b.n	392 <RTC_Wakeup_IRQHandler>
 394:	e7fe      	b.n	394 <RTC_Wakeup_IRQHandler+0x2>
 396:	e7fe      	b.n	396 <RTC_Wakeup_IRQHandler+0x4>

00000398 <I2C0_IRQHandler>:
 398:	e7fe      	b.n	398 <I2C0_IRQHandler>

0000039a <I2C0_SMBAlert_IRQHandler>:
 39a:	e7fe      	b.n	39a <I2C0_SMBAlert_IRQHandler>

0000039c <I2C0_SMBus_IRQHandler>:
 39c:	e7fe      	b.n	39c <I2C0_SMBus_IRQHandler>

0000039e <I2C1_IRQHandler>:
 39e:	e7fe      	b.n	39e <I2C1_IRQHandler>

000003a0 <I2C1_SMBAlert_IRQHandler>:
 3a0:	e7fe      	b.n	3a0 <I2C1_SMBAlert_IRQHandler>

000003a2 <I2C1_SMBus_IRQHandler>:
 3a2:	e7fe      	b.n	3a2 <I2C1_SMBus_IRQHandler>
 3a4:	e7fe      	b.n	3a4 <I2C1_SMBus_IRQHandler+0x2>
 3a6:	e7fe      	b.n	3a6 <I2C1_SMBus_IRQHandler+0x4>

000003a8 <EthernetMAC_IRQHandler>:
 3a8:	e7fe      	b.n	3a8 <EthernetMAC_IRQHandler>

000003aa <DMA_IRQHandler>:
 3aa:	e7fe      	b.n	3aa <DMA_IRQHandler>

000003ac <Timer1_IRQHandler>:
 3ac:	e7fe      	b.n	3ac <Timer1_IRQHandler>

000003ae <Timer2_IRQHandler>:
 3ae:	e7fe      	b.n	3ae <Timer2_IRQHandler>

000003b0 <CAN_IRQHandler>:
 3b0:	e7fe      	b.n	3b0 <CAN_IRQHandler>

000003b2 <ENVM0_IRQHandler>:
 3b2:	e7fe      	b.n	3b2 <ENVM0_IRQHandler>

000003b4 <ENVM1_IRQHandler>:
 3b4:	e7fe      	b.n	3b4 <ENVM1_IRQHandler>
 3b6:	e7fe      	b.n	3b6 <ENVM1_IRQHandler+0x2>

000003b8 <USB_IRQHandler>:
 3b8:	e7fe      	b.n	3b8 <USB_IRQHandler>

000003ba <USB_DMA_IRQHandler>:
 3ba:	e7fe      	b.n	3ba <USB_DMA_IRQHandler>

000003bc <PLL_Lock_IRQHandler>:
 3bc:	e7fe      	b.n	3bc <PLL_Lock_IRQHandler>

000003be <PLL_LockLost_IRQHandler>:
 3be:	e7fe      	b.n	3be <PLL_LockLost_IRQHandler>

000003c0 <CommSwitchError_IRQHandler>:
 3c0:	e7fe      	b.n	3c0 <CommSwitchError_IRQHandler>

000003c2 <CacheError_IRQHandler>:
 3c2:	e7fe      	b.n	3c2 <CacheError_IRQHandler>

000003c4 <DDR_IRQHandler>:
 3c4:	e7fe      	b.n	3c4 <DDR_IRQHandler>
 3c6:	e7fe      	b.n	3c6 <DDR_IRQHandler+0x2>
 3c8:	e7fe      	b.n	3c8 <DDR_IRQHandler+0x4>

000003ca <ECC_Error_IRQHandler>:
 3ca:	e7fe      	b.n	3ca <ECC_Error_IRQHandler>

000003cc <MDDR_IOCalib_IRQHandler>:
 3cc:	e7fe      	b.n	3cc <MDDR_IOCalib_IRQHandler>

000003ce <FAB_PLL_Lock_IRQHandler>:
 3ce:	e7fe      	b.n	3ce <FAB_PLL_Lock_IRQHandler>

000003d0 <FAB_PLL_LockLost_IRQHandler>:
 3d0:	e7fe      	b.n	3d0 <FAB_PLL_LockLost_IRQHandler>

000003d2 <FIC64_IRQHandler>:
 3d2:	e7fe      	b.n	3d2 <FIC64_IRQHandler>

000003d4 <FabricIrq0_IRQHandler>:
 3d4:	e7fe      	b.n	3d4 <FabricIrq0_IRQHandler>

000003d6 <FabricIrq1_IRQHandler>:
 3d6:	e7fe      	b.n	3d6 <FabricIrq1_IRQHandler>

000003d8 <FabricIrq2_IRQHandler>:
 3d8:	e7fe      	b.n	3d8 <FabricIrq2_IRQHandler>

000003da <FabricIrq3_IRQHandler>:
 3da:	e7fe      	b.n	3da <FabricIrq3_IRQHandler>

000003dc <FabricIrq4_IRQHandler>:
 3dc:	e7fe      	b.n	3dc <FabricIrq4_IRQHandler>

000003de <FabricIrq5_IRQHandler>:
 3de:	e7fe      	b.n	3de <FabricIrq5_IRQHandler>

000003e0 <FabricIrq6_IRQHandler>:
 3e0:	e7fe      	b.n	3e0 <FabricIrq6_IRQHandler>

000003e2 <FabricIrq7_IRQHandler>:
 3e2:	e7fe      	b.n	3e2 <FabricIrq7_IRQHandler>

000003e4 <FabricIrq8_IRQHandler>:
 3e4:	e7fe      	b.n	3e4 <FabricIrq8_IRQHandler>

000003e6 <FabricIrq9_IRQHandler>:
 3e6:	e7fe      	b.n	3e6 <FabricIrq9_IRQHandler>

000003e8 <FabricIrq10_IRQHandler>:
 3e8:	e7fe      	b.n	3e8 <FabricIrq10_IRQHandler>

000003ea <FabricIrq11_IRQHandler>:
 3ea:	e7fe      	b.n	3ea <FabricIrq11_IRQHandler>

000003ec <FabricIrq12_IRQHandler>:
 3ec:	e7fe      	b.n	3ec <FabricIrq12_IRQHandler>

000003ee <FabricIrq13_IRQHandler>:
 3ee:	e7fe      	b.n	3ee <FabricIrq13_IRQHandler>

000003f0 <FabricIrq14_IRQHandler>:
 3f0:	e7fe      	b.n	3f0 <FabricIrq14_IRQHandler>

000003f2 <FabricIrq15_IRQHandler>:
 3f2:	e7fe      	b.n	3f2 <FabricIrq15_IRQHandler>

000003f4 <GPIO0_IRQHandler>:
 3f4:	e7fe      	b.n	3f4 <GPIO0_IRQHandler>

000003f6 <GPIO1_IRQHandler>:
 3f6:	e7fe      	b.n	3f6 <GPIO1_IRQHandler>

000003f8 <GPIO2_IRQHandler>:
 3f8:	e7fe      	b.n	3f8 <GPIO2_IRQHandler>

000003fa <GPIO3_IRQHandler>:
 3fa:	e7fe      	b.n	3fa <GPIO3_IRQHandler>

000003fc <GPIO4_IRQHandler>:
 3fc:	e7fe      	b.n	3fc <GPIO4_IRQHandler>

000003fe <GPIO5_IRQHandler>:
 3fe:	e7fe      	b.n	3fe <GPIO5_IRQHandler>

00000400 <GPIO6_IRQHandler>:
 400:	e7fe      	b.n	400 <GPIO6_IRQHandler>

00000402 <GPIO7_IRQHandler>:
 402:	e7fe      	b.n	402 <GPIO7_IRQHandler>

00000404 <GPIO8_IRQHandler>:
 404:	e7fe      	b.n	404 <GPIO8_IRQHandler>

00000406 <GPIO9_IRQHandler>:
 406:	e7fe      	b.n	406 <GPIO9_IRQHandler>

00000408 <GPIO10_IRQHandler>:
 408:	e7fe      	b.n	408 <GPIO10_IRQHandler>

0000040a <GPIO11_IRQHandler>:
 40a:	e7fe      	b.n	40a <GPIO11_IRQHandler>

0000040c <GPIO12_IRQHandler>:
 40c:	e7fe      	b.n	40c <GPIO12_IRQHandler>

0000040e <GPIO13_IRQHandler>:
 40e:	e7fe      	b.n	40e <GPIO13_IRQHandler>

00000410 <GPIO14_IRQHandler>:
 410:	e7fe      	b.n	410 <GPIO14_IRQHandler>

00000412 <GPIO15_IRQHandler>:
 412:	e7fe      	b.n	412 <GPIO15_IRQHandler>

00000414 <GPIO16_IRQHandler>:
 414:	e7fe      	b.n	414 <GPIO16_IRQHandler>

00000416 <GPIO17_IRQHandler>:
 416:	e7fe      	b.n	416 <GPIO17_IRQHandler>

00000418 <GPIO18_IRQHandler>:
 418:	e7fe      	b.n	418 <GPIO18_IRQHandler>

0000041a <GPIO19_IRQHandler>:
 41a:	e7fe      	b.n	41a <GPIO19_IRQHandler>

0000041c <GPIO20_IRQHandler>:
 41c:	e7fe      	b.n	41c <GPIO20_IRQHandler>

0000041e <GPIO21_IRQHandler>:
 41e:	e7fe      	b.n	41e <GPIO21_IRQHandler>

00000420 <GPIO22_IRQHandler>:
 420:	e7fe      	b.n	420 <GPIO22_IRQHandler>

00000422 <GPIO23_IRQHandler>:
 422:	e7fe      	b.n	422 <GPIO23_IRQHandler>

00000424 <GPIO24_IRQHandler>:
 424:	e7fe      	b.n	424 <GPIO24_IRQHandler>

00000426 <GPIO25_IRQHandler>:
 426:	e7fe      	b.n	426 <GPIO25_IRQHandler>

00000428 <GPIO26_IRQHandler>:
 428:	e7fe      	b.n	428 <GPIO26_IRQHandler>

0000042a <GPIO27_IRQHandler>:
 42a:	e7fe      	b.n	42a <GPIO27_IRQHandler>

0000042c <GPIO28_IRQHandler>:
 42c:	e7fe      	b.n	42c <GPIO28_IRQHandler>

0000042e <GPIO29_IRQHandler>:
 42e:	e7fe      	b.n	42e <GPIO29_IRQHandler>

00000430 <GPIO30_IRQHandler>:
 430:	e7fe      	b.n	430 <GPIO30_IRQHandler>

00000432 <GPIO31_IRQHandler>:
 432:	e7fe      	b.n	432 <GPIO31_IRQHandler>

00000434 <mscc_post_hw_cfg_init>:
 434:	4770      	bx	lr

00000436 <RAM_INIT_PATTERN>:
 436:	0000      	.short	0x0000
	...

0000043a <HEAP_INIT_PATTERN>:
 43a:	a2a2      	.short	0xa2a2
 43c:	a2a2      	.short	0xa2a2

0000043e <SF2_ESRAM_CR>:
 43e:	8000      	.short	0x8000
 440:	4003      	.short	0x4003

00000442 <SF2_DDR_CR>:
 442:	8008      	.short	0x8008
 444:	4003      	.short	0x4003

00000446 <SF2_ENVM_REMAP_CR>:
 446:	8010      	.short	0x8010
 448:	4003      	.short	0x4003

0000044a <SF2_DDRB_NB_SIZE>:
 44a:	8030      	.short	0x8030
 44c:	4003      	.short	0x4003

0000044e <SF2_DDRB_CR>:
 44e:	8034      	.short	0x8034
 450:	4003      	.short	0x4003

00000452 <SF2_EDAC_CR>:
 452:	8038      	.short	0x8038
 454:	4003      	.short	0x4003

00000456 <SF2_MDDR_MODE_CR>:
 456:	0818      	.short	0x0818
 458:	00004002 	.word	0x00004002
 45c:	2000f000 	.word	0x2000f000
 460:	20010000 	.word	0x20010000
 464:	000004c1 	.word	0x000004c1
	...
 470:	00000001 	.word	0x00000001
 474:	00000001 	.word	0x00000001
 478:	60000000 	.word	0x60000000
 47c:	00000000 	.word	0x00000000
 480:	00000190 	.word	0x00000190
 484:	60000a60 	.word	0x60000a60
 488:	00000a60 	.word	0x00000a60
 48c:	00009fa0 	.word	0x00009fa0
 490:	60009fa0 	.word	0x60009fa0
 494:	20000000 	.word	0x20000000
 498:	20000130 	.word	0x20000130
 49c:	20000130 	.word	0x20000130
 4a0:	20000340 	.word	0x20000340
 4a4:	20000340 	.word	0x20000340
 4a8:	2000f000 	.word	0x2000f000
 4ac:	00009b51 	.word	0x00009b51
 4b0:	00000bbd 	.word	0x00000bbd
 4b4:	f3af 8000 	nop.w
 4b8:	f3af 8000 	nop.w
 4bc:	f3af 8000 	nop.w

000004c0 <SystemInit>:

/***************************************************************************//**
 * See system_m2sxxx.h for details.
 */
void SystemInit(void)
{
 4c0:	b580      	push	{r7, lr}
 4c2:	b082      	sub	sp, #8
 4c4:	af00      	add	r7, sp, #0
     */
#if (MSS_SYS_FACC_INIT_BY_CORTEX == 1)
    complete_clock_config();
#endif

    silicon_workarounds();
 4c6:	f000 fa0b 	bl	8e0 <silicon_workarounds>
    /*--------------------------------------------------------------------------
     * Set STKALIGN to ensure exception stacking starts on 8 bytes address
     * boundary. This ensures compliance with the "Procedure Call Standards for
     * the ARM Architecture" (AAPCS).
     */
    SCB->CCR |= SCB_CCR_STKALIGN_Msk;
 4ca:	f64e 5300 	movw	r3, #60672	; 0xed00
 4ce:	f2ce 0300 	movt	r3, #57344	; 0xe000
 4d2:	f64e 5200 	movw	r2, #60672	; 0xed00
 4d6:	f2ce 0200 	movt	r2, #57344	; 0xe000
 4da:	6952      	ldr	r2, [r2, #20]
 4dc:	f442 7200 	orr.w	r2, r2, #512	; 0x200
 4e0:	615a      	str	r2, [r3, #20]

    /*--------------------------------------------------------------------------
     * MDDR configuration
     */
#if MSS_SYS_MDDR_CONFIG_BY_CORTEX
    if(0u == SYSREG->DDR_CR)
 4e2:	f248 0300 	movw	r3, #32768	; 0x8000
 4e6:	f2c4 0303 	movt	r3, #16387	; 0x4003
 4ea:	689b      	ldr	r3, [r3, #8]
 4ec:	2b00      	cmp	r3, #0
 4ee:	d10b      	bne.n	508 <SystemInit+0x48>
         * to address 0x00000000. If MDDR is remapped to 0x00000000 then we are
         * probably executing this code from MDDR in a debugging session and
         * attempting to reconfigure the MDDR memory controller will cause the
         * Cortex-M3 to crash.
         */
        config_ddr_subsys(&g_m2s_mddr_subsys_config, &g_m2s_mddr_addr->core);
 4f0:	f640 1344 	movw	r3, #2372	; 0x944
 4f4:	f2c0 0300 	movt	r3, #0
 4f8:	681b      	ldr	r3, [r3, #0]
 4fa:	f640 1048 	movw	r0, #2376	; 0x948
 4fe:	f2c0 0000 	movt	r0, #0
 502:	4619      	mov	r1, r3
 504:	f000 f94c 	bl	7a0 <config_ddr_subsys>
#endif

    /*--------------------------------------------------------------------------
     * Call user defined configuration function.
     */
    mscc_post_hw_cfg_init();
 508:	f7ff ff94 	bl	434 <mscc_post_hw_cfg_init>
     * do this here because this signal is only deasserted by the System
     * Controller on a power-on reset. Other types of reset such as a watchdog
     * reset would result in the FPGA fabric being held in reset and getting
     * stuck waiting for the CoreSF2Config INIT_DONE to become asserted.
     */
    SYSREG->SOFT_RST_CR &= ~SYSREG_FPGA_SOFTRESET_MASK;
 50c:	f248 0300 	movw	r3, #32768	; 0x8000
 510:	f2c4 0303 	movt	r3, #16387	; 0x4003
 514:	f248 0200 	movw	r2, #32768	; 0x8000
 518:	f2c4 0203 	movt	r2, #16387	; 0x4003
 51c:	6c92      	ldr	r2, [r2, #72]	; 0x48
 51e:	f422 3280 	bic.w	r2, r2, #65536	; 0x10000
 522:	649a      	str	r2, [r3, #72]	; 0x48

    /*
     * Signal to CoreSF2Reset that peripheral configuration registers have been
     * written.
     */
    CORE_SF2_CFG->CONFIG_DONE |= (CONFIG_1_DONE | CONFIG_2_DONE);
 524:	f242 0300 	movw	r3, #8192	; 0x2000
 528:	f2c4 0302 	movt	r3, #16386	; 0x4002
 52c:	f242 0200 	movw	r2, #8192	; 0x2000
 530:	f2c4 0202 	movt	r2, #16386	; 0x4002
 534:	6812      	ldr	r2, [r2, #0]
 536:	f042 0203 	orr.w	r2, r2, #3
 53a:	601a      	str	r2, [r3, #0]

    /* Wait for INIT_DONE from CoreSF2Reset. */
    do
    {
        init_done = CORE_SF2_CFG->INIT_DONE & INIT_DONE_MASK;
 53c:	f242 0300 	movw	r3, #8192	; 0x2000
 540:	f2c4 0302 	movt	r3, #16386	; 0x4002
 544:	685b      	ldr	r3, [r3, #4]
 546:	f003 0301 	and.w	r3, r3, #1
 54a:	607b      	str	r3, [r7, #4]
    } while (0u == init_done);
 54c:	687b      	ldr	r3, [r7, #4]
 54e:	2b00      	cmp	r3, #0
 550:	d0f4      	beq.n	53c <SystemInit+0x7c>
#endif
}
 552:	f107 0708 	add.w	r7, r7, #8
 556:	46bd      	mov	sp, r7
 558:	bd80      	pop	{r7, pc}
 55a:	bf00      	nop

0000055c <SystemCoreClockUpdate>:
#define FREQ_1MHZ    1000000u
#define FREQ_25MHZ   25000000u
#define FREQ_50MHZ   50000000u

void SystemCoreClockUpdate(void)
{
 55c:	b580      	push	{r7, lr}
 55e:	b088      	sub	sp, #32
 560:	af00      	add	r7, sp, #0
    uint32_t controller_pll_init;
    uint32_t clk_src;

    controller_pll_init = SYSREG->MSSDDR_FACC1_CR & CONTROLLER_PLL_INIT_MASK;
 562:	f248 0300 	movw	r3, #32768	; 0x8000
 566:	f2c4 0303 	movt	r3, #16387	; 0x4003
 56a:	f8d3 3098 	ldr.w	r3, [r3, #152]	; 0x98
 56e:	f003 6380 	and.w	r3, r3, #67108864	; 0x4000000
 572:	60fb      	str	r3, [r7, #12]

    if(0u == controller_pll_init)
 574:	68fb      	ldr	r3, [r7, #12]
 576:	2b00      	cmp	r3, #0
 578:	f040 808b 	bne.w	692 <SystemCoreClockUpdate+0x136>
    {
        /* Normal operations. */
        uint32_t global_mux_sel;

        global_mux_sel = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK;
 57c:	f248 0300 	movw	r3, #32768	; 0x8000
 580:	f2c4 0303 	movt	r3, #16387	; 0x4003
 584:	f8d3 3098 	ldr.w	r3, [r3, #152]	; 0x98
 588:	f403 5380 	and.w	r3, r3, #4096	; 0x1000
 58c:	617b      	str	r3, [r7, #20]
        if(0u == global_mux_sel)
 58e:	697b      	ldr	r3, [r7, #20]
 590:	2b00      	cmp	r3, #0
 592:	d13f      	bne.n	614 <SystemCoreClockUpdate+0xb8>
        {
            /* MSS clocked from MSS PLL. Use Libero flow defines. */
            SystemCoreClock = MSS_SYS_M3_CLK_FREQ;
 594:	f240 0310 	movw	r3, #16
 598:	f2c2 0300 	movt	r3, #8192	; 0x2000
 59c:	f24b 4200 	movw	r2, #46080	; 0xb400
 5a0:	f2c0 42c4 	movt	r2, #1220	; 0x4c4
 5a4:	601a      	str	r2, [r3, #0]
            g_FrequencyPCLK0 = MSS_SYS_APB_0_CLK_FREQ;
 5a6:	f240 0314 	movw	r3, #20
 5aa:	f2c2 0300 	movt	r3, #8192	; 0x2000
 5ae:	f24b 4200 	movw	r2, #46080	; 0xb400
 5b2:	f2c0 42c4 	movt	r2, #1220	; 0x4c4
 5b6:	601a      	str	r2, [r3, #0]
            g_FrequencyPCLK1 = MSS_SYS_APB_1_CLK_FREQ;
 5b8:	f240 0318 	movw	r3, #24
 5bc:	f2c2 0300 	movt	r3, #8192	; 0x2000
 5c0:	f24b 4200 	movw	r2, #46080	; 0xb400
 5c4:	f2c0 42c4 	movt	r2, #1220	; 0x4c4
 5c8:	601a      	str	r2, [r3, #0]
            g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
 5ca:	f240 031c 	movw	r3, #28
 5ce:	f2c2 0300 	movt	r3, #8192	; 0x2000
 5d2:	f642 5200 	movw	r2, #11520	; 0x2d00
 5d6:	f2c0 1231 	movt	r2, #305	; 0x131
 5da:	601a      	str	r2, [r3, #0]
            g_FrequencyFIC0 = MSS_SYS_FIC_0_CLK_FREQ;
 5dc:	f240 0320 	movw	r3, #32
 5e0:	f2c2 0300 	movt	r3, #8192	; 0x2000
 5e4:	f24b 4200 	movw	r2, #46080	; 0xb400
 5e8:	f2c0 42c4 	movt	r2, #1220	; 0x4c4
 5ec:	601a      	str	r2, [r3, #0]
            g_FrequencyFIC1 = MSS_SYS_FIC_1_CLK_FREQ;
 5ee:	f240 0324 	movw	r3, #36	; 0x24
 5f2:	f2c2 0300 	movt	r3, #8192	; 0x2000
 5f6:	f24b 4200 	movw	r2, #46080	; 0xb400
 5fa:	f2c0 42c4 	movt	r2, #1220	; 0x4c4
 5fe:	601a      	str	r2, [r3, #0]
            g_FrequencyFIC64 = MSS_SYS_FIC64_CLK_FREQ;
 600:	f240 0328 	movw	r3, #40	; 0x28
 604:	f2c2 0300 	movt	r3, #8192	; 0x2000
 608:	f24b 4200 	movw	r2, #46080	; 0xb400
 60c:	f2c0 42c4 	movt	r2, #1220	; 0x4c4
 610:	601a      	str	r2, [r3, #0]
                break;

                case CCC2ASCI_CLK_SRC:
                    /* Fall through. */
                default:
                    set_clock_frequency_globals(FREQ_1MHZ);
 612:	e045      	b.n	6a0 <SystemCoreClockUpdate+0x144>
                                                   RCOSC_25_50MHZ_CLK_SRC,
                                                   CLK_XTAL_CLK_SRC,
                                                   RCOSC_1_MHZ_CLK_SRC,
                                                   RCOSC_1_MHZ_CLK_SRC,
                                                   CCC2ASCI_CLK_SRC,
                                                   CCC2ASCI_CLK_SRC };
 614:	f649 7338 	movw	r3, #40760	; 0x9f38
 618:	f2c0 0300 	movt	r3, #0
 61c:	f107 0204 	add.w	r2, r7, #4
 620:	e893 0003 	ldmia.w	r3, {r0, r1}
 624:	e882 0003 	stmia.w	r2, {r0, r1}

            uint32_t standby_sel;
            uint8_t clock_source;

            standby_sel = (SYSREG->MSSDDR_FACC2_CR >> FACC_STANDBY_SHIFT) & FACC_STANDBY_SEL_MASK;
 628:	f248 0300 	movw	r3, #32768	; 0x8000
 62c:	f2c4 0303 	movt	r3, #16387	; 0x4003
 630:	f8d3 309c 	ldr.w	r3, [r3, #156]	; 0x9c
 634:	ea4f 1393 	mov.w	r3, r3, lsr #6
 638:	f003 0307 	and.w	r3, r3, #7
 63c:	61bb      	str	r3, [r7, #24]
            clock_source = standby_clock_lut[standby_sel];
 63e:	69bb      	ldr	r3, [r7, #24]
 640:	f107 0220 	add.w	r2, r7, #32
 644:	4413      	add	r3, r2
 646:	f813 3c1c 	ldrb.w	r3, [r3, #-28]
 64a:	77fb      	strb	r3, [r7, #31]
            switch(clock_source)
 64c:	7ffb      	ldrb	r3, [r7, #31]
 64e:	2b01      	cmp	r3, #1
 650:	d00b      	beq.n	66a <SystemCoreClockUpdate+0x10e>
 652:	2b02      	cmp	r3, #2
 654:	d00e      	beq.n	674 <SystemCoreClockUpdate+0x118>
 656:	2b00      	cmp	r3, #0
 658:	d114      	bne.n	684 <SystemCoreClockUpdate+0x128>
            {
                case RCOSC_25_50MHZ_CLK_SRC:
                    clk_src = get_rcosc_25_50mhz_frequency();
 65a:	f000 f825 	bl	6a8 <get_rcosc_25_50mhz_frequency>
 65e:	4603      	mov	r3, r0
 660:	613b      	str	r3, [r7, #16]
                    set_clock_frequency_globals(clk_src);
 662:	6938      	ldr	r0, [r7, #16]
 664:	f000 f842 	bl	6ec <set_clock_frequency_globals>
                break;
 668:	e01a      	b.n	6a0 <SystemCoreClockUpdate+0x144>

                case CLK_XTAL_CLK_SRC:
                    set_clock_frequency_globals(FREQ_32KHZ);
 66a:	f44f 4000 	mov.w	r0, #32768	; 0x8000
 66e:	f000 f83d 	bl	6ec <set_clock_frequency_globals>
                break;
 672:	e015      	b.n	6a0 <SystemCoreClockUpdate+0x144>

                case RCOSC_1_MHZ_CLK_SRC:
                    set_clock_frequency_globals(FREQ_1MHZ);
 674:	f244 2040 	movw	r0, #16960	; 0x4240
 678:	f2c0 000f 	movt	r0, #15
 67c:	f000 f836 	bl	6ec <set_clock_frequency_globals>
                break;
 680:	bf00      	nop
 682:	e00d      	b.n	6a0 <SystemCoreClockUpdate+0x144>

                case CCC2ASCI_CLK_SRC:
                    /* Fall through. */
                default:
                    set_clock_frequency_globals(FREQ_1MHZ);
 684:	f244 2040 	movw	r0, #16960	; 0x4240
 688:	f2c0 000f 	movt	r0, #15
 68c:	f000 f82e 	bl	6ec <set_clock_frequency_globals>
 690:	e006      	b.n	6a0 <SystemCoreClockUpdate+0x144>
        }
    }
    else
    {
        /* PLL initialization mode. Running from 25/50MHZ RC oscillator. */
        clk_src = get_rcosc_25_50mhz_frequency();
 692:	f000 f809 	bl	6a8 <get_rcosc_25_50mhz_frequency>
 696:	4603      	mov	r3, r0
 698:	613b      	str	r3, [r7, #16]
        set_clock_frequency_globals(clk_src);
 69a:	6938      	ldr	r0, [r7, #16]
 69c:	f000 f826 	bl	6ec <set_clock_frequency_globals>
    }
}
 6a0:	f107 0720 	add.w	r7, r7, #32
 6a4:	46bd      	mov	sp, r7
 6a6:	bd80      	pop	{r7, pc}

000006a8 <get_rcosc_25_50mhz_frequency>:

/***************************************************************************//**
 * Find out frequency generated by the 25_50mhz RC osciallator.
 */
static uint32_t get_rcosc_25_50mhz_frequency(void)
{
 6a8:	b480      	push	{r7}
 6aa:	b083      	sub	sp, #12
 6ac:	af00      	add	r7, sp, #0
    uint32_t rcosc_div2;
    uint32_t rcosc_frequency;

    rcosc_div2 = SYSREG->MSSDDR_PLL_STATUS & RCOSC_DIV2_MASK;
 6ae:	f248 0300 	movw	r3, #32768	; 0x8000
 6b2:	f2c4 0303 	movt	r3, #16387	; 0x4003
 6b6:	f8d3 3150 	ldr.w	r3, [r3, #336]	; 0x150
 6ba:	f003 0304 	and.w	r3, r3, #4
 6be:	603b      	str	r3, [r7, #0]
    if(0u == rcosc_div2)
 6c0:	683b      	ldr	r3, [r7, #0]
 6c2:	2b00      	cmp	r3, #0
 6c4:	d105      	bne.n	6d2 <get_rcosc_25_50mhz_frequency+0x2a>
    {
        /* 25_50mhz oscillator is configured for 25 MHz operations. */
        rcosc_frequency = FREQ_25MHZ;
 6c6:	f647 0340 	movw	r3, #30784	; 0x7840
 6ca:	f2c0 137d 	movt	r3, #381	; 0x17d
 6ce:	607b      	str	r3, [r7, #4]
 6d0:	e004      	b.n	6dc <get_rcosc_25_50mhz_frequency+0x34>
    }
    else
    {
        /* 25_50mhz oscillator is configured for 50 MHz operations. */
        rcosc_frequency = FREQ_50MHZ;
 6d2:	f24f 0380 	movw	r3, #61568	; 0xf080
 6d6:	f2c0 23fa 	movt	r3, #762	; 0x2fa
 6da:	607b      	str	r3, [r7, #4]
    }

    return rcosc_frequency;
 6dc:	687b      	ldr	r3, [r7, #4]
}
 6de:	4618      	mov	r0, r3
 6e0:	f107 070c 	add.w	r7, r7, #12
 6e4:	46bd      	mov	sp, r7
 6e6:	bc80      	pop	{r7}
 6e8:	4770      	bx	lr
 6ea:	bf00      	nop

000006ec <set_clock_frequency_globals>:
        - g_FrequencyFIC0
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
 6ec:	b480      	push	{r7}
 6ee:	b083      	sub	sp, #12
 6f0:	af00      	add	r7, sp, #0
 6f2:	6078      	str	r0, [r7, #4]
    SystemCoreClock = standby_clk;
 6f4:	f240 0310 	movw	r3, #16
 6f8:	f2c2 0300 	movt	r3, #8192	; 0x2000
 6fc:	687a      	ldr	r2, [r7, #4]
 6fe:	601a      	str	r2, [r3, #0]
    g_FrequencyPCLK0 = standby_clk;
 700:	f240 0314 	movw	r3, #20
 704:	f2c2 0300 	movt	r3, #8192	; 0x2000
 708:	687a      	ldr	r2, [r7, #4]
 70a:	601a      	str	r2, [r3, #0]
    g_FrequencyPCLK1 = standby_clk;
 70c:	f240 0318 	movw	r3, #24
 710:	f2c2 0300 	movt	r3, #8192	; 0x2000
 714:	687a      	ldr	r2, [r7, #4]
 716:	601a      	str	r2, [r3, #0]
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
 718:	f240 031c 	movw	r3, #28
 71c:	f2c2 0300 	movt	r3, #8192	; 0x2000
 720:	f642 5200 	movw	r2, #11520	; 0x2d00
 724:	f2c0 1231 	movt	r2, #305	; 0x131
 728:	601a      	str	r2, [r3, #0]
    g_FrequencyFIC0 = standby_clk;
 72a:	f240 0320 	movw	r3, #32
 72e:	f2c2 0300 	movt	r3, #8192	; 0x2000
 732:	687a      	ldr	r2, [r7, #4]
 734:	601a      	str	r2, [r3, #0]
    g_FrequencyFIC1 = standby_clk;
 736:	f240 0324 	movw	r3, #36	; 0x24
 73a:	f2c2 0300 	movt	r3, #8192	; 0x2000
 73e:	687a      	ldr	r2, [r7, #4]
 740:	601a      	str	r2, [r3, #0]
    g_FrequencyFIC64 = standby_clk;
 742:	f240 0328 	movw	r3, #40	; 0x28
 746:	f2c2 0300 	movt	r3, #8192	; 0x2000
 74a:	687a      	ldr	r2, [r7, #4]
 74c:	601a      	str	r2, [r3, #0]
}
 74e:	f107 070c 	add.w	r7, r7, #12
 752:	46bd      	mov	sp, r7
 754:	bc80      	pop	{r7}
 756:	4770      	bx	lr

00000758 <copy_cfg16_to_regs>:
(
    volatile uint32_t * p_regs,
    const uint16_t * p_cfg,
    uint32_t nb_16bit_words
)
{
 758:	b480      	push	{r7}
 75a:	b087      	sub	sp, #28
 75c:	af00      	add	r7, sp, #0
 75e:	60f8      	str	r0, [r7, #12]
 760:	60b9      	str	r1, [r7, #8]
 762:	607a      	str	r2, [r7, #4]
    uint32_t inc;

    for(inc = 0u; inc < nb_16bit_words; ++inc)
 764:	f04f 0300 	mov.w	r3, #0
 768:	617b      	str	r3, [r7, #20]
 76a:	e00f      	b.n	78c <copy_cfg16_to_regs+0x34>
    {
        p_regs[inc] = p_cfg[inc];
 76c:	697b      	ldr	r3, [r7, #20]
 76e:	ea4f 0283 	mov.w	r2, r3, lsl #2
 772:	68fb      	ldr	r3, [r7, #12]
 774:	4413      	add	r3, r2
 776:	697a      	ldr	r2, [r7, #20]
 778:	ea4f 0142 	mov.w	r1, r2, lsl #1
 77c:	68ba      	ldr	r2, [r7, #8]
 77e:	440a      	add	r2, r1
 780:	8812      	ldrh	r2, [r2, #0]
 782:	601a      	str	r2, [r3, #0]
    uint32_t nb_16bit_words
)
{
    uint32_t inc;

    for(inc = 0u; inc < nb_16bit_words; ++inc)
 784:	697b      	ldr	r3, [r7, #20]
 786:	f103 0301 	add.w	r3, r3, #1
 78a:	617b      	str	r3, [r7, #20]
 78c:	697a      	ldr	r2, [r7, #20]
 78e:	687b      	ldr	r3, [r7, #4]
 790:	429a      	cmp	r2, r3
 792:	d3eb      	bcc.n	76c <copy_cfg16_to_regs+0x14>
    {
        p_regs[inc] = p_cfg[inc];
    }
}
 794:	f107 071c 	add.w	r7, r7, #28
 798:	46bd      	mov	sp, r7
 79a:	bc80      	pop	{r7}
 79c:	4770      	bx	lr
 79e:	bf00      	nop

000007a0 <config_ddr_subsys>:
static void config_ddr_subsys
(
    const ddr_subsys_cfg_t * p_ddr_subsys_cfg,
    DDRCore_TypeDef * p_ddr_subsys_regs
)
{
 7a0:	b580      	push	{r7, lr}
 7a2:	b084      	sub	sp, #16
 7a4:	af00      	add	r7, sp, #0
 7a6:	6078      	str	r0, [r7, #4]
 7a8:	6039      	str	r1, [r7, #0]
    const uint16_t * p_cfg;

    /*--------------------------------------------------------------------------
     * Configure DDR controller part of the MDDR subsystem.
     */
    p_cfg = &p_ddr_subsys_cfg->ddrc.DYN_SOFT_RESET_CR;
 7aa:	687b      	ldr	r3, [r7, #4]
 7ac:	60fb      	str	r3, [r7, #12]
    p_regs = &p_ddr_subsys_regs->ddrc.DYN_SOFT_RESET_CR;
 7ae:	683b      	ldr	r3, [r7, #0]
 7b0:	60bb      	str	r3, [r7, #8]

    copy_cfg16_to_regs(p_regs, p_cfg, NB_OF_DDRC_REGS_TO_CONFIG);
 7b2:	68b8      	ldr	r0, [r7, #8]
 7b4:	68f9      	ldr	r1, [r7, #12]
 7b6:	f04f 0239 	mov.w	r2, #57	; 0x39
 7ba:	f7ff ffcd 	bl	758 <copy_cfg16_to_regs>

    /*--------------------------------------------------------------------------
     * Configure DDR PHY.
     */
    p_cfg = &p_ddr_subsys_cfg->phy.LOOPBACK_TEST_CR;
 7be:	687b      	ldr	r3, [r7, #4]
 7c0:	f103 0372 	add.w	r3, r3, #114	; 0x72
 7c4:	60fb      	str	r3, [r7, #12]
    p_regs = &p_ddr_subsys_regs->phy.LOOPBACK_TEST_CR;
 7c6:	683b      	ldr	r3, [r7, #0]
 7c8:	f503 7307 	add.w	r3, r3, #540	; 0x21c
 7cc:	60bb      	str	r3, [r7, #8]

    copy_cfg16_to_regs(p_regs, p_cfg, NB_OF_DDR_PHY_REGS_TO_CONFIG);
 7ce:	68b8      	ldr	r0, [r7, #8]
 7d0:	68f9      	ldr	r1, [r7, #12]
 7d2:	f04f 0241 	mov.w	r2, #65	; 0x41
 7d6:	f7ff ffbf 	bl	758 <copy_cfg16_to_regs>

    /*--------------------------------------------------------------------------
     * Configure DDR FIC.
     */
    p_ddr_subsys_regs->fic.NB_ADDR_CR = p_ddr_subsys_cfg->fic.NB_ADDR_CR;
 7da:	687b      	ldr	r3, [r7, #4]
 7dc:	f8b3 30f4 	ldrh.w	r3, [r3, #244]	; 0xf4
 7e0:	461a      	mov	r2, r3
 7e2:	683b      	ldr	r3, [r7, #0]
 7e4:	f8c3 2400 	str.w	r2, [r3, #1024]	; 0x400
    p_ddr_subsys_regs->fic.NBRWB_SIZE_CR = p_ddr_subsys_cfg->fic.NBRWB_SIZE_CR;
 7e8:	687b      	ldr	r3, [r7, #4]
 7ea:	f8b3 30f6 	ldrh.w	r3, [r3, #246]	; 0xf6
 7ee:	461a      	mov	r2, r3
 7f0:	683b      	ldr	r3, [r7, #0]
 7f2:	f8c3 2404 	str.w	r2, [r3, #1028]	; 0x404
    p_ddr_subsys_regs->fic.WB_TIMEOUT_CR = p_ddr_subsys_cfg->fic.WB_TIMEOUT_CR;
 7f6:	687b      	ldr	r3, [r7, #4]
 7f8:	f8b3 30f8 	ldrh.w	r3, [r3, #248]	; 0xf8
 7fc:	461a      	mov	r2, r3
 7fe:	683b      	ldr	r3, [r7, #0]
 800:	f8c3 2408 	str.w	r2, [r3, #1032]	; 0x408
    p_ddr_subsys_regs->fic.HPD_SW_RW_EN_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_EN_CR;
 804:	687b      	ldr	r3, [r7, #4]
 806:	f8b3 30fa 	ldrh.w	r3, [r3, #250]	; 0xfa
 80a:	461a      	mov	r2, r3
 80c:	683b      	ldr	r3, [r7, #0]
 80e:	f8c3 240c 	str.w	r2, [r3, #1036]	; 0x40c
    p_ddr_subsys_regs->fic.HPD_SW_RW_INVAL_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_INVAL_CR;
 812:	687b      	ldr	r3, [r7, #4]
 814:	f8b3 30fc 	ldrh.w	r3, [r3, #252]	; 0xfc
 818:	461a      	mov	r2, r3
 81a:	683b      	ldr	r3, [r7, #0]
 81c:	f8c3 2410 	str.w	r2, [r3, #1040]	; 0x410
    p_ddr_subsys_regs->fic.SW_WR_ERCLR_CR = p_ddr_subsys_cfg->fic.SW_WR_ERCLR_CR;
 820:	687b      	ldr	r3, [r7, #4]
 822:	f8b3 30fe 	ldrh.w	r3, [r3, #254]	; 0xfe
 826:	461a      	mov	r2, r3
 828:	683b      	ldr	r3, [r7, #0]
 82a:	f8c3 2414 	str.w	r2, [r3, #1044]	; 0x414
    p_ddr_subsys_regs->fic.ERR_INT_ENABLE_CR = p_ddr_subsys_cfg->fic.ERR_INT_ENABLE_CR;
 82e:	687b      	ldr	r3, [r7, #4]
 830:	f8b3 3100 	ldrh.w	r3, [r3, #256]	; 0x100
 834:	461a      	mov	r2, r3
 836:	683b      	ldr	r3, [r7, #0]
 838:	f8c3 2418 	str.w	r2, [r3, #1048]	; 0x418
    p_ddr_subsys_regs->fic.NUM_AHB_MASTERS_CR = p_ddr_subsys_cfg->fic.NUM_AHB_MASTERS_CR;
 83c:	687b      	ldr	r3, [r7, #4]
 83e:	f8b3 3102 	ldrh.w	r3, [r3, #258]	; 0x102
 842:	461a      	mov	r2, r3
 844:	683b      	ldr	r3, [r7, #0]
 846:	f8c3 241c 	str.w	r2, [r3, #1052]	; 0x41c
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[0] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_1_CR;
 84a:	687b      	ldr	r3, [r7, #4]
 84c:	f8b3 3104 	ldrh.w	r3, [r3, #260]	; 0x104
 850:	461a      	mov	r2, r3
 852:	683b      	ldr	r3, [r7, #0]
 854:	f8c3 2440 	str.w	r2, [r3, #1088]	; 0x440
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[1] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_2_CR;
 858:	687b      	ldr	r3, [r7, #4]
 85a:	f8b3 3106 	ldrh.w	r3, [r3, #262]	; 0x106
 85e:	461a      	mov	r2, r3
 860:	683b      	ldr	r3, [r7, #0]
 862:	f8c3 2444 	str.w	r2, [r3, #1092]	; 0x444
    p_ddr_subsys_regs->fic.LOCK_TIMEOUT_EN_CR = p_ddr_subsys_cfg->fic.LOCK_TIMEOUT_EN_CR;
 866:	687b      	ldr	r3, [r7, #4]
 868:	f8b3 3108 	ldrh.w	r3, [r3, #264]	; 0x108
 86c:	461a      	mov	r2, r3
 86e:	683b      	ldr	r3, [r7, #0]
 870:	f8c3 2448 	str.w	r2, [r3, #1096]	; 0x448

    /*--------------------------------------------------------------------------
     * Enable DDR.
     */
    p_ddr_subsys_regs->ddrc.DYN_SOFT_RESET_CR = 0x01u;
 874:	683b      	ldr	r3, [r7, #0]
 876:	f04f 0201 	mov.w	r2, #1
 87a:	601a      	str	r2, [r3, #0]

    while(0x0000u == p_ddr_subsys_regs->ddrc.DDRC_SR)
 87c:	683b      	ldr	r3, [r7, #0]
 87e:	f8d3 30e4 	ldr.w	r3, [r3, #228]	; 0xe4
 882:	2b00      	cmp	r3, #0
 884:	d0fa      	beq.n	87c <config_ddr_subsys+0xdc>
    {
        ;
    }
}
 886:	f107 0710 	add.w	r7, r7, #16
 88a:	46bd      	mov	sp, r7
 88c:	bd80      	pop	{r7, pc}
 88e:	bf00      	nop

00000890 <get_silicon_revision>:

/*------------------------------------------------------------------------------
  Retrieve silicon revision from system registers.
 */
static uint32_t get_silicon_revision(void)
{
 890:	b480      	push	{r7}
 892:	b083      	sub	sp, #12
 894:	af00      	add	r7, sp, #0
    uint32_t silicon_revision;
    uint32_t device_version;

    device_version = SYSREG->DEVICE_VERSION;
 896:	f248 0300 	movw	r3, #32768	; 0x8000
 89a:	f2c4 0303 	movt	r3, #16387	; 0x4003
 89e:	f8d3 314c 	ldr.w	r3, [r3, #332]	; 0x14c
 8a2:	607b      	str	r3, [r7, #4]
    switch(device_version)
 8a4:	687a      	ldr	r2, [r7, #4]
 8a6:	f64f 0302 	movw	r3, #63490	; 0xf802
 8aa:	429a      	cmp	r2, r3
 8ac:	d006      	beq.n	8bc <get_silicon_revision+0x2c>
 8ae:	f64f 0302 	movw	r3, #63490	; 0xf802
 8b2:	f2c0 0301 	movt	r3, #1
 8b6:	429a      	cmp	r2, r3
 8b8:	d004      	beq.n	8c4 <get_silicon_revision+0x34>
 8ba:	e007      	b.n	8cc <get_silicon_revision+0x3c>
    {
        case 0x0000F802:
            silicon_revision = M2S050_REV_A_SILICON;
 8bc:	f04f 0301 	mov.w	r3, #1
 8c0:	603b      	str	r3, [r7, #0]
            break;
 8c2:	e006      	b.n	8d2 <get_silicon_revision+0x42>

        case 0x0001F802:
            silicon_revision = M2S050_REV_B_SILICON;
 8c4:	f04f 0302 	mov.w	r3, #2
 8c8:	603b      	str	r3, [r7, #0]
            break;
 8ca:	e002      	b.n	8d2 <get_silicon_revision+0x42>

        default:
            silicon_revision = UNKNOWN_SILICON_REV;
 8cc:	f04f 0300 	mov.w	r3, #0
 8d0:	603b      	str	r3, [r7, #0]
            break;
    }

    return silicon_revision;
 8d2:	683b      	ldr	r3, [r7, #0]
}
 8d4:	4618      	mov	r0, r3
 8d6:	f107 070c 	add.w	r7, r7, #12
 8da:	46bd      	mov	sp, r7
 8dc:	bc80      	pop	{r7}
 8de:	4770      	bx	lr

000008e0 <silicon_workarounds>:

/*------------------------------------------------------------------------------
  Workarounds for various silicon versions.
 */
static void silicon_workarounds(void)
{
 8e0:	b580      	push	{r7, lr}
 8e2:	b082      	sub	sp, #8
 8e4:	af00      	add	r7, sp, #0
    uint32_t silicon_revision;

    silicon_revision = get_silicon_revision();
 8e6:	f7ff ffd3 	bl	890 <get_silicon_revision>
 8ea:	4603      	mov	r3, r0
 8ec:	607b      	str	r3, [r7, #4]

    switch(silicon_revision)
 8ee:	687b      	ldr	r3, [r7, #4]
 8f0:	2b01      	cmp	r3, #1
 8f2:	d101      	bne.n	8f8 <silicon_workarounds+0x18>
    {
        case M2S050_REV_A_SILICON:
            m2s050_rev_a_workarounds();
 8f4:	f000 f804 	bl	900 <m2s050_rev_a_workarounds>
        case UNKNOWN_SILICON_REV:
            /* Fall through. */
        default:
            break;
    }
}
 8f8:	f107 0708 	add.w	r7, r7, #8
 8fc:	46bd      	mov	sp, r7
 8fe:	bd80      	pop	{r7, pc}

00000900 <m2s050_rev_a_workarounds>:

/*------------------------------------------------------------------------------
  Silicon workarounds for M2S050 rev A.
 */
static void m2s050_rev_a_workarounds(void)
{
 900:	b480      	push	{r7}
 902:	af00      	add	r7, sp, #0
    /*--------------------------------------------------------------------------
     * Work around a couple of silicon issues:
     */
    /* DDR_CLK_EN <- 1 */
    SYSREG->MSSDDR_FACC1_CR |= (uint32_t)1 << DDR_CLK_EN_SHIFT;
 904:	f248 0300 	movw	r3, #32768	; 0x8000
 908:	f2c4 0303 	movt	r3, #16387	; 0x4003
 90c:	f248 0200 	movw	r2, #32768	; 0x8000
 910:	f2c4 0203 	movt	r2, #16387	; 0x4003
 914:	f8d2 2098 	ldr.w	r2, [r2, #152]	; 0x98
 918:	f442 7280 	orr.w	r2, r2, #256	; 0x100
 91c:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98

    /* CONTROLLER_PLL_INIT <- 0 */
    SYSREG->MSSDDR_FACC1_CR = SYSREG->MSSDDR_FACC1_CR & ~CONTROLLER_PLL_INIT_MASK;
 920:	f248 0300 	movw	r3, #32768	; 0x8000
 924:	f2c4 0303 	movt	r3, #16387	; 0x4003
 928:	f248 0200 	movw	r2, #32768	; 0x8000
 92c:	f2c4 0203 	movt	r2, #16387	; 0x4003
 930:	f8d2 2098 	ldr.w	r2, [r2, #152]	; 0x98
 934:	f022 6280 	bic.w	r2, r2, #67108864	; 0x4000000
 938:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98
}
 93c:	46bd      	mov	sp, r7
 93e:	bc80      	pop	{r7}
 940:	4770      	bx	lr
 942:	bf00      	nop

00000944 <g_m2s_mddr_addr>:
 944:	0800 4002                                   ...@

00000948 <g_m2s_mddr_subsys_config>:
 948:	0000 0000 1188 0290 0002 0000 0101 0999     ................
 958:	0000 3333 ffff 8888 0888 0001 4200 0008     ..33.........B..
 968:	0912 0002 0000 0000 0000 0085 0235 0064     ............5.d.
 978:	0020 0178 0000 0240 0014 0000 3300 0000      .x...@......3..
 988:	0000 040c 0000 0000 0000 0002 0000 2080     ............... 
 998:	80f8 0007 80f8 0007 0200 0000 0000 0004     ................
 9a8:	0003 0040 0000 0000 0000 0000 0309 0001     ..@.............
 9b8:	0000 0000 0000 0080 0000 0000 0003 0000     ................
	...
 9d0:	000b 0000 0000 0000 0000 0080 2004 0100     ............. ..
 9e0:	0008 0000 0000 0000 0000 0000 0000 0000     ................
	...
 9f8:	4050 0501 5014 0000 0000 0000 0000 0000     P@...P..........
	...
 a18:	0050 0501 5010 0000 0000 0000 0000 0000     P....P..........
 a28:	0000 0043 0000 0003 0001 0001 0000 0000     ..C.............
 a38:	0000 0001 0000 0000 0000 0000 0000 0000     ................
	...

Disassembly of section .text:

00000a60 <__do_global_dtors_aux>:
     a60:	f240 1330 	movw	r3, #304	; 0x130
     a64:	f2c2 0300 	movt	r3, #8192	; 0x2000
     a68:	781a      	ldrb	r2, [r3, #0]
     a6a:	b90a      	cbnz	r2, a70 <__do_global_dtors_aux+0x10>
     a6c:	2001      	movs	r0, #1
     a6e:	7018      	strb	r0, [r3, #0]
     a70:	4770      	bx	lr
     a72:	bf00      	nop

00000a74 <frame_dummy>:
     a74:	f240 0000 	movw	r0, #0
     a78:	f2c2 0000 	movt	r0, #8192	; 0x2000
     a7c:	b508      	push	{r3, lr}
     a7e:	6803      	ldr	r3, [r0, #0]
     a80:	b12b      	cbz	r3, a8e <frame_dummy+0x1a>
     a82:	f240 0300 	movw	r3, #0
     a86:	f2c0 0300 	movt	r3, #0
     a8a:	b103      	cbz	r3, a8e <frame_dummy+0x1a>
     a8c:	4798      	blx	r3
     a8e:	bd08      	pop	{r3, pc}

00000a90 <UartMsgHandler>:

uint8_t   key;
uint8_t rx_buff[1];
uint32_t MDDR_status=0;

void UartMsgHandler(){
     a90:	b580      	push	{r7, lr}
     a92:	af00      	add	r7, sp, #0

      switch(key)
     a94:	f240 13b5 	movw	r3, #437	; 0x1b5
     a98:	f2c2 0300 	movt	r3, #8192	; 0x2000
     a9c:	781b      	ldrb	r3, [r3, #0]
     a9e:	2b50      	cmp	r3, #80	; 0x50
     aa0:	d024      	beq.n	aec <UartMsgHandler+0x5c>
     aa2:	2b69      	cmp	r3, #105	; 0x69
     aa4:	d134      	bne.n	b10 <UartMsgHandler+0x80>
      {
				 case 'i':
      					   if((MDDR_status&0x2) == 0x2)
     aa6:	f240 1334 	movw	r3, #308	; 0x134
     aaa:	f2c2 0300 	movt	r3, #8192	; 0x2000
     aae:	681b      	ldr	r3, [r3, #0]
     ab0:	f003 0302 	and.w	r3, r3, #2
     ab4:	2b00      	cmp	r3, #0
     ab6:	d00c      	beq.n	ad2 <UartMsgHandler+0x42>
      						   MSS_UART_polled_tx( &g_mss_uart0, (const uint8_t *)"s", 1 );
     ab8:	f240 10f8 	movw	r0, #504	; 0x1f8
     abc:	f2c2 0000 	movt	r0, #8192	; 0x2000
     ac0:	f649 6104 	movw	r1, #40452	; 0x9e04
     ac4:	f2c0 0100 	movt	r1, #0
     ac8:	f04f 0201 	mov.w	r2, #1
     acc:	f000 fd00 	bl	14d0 <MSS_UART_polled_tx>
      					   else
      						   MSS_UART_polled_tx( &g_mss_uart0, (const uint8_t *)"d", 1 );
      					   break;
     ad0:	e01e      	b.n	b10 <UartMsgHandler+0x80>
      {
				 case 'i':
      					   if((MDDR_status&0x2) == 0x2)
      						   MSS_UART_polled_tx( &g_mss_uart0, (const uint8_t *)"s", 1 );
      					   else
      						   MSS_UART_polled_tx( &g_mss_uart0, (const uint8_t *)"d", 1 );
     ad2:	f240 10f8 	movw	r0, #504	; 0x1f8
     ad6:	f2c2 0000 	movt	r0, #8192	; 0x2000
     ada:	f649 6108 	movw	r1, #40456	; 0x9e08
     ade:	f2c0 0100 	movt	r1, #0
     ae2:	f04f 0201 	mov.w	r2, #1
     ae6:	f000 fcf3 	bl	14d0 <MSS_UART_polled_tx>
      					   break;
     aea:	e011      	b.n	b10 <UartMsgHandler+0x80>
                 case 'P':
						   MSS_UART_disable_irq(&g_mss_uart0,MSS_UART_RBF_IRQ );
     aec:	f240 10f8 	movw	r0, #504	; 0x1f8
     af0:	f2c2 0000 	movt	r0, #8192	; 0x2000
     af4:	f04f 0101 	mov.w	r1, #1
     af8:	f000 ff30 	bl	195c <MSS_UART_disable_irq>
      					   spi_flash_loader();				//program SPI Flash
     afc:	f000 f884 	bl	c08 <spi_flash_loader>
      					   MSS_UART_enable_irq(&g_mss_uart0,MSS_UART_RBF_IRQ );
     b00:	f240 10f8 	movw	r0, #504	; 0x1f8
     b04:	f2c2 0000 	movt	r0, #8192	; 0x2000
     b08:	f04f 0101 	mov.w	r1, #1
     b0c:	f000 fec8 	bl	18a0 <MSS_UART_enable_irq>
      					   break;
        }
}
     b10:	bd80      	pop	{r7, pc}
     b12:	bf00      	nop

00000b14 <uart0_rx_handler>:

void uart0_rx_handler( mss_uart_instance_t * this_uart )
{
     b14:	b580      	push	{r7, lr}
     b16:	b084      	sub	sp, #16
     b18:	af00      	add	r7, sp, #0
     b1a:	6078      	str	r0, [r7, #4]
	size_t rx_size = 0U;
     b1c:	f04f 0300 	mov.w	r3, #0
     b20:	60fb      	str	r3, [r7, #12]
	rx_size = MSS_UART_get_rx( &g_mss_uart0, &key, 1);
     b22:	f240 10f8 	movw	r0, #504	; 0x1f8
     b26:	f2c2 0000 	movt	r0, #8192	; 0x2000
     b2a:	f240 11b5 	movw	r1, #437	; 0x1b5
     b2e:	f2c2 0100 	movt	r1, #8192	; 0x2000
     b32:	f04f 0201 	mov.w	r2, #1
     b36:	f000 fe45 	bl	17c4 <MSS_UART_get_rx>
     b3a:	4603      	mov	r3, r0
     b3c:	60fb      	str	r3, [r7, #12]

      if(rx_size==1)
     b3e:	68fb      	ldr	r3, [r7, #12]
     b40:	2b01      	cmp	r3, #1
     b42:	d10b      	bne.n	b5c <uart0_rx_handler+0x48>
      {
    	  UartMsgHandler();
     b44:	f7ff ffa4 	bl	a90 <UartMsgHandler>
          rx_size  = 0;
     b48:	f04f 0300 	mov.w	r3, #0
     b4c:	60fb      	str	r3, [r7, #12]
          key=0;
     b4e:	f240 13b5 	movw	r3, #437	; 0x1b5
     b52:	f2c2 0300 	movt	r3, #8192	; 0x2000
     b56:	f04f 0200 	mov.w	r2, #0
     b5a:	701a      	strb	r2, [r3, #0]
      }
}
     b5c:	f107 0710 	add.w	r7, r7, #16
     b60:	46bd      	mov	sp, r7
     b62:	bd80      	pop	{r7, pc}

00000b64 <UART_Polled_Rx>:
(
    mss_uart_instance_t * this_uart,
    uint8_t * rx_buff,
    size_t buff_size
)
{
     b64:	b480      	push	{r7}
     b66:	b087      	sub	sp, #28
     b68:	af00      	add	r7, sp, #0
     b6a:	60f8      	str	r0, [r7, #12]
     b6c:	60b9      	str	r1, [r7, #8]
     b6e:	607a      	str	r2, [r7, #4]
    size_t rx_size = 0U;
     b70:	f04f 0300 	mov.w	r3, #0
     b74:	617b      	str	r3, [r7, #20]

    while( rx_size < buff_size )
     b76:	e016      	b.n	ba6 <UART_Polled_Rx+0x42>
    {
       while ( ((this_uart->hw_reg->LSR) & 0x1) != 0U  )
       {
           rx_buff[rx_size] = this_uart->hw_reg->RBR;
     b78:	68ba      	ldr	r2, [r7, #8]
     b7a:	697b      	ldr	r3, [r7, #20]
     b7c:	4413      	add	r3, r2
     b7e:	68fa      	ldr	r2, [r7, #12]
     b80:	6812      	ldr	r2, [r2, #0]
     b82:	7812      	ldrb	r2, [r2, #0]
     b84:	b2d2      	uxtb	r2, r2
     b86:	701a      	strb	r2, [r3, #0]
           ++rx_size;
     b88:	697b      	ldr	r3, [r7, #20]
     b8a:	f103 0301 	add.w	r3, r3, #1
     b8e:	617b      	str	r3, [r7, #20]
     b90:	e000      	b.n	b94 <UART_Polled_Rx+0x30>
{
    size_t rx_size = 0U;

    while( rx_size < buff_size )
    {
       while ( ((this_uart->hw_reg->LSR) & 0x1) != 0U  )
     b92:	bf00      	nop
     b94:	68fb      	ldr	r3, [r7, #12]
     b96:	681b      	ldr	r3, [r3, #0]
     b98:	7d1b      	ldrb	r3, [r3, #20]
     b9a:	b2db      	uxtb	r3, r3
     b9c:	f003 0301 	and.w	r3, r3, #1
     ba0:	b2db      	uxtb	r3, r3
     ba2:	2b00      	cmp	r3, #0
     ba4:	d1e8      	bne.n	b78 <UART_Polled_Rx+0x14>
    size_t buff_size
)
{
    size_t rx_size = 0U;

    while( rx_size < buff_size )
     ba6:	697a      	ldr	r2, [r7, #20]
     ba8:	687b      	ldr	r3, [r7, #4]
     baa:	429a      	cmp	r2, r3
     bac:	d3f1      	bcc.n	b92 <UART_Polled_Rx+0x2e>
           rx_buff[rx_size] = this_uart->hw_reg->RBR;
           ++rx_size;
       }
    }

    return rx_size;
     bae:	697b      	ldr	r3, [r7, #20]
}
     bb0:	4618      	mov	r0, r3
     bb2:	f107 071c 	add.w	r7, r7, #28
     bb6:	46bd      	mov	sp, r7
     bb8:	bc80      	pop	{r7}
     bba:	4770      	bx	lr

00000bbc <main>:

/*==============================================================================
 * main function.
 */
int main()
{
     bbc:	b580      	push	{r7, lr}
     bbe:	af00      	add	r7, sp, #0

   /* Initialize and configure UART0. */
    MSS_UART_init( &g_mss_uart0,
     bc0:	f240 10f8 	movw	r0, #504	; 0x1f8
     bc4:	f2c2 0000 	movt	r0, #8192	; 0x2000
     bc8:	f44f 31e1 	mov.w	r1, #115200	; 0x1c200
     bcc:	f04f 0203 	mov.w	r2, #3
     bd0:	f000 fb38 	bl	1244 <MSS_UART_init>
                  MSS_UART_115200_BAUD,
                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT );
    MDDR_status = SYSREG->MDDR_CR;
     bd4:	f248 0300 	movw	r3, #32768	; 0x8000
     bd8:	f2c4 0303 	movt	r3, #16387	; 0x4003
     bdc:	6e1a      	ldr	r2, [r3, #96]	; 0x60
     bde:	f240 1334 	movw	r3, #308	; 0x134
     be2:	f2c2 0300 	movt	r3, #8192	; 0x2000
     be6:	601a      	str	r2, [r3, #0]
    MSS_UART_set_rx_handler( &g_mss_uart0,
     be8:	f240 10f8 	movw	r0, #504	; 0x1f8
     bec:	f2c2 0000 	movt	r0, #8192	; 0x2000
     bf0:	f640 3115 	movw	r1, #2837	; 0xb15
     bf4:	f2c0 0100 	movt	r1, #0
     bf8:	f04f 0200 	mov.w	r2, #0
     bfc:	f000 ff0a 	bl	1a14 <MSS_UART_set_rx_handler>
                             uart0_rx_handler,
                             MSS_UART_FIFO_SINGLE_BYTE );
    FLASH_init();
     c00:	f008 fc3a 	bl	9478 <FLASH_init>

  while(1)
  {

  }
     c04:	e7fe      	b.n	c04 <main+0x48>
     c06:	bf00      	nop

00000c08 <spi_flash_loader>:
   return 0;
}

static void spi_flash_loader(void)
{
     c08:	b580      	push	{r7, lr}
     c0a:	f5ad 6d03 	sub.w	sp, sp, #2096	; 0x830
     c0e:	af00      	add	r7, sp, #0
    size_t rx_size;
    uint8_t img_buffer[1024];
    uint8_t img_buffer2[1030];
    uint32_t address, oriAddress;
    uint32_t img_size = 0,ii = 0,length = 0, oriSize = 0;
     c10:	463b      	mov	r3, r7
     c12:	f04f 0200 	mov.w	r2, #0
     c16:	601a      	str	r2, [r3, #0]
     c18:	f04f 0300 	mov.w	r3, #0
     c1c:	f8c7 3818 	str.w	r3, [r7, #2072]	; 0x818
     c20:	f04f 0300 	mov.w	r3, #0
     c24:	f8c7 381c 	str.w	r3, [r7, #2076]	; 0x81c
     c28:	f04f 0300 	mov.w	r3, #0
     c2c:	f8c7 3820 	str.w	r3, [r7, #2080]	; 0x820
    ii     = 0;
     c30:	f04f 0300 	mov.w	r3, #0
     c34:	f8c7 3818 	str.w	r3, [r7, #2072]	; 0x818
    length = 0;
     c38:	f04f 0300 	mov.w	r3, #0
     c3c:	f8c7 381c 	str.w	r3, [r7, #2076]	; 0x81c
//    spi_flash_status_t spi_status;

    uint32_t erase_spi = 0,erase_count = 0,erase_address =0;
     c40:	f04f 0300 	mov.w	r3, #0
     c44:	f8c7 3824 	str.w	r3, [r7, #2084]	; 0x824
     c48:	f04f 0300 	mov.w	r3, #0
     c4c:	f8c7 3828 	str.w	r3, [r7, #2088]	; 0x828
     c50:	f04f 0300 	mov.w	r3, #0
     c54:	f8c7 382c 	str.w	r3, [r7, #2092]	; 0x82c

    /**************handshaking with MMUART***********************/

    while(!(UART_Polled_Rx ( &g_mss_uart0, rx_buff, 1 )))
     c58:	f240 10f8 	movw	r0, #504	; 0x1f8
     c5c:	f2c2 0000 	movt	r0, #8192	; 0x2000
     c60:	f240 11b4 	movw	r1, #436	; 0x1b4
     c64:	f2c2 0100 	movt	r1, #8192	; 0x2000
     c68:	f04f 0201 	mov.w	r2, #1
     c6c:	f7ff ff7a 	bl	b64 <UART_Polled_Rx>
     c70:	4603      	mov	r3, r0
     c72:	2b00      	cmp	r3, #0
     c74:	d0f0      	beq.n	c58 <spi_flash_loader+0x50>
         ;
    if(rx_buff[0] == 'h')
     c76:	f240 13b4 	movw	r3, #436	; 0x1b4
     c7a:	f2c2 0300 	movt	r3, #8192	; 0x2000
     c7e:	781b      	ldrb	r3, [r3, #0]
     c80:	2b68      	cmp	r3, #104	; 0x68
     c82:	d10b      	bne.n	c9c <spi_flash_loader+0x94>
        MSS_UART_polled_tx( &g_mss_uart0, (const uint8_t *)"a", 1 );
     c84:	f240 10f8 	movw	r0, #504	; 0x1f8
     c88:	f2c2 0000 	movt	r0, #8192	; 0x2000
     c8c:	f649 610c 	movw	r1, #40460	; 0x9e0c
     c90:	f2c0 0100 	movt	r1, #0
     c94:	f04f 0201 	mov.w	r2, #1
     c98:	f000 fc1a 	bl	14d0 <MSS_UART_polled_tx>

    while(!(UART_Polled_Rx ( &g_mss_uart0, rx_buff, 1 )))
     c9c:	f240 10f8 	movw	r0, #504	; 0x1f8
     ca0:	f2c2 0000 	movt	r0, #8192	; 0x2000
     ca4:	f240 11b4 	movw	r1, #436	; 0x1b4
     ca8:	f2c2 0100 	movt	r1, #8192	; 0x2000
     cac:	f04f 0201 	mov.w	r2, #1
     cb0:	f7ff ff58 	bl	b64 <UART_Polled_Rx>
     cb4:	4603      	mov	r3, r0
     cb6:	2b00      	cmp	r3, #0
     cb8:	d0f0      	beq.n	c9c <spi_flash_loader+0x94>
         ;

    if(rx_buff[0] == 'n')
     cba:	f240 13b4 	movw	r3, #436	; 0x1b4
     cbe:	f2c2 0300 	movt	r3, #8192	; 0x2000
     cc2:	781b      	ldrb	r3, [r3, #0]
     cc4:	2b6e      	cmp	r3, #110	; 0x6e
     cc6:	d10b      	bne.n	ce0 <spi_flash_loader+0xd8>
        MSS_UART_polled_tx( &g_mss_uart0, (const uint8_t *)"d", 1 );
     cc8:	f240 10f8 	movw	r0, #504	; 0x1f8
     ccc:	f2c2 0000 	movt	r0, #8192	; 0x2000
     cd0:	f649 6108 	movw	r1, #40456	; 0x9e08
     cd4:	f2c0 0100 	movt	r1, #0
     cd8:	f04f 0201 	mov.w	r2, #1
     cdc:	f000 fbf8 	bl	14d0 <MSS_UART_polled_tx>

    while(!(UART_Polled_Rx ( &g_mss_uart0, rx_buff, 1 )))
     ce0:	f240 10f8 	movw	r0, #504	; 0x1f8
     ce4:	f2c2 0000 	movt	r0, #8192	; 0x2000
     ce8:	f240 11b4 	movw	r1, #436	; 0x1b4
     cec:	f2c2 0100 	movt	r1, #8192	; 0x2000
     cf0:	f04f 0201 	mov.w	r2, #1
     cf4:	f7ff ff36 	bl	b64 <UART_Polled_Rx>
     cf8:	4603      	mov	r3, r0
     cfa:	2b00      	cmp	r3, #0
     cfc:	d0f0      	beq.n	ce0 <spi_flash_loader+0xd8>
         ;

    if(rx_buff[0] == 's')
     cfe:	f240 13b4 	movw	r3, #436	; 0x1b4
     d02:	f2c2 0300 	movt	r3, #8192	; 0x2000
     d06:	781b      	ldrb	r3, [r3, #0]
     d08:	2b73      	cmp	r3, #115	; 0x73
     d0a:	d10b      	bne.n	d24 <spi_flash_loader+0x11c>
        MSS_UART_polled_tx( &g_mss_uart0, (const uint8_t *)"h", 1 );
     d0c:	f240 10f8 	movw	r0, #504	; 0x1f8
     d10:	f2c2 0000 	movt	r0, #8192	; 0x2000
     d14:	f649 6110 	movw	r1, #40464	; 0x9e10
     d18:	f2c0 0100 	movt	r1, #0
     d1c:	f04f 0201 	mov.w	r2, #1
     d20:	f000 fbd6 	bl	14d0 <MSS_UART_polled_tx>

    while(!(UART_Polled_Rx ( &g_mss_uart0, rx_buff, 1 )))
     d24:	f240 10f8 	movw	r0, #504	; 0x1f8
     d28:	f2c2 0000 	movt	r0, #8192	; 0x2000
     d2c:	f240 11b4 	movw	r1, #436	; 0x1b4
     d30:	f2c2 0100 	movt	r1, #8192	; 0x2000
     d34:	f04f 0201 	mov.w	r2, #1
     d38:	f7ff ff14 	bl	b64 <UART_Polled_Rx>
     d3c:	4603      	mov	r3, r0
     d3e:	2b00      	cmp	r3, #0
     d40:	d0f0      	beq.n	d24 <spi_flash_loader+0x11c>
         ;

    if(rx_buff[0] == 'a')
     d42:	f240 13b4 	movw	r3, #436	; 0x1b4
     d46:	f2c2 0300 	movt	r3, #8192	; 0x2000
     d4a:	781b      	ldrb	r3, [r3, #0]
     d4c:	2b61      	cmp	r3, #97	; 0x61
     d4e:	d10b      	bne.n	d68 <spi_flash_loader+0x160>
        MSS_UART_polled_tx( &g_mss_uart0, (const uint8_t *)"k", 1 );
     d50:	f240 10f8 	movw	r0, #504	; 0x1f8
     d54:	f2c2 0000 	movt	r0, #8192	; 0x2000
     d58:	f649 6114 	movw	r1, #40468	; 0x9e14
     d5c:	f2c0 0100 	movt	r1, #0
     d60:	f04f 0201 	mov.w	r2, #1
     d64:	f000 fbb4 	bl	14d0 <MSS_UART_polled_tx>


    /* Read the image size */
    while( ! UART_Polled_Rx(&g_mss_uart0, (uint8_t *)&img_size, 4));
     d68:	463b      	mov	r3, r7
     d6a:	f240 10f8 	movw	r0, #504	; 0x1f8
     d6e:	f2c2 0000 	movt	r0, #8192	; 0x2000
     d72:	4619      	mov	r1, r3
     d74:	f04f 0204 	mov.w	r2, #4
     d78:	f7ff fef4 	bl	b64 <UART_Polled_Rx>
     d7c:	4603      	mov	r3, r0
     d7e:	2b00      	cmp	r3, #0
     d80:	d0f2      	beq.n	d68 <spi_flash_loader+0x160>

    MSS_UART_polled_tx( &g_mss_uart0,(const uint8_t *)&img_size, 4 );
     d82:	463b      	mov	r3, r7
     d84:	f240 10f8 	movw	r0, #504	; 0x1f8
     d88:	f2c2 0000 	movt	r0, #8192	; 0x2000
     d8c:	4619      	mov	r1, r3
     d8e:	f04f 0204 	mov.w	r2, #4
     d92:	f000 fb9d 	bl	14d0 <MSS_UART_polled_tx>

    oriSize = img_size;
     d96:	463b      	mov	r3, r7
     d98:	681b      	ldr	r3, [r3, #0]
     d9a:	f8c7 3820 	str.w	r3, [r7, #2080]	; 0x820

    /* Read the address */
    while( ! UART_Polled_Rx(&g_mss_uart0, (uint8_t *)&address, 4))
     d9e:	f107 0310 	add.w	r3, r7, #16
     da2:	f1a3 030c 	sub.w	r3, r3, #12
     da6:	f240 10f8 	movw	r0, #504	; 0x1f8
     daa:	f2c2 0000 	movt	r0, #8192	; 0x2000
     dae:	4619      	mov	r1, r3
     db0:	f04f 0204 	mov.w	r2, #4
     db4:	f7ff fed6 	bl	b64 <UART_Polled_Rx>
     db8:	4603      	mov	r3, r0
     dba:	2b00      	cmp	r3, #0
     dbc:	d0ef      	beq.n	d9e <spi_flash_loader+0x196>
        ;

    MSS_UART_polled_tx( &g_mss_uart0,(const uint8_t *)&address, 4 );
     dbe:	f107 0310 	add.w	r3, r7, #16
     dc2:	f1a3 030c 	sub.w	r3, r3, #12
     dc6:	f240 10f8 	movw	r0, #504	; 0x1f8
     dca:	f2c2 0000 	movt	r0, #8192	; 0x2000
     dce:	4619      	mov	r1, r3
     dd0:	f04f 0204 	mov.w	r2, #4
     dd4:	f000 fb7c 	bl	14d0 <MSS_UART_polled_tx>
    oriAddress = address;
     dd8:	f107 0310 	add.w	r3, r7, #16
     ddc:	f1a3 030c 	sub.w	r3, r3, #12
     de0:	681b      	ldr	r3, [r3, #0]
     de2:	f8c7 3814 	str.w	r3, [r7, #2068]	; 0x814

    /*********** Read the file and burn into external flash *****************/

    /* Erasing SPI flash*/

    FLASH_global_unprotect();
     de6:	f008 fbe1 	bl	95ac <FLASH_global_unprotect>
	for(erase_count = 0;erase_count<=4;erase_count++)  //4*64k erase
     dea:	f04f 0300 	mov.w	r3, #0
     dee:	f8c7 3828 	str.w	r3, [r7, #2088]	; 0x828
     df2:	e011      	b.n	e18 <spi_flash_loader+0x210>
	{
		FLASH_erase_xk_block(erase_address,1);
     df4:	f8d7 082c 	ldr.w	r0, [r7, #2092]	; 0x82c
     df8:	f04f 0101 	mov.w	r1, #1
     dfc:	f008 fc76 	bl	96ec <FLASH_erase_xk_block>
		erase_address+=0x10000;
     e00:	f8d7 382c 	ldr.w	r3, [r7, #2092]	; 0x82c
     e04:	f503 3380 	add.w	r3, r3, #65536	; 0x10000
     e08:	f8c7 382c 	str.w	r3, [r7, #2092]	; 0x82c
    /*********** Read the file and burn into external flash *****************/

    /* Erasing SPI flash*/

    FLASH_global_unprotect();
	for(erase_count = 0;erase_count<=4;erase_count++)  //4*64k erase
     e0c:	f8d7 3828 	ldr.w	r3, [r7, #2088]	; 0x828
     e10:	f103 0301 	add.w	r3, r3, #1
     e14:	f8c7 3828 	str.w	r3, [r7, #2088]	; 0x828
     e18:	f8d7 3828 	ldr.w	r3, [r7, #2088]	; 0x828
     e1c:	2b04      	cmp	r3, #4
     e1e:	d9e9      	bls.n	df4 <spi_flash_loader+0x1ec>
		FLASH_erase_xk_block(erase_address,1);
		erase_address+=0x10000;

	}

    MSS_UART_polled_tx( &g_mss_uart0, (const uint8_t *)"c", 1 );
     e20:	f240 10f8 	movw	r0, #504	; 0x1f8
     e24:	f2c2 0000 	movt	r0, #8192	; 0x2000
     e28:	f649 6118 	movw	r1, #40472	; 0x9e18
     e2c:	f2c0 0100 	movt	r1, #0
     e30:	f04f 0201 	mov.w	r2, #1
     e34:	f000 fb4c 	bl	14d0 <MSS_UART_polled_tx>


    while(img_size > 0)
     e38:	e062      	b.n	f00 <spi_flash_loader+0x2f8>
    {
        rx_size =0;
     e3a:	f04f 0300 	mov.w	r3, #0
     e3e:	f8c7 3810 	str.w	r3, [r7, #2064]	; 0x810
        if (img_size >=256)
     e42:	463b      	mov	r3, r7
     e44:	681b      	ldr	r3, [r3, #0]
     e46:	2bff      	cmp	r3, #255	; 0xff
     e48:	d904      	bls.n	e54 <spi_flash_loader+0x24c>
        {
            length = 256;
     e4a:	f44f 7380 	mov.w	r3, #256	; 0x100
     e4e:	f8c7 381c 	str.w	r3, [r7, #2076]	; 0x81c
     e52:	e003      	b.n	e5c <spi_flash_loader+0x254>
        }
        else
        {
            length = img_size;
     e54:	463b      	mov	r3, r7
     e56:	681b      	ldr	r3, [r3, #0]
     e58:	f8c7 381c 	str.w	r3, [r7, #2076]	; 0x81c
        }

        do
        {
            rx_size = UART_Polled_Rx(&g_mss_uart0, (uint8_t *)&img_buffer, length);
     e5c:	f507 6382 	add.w	r3, r7, #1040	; 0x410
     e60:	f240 10f8 	movw	r0, #504	; 0x1f8
     e64:	f2c2 0000 	movt	r0, #8192	; 0x2000
     e68:	4619      	mov	r1, r3
     e6a:	f8d7 281c 	ldr.w	r2, [r7, #2076]	; 0x81c
     e6e:	f7ff fe79 	bl	b64 <UART_Polled_Rx>
     e72:	4603      	mov	r3, r0
     e74:	f8c7 3810 	str.w	r3, [r7, #2064]	; 0x810
        }
        while(!rx_size);
     e78:	f8d7 3810 	ldr.w	r3, [r7, #2064]	; 0x810
     e7c:	2b00      	cmp	r3, #0
     e7e:	d0ed      	beq.n	e5c <spi_flash_loader+0x254>

        if(rx_size != length)
     e80:	f8d7 2810 	ldr.w	r2, [r7, #2064]	; 0x810
     e84:	f8d7 381c 	ldr.w	r3, [r7, #2076]	; 0x81c
     e88:	429a      	cmp	r2, r3
     e8a:	f040 8091 	bne.w	fb0 <spi_flash_loader+0x3a8>
        {
            return;
        }
        img_size -= length;
     e8e:	463b      	mov	r3, r7
     e90:	681a      	ldr	r2, [r3, #0]
     e92:	f8d7 381c 	ldr.w	r3, [r7, #2076]	; 0x81c
     e96:	ebc3 0202 	rsb	r2, r3, r2
     e9a:	463b      	mov	r3, r7
     e9c:	601a      	str	r2, [r3, #0]
          /* aligning to 32 bit */
        if ((length%4) != 0)
     e9e:	f8d7 381c 	ldr.w	r3, [r7, #2076]	; 0x81c
     ea2:	f003 0303 	and.w	r3, r3, #3
     ea6:	2b00      	cmp	r3, #0
     ea8:	d007      	beq.n	eba <spi_flash_loader+0x2b2>
        {
            length += (4-(length%4));
     eaa:	f8d7 381c 	ldr.w	r3, [r7, #2076]	; 0x81c
     eae:	f023 0303 	bic.w	r3, r3, #3
     eb2:	f103 0304 	add.w	r3, r3, #4
     eb6:	f8c7 381c 	str.w	r3, [r7, #2076]	; 0x81c
        }
        FLASH_program(address + ii, img_buffer, length);
     eba:	f107 0310 	add.w	r3, r7, #16
     ebe:	f1a3 030c 	sub.w	r3, r3, #12
     ec2:	681a      	ldr	r2, [r3, #0]
     ec4:	f8d7 3818 	ldr.w	r3, [r7, #2072]	; 0x818
     ec8:	441a      	add	r2, r3
     eca:	f507 6382 	add.w	r3, r7, #1040	; 0x410
     ece:	4610      	mov	r0, r2
     ed0:	4619      	mov	r1, r3
     ed2:	f8d7 281c 	ldr.w	r2, [r7, #2076]	; 0x81c
     ed6:	f008 fd59 	bl	998c <FLASH_program>


        		ii += length;
     eda:	f8d7 2818 	ldr.w	r2, [r7, #2072]	; 0x818
     ede:	f8d7 381c 	ldr.w	r3, [r7, #2076]	; 0x81c
     ee2:	4413      	add	r3, r2
     ee4:	f8c7 3818 	str.w	r3, [r7, #2072]	; 0x818

        MSS_UART_polled_tx(&g_mss_uart0,(const uint8_t *)"p",1);
     ee8:	f240 10f8 	movw	r0, #504	; 0x1f8
     eec:	f2c2 0000 	movt	r0, #8192	; 0x2000
     ef0:	f649 611c 	movw	r1, #40476	; 0x9e1c
     ef4:	f2c0 0100 	movt	r1, #0
     ef8:	f04f 0201 	mov.w	r2, #1
     efc:	f000 fae8 	bl	14d0 <MSS_UART_polled_tx>
	}

    MSS_UART_polled_tx( &g_mss_uart0, (const uint8_t *)"c", 1 );


    while(img_size > 0)
     f00:	463b      	mov	r3, r7
     f02:	681b      	ldr	r3, [r3, #0]
     f04:	2b00      	cmp	r3, #0
     f06:	d198      	bne.n	e3a <spi_flash_loader+0x232>


    }
           /* Verify the last bytes */

        ii -= length;
     f08:	f8d7 2818 	ldr.w	r2, [r7, #2072]	; 0x818
     f0c:	f8d7 381c 	ldr.w	r3, [r7, #2076]	; 0x81c
     f10:	ebc3 0302 	rsb	r3, r3, r2
     f14:	f8c7 3818 	str.w	r3, [r7, #2072]	; 0x818
        FLASH_read(address + ii, img_buffer2, length);
     f18:	f107 0310 	add.w	r3, r7, #16
     f1c:	f1a3 030c 	sub.w	r3, r3, #12
     f20:	681a      	ldr	r2, [r3, #0]
     f22:	f8d7 3818 	ldr.w	r3, [r7, #2072]	; 0x818
     f26:	441a      	add	r2, r3
     f28:	f107 0310 	add.w	r3, r7, #16
     f2c:	f1a3 0308 	sub.w	r3, r3, #8
     f30:	4610      	mov	r0, r2
     f32:	4619      	mov	r1, r3
     f34:	f8d7 281c 	ldr.w	r2, [r7, #2076]	; 0x81c
     f38:	f008 faf2 	bl	9520 <FLASH_read>
        for(ii=0; ii<length; ii++)
     f3c:	f04f 0300 	mov.w	r3, #0
     f40:	f8c7 3818 	str.w	r3, [r7, #2072]	; 0x818
     f44:	e020      	b.n	f88 <spi_flash_loader+0x380>
        {
            if(img_buffer[ii] != img_buffer2[ii])
     f46:	f8d7 3818 	ldr.w	r3, [r7, #2072]	; 0x818
     f4a:	f507 6282 	add.w	r2, r7, #1040	; 0x410
     f4e:	5cd2      	ldrb	r2, [r2, r3]
     f50:	f8d7 1818 	ldr.w	r1, [r7, #2072]	; 0x818
     f54:	f107 0310 	add.w	r3, r7, #16
     f58:	f1a3 0308 	sub.w	r3, r3, #8
     f5c:	5c5b      	ldrb	r3, [r3, r1]
     f5e:	429a      	cmp	r2, r3
     f60:	d00c      	beq.n	f7c <spi_flash_loader+0x374>
            {
                MSS_UART_polled_tx(&g_mss_uart0,(const uint8_t *)"v",1);
     f62:	f240 10f8 	movw	r0, #504	; 0x1f8
     f66:	f2c2 0000 	movt	r0, #8192	; 0x2000
     f6a:	f649 6120 	movw	r1, #40480	; 0x9e20
     f6e:	f2c0 0100 	movt	r1, #0
     f72:	f04f 0201 	mov.w	r2, #1
     f76:	f000 faab 	bl	14d0 <MSS_UART_polled_tx>
                return;
     f7a:	e01a      	b.n	fb2 <spi_flash_loader+0x3aa>
    }
           /* Verify the last bytes */

        ii -= length;
        FLASH_read(address + ii, img_buffer2, length);
        for(ii=0; ii<length; ii++)
     f7c:	f8d7 3818 	ldr.w	r3, [r7, #2072]	; 0x818
     f80:	f103 0301 	add.w	r3, r3, #1
     f84:	f8c7 3818 	str.w	r3, [r7, #2072]	; 0x818
     f88:	f8d7 2818 	ldr.w	r2, [r7, #2072]	; 0x818
     f8c:	f8d7 381c 	ldr.w	r3, [r7, #2076]	; 0x81c
     f90:	429a      	cmp	r2, r3
     f92:	d3d8      	bcc.n	f46 <spi_flash_loader+0x33e>
            {
                MSS_UART_polled_tx(&g_mss_uart0,(const uint8_t *)"v",1);
                return;
            }
        }
        MSS_UART_polled_tx(&g_mss_uart0,(const uint8_t *)"y",1);
     f94:	f240 10f8 	movw	r0, #504	; 0x1f8
     f98:	f2c2 0000 	movt	r0, #8192	; 0x2000
     f9c:	f649 6124 	movw	r1, #40484	; 0x9e24
     fa0:	f2c0 0100 	movt	r1, #0
     fa4:	f04f 0201 	mov.w	r2, #1
     fa8:	f000 fa92 	bl	14d0 <MSS_UART_polled_tx>
        //exit_4byte_address_mode();
    return;
     fac:	bf00      	nop
     fae:	e000      	b.n	fb2 <spi_flash_loader+0x3aa>
        }
        while(!rx_size);

        if(rx_size != length)
        {
            return;
     fb0:	bf00      	nop
            }
        }
        MSS_UART_polled_tx(&g_mss_uart0,(const uint8_t *)"y",1);
        //exit_4byte_address_mode();
    return;
}
     fb2:	f507 6703 	add.w	r7, r7, #2096	; 0x830
     fb6:	46bd      	mov	sp, r7
     fb8:	bd80      	pop	{r7, pc}
     fba:	bf00      	nop

00000fbc <NVIC_init>:

/***************************************************************************//**
 * 
 */
void NVIC_init( void )
{
     fbc:	b480      	push	{r7}
     fbe:	af00      	add	r7, sp, #0
     * Hardware Abstraction Layer. The use of the Actel HAL NVIC control
     * functions is obsolete on SmartFusion2 devices.
     *
     * Simply remove the call to NVIC_init() from your application code.
     */
    ASSERT(0);
     fc0:	be00      	bkpt	0x0000
}
     fc2:	46bd      	mov	sp, r7
     fc4:	bc80      	pop	{r7}
     fc6:	4770      	bx	lr

00000fc8 <NVIC_set_handler>:
void NVIC_set_handler
(
    uint32_t interrupt_number,
    hal_nvic_irq_handler_t handler
)
{
     fc8:	b480      	push	{r7}
     fca:	b083      	sub	sp, #12
     fcc:	af00      	add	r7, sp, #0
     fce:	6078      	str	r0, [r7, #4]
     fd0:	6039      	str	r1, [r7, #0]
     *      - void FabricIrq15_IRQHandler(void)
     * The function to implement depends on which MSS_INT_F2M[n] signal is used
     * in your Libero design to connect the interrupt signal of the peripheral
     * generating the interrupt.
     */
    ASSERT(0);
     fd2:	be00      	bkpt	0x0000
}
     fd4:	f107 070c 	add.w	r7, r7, #12
     fd8:	46bd      	mov	sp, r7
     fda:	bc80      	pop	{r7}
     fdc:	4770      	bx	lr
     fde:	bf00      	nop

00000fe0 <NVIC_set_priority>:
void NVIC_set_priority
(
    uint32_t interrupt_number,
    uint8_t priority_level
)
{
     fe0:	b480      	push	{r7}
     fe2:	b083      	sub	sp, #12
     fe4:	af00      	add	r7, sp, #0
     fe6:	6078      	str	r0, [r7, #4]
     fe8:	460b      	mov	r3, r1
     fea:	70fb      	strb	r3, [r7, #3]
     *      - FabricIrq12_IRQn
     *      - FabricIrq13_IRQn
     *      - FabricIrq14_IRQn
     *      - FabricIrq15_IRQn
     */
    ASSERT(0);
     fec:	be00      	bkpt	0x0000
}
     fee:	f107 070c 	add.w	r7, r7, #12
     ff2:	46bd      	mov	sp, r7
     ff4:	bc80      	pop	{r7}
     ff6:	4770      	bx	lr

00000ff8 <NVIC_enable_interrupt>:

/***************************************************************************//**
 * 
 */
void NVIC_enable_interrupt( uint32_t interrupt_number )
{
     ff8:	b480      	push	{r7}
     ffa:	b083      	sub	sp, #12
     ffc:	af00      	add	r7, sp, #0
     ffe:	6078      	str	r0, [r7, #4]
     *      - FabricIrq12_IRQn
     *      - FabricIrq13_IRQn
     *      - FabricIrq14_IRQn
     *      - FabricIrq15_IRQn
     */
    ASSERT(0);
    1000:	be00      	bkpt	0x0000
}
    1002:	f107 070c 	add.w	r7, r7, #12
    1006:	46bd      	mov	sp, r7
    1008:	bc80      	pop	{r7}
    100a:	4770      	bx	lr

0000100c <NVIC_disable_interrupt>:

/***************************************************************************//**
 * 
 */
void NVIC_disable_interrupt( uint32_t interrupt_number )
{
    100c:	b480      	push	{r7}
    100e:	b083      	sub	sp, #12
    1010:	af00      	add	r7, sp, #0
    1012:	6078      	str	r0, [r7, #4]
     *      - FabricIrq12_IRQn
     *      - FabricIrq13_IRQn
     *      - FabricIrq14_IRQn
     *      - FabricIrq15_IRQn
     */
    ASSERT(0);
    1014:	be00      	bkpt	0x0000
}
    1016:	f107 070c 	add.w	r7, r7, #12
    101a:	46bd      	mov	sp, r7
    101c:	bc80      	pop	{r7}
    101e:	4770      	bx	lr

00001020 <NVIC_clear_interrupt>:

/***************************************************************************//**
 * 
 */
void NVIC_clear_interrupt( uint32_t interrupt_number )
{
    1020:	b480      	push	{r7}
    1022:	b083      	sub	sp, #12
    1024:	af00      	add	r7, sp, #0
    1026:	6078      	str	r0, [r7, #4]
     *      - FabricIrq12_IRQn
     *      - FabricIrq13_IRQn
     *      - FabricIrq14_IRQn
     *      - FabricIrq15_IRQn
     */
    ASSERT(0);
    1028:	be00      	bkpt	0x0000
}
    102a:	f107 070c 	add.w	r7, r7, #12
    102e:	46bd      	mov	sp, r7
    1030:	bc80      	pop	{r7}
    1032:	4770      	bx	lr

00001034 <HAL_disable_interrupts>:
    1034:	f3ef 8010 	mrs	r0, PRIMASK
    1038:	b672      	cpsid	i
    103a:	4770      	bx	lr

0000103c <HAL_restore_interrupts>:
    103c:	f380 8810 	msr	PRIMASK, r0
    1040:	4770      	bx	lr

00001042 <HW_set_32bit_reg>:
    1042:	6001      	str	r1, [r0, #0]
    1044:	4770      	bx	lr

00001046 <HW_get_32bit_reg>:
    1046:	6800      	ldr	r0, [r0, #0]
    1048:	4770      	bx	lr

0000104a <HW_set_32bit_reg_field>:
    104a:	b50e      	push	{r1, r2, r3, lr}
    104c:	fa03 f301 	lsl.w	r3, r3, r1
    1050:	ea03 0302 	and.w	r3, r3, r2
    1054:	6801      	ldr	r1, [r0, #0]
    1056:	ea6f 0202 	mvn.w	r2, r2
    105a:	ea01 0102 	and.w	r1, r1, r2
    105e:	ea41 0103 	orr.w	r1, r1, r3
    1062:	6001      	str	r1, [r0, #0]
    1064:	bd0e      	pop	{r1, r2, r3, pc}

00001066 <HW_get_32bit_reg_field>:
    1066:	6800      	ldr	r0, [r0, #0]
    1068:	ea00 0002 	and.w	r0, r0, r2
    106c:	fa20 f001 	lsr.w	r0, r0, r1
    1070:	4770      	bx	lr

00001072 <HW_set_16bit_reg>:
    1072:	8001      	strh	r1, [r0, #0]
    1074:	4770      	bx	lr

00001076 <HW_get_16bit_reg>:
    1076:	8800      	ldrh	r0, [r0, #0]
    1078:	4770      	bx	lr

0000107a <HW_set_16bit_reg_field>:
    107a:	b50e      	push	{r1, r2, r3, lr}
    107c:	fa03 f301 	lsl.w	r3, r3, r1
    1080:	ea03 0302 	and.w	r3, r3, r2
    1084:	8801      	ldrh	r1, [r0, #0]
    1086:	ea6f 0202 	mvn.w	r2, r2
    108a:	ea01 0102 	and.w	r1, r1, r2
    108e:	ea41 0103 	orr.w	r1, r1, r3
    1092:	8001      	strh	r1, [r0, #0]
    1094:	bd0e      	pop	{r1, r2, r3, pc}

00001096 <HW_get_16bit_reg_field>:
    1096:	8800      	ldrh	r0, [r0, #0]
    1098:	ea00 0002 	and.w	r0, r0, r2
    109c:	fa20 f001 	lsr.w	r0, r0, r1
    10a0:	4770      	bx	lr

000010a2 <HW_set_8bit_reg>:
    10a2:	7001      	strb	r1, [r0, #0]
    10a4:	4770      	bx	lr

000010a6 <HW_get_8bit_reg>:
    10a6:	7800      	ldrb	r0, [r0, #0]
    10a8:	4770      	bx	lr

000010aa <HW_set_8bit_reg_field>:
    10aa:	b50e      	push	{r1, r2, r3, lr}
    10ac:	fa03 f301 	lsl.w	r3, r3, r1
    10b0:	ea03 0302 	and.w	r3, r3, r2
    10b4:	7801      	ldrb	r1, [r0, #0]
    10b6:	ea6f 0202 	mvn.w	r2, r2
    10ba:	ea01 0102 	and.w	r1, r1, r2
    10be:	ea41 0103 	orr.w	r1, r1, r3
    10c2:	7001      	strb	r1, [r0, #0]
    10c4:	bd0e      	pop	{r1, r2, r3, pc}

000010c6 <HW_get_8bit_reg_field>:
    10c6:	7800      	ldrb	r0, [r0, #0]
    10c8:	ea00 0002 	and.w	r0, r0, r2
    10cc:	fa20 f001 	lsr.w	r0, r0, r1
    10d0:	4770      	bx	lr
	...

000010d4 <NVIC_EnableIRQ>:
    The function enables a device-specific interrupt in the NVIC interrupt controller.

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
    10d4:	b480      	push	{r7}
    10d6:	b083      	sub	sp, #12
    10d8:	af00      	add	r7, sp, #0
    10da:	4603      	mov	r3, r0
    10dc:	71fb      	strb	r3, [r7, #7]
  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
    10de:	f24e 1300 	movw	r3, #57600	; 0xe100
    10e2:	f2ce 0300 	movt	r3, #57344	; 0xe000
    10e6:	f997 2007 	ldrsb.w	r2, [r7, #7]
    10ea:	ea4f 1252 	mov.w	r2, r2, lsr #5
    10ee:	79f9      	ldrb	r1, [r7, #7]
    10f0:	f001 011f 	and.w	r1, r1, #31
    10f4:	f04f 0001 	mov.w	r0, #1
    10f8:	fa00 f101 	lsl.w	r1, r0, r1
    10fc:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
}
    1100:	f107 070c 	add.w	r7, r7, #12
    1104:	46bd      	mov	sp, r7
    1106:	bc80      	pop	{r7}
    1108:	4770      	bx	lr
    110a:	bf00      	nop

0000110c <NVIC_DisableIRQ>:
    The function disables a device-specific interrupt in the NVIC interrupt controller.

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
    110c:	b480      	push	{r7}
    110e:	b083      	sub	sp, #12
    1110:	af00      	add	r7, sp, #0
    1112:	4603      	mov	r3, r0
    1114:	71fb      	strb	r3, [r7, #7]
  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
    1116:	f24e 1300 	movw	r3, #57600	; 0xe100
    111a:	f2ce 0300 	movt	r3, #57344	; 0xe000
    111e:	f997 2007 	ldrsb.w	r2, [r7, #7]
    1122:	ea4f 1252 	mov.w	r2, r2, lsr #5
    1126:	79f9      	ldrb	r1, [r7, #7]
    1128:	f001 011f 	and.w	r1, r1, #31
    112c:	f04f 0001 	mov.w	r0, #1
    1130:	fa00 f101 	lsl.w	r1, r0, r1
    1134:	f102 0220 	add.w	r2, r2, #32
    1138:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
}
    113c:	f107 070c 	add.w	r7, r7, #12
    1140:	46bd      	mov	sp, r7
    1142:	bc80      	pop	{r7}
    1144:	4770      	bx	lr
    1146:	bf00      	nop

00001148 <NVIC_ClearPendingIRQ>:
    The function clears the pending bit of an external interrupt.

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
    1148:	b480      	push	{r7}
    114a:	b083      	sub	sp, #12
    114c:	af00      	add	r7, sp, #0
    114e:	4603      	mov	r3, r0
    1150:	71fb      	strb	r3, [r7, #7]
  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
    1152:	f24e 1300 	movw	r3, #57600	; 0xe100
    1156:	f2ce 0300 	movt	r3, #57344	; 0xe000
    115a:	f997 2007 	ldrsb.w	r2, [r7, #7]
    115e:	ea4f 1252 	mov.w	r2, r2, lsr #5
    1162:	79f9      	ldrb	r1, [r7, #7]
    1164:	f001 011f 	and.w	r1, r1, #31
    1168:	f04f 0001 	mov.w	r0, #1
    116c:	fa00 f101 	lsl.w	r1, r0, r1
    1170:	f102 0260 	add.w	r2, r2, #96	; 0x60
    1174:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
}
    1178:	f107 070c 	add.w	r7, r7, #12
    117c:	46bd      	mov	sp, r7
    117e:	bc80      	pop	{r7}
    1180:	4770      	bx	lr
    1182:	bf00      	nop

00001184 <set_bit_reg8>:
static __INLINE void set_bit_reg16(volatile uint16_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    1184:	b480      	push	{r7}
    1186:	b083      	sub	sp, #12
    1188:	af00      	add	r7, sp, #0
    118a:	6078      	str	r0, [r7, #4]
    118c:	460b      	mov	r3, r1
    118e:	70fb      	strb	r3, [r7, #3]
    HW_REG_BIT(reg,bit) = 0x1;
    1190:	687b      	ldr	r3, [r7, #4]
    1192:	f003 4270 	and.w	r2, r3, #4026531840	; 0xf0000000
    1196:	687b      	ldr	r3, [r7, #4]
    1198:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
    119c:	f423 0370 	bic.w	r3, r3, #15728640	; 0xf00000
    11a0:	ea4f 1343 	mov.w	r3, r3, lsl #5
    11a4:	441a      	add	r2, r3
    11a6:	78fb      	ldrb	r3, [r7, #3]
    11a8:	ea4f 0383 	mov.w	r3, r3, lsl #2
    11ac:	4413      	add	r3, r2
    11ae:	f103 7300 	add.w	r3, r3, #33554432	; 0x2000000
    11b2:	f04f 0201 	mov.w	r2, #1
    11b6:	601a      	str	r2, [r3, #0]
}
    11b8:	f107 070c 	add.w	r7, r7, #12
    11bc:	46bd      	mov	sp, r7
    11be:	bc80      	pop	{r7}
    11c0:	4770      	bx	lr
    11c2:	bf00      	nop

000011c4 <clear_bit_reg8>:
static __INLINE void clear_bit_reg16(volatile uint16_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    11c4:	b480      	push	{r7}
    11c6:	b083      	sub	sp, #12
    11c8:	af00      	add	r7, sp, #0
    11ca:	6078      	str	r0, [r7, #4]
    11cc:	460b      	mov	r3, r1
    11ce:	70fb      	strb	r3, [r7, #3]
    HW_REG_BIT(reg,bit) = 0x0;
    11d0:	687b      	ldr	r3, [r7, #4]
    11d2:	f003 4270 	and.w	r2, r3, #4026531840	; 0xf0000000
    11d6:	687b      	ldr	r3, [r7, #4]
    11d8:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
    11dc:	f423 0370 	bic.w	r3, r3, #15728640	; 0xf00000
    11e0:	ea4f 1343 	mov.w	r3, r3, lsl #5
    11e4:	441a      	add	r2, r3
    11e6:	78fb      	ldrb	r3, [r7, #3]
    11e8:	ea4f 0383 	mov.w	r3, r3, lsl #2
    11ec:	4413      	add	r3, r2
    11ee:	f103 7300 	add.w	r3, r3, #33554432	; 0x2000000
    11f2:	f04f 0200 	mov.w	r2, #0
    11f6:	601a      	str	r2, [r3, #0]
}
    11f8:	f107 070c 	add.w	r7, r7, #12
    11fc:	46bd      	mov	sp, r7
    11fe:	bc80      	pop	{r7}
    1200:	4770      	bx	lr
    1202:	bf00      	nop

00001204 <read_bit_reg8>:
static __INLINE uint8_t read_bit_reg16(volatile uint16_t * reg, uint8_t bit)
{
    return (HW_REG_BIT(reg,bit));
}
static __INLINE uint8_t read_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    1204:	b480      	push	{r7}
    1206:	b083      	sub	sp, #12
    1208:	af00      	add	r7, sp, #0
    120a:	6078      	str	r0, [r7, #4]
    120c:	460b      	mov	r3, r1
    120e:	70fb      	strb	r3, [r7, #3]
    return (HW_REG_BIT(reg,bit));
    1210:	687b      	ldr	r3, [r7, #4]
    1212:	f003 4270 	and.w	r2, r3, #4026531840	; 0xf0000000
    1216:	687b      	ldr	r3, [r7, #4]
    1218:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
    121c:	f423 0370 	bic.w	r3, r3, #15728640	; 0xf00000
    1220:	ea4f 1343 	mov.w	r3, r3, lsl #5
    1224:	441a      	add	r2, r3
    1226:	78fb      	ldrb	r3, [r7, #3]
    1228:	ea4f 0383 	mov.w	r3, r3, lsl #2
    122c:	4413      	add	r3, r2
    122e:	f103 7300 	add.w	r3, r3, #33554432	; 0x2000000
    1232:	681b      	ldr	r3, [r3, #0]
    1234:	b2db      	uxtb	r3, r3
}
    1236:	4618      	mov	r0, r3
    1238:	f107 070c 	add.w	r7, r7, #12
    123c:	46bd      	mov	sp, r7
    123e:	bc80      	pop	{r7}
    1240:	4770      	bx	lr
    1242:	bf00      	nop

00001244 <MSS_UART_init>:
(
    mss_uart_instance_t* this_uart, 
    uint32_t baud_rate,
    uint8_t line_config
)
{
    1244:	b580      	push	{r7, lr}
    1246:	b084      	sub	sp, #16
    1248:	af00      	add	r7, sp, #0
    124a:	60f8      	str	r0, [r7, #12]
    124c:	60b9      	str	r1, [r7, #8]
    124e:	4613      	mov	r3, r2
    1250:	71fb      	strb	r3, [r7, #7]
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    1252:	68fa      	ldr	r2, [r7, #12]
    1254:	f240 13f8 	movw	r3, #504	; 0x1f8
    1258:	f2c2 0300 	movt	r3, #8192	; 0x2000
    125c:	429a      	cmp	r2, r3
    125e:	d007      	beq.n	1270 <MSS_UART_init+0x2c>
    1260:	68fa      	ldr	r2, [r7, #12]
    1262:	f240 13b8 	movw	r3, #440	; 0x1b8
    1266:	f2c2 0300 	movt	r3, #8192	; 0x2000
    126a:	429a      	cmp	r2, r3
    126c:	d000      	beq.n	1270 <MSS_UART_init+0x2c>
    126e:	be00      	bkpt	0x0000

    /* Perform generic initialization */
    global_init(this_uart, baud_rate, line_config);
    1270:	79fb      	ldrb	r3, [r7, #7]
    1272:	68f8      	ldr	r0, [r7, #12]
    1274:	68b9      	ldr	r1, [r7, #8]
    1276:	461a      	mov	r2, r3
    1278:	f001 fc8e 	bl	2b98 <global_init>

    /* Disable LIN mode */
    clear_bit_reg8(&this_uart->hw_reg->MM0, ELIN);
    127c:	68fb      	ldr	r3, [r7, #12]
    127e:	681b      	ldr	r3, [r3, #0]
    1280:	f103 0330 	add.w	r3, r3, #48	; 0x30
    1284:	4618      	mov	r0, r3
    1286:	f04f 0103 	mov.w	r1, #3
    128a:	f7ff ff9b 	bl	11c4 <clear_bit_reg8>

    /* Disable IrDA mode */
    clear_bit_reg8(&this_uart->hw_reg->MM1, EIRD);
    128e:	68fb      	ldr	r3, [r7, #12]
    1290:	681b      	ldr	r3, [r3, #0]
    1292:	f103 0334 	add.w	r3, r3, #52	; 0x34
    1296:	4618      	mov	r0, r3
    1298:	f04f 0102 	mov.w	r1, #2
    129c:	f7ff ff92 	bl	11c4 <clear_bit_reg8>

    /* Disable SmartCard Mode */
    clear_bit_reg8(&this_uart->hw_reg->MM2, EERR);
    12a0:	68fb      	ldr	r3, [r7, #12]
    12a2:	681b      	ldr	r3, [r3, #0]
    12a4:	f103 0338 	add.w	r3, r3, #56	; 0x38
    12a8:	4618      	mov	r0, r3
    12aa:	f04f 0100 	mov.w	r1, #0
    12ae:	f7ff ff89 	bl	11c4 <clear_bit_reg8>

    /* set default tx handler for automated TX using interrupt in USART mode */
    this_uart->tx_handler = default_tx_handler;
    12b2:	68fa      	ldr	r2, [r7, #12]
    12b4:	f243 0331 	movw	r3, #12337	; 0x3031
    12b8:	f2c0 0300 	movt	r3, #0
    12bc:	6253      	str	r3, [r2, #36]	; 0x24
}
    12be:	f107 0710 	add.w	r7, r7, #16
    12c2:	46bd      	mov	sp, r7
    12c4:	bd80      	pop	{r7, pc}
    12c6:	bf00      	nop

000012c8 <MSS_UART_lin_init>:
(
    mss_uart_instance_t* this_uart, 
    uint32_t baud_rate,
    uint8_t line_config
)
{
    12c8:	b580      	push	{r7, lr}
    12ca:	b084      	sub	sp, #16
    12cc:	af00      	add	r7, sp, #0
    12ce:	60f8      	str	r0, [r7, #12]
    12d0:	60b9      	str	r1, [r7, #8]
    12d2:	4613      	mov	r3, r2
    12d4:	71fb      	strb	r3, [r7, #7]
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    12d6:	68fa      	ldr	r2, [r7, #12]
    12d8:	f240 13f8 	movw	r3, #504	; 0x1f8
    12dc:	f2c2 0300 	movt	r3, #8192	; 0x2000
    12e0:	429a      	cmp	r2, r3
    12e2:	d007      	beq.n	12f4 <MSS_UART_lin_init+0x2c>
    12e4:	68fa      	ldr	r2, [r7, #12]
    12e6:	f240 13b8 	movw	r3, #440	; 0x1b8
    12ea:	f2c2 0300 	movt	r3, #8192	; 0x2000
    12ee:	429a      	cmp	r2, r3
    12f0:	d000      	beq.n	12f4 <MSS_UART_lin_init+0x2c>
    12f2:	be00      	bkpt	0x0000

    /* Perform generic initialization */
    global_init(this_uart, baud_rate, line_config);
    12f4:	79fb      	ldrb	r3, [r7, #7]
    12f6:	68f8      	ldr	r0, [r7, #12]
    12f8:	68b9      	ldr	r1, [r7, #8]
    12fa:	461a      	mov	r2, r3
    12fc:	f001 fc4c 	bl	2b98 <global_init>

     /* Enable LIN mode */
    set_bit_reg8(&this_uart->hw_reg->MM0, ELIN);
    1300:	68fb      	ldr	r3, [r7, #12]
    1302:	681b      	ldr	r3, [r3, #0]
    1304:	f103 0330 	add.w	r3, r3, #48	; 0x30
    1308:	4618      	mov	r0, r3
    130a:	f04f 0103 	mov.w	r1, #3
    130e:	f7ff ff39 	bl	1184 <set_bit_reg8>

    /* Disable IrDA mode */
    clear_bit_reg8(&this_uart->hw_reg->MM1, EIRD);
    1312:	68fb      	ldr	r3, [r7, #12]
    1314:	681b      	ldr	r3, [r3, #0]
    1316:	f103 0334 	add.w	r3, r3, #52	; 0x34
    131a:	4618      	mov	r0, r3
    131c:	f04f 0102 	mov.w	r1, #2
    1320:	f7ff ff50 	bl	11c4 <clear_bit_reg8>

    /* Disable SmartCard Mode */
    clear_bit_reg8(&this_uart->hw_reg->MM2, EERR);
    1324:	68fb      	ldr	r3, [r7, #12]
    1326:	681b      	ldr	r3, [r3, #0]
    1328:	f103 0338 	add.w	r3, r3, #56	; 0x38
    132c:	4618      	mov	r0, r3
    132e:	f04f 0100 	mov.w	r1, #0
    1332:	f7ff ff47 	bl	11c4 <clear_bit_reg8>
}
    1336:	f107 0710 	add.w	r7, r7, #16
    133a:	46bd      	mov	sp, r7
    133c:	bd80      	pop	{r7, pc}
    133e:	bf00      	nop

00001340 <MSS_UART_irda_init>:
    uint8_t line_config,
    mss_uart_rzi_polarity_t rxpol,
    mss_uart_rzi_polarity_t txpol,
    mss_uart_rzi_pulsewidth_t pw
)
{
    1340:	b580      	push	{r7, lr}
    1342:	b084      	sub	sp, #16
    1344:	af00      	add	r7, sp, #0
    1346:	60f8      	str	r0, [r7, #12]
    1348:	60b9      	str	r1, [r7, #8]
    134a:	71fa      	strb	r2, [r7, #7]
    134c:	71bb      	strb	r3, [r7, #6]
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    134e:	68fa      	ldr	r2, [r7, #12]
    1350:	f240 13f8 	movw	r3, #504	; 0x1f8
    1354:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1358:	429a      	cmp	r2, r3
    135a:	d007      	beq.n	136c <MSS_UART_irda_init+0x2c>
    135c:	68fa      	ldr	r2, [r7, #12]
    135e:	f240 13b8 	movw	r3, #440	; 0x1b8
    1362:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1366:	429a      	cmp	r2, r3
    1368:	d000      	beq.n	136c <MSS_UART_irda_init+0x2c>
    136a:	be00      	bkpt	0x0000

    /* Perform generic initialization */
    global_init(this_uart, baud_rate, line_config);
    136c:	79fb      	ldrb	r3, [r7, #7]
    136e:	68f8      	ldr	r0, [r7, #12]
    1370:	68b9      	ldr	r1, [r7, #8]
    1372:	461a      	mov	r2, r3
    1374:	f001 fc10 	bl	2b98 <global_init>

     /* Enable LIN mode */
    clear_bit_reg8(&this_uart->hw_reg->MM0, ELIN);
    1378:	68fb      	ldr	r3, [r7, #12]
    137a:	681b      	ldr	r3, [r3, #0]
    137c:	f103 0330 	add.w	r3, r3, #48	; 0x30
    1380:	4618      	mov	r0, r3
    1382:	f04f 0103 	mov.w	r1, #3
    1386:	f7ff ff1d 	bl	11c4 <clear_bit_reg8>

    /* Disable IrDA mode */
    set_bit_reg8(&this_uart->hw_reg->MM1, EIRD);
    138a:	68fb      	ldr	r3, [r7, #12]
    138c:	681b      	ldr	r3, [r3, #0]
    138e:	f103 0334 	add.w	r3, r3, #52	; 0x34
    1392:	4618      	mov	r0, r3
    1394:	f04f 0102 	mov.w	r1, #2
    1398:	f7ff fef4 	bl	1184 <set_bit_reg8>
    ((rxpol == MSS_UART_ACTIVE_LOW) ? clear_bit_reg8(&this_uart->hw_reg->MM1,EIRX) : 
    139c:	79bb      	ldrb	r3, [r7, #6]
    139e:	2b00      	cmp	r3, #0
    13a0:	d109      	bne.n	13b6 <MSS_UART_irda_init+0x76>
    13a2:	68fb      	ldr	r3, [r7, #12]
    13a4:	681b      	ldr	r3, [r3, #0]
    13a6:	f103 0334 	add.w	r3, r3, #52	; 0x34
    13aa:	4618      	mov	r0, r3
    13ac:	f04f 0103 	mov.w	r1, #3
    13b0:	f7ff ff08 	bl	11c4 <clear_bit_reg8>
    13b4:	e008      	b.n	13c8 <MSS_UART_irda_init+0x88>
                                      set_bit_reg8(&this_uart->hw_reg->MM1,EIRX));
    13b6:	68fb      	ldr	r3, [r7, #12]
    13b8:	681b      	ldr	r3, [r3, #0]
    13ba:	f103 0334 	add.w	r3, r3, #52	; 0x34
    13be:	4618      	mov	r0, r3
    13c0:	f04f 0103 	mov.w	r1, #3
    13c4:	f7ff fede 	bl	1184 <set_bit_reg8>
                                      
    ((txpol == MSS_UART_ACTIVE_LOW) ? clear_bit_reg8(&this_uart->hw_reg->MM1,EITX) : 
    13c8:	7e3b      	ldrb	r3, [r7, #24]
    13ca:	2b00      	cmp	r3, #0
    13cc:	d109      	bne.n	13e2 <MSS_UART_irda_init+0xa2>
    13ce:	68fb      	ldr	r3, [r7, #12]
    13d0:	681b      	ldr	r3, [r3, #0]
    13d2:	f103 0334 	add.w	r3, r3, #52	; 0x34
    13d6:	4618      	mov	r0, r3
    13d8:	f04f 0104 	mov.w	r1, #4
    13dc:	f7ff fef2 	bl	11c4 <clear_bit_reg8>
    13e0:	e008      	b.n	13f4 <MSS_UART_irda_init+0xb4>
                                      set_bit_reg8(&this_uart->hw_reg->MM1,EITX));
    13e2:	68fb      	ldr	r3, [r7, #12]
    13e4:	681b      	ldr	r3, [r3, #0]
    13e6:	f103 0334 	add.w	r3, r3, #52	; 0x34
    13ea:	4618      	mov	r0, r3
    13ec:	f04f 0104 	mov.w	r1, #4
    13f0:	f7ff fec8 	bl	1184 <set_bit_reg8>
                                      
    ((pw == MSS_UART_3_BY_16) ? clear_bit_reg8(&this_uart->hw_reg->MM1,EITP) : 
    13f4:	7f3b      	ldrb	r3, [r7, #28]
    13f6:	2b00      	cmp	r3, #0
    13f8:	d109      	bne.n	140e <MSS_UART_irda_init+0xce>
    13fa:	68fb      	ldr	r3, [r7, #12]
    13fc:	681b      	ldr	r3, [r3, #0]
    13fe:	f103 0334 	add.w	r3, r3, #52	; 0x34
    1402:	4618      	mov	r0, r3
    1404:	f04f 0105 	mov.w	r1, #5
    1408:	f7ff fedc 	bl	11c4 <clear_bit_reg8>
    140c:	e008      	b.n	1420 <MSS_UART_irda_init+0xe0>
                                      set_bit_reg8(&this_uart->hw_reg->MM1,EITP));
    140e:	68fb      	ldr	r3, [r7, #12]
    1410:	681b      	ldr	r3, [r3, #0]
    1412:	f103 0334 	add.w	r3, r3, #52	; 0x34
    1416:	4618      	mov	r0, r3
    1418:	f04f 0105 	mov.w	r1, #5
    141c:	f7ff feb2 	bl	1184 <set_bit_reg8>
    /* Disable SmartCard Mode */
    clear_bit_reg8(&this_uart->hw_reg->MM2, EERR);
    1420:	68fb      	ldr	r3, [r7, #12]
    1422:	681b      	ldr	r3, [r3, #0]
    1424:	f103 0338 	add.w	r3, r3, #56	; 0x38
    1428:	4618      	mov	r0, r3
    142a:	f04f 0100 	mov.w	r1, #0
    142e:	f7ff fec9 	bl	11c4 <clear_bit_reg8>
}
    1432:	f107 0710 	add.w	r7, r7, #16
    1436:	46bd      	mov	sp, r7
    1438:	bd80      	pop	{r7, pc}
    143a:	bf00      	nop

0000143c <MSS_UART_smartcard_init>:
(
    mss_uart_instance_t* this_uart, 
    uint32_t baud_rate,
    uint8_t line_config
)
{
    143c:	b580      	push	{r7, lr}
    143e:	b084      	sub	sp, #16
    1440:	af00      	add	r7, sp, #0
    1442:	60f8      	str	r0, [r7, #12]
    1444:	60b9      	str	r1, [r7, #8]
    1446:	4613      	mov	r3, r2
    1448:	71fb      	strb	r3, [r7, #7]
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    144a:	68fa      	ldr	r2, [r7, #12]
    144c:	f240 13f8 	movw	r3, #504	; 0x1f8
    1450:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1454:	429a      	cmp	r2, r3
    1456:	d007      	beq.n	1468 <MSS_UART_smartcard_init+0x2c>
    1458:	68fa      	ldr	r2, [r7, #12]
    145a:	f240 13b8 	movw	r3, #440	; 0x1b8
    145e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1462:	429a      	cmp	r2, r3
    1464:	d000      	beq.n	1468 <MSS_UART_smartcard_init+0x2c>
    1466:	be00      	bkpt	0x0000

    /* Perform generic initialization */
    global_init(this_uart, baud_rate, line_config);
    1468:	79fb      	ldrb	r3, [r7, #7]
    146a:	68f8      	ldr	r0, [r7, #12]
    146c:	68b9      	ldr	r1, [r7, #8]
    146e:	461a      	mov	r2, r3
    1470:	f001 fb92 	bl	2b98 <global_init>
    
    /* Disable LIN mode */
    clear_bit_reg8(&this_uart->hw_reg->MM0, ELIN);
    1474:	68fb      	ldr	r3, [r7, #12]
    1476:	681b      	ldr	r3, [r3, #0]
    1478:	f103 0330 	add.w	r3, r3, #48	; 0x30
    147c:	4618      	mov	r0, r3
    147e:	f04f 0103 	mov.w	r1, #3
    1482:	f7ff fe9f 	bl	11c4 <clear_bit_reg8>

    /* Disable IrDA mode */
    clear_bit_reg8(&this_uart->hw_reg->MM1, EIRD);
    1486:	68fb      	ldr	r3, [r7, #12]
    1488:	681b      	ldr	r3, [r3, #0]
    148a:	f103 0334 	add.w	r3, r3, #52	; 0x34
    148e:	4618      	mov	r0, r3
    1490:	f04f 0102 	mov.w	r1, #2
    1494:	f7ff fe96 	bl	11c4 <clear_bit_reg8>

    /* Enable SmartCard Mode : Only when data is 8-bit and 2 stop bits*/
    if( ( MSS_UART_DATA_8_BITS | MSS_UART_TWO_STOP_BITS) == 
        (line_config & (MSS_UART_DATA_8_BITS | MSS_UART_TWO_STOP_BITS)))
    1498:	79fb      	ldrb	r3, [r7, #7]
    149a:	f003 0307 	and.w	r3, r3, #7

    /* Disable IrDA mode */
    clear_bit_reg8(&this_uart->hw_reg->MM1, EIRD);

    /* Enable SmartCard Mode : Only when data is 8-bit and 2 stop bits*/
    if( ( MSS_UART_DATA_8_BITS | MSS_UART_TWO_STOP_BITS) == 
    149e:	2b07      	cmp	r3, #7
    14a0:	d111      	bne.n	14c6 <MSS_UART_smartcard_init+0x8a>
        (line_config & (MSS_UART_DATA_8_BITS | MSS_UART_TWO_STOP_BITS)))
    {
        set_bit_reg8(&this_uart->hw_reg->MM2, EERR);    
    14a2:	68fb      	ldr	r3, [r7, #12]
    14a4:	681b      	ldr	r3, [r3, #0]
    14a6:	f103 0338 	add.w	r3, r3, #56	; 0x38
    14aa:	4618      	mov	r0, r3
    14ac:	f04f 0100 	mov.w	r1, #0
    14b0:	f7ff fe68 	bl	1184 <set_bit_reg8>
        /* Enable single wire half-duplex mode */
        set_bit_reg8(&this_uart->hw_reg->MM2,ESWM);
    14b4:	68fb      	ldr	r3, [r7, #12]
    14b6:	681b      	ldr	r3, [r3, #0]
    14b8:	f103 0338 	add.w	r3, r3, #56	; 0x38
    14bc:	4618      	mov	r0, r3
    14be:	f04f 0103 	mov.w	r1, #3
    14c2:	f7ff fe5f 	bl	1184 <set_bit_reg8>
    }
}
    14c6:	f107 0710 	add.w	r7, r7, #16
    14ca:	46bd      	mov	sp, r7
    14cc:	bd80      	pop	{r7, pc}
    14ce:	bf00      	nop

000014d0 <MSS_UART_polled_tx>:
(
    mss_uart_instance_t * this_uart,
    const uint8_t * pbuff,
    uint32_t tx_size
)
{
    14d0:	b480      	push	{r7}
    14d2:	b089      	sub	sp, #36	; 0x24
    14d4:	af00      	add	r7, sp, #0
    14d6:	60f8      	str	r0, [r7, #12]
    14d8:	60b9      	str	r1, [r7, #8]
    14da:	607a      	str	r2, [r7, #4]
    uint32_t char_idx = 0u;
    14dc:	f04f 0300 	mov.w	r3, #0
    14e0:	613b      	str	r3, [r7, #16]
    uint32_t size_sent;
    uint8_t status;

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    14e2:	68fa      	ldr	r2, [r7, #12]
    14e4:	f240 13f8 	movw	r3, #504	; 0x1f8
    14e8:	f2c2 0300 	movt	r3, #8192	; 0x2000
    14ec:	429a      	cmp	r2, r3
    14ee:	d007      	beq.n	1500 <MSS_UART_polled_tx+0x30>
    14f0:	68fa      	ldr	r2, [r7, #12]
    14f2:	f240 13b8 	movw	r3, #440	; 0x1b8
    14f6:	f2c2 0300 	movt	r3, #8192	; 0x2000
    14fa:	429a      	cmp	r2, r3
    14fc:	d000      	beq.n	1500 <MSS_UART_polled_tx+0x30>
    14fe:	be00      	bkpt	0x0000
    ASSERT(pbuff != ( (uint8_t *)0));
    1500:	68bb      	ldr	r3, [r7, #8]
    1502:	2b00      	cmp	r3, #0
    1504:	d100      	bne.n	1508 <MSS_UART_polled_tx+0x38>
    1506:	be00      	bkpt	0x0000
    ASSERT(tx_size > 0u);
    1508:	687b      	ldr	r3, [r7, #4]
    150a:	2b00      	cmp	r3, #0
    150c:	d100      	bne.n	1510 <MSS_UART_polled_tx+0x40>
    150e:	be00      	bkpt	0x0000

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
    1510:	68fa      	ldr	r2, [r7, #12]
    1512:	f240 13f8 	movw	r3, #504	; 0x1f8
    1516:	f2c2 0300 	movt	r3, #8192	; 0x2000
    151a:	429a      	cmp	r2, r3
    151c:	d006      	beq.n	152c <MSS_UART_polled_tx+0x5c>
    151e:	68fa      	ldr	r2, [r7, #12]
    1520:	f240 13b8 	movw	r3, #440	; 0x1b8
    1524:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1528:	429a      	cmp	r2, r3
    152a:	d13d      	bne.n	15a8 <MSS_UART_polled_tx+0xd8>
    152c:	68bb      	ldr	r3, [r7, #8]
    152e:	2b00      	cmp	r3, #0
    1530:	d03a      	beq.n	15a8 <MSS_UART_polled_tx+0xd8>
    1532:	687b      	ldr	r3, [r7, #4]
    1534:	2b00      	cmp	r3, #0
    1536:	d037      	beq.n	15a8 <MSS_UART_polled_tx+0xd8>
         /* Remain in this loop until the entire input buffer
          * has been transferred to the UART.
          */
        do {
            /* Read the Line Status Register and update the sticky record */
            status = this_uart->hw_reg->LSR;
    1538:	68fb      	ldr	r3, [r7, #12]
    153a:	681b      	ldr	r3, [r3, #0]
    153c:	7d1b      	ldrb	r3, [r3, #20]
    153e:	76fb      	strb	r3, [r7, #27]
            this_uart->status |= status;
    1540:	68fb      	ldr	r3, [r7, #12]
    1542:	7b5a      	ldrb	r2, [r3, #13]
    1544:	7efb      	ldrb	r3, [r7, #27]
    1546:	ea42 0303 	orr.w	r3, r2, r3
    154a:	b2da      	uxtb	r2, r3
    154c:	68fb      	ldr	r3, [r7, #12]
    154e:	735a      	strb	r2, [r3, #13]

            /* Check if TX FIFO is empty. */
            if(status & MSS_UART_THRE)
    1550:	7efb      	ldrb	r3, [r7, #27]
    1552:	f003 0320 	and.w	r3, r3, #32
    1556:	2b00      	cmp	r3, #0
    1558:	d023      	beq.n	15a2 <MSS_UART_polled_tx+0xd2>
            {
                uint32_t fill_size = TX_FIFO_SIZE;
    155a:	f04f 0310 	mov.w	r3, #16
    155e:	61fb      	str	r3, [r7, #28]

                /* Calculate the number of bytes to transmit. */
                if(tx_size < TX_FIFO_SIZE)
    1560:	687b      	ldr	r3, [r7, #4]
    1562:	2b0f      	cmp	r3, #15
    1564:	d801      	bhi.n	156a <MSS_UART_polled_tx+0x9a>
                {
                    fill_size = tx_size;
    1566:	687b      	ldr	r3, [r7, #4]
    1568:	61fb      	str	r3, [r7, #28]
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
    156a:	f04f 0300 	mov.w	r3, #0
    156e:	617b      	str	r3, [r7, #20]
    1570:	e00e      	b.n	1590 <MSS_UART_polled_tx+0xc0>
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
    1572:	68fb      	ldr	r3, [r7, #12]
    1574:	681b      	ldr	r3, [r3, #0]
    1576:	68b9      	ldr	r1, [r7, #8]
    1578:	693a      	ldr	r2, [r7, #16]
    157a:	440a      	add	r2, r1
    157c:	7812      	ldrb	r2, [r2, #0]
    157e:	701a      	strb	r2, [r3, #0]
                    char_idx++;
    1580:	693b      	ldr	r3, [r7, #16]
    1582:	f103 0301 	add.w	r3, r3, #1
    1586:	613b      	str	r3, [r7, #16]
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
    1588:	697b      	ldr	r3, [r7, #20]
    158a:	f103 0301 	add.w	r3, r3, #1
    158e:	617b      	str	r3, [r7, #20]
    1590:	697a      	ldr	r2, [r7, #20]
    1592:	69fb      	ldr	r3, [r7, #28]
    1594:	429a      	cmp	r2, r3
    1596:	d3ec      	bcc.n	1572 <MSS_UART_polled_tx+0xa2>
                    this_uart->hw_reg->THR = pbuff[char_idx];
                    char_idx++;
                }

                /* Calculate the number of untransmitted bytes remaining. */
                tx_size -= size_sent;
    1598:	687a      	ldr	r2, [r7, #4]
    159a:	697b      	ldr	r3, [r7, #20]
    159c:	ebc3 0302 	rsb	r3, r3, r2
    15a0:	607b      	str	r3, [r7, #4]
            }
        } while(tx_size);
    15a2:	687b      	ldr	r3, [r7, #4]
    15a4:	2b00      	cmp	r3, #0
    15a6:	d1c7      	bne.n	1538 <MSS_UART_polled_tx+0x68>
    }
}
    15a8:	f107 0724 	add.w	r7, r7, #36	; 0x24
    15ac:	46bd      	mov	sp, r7
    15ae:	bc80      	pop	{r7}
    15b0:	4770      	bx	lr
    15b2:	bf00      	nop

000015b4 <MSS_UART_polled_tx_string>:
MSS_UART_polled_tx_string
(
    mss_uart_instance_t * this_uart,
    const uint8_t * p_sz_string
)
{
    15b4:	b480      	push	{r7}
    15b6:	b087      	sub	sp, #28
    15b8:	af00      	add	r7, sp, #0
    15ba:	6078      	str	r0, [r7, #4]
    15bc:	6039      	str	r1, [r7, #0]
    uint32_t char_idx = 0u;
    15be:	f04f 0300 	mov.w	r3, #0
    15c2:	60fb      	str	r3, [r7, #12]
    uint32_t fill_size;
    uint8_t data_byte;
    uint8_t status;

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    15c4:	687a      	ldr	r2, [r7, #4]
    15c6:	f240 13f8 	movw	r3, #504	; 0x1f8
    15ca:	f2c2 0300 	movt	r3, #8192	; 0x2000
    15ce:	429a      	cmp	r2, r3
    15d0:	d007      	beq.n	15e2 <MSS_UART_polled_tx_string+0x2e>
    15d2:	687a      	ldr	r2, [r7, #4]
    15d4:	f240 13b8 	movw	r3, #440	; 0x1b8
    15d8:	f2c2 0300 	movt	r3, #8192	; 0x2000
    15dc:	429a      	cmp	r2, r3
    15de:	d000      	beq.n	15e2 <MSS_UART_polled_tx_string+0x2e>
    15e0:	be00      	bkpt	0x0000
    ASSERT(p_sz_string != ((uint8_t *)0));
    15e2:	683b      	ldr	r3, [r7, #0]
    15e4:	2b00      	cmp	r3, #0
    15e6:	d100      	bne.n	15ea <MSS_UART_polled_tx_string+0x36>
    15e8:	be00      	bkpt	0x0000

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
    15ea:	687a      	ldr	r2, [r7, #4]
    15ec:	f240 13f8 	movw	r3, #504	; 0x1f8
    15f0:	f2c2 0300 	movt	r3, #8192	; 0x2000
    15f4:	429a      	cmp	r2, r3
    15f6:	d006      	beq.n	1606 <MSS_UART_polled_tx_string+0x52>
    15f8:	687a      	ldr	r2, [r7, #4]
    15fa:	f240 13b8 	movw	r3, #440	; 0x1b8
    15fe:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1602:	429a      	cmp	r2, r3
    1604:	d137      	bne.n	1676 <MSS_UART_polled_tx_string+0xc2>
    1606:	683b      	ldr	r3, [r7, #0]
    1608:	2b00      	cmp	r3, #0
    160a:	d034      	beq.n	1676 <MSS_UART_polled_tx_string+0xc2>
       (p_sz_string != ((uint8_t *)0)))
    {
        /* Get the first data byte from the input buffer */
        data_byte = p_sz_string[char_idx];
    160c:	683a      	ldr	r2, [r7, #0]
    160e:	68fb      	ldr	r3, [r7, #12]
    1610:	4413      	add	r3, r2
    1612:	781b      	ldrb	r3, [r3, #0]
    1614:	75bb      	strb	r3, [r7, #22]

        /* First check for the NULL terminator byte.
         * Then remain in this loop until the entire string in the input buffer
         * has been transferred to the UART.
         */
        while(0u != data_byte)
    1616:	e02b      	b.n	1670 <MSS_UART_polled_tx_string+0xbc>
        {
            /* Wait until TX FIFO is empty. */
            do {
                status = this_uart->hw_reg->LSR;
    1618:	687b      	ldr	r3, [r7, #4]
    161a:	681b      	ldr	r3, [r3, #0]
    161c:	7d1b      	ldrb	r3, [r3, #20]
    161e:	75fb      	strb	r3, [r7, #23]
                this_uart->status |= status;
    1620:	687b      	ldr	r3, [r7, #4]
    1622:	7b5a      	ldrb	r2, [r3, #13]
    1624:	7dfb      	ldrb	r3, [r7, #23]
    1626:	ea42 0303 	orr.w	r3, r2, r3
    162a:	b2da      	uxtb	r2, r3
    162c:	687b      	ldr	r3, [r7, #4]
    162e:	735a      	strb	r2, [r3, #13]
            } while (0u == (status & MSS_UART_THRE));
    1630:	7dfb      	ldrb	r3, [r7, #23]
    1632:	f003 0320 	and.w	r3, r3, #32
    1636:	2b00      	cmp	r3, #0
    1638:	d0ee      	beq.n	1618 <MSS_UART_polled_tx_string+0x64>

            /* Send bytes from the input buffer until the TX FIFO is full
             * or we reach the NULL terminator byte.
             */
            fill_size = 0u;
    163a:	f04f 0300 	mov.w	r3, #0
    163e:	613b      	str	r3, [r7, #16]
            while((0u != data_byte) && (fill_size < TX_FIFO_SIZE))
    1640:	e010      	b.n	1664 <MSS_UART_polled_tx_string+0xb0>
            {
                /* Send the data byte */
                this_uart->hw_reg->THR = data_byte;
    1642:	687b      	ldr	r3, [r7, #4]
    1644:	681b      	ldr	r3, [r3, #0]
    1646:	7dba      	ldrb	r2, [r7, #22]
    1648:	701a      	strb	r2, [r3, #0]
                ++fill_size;
    164a:	693b      	ldr	r3, [r7, #16]
    164c:	f103 0301 	add.w	r3, r3, #1
    1650:	613b      	str	r3, [r7, #16]
                char_idx++;
    1652:	68fb      	ldr	r3, [r7, #12]
    1654:	f103 0301 	add.w	r3, r3, #1
    1658:	60fb      	str	r3, [r7, #12]
                /* Get the next data byte from the input buffer */
                data_byte = p_sz_string[char_idx];
    165a:	683a      	ldr	r2, [r7, #0]
    165c:	68fb      	ldr	r3, [r7, #12]
    165e:	4413      	add	r3, r2
    1660:	781b      	ldrb	r3, [r3, #0]
    1662:	75bb      	strb	r3, [r7, #22]

            /* Send bytes from the input buffer until the TX FIFO is full
             * or we reach the NULL terminator byte.
             */
            fill_size = 0u;
            while((0u != data_byte) && (fill_size < TX_FIFO_SIZE))
    1664:	7dbb      	ldrb	r3, [r7, #22]
    1666:	2b00      	cmp	r3, #0
    1668:	d002      	beq.n	1670 <MSS_UART_polled_tx_string+0xbc>
    166a:	693b      	ldr	r3, [r7, #16]
    166c:	2b0f      	cmp	r3, #15
    166e:	d9e8      	bls.n	1642 <MSS_UART_polled_tx_string+0x8e>

        /* First check for the NULL terminator byte.
         * Then remain in this loop until the entire string in the input buffer
         * has been transferred to the UART.
         */
        while(0u != data_byte)
    1670:	7dbb      	ldrb	r3, [r7, #22]
    1672:	2b00      	cmp	r3, #0
    1674:	d1d0      	bne.n	1618 <MSS_UART_polled_tx_string+0x64>
                /* Get the next data byte from the input buffer */
                data_byte = p_sz_string[char_idx];
            }
        }
    }
}
    1676:	f107 071c 	add.w	r7, r7, #28
    167a:	46bd      	mov	sp, r7
    167c:	bc80      	pop	{r7}
    167e:	4770      	bx	lr

00001680 <MSS_UART_irq_tx>:
(
    mss_uart_instance_t * this_uart,
    const uint8_t * pbuff,
    uint32_t tx_size
)
{
    1680:	b580      	push	{r7, lr}
    1682:	b084      	sub	sp, #16
    1684:	af00      	add	r7, sp, #0
    1686:	60f8      	str	r0, [r7, #12]
    1688:	60b9      	str	r1, [r7, #8]
    168a:	607a      	str	r2, [r7, #4]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    168c:	68fa      	ldr	r2, [r7, #12]
    168e:	f240 13f8 	movw	r3, #504	; 0x1f8
    1692:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1696:	429a      	cmp	r2, r3
    1698:	d007      	beq.n	16aa <MSS_UART_irq_tx+0x2a>
    169a:	68fa      	ldr	r2, [r7, #12]
    169c:	f240 13b8 	movw	r3, #440	; 0x1b8
    16a0:	f2c2 0300 	movt	r3, #8192	; 0x2000
    16a4:	429a      	cmp	r2, r3
    16a6:	d000      	beq.n	16aa <MSS_UART_irq_tx+0x2a>
    16a8:	be00      	bkpt	0x0000
    ASSERT(pbuff != ((uint8_t *)0));
    16aa:	68bb      	ldr	r3, [r7, #8]
    16ac:	2b00      	cmp	r3, #0
    16ae:	d100      	bne.n	16b2 <MSS_UART_irq_tx+0x32>
    16b0:	be00      	bkpt	0x0000
    ASSERT(tx_size > 0u);
    16b2:	687b      	ldr	r3, [r7, #4]
    16b4:	2b00      	cmp	r3, #0
    16b6:	d100      	bne.n	16ba <MSS_UART_irq_tx+0x3a>
    16b8:	be00      	bkpt	0x0000

    if((tx_size > 0u) && ( pbuff != ((uint8_t *)0)) &&
    16ba:	687b      	ldr	r3, [r7, #4]
    16bc:	2b00      	cmp	r3, #0
    16be:	d035      	beq.n	172c <MSS_UART_irq_tx+0xac>
    16c0:	68bb      	ldr	r3, [r7, #8]
    16c2:	2b00      	cmp	r3, #0
    16c4:	d032      	beq.n	172c <MSS_UART_irq_tx+0xac>
      ((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)))
    16c6:	68fa      	ldr	r2, [r7, #12]
    16c8:	f240 13f8 	movw	r3, #504	; 0x1f8
    16cc:	f2c2 0300 	movt	r3, #8192	; 0x2000
    16d0:	429a      	cmp	r2, r3
    16d2:	d006      	beq.n	16e2 <MSS_UART_irq_tx+0x62>
    16d4:	68fa      	ldr	r2, [r7, #12]
    16d6:	f240 13b8 	movw	r3, #440	; 0x1b8
    16da:	f2c2 0300 	movt	r3, #8192	; 0x2000
    16de:	429a      	cmp	r2, r3
    16e0:	d124      	bne.n	172c <MSS_UART_irq_tx+0xac>
    {
        /*Initialise the transmit info for the UART instance with the arguments.*/
        this_uart->tx_buffer = pbuff;
    16e2:	68fb      	ldr	r3, [r7, #12]
    16e4:	68ba      	ldr	r2, [r7, #8]
    16e6:	611a      	str	r2, [r3, #16]
        this_uart->tx_buff_size = tx_size;
    16e8:	68fb      	ldr	r3, [r7, #12]
    16ea:	687a      	ldr	r2, [r7, #4]
    16ec:	615a      	str	r2, [r3, #20]
        this_uart->tx_idx = (uint16_t)0;
    16ee:	68fb      	ldr	r3, [r7, #12]
    16f0:	f04f 0200 	mov.w	r2, #0
    16f4:	619a      	str	r2, [r3, #24]

        /* Clear any previously pended interrupts */
        NVIC_ClearPendingIRQ(this_uart->irqn);
    16f6:	68fb      	ldr	r3, [r7, #12]
    16f8:	791b      	ldrb	r3, [r3, #4]
    16fa:	b25b      	sxtb	r3, r3
    16fc:	4618      	mov	r0, r3
    16fe:	f7ff fd23 	bl	1148 <NVIC_ClearPendingIRQ>

        /* assign default handler for data transfer */
        this_uart->tx_handler = default_tx_handler;
    1702:	68fa      	ldr	r2, [r7, #12]
    1704:	f243 0331 	movw	r3, #12337	; 0x3031
    1708:	f2c0 0300 	movt	r3, #0
    170c:	6253      	str	r3, [r2, #36]	; 0x24

        /* enables TX interrupt */
        set_bit_reg8(&this_uart->hw_reg->IER,ETBEI);
    170e:	68fb      	ldr	r3, [r7, #12]
    1710:	681b      	ldr	r3, [r3, #0]
    1712:	f103 0304 	add.w	r3, r3, #4
    1716:	4618      	mov	r0, r3
    1718:	f04f 0101 	mov.w	r1, #1
    171c:	f7ff fd32 	bl	1184 <set_bit_reg8>

        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
        NVIC_EnableIRQ(this_uart->irqn);
    1720:	68fb      	ldr	r3, [r7, #12]
    1722:	791b      	ldrb	r3, [r3, #4]
    1724:	b25b      	sxtb	r3, r3
    1726:	4618      	mov	r0, r3
    1728:	f7ff fcd4 	bl	10d4 <NVIC_EnableIRQ>
    }
}
    172c:	f107 0710 	add.w	r7, r7, #16
    1730:	46bd      	mov	sp, r7
    1732:	bd80      	pop	{r7, pc}

00001734 <MSS_UART_tx_complete>:
int8_t
MSS_UART_tx_complete
(
    mss_uart_instance_t * this_uart
)
{
    1734:	b480      	push	{r7}
    1736:	b085      	sub	sp, #20
    1738:	af00      	add	r7, sp, #0
    173a:	6078      	str	r0, [r7, #4]
    int8_t ret_value = 0;
    173c:	f04f 0300 	mov.w	r3, #0
    1740:	73bb      	strb	r3, [r7, #14]
    uint8_t status = 0u;
    1742:	f04f 0300 	mov.w	r3, #0
    1746:	73fb      	strb	r3, [r7, #15]

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    1748:	687a      	ldr	r2, [r7, #4]
    174a:	f240 13f8 	movw	r3, #504	; 0x1f8
    174e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1752:	429a      	cmp	r2, r3
    1754:	d007      	beq.n	1766 <MSS_UART_tx_complete+0x32>
    1756:	687a      	ldr	r2, [r7, #4]
    1758:	f240 13b8 	movw	r3, #440	; 0x1b8
    175c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1760:	429a      	cmp	r2, r3
    1762:	d000      	beq.n	1766 <MSS_UART_tx_complete+0x32>
    1764:	be00      	bkpt	0x0000

    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
    1766:	687a      	ldr	r2, [r7, #4]
    1768:	f240 13f8 	movw	r3, #504	; 0x1f8
    176c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1770:	429a      	cmp	r2, r3
    1772:	d006      	beq.n	1782 <MSS_UART_tx_complete+0x4e>
    1774:	687a      	ldr	r2, [r7, #4]
    1776:	f240 13b8 	movw	r3, #440	; 0x1b8
    177a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    177e:	429a      	cmp	r2, r3
    1780:	d117      	bne.n	17b2 <MSS_UART_tx_complete+0x7e>
    {
        /* Read the Line Status Register and update the sticky record. */
        status = this_uart->hw_reg->LSR;
    1782:	687b      	ldr	r3, [r7, #4]
    1784:	681b      	ldr	r3, [r3, #0]
    1786:	7d1b      	ldrb	r3, [r3, #20]
    1788:	73fb      	strb	r3, [r7, #15]
        this_uart->status |= status;
    178a:	687b      	ldr	r3, [r7, #4]
    178c:	7b5a      	ldrb	r2, [r3, #13]
    178e:	7bfb      	ldrb	r3, [r7, #15]
    1790:	ea42 0303 	orr.w	r3, r2, r3
    1794:	b2da      	uxtb	r2, r3
    1796:	687b      	ldr	r3, [r7, #4]
    1798:	735a      	strb	r2, [r3, #13]

        if((TX_COMPLETE == this_uart->tx_buff_size) &&
    179a:	687b      	ldr	r3, [r7, #4]
    179c:	695b      	ldr	r3, [r3, #20]
    179e:	2b00      	cmp	r3, #0
    17a0:	d107      	bne.n	17b2 <MSS_UART_tx_complete+0x7e>
           ((status & MSS_UART_TEMT) != 0u))
    17a2:	7bfb      	ldrb	r3, [r7, #15]
    17a4:	f003 0340 	and.w	r3, r3, #64	; 0x40
    {
        /* Read the Line Status Register and update the sticky record. */
        status = this_uart->hw_reg->LSR;
        this_uart->status |= status;

        if((TX_COMPLETE == this_uart->tx_buff_size) &&
    17a8:	2b00      	cmp	r3, #0
    17aa:	d002      	beq.n	17b2 <MSS_UART_tx_complete+0x7e>
           ((status & MSS_UART_TEMT) != 0u))
        {
            ret_value = (int8_t)1;
    17ac:	f04f 0301 	mov.w	r3, #1
    17b0:	73bb      	strb	r3, [r7, #14]
        }
    }
    return ret_value;
    17b2:	7bbb      	ldrb	r3, [r7, #14]
    17b4:	b25b      	sxtb	r3, r3
}
    17b6:	4618      	mov	r0, r3
    17b8:	f107 0714 	add.w	r7, r7, #20
    17bc:	46bd      	mov	sp, r7
    17be:	bc80      	pop	{r7}
    17c0:	4770      	bx	lr
    17c2:	bf00      	nop

000017c4 <MSS_UART_get_rx>:
(
    mss_uart_instance_t * this_uart,
    uint8_t * rx_buff,
    size_t buff_size
)
{
    17c4:	b480      	push	{r7}
    17c6:	b087      	sub	sp, #28
    17c8:	af00      	add	r7, sp, #0
    17ca:	60f8      	str	r0, [r7, #12]
    17cc:	60b9      	str	r1, [r7, #8]
    17ce:	607a      	str	r2, [r7, #4]
    size_t rx_size = 0u;
    17d0:	f04f 0300 	mov.w	r3, #0
    17d4:	613b      	str	r3, [r7, #16]
    uint8_t status = 0u;
    17d6:	f04f 0300 	mov.w	r3, #0
    17da:	75fb      	strb	r3, [r7, #23]

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    17dc:	68fa      	ldr	r2, [r7, #12]
    17de:	f240 13f8 	movw	r3, #504	; 0x1f8
    17e2:	f2c2 0300 	movt	r3, #8192	; 0x2000
    17e6:	429a      	cmp	r2, r3
    17e8:	d007      	beq.n	17fa <MSS_UART_get_rx+0x36>
    17ea:	68fa      	ldr	r2, [r7, #12]
    17ec:	f240 13b8 	movw	r3, #440	; 0x1b8
    17f0:	f2c2 0300 	movt	r3, #8192	; 0x2000
    17f4:	429a      	cmp	r2, r3
    17f6:	d000      	beq.n	17fa <MSS_UART_get_rx+0x36>
    17f8:	be00      	bkpt	0x0000
    ASSERT(rx_buff != ((uint8_t *)0));
    17fa:	68bb      	ldr	r3, [r7, #8]
    17fc:	2b00      	cmp	r3, #0
    17fe:	d100      	bne.n	1802 <MSS_UART_get_rx+0x3e>
    1800:	be00      	bkpt	0x0000
    ASSERT(buff_size > 0u);
    1802:	687b      	ldr	r3, [r7, #4]
    1804:	2b00      	cmp	r3, #0
    1806:	d100      	bne.n	180a <MSS_UART_get_rx+0x46>
    1808:	be00      	bkpt	0x0000

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
    180a:	68fa      	ldr	r2, [r7, #12]
    180c:	f240 13f8 	movw	r3, #504	; 0x1f8
    1810:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1814:	429a      	cmp	r2, r3
    1816:	d006      	beq.n	1826 <MSS_UART_get_rx+0x62>
    1818:	68fa      	ldr	r2, [r7, #12]
    181a:	f240 13b8 	movw	r3, #440	; 0x1b8
    181e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1822:	429a      	cmp	r2, r3
    1824:	d134      	bne.n	1890 <MSS_UART_get_rx+0xcc>
    1826:	68bb      	ldr	r3, [r7, #8]
    1828:	2b00      	cmp	r3, #0
    182a:	d031      	beq.n	1890 <MSS_UART_get_rx+0xcc>
    182c:	687b      	ldr	r3, [r7, #4]
    182e:	2b00      	cmp	r3, #0
    1830:	d02e      	beq.n	1890 <MSS_UART_get_rx+0xcc>
       (rx_buff != ((uint8_t *)0)) && (buff_size > 0u))
    {
        status = this_uart->hw_reg->LSR;
    1832:	68fb      	ldr	r3, [r7, #12]
    1834:	681b      	ldr	r3, [r3, #0]
    1836:	7d1b      	ldrb	r3, [r3, #20]
    1838:	75fb      	strb	r3, [r7, #23]
        this_uart->status |= status;
    183a:	68fb      	ldr	r3, [r7, #12]
    183c:	7b5a      	ldrb	r2, [r3, #13]
    183e:	7dfb      	ldrb	r3, [r7, #23]
    1840:	ea42 0303 	orr.w	r3, r2, r3
    1844:	b2da      	uxtb	r2, r3
    1846:	68fb      	ldr	r3, [r7, #12]
    1848:	735a      	strb	r2, [r3, #13]

        while(((status & MSS_UART_DATA_READY) != 0u) &&
    184a:	e017      	b.n	187c <MSS_UART_get_rx+0xb8>
              (rx_size < buff_size))
        {
            rx_buff[rx_size] = this_uart->hw_reg->RBR;
    184c:	68ba      	ldr	r2, [r7, #8]
    184e:	693b      	ldr	r3, [r7, #16]
    1850:	4413      	add	r3, r2
    1852:	68fa      	ldr	r2, [r7, #12]
    1854:	6812      	ldr	r2, [r2, #0]
    1856:	7812      	ldrb	r2, [r2, #0]
    1858:	b2d2      	uxtb	r2, r2
    185a:	701a      	strb	r2, [r3, #0]
            ++rx_size;
    185c:	693b      	ldr	r3, [r7, #16]
    185e:	f103 0301 	add.w	r3, r3, #1
    1862:	613b      	str	r3, [r7, #16]
            status = this_uart->hw_reg->LSR;
    1864:	68fb      	ldr	r3, [r7, #12]
    1866:	681b      	ldr	r3, [r3, #0]
    1868:	7d1b      	ldrb	r3, [r3, #20]
    186a:	75fb      	strb	r3, [r7, #23]
            this_uart->status |= status;
    186c:	68fb      	ldr	r3, [r7, #12]
    186e:	7b5a      	ldrb	r2, [r3, #13]
    1870:	7dfb      	ldrb	r3, [r7, #23]
    1872:	ea42 0303 	orr.w	r3, r2, r3
    1876:	b2da      	uxtb	r2, r3
    1878:	68fb      	ldr	r3, [r7, #12]
    187a:	735a      	strb	r2, [r3, #13]
       (rx_buff != ((uint8_t *)0)) && (buff_size > 0u))
    {
        status = this_uart->hw_reg->LSR;
        this_uart->status |= status;

        while(((status & MSS_UART_DATA_READY) != 0u) &&
    187c:	7dfb      	ldrb	r3, [r7, #23]
    187e:	f003 0301 	and.w	r3, r3, #1
    1882:	b2db      	uxtb	r3, r3
    1884:	2b00      	cmp	r3, #0
    1886:	d003      	beq.n	1890 <MSS_UART_get_rx+0xcc>
    1888:	693a      	ldr	r2, [r7, #16]
    188a:	687b      	ldr	r3, [r7, #4]
    188c:	429a      	cmp	r2, r3
    188e:	d3dd      	bcc.n	184c <MSS_UART_get_rx+0x88>
            ++rx_size;
            status = this_uart->hw_reg->LSR;
            this_uart->status |= status;
        }
    }
    return rx_size;
    1890:	693b      	ldr	r3, [r7, #16]
}
    1892:	4618      	mov	r0, r3
    1894:	f107 071c 	add.w	r7, r7, #28
    1898:	46bd      	mov	sp, r7
    189a:	bc80      	pop	{r7}
    189c:	4770      	bx	lr
    189e:	bf00      	nop

000018a0 <MSS_UART_enable_irq>:
MSS_UART_enable_irq
(
    mss_uart_instance_t * this_uart,
    mss_uart_irq_t irq_mask
)
{
    18a0:	b580      	push	{r7, lr}
    18a2:	b082      	sub	sp, #8
    18a4:	af00      	add	r7, sp, #0
    18a6:	6078      	str	r0, [r7, #4]
    18a8:	460b      	mov	r3, r1
    18aa:	807b      	strh	r3, [r7, #2]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    18ac:	687a      	ldr	r2, [r7, #4]
    18ae:	f240 13f8 	movw	r3, #504	; 0x1f8
    18b2:	f2c2 0300 	movt	r3, #8192	; 0x2000
    18b6:	429a      	cmp	r2, r3
    18b8:	d007      	beq.n	18ca <MSS_UART_enable_irq+0x2a>
    18ba:	687a      	ldr	r2, [r7, #4]
    18bc:	f240 13b8 	movw	r3, #440	; 0x1b8
    18c0:	f2c2 0300 	movt	r3, #8192	; 0x2000
    18c4:	429a      	cmp	r2, r3
    18c6:	d000      	beq.n	18ca <MSS_UART_enable_irq+0x2a>
    18c8:	be00      	bkpt	0x0000
    ASSERT(MSS_UART_INVALID_IRQ > irq_mask);
    18ca:	887a      	ldrh	r2, [r7, #2]
    18cc:	f64f 73ff 	movw	r3, #65535	; 0xffff
    18d0:	429a      	cmp	r2, r3
    18d2:	d100      	bne.n	18d6 <MSS_UART_enable_irq+0x36>
    18d4:	be00      	bkpt	0x0000

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && 
    18d6:	687a      	ldr	r2, [r7, #4]
    18d8:	f240 13f8 	movw	r3, #504	; 0x1f8
    18dc:	f2c2 0300 	movt	r3, #8192	; 0x2000
    18e0:	429a      	cmp	r2, r3
    18e2:	d006      	beq.n	18f2 <MSS_UART_enable_irq+0x52>
    18e4:	687a      	ldr	r2, [r7, #4]
    18e6:	f240 13b8 	movw	r3, #440	; 0x1b8
    18ea:	f2c2 0300 	movt	r3, #8192	; 0x2000
    18ee:	429a      	cmp	r2, r3
    18f0:	d130      	bne.n	1954 <MSS_UART_enable_irq+0xb4>
    18f2:	887a      	ldrh	r2, [r7, #2]
    18f4:	f64f 73ff 	movw	r3, #65535	; 0xffff
    18f8:	429a      	cmp	r2, r3
    18fa:	d02b      	beq.n	1954 <MSS_UART_enable_irq+0xb4>
       (MSS_UART_INVALID_IRQ > irq_mask))
    {
        /* Clear any previously pended interrupts */
        NVIC_ClearPendingIRQ(this_uart->irqn);
    18fc:	687b      	ldr	r3, [r7, #4]
    18fe:	791b      	ldrb	r3, [r3, #4]
    1900:	b25b      	sxtb	r3, r3
    1902:	4618      	mov	r0, r3
    1904:	f7ff fc20 	bl	1148 <NVIC_ClearPendingIRQ>
         * bit 0 - Receive Data Available Interrupt
         * bit 1 - Transmitter Holding  Register Empty Interrupt
         * bit 2 - Receiver Line Status Interrupt
         * bit 3 - Modem Status Interrupt
         */
        this_uart->hw_reg->IER |= (uint8_t)irq_mask & IIRF_MASK;
    1908:	687b      	ldr	r3, [r7, #4]
    190a:	681a      	ldr	r2, [r3, #0]
    190c:	687b      	ldr	r3, [r7, #4]
    190e:	681b      	ldr	r3, [r3, #0]
    1910:	791b      	ldrb	r3, [r3, #4]
    1912:	b2d9      	uxtb	r1, r3
    1914:	887b      	ldrh	r3, [r7, #2]
    1916:	b2db      	uxtb	r3, r3
    1918:	f003 030f 	and.w	r3, r3, #15
    191c:	ea41 0303 	orr.w	r3, r1, r3
    1920:	b2db      	uxtb	r3, r3
    1922:	7113      	strb	r3, [r2, #4]
         * bit 5 - NACK / ERR signal interrupt
         * bit 6 - PID parity error interrupt 
         * bit 7 - LIN break detection interrupt
         * bit 8 - LIN Sync detection interrupt
         */
        this_uart->hw_reg->IEM |= (uint8_t)(((uint32_t)irq_mask & ~((uint32_t)IIRF_MASK)) >> 4u);
    1924:	687b      	ldr	r3, [r7, #4]
    1926:	681b      	ldr	r3, [r3, #0]
    1928:	687a      	ldr	r2, [r7, #4]
    192a:	6812      	ldr	r2, [r2, #0]
    192c:	f892 2024 	ldrb.w	r2, [r2, #36]	; 0x24
    1930:	b2d1      	uxtb	r1, r2
    1932:	887a      	ldrh	r2, [r7, #2]
    1934:	f022 020f 	bic.w	r2, r2, #15
    1938:	ea4f 1212 	mov.w	r2, r2, lsr #4
    193c:	b2d2      	uxtb	r2, r2
    193e:	ea41 0202 	orr.w	r2, r1, r2
    1942:	b2d2      	uxtb	r2, r2
    1944:	f883 2024 	strb.w	r2, [r3, #36]	; 0x24

        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
        NVIC_EnableIRQ(this_uart->irqn);
    1948:	687b      	ldr	r3, [r7, #4]
    194a:	791b      	ldrb	r3, [r3, #4]
    194c:	b25b      	sxtb	r3, r3
    194e:	4618      	mov	r0, r3
    1950:	f7ff fbc0 	bl	10d4 <NVIC_EnableIRQ>
    }
}
    1954:	f107 0708 	add.w	r7, r7, #8
    1958:	46bd      	mov	sp, r7
    195a:	bd80      	pop	{r7, pc}

0000195c <MSS_UART_disable_irq>:
MSS_UART_disable_irq
(
    mss_uart_instance_t * this_uart,
    mss_uart_irq_t irq_mask
)
{
    195c:	b580      	push	{r7, lr}
    195e:	b082      	sub	sp, #8
    1960:	af00      	add	r7, sp, #0
    1962:	6078      	str	r0, [r7, #4]
    1964:	460b      	mov	r3, r1
    1966:	807b      	strh	r3, [r7, #2]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    1968:	687a      	ldr	r2, [r7, #4]
    196a:	f240 13f8 	movw	r3, #504	; 0x1f8
    196e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1972:	429a      	cmp	r2, r3
    1974:	d007      	beq.n	1986 <MSS_UART_disable_irq+0x2a>
    1976:	687a      	ldr	r2, [r7, #4]
    1978:	f240 13b8 	movw	r3, #440	; 0x1b8
    197c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1980:	429a      	cmp	r2, r3
    1982:	d000      	beq.n	1986 <MSS_UART_disable_irq+0x2a>
    1984:	be00      	bkpt	0x0000

    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
    1986:	687a      	ldr	r2, [r7, #4]
    1988:	f240 13f8 	movw	r3, #504	; 0x1f8
    198c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1990:	429a      	cmp	r2, r3
    1992:	d006      	beq.n	19a2 <MSS_UART_disable_irq+0x46>
    1994:	687a      	ldr	r2, [r7, #4]
    1996:	f240 13b8 	movw	r3, #440	; 0x1b8
    199a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    199e:	429a      	cmp	r2, r3
    19a0:	d134      	bne.n	1a0c <MSS_UART_disable_irq+0xb0>
         * bit 0 - Receive Data Available Interrupt
         * bit 1 - Transmitter Holding  Register Empty Interrupt
         * bit 2 - Receiver Line Status Interrupt
         * bit 3 - Modem Status Interrupt
         */
        this_uart->hw_reg->IER &= ((uint8_t)(~((uint32_t)irq_mask & (uint32_t)IIRF_MASK)));
    19a2:	687b      	ldr	r3, [r7, #4]
    19a4:	681a      	ldr	r2, [r3, #0]
    19a6:	687b      	ldr	r3, [r7, #4]
    19a8:	681b      	ldr	r3, [r3, #0]
    19aa:	791b      	ldrb	r3, [r3, #4]
    19ac:	b2d9      	uxtb	r1, r3
    19ae:	887b      	ldrh	r3, [r7, #2]
    19b0:	b2db      	uxtb	r3, r3
    19b2:	f003 030f 	and.w	r3, r3, #15
    19b6:	ea6f 0303 	mvn.w	r3, r3
    19ba:	b2db      	uxtb	r3, r3
    19bc:	ea01 0303 	and.w	r3, r1, r3
    19c0:	b2db      	uxtb	r3, r3
    19c2:	7113      	strb	r3, [r2, #4]
         * bit 5 - NACK / ERR signal interrupt
         * bit 6 - PID parity error interrupt 
         * bit 7 - LIN break detection interrupt
         * bit 8 - LIN Sync detection interrupt
         */
        this_uart->hw_reg->IEM |= (uint8_t)(~(((uint32_t)irq_mask & ~((uint32_t)IIRF_MASK)) >> 8u));
    19c4:	687b      	ldr	r3, [r7, #4]
    19c6:	681b      	ldr	r3, [r3, #0]
    19c8:	687a      	ldr	r2, [r7, #4]
    19ca:	6812      	ldr	r2, [r2, #0]
    19cc:	f892 2024 	ldrb.w	r2, [r2, #36]	; 0x24
    19d0:	b2d1      	uxtb	r1, r2
    19d2:	887a      	ldrh	r2, [r7, #2]
    19d4:	f022 020f 	bic.w	r2, r2, #15
    19d8:	ea4f 2212 	mov.w	r2, r2, lsr #8
    19dc:	b2d2      	uxtb	r2, r2
    19de:	ea6f 0202 	mvn.w	r2, r2
    19e2:	b2d2      	uxtb	r2, r2
    19e4:	ea41 0202 	orr.w	r2, r1, r2
    19e8:	b2d2      	uxtb	r2, r2
    19ea:	f883 2024 	strb.w	r2, [r3, #36]	; 0x24

        /* Clear any previously pended interrupts */
        NVIC_ClearPendingIRQ(this_uart->irqn);
    19ee:	687b      	ldr	r3, [r7, #4]
    19f0:	791b      	ldrb	r3, [r3, #4]
    19f2:	b25b      	sxtb	r3, r3
    19f4:	4618      	mov	r0, r3
    19f6:	f7ff fba7 	bl	1148 <NVIC_ClearPendingIRQ>

        if(irq_mask == IIRF_MASK)
    19fa:	887b      	ldrh	r3, [r7, #2]
    19fc:	2b0f      	cmp	r3, #15
    19fe:	d105      	bne.n	1a0c <MSS_UART_disable_irq+0xb0>
        {
            /* Disable UART instance interrupt in Cortex-M3 NVIC. */
            NVIC_DisableIRQ(this_uart->irqn);
    1a00:	687b      	ldr	r3, [r7, #4]
    1a02:	791b      	ldrb	r3, [r3, #4]
    1a04:	b25b      	sxtb	r3, r3
    1a06:	4618      	mov	r0, r3
    1a08:	f7ff fb80 	bl	110c <NVIC_DisableIRQ>

        }
    }
}
    1a0c:	f107 0708 	add.w	r7, r7, #8
    1a10:	46bd      	mov	sp, r7
    1a12:	bd80      	pop	{r7, pc}

00001a14 <MSS_UART_set_rx_handler>:
(
    mss_uart_instance_t *       this_uart,
    mss_uart_irq_handler_t      handler,
    mss_uart_rx_trig_level_t    trigger_level
)
{
    1a14:	b580      	push	{r7, lr}
    1a16:	b084      	sub	sp, #16
    1a18:	af00      	add	r7, sp, #0
    1a1a:	60f8      	str	r0, [r7, #12]
    1a1c:	60b9      	str	r1, [r7, #8]
    1a1e:	4613      	mov	r3, r2
    1a20:	71fb      	strb	r3, [r7, #7]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    1a22:	68fa      	ldr	r2, [r7, #12]
    1a24:	f240 13f8 	movw	r3, #504	; 0x1f8
    1a28:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1a2c:	429a      	cmp	r2, r3
    1a2e:	d007      	beq.n	1a40 <MSS_UART_set_rx_handler+0x2c>
    1a30:	68fa      	ldr	r2, [r7, #12]
    1a32:	f240 13b8 	movw	r3, #440	; 0x1b8
    1a36:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1a3a:	429a      	cmp	r2, r3
    1a3c:	d000      	beq.n	1a40 <MSS_UART_set_rx_handler+0x2c>
    1a3e:	be00      	bkpt	0x0000
    ASSERT(handler != INVALID_IRQ_HANDLER );
    1a40:	68bb      	ldr	r3, [r7, #8]
    1a42:	2b00      	cmp	r3, #0
    1a44:	d100      	bne.n	1a48 <MSS_UART_set_rx_handler+0x34>
    1a46:	be00      	bkpt	0x0000
    ASSERT(trigger_level < MSS_UART_FIFO_INVALID_TRIG_LEVEL);
    1a48:	79fb      	ldrb	r3, [r7, #7]
    1a4a:	2bc0      	cmp	r3, #192	; 0xc0
    1a4c:	d900      	bls.n	1a50 <MSS_UART_set_rx_handler+0x3c>
    1a4e:	be00      	bkpt	0x0000

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
    1a50:	68fa      	ldr	r2, [r7, #12]
    1a52:	f240 13f8 	movw	r3, #504	; 0x1f8
    1a56:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1a5a:	429a      	cmp	r2, r3
    1a5c:	d006      	beq.n	1a6c <MSS_UART_set_rx_handler+0x58>
    1a5e:	68fa      	ldr	r2, [r7, #12]
    1a60:	f240 13b8 	movw	r3, #440	; 0x1b8
    1a64:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1a68:	429a      	cmp	r2, r3
    1a6a:	d12e      	bne.n	1aca <MSS_UART_set_rx_handler+0xb6>
    1a6c:	68bb      	ldr	r3, [r7, #8]
    1a6e:	2b00      	cmp	r3, #0
    1a70:	d02b      	beq.n	1aca <MSS_UART_set_rx_handler+0xb6>
    1a72:	79fb      	ldrb	r3, [r7, #7]
    1a74:	2bc0      	cmp	r3, #192	; 0xc0
    1a76:	d828      	bhi.n	1aca <MSS_UART_set_rx_handler+0xb6>
       (handler != INVALID_IRQ_HANDLER) &&
       (trigger_level < MSS_UART_FIFO_INVALID_TRIG_LEVEL))
    {
        this_uart->rx_handler = handler;
    1a78:	68fb      	ldr	r3, [r7, #12]
    1a7a:	68ba      	ldr	r2, [r7, #8]
    1a7c:	621a      	str	r2, [r3, #32]

        /* Set the receive interrupt trigger level. */
        this_uart->hw_reg->FCR = (this_uart->hw_reg->FCR &
    1a7e:	68fb      	ldr	r3, [r7, #12]
    1a80:	681a      	ldr	r2, [r3, #0]
    1a82:	68fb      	ldr	r3, [r7, #12]
    1a84:	681b      	ldr	r3, [r3, #0]
    1a86:	7a1b      	ldrb	r3, [r3, #8]
    1a88:	b2db      	uxtb	r3, r3
    1a8a:	b2db      	uxtb	r3, r3
    1a8c:	f003 033f 	and.w	r3, r3, #63	; 0x3f
    1a90:	79f8      	ldrb	r0, [r7, #7]
    1a92:	4619      	mov	r1, r3
    1a94:	4603      	mov	r3, r0
    1a96:	ea41 0303 	orr.w	r3, r1, r3
    1a9a:	b2db      	uxtb	r3, r3
    1a9c:	b2db      	uxtb	r3, r3
    1a9e:	7213      	strb	r3, [r2, #8]
                                 (uint8_t)(~((uint8_t)FCR_TRIG_LEVEL_MASK))) |
                                 (uint8_t)trigger_level;
        /* Clear any previously pended interrupts */
        NVIC_ClearPendingIRQ(this_uart->irqn);
    1aa0:	68fb      	ldr	r3, [r7, #12]
    1aa2:	791b      	ldrb	r3, [r3, #4]
    1aa4:	b25b      	sxtb	r3, r3
    1aa6:	4618      	mov	r0, r3
    1aa8:	f7ff fb4e 	bl	1148 <NVIC_ClearPendingIRQ>

        /* Enable receive interrupt. */
        set_bit_reg8(&this_uart->hw_reg->IER,ERBFI);
    1aac:	68fb      	ldr	r3, [r7, #12]
    1aae:	681b      	ldr	r3, [r3, #0]
    1ab0:	f103 0304 	add.w	r3, r3, #4
    1ab4:	4618      	mov	r0, r3
    1ab6:	f04f 0100 	mov.w	r1, #0
    1aba:	f7ff fb63 	bl	1184 <set_bit_reg8>

        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
        NVIC_EnableIRQ(this_uart->irqn);
    1abe:	68fb      	ldr	r3, [r7, #12]
    1ac0:	791b      	ldrb	r3, [r3, #4]
    1ac2:	b25b      	sxtb	r3, r3
    1ac4:	4618      	mov	r0, r3
    1ac6:	f7ff fb05 	bl	10d4 <NVIC_EnableIRQ>
    }
}
    1aca:	f107 0710 	add.w	r7, r7, #16
    1ace:	46bd      	mov	sp, r7
    1ad0:	bd80      	pop	{r7, pc}
    1ad2:	bf00      	nop

00001ad4 <MSS_UART_set_loopback>:
MSS_UART_set_loopback
(
    mss_uart_instance_t *   this_uart,
    mss_uart_loopback_t     loopback
)
{
    1ad4:	b580      	push	{r7, lr}
    1ad6:	b082      	sub	sp, #8
    1ad8:	af00      	add	r7, sp, #0
    1ada:	6078      	str	r0, [r7, #4]
    1adc:	460b      	mov	r3, r1
    1ade:	70fb      	strb	r3, [r7, #3]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    1ae0:	687a      	ldr	r2, [r7, #4]
    1ae2:	f240 13f8 	movw	r3, #504	; 0x1f8
    1ae6:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1aea:	429a      	cmp	r2, r3
    1aec:	d007      	beq.n	1afe <MSS_UART_set_loopback+0x2a>
    1aee:	687a      	ldr	r2, [r7, #4]
    1af0:	f240 13b8 	movw	r3, #440	; 0x1b8
    1af4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1af8:	429a      	cmp	r2, r3
    1afa:	d000      	beq.n	1afe <MSS_UART_set_loopback+0x2a>
    1afc:	be00      	bkpt	0x0000
    ASSERT(MSS_UART_INVALID_LOOPBACK > loopback);
    1afe:	78fb      	ldrb	r3, [r7, #3]
    1b00:	2b05      	cmp	r3, #5
    1b02:	d900      	bls.n	1b06 <MSS_UART_set_loopback+0x32>
    1b04:	be00      	bkpt	0x0000

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) ||
    1b06:	687a      	ldr	r2, [r7, #4]
    1b08:	f240 13f8 	movw	r3, #504	; 0x1f8
    1b0c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1b10:	429a      	cmp	r2, r3
    1b12:	d009      	beq.n	1b28 <MSS_UART_set_loopback+0x54>
    1b14:	687a      	ldr	r2, [r7, #4]
    1b16:	f240 13b8 	movw	r3, #440	; 0x1b8
    1b1a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1b1e:	429a      	cmp	r2, r3
    1b20:	d002      	beq.n	1b28 <MSS_UART_set_loopback+0x54>
    1b22:	78fb      	ldrb	r3, [r7, #3]
    1b24:	2b05      	cmp	r3, #5
    1b26:	d846      	bhi.n	1bb6 <MSS_UART_set_loopback+0xe2>
       (MSS_UART_INVALID_LOOPBACK > loopback))
    {
        switch(loopback)
    1b28:	78fb      	ldrb	r3, [r7, #3]
    1b2a:	2b05      	cmp	r3, #5
    1b2c:	d842      	bhi.n	1bb4 <MSS_UART_set_loopback+0xe0>
    1b2e:	a201      	add	r2, pc, #4	; (adr r2, 1b34 <MSS_UART_set_loopback+0x60>)
    1b30:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
    1b34:	00001b4d 	.word	0x00001b4d
    1b38:	00001b61 	.word	0x00001b61
    1b3c:	00001b75 	.word	0x00001b75
    1b40:	00001b89 	.word	0x00001b89
    1b44:	00001b75 	.word	0x00001b75
    1b48:	00001b9f 	.word	0x00001b9f
        {
            case MSS_UART_LOCAL_LOOPBACK_OFF:
                /* Disable local loopback */
                clear_bit_reg8(&this_uart->hw_reg->MCR,LOOP);
    1b4c:	687b      	ldr	r3, [r7, #4]
    1b4e:	681b      	ldr	r3, [r3, #0]
    1b50:	f103 0310 	add.w	r3, r3, #16
    1b54:	4618      	mov	r0, r3
    1b56:	f04f 0104 	mov.w	r1, #4
    1b5a:	f7ff fb33 	bl	11c4 <clear_bit_reg8>
                break;
    1b5e:	e02a      	b.n	1bb6 <MSS_UART_set_loopback+0xe2>
                
            case MSS_UART_LOCAL_LOOPBACK_ON:
                /* Enable local loopback */
                set_bit_reg8(&this_uart->hw_reg->MCR,LOOP);
    1b60:	687b      	ldr	r3, [r7, #4]
    1b62:	681b      	ldr	r3, [r3, #0]
    1b64:	f103 0310 	add.w	r3, r3, #16
    1b68:	4618      	mov	r0, r3
    1b6a:	f04f 0104 	mov.w	r1, #4
    1b6e:	f7ff fb09 	bl	1184 <set_bit_reg8>
                break;
    1b72:	e020      	b.n	1bb6 <MSS_UART_set_loopback+0xe2>
            
            case MSS_UART_REMOTE_LOOPBACK_OFF:
            case MSS_UART_AUTO_ECHO_OFF:
                /* Disable remote loopback & automatic echo*/
                this_uart->hw_reg->MCR &= ~RLOOP_MASK;
    1b74:	687b      	ldr	r3, [r7, #4]
    1b76:	681a      	ldr	r2, [r3, #0]
    1b78:	687b      	ldr	r3, [r7, #4]
    1b7a:	681b      	ldr	r3, [r3, #0]
    1b7c:	7c1b      	ldrb	r3, [r3, #16]
    1b7e:	b2db      	uxtb	r3, r3
    1b80:	f003 03f9 	and.w	r3, r3, #249	; 0xf9
    1b84:	7413      	strb	r3, [r2, #16]
                break;
    1b86:	e016      	b.n	1bb6 <MSS_UART_set_loopback+0xe2>
            
            case MSS_UART_REMOTE_LOOPBACK_ON:
                /* Enable remote loopback */
                this_uart->hw_reg->MCR |= (1u << RLOOP);
    1b88:	687b      	ldr	r3, [r7, #4]
    1b8a:	681b      	ldr	r3, [r3, #0]
    1b8c:	687a      	ldr	r2, [r7, #4]
    1b8e:	6812      	ldr	r2, [r2, #0]
    1b90:	7c12      	ldrb	r2, [r2, #16]
    1b92:	b2d2      	uxtb	r2, r2
    1b94:	f042 0220 	orr.w	r2, r2, #32
    1b98:	b2d2      	uxtb	r2, r2
    1b9a:	741a      	strb	r2, [r3, #16]
                break;
    1b9c:	e00b      	b.n	1bb6 <MSS_UART_set_loopback+0xe2>
                
            case MSS_UART_AUTO_ECHO_ON:
                /* Enable automatic echo */
                this_uart->hw_reg->MCR |= (1u << ECHO);
    1b9e:	687b      	ldr	r3, [r7, #4]
    1ba0:	681b      	ldr	r3, [r3, #0]
    1ba2:	687a      	ldr	r2, [r7, #4]
    1ba4:	6812      	ldr	r2, [r2, #0]
    1ba6:	7c12      	ldrb	r2, [r2, #16]
    1ba8:	b2d2      	uxtb	r2, r2
    1baa:	f042 0240 	orr.w	r2, r2, #64	; 0x40
    1bae:	b2d2      	uxtb	r2, r2
    1bb0:	741a      	strb	r2, [r3, #16]
                break;
    1bb2:	e000      	b.n	1bb6 <MSS_UART_set_loopback+0xe2>
                
            case MSS_UART_INVALID_LOOPBACK:
                /* Fall through to default. */
            default:
                ASSERT(0);
    1bb4:	be00      	bkpt	0x0000
                break;
        }
    }
}
    1bb6:	f107 0708 	add.w	r7, r7, #8
    1bba:	46bd      	mov	sp, r7
    1bbc:	bd80      	pop	{r7, pc}
    1bbe:	bf00      	nop

00001bc0 <UART0_IRQHandler>:
#if defined(__GNUC__)
__attribute__((__interrupt__)) void UART0_IRQHandler(void)
#else
void UART0_IRQHandler(void)
#endif
{
    1bc0:	4668      	mov	r0, sp
    1bc2:	f020 0107 	bic.w	r1, r0, #7
    1bc6:	468d      	mov	sp, r1
    1bc8:	b589      	push	{r0, r3, r7, lr}
    1bca:	af00      	add	r7, sp, #0
    MSS_UART_isr(&g_mss_uart0);
    1bcc:	f240 10f8 	movw	r0, #504	; 0x1f8
    1bd0:	f2c2 0000 	movt	r0, #8192	; 0x2000
    1bd4:	f001 f916 	bl	2e04 <MSS_UART_isr>
}
    1bd8:	46bd      	mov	sp, r7
    1bda:	e8bd 4089 	ldmia.w	sp!, {r0, r3, r7, lr}
    1bde:	4685      	mov	sp, r0
    1be0:	4770      	bx	lr
    1be2:	bf00      	nop

00001be4 <UART1_IRQHandler>:
#if defined(__GNUC__)
__attribute__((__interrupt__)) void UART1_IRQHandler(void)
#else
void UART1_IRQHandler(void)
#endif
{
    1be4:	4668      	mov	r0, sp
    1be6:	f020 0107 	bic.w	r1, r0, #7
    1bea:	468d      	mov	sp, r1
    1bec:	b589      	push	{r0, r3, r7, lr}
    1bee:	af00      	add	r7, sp, #0
    MSS_UART_isr(&g_mss_uart1);
    1bf0:	f240 10b8 	movw	r0, #440	; 0x1b8
    1bf4:	f2c2 0000 	movt	r0, #8192	; 0x2000
    1bf8:	f001 f904 	bl	2e04 <MSS_UART_isr>
}
    1bfc:	46bd      	mov	sp, r7
    1bfe:	e8bd 4089 	ldmia.w	sp!, {r0, r3, r7, lr}
    1c02:	4685      	mov	sp, r0
    1c04:	4770      	bx	lr
    1c06:	bf00      	nop

00001c08 <MSS_UART_set_rxstatus_handler>:
MSS_UART_set_rxstatus_handler
(
    mss_uart_instance_t * this_uart,
    mss_uart_irq_handler_t handler
)
{
    1c08:	b580      	push	{r7, lr}
    1c0a:	b082      	sub	sp, #8
    1c0c:	af00      	add	r7, sp, #0
    1c0e:	6078      	str	r0, [r7, #4]
    1c10:	6039      	str	r1, [r7, #0]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    1c12:	687a      	ldr	r2, [r7, #4]
    1c14:	f240 13f8 	movw	r3, #504	; 0x1f8
    1c18:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1c1c:	429a      	cmp	r2, r3
    1c1e:	d007      	beq.n	1c30 <MSS_UART_set_rxstatus_handler+0x28>
    1c20:	687a      	ldr	r2, [r7, #4]
    1c22:	f240 13b8 	movw	r3, #440	; 0x1b8
    1c26:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1c2a:	429a      	cmp	r2, r3
    1c2c:	d000      	beq.n	1c30 <MSS_UART_set_rxstatus_handler+0x28>
    1c2e:	be00      	bkpt	0x0000
    ASSERT(handler != INVALID_IRQ_HANDLER);
    1c30:	683b      	ldr	r3, [r7, #0]
    1c32:	2b00      	cmp	r3, #0
    1c34:	d100      	bne.n	1c38 <MSS_UART_set_rxstatus_handler+0x30>
    1c36:	be00      	bkpt	0x0000

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
    1c38:	687a      	ldr	r2, [r7, #4]
    1c3a:	f240 13f8 	movw	r3, #504	; 0x1f8
    1c3e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1c42:	429a      	cmp	r2, r3
    1c44:	d006      	beq.n	1c54 <MSS_UART_set_rxstatus_handler+0x4c>
    1c46:	687a      	ldr	r2, [r7, #4]
    1c48:	f240 13b8 	movw	r3, #440	; 0x1b8
    1c4c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1c50:	429a      	cmp	r2, r3
    1c52:	d11a      	bne.n	1c8a <MSS_UART_set_rxstatus_handler+0x82>
    1c54:	683b      	ldr	r3, [r7, #0]
    1c56:	2b00      	cmp	r3, #0
    1c58:	d017      	beq.n	1c8a <MSS_UART_set_rxstatus_handler+0x82>
       (handler != INVALID_IRQ_HANDLER))
    {
        this_uart->linests_handler = handler;
    1c5a:	687b      	ldr	r3, [r7, #4]
    1c5c:	683a      	ldr	r2, [r7, #0]
    1c5e:	61da      	str	r2, [r3, #28]

        /* Clear any previously pended interrupts */
        NVIC_ClearPendingIRQ(this_uart->irqn);
    1c60:	687b      	ldr	r3, [r7, #4]
    1c62:	791b      	ldrb	r3, [r3, #4]
    1c64:	b25b      	sxtb	r3, r3
    1c66:	4618      	mov	r0, r3
    1c68:	f7ff fa6e 	bl	1148 <NVIC_ClearPendingIRQ>

        /* Enable receiver line status interrupt. */
        set_bit_reg8(&this_uart->hw_reg->IER,ELSI);
    1c6c:	687b      	ldr	r3, [r7, #4]
    1c6e:	681b      	ldr	r3, [r3, #0]
    1c70:	f103 0304 	add.w	r3, r3, #4
    1c74:	4618      	mov	r0, r3
    1c76:	f04f 0102 	mov.w	r1, #2
    1c7a:	f7ff fa83 	bl	1184 <set_bit_reg8>

        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
        NVIC_EnableIRQ(this_uart->irqn);
    1c7e:	687b      	ldr	r3, [r7, #4]
    1c80:	791b      	ldrb	r3, [r3, #4]
    1c82:	b25b      	sxtb	r3, r3
    1c84:	4618      	mov	r0, r3
    1c86:	f7ff fa25 	bl	10d4 <NVIC_EnableIRQ>
    }
}
    1c8a:	f107 0708 	add.w	r7, r7, #8
    1c8e:	46bd      	mov	sp, r7
    1c90:	bd80      	pop	{r7, pc}
    1c92:	bf00      	nop

00001c94 <MSS_UART_set_tx_handler>:
MSS_UART_set_tx_handler
(
    mss_uart_instance_t * this_uart,
    mss_uart_irq_handler_t handler
)
{
    1c94:	b580      	push	{r7, lr}
    1c96:	b082      	sub	sp, #8
    1c98:	af00      	add	r7, sp, #0
    1c9a:	6078      	str	r0, [r7, #4]
    1c9c:	6039      	str	r1, [r7, #0]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    1c9e:	687a      	ldr	r2, [r7, #4]
    1ca0:	f240 13f8 	movw	r3, #504	; 0x1f8
    1ca4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1ca8:	429a      	cmp	r2, r3
    1caa:	d007      	beq.n	1cbc <MSS_UART_set_tx_handler+0x28>
    1cac:	687a      	ldr	r2, [r7, #4]
    1cae:	f240 13b8 	movw	r3, #440	; 0x1b8
    1cb2:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1cb6:	429a      	cmp	r2, r3
    1cb8:	d000      	beq.n	1cbc <MSS_UART_set_tx_handler+0x28>
    1cba:	be00      	bkpt	0x0000
    ASSERT(handler != INVALID_IRQ_HANDLER);
    1cbc:	683b      	ldr	r3, [r7, #0]
    1cbe:	2b00      	cmp	r3, #0
    1cc0:	d100      	bne.n	1cc4 <MSS_UART_set_tx_handler+0x30>
    1cc2:	be00      	bkpt	0x0000

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
    1cc4:	687a      	ldr	r2, [r7, #4]
    1cc6:	f240 13f8 	movw	r3, #504	; 0x1f8
    1cca:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1cce:	429a      	cmp	r2, r3
    1cd0:	d006      	beq.n	1ce0 <MSS_UART_set_tx_handler+0x4c>
    1cd2:	687a      	ldr	r2, [r7, #4]
    1cd4:	f240 13b8 	movw	r3, #440	; 0x1b8
    1cd8:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1cdc:	429a      	cmp	r2, r3
    1cde:	d122      	bne.n	1d26 <MSS_UART_set_tx_handler+0x92>
    1ce0:	683b      	ldr	r3, [r7, #0]
    1ce2:	2b00      	cmp	r3, #0
    1ce4:	d01f      	beq.n	1d26 <MSS_UART_set_tx_handler+0x92>
       (handler != INVALID_IRQ_HANDLER))
    {
        this_uart->tx_handler = handler;
    1ce6:	687b      	ldr	r3, [r7, #4]
    1ce8:	683a      	ldr	r2, [r7, #0]
    1cea:	625a      	str	r2, [r3, #36]	; 0x24

        /* Make TX buffer info invalid */
        this_uart->tx_buffer = (const uint8_t *)0;
    1cec:	687b      	ldr	r3, [r7, #4]
    1cee:	f04f 0200 	mov.w	r2, #0
    1cf2:	611a      	str	r2, [r3, #16]
        this_uart->tx_buff_size = 0u;
    1cf4:	687b      	ldr	r3, [r7, #4]
    1cf6:	f04f 0200 	mov.w	r2, #0
    1cfa:	615a      	str	r2, [r3, #20]

        /* Clear any previously pended interrupts */
        NVIC_ClearPendingIRQ(this_uart->irqn);
    1cfc:	687b      	ldr	r3, [r7, #4]
    1cfe:	791b      	ldrb	r3, [r3, #4]
    1d00:	b25b      	sxtb	r3, r3
    1d02:	4618      	mov	r0, r3
    1d04:	f7ff fa20 	bl	1148 <NVIC_ClearPendingIRQ>

        /* Enable transmitter holding register Empty interrupt. */
        set_bit_reg8(&this_uart->hw_reg->IER,ETBEI);
    1d08:	687b      	ldr	r3, [r7, #4]
    1d0a:	681b      	ldr	r3, [r3, #0]
    1d0c:	f103 0304 	add.w	r3, r3, #4
    1d10:	4618      	mov	r0, r3
    1d12:	f04f 0101 	mov.w	r1, #1
    1d16:	f7ff fa35 	bl	1184 <set_bit_reg8>

        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
        NVIC_EnableIRQ(this_uart->irqn);
    1d1a:	687b      	ldr	r3, [r7, #4]
    1d1c:	791b      	ldrb	r3, [r3, #4]
    1d1e:	b25b      	sxtb	r3, r3
    1d20:	4618      	mov	r0, r3
    1d22:	f7ff f9d7 	bl	10d4 <NVIC_EnableIRQ>
    }
}
    1d26:	f107 0708 	add.w	r7, r7, #8
    1d2a:	46bd      	mov	sp, r7
    1d2c:	bd80      	pop	{r7, pc}
    1d2e:	bf00      	nop

00001d30 <MSS_UART_set_modemstatus_handler>:
MSS_UART_set_modemstatus_handler
(
    mss_uart_instance_t * this_uart,
    mss_uart_irq_handler_t handler
)
{
    1d30:	b580      	push	{r7, lr}
    1d32:	b082      	sub	sp, #8
    1d34:	af00      	add	r7, sp, #0
    1d36:	6078      	str	r0, [r7, #4]
    1d38:	6039      	str	r1, [r7, #0]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    1d3a:	687a      	ldr	r2, [r7, #4]
    1d3c:	f240 13f8 	movw	r3, #504	; 0x1f8
    1d40:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1d44:	429a      	cmp	r2, r3
    1d46:	d007      	beq.n	1d58 <MSS_UART_set_modemstatus_handler+0x28>
    1d48:	687a      	ldr	r2, [r7, #4]
    1d4a:	f240 13b8 	movw	r3, #440	; 0x1b8
    1d4e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1d52:	429a      	cmp	r2, r3
    1d54:	d000      	beq.n	1d58 <MSS_UART_set_modemstatus_handler+0x28>
    1d56:	be00      	bkpt	0x0000
    ASSERT(handler != INVALID_IRQ_HANDLER);
    1d58:	683b      	ldr	r3, [r7, #0]
    1d5a:	2b00      	cmp	r3, #0
    1d5c:	d100      	bne.n	1d60 <MSS_UART_set_modemstatus_handler+0x30>
    1d5e:	be00      	bkpt	0x0000

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
    1d60:	687a      	ldr	r2, [r7, #4]
    1d62:	f240 13f8 	movw	r3, #504	; 0x1f8
    1d66:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1d6a:	429a      	cmp	r2, r3
    1d6c:	d006      	beq.n	1d7c <MSS_UART_set_modemstatus_handler+0x4c>
    1d6e:	687a      	ldr	r2, [r7, #4]
    1d70:	f240 13b8 	movw	r3, #440	; 0x1b8
    1d74:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1d78:	429a      	cmp	r2, r3
    1d7a:	d11a      	bne.n	1db2 <MSS_UART_set_modemstatus_handler+0x82>
    1d7c:	683b      	ldr	r3, [r7, #0]
    1d7e:	2b00      	cmp	r3, #0
    1d80:	d017      	beq.n	1db2 <MSS_UART_set_modemstatus_handler+0x82>
       (handler != INVALID_IRQ_HANDLER))
    {
        this_uart->modemsts_handler = handler;
    1d82:	687b      	ldr	r3, [r7, #4]
    1d84:	683a      	ldr	r2, [r7, #0]
    1d86:	629a      	str	r2, [r3, #40]	; 0x28

        /* Clear any previously pended interrupts */
        NVIC_ClearPendingIRQ(this_uart->irqn);
    1d88:	687b      	ldr	r3, [r7, #4]
    1d8a:	791b      	ldrb	r3, [r3, #4]
    1d8c:	b25b      	sxtb	r3, r3
    1d8e:	4618      	mov	r0, r3
    1d90:	f7ff f9da 	bl	1148 <NVIC_ClearPendingIRQ>

        /* Enable modem status interrupt. */
        set_bit_reg8(&this_uart->hw_reg->IER,EDSSI);
    1d94:	687b      	ldr	r3, [r7, #4]
    1d96:	681b      	ldr	r3, [r3, #0]
    1d98:	f103 0304 	add.w	r3, r3, #4
    1d9c:	4618      	mov	r0, r3
    1d9e:	f04f 0103 	mov.w	r1, #3
    1da2:	f7ff f9ef 	bl	1184 <set_bit_reg8>

        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
        NVIC_EnableIRQ(this_uart->irqn);
    1da6:	687b      	ldr	r3, [r7, #4]
    1da8:	791b      	ldrb	r3, [r3, #4]
    1daa:	b25b      	sxtb	r3, r3
    1dac:	4618      	mov	r0, r3
    1dae:	f7ff f991 	bl	10d4 <NVIC_EnableIRQ>
    }
}
    1db2:	f107 0708 	add.w	r7, r7, #8
    1db6:	46bd      	mov	sp, r7
    1db8:	bd80      	pop	{r7, pc}
    1dba:	bf00      	nop

00001dbc <MSS_UART_fill_tx_fifo>:
(
    mss_uart_instance_t * this_uart,
    const uint8_t * tx_buffer,
    size_t tx_size
)
{
    1dbc:	b480      	push	{r7}
    1dbe:	b089      	sub	sp, #36	; 0x24
    1dc0:	af00      	add	r7, sp, #0
    1dc2:	60f8      	str	r0, [r7, #12]
    1dc4:	60b9      	str	r1, [r7, #8]
    1dc6:	607a      	str	r2, [r7, #4]
    uint8_t status = 0u;
    1dc8:	f04f 0300 	mov.w	r3, #0
    1dcc:	75fb      	strb	r3, [r7, #23]
    size_t size_sent = 0u;
    1dce:	f04f 0300 	mov.w	r3, #0
    1dd2:	61bb      	str	r3, [r7, #24]

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    1dd4:	68fa      	ldr	r2, [r7, #12]
    1dd6:	f240 13f8 	movw	r3, #504	; 0x1f8
    1dda:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1dde:	429a      	cmp	r2, r3
    1de0:	d007      	beq.n	1df2 <MSS_UART_fill_tx_fifo+0x36>
    1de2:	68fa      	ldr	r2, [r7, #12]
    1de4:	f240 13b8 	movw	r3, #440	; 0x1b8
    1de8:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1dec:	429a      	cmp	r2, r3
    1dee:	d000      	beq.n	1df2 <MSS_UART_fill_tx_fifo+0x36>
    1df0:	be00      	bkpt	0x0000
    ASSERT(tx_buffer != ( (uint8_t *)0));
    1df2:	68bb      	ldr	r3, [r7, #8]
    1df4:	2b00      	cmp	r3, #0
    1df6:	d100      	bne.n	1dfa <MSS_UART_fill_tx_fifo+0x3e>
    1df8:	be00      	bkpt	0x0000
    ASSERT(tx_size > 0);
    1dfa:	687b      	ldr	r3, [r7, #4]
    1dfc:	2b00      	cmp	r3, #0
    1dfe:	d100      	bne.n	1e02 <MSS_UART_fill_tx_fifo+0x46>
    1e00:	be00      	bkpt	0x0000

    /* Fill the UART's Tx FIFO until the FIFO is full or the complete input
     * buffer has been written. */
    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
    1e02:	68fa      	ldr	r2, [r7, #12]
    1e04:	f240 13f8 	movw	r3, #504	; 0x1f8
    1e08:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1e0c:	429a      	cmp	r2, r3
    1e0e:	d006      	beq.n	1e1e <MSS_UART_fill_tx_fifo+0x62>
    1e10:	68fa      	ldr	r2, [r7, #12]
    1e12:	f240 13b8 	movw	r3, #440	; 0x1b8
    1e16:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1e1a:	429a      	cmp	r2, r3
    1e1c:	d131      	bne.n	1e82 <MSS_UART_fill_tx_fifo+0xc6>
    1e1e:	68bb      	ldr	r3, [r7, #8]
    1e20:	2b00      	cmp	r3, #0
    1e22:	d02e      	beq.n	1e82 <MSS_UART_fill_tx_fifo+0xc6>
    1e24:	687b      	ldr	r3, [r7, #4]
    1e26:	2b00      	cmp	r3, #0
    1e28:	d02b      	beq.n	1e82 <MSS_UART_fill_tx_fifo+0xc6>
       (tx_buffer != ((uint8_t *)0))   &&
       (tx_size > 0u))
    {
        status = this_uart->hw_reg->LSR;
    1e2a:	68fb      	ldr	r3, [r7, #12]
    1e2c:	681b      	ldr	r3, [r3, #0]
    1e2e:	7d1b      	ldrb	r3, [r3, #20]
    1e30:	75fb      	strb	r3, [r7, #23]
        this_uart->status |= status;
    1e32:	68fb      	ldr	r3, [r7, #12]
    1e34:	7b5a      	ldrb	r2, [r3, #13]
    1e36:	7dfb      	ldrb	r3, [r7, #23]
    1e38:	ea42 0303 	orr.w	r3, r2, r3
    1e3c:	b2da      	uxtb	r2, r3
    1e3e:	68fb      	ldr	r3, [r7, #12]
    1e40:	735a      	strb	r2, [r3, #13]

        if(status & MSS_UART_THRE)
    1e42:	7dfb      	ldrb	r3, [r7, #23]
    1e44:	f003 0320 	and.w	r3, r3, #32
    1e48:	2b00      	cmp	r3, #0
    1e4a:	d01a      	beq.n	1e82 <MSS_UART_fill_tx_fifo+0xc6>
        {
            uint32_t fill_size = TX_FIFO_SIZE;
    1e4c:	f04f 0310 	mov.w	r3, #16
    1e50:	61fb      	str	r3, [r7, #28]

            if(tx_size < TX_FIFO_SIZE)
    1e52:	687b      	ldr	r3, [r7, #4]
    1e54:	2b0f      	cmp	r3, #15
    1e56:	d801      	bhi.n	1e5c <MSS_UART_fill_tx_fifo+0xa0>
            {
                fill_size = tx_size;
    1e58:	687b      	ldr	r3, [r7, #4]
    1e5a:	61fb      	str	r3, [r7, #28]
            }
            /* Fill up FIFO */
            for(size_sent = 0u; size_sent < fill_size; ++size_sent)
    1e5c:	f04f 0300 	mov.w	r3, #0
    1e60:	61bb      	str	r3, [r7, #24]
    1e62:	e00a      	b.n	1e7a <MSS_UART_fill_tx_fifo+0xbe>
            {

                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = tx_buffer[size_sent];
    1e64:	68fb      	ldr	r3, [r7, #12]
    1e66:	681b      	ldr	r3, [r3, #0]
    1e68:	68b9      	ldr	r1, [r7, #8]
    1e6a:	69ba      	ldr	r2, [r7, #24]
    1e6c:	440a      	add	r2, r1
    1e6e:	7812      	ldrb	r2, [r2, #0]
    1e70:	701a      	strb	r2, [r3, #0]
            if(tx_size < TX_FIFO_SIZE)
            {
                fill_size = tx_size;
            }
            /* Fill up FIFO */
            for(size_sent = 0u; size_sent < fill_size; ++size_sent)
    1e72:	69bb      	ldr	r3, [r7, #24]
    1e74:	f103 0301 	add.w	r3, r3, #1
    1e78:	61bb      	str	r3, [r7, #24]
    1e7a:	69ba      	ldr	r2, [r7, #24]
    1e7c:	69fb      	ldr	r3, [r7, #28]
    1e7e:	429a      	cmp	r2, r3
    1e80:	d3f0      	bcc.n	1e64 <MSS_UART_fill_tx_fifo+0xa8>
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = tx_buffer[size_sent];
            }
        }
    }
    return size_sent;
    1e82:	69bb      	ldr	r3, [r7, #24]
}
    1e84:	4618      	mov	r0, r3
    1e86:	f107 0724 	add.w	r7, r7, #36	; 0x24
    1e8a:	46bd      	mov	sp, r7
    1e8c:	bc80      	pop	{r7}
    1e8e:	4770      	bx	lr

00001e90 <MSS_UART_get_rx_status>:
uint8_t
MSS_UART_get_rx_status
(
    mss_uart_instance_t * this_uart
)
{
    1e90:	b480      	push	{r7}
    1e92:	b085      	sub	sp, #20
    1e94:	af00      	add	r7, sp, #0
    1e96:	6078      	str	r0, [r7, #4]
    uint8_t status = MSS_UART_INVALID_PARAM;
    1e98:	f04f 33ff 	mov.w	r3, #4294967295
    1e9c:	73fb      	strb	r3, [r7, #15]

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    1e9e:	687a      	ldr	r2, [r7, #4]
    1ea0:	f240 13f8 	movw	r3, #504	; 0x1f8
    1ea4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1ea8:	429a      	cmp	r2, r3
    1eaa:	d007      	beq.n	1ebc <MSS_UART_get_rx_status+0x2c>
    1eac:	687a      	ldr	r2, [r7, #4]
    1eae:	f240 13b8 	movw	r3, #440	; 0x1b8
    1eb2:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1eb6:	429a      	cmp	r2, r3
    1eb8:	d000      	beq.n	1ebc <MSS_UART_get_rx_status+0x2c>
    1eba:	be00      	bkpt	0x0000

    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
    1ebc:	687a      	ldr	r2, [r7, #4]
    1ebe:	f240 13f8 	movw	r3, #504	; 0x1f8
    1ec2:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1ec6:	429a      	cmp	r2, r3
    1ec8:	d006      	beq.n	1ed8 <MSS_UART_get_rx_status+0x48>
    1eca:	687a      	ldr	r2, [r7, #4]
    1ecc:	f240 13b8 	movw	r3, #440	; 0x1b8
    1ed0:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1ed4:	429a      	cmp	r2, r3
    1ed6:	d113      	bne.n	1f00 <MSS_UART_get_rx_status+0x70>
         * Bit 2 - Parity error status
         * Bit 3 - Frame error status
         * Bit 4 - Break interrupt indicator
         * Bit 7 - FIFO data error status
         */
        this_uart->status |= (this_uart->hw_reg->LSR);
    1ed8:	687b      	ldr	r3, [r7, #4]
    1eda:	7b5a      	ldrb	r2, [r3, #13]
    1edc:	687b      	ldr	r3, [r7, #4]
    1ede:	681b      	ldr	r3, [r3, #0]
    1ee0:	7d1b      	ldrb	r3, [r3, #20]
    1ee2:	b2db      	uxtb	r3, r3
    1ee4:	ea42 0303 	orr.w	r3, r2, r3
    1ee8:	b2da      	uxtb	r2, r3
    1eea:	687b      	ldr	r3, [r7, #4]
    1eec:	735a      	strb	r2, [r3, #13]
        status = (this_uart->status & STATUS_ERROR_MASK);
    1eee:	687b      	ldr	r3, [r7, #4]
    1ef0:	7b5b      	ldrb	r3, [r3, #13]
    1ef2:	f023 0361 	bic.w	r3, r3, #97	; 0x61
    1ef6:	73fb      	strb	r3, [r7, #15]
        /* Clear the sticky status after reading */
        this_uart->status = 0u;
    1ef8:	687b      	ldr	r3, [r7, #4]
    1efa:	f04f 0200 	mov.w	r2, #0
    1efe:	735a      	strb	r2, [r3, #13]
    }
    return status;
    1f00:	7bfb      	ldrb	r3, [r7, #15]
}
    1f02:	4618      	mov	r0, r3
    1f04:	f107 0714 	add.w	r7, r7, #20
    1f08:	46bd      	mov	sp, r7
    1f0a:	bc80      	pop	{r7}
    1f0c:	4770      	bx	lr
    1f0e:	bf00      	nop

00001f10 <MSS_UART_get_modem_status>:
uint8_t
MSS_UART_get_modem_status
(
    mss_uart_instance_t * this_uart
)
{
    1f10:	b480      	push	{r7}
    1f12:	b085      	sub	sp, #20
    1f14:	af00      	add	r7, sp, #0
    1f16:	6078      	str	r0, [r7, #4]
    uint8_t status = MSS_UART_INVALID_PARAM;
    1f18:	f04f 33ff 	mov.w	r3, #4294967295
    1f1c:	73fb      	strb	r3, [r7, #15]

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    1f1e:	687a      	ldr	r2, [r7, #4]
    1f20:	f240 13f8 	movw	r3, #504	; 0x1f8
    1f24:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1f28:	429a      	cmp	r2, r3
    1f2a:	d007      	beq.n	1f3c <MSS_UART_get_modem_status+0x2c>
    1f2c:	687a      	ldr	r2, [r7, #4]
    1f2e:	f240 13b8 	movw	r3, #440	; 0x1b8
    1f32:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1f36:	429a      	cmp	r2, r3
    1f38:	d000      	beq.n	1f3c <MSS_UART_get_modem_status+0x2c>
    1f3a:	be00      	bkpt	0x0000

    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
    1f3c:	687a      	ldr	r2, [r7, #4]
    1f3e:	f240 13f8 	movw	r3, #504	; 0x1f8
    1f42:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1f46:	429a      	cmp	r2, r3
    1f48:	d006      	beq.n	1f58 <MSS_UART_get_modem_status+0x48>
    1f4a:	687a      	ldr	r2, [r7, #4]
    1f4c:	f240 13b8 	movw	r3, #440	; 0x1b8
    1f50:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1f54:	429a      	cmp	r2, r3
    1f56:	d103      	bne.n	1f60 <MSS_UART_get_modem_status+0x50>
         * Bit 4 - Clear To Send
         * Bit 5 - Data Set Ready
         * Bit 6 - Ring Indicator
         * Bit 7 - Data Carrier Detect
         */
        status = this_uart->hw_reg->MSR;
    1f58:	687b      	ldr	r3, [r7, #4]
    1f5a:	681b      	ldr	r3, [r3, #0]
    1f5c:	7e1b      	ldrb	r3, [r3, #24]
    1f5e:	73fb      	strb	r3, [r7, #15]
    }
    return status;
    1f60:	7bfb      	ldrb	r3, [r7, #15]
}
    1f62:	4618      	mov	r0, r3
    1f64:	f107 0714 	add.w	r7, r7, #20
    1f68:	46bd      	mov	sp, r7
    1f6a:	bc80      	pop	{r7}
    1f6c:	4770      	bx	lr
    1f6e:	bf00      	nop

00001f70 <MSS_UART_get_tx_status>:
uint8_t
MSS_UART_get_tx_status
(
    mss_uart_instance_t * this_uart
)
{
    1f70:	b480      	push	{r7}
    1f72:	b085      	sub	sp, #20
    1f74:	af00      	add	r7, sp, #0
    1f76:	6078      	str	r0, [r7, #4]
    uint8_t status = MSS_UART_TX_BUSY;
    1f78:	f04f 0300 	mov.w	r3, #0
    1f7c:	73fb      	strb	r3, [r7, #15]

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    1f7e:	687a      	ldr	r2, [r7, #4]
    1f80:	f240 13f8 	movw	r3, #504	; 0x1f8
    1f84:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1f88:	429a      	cmp	r2, r3
    1f8a:	d007      	beq.n	1f9c <MSS_UART_get_tx_status+0x2c>
    1f8c:	687a      	ldr	r2, [r7, #4]
    1f8e:	f240 13b8 	movw	r3, #440	; 0x1b8
    1f92:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1f96:	429a      	cmp	r2, r3
    1f98:	d000      	beq.n	1f9c <MSS_UART_get_tx_status+0x2c>
    1f9a:	be00      	bkpt	0x0000

    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
    1f9c:	687a      	ldr	r2, [r7, #4]
    1f9e:	f240 13f8 	movw	r3, #504	; 0x1f8
    1fa2:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1fa6:	429a      	cmp	r2, r3
    1fa8:	d006      	beq.n	1fb8 <MSS_UART_get_tx_status+0x48>
    1faa:	687a      	ldr	r2, [r7, #4]
    1fac:	f240 13b8 	movw	r3, #440	; 0x1b8
    1fb0:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1fb4:	429a      	cmp	r2, r3
    1fb6:	d10f      	bne.n	1fd8 <MSS_UART_get_tx_status+0x68>
    {
        /* Read the Line Status Register and update the sticky record. */
        status = this_uart->hw_reg->LSR;
    1fb8:	687b      	ldr	r3, [r7, #4]
    1fba:	681b      	ldr	r3, [r3, #0]
    1fbc:	7d1b      	ldrb	r3, [r3, #20]
    1fbe:	73fb      	strb	r3, [r7, #15]
        this_uart->status |= status;
    1fc0:	687b      	ldr	r3, [r7, #4]
    1fc2:	7b5a      	ldrb	r2, [r3, #13]
    1fc4:	7bfb      	ldrb	r3, [r7, #15]
    1fc6:	ea42 0303 	orr.w	r3, r2, r3
    1fca:	b2da      	uxtb	r2, r3
    1fcc:	687b      	ldr	r3, [r7, #4]
    1fce:	735a      	strb	r2, [r3, #13]
        /*
         * Extract the transmit status bits from the UART's Line Status Register.
         * Bit 5 - Transmitter Holding Register/FIFO Empty (THRE) status. (If = 1, TX FIFO is empty)
         * Bit 6 - Transmitter Empty (TEMT) status. (If = 1, both TX FIFO and shift register are empty)
         */
        status &= (MSS_UART_THRE | MSS_UART_TEMT);
    1fd0:	7bfb      	ldrb	r3, [r7, #15]
    1fd2:	f003 0360 	and.w	r3, r3, #96	; 0x60
    1fd6:	73fb      	strb	r3, [r7, #15]
    }
    return status;
    1fd8:	7bfb      	ldrb	r3, [r7, #15]
}
    1fda:	4618      	mov	r0, r3
    1fdc:	f107 0714 	add.w	r7, r7, #20
    1fe0:	46bd      	mov	sp, r7
    1fe2:	bc80      	pop	{r7}
    1fe4:	4770      	bx	lr
    1fe6:	bf00      	nop

00001fe8 <MSS_UART_set_break>:
void
MSS_UART_set_break
(
    mss_uart_instance_t * this_uart
)
{
    1fe8:	b580      	push	{r7, lr}
    1fea:	b082      	sub	sp, #8
    1fec:	af00      	add	r7, sp, #0
    1fee:	6078      	str	r0, [r7, #4]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    1ff0:	687a      	ldr	r2, [r7, #4]
    1ff2:	f240 13f8 	movw	r3, #504	; 0x1f8
    1ff6:	f2c2 0300 	movt	r3, #8192	; 0x2000
    1ffa:	429a      	cmp	r2, r3
    1ffc:	d007      	beq.n	200e <MSS_UART_set_break+0x26>
    1ffe:	687a      	ldr	r2, [r7, #4]
    2000:	f240 13b8 	movw	r3, #440	; 0x1b8
    2004:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2008:	429a      	cmp	r2, r3
    200a:	d000      	beq.n	200e <MSS_UART_set_break+0x26>
    200c:	be00      	bkpt	0x0000
    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
    200e:	687a      	ldr	r2, [r7, #4]
    2010:	f240 13f8 	movw	r3, #504	; 0x1f8
    2014:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2018:	429a      	cmp	r2, r3
    201a:	d006      	beq.n	202a <MSS_UART_set_break+0x42>
    201c:	687a      	ldr	r2, [r7, #4]
    201e:	f240 13b8 	movw	r3, #440	; 0x1b8
    2022:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2026:	429a      	cmp	r2, r3
    2028:	d108      	bne.n	203c <MSS_UART_set_break+0x54>
    {
        /* set break charecter on Tx line */
        set_bit_reg8(&this_uart->hw_reg->LCR,SB);
    202a:	687b      	ldr	r3, [r7, #4]
    202c:	681b      	ldr	r3, [r3, #0]
    202e:	f103 030c 	add.w	r3, r3, #12
    2032:	4618      	mov	r0, r3
    2034:	f04f 0106 	mov.w	r1, #6
    2038:	f7ff f8a4 	bl	1184 <set_bit_reg8>
    }
}
    203c:	f107 0708 	add.w	r7, r7, #8
    2040:	46bd      	mov	sp, r7
    2042:	bd80      	pop	{r7, pc}

00002044 <MSS_UART_clear_break>:
void
MSS_UART_clear_break
(
    mss_uart_instance_t * this_uart
)
{
    2044:	b580      	push	{r7, lr}
    2046:	b082      	sub	sp, #8
    2048:	af00      	add	r7, sp, #0
    204a:	6078      	str	r0, [r7, #4]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    204c:	687a      	ldr	r2, [r7, #4]
    204e:	f240 13f8 	movw	r3, #504	; 0x1f8
    2052:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2056:	429a      	cmp	r2, r3
    2058:	d007      	beq.n	206a <MSS_UART_clear_break+0x26>
    205a:	687a      	ldr	r2, [r7, #4]
    205c:	f240 13b8 	movw	r3, #440	; 0x1b8
    2060:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2064:	429a      	cmp	r2, r3
    2066:	d000      	beq.n	206a <MSS_UART_clear_break+0x26>
    2068:	be00      	bkpt	0x0000
    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
    206a:	687a      	ldr	r2, [r7, #4]
    206c:	f240 13f8 	movw	r3, #504	; 0x1f8
    2070:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2074:	429a      	cmp	r2, r3
    2076:	d006      	beq.n	2086 <MSS_UART_clear_break+0x42>
    2078:	687a      	ldr	r2, [r7, #4]
    207a:	f240 13b8 	movw	r3, #440	; 0x1b8
    207e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2082:	429a      	cmp	r2, r3
    2084:	d108      	bne.n	2098 <MSS_UART_clear_break+0x54>
    {
        /* remove break charecter from Tx line */
        clear_bit_reg8(&this_uart->hw_reg->LCR,SB);
    2086:	687b      	ldr	r3, [r7, #4]
    2088:	681b      	ldr	r3, [r3, #0]
    208a:	f103 030c 	add.w	r3, r3, #12
    208e:	4618      	mov	r0, r3
    2090:	f04f 0106 	mov.w	r1, #6
    2094:	f7ff f896 	bl	11c4 <clear_bit_reg8>
    }
}
    2098:	f107 0708 	add.w	r7, r7, #8
    209c:	46bd      	mov	sp, r7
    209e:	bd80      	pop	{r7, pc}

000020a0 <MSS_UART_set_pidpei_handler>:
MSS_UART_set_pidpei_handler
(
    mss_uart_instance_t * this_uart,
    mss_uart_irq_handler_t handler
)
{
    20a0:	b580      	push	{r7, lr}
    20a2:	b082      	sub	sp, #8
    20a4:	af00      	add	r7, sp, #0
    20a6:	6078      	str	r0, [r7, #4]
    20a8:	6039      	str	r1, [r7, #0]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    20aa:	687a      	ldr	r2, [r7, #4]
    20ac:	f240 13f8 	movw	r3, #504	; 0x1f8
    20b0:	f2c2 0300 	movt	r3, #8192	; 0x2000
    20b4:	429a      	cmp	r2, r3
    20b6:	d007      	beq.n	20c8 <MSS_UART_set_pidpei_handler+0x28>
    20b8:	687a      	ldr	r2, [r7, #4]
    20ba:	f240 13b8 	movw	r3, #440	; 0x1b8
    20be:	f2c2 0300 	movt	r3, #8192	; 0x2000
    20c2:	429a      	cmp	r2, r3
    20c4:	d000      	beq.n	20c8 <MSS_UART_set_pidpei_handler+0x28>
    20c6:	be00      	bkpt	0x0000
    ASSERT(handler != INVALID_IRQ_HANDLER);
    20c8:	683b      	ldr	r3, [r7, #0]
    20ca:	2b00      	cmp	r3, #0
    20cc:	d100      	bne.n	20d0 <MSS_UART_set_pidpei_handler+0x30>
    20ce:	be00      	bkpt	0x0000

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
    20d0:	687a      	ldr	r2, [r7, #4]
    20d2:	f240 13f8 	movw	r3, #504	; 0x1f8
    20d6:	f2c2 0300 	movt	r3, #8192	; 0x2000
    20da:	429a      	cmp	r2, r3
    20dc:	d006      	beq.n	20ec <MSS_UART_set_pidpei_handler+0x4c>
    20de:	687a      	ldr	r2, [r7, #4]
    20e0:	f240 13b8 	movw	r3, #440	; 0x1b8
    20e4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    20e8:	429a      	cmp	r2, r3
    20ea:	d11a      	bne.n	2122 <MSS_UART_set_pidpei_handler+0x82>
    20ec:	683b      	ldr	r3, [r7, #0]
    20ee:	2b00      	cmp	r3, #0
    20f0:	d017      	beq.n	2122 <MSS_UART_set_pidpei_handler+0x82>
       (handler != INVALID_IRQ_HANDLER))
    {
        this_uart->pid_pei_handler = handler;
    20f2:	687b      	ldr	r3, [r7, #4]
    20f4:	683a      	ldr	r2, [r7, #0]
    20f6:	635a      	str	r2, [r3, #52]	; 0x34

        /* Clear any previously pended interrupts */
        NVIC_ClearPendingIRQ( this_uart->irqn );
    20f8:	687b      	ldr	r3, [r7, #4]
    20fa:	791b      	ldrb	r3, [r3, #4]
    20fc:	b25b      	sxtb	r3, r3
    20fe:	4618      	mov	r0, r3
    2100:	f7ff f822 	bl	1148 <NVIC_ClearPendingIRQ>

        /* Enable PID parity error interrupt. */
        set_bit_reg8(&this_uart->hw_reg->IEM,EPID_PEI);
    2104:	687b      	ldr	r3, [r7, #4]
    2106:	681b      	ldr	r3, [r3, #0]
    2108:	f103 0324 	add.w	r3, r3, #36	; 0x24
    210c:	4618      	mov	r0, r3
    210e:	f04f 0102 	mov.w	r1, #2
    2112:	f7ff f837 	bl	1184 <set_bit_reg8>

        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
        NVIC_EnableIRQ(this_uart->irqn);
    2116:	687b      	ldr	r3, [r7, #4]
    2118:	791b      	ldrb	r3, [r3, #4]
    211a:	b25b      	sxtb	r3, r3
    211c:	4618      	mov	r0, r3
    211e:	f7fe ffd9 	bl	10d4 <NVIC_EnableIRQ>
    }
}
    2122:	f107 0708 	add.w	r7, r7, #8
    2126:	46bd      	mov	sp, r7
    2128:	bd80      	pop	{r7, pc}
    212a:	bf00      	nop

0000212c <MSS_UART_set_linbreak_handler>:
MSS_UART_set_linbreak_handler
(
    mss_uart_instance_t * this_uart,
    mss_uart_irq_handler_t handler
)
{
    212c:	b580      	push	{r7, lr}
    212e:	b082      	sub	sp, #8
    2130:	af00      	add	r7, sp, #0
    2132:	6078      	str	r0, [r7, #4]
    2134:	6039      	str	r1, [r7, #0]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    2136:	687a      	ldr	r2, [r7, #4]
    2138:	f240 13f8 	movw	r3, #504	; 0x1f8
    213c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2140:	429a      	cmp	r2, r3
    2142:	d007      	beq.n	2154 <MSS_UART_set_linbreak_handler+0x28>
    2144:	687a      	ldr	r2, [r7, #4]
    2146:	f240 13b8 	movw	r3, #440	; 0x1b8
    214a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    214e:	429a      	cmp	r2, r3
    2150:	d000      	beq.n	2154 <MSS_UART_set_linbreak_handler+0x28>
    2152:	be00      	bkpt	0x0000
    ASSERT(handler != INVALID_IRQ_HANDLER);
    2154:	683b      	ldr	r3, [r7, #0]
    2156:	2b00      	cmp	r3, #0
    2158:	d100      	bne.n	215c <MSS_UART_set_linbreak_handler+0x30>
    215a:	be00      	bkpt	0x0000

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
    215c:	687a      	ldr	r2, [r7, #4]
    215e:	f240 13f8 	movw	r3, #504	; 0x1f8
    2162:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2166:	429a      	cmp	r2, r3
    2168:	d006      	beq.n	2178 <MSS_UART_set_linbreak_handler+0x4c>
    216a:	687a      	ldr	r2, [r7, #4]
    216c:	f240 13b8 	movw	r3, #440	; 0x1b8
    2170:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2174:	429a      	cmp	r2, r3
    2176:	d11a      	bne.n	21ae <MSS_UART_set_linbreak_handler+0x82>
    2178:	683b      	ldr	r3, [r7, #0]
    217a:	2b00      	cmp	r3, #0
    217c:	d017      	beq.n	21ae <MSS_UART_set_linbreak_handler+0x82>
       (handler != INVALID_IRQ_HANDLER))
    {
        this_uart->break_handler = handler;
    217e:	687b      	ldr	r3, [r7, #4]
    2180:	683a      	ldr	r2, [r7, #0]
    2182:	639a      	str	r2, [r3, #56]	; 0x38

        /* Clear any previously pended interrupts */
        NVIC_ClearPendingIRQ( this_uart->irqn );
    2184:	687b      	ldr	r3, [r7, #4]
    2186:	791b      	ldrb	r3, [r3, #4]
    2188:	b25b      	sxtb	r3, r3
    218a:	4618      	mov	r0, r3
    218c:	f7fe ffdc 	bl	1148 <NVIC_ClearPendingIRQ>

        /* Enable LIN break detection interrupt. */
        set_bit_reg8(&this_uart->hw_reg->IEM,ELINBI);
    2190:	687b      	ldr	r3, [r7, #4]
    2192:	681b      	ldr	r3, [r3, #0]
    2194:	f103 0324 	add.w	r3, r3, #36	; 0x24
    2198:	4618      	mov	r0, r3
    219a:	f04f 0103 	mov.w	r1, #3
    219e:	f7fe fff1 	bl	1184 <set_bit_reg8>

        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
        NVIC_EnableIRQ(this_uart->irqn);
    21a2:	687b      	ldr	r3, [r7, #4]
    21a4:	791b      	ldrb	r3, [r3, #4]
    21a6:	b25b      	sxtb	r3, r3
    21a8:	4618      	mov	r0, r3
    21aa:	f7fe ff93 	bl	10d4 <NVIC_EnableIRQ>
    }
}
    21ae:	f107 0708 	add.w	r7, r7, #8
    21b2:	46bd      	mov	sp, r7
    21b4:	bd80      	pop	{r7, pc}
    21b6:	bf00      	nop

000021b8 <MSS_UART_set_linsync_handler>:
MSS_UART_set_linsync_handler
(
    mss_uart_instance_t * this_uart,
    mss_uart_irq_handler_t handler
)
{
    21b8:	b580      	push	{r7, lr}
    21ba:	b082      	sub	sp, #8
    21bc:	af00      	add	r7, sp, #0
    21be:	6078      	str	r0, [r7, #4]
    21c0:	6039      	str	r1, [r7, #0]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    21c2:	687a      	ldr	r2, [r7, #4]
    21c4:	f240 13f8 	movw	r3, #504	; 0x1f8
    21c8:	f2c2 0300 	movt	r3, #8192	; 0x2000
    21cc:	429a      	cmp	r2, r3
    21ce:	d007      	beq.n	21e0 <MSS_UART_set_linsync_handler+0x28>
    21d0:	687a      	ldr	r2, [r7, #4]
    21d2:	f240 13b8 	movw	r3, #440	; 0x1b8
    21d6:	f2c2 0300 	movt	r3, #8192	; 0x2000
    21da:	429a      	cmp	r2, r3
    21dc:	d000      	beq.n	21e0 <MSS_UART_set_linsync_handler+0x28>
    21de:	be00      	bkpt	0x0000
    ASSERT(handler != INVALID_IRQ_HANDLER);
    21e0:	683b      	ldr	r3, [r7, #0]
    21e2:	2b00      	cmp	r3, #0
    21e4:	d100      	bne.n	21e8 <MSS_UART_set_linsync_handler+0x30>
    21e6:	be00      	bkpt	0x0000

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
    21e8:	687a      	ldr	r2, [r7, #4]
    21ea:	f240 13f8 	movw	r3, #504	; 0x1f8
    21ee:	f2c2 0300 	movt	r3, #8192	; 0x2000
    21f2:	429a      	cmp	r2, r3
    21f4:	d006      	beq.n	2204 <MSS_UART_set_linsync_handler+0x4c>
    21f6:	687a      	ldr	r2, [r7, #4]
    21f8:	f240 13b8 	movw	r3, #440	; 0x1b8
    21fc:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2200:	429a      	cmp	r2, r3
    2202:	d11a      	bne.n	223a <MSS_UART_set_linsync_handler+0x82>
    2204:	683b      	ldr	r3, [r7, #0]
    2206:	2b00      	cmp	r3, #0
    2208:	d017      	beq.n	223a <MSS_UART_set_linsync_handler+0x82>
       (handler != INVALID_IRQ_HANDLER))
    {
        this_uart->sync_handler = handler;
    220a:	687b      	ldr	r3, [r7, #4]
    220c:	683a      	ldr	r2, [r7, #0]
    220e:	63da      	str	r2, [r3, #60]	; 0x3c

        /* Clear any previously pended interrupts */
        NVIC_ClearPendingIRQ( this_uart->irqn );
    2210:	687b      	ldr	r3, [r7, #4]
    2212:	791b      	ldrb	r3, [r3, #4]
    2214:	b25b      	sxtb	r3, r3
    2216:	4618      	mov	r0, r3
    2218:	f7fe ff96 	bl	1148 <NVIC_ClearPendingIRQ>

        /* Enable LIN sync detection interrupt. */
        set_bit_reg8(&this_uart->hw_reg->IEM,ELINSI);
    221c:	687b      	ldr	r3, [r7, #4]
    221e:	681b      	ldr	r3, [r3, #0]
    2220:	f103 0324 	add.w	r3, r3, #36	; 0x24
    2224:	4618      	mov	r0, r3
    2226:	f04f 0104 	mov.w	r1, #4
    222a:	f7fe ffab 	bl	1184 <set_bit_reg8>

        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
        NVIC_EnableIRQ(this_uart->irqn);
    222e:	687b      	ldr	r3, [r7, #4]
    2230:	791b      	ldrb	r3, [r3, #4]
    2232:	b25b      	sxtb	r3, r3
    2234:	4618      	mov	r0, r3
    2236:	f7fe ff4d 	bl	10d4 <NVIC_EnableIRQ>
    }
}
    223a:	f107 0708 	add.w	r7, r7, #8
    223e:	46bd      	mov	sp, r7
    2240:	bd80      	pop	{r7, pc}
    2242:	bf00      	nop

00002244 <MSS_UART_set_nack_handler>:
MSS_UART_set_nack_handler
(
    mss_uart_instance_t * this_uart,
    mss_uart_irq_handler_t handler
)
{
    2244:	b580      	push	{r7, lr}
    2246:	b082      	sub	sp, #8
    2248:	af00      	add	r7, sp, #0
    224a:	6078      	str	r0, [r7, #4]
    224c:	6039      	str	r1, [r7, #0]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    224e:	687a      	ldr	r2, [r7, #4]
    2250:	f240 13f8 	movw	r3, #504	; 0x1f8
    2254:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2258:	429a      	cmp	r2, r3
    225a:	d007      	beq.n	226c <MSS_UART_set_nack_handler+0x28>
    225c:	687a      	ldr	r2, [r7, #4]
    225e:	f240 13b8 	movw	r3, #440	; 0x1b8
    2262:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2266:	429a      	cmp	r2, r3
    2268:	d000      	beq.n	226c <MSS_UART_set_nack_handler+0x28>
    226a:	be00      	bkpt	0x0000
    ASSERT(handler != INVALID_IRQ_HANDLER);
    226c:	683b      	ldr	r3, [r7, #0]
    226e:	2b00      	cmp	r3, #0
    2270:	d100      	bne.n	2274 <MSS_UART_set_nack_handler+0x30>
    2272:	be00      	bkpt	0x0000

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
    2274:	687a      	ldr	r2, [r7, #4]
    2276:	f240 13f8 	movw	r3, #504	; 0x1f8
    227a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    227e:	429a      	cmp	r2, r3
    2280:	d006      	beq.n	2290 <MSS_UART_set_nack_handler+0x4c>
    2282:	687a      	ldr	r2, [r7, #4]
    2284:	f240 13b8 	movw	r3, #440	; 0x1b8
    2288:	f2c2 0300 	movt	r3, #8192	; 0x2000
    228c:	429a      	cmp	r2, r3
    228e:	d11a      	bne.n	22c6 <MSS_UART_set_nack_handler+0x82>
    2290:	683b      	ldr	r3, [r7, #0]
    2292:	2b00      	cmp	r3, #0
    2294:	d017      	beq.n	22c6 <MSS_UART_set_nack_handler+0x82>
       (handler != INVALID_IRQ_HANDLER))
    {
        this_uart->nack_handler = handler;
    2296:	687b      	ldr	r3, [r7, #4]
    2298:	683a      	ldr	r2, [r7, #0]
    229a:	631a      	str	r2, [r3, #48]	; 0x30

        /* Clear any previously pended interrupts */
        NVIC_ClearPendingIRQ( this_uart->irqn );
    229c:	687b      	ldr	r3, [r7, #4]
    229e:	791b      	ldrb	r3, [r3, #4]
    22a0:	b25b      	sxtb	r3, r3
    22a2:	4618      	mov	r0, r3
    22a4:	f7fe ff50 	bl	1148 <NVIC_ClearPendingIRQ>

        /* Enable LIN sync detection interrupt. */
        set_bit_reg8(&this_uart->hw_reg->IEM,ENACKI);
    22a8:	687b      	ldr	r3, [r7, #4]
    22aa:	681b      	ldr	r3, [r3, #0]
    22ac:	f103 0324 	add.w	r3, r3, #36	; 0x24
    22b0:	4618      	mov	r0, r3
    22b2:	f04f 0101 	mov.w	r1, #1
    22b6:	f7fe ff65 	bl	1184 <set_bit_reg8>

        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
        NVIC_EnableIRQ(this_uart->irqn);
    22ba:	687b      	ldr	r3, [r7, #4]
    22bc:	791b      	ldrb	r3, [r3, #4]
    22be:	b25b      	sxtb	r3, r3
    22c0:	4618      	mov	r0, r3
    22c2:	f7fe ff07 	bl	10d4 <NVIC_EnableIRQ>
    }
}
    22c6:	f107 0708 	add.w	r7, r7, #8
    22ca:	46bd      	mov	sp, r7
    22cc:	bd80      	pop	{r7, pc}
    22ce:	bf00      	nop

000022d0 <MSS_UART_set_rx_timeout_handler>:
MSS_UART_set_rx_timeout_handler
(
    mss_uart_instance_t * this_uart,
    mss_uart_irq_handler_t handler
)
{
    22d0:	b580      	push	{r7, lr}
    22d2:	b082      	sub	sp, #8
    22d4:	af00      	add	r7, sp, #0
    22d6:	6078      	str	r0, [r7, #4]
    22d8:	6039      	str	r1, [r7, #0]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    22da:	687a      	ldr	r2, [r7, #4]
    22dc:	f240 13f8 	movw	r3, #504	; 0x1f8
    22e0:	f2c2 0300 	movt	r3, #8192	; 0x2000
    22e4:	429a      	cmp	r2, r3
    22e6:	d007      	beq.n	22f8 <MSS_UART_set_rx_timeout_handler+0x28>
    22e8:	687a      	ldr	r2, [r7, #4]
    22ea:	f240 13b8 	movw	r3, #440	; 0x1b8
    22ee:	f2c2 0300 	movt	r3, #8192	; 0x2000
    22f2:	429a      	cmp	r2, r3
    22f4:	d000      	beq.n	22f8 <MSS_UART_set_rx_timeout_handler+0x28>
    22f6:	be00      	bkpt	0x0000
    ASSERT(handler != INVALID_IRQ_HANDLER);
    22f8:	683b      	ldr	r3, [r7, #0]
    22fa:	2b00      	cmp	r3, #0
    22fc:	d100      	bne.n	2300 <MSS_UART_set_rx_timeout_handler+0x30>
    22fe:	be00      	bkpt	0x0000

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
    2300:	687a      	ldr	r2, [r7, #4]
    2302:	f240 13f8 	movw	r3, #504	; 0x1f8
    2306:	f2c2 0300 	movt	r3, #8192	; 0x2000
    230a:	429a      	cmp	r2, r3
    230c:	d006      	beq.n	231c <MSS_UART_set_rx_timeout_handler+0x4c>
    230e:	687a      	ldr	r2, [r7, #4]
    2310:	f240 13b8 	movw	r3, #440	; 0x1b8
    2314:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2318:	429a      	cmp	r2, r3
    231a:	d11a      	bne.n	2352 <MSS_UART_set_rx_timeout_handler+0x82>
    231c:	683b      	ldr	r3, [r7, #0]
    231e:	2b00      	cmp	r3, #0
    2320:	d017      	beq.n	2352 <MSS_UART_set_rx_timeout_handler+0x82>
       (handler != INVALID_IRQ_HANDLER))
    {
        this_uart->rto_handler = handler;
    2322:	687b      	ldr	r3, [r7, #4]
    2324:	683a      	ldr	r2, [r7, #0]
    2326:	62da      	str	r2, [r3, #44]	; 0x2c

        /* Clear any previously pended interrupts */
        NVIC_ClearPendingIRQ( this_uart->irqn );
    2328:	687b      	ldr	r3, [r7, #4]
    232a:	791b      	ldrb	r3, [r3, #4]
    232c:	b25b      	sxtb	r3, r3
    232e:	4618      	mov	r0, r3
    2330:	f7fe ff0a 	bl	1148 <NVIC_ClearPendingIRQ>

        /* Enable receiver timeout interrupt. */
        set_bit_reg8(&this_uart->hw_reg->IEM,ERTOI);
    2334:	687b      	ldr	r3, [r7, #4]
    2336:	681b      	ldr	r3, [r3, #0]
    2338:	f103 0324 	add.w	r3, r3, #36	; 0x24
    233c:	4618      	mov	r0, r3
    233e:	f04f 0100 	mov.w	r1, #0
    2342:	f7fe ff1f 	bl	1184 <set_bit_reg8>

        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
        NVIC_EnableIRQ(this_uart->irqn);
    2346:	687b      	ldr	r3, [r7, #4]
    2348:	791b      	ldrb	r3, [r3, #4]
    234a:	b25b      	sxtb	r3, r3
    234c:	4618      	mov	r0, r3
    234e:	f7fe fec1 	bl	10d4 <NVIC_EnableIRQ>
    }
}
    2352:	f107 0708 	add.w	r7, r7, #8
    2356:	46bd      	mov	sp, r7
    2358:	bd80      	pop	{r7, pc}
    235a:	bf00      	nop

0000235c <MSS_UART_enable_half_duplex>:
void 
MSS_UART_enable_half_duplex
(
    mss_uart_instance_t * this_uart
)
{
    235c:	b580      	push	{r7, lr}
    235e:	b082      	sub	sp, #8
    2360:	af00      	add	r7, sp, #0
    2362:	6078      	str	r0, [r7, #4]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    2364:	687a      	ldr	r2, [r7, #4]
    2366:	f240 13f8 	movw	r3, #504	; 0x1f8
    236a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    236e:	429a      	cmp	r2, r3
    2370:	d007      	beq.n	2382 <MSS_UART_enable_half_duplex+0x26>
    2372:	687a      	ldr	r2, [r7, #4]
    2374:	f240 13b8 	movw	r3, #440	; 0x1b8
    2378:	f2c2 0300 	movt	r3, #8192	; 0x2000
    237c:	429a      	cmp	r2, r3
    237e:	d000      	beq.n	2382 <MSS_UART_enable_half_duplex+0x26>
    2380:	be00      	bkpt	0x0000
    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
    2382:	687a      	ldr	r2, [r7, #4]
    2384:	f240 13f8 	movw	r3, #504	; 0x1f8
    2388:	f2c2 0300 	movt	r3, #8192	; 0x2000
    238c:	429a      	cmp	r2, r3
    238e:	d006      	beq.n	239e <MSS_UART_enable_half_duplex+0x42>
    2390:	687a      	ldr	r2, [r7, #4]
    2392:	f240 13b8 	movw	r3, #440	; 0x1b8
    2396:	f2c2 0300 	movt	r3, #8192	; 0x2000
    239a:	429a      	cmp	r2, r3
    239c:	d108      	bne.n	23b0 <MSS_UART_enable_half_duplex+0x54>
    {
        /* enable single wire half-duplex mode */
        set_bit_reg8(&this_uart->hw_reg->MM2,ESWM);
    239e:	687b      	ldr	r3, [r7, #4]
    23a0:	681b      	ldr	r3, [r3, #0]
    23a2:	f103 0338 	add.w	r3, r3, #56	; 0x38
    23a6:	4618      	mov	r0, r3
    23a8:	f04f 0103 	mov.w	r1, #3
    23ac:	f7fe feea 	bl	1184 <set_bit_reg8>
    }
}
    23b0:	f107 0708 	add.w	r7, r7, #8
    23b4:	46bd      	mov	sp, r7
    23b6:	bd80      	pop	{r7, pc}

000023b8 <MSS_UART_disable_half_duplex>:
void 
MSS_UART_disable_half_duplex
(
    mss_uart_instance_t * this_uart
)
{
    23b8:	b580      	push	{r7, lr}
    23ba:	b082      	sub	sp, #8
    23bc:	af00      	add	r7, sp, #0
    23be:	6078      	str	r0, [r7, #4]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    23c0:	687a      	ldr	r2, [r7, #4]
    23c2:	f240 13f8 	movw	r3, #504	; 0x1f8
    23c6:	f2c2 0300 	movt	r3, #8192	; 0x2000
    23ca:	429a      	cmp	r2, r3
    23cc:	d007      	beq.n	23de <MSS_UART_disable_half_duplex+0x26>
    23ce:	687a      	ldr	r2, [r7, #4]
    23d0:	f240 13b8 	movw	r3, #440	; 0x1b8
    23d4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    23d8:	429a      	cmp	r2, r3
    23da:	d000      	beq.n	23de <MSS_UART_disable_half_duplex+0x26>
    23dc:	be00      	bkpt	0x0000
    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
    23de:	687a      	ldr	r2, [r7, #4]
    23e0:	f240 13f8 	movw	r3, #504	; 0x1f8
    23e4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    23e8:	429a      	cmp	r2, r3
    23ea:	d006      	beq.n	23fa <MSS_UART_disable_half_duplex+0x42>
    23ec:	687a      	ldr	r2, [r7, #4]
    23ee:	f240 13b8 	movw	r3, #440	; 0x1b8
    23f2:	f2c2 0300 	movt	r3, #8192	; 0x2000
    23f6:	429a      	cmp	r2, r3
    23f8:	d108      	bne.n	240c <MSS_UART_disable_half_duplex+0x54>
    {
        /* enable single wire half-duplex mode */
        clear_bit_reg8(&this_uart->hw_reg->MM2,ESWM);
    23fa:	687b      	ldr	r3, [r7, #4]
    23fc:	681b      	ldr	r3, [r3, #0]
    23fe:	f103 0338 	add.w	r3, r3, #56	; 0x38
    2402:	4618      	mov	r0, r3
    2404:	f04f 0103 	mov.w	r1, #3
    2408:	f7fe fedc 	bl	11c4 <clear_bit_reg8>
    }
}
    240c:	f107 0708 	add.w	r7, r7, #8
    2410:	46bd      	mov	sp, r7
    2412:	bd80      	pop	{r7, pc}

00002414 <MSS_UART_set_rx_endian>:
MSS_UART_set_rx_endian
(
    mss_uart_instance_t * this_uart,
    mss_uart_endian_t endian    
)
{
    2414:	b580      	push	{r7, lr}
    2416:	b082      	sub	sp, #8
    2418:	af00      	add	r7, sp, #0
    241a:	6078      	str	r0, [r7, #4]
    241c:	460b      	mov	r3, r1
    241e:	70fb      	strb	r3, [r7, #3]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    2420:	687a      	ldr	r2, [r7, #4]
    2422:	f240 13f8 	movw	r3, #504	; 0x1f8
    2426:	f2c2 0300 	movt	r3, #8192	; 0x2000
    242a:	429a      	cmp	r2, r3
    242c:	d007      	beq.n	243e <MSS_UART_set_rx_endian+0x2a>
    242e:	687a      	ldr	r2, [r7, #4]
    2430:	f240 13b8 	movw	r3, #440	; 0x1b8
    2434:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2438:	429a      	cmp	r2, r3
    243a:	d000      	beq.n	243e <MSS_UART_set_rx_endian+0x2a>
    243c:	be00      	bkpt	0x0000
    ASSERT(MSS_UART_INVALID_ENDIAN > endian);
    243e:	78fb      	ldrb	r3, [r7, #3]
    2440:	2b01      	cmp	r3, #1
    2442:	d900      	bls.n	2446 <MSS_UART_set_rx_endian+0x32>
    2444:	be00      	bkpt	0x0000

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && 
    2446:	687a      	ldr	r2, [r7, #4]
    2448:	f240 13f8 	movw	r3, #504	; 0x1f8
    244c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2450:	429a      	cmp	r2, r3
    2452:	d006      	beq.n	2462 <MSS_UART_set_rx_endian+0x4e>
    2454:	687a      	ldr	r2, [r7, #4]
    2456:	f240 13b8 	movw	r3, #440	; 0x1b8
    245a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    245e:	429a      	cmp	r2, r3
    2460:	d118      	bne.n	2494 <MSS_UART_set_rx_endian+0x80>
    2462:	78fb      	ldrb	r3, [r7, #3]
    2464:	2b01      	cmp	r3, #1
    2466:	d815      	bhi.n	2494 <MSS_UART_set_rx_endian+0x80>
       (MSS_UART_INVALID_ENDIAN > endian))
    {
        /* Configure MSB first / LSB first for receiver */
        ((MSS_UART_LITTLEEND == endian) ? (clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_RX)) :
    2468:	78fb      	ldrb	r3, [r7, #3]
    246a:	2b00      	cmp	r3, #0
    246c:	d109      	bne.n	2482 <MSS_UART_set_rx_endian+0x6e>
    246e:	687b      	ldr	r3, [r7, #4]
    2470:	681b      	ldr	r3, [r3, #0]
    2472:	f103 0334 	add.w	r3, r3, #52	; 0x34
    2476:	4618      	mov	r0, r3
    2478:	f04f 0100 	mov.w	r1, #0
    247c:	f7fe fea2 	bl	11c4 <clear_bit_reg8>
    2480:	e008      	b.n	2494 <MSS_UART_set_rx_endian+0x80>
                                          (set_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_RX)));
    2482:	687b      	ldr	r3, [r7, #4]
    2484:	681b      	ldr	r3, [r3, #0]
    2486:	f103 0334 	add.w	r3, r3, #52	; 0x34
    248a:	4618      	mov	r0, r3
    248c:	f04f 0100 	mov.w	r1, #0
    2490:	f7fe fe78 	bl	1184 <set_bit_reg8>
    }
}
    2494:	f107 0708 	add.w	r7, r7, #8
    2498:	46bd      	mov	sp, r7
    249a:	bd80      	pop	{r7, pc}

0000249c <MSS_UART_set_tx_endian>:
MSS_UART_set_tx_endian
(
    mss_uart_instance_t * this_uart,
    mss_uart_endian_t endian    
)
{
    249c:	b580      	push	{r7, lr}
    249e:	b082      	sub	sp, #8
    24a0:	af00      	add	r7, sp, #0
    24a2:	6078      	str	r0, [r7, #4]
    24a4:	460b      	mov	r3, r1
    24a6:	70fb      	strb	r3, [r7, #3]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    24a8:	687a      	ldr	r2, [r7, #4]
    24aa:	f240 13f8 	movw	r3, #504	; 0x1f8
    24ae:	f2c2 0300 	movt	r3, #8192	; 0x2000
    24b2:	429a      	cmp	r2, r3
    24b4:	d007      	beq.n	24c6 <MSS_UART_set_tx_endian+0x2a>
    24b6:	687a      	ldr	r2, [r7, #4]
    24b8:	f240 13b8 	movw	r3, #440	; 0x1b8
    24bc:	f2c2 0300 	movt	r3, #8192	; 0x2000
    24c0:	429a      	cmp	r2, r3
    24c2:	d000      	beq.n	24c6 <MSS_UART_set_tx_endian+0x2a>
    24c4:	be00      	bkpt	0x0000
    ASSERT(MSS_UART_INVALID_ENDIAN > endian);
    24c6:	78fb      	ldrb	r3, [r7, #3]
    24c8:	2b01      	cmp	r3, #1
    24ca:	d900      	bls.n	24ce <MSS_UART_set_tx_endian+0x32>
    24cc:	be00      	bkpt	0x0000

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && 
    24ce:	687a      	ldr	r2, [r7, #4]
    24d0:	f240 13f8 	movw	r3, #504	; 0x1f8
    24d4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    24d8:	429a      	cmp	r2, r3
    24da:	d006      	beq.n	24ea <MSS_UART_set_tx_endian+0x4e>
    24dc:	687a      	ldr	r2, [r7, #4]
    24de:	f240 13b8 	movw	r3, #440	; 0x1b8
    24e2:	f2c2 0300 	movt	r3, #8192	; 0x2000
    24e6:	429a      	cmp	r2, r3
    24e8:	d118      	bne.n	251c <MSS_UART_set_tx_endian+0x80>
    24ea:	78fb      	ldrb	r3, [r7, #3]
    24ec:	2b01      	cmp	r3, #1
    24ee:	d815      	bhi.n	251c <MSS_UART_set_tx_endian+0x80>
       (MSS_UART_INVALID_ENDIAN > endian))
    {
        /* Configure MSB first / LSB first for transmitter */
        ((MSS_UART_LITTLEEND == endian) ? (clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_TX)) :
    24f0:	78fb      	ldrb	r3, [r7, #3]
    24f2:	2b00      	cmp	r3, #0
    24f4:	d109      	bne.n	250a <MSS_UART_set_tx_endian+0x6e>
    24f6:	687b      	ldr	r3, [r7, #4]
    24f8:	681b      	ldr	r3, [r3, #0]
    24fa:	f103 0334 	add.w	r3, r3, #52	; 0x34
    24fe:	4618      	mov	r0, r3
    2500:	f04f 0101 	mov.w	r1, #1
    2504:	f7fe fe5e 	bl	11c4 <clear_bit_reg8>
    2508:	e008      	b.n	251c <MSS_UART_set_tx_endian+0x80>
                                          (set_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_TX)) ) ;
    250a:	687b      	ldr	r3, [r7, #4]
    250c:	681b      	ldr	r3, [r3, #0]
    250e:	f103 0334 	add.w	r3, r3, #52	; 0x34
    2512:	4618      	mov	r0, r3
    2514:	f04f 0101 	mov.w	r1, #1
    2518:	f7fe fe34 	bl	1184 <set_bit_reg8>
    }
}
    251c:	f107 0708 	add.w	r7, r7, #8
    2520:	46bd      	mov	sp, r7
    2522:	bd80      	pop	{r7, pc}

00002524 <MSS_UART_set_filter_length>:
MSS_UART_set_filter_length
(
    mss_uart_instance_t * this_uart,
    mss_uart_filter_length_t length
)
{
    2524:	b480      	push	{r7}
    2526:	b083      	sub	sp, #12
    2528:	af00      	add	r7, sp, #0
    252a:	6078      	str	r0, [r7, #4]
    252c:	460b      	mov	r3, r1
    252e:	70fb      	strb	r3, [r7, #3]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    2530:	687a      	ldr	r2, [r7, #4]
    2532:	f240 13f8 	movw	r3, #504	; 0x1f8
    2536:	f2c2 0300 	movt	r3, #8192	; 0x2000
    253a:	429a      	cmp	r2, r3
    253c:	d007      	beq.n	254e <MSS_UART_set_filter_length+0x2a>
    253e:	687a      	ldr	r2, [r7, #4]
    2540:	f240 13b8 	movw	r3, #440	; 0x1b8
    2544:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2548:	429a      	cmp	r2, r3
    254a:	d000      	beq.n	254e <MSS_UART_set_filter_length+0x2a>
    254c:	be00      	bkpt	0x0000
    ASSERT(MSS_UART_INVALID_FILTER_LENGTH > length);
    254e:	78fb      	ldrb	r3, [r7, #3]
    2550:	2b07      	cmp	r3, #7
    2552:	d900      	bls.n	2556 <MSS_UART_set_filter_length+0x32>
    2554:	be00      	bkpt	0x0000
    
    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && 
    2556:	687a      	ldr	r2, [r7, #4]
    2558:	f240 13f8 	movw	r3, #504	; 0x1f8
    255c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2560:	429a      	cmp	r2, r3
    2562:	d006      	beq.n	2572 <MSS_UART_set_filter_length+0x4e>
    2564:	687a      	ldr	r2, [r7, #4]
    2566:	f240 13b8 	movw	r3, #440	; 0x1b8
    256a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    256e:	429a      	cmp	r2, r3
    2570:	d107      	bne.n	2582 <MSS_UART_set_filter_length+0x5e>
    2572:	78fb      	ldrb	r3, [r7, #3]
    2574:	2b07      	cmp	r3, #7
    2576:	d804      	bhi.n	2582 <MSS_UART_set_filter_length+0x5e>
       (MSS_UART_INVALID_FILTER_LENGTH > length))
    {
        /* Configure glitch filter length */
        this_uart->hw_reg->GFR = (uint8_t)length;
    2578:	687b      	ldr	r3, [r7, #4]
    257a:	681b      	ldr	r3, [r3, #0]
    257c:	78fa      	ldrb	r2, [r7, #3]
    257e:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
    }
}
    2582:	f107 070c 	add.w	r7, r7, #12
    2586:	46bd      	mov	sp, r7
    2588:	bc80      	pop	{r7}
    258a:	4770      	bx	lr

0000258c <MSS_UART_enable_afm>:
void
MSS_UART_enable_afm
(
     mss_uart_instance_t * this_uart
)
{
    258c:	b580      	push	{r7, lr}
    258e:	b082      	sub	sp, #8
    2590:	af00      	add	r7, sp, #0
    2592:	6078      	str	r0, [r7, #4]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    2594:	687a      	ldr	r2, [r7, #4]
    2596:	f240 13f8 	movw	r3, #504	; 0x1f8
    259a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    259e:	429a      	cmp	r2, r3
    25a0:	d007      	beq.n	25b2 <MSS_UART_enable_afm+0x26>
    25a2:	687a      	ldr	r2, [r7, #4]
    25a4:	f240 13b8 	movw	r3, #440	; 0x1b8
    25a8:	f2c2 0300 	movt	r3, #8192	; 0x2000
    25ac:	429a      	cmp	r2, r3
    25ae:	d000      	beq.n	25b2 <MSS_UART_enable_afm+0x26>
    25b0:	be00      	bkpt	0x0000

    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
    25b2:	687a      	ldr	r2, [r7, #4]
    25b4:	f240 13f8 	movw	r3, #504	; 0x1f8
    25b8:	f2c2 0300 	movt	r3, #8192	; 0x2000
    25bc:	429a      	cmp	r2, r3
    25be:	d006      	beq.n	25ce <MSS_UART_enable_afm+0x42>
    25c0:	687a      	ldr	r2, [r7, #4]
    25c2:	f240 13b8 	movw	r3, #440	; 0x1b8
    25c6:	f2c2 0300 	movt	r3, #8192	; 0x2000
    25ca:	429a      	cmp	r2, r3
    25cc:	d108      	bne.n	25e0 <MSS_UART_enable_afm+0x54>
    {
        /* Disable RX FIFO till address flag with correct address is received */
        set_bit_reg8(&this_uart->hw_reg->MM2,EAFM);
    25ce:	687b      	ldr	r3, [r7, #4]
    25d0:	681b      	ldr	r3, [r3, #0]
    25d2:	f103 0338 	add.w	r3, r3, #56	; 0x38
    25d6:	4618      	mov	r0, r3
    25d8:	f04f 0101 	mov.w	r1, #1
    25dc:	f7fe fdd2 	bl	1184 <set_bit_reg8>
    }
}
    25e0:	f107 0708 	add.w	r7, r7, #8
    25e4:	46bd      	mov	sp, r7
    25e6:	bd80      	pop	{r7, pc}

000025e8 <MSS_UART_disable_afm>:
void
MSS_UART_disable_afm
(
     mss_uart_instance_t * this_uart
)
{
    25e8:	b580      	push	{r7, lr}
    25ea:	b082      	sub	sp, #8
    25ec:	af00      	add	r7, sp, #0
    25ee:	6078      	str	r0, [r7, #4]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    25f0:	687a      	ldr	r2, [r7, #4]
    25f2:	f240 13f8 	movw	r3, #504	; 0x1f8
    25f6:	f2c2 0300 	movt	r3, #8192	; 0x2000
    25fa:	429a      	cmp	r2, r3
    25fc:	d007      	beq.n	260e <MSS_UART_disable_afm+0x26>
    25fe:	687a      	ldr	r2, [r7, #4]
    2600:	f240 13b8 	movw	r3, #440	; 0x1b8
    2604:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2608:	429a      	cmp	r2, r3
    260a:	d000      	beq.n	260e <MSS_UART_disable_afm+0x26>
    260c:	be00      	bkpt	0x0000

    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
    260e:	687a      	ldr	r2, [r7, #4]
    2610:	f240 13f8 	movw	r3, #504	; 0x1f8
    2614:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2618:	429a      	cmp	r2, r3
    261a:	d006      	beq.n	262a <MSS_UART_disable_afm+0x42>
    261c:	687a      	ldr	r2, [r7, #4]
    261e:	f240 13b8 	movw	r3, #440	; 0x1b8
    2622:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2626:	429a      	cmp	r2, r3
    2628:	d108      	bne.n	263c <MSS_UART_disable_afm+0x54>
    {
        /* Enable RX FIFO irrespective of address flag and
           correct address is received */
        clear_bit_reg8(&this_uart->hw_reg->MM2,EAFM);
    262a:	687b      	ldr	r3, [r7, #4]
    262c:	681b      	ldr	r3, [r3, #0]
    262e:	f103 0338 	add.w	r3, r3, #56	; 0x38
    2632:	4618      	mov	r0, r3
    2634:	f04f 0101 	mov.w	r1, #1
    2638:	f7fe fdc4 	bl	11c4 <clear_bit_reg8>
    }
}
    263c:	f107 0708 	add.w	r7, r7, #8
    2640:	46bd      	mov	sp, r7
    2642:	bd80      	pop	{r7, pc}

00002644 <MSS_UART_enable_afclear>:
void
MSS_UART_enable_afclear
(
     mss_uart_instance_t * this_uart
)
{
    2644:	b580      	push	{r7, lr}
    2646:	b082      	sub	sp, #8
    2648:	af00      	add	r7, sp, #0
    264a:	6078      	str	r0, [r7, #4]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    264c:	687a      	ldr	r2, [r7, #4]
    264e:	f240 13f8 	movw	r3, #504	; 0x1f8
    2652:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2656:	429a      	cmp	r2, r3
    2658:	d007      	beq.n	266a <MSS_UART_enable_afclear+0x26>
    265a:	687a      	ldr	r2, [r7, #4]
    265c:	f240 13b8 	movw	r3, #440	; 0x1b8
    2660:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2664:	429a      	cmp	r2, r3
    2666:	d000      	beq.n	266a <MSS_UART_enable_afclear+0x26>
    2668:	be00      	bkpt	0x0000

    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
    266a:	687a      	ldr	r2, [r7, #4]
    266c:	f240 13f8 	movw	r3, #504	; 0x1f8
    2670:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2674:	429a      	cmp	r2, r3
    2676:	d006      	beq.n	2686 <MSS_UART_enable_afclear+0x42>
    2678:	687a      	ldr	r2, [r7, #4]
    267a:	f240 13b8 	movw	r3, #440	; 0x1b8
    267e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2682:	429a      	cmp	r2, r3
    2684:	d108      	bne.n	2698 <MSS_UART_enable_afclear+0x54>
    {
        /* Enable address flag clearing */
        /* Disable RX FIFO till another address flag with 
           correct address is received */
        set_bit_reg8(&this_uart->hw_reg->MM2,EAFC);
    2686:	687b      	ldr	r3, [r7, #4]
    2688:	681b      	ldr	r3, [r3, #0]
    268a:	f103 0338 	add.w	r3, r3, #56	; 0x38
    268e:	4618      	mov	r0, r3
    2690:	f04f 0102 	mov.w	r1, #2
    2694:	f7fe fd76 	bl	1184 <set_bit_reg8>
    }
}
    2698:	f107 0708 	add.w	r7, r7, #8
    269c:	46bd      	mov	sp, r7
    269e:	bd80      	pop	{r7, pc}

000026a0 <MSS_UART_disable_afclear>:
void
MSS_UART_disable_afclear
(
     mss_uart_instance_t * this_uart
)
{
    26a0:	b580      	push	{r7, lr}
    26a2:	b082      	sub	sp, #8
    26a4:	af00      	add	r7, sp, #0
    26a6:	6078      	str	r0, [r7, #4]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    26a8:	687a      	ldr	r2, [r7, #4]
    26aa:	f240 13f8 	movw	r3, #504	; 0x1f8
    26ae:	f2c2 0300 	movt	r3, #8192	; 0x2000
    26b2:	429a      	cmp	r2, r3
    26b4:	d007      	beq.n	26c6 <MSS_UART_disable_afclear+0x26>
    26b6:	687a      	ldr	r2, [r7, #4]
    26b8:	f240 13b8 	movw	r3, #440	; 0x1b8
    26bc:	f2c2 0300 	movt	r3, #8192	; 0x2000
    26c0:	429a      	cmp	r2, r3
    26c2:	d000      	beq.n	26c6 <MSS_UART_disable_afclear+0x26>
    26c4:	be00      	bkpt	0x0000

    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
    26c6:	687a      	ldr	r2, [r7, #4]
    26c8:	f240 13f8 	movw	r3, #504	; 0x1f8
    26cc:	f2c2 0300 	movt	r3, #8192	; 0x2000
    26d0:	429a      	cmp	r2, r3
    26d2:	d006      	beq.n	26e2 <MSS_UART_disable_afclear+0x42>
    26d4:	687a      	ldr	r2, [r7, #4]
    26d6:	f240 13b8 	movw	r3, #440	; 0x1b8
    26da:	f2c2 0300 	movt	r3, #8192	; 0x2000
    26de:	429a      	cmp	r2, r3
    26e0:	d108      	bne.n	26f4 <MSS_UART_disable_afclear+0x54>
    {
        /* Disable address flag clearing */
        clear_bit_reg8(&this_uart->hw_reg->MM2,EAFC);
    26e2:	687b      	ldr	r3, [r7, #4]
    26e4:	681b      	ldr	r3, [r3, #0]
    26e6:	f103 0338 	add.w	r3, r3, #56	; 0x38
    26ea:	4618      	mov	r0, r3
    26ec:	f04f 0102 	mov.w	r1, #2
    26f0:	f7fe fd68 	bl	11c4 <clear_bit_reg8>
    }
}
    26f4:	f107 0708 	add.w	r7, r7, #8
    26f8:	46bd      	mov	sp, r7
    26fa:	bd80      	pop	{r7, pc}

000026fc <MSS_UART_enable_rx_timeout>:
MSS_UART_enable_rx_timeout
(
    mss_uart_instance_t * this_uart,
    uint8_t timeout
)
{
    26fc:	b580      	push	{r7, lr}
    26fe:	b082      	sub	sp, #8
    2700:	af00      	add	r7, sp, #0
    2702:	6078      	str	r0, [r7, #4]
    2704:	460b      	mov	r3, r1
    2706:	70fb      	strb	r3, [r7, #3]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    2708:	687a      	ldr	r2, [r7, #4]
    270a:	f240 13f8 	movw	r3, #504	; 0x1f8
    270e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2712:	429a      	cmp	r2, r3
    2714:	d007      	beq.n	2726 <MSS_UART_enable_rx_timeout+0x2a>
    2716:	687a      	ldr	r2, [r7, #4]
    2718:	f240 13b8 	movw	r3, #440	; 0x1b8
    271c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2720:	429a      	cmp	r2, r3
    2722:	d000      	beq.n	2726 <MSS_UART_enable_rx_timeout+0x2a>
    2724:	be00      	bkpt	0x0000

    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
    2726:	687a      	ldr	r2, [r7, #4]
    2728:	f240 13f8 	movw	r3, #504	; 0x1f8
    272c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2730:	429a      	cmp	r2, r3
    2732:	d006      	beq.n	2742 <MSS_UART_enable_rx_timeout+0x46>
    2734:	687a      	ldr	r2, [r7, #4]
    2736:	f240 13b8 	movw	r3, #440	; 0x1b8
    273a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    273e:	429a      	cmp	r2, r3
    2740:	d10d      	bne.n	275e <MSS_UART_enable_rx_timeout+0x62>
    {
        /* Load the receive timeout value */
        this_uart->hw_reg->RTO = timeout;
    2742:	687b      	ldr	r3, [r7, #4]
    2744:	681b      	ldr	r3, [r3, #0]
    2746:	78fa      	ldrb	r2, [r7, #3]
    2748:	f883 204c 	strb.w	r2, [r3, #76]	; 0x4c
        /*Enable receiver time-out */
        set_bit_reg8(&this_uart->hw_reg->MM0,ERTO);
    274c:	687b      	ldr	r3, [r7, #4]
    274e:	681b      	ldr	r3, [r3, #0]
    2750:	f103 0330 	add.w	r3, r3, #48	; 0x30
    2754:	4618      	mov	r0, r3
    2756:	f04f 0106 	mov.w	r1, #6
    275a:	f7fe fd13 	bl	1184 <set_bit_reg8>
    }
}
    275e:	f107 0708 	add.w	r7, r7, #8
    2762:	46bd      	mov	sp, r7
    2764:	bd80      	pop	{r7, pc}
    2766:	bf00      	nop

00002768 <MSS_UART_disable_rx_timeout>:
void 
MSS_UART_disable_rx_timeout
(
    mss_uart_instance_t * this_uart
)
{
    2768:	b580      	push	{r7, lr}
    276a:	b082      	sub	sp, #8
    276c:	af00      	add	r7, sp, #0
    276e:	6078      	str	r0, [r7, #4]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    2770:	687a      	ldr	r2, [r7, #4]
    2772:	f240 13f8 	movw	r3, #504	; 0x1f8
    2776:	f2c2 0300 	movt	r3, #8192	; 0x2000
    277a:	429a      	cmp	r2, r3
    277c:	d007      	beq.n	278e <MSS_UART_disable_rx_timeout+0x26>
    277e:	687a      	ldr	r2, [r7, #4]
    2780:	f240 13b8 	movw	r3, #440	; 0x1b8
    2784:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2788:	429a      	cmp	r2, r3
    278a:	d000      	beq.n	278e <MSS_UART_disable_rx_timeout+0x26>
    278c:	be00      	bkpt	0x0000

    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
    278e:	687a      	ldr	r2, [r7, #4]
    2790:	f240 13f8 	movw	r3, #504	; 0x1f8
    2794:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2798:	429a      	cmp	r2, r3
    279a:	d006      	beq.n	27aa <MSS_UART_disable_rx_timeout+0x42>
    279c:	687a      	ldr	r2, [r7, #4]
    279e:	f240 13b8 	movw	r3, #440	; 0x1b8
    27a2:	f2c2 0300 	movt	r3, #8192	; 0x2000
    27a6:	429a      	cmp	r2, r3
    27a8:	d108      	bne.n	27bc <MSS_UART_disable_rx_timeout+0x54>
    {
        /*Disable receiver time-out */
        clear_bit_reg8(&this_uart->hw_reg->MM0,ERTO);
    27aa:	687b      	ldr	r3, [r7, #4]
    27ac:	681b      	ldr	r3, [r3, #0]
    27ae:	f103 0330 	add.w	r3, r3, #48	; 0x30
    27b2:	4618      	mov	r0, r3
    27b4:	f04f 0106 	mov.w	r1, #6
    27b8:	f7fe fd04 	bl	11c4 <clear_bit_reg8>
    }
}
    27bc:	f107 0708 	add.w	r7, r7, #8
    27c0:	46bd      	mov	sp, r7
    27c2:	bd80      	pop	{r7, pc}

000027c4 <MSS_UART_enable_tx_time_guard>:
MSS_UART_enable_tx_time_guard
(
    mss_uart_instance_t * this_uart,
    uint8_t timeguard
)
{
    27c4:	b580      	push	{r7, lr}
    27c6:	b082      	sub	sp, #8
    27c8:	af00      	add	r7, sp, #0
    27ca:	6078      	str	r0, [r7, #4]
    27cc:	460b      	mov	r3, r1
    27ce:	70fb      	strb	r3, [r7, #3]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    27d0:	687a      	ldr	r2, [r7, #4]
    27d2:	f240 13f8 	movw	r3, #504	; 0x1f8
    27d6:	f2c2 0300 	movt	r3, #8192	; 0x2000
    27da:	429a      	cmp	r2, r3
    27dc:	d007      	beq.n	27ee <MSS_UART_enable_tx_time_guard+0x2a>
    27de:	687a      	ldr	r2, [r7, #4]
    27e0:	f240 13b8 	movw	r3, #440	; 0x1b8
    27e4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    27e8:	429a      	cmp	r2, r3
    27ea:	d000      	beq.n	27ee <MSS_UART_enable_tx_time_guard+0x2a>
    27ec:	be00      	bkpt	0x0000

    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
    27ee:	687a      	ldr	r2, [r7, #4]
    27f0:	f240 13f8 	movw	r3, #504	; 0x1f8
    27f4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    27f8:	429a      	cmp	r2, r3
    27fa:	d006      	beq.n	280a <MSS_UART_enable_tx_time_guard+0x46>
    27fc:	687a      	ldr	r2, [r7, #4]
    27fe:	f240 13b8 	movw	r3, #440	; 0x1b8
    2802:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2806:	429a      	cmp	r2, r3
    2808:	d10d      	bne.n	2826 <MSS_UART_enable_tx_time_guard+0x62>
    {
        /* Load the transmitter time guard value */
        this_uart->hw_reg->TTG = timeguard;
    280a:	687b      	ldr	r3, [r7, #4]
    280c:	681b      	ldr	r3, [r3, #0]
    280e:	78fa      	ldrb	r2, [r7, #3]
    2810:	f883 2048 	strb.w	r2, [r3, #72]	; 0x48
        /*Enable transmitter time guard */
        set_bit_reg8(&this_uart->hw_reg->MM0,ETTG);
    2814:	687b      	ldr	r3, [r7, #4]
    2816:	681b      	ldr	r3, [r3, #0]
    2818:	f103 0330 	add.w	r3, r3, #48	; 0x30
    281c:	4618      	mov	r0, r3
    281e:	f04f 0105 	mov.w	r1, #5
    2822:	f7fe fcaf 	bl	1184 <set_bit_reg8>
    }
}
    2826:	f107 0708 	add.w	r7, r7, #8
    282a:	46bd      	mov	sp, r7
    282c:	bd80      	pop	{r7, pc}
    282e:	bf00      	nop

00002830 <MSS_UART_disable_tx_time_guard>:
void 
MSS_UART_disable_tx_time_guard
(
    mss_uart_instance_t * this_uart
)
{
    2830:	b580      	push	{r7, lr}
    2832:	b082      	sub	sp, #8
    2834:	af00      	add	r7, sp, #0
    2836:	6078      	str	r0, [r7, #4]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    2838:	687a      	ldr	r2, [r7, #4]
    283a:	f240 13f8 	movw	r3, #504	; 0x1f8
    283e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2842:	429a      	cmp	r2, r3
    2844:	d007      	beq.n	2856 <MSS_UART_disable_tx_time_guard+0x26>
    2846:	687a      	ldr	r2, [r7, #4]
    2848:	f240 13b8 	movw	r3, #440	; 0x1b8
    284c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2850:	429a      	cmp	r2, r3
    2852:	d000      	beq.n	2856 <MSS_UART_disable_tx_time_guard+0x26>
    2854:	be00      	bkpt	0x0000

    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
    2856:	687a      	ldr	r2, [r7, #4]
    2858:	f240 13f8 	movw	r3, #504	; 0x1f8
    285c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2860:	429a      	cmp	r2, r3
    2862:	d006      	beq.n	2872 <MSS_UART_disable_tx_time_guard+0x42>
    2864:	687a      	ldr	r2, [r7, #4]
    2866:	f240 13b8 	movw	r3, #440	; 0x1b8
    286a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    286e:	429a      	cmp	r2, r3
    2870:	d108      	bne.n	2884 <MSS_UART_disable_tx_time_guard+0x54>
    {
        /*Disable transmitter time guard */
        clear_bit_reg8(&this_uart->hw_reg->MM0,ETTG);
    2872:	687b      	ldr	r3, [r7, #4]
    2874:	681b      	ldr	r3, [r3, #0]
    2876:	f103 0330 	add.w	r3, r3, #48	; 0x30
    287a:	4618      	mov	r0, r3
    287c:	f04f 0105 	mov.w	r1, #5
    2880:	f7fe fca0 	bl	11c4 <clear_bit_reg8>
    }
}
    2884:	f107 0708 	add.w	r7, r7, #8
    2888:	46bd      	mov	sp, r7
    288a:	bd80      	pop	{r7, pc}

0000288c <MSS_UART_set_address>:
MSS_UART_set_address
(
    mss_uart_instance_t * this_uart,
    uint8_t address
)
{
    288c:	b480      	push	{r7}
    288e:	b083      	sub	sp, #12
    2890:	af00      	add	r7, sp, #0
    2892:	6078      	str	r0, [r7, #4]
    2894:	460b      	mov	r3, r1
    2896:	70fb      	strb	r3, [r7, #3]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    2898:	687a      	ldr	r2, [r7, #4]
    289a:	f240 13f8 	movw	r3, #504	; 0x1f8
    289e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    28a2:	429a      	cmp	r2, r3
    28a4:	d007      	beq.n	28b6 <MSS_UART_set_address+0x2a>
    28a6:	687a      	ldr	r2, [r7, #4]
    28a8:	f240 13b8 	movw	r3, #440	; 0x1b8
    28ac:	f2c2 0300 	movt	r3, #8192	; 0x2000
    28b0:	429a      	cmp	r2, r3
    28b2:	d000      	beq.n	28b6 <MSS_UART_set_address+0x2a>
    28b4:	be00      	bkpt	0x0000

    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
    28b6:	687a      	ldr	r2, [r7, #4]
    28b8:	f240 13f8 	movw	r3, #504	; 0x1f8
    28bc:	f2c2 0300 	movt	r3, #8192	; 0x2000
    28c0:	429a      	cmp	r2, r3
    28c2:	d006      	beq.n	28d2 <MSS_UART_set_address+0x46>
    28c4:	687a      	ldr	r2, [r7, #4]
    28c6:	f240 13b8 	movw	r3, #440	; 0x1b8
    28ca:	f2c2 0300 	movt	r3, #8192	; 0x2000
    28ce:	429a      	cmp	r2, r3
    28d0:	d104      	bne.n	28dc <MSS_UART_set_address+0x50>
    {
        this_uart->hw_reg->ADR = address;
    28d2:	687b      	ldr	r3, [r7, #4]
    28d4:	681b      	ldr	r3, [r3, #0]
    28d6:	78fa      	ldrb	r2, [r7, #3]
    28d8:	f883 2050 	strb.w	r2, [r3, #80]	; 0x50
    }
}
    28dc:	f107 070c 	add.w	r7, r7, #12
    28e0:	46bd      	mov	sp, r7
    28e2:	bc80      	pop	{r7}
    28e4:	4770      	bx	lr
    28e6:	bf00      	nop

000028e8 <MSS_UART_set_ready_mode>:
MSS_UART_set_ready_mode
(
    mss_uart_instance_t * this_uart,
    mss_uart_ready_mode_t mode    
)
{
    28e8:	b580      	push	{r7, lr}
    28ea:	b082      	sub	sp, #8
    28ec:	af00      	add	r7, sp, #0
    28ee:	6078      	str	r0, [r7, #4]
    28f0:	460b      	mov	r3, r1
    28f2:	70fb      	strb	r3, [r7, #3]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    28f4:	687a      	ldr	r2, [r7, #4]
    28f6:	f240 13f8 	movw	r3, #504	; 0x1f8
    28fa:	f2c2 0300 	movt	r3, #8192	; 0x2000
    28fe:	429a      	cmp	r2, r3
    2900:	d007      	beq.n	2912 <MSS_UART_set_ready_mode+0x2a>
    2902:	687a      	ldr	r2, [r7, #4]
    2904:	f240 13b8 	movw	r3, #440	; 0x1b8
    2908:	f2c2 0300 	movt	r3, #8192	; 0x2000
    290c:	429a      	cmp	r2, r3
    290e:	d000      	beq.n	2912 <MSS_UART_set_ready_mode+0x2a>
    2910:	be00      	bkpt	0x0000
    ASSERT(MSS_UART_INVALID_READY_MODE > mode);
    2912:	78fb      	ldrb	r3, [r7, #3]
    2914:	2b01      	cmp	r3, #1
    2916:	d900      	bls.n	291a <MSS_UART_set_ready_mode+0x32>
    2918:	be00      	bkpt	0x0000

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
    291a:	687a      	ldr	r2, [r7, #4]
    291c:	f240 13f8 	movw	r3, #504	; 0x1f8
    2920:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2924:	429a      	cmp	r2, r3
    2926:	d006      	beq.n	2936 <MSS_UART_set_ready_mode+0x4e>
    2928:	687a      	ldr	r2, [r7, #4]
    292a:	f240 13b8 	movw	r3, #440	; 0x1b8
    292e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2932:	429a      	cmp	r2, r3
    2934:	d118      	bne.n	2968 <MSS_UART_set_ready_mode+0x80>
    2936:	78fb      	ldrb	r3, [r7, #3]
    2938:	2b01      	cmp	r3, #1
    293a:	d815      	bhi.n	2968 <MSS_UART_set_ready_mode+0x80>
       (MSS_UART_INVALID_READY_MODE > mode ) )
    {
        /* Configure mode 0 or mode 1 for TXRDY and RXRDY */
        ((MSS_UART_READY_MODE0 == mode) ? clear_bit_reg8(&this_uart->hw_reg->FCR,RDYMODE) :
    293c:	78fb      	ldrb	r3, [r7, #3]
    293e:	2b00      	cmp	r3, #0
    2940:	d109      	bne.n	2956 <MSS_UART_set_ready_mode+0x6e>
    2942:	687b      	ldr	r3, [r7, #4]
    2944:	681b      	ldr	r3, [r3, #0]
    2946:	f103 0308 	add.w	r3, r3, #8
    294a:	4618      	mov	r0, r3
    294c:	f04f 0103 	mov.w	r1, #3
    2950:	f7fe fc38 	bl	11c4 <clear_bit_reg8>
    2954:	e008      	b.n	2968 <MSS_UART_set_ready_mode+0x80>
                                 set_bit_reg8(&this_uart->hw_reg->FCR,RDYMODE) );    
    2956:	687b      	ldr	r3, [r7, #4]
    2958:	681b      	ldr	r3, [r3, #0]
    295a:	f103 0308 	add.w	r3, r3, #8
    295e:	4618      	mov	r0, r3
    2960:	f04f 0103 	mov.w	r1, #3
    2964:	f7fe fc0e 	bl	1184 <set_bit_reg8>
    }
}
    2968:	f107 0708 	add.w	r7, r7, #8
    296c:	46bd      	mov	sp, r7
    296e:	bd80      	pop	{r7, pc}

00002970 <config_baud_divisors>:
config_baud_divisors
(
    mss_uart_instance_t * this_uart,
    uint32_t baudrate    
)
{
    2970:	b580      	push	{r7, lr}
    2972:	b088      	sub	sp, #32
    2974:	af00      	add	r7, sp, #0
    2976:	6078      	str	r0, [r7, #4]
    2978:	6039      	str	r1, [r7, #0]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    297a:	687a      	ldr	r2, [r7, #4]
    297c:	f240 13f8 	movw	r3, #504	; 0x1f8
    2980:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2984:	429a      	cmp	r2, r3
    2986:	d007      	beq.n	2998 <config_baud_divisors+0x28>
    2988:	687a      	ldr	r2, [r7, #4]
    298a:	f240 13b8 	movw	r3, #440	; 0x1b8
    298e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2992:	429a      	cmp	r2, r3
    2994:	d000      	beq.n	2998 <config_baud_divisors+0x28>
    2996:	be00      	bkpt	0x0000
    
    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
    2998:	687a      	ldr	r2, [r7, #4]
    299a:	f240 13f8 	movw	r3, #504	; 0x1f8
    299e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    29a2:	429a      	cmp	r2, r3
    29a4:	d007      	beq.n	29b6 <config_baud_divisors+0x46>
    29a6:	687a      	ldr	r2, [r7, #4]
    29a8:	f240 13b8 	movw	r3, #440	; 0x1b8
    29ac:	f2c2 0300 	movt	r3, #8192	; 0x2000
    29b0:	429a      	cmp	r2, r3
    29b2:	f040 80a4 	bne.w	2afe <config_baud_divisors+0x18e>
        uint32_t baud_value_by_64;
        uint32_t baud_value_by_128;
        uint32_t fractional_baud_value;
        uint32_t pclk_freq;

        this_uart->baudrate = baudrate;
    29b6:	687b      	ldr	r3, [r7, #4]
    29b8:	683a      	ldr	r2, [r7, #0]
    29ba:	609a      	str	r2, [r3, #8]

        /* Force the value of the CMSIS global variables holding the various system
          * clock frequencies to be updated. */
        SystemCoreClockUpdate();
    29bc:	f7fd fdce 	bl	55c <SystemCoreClockUpdate>
        if(this_uart == &g_mss_uart0)
    29c0:	687a      	ldr	r2, [r7, #4]
    29c2:	f240 13f8 	movw	r3, #504	; 0x1f8
    29c6:	f2c2 0300 	movt	r3, #8192	; 0x2000
    29ca:	429a      	cmp	r2, r3
    29cc:	d106      	bne.n	29dc <config_baud_divisors+0x6c>
        {
            pclk_freq = g_FrequencyPCLK0;
    29ce:	f240 0314 	movw	r3, #20
    29d2:	f2c2 0300 	movt	r3, #8192	; 0x2000
    29d6:	681b      	ldr	r3, [r3, #0]
    29d8:	61fb      	str	r3, [r7, #28]
    29da:	e005      	b.n	29e8 <config_baud_divisors+0x78>
        }
        else
        {
            pclk_freq = g_FrequencyPCLK1;
    29dc:	f240 0318 	movw	r3, #24
    29e0:	f2c2 0300 	movt	r3, #8192	; 0x2000
    29e4:	681b      	ldr	r3, [r3, #0]
    29e6:	61fb      	str	r3, [r7, #28]
        /*
         * Compute baud value based on requested baud rate and PCLK frequency.
         * The baud value is computed using the following equation:
         *      baud_value = PCLK_Frequency / (baud_rate * 16)
         */
        baud_value_by_128 = (8u * pclk_freq) / baudrate;
    29e8:	69fb      	ldr	r3, [r7, #28]
    29ea:	ea4f 02c3 	mov.w	r2, r3, lsl #3
    29ee:	683b      	ldr	r3, [r7, #0]
    29f0:	fbb2 f3f3 	udiv	r3, r2, r3
    29f4:	617b      	str	r3, [r7, #20]
        baud_value_by_64 = baud_value_by_128 / 2u;
    29f6:	697b      	ldr	r3, [r7, #20]
    29f8:	ea4f 0353 	mov.w	r3, r3, lsr #1
    29fc:	613b      	str	r3, [r7, #16]
        baud_value = baud_value_by_64 / 64u;
    29fe:	693b      	ldr	r3, [r7, #16]
    2a00:	ea4f 1393 	mov.w	r3, r3, lsr #6
    2a04:	60fb      	str	r3, [r7, #12]
        fractional_baud_value = baud_value_by_64 - (baud_value * 64u);
    2a06:	68fb      	ldr	r3, [r7, #12]
    2a08:	ea4f 1383 	mov.w	r3, r3, lsl #6
    2a0c:	693a      	ldr	r2, [r7, #16]
    2a0e:	ebc3 0302 	rsb	r3, r3, r2
    2a12:	61bb      	str	r3, [r7, #24]
        fractional_baud_value += (baud_value_by_128 - (baud_value * 128u)) - (fractional_baud_value * 2u);
    2a14:	68fb      	ldr	r3, [r7, #12]
    2a16:	ea4f 13c3 	mov.w	r3, r3, lsl #7
    2a1a:	697a      	ldr	r2, [r7, #20]
    2a1c:	ebc3 0202 	rsb	r2, r3, r2
    2a20:	69bb      	ldr	r3, [r7, #24]
    2a22:	ea4f 0343 	mov.w	r3, r3, lsl #1
    2a26:	ebc3 0302 	rsb	r3, r3, r2
    2a2a:	69ba      	ldr	r2, [r7, #24]
    2a2c:	4413      	add	r3, r2
    2a2e:	61bb      	str	r3, [r7, #24]
        
        /* Assert if integer baud value fits in 16-bit. */
        ASSERT(baud_value <= UINT16_MAX);
    2a30:	68fa      	ldr	r2, [r7, #12]
    2a32:	f64f 73ff 	movw	r3, #65535	; 0xffff
    2a36:	429a      	cmp	r2, r3
    2a38:	d900      	bls.n	2a3c <config_baud_divisors+0xcc>
    2a3a:	be00      	bkpt	0x0000
    
        if(baud_value <= (uint32_t)UINT16_MAX)
    2a3c:	68fa      	ldr	r2, [r7, #12]
    2a3e:	f64f 73ff 	movw	r3, #65535	; 0xffff
    2a42:	429a      	cmp	r2, r3
    2a44:	d85b      	bhi.n	2afe <config_baud_divisors+0x18e>
        {
            if(baud_value > 1u)
    2a46:	68fb      	ldr	r3, [r7, #12]
    2a48:	2b01      	cmp	r3, #1
    2a4a:	d931      	bls.n	2ab0 <config_baud_divisors+0x140>
            {
                /* 
                 * Use Frational baud rate divisors
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
    2a4c:	687b      	ldr	r3, [r7, #4]
    2a4e:	681b      	ldr	r3, [r3, #0]
    2a50:	f103 030c 	add.w	r3, r3, #12
    2a54:	4618      	mov	r0, r3
    2a56:	f04f 0107 	mov.w	r1, #7
    2a5a:	f7fe fb93 	bl	1184 <set_bit_reg8>
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8);
    2a5e:	687b      	ldr	r3, [r7, #4]
    2a60:	681b      	ldr	r3, [r3, #0]
    2a62:	68fa      	ldr	r2, [r7, #12]
    2a64:	ea4f 2212 	mov.w	r2, r2, lsr #8
    2a68:	b2d2      	uxtb	r2, r2
    2a6a:	711a      	strb	r2, [r3, #4]
                /* lsb of baud value */
                this_uart->hw_reg->DLR = (uint8_t)baud_value;
    2a6c:	687b      	ldr	r3, [r7, #4]
    2a6e:	681b      	ldr	r3, [r3, #0]
    2a70:	68fa      	ldr	r2, [r7, #12]
    2a72:	b2d2      	uxtb	r2, r2
    2a74:	701a      	strb	r2, [r3, #0]
            
                /* reset divisor latch */
                clear_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
    2a76:	687b      	ldr	r3, [r7, #4]
    2a78:	681b      	ldr	r3, [r3, #0]
    2a7a:	f103 030c 	add.w	r3, r3, #12
    2a7e:	4618      	mov	r0, r3
    2a80:	f04f 0107 	mov.w	r1, #7
    2a84:	f7fe fb9e 	bl	11c4 <clear_bit_reg8>
        
                /* Enable Fractional baud rate */
                set_bit_reg8(&this_uart->hw_reg->MM0,EFBR);
    2a88:	687b      	ldr	r3, [r7, #4]
    2a8a:	681b      	ldr	r3, [r3, #0]
    2a8c:	f103 0330 	add.w	r3, r3, #48	; 0x30
    2a90:	4618      	mov	r0, r3
    2a92:	f04f 0107 	mov.w	r1, #7
    2a96:	f7fe fb75 	bl	1184 <set_bit_reg8>
        
                /* Load the fractional baud rate register */
                ASSERT(fractional_baud_value <= (uint32_t)UINT8_MAX);
    2a9a:	69bb      	ldr	r3, [r7, #24]
    2a9c:	2bff      	cmp	r3, #255	; 0xff
    2a9e:	d900      	bls.n	2aa2 <config_baud_divisors+0x132>
    2aa0:	be00      	bkpt	0x0000
                this_uart->hw_reg->DFR = (uint8_t)fractional_baud_value;
    2aa2:	687b      	ldr	r3, [r7, #4]
    2aa4:	681b      	ldr	r3, [r3, #0]
    2aa6:	69ba      	ldr	r2, [r7, #24]
    2aa8:	b2d2      	uxtb	r2, r2
    2aaa:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
    2aae:	e026      	b.n	2afe <config_baud_divisors+0x18e>
            {
                /*
                 * Do NOT use Frational baud rate divisors.
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
    2ab0:	687b      	ldr	r3, [r7, #4]
    2ab2:	681b      	ldr	r3, [r3, #0]
    2ab4:	f103 030c 	add.w	r3, r3, #12
    2ab8:	4618      	mov	r0, r3
    2aba:	f04f 0107 	mov.w	r1, #7
    2abe:	f7fe fb61 	bl	1184 <set_bit_reg8>
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8u);
    2ac2:	687b      	ldr	r3, [r7, #4]
    2ac4:	681b      	ldr	r3, [r3, #0]
    2ac6:	68fa      	ldr	r2, [r7, #12]
    2ac8:	ea4f 2212 	mov.w	r2, r2, lsr #8
    2acc:	b2d2      	uxtb	r2, r2
    2ace:	711a      	strb	r2, [r3, #4]
                /* lsb of baud value */
                this_uart->hw_reg->DLR = (uint8_t)baud_value;
    2ad0:	687b      	ldr	r3, [r7, #4]
    2ad2:	681b      	ldr	r3, [r3, #0]
    2ad4:	68fa      	ldr	r2, [r7, #12]
    2ad6:	b2d2      	uxtb	r2, r2
    2ad8:	701a      	strb	r2, [r3, #0]
            
                /* reset divisor latch */
                clear_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
    2ada:	687b      	ldr	r3, [r7, #4]
    2adc:	681b      	ldr	r3, [r3, #0]
    2ade:	f103 030c 	add.w	r3, r3, #12
    2ae2:	4618      	mov	r0, r3
    2ae4:	f04f 0107 	mov.w	r1, #7
    2ae8:	f7fe fb6c 	bl	11c4 <clear_bit_reg8>
                
                /* Disable Fractional baud rate */
                clear_bit_reg8(&this_uart->hw_reg->MM0,EFBR);
    2aec:	687b      	ldr	r3, [r7, #4]
    2aee:	681b      	ldr	r3, [r3, #0]
    2af0:	f103 0330 	add.w	r3, r3, #48	; 0x30
    2af4:	4618      	mov	r0, r3
    2af6:	f04f 0107 	mov.w	r1, #7
    2afa:	f7fe fb63 	bl	11c4 <clear_bit_reg8>
            }
        }
    }
}
    2afe:	f107 0720 	add.w	r7, r7, #32
    2b02:	46bd      	mov	sp, r7
    2b04:	bd80      	pop	{r7, pc}
    2b06:	bf00      	nop

00002b08 <MSS_UART_set_usart_mode>:
MSS_UART_set_usart_mode
(
    mss_uart_instance_t * this_uart,
    mss_uart_usart_mode_t mode
)
{
    2b08:	b480      	push	{r7}
    2b0a:	b083      	sub	sp, #12
    2b0c:	af00      	add	r7, sp, #0
    2b0e:	6078      	str	r0, [r7, #4]
    2b10:	460b      	mov	r3, r1
    2b12:	70fb      	strb	r3, [r7, #3]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    2b14:	687a      	ldr	r2, [r7, #4]
    2b16:	f240 13f8 	movw	r3, #504	; 0x1f8
    2b1a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2b1e:	429a      	cmp	r2, r3
    2b20:	d007      	beq.n	2b32 <MSS_UART_set_usart_mode+0x2a>
    2b22:	687a      	ldr	r2, [r7, #4]
    2b24:	f240 13b8 	movw	r3, #440	; 0x1b8
    2b28:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2b2c:	429a      	cmp	r2, r3
    2b2e:	d000      	beq.n	2b32 <MSS_UART_set_usart_mode+0x2a>
    2b30:	be00      	bkpt	0x0000
    ASSERT(MSS_UART_INVALID_SYNC_MODE > mode);
    2b32:	78fb      	ldrb	r3, [r7, #3]
    2b34:	2b04      	cmp	r3, #4
    2b36:	d900      	bls.n	2b3a <MSS_UART_set_usart_mode+0x32>
    2b38:	be00      	bkpt	0x0000

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
    2b3a:	687a      	ldr	r2, [r7, #4]
    2b3c:	f240 13f8 	movw	r3, #504	; 0x1f8
    2b40:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2b44:	429a      	cmp	r2, r3
    2b46:	d006      	beq.n	2b56 <MSS_UART_set_usart_mode+0x4e>
    2b48:	687a      	ldr	r2, [r7, #4]
    2b4a:	f240 13b8 	movw	r3, #440	; 0x1b8
    2b4e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2b52:	429a      	cmp	r2, r3
    2b54:	d11a      	bne.n	2b8c <MSS_UART_set_usart_mode+0x84>
    2b56:	78fb      	ldrb	r3, [r7, #3]
    2b58:	2b04      	cmp	r3, #4
    2b5a:	d817      	bhi.n	2b8c <MSS_UART_set_usart_mode+0x84>
       (MSS_UART_INVALID_SYNC_MODE > mode))
    {
        /* Nothing to do for the baudrate: operates at PCLK / 2 + glitch filter length */
        /* Clear the ESYN bits 2:0 */
        this_uart->hw_reg->MM0 &= ~SYNC_ASYNC_MODE_MASK;
    2b5c:	687b      	ldr	r3, [r7, #4]
    2b5e:	681a      	ldr	r2, [r3, #0]
    2b60:	687b      	ldr	r3, [r7, #4]
    2b62:	681b      	ldr	r3, [r3, #0]
    2b64:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
    2b68:	b2db      	uxtb	r3, r3
    2b6a:	f003 03f8 	and.w	r3, r3, #248	; 0xf8
    2b6e:	f882 3030 	strb.w	r3, [r2, #48]	; 0x30
        this_uart->hw_reg->MM0 |= (uint8_t)mode;
    2b72:	687b      	ldr	r3, [r7, #4]
    2b74:	681b      	ldr	r3, [r3, #0]
    2b76:	687a      	ldr	r2, [r7, #4]
    2b78:	6812      	ldr	r2, [r2, #0]
    2b7a:	f892 2030 	ldrb.w	r2, [r2, #48]	; 0x30
    2b7e:	b2d1      	uxtb	r1, r2
    2b80:	78fa      	ldrb	r2, [r7, #3]
    2b82:	ea41 0202 	orr.w	r2, r1, r2
    2b86:	b2d2      	uxtb	r2, r2
    2b88:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
    }
}
    2b8c:	f107 070c 	add.w	r7, r7, #12
    2b90:	46bd      	mov	sp, r7
    2b92:	bc80      	pop	{r7}
    2b94:	4770      	bx	lr
    2b96:	bf00      	nop

00002b98 <global_init>:
(
    mss_uart_instance_t * this_uart,
    uint32_t baud_rate,
    uint8_t line_config
)
{
    2b98:	b580      	push	{r7, lr}
    2b9a:	b084      	sub	sp, #16
    2b9c:	af00      	add	r7, sp, #0
    2b9e:	60f8      	str	r0, [r7, #12]
    2ba0:	60b9      	str	r1, [r7, #8]
    2ba2:	4613      	mov	r3, r2
    2ba4:	71fb      	strb	r3, [r7, #7]
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    2ba6:	68fa      	ldr	r2, [r7, #12]
    2ba8:	f240 13f8 	movw	r3, #504	; 0x1f8
    2bac:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2bb0:	429a      	cmp	r2, r3
    2bb2:	d007      	beq.n	2bc4 <global_init+0x2c>
    2bb4:	68fa      	ldr	r2, [r7, #12]
    2bb6:	f240 13b8 	movw	r3, #440	; 0x1b8
    2bba:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2bbe:	429a      	cmp	r2, r3
    2bc0:	d000      	beq.n	2bc4 <global_init+0x2c>
    2bc2:	be00      	bkpt	0x0000

    if(this_uart == &g_mss_uart0)
    2bc4:	68fa      	ldr	r2, [r7, #12]
    2bc6:	f240 13f8 	movw	r3, #504	; 0x1f8
    2bca:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2bce:	429a      	cmp	r2, r3
    2bd0:	d124      	bne.n	2c1c <global_init+0x84>
    {
        this_uart->hw_reg = UART0;
    2bd2:	68fb      	ldr	r3, [r7, #12]
    2bd4:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
    2bd8:	601a      	str	r2, [r3, #0]
        this_uart->irqn = UART0_IRQn;
    2bda:	68fb      	ldr	r3, [r7, #12]
    2bdc:	f04f 020a 	mov.w	r2, #10
    2be0:	711a      	strb	r2, [r3, #4]
        /* reset UART0 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART0_SOFTRESET_MASK;
    2be2:	f248 0300 	movw	r3, #32768	; 0x8000
    2be6:	f2c4 0303 	movt	r3, #16387	; 0x4003
    2bea:	f248 0200 	movw	r2, #32768	; 0x8000
    2bee:	f2c4 0203 	movt	r2, #16387	; 0x4003
    2bf2:	6c92      	ldr	r2, [r2, #72]	; 0x48
    2bf4:	f042 0280 	orr.w	r2, r2, #128	; 0x80
    2bf8:	649a      	str	r2, [r3, #72]	; 0x48
        /* Clear any previously pended UART0 interrupt */
        NVIC_ClearPendingIRQ(UART0_IRQn);
    2bfa:	f04f 000a 	mov.w	r0, #10
    2bfe:	f7fe faa3 	bl	1148 <NVIC_ClearPendingIRQ>
        /* Take UART0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
    2c02:	f248 0300 	movw	r3, #32768	; 0x8000
    2c06:	f2c4 0303 	movt	r3, #16387	; 0x4003
    2c0a:	f248 0200 	movw	r2, #32768	; 0x8000
    2c0e:	f2c4 0203 	movt	r2, #16387	; 0x4003
    2c12:	6c92      	ldr	r2, [r2, #72]	; 0x48
    2c14:	f022 0280 	bic.w	r2, r2, #128	; 0x80
    2c18:	649a      	str	r2, [r3, #72]	; 0x48
    2c1a:	e025      	b.n	2c68 <global_init+0xd0>
    }
    else
    {
        this_uart->hw_reg = UART1;
    2c1c:	68fa      	ldr	r2, [r7, #12]
    2c1e:	f240 0300 	movw	r3, #0
    2c22:	f2c4 0301 	movt	r3, #16385	; 0x4001
    2c26:	6013      	str	r3, [r2, #0]
        this_uart->irqn = UART1_IRQn;
    2c28:	68fb      	ldr	r3, [r7, #12]
    2c2a:	f04f 020b 	mov.w	r2, #11
    2c2e:	711a      	strb	r2, [r3, #4]
        /* Reset UART1 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART1_SOFTRESET_MASK;
    2c30:	f248 0300 	movw	r3, #32768	; 0x8000
    2c34:	f2c4 0303 	movt	r3, #16387	; 0x4003
    2c38:	f248 0200 	movw	r2, #32768	; 0x8000
    2c3c:	f2c4 0203 	movt	r2, #16387	; 0x4003
    2c40:	6c92      	ldr	r2, [r2, #72]	; 0x48
    2c42:	f442 7280 	orr.w	r2, r2, #256	; 0x100
    2c46:	649a      	str	r2, [r3, #72]	; 0x48
        /* Clear any previously pended UART1 interrupt */
        NVIC_ClearPendingIRQ(UART1_IRQn);
    2c48:	f04f 000b 	mov.w	r0, #11
    2c4c:	f7fe fa7c 	bl	1148 <NVIC_ClearPendingIRQ>
        /* Take UART1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART1_SOFTRESET_MASK;
    2c50:	f248 0300 	movw	r3, #32768	; 0x8000
    2c54:	f2c4 0303 	movt	r3, #16387	; 0x4003
    2c58:	f248 0200 	movw	r2, #32768	; 0x8000
    2c5c:	f2c4 0203 	movt	r2, #16387	; 0x4003
    2c60:	6c92      	ldr	r2, [r2, #72]	; 0x48
    2c62:	f422 7280 	bic.w	r2, r2, #256	; 0x100
    2c66:	649a      	str	r2, [r3, #72]	; 0x48
    }

    /* disable interrupts */
    this_uart->hw_reg->IER = 0u;
    2c68:	68fb      	ldr	r3, [r7, #12]
    2c6a:	681b      	ldr	r3, [r3, #0]
    2c6c:	f04f 0200 	mov.w	r2, #0
    2c70:	711a      	strb	r2, [r3, #4]

    /* FIFO configuration */
    this_uart->hw_reg->FCR = (uint8_t)MSS_UART_FIFO_SINGLE_BYTE;
    2c72:	68fb      	ldr	r3, [r7, #12]
    2c74:	681b      	ldr	r3, [r3, #0]
    2c76:	f04f 0200 	mov.w	r2, #0
    2c7a:	721a      	strb	r2, [r3, #8]
    /* clear receiver FIFO */
    set_bit_reg8(&this_uart->hw_reg->FCR,CLEAR_RX_FIFO);
    2c7c:	68fb      	ldr	r3, [r7, #12]
    2c7e:	681b      	ldr	r3, [r3, #0]
    2c80:	f103 0308 	add.w	r3, r3, #8
    2c84:	4618      	mov	r0, r3
    2c86:	f04f 0101 	mov.w	r1, #1
    2c8a:	f7fe fa7b 	bl	1184 <set_bit_reg8>
    /* clear transmitter FIFO */
    set_bit_reg8(&this_uart->hw_reg->FCR,CLEAR_TX_FIFO);
    2c8e:	68fb      	ldr	r3, [r7, #12]
    2c90:	681b      	ldr	r3, [r3, #0]
    2c92:	f103 0308 	add.w	r3, r3, #8
    2c96:	4618      	mov	r0, r3
    2c98:	f04f 0102 	mov.w	r1, #2
    2c9c:	f7fe fa72 	bl	1184 <set_bit_reg8>

    /* set default READY mode : Mode 0*/
    /* enable RXRDYN and TXRDYN pins. The earlier FCR write to set the TX FIFO
     * trigger level inadvertently disabled the FCR_RXRDY_TXRDYN_EN bit. */
    set_bit_reg8(&this_uart->hw_reg->FCR,RXRDY_TXRDYN_EN);
    2ca0:	68fb      	ldr	r3, [r7, #12]
    2ca2:	681b      	ldr	r3, [r3, #0]
    2ca4:	f103 0308 	add.w	r3, r3, #8
    2ca8:	4618      	mov	r0, r3
    2caa:	f04f 0100 	mov.w	r1, #0
    2cae:	f7fe fa69 	bl	1184 <set_bit_reg8>

    /* disable loopback : local * remote */
    clear_bit_reg8(&this_uart->hw_reg->MCR,LOOP);
    2cb2:	68fb      	ldr	r3, [r7, #12]
    2cb4:	681b      	ldr	r3, [r3, #0]
    2cb6:	f103 0310 	add.w	r3, r3, #16
    2cba:	4618      	mov	r0, r3
    2cbc:	f04f 0104 	mov.w	r1, #4
    2cc0:	f7fe fa80 	bl	11c4 <clear_bit_reg8>
    clear_bit_reg8(&this_uart->hw_reg->MCR,RLOOP);
    2cc4:	68fb      	ldr	r3, [r7, #12]
    2cc6:	681b      	ldr	r3, [r3, #0]
    2cc8:	f103 0310 	add.w	r3, r3, #16
    2ccc:	4618      	mov	r0, r3
    2cce:	f04f 0105 	mov.w	r1, #5
    2cd2:	f7fe fa77 	bl	11c4 <clear_bit_reg8>

    /* set default TX endian */
    clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_TX);
    2cd6:	68fb      	ldr	r3, [r7, #12]
    2cd8:	681b      	ldr	r3, [r3, #0]
    2cda:	f103 0334 	add.w	r3, r3, #52	; 0x34
    2cde:	4618      	mov	r0, r3
    2ce0:	f04f 0101 	mov.w	r1, #1
    2ce4:	f7fe fa6e 	bl	11c4 <clear_bit_reg8>
    /* set default RX endian */
    clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_RX);
    2ce8:	68fb      	ldr	r3, [r7, #12]
    2cea:	681b      	ldr	r3, [r3, #0]
    2cec:	f103 0334 	add.w	r3, r3, #52	; 0x34
    2cf0:	4618      	mov	r0, r3
    2cf2:	f04f 0100 	mov.w	r1, #0
    2cf6:	f7fe fa65 	bl	11c4 <clear_bit_reg8>

    /* default AFM : disabled */
    clear_bit_reg8(&this_uart->hw_reg->MM2,EAFM);
    2cfa:	68fb      	ldr	r3, [r7, #12]
    2cfc:	681b      	ldr	r3, [r3, #0]
    2cfe:	f103 0338 	add.w	r3, r3, #56	; 0x38
    2d02:	4618      	mov	r0, r3
    2d04:	f04f 0101 	mov.w	r1, #1
    2d08:	f7fe fa5c 	bl	11c4 <clear_bit_reg8>

    /* disable TX time gaurd */
    clear_bit_reg8(&this_uart->hw_reg->MM0,ETTG); 
    2d0c:	68fb      	ldr	r3, [r7, #12]
    2d0e:	681b      	ldr	r3, [r3, #0]
    2d10:	f103 0330 	add.w	r3, r3, #48	; 0x30
    2d14:	4618      	mov	r0, r3
    2d16:	f04f 0105 	mov.w	r1, #5
    2d1a:	f7fe fa53 	bl	11c4 <clear_bit_reg8>

    /* set default RX timeout */
    clear_bit_reg8(&this_uart->hw_reg->MM0,ERTO); 
    2d1e:	68fb      	ldr	r3, [r7, #12]
    2d20:	681b      	ldr	r3, [r3, #0]
    2d22:	f103 0330 	add.w	r3, r3, #48	; 0x30
    2d26:	4618      	mov	r0, r3
    2d28:	f04f 0106 	mov.w	r1, #6
    2d2c:	f7fe fa4a 	bl	11c4 <clear_bit_reg8>

    /* disable fractional baud-rate */
    clear_bit_reg8(&this_uart->hw_reg->MM0,EFBR); 
    2d30:	68fb      	ldr	r3, [r7, #12]
    2d32:	681b      	ldr	r3, [r3, #0]
    2d34:	f103 0330 	add.w	r3, r3, #48	; 0x30
    2d38:	4618      	mov	r0, r3
    2d3a:	f04f 0107 	mov.w	r1, #7
    2d3e:	f7fe fa41 	bl	11c4 <clear_bit_reg8>

    /* disable single wire mode */
    clear_bit_reg8(&this_uart->hw_reg->MM2,ESWM);
    2d42:	68fb      	ldr	r3, [r7, #12]
    2d44:	681b      	ldr	r3, [r3, #0]
    2d46:	f103 0338 	add.w	r3, r3, #56	; 0x38
    2d4a:	4618      	mov	r0, r3
    2d4c:	f04f 0103 	mov.w	r1, #3
    2d50:	f7fe fa38 	bl	11c4 <clear_bit_reg8>

    /* set filter to minimum value */
    this_uart->hw_reg->GFR = 0u;
    2d54:	68fb      	ldr	r3, [r7, #12]
    2d56:	681b      	ldr	r3, [r3, #0]
    2d58:	f04f 0200 	mov.w	r2, #0
    2d5c:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
    /* set default TX time gaurd */
    this_uart->hw_reg->TTG = 0u;
    2d60:	68fb      	ldr	r3, [r7, #12]
    2d62:	681b      	ldr	r3, [r3, #0]
    2d64:	f04f 0200 	mov.w	r2, #0
    2d68:	f883 2048 	strb.w	r2, [r3, #72]	; 0x48
    /* set default RX timeout */
    this_uart->hw_reg->RTO = 0u;
    2d6c:	68fb      	ldr	r3, [r7, #12]
    2d6e:	681b      	ldr	r3, [r3, #0]
    2d70:	f04f 0200 	mov.w	r2, #0
    2d74:	f883 204c 	strb.w	r2, [r3, #76]	; 0x4c
    
    /* 
     * Configure baud rate divisors. This uses the frational baud rate divisor
     * where possible to provide the most accurate baud rat possible.
     */
    config_baud_divisors(this_uart, baud_rate);
    2d78:	68f8      	ldr	r0, [r7, #12]
    2d7a:	68b9      	ldr	r1, [r7, #8]
    2d7c:	f7ff fdf8 	bl	2970 <config_baud_divisors>

    /* set the line control register (bit length, stop bits, parity) */
    this_uart->hw_reg->LCR = line_config;
    2d80:	68fb      	ldr	r3, [r7, #12]
    2d82:	681b      	ldr	r3, [r3, #0]
    2d84:	79fa      	ldrb	r2, [r7, #7]
    2d86:	731a      	strb	r2, [r3, #12]

    /* Instance setup */
    this_uart->baudrate = baud_rate;
    2d88:	68fb      	ldr	r3, [r7, #12]
    2d8a:	68ba      	ldr	r2, [r7, #8]
    2d8c:	609a      	str	r2, [r3, #8]
    this_uart->lineconfig = line_config;
    2d8e:	68fb      	ldr	r3, [r7, #12]
    2d90:	79fa      	ldrb	r2, [r7, #7]
    2d92:	731a      	strb	r2, [r3, #12]
    this_uart->tx_buff_size = TX_COMPLETE;
    2d94:	68fb      	ldr	r3, [r7, #12]
    2d96:	f04f 0200 	mov.w	r2, #0
    2d9a:	615a      	str	r2, [r3, #20]
    this_uart->tx_buffer = (const uint8_t *)0;
    2d9c:	68fb      	ldr	r3, [r7, #12]
    2d9e:	f04f 0200 	mov.w	r2, #0
    2da2:	611a      	str	r2, [r3, #16]
    this_uart->tx_idx = 0u;
    2da4:	68fb      	ldr	r3, [r7, #12]
    2da6:	f04f 0200 	mov.w	r2, #0
    2daa:	619a      	str	r2, [r3, #24]

    /* Default handlers for MSS UART interrupts */
    this_uart->rx_handler       = NULL_HANDLER;
    2dac:	68fb      	ldr	r3, [r7, #12]
    2dae:	f04f 0200 	mov.w	r2, #0
    2db2:	621a      	str	r2, [r3, #32]
    this_uart->tx_handler       = NULL_HANDLER;
    2db4:	68fb      	ldr	r3, [r7, #12]
    2db6:	f04f 0200 	mov.w	r2, #0
    2dba:	625a      	str	r2, [r3, #36]	; 0x24
    this_uart->linests_handler  = NULL_HANDLER;
    2dbc:	68fb      	ldr	r3, [r7, #12]
    2dbe:	f04f 0200 	mov.w	r2, #0
    2dc2:	61da      	str	r2, [r3, #28]
    this_uart->modemsts_handler = NULL_HANDLER;
    2dc4:	68fb      	ldr	r3, [r7, #12]
    2dc6:	f04f 0200 	mov.w	r2, #0
    2dca:	629a      	str	r2, [r3, #40]	; 0x28
    this_uart->rto_handler      = NULL_HANDLER;    
    2dcc:	68fb      	ldr	r3, [r7, #12]
    2dce:	f04f 0200 	mov.w	r2, #0
    2dd2:	62da      	str	r2, [r3, #44]	; 0x2c
    this_uart->nack_handler     = NULL_HANDLER;   
    2dd4:	68fb      	ldr	r3, [r7, #12]
    2dd6:	f04f 0200 	mov.w	r2, #0
    2dda:	631a      	str	r2, [r3, #48]	; 0x30
    this_uart->pid_pei_handler  = NULL_HANDLER;
    2ddc:	68fb      	ldr	r3, [r7, #12]
    2dde:	f04f 0200 	mov.w	r2, #0
    2de2:	635a      	str	r2, [r3, #52]	; 0x34
    this_uart->break_handler    = NULL_HANDLER;    
    2de4:	68fb      	ldr	r3, [r7, #12]
    2de6:	f04f 0200 	mov.w	r2, #0
    2dea:	639a      	str	r2, [r3, #56]	; 0x38
    this_uart->sync_handler     = NULL_HANDLER;   
    2dec:	68fb      	ldr	r3, [r7, #12]
    2dee:	f04f 0200 	mov.w	r2, #0
    2df2:	63da      	str	r2, [r3, #60]	; 0x3c

    /* Initialize the sticky status */
    this_uart->status = 0u;
    2df4:	68fb      	ldr	r3, [r7, #12]
    2df6:	f04f 0200 	mov.w	r2, #0
    2dfa:	735a      	strb	r2, [r3, #13]
}
    2dfc:	f107 0710 	add.w	r7, r7, #16
    2e00:	46bd      	mov	sp, r7
    2e02:	bd80      	pop	{r7, pc}

00002e04 <MSS_UART_isr>:
static void
MSS_UART_isr
(
    mss_uart_instance_t * this_uart
)
{
    2e04:	b580      	push	{r7, lr}
    2e06:	b084      	sub	sp, #16
    2e08:	af00      	add	r7, sp, #0
    2e0a:	6078      	str	r0, [r7, #4]
    uint8_t iirf;

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    2e0c:	687a      	ldr	r2, [r7, #4]
    2e0e:	f240 13f8 	movw	r3, #504	; 0x1f8
    2e12:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2e16:	429a      	cmp	r2, r3
    2e18:	d007      	beq.n	2e2a <MSS_UART_isr+0x26>
    2e1a:	687a      	ldr	r2, [r7, #4]
    2e1c:	f240 13b8 	movw	r3, #440	; 0x1b8
    2e20:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2e24:	429a      	cmp	r2, r3
    2e26:	d000      	beq.n	2e2a <MSS_UART_isr+0x26>
    2e28:	be00      	bkpt	0x0000

    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
    2e2a:	687a      	ldr	r2, [r7, #4]
    2e2c:	f240 13f8 	movw	r3, #504	; 0x1f8
    2e30:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2e34:	429a      	cmp	r2, r3
    2e36:	d007      	beq.n	2e48 <MSS_UART_isr+0x44>
    2e38:	687a      	ldr	r2, [r7, #4]
    2e3a:	f240 13b8 	movw	r3, #440	; 0x1b8
    2e3e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    2e42:	429a      	cmp	r2, r3
    2e44:	f040 80ef 	bne.w	3026 <MSS_UART_isr+0x222>
    {
        iirf = this_uart->hw_reg->IIR & IIRF_MASK;
    2e48:	687b      	ldr	r3, [r7, #4]
    2e4a:	681b      	ldr	r3, [r3, #0]
    2e4c:	7a1b      	ldrb	r3, [r3, #8]
    2e4e:	b2db      	uxtb	r3, r3
    2e50:	f003 030f 	and.w	r3, r3, #15
    2e54:	73fb      	strb	r3, [r7, #15]

        switch (iirf)
    2e56:	7bfb      	ldrb	r3, [r7, #15]
    2e58:	2b0c      	cmp	r3, #12
    2e5a:	f200 80d7 	bhi.w	300c <MSS_UART_isr+0x208>
    2e5e:	a201      	add	r2, pc, #4	; (adr r2, 2e64 <MSS_UART_isr+0x60>)
    2e60:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
    2e64:	00002e99 	.word	0x00002e99
    2e68:	0000300d 	.word	0x0000300d
    2e6c:	00002eb7 	.word	0x00002eb7
    2e70:	00002f11 	.word	0x00002f11
    2e74:	00002ed5 	.word	0x00002ed5
    2e78:	0000300d 	.word	0x0000300d
    2e7c:	00002ef3 	.word	0x00002ef3
    2e80:	0000300d 	.word	0x0000300d
    2e84:	0000300d 	.word	0x0000300d
    2e88:	0000300d 	.word	0x0000300d
    2e8c:	0000300d 	.word	0x0000300d
    2e90:	0000300d 	.word	0x0000300d
    2e94:	00002ed5 	.word	0x00002ed5
        {
            case IIRF_MODEM_STATUS:  /* Modem status interrupt */
            {
                ASSERT(NULL_HANDLER != this_uart->modemsts_handler);
    2e98:	687b      	ldr	r3, [r7, #4]
    2e9a:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    2e9c:	2b00      	cmp	r3, #0
    2e9e:	d100      	bne.n	2ea2 <MSS_UART_isr+0x9e>
    2ea0:	be00      	bkpt	0x0000
                if(NULL_HANDLER != this_uart->modemsts_handler)
    2ea2:	687b      	ldr	r3, [r7, #4]
    2ea4:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    2ea6:	2b00      	cmp	r3, #0
    2ea8:	f000 80b2 	beq.w	3010 <MSS_UART_isr+0x20c>
                {
                   (*(this_uart->modemsts_handler))(this_uart);
    2eac:	687b      	ldr	r3, [r7, #4]
    2eae:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    2eb0:	6878      	ldr	r0, [r7, #4]
    2eb2:	4798      	blx	r3
                }
            }
            break;
    2eb4:	e0b7      	b.n	3026 <MSS_UART_isr+0x222>

            case IIRF_THRE: /* Transmitter Holding Register Empty */
            {
                ASSERT(NULL_HANDLER != this_uart->tx_handler);
    2eb6:	687b      	ldr	r3, [r7, #4]
    2eb8:	6a5b      	ldr	r3, [r3, #36]	; 0x24
    2eba:	2b00      	cmp	r3, #0
    2ebc:	d100      	bne.n	2ec0 <MSS_UART_isr+0xbc>
    2ebe:	be00      	bkpt	0x0000
                if(NULL_HANDLER != this_uart->tx_handler)
    2ec0:	687b      	ldr	r3, [r7, #4]
    2ec2:	6a5b      	ldr	r3, [r3, #36]	; 0x24
    2ec4:	2b00      	cmp	r3, #0
    2ec6:	f000 80a5 	beq.w	3014 <MSS_UART_isr+0x210>
                {
                    (*(this_uart->tx_handler))(this_uart);
    2eca:	687b      	ldr	r3, [r7, #4]
    2ecc:	6a5b      	ldr	r3, [r3, #36]	; 0x24
    2ece:	6878      	ldr	r0, [r7, #4]
    2ed0:	4798      	blx	r3
                }
            }
            break;
    2ed2:	e0a8      	b.n	3026 <MSS_UART_isr+0x222>

            case IIRF_RX_DATA:      /* Received Data Available */
            case IIRF_DATA_TIMEOUT: /* Received Data Timed-out */
            {
                ASSERT(NULL_HANDLER != this_uart->rx_handler);
    2ed4:	687b      	ldr	r3, [r7, #4]
    2ed6:	6a1b      	ldr	r3, [r3, #32]
    2ed8:	2b00      	cmp	r3, #0
    2eda:	d100      	bne.n	2ede <MSS_UART_isr+0xda>
    2edc:	be00      	bkpt	0x0000
                if(NULL_HANDLER != this_uart->rx_handler)
    2ede:	687b      	ldr	r3, [r7, #4]
    2ee0:	6a1b      	ldr	r3, [r3, #32]
    2ee2:	2b00      	cmp	r3, #0
    2ee4:	f000 8098 	beq.w	3018 <MSS_UART_isr+0x214>
                {
                    (*(this_uart->rx_handler))(this_uart);
    2ee8:	687b      	ldr	r3, [r7, #4]
    2eea:	6a1b      	ldr	r3, [r3, #32]
    2eec:	6878      	ldr	r0, [r7, #4]
    2eee:	4798      	blx	r3
                }
            }
            break;
    2ef0:	e099      	b.n	3026 <MSS_UART_isr+0x222>

            case IIRF_RX_LINE_STATUS:  /* Line Status Interrupt */
            {
                ASSERT(NULL_HANDLER != this_uart->linests_handler);
    2ef2:	687b      	ldr	r3, [r7, #4]
    2ef4:	69db      	ldr	r3, [r3, #28]
    2ef6:	2b00      	cmp	r3, #0
    2ef8:	d100      	bne.n	2efc <MSS_UART_isr+0xf8>
    2efa:	be00      	bkpt	0x0000
                if(NULL_HANDLER != this_uart->linests_handler)
    2efc:	687b      	ldr	r3, [r7, #4]
    2efe:	69db      	ldr	r3, [r3, #28]
    2f00:	2b00      	cmp	r3, #0
    2f02:	f000 808b 	beq.w	301c <MSS_UART_isr+0x218>
                {
                   (*(this_uart->linests_handler))(this_uart);
    2f06:	687b      	ldr	r3, [r7, #4]
    2f08:	69db      	ldr	r3, [r3, #28]
    2f0a:	6878      	ldr	r0, [r7, #4]
    2f0c:	4798      	blx	r3
                }
            }
            break;
    2f0e:	e08a      	b.n	3026 <MSS_UART_isr+0x222>
            case IIRF_MMI:
            {
                /* Identify multimode interrupts and handle */

                /* Receiver time-out interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,ERTOI))
    2f10:	687b      	ldr	r3, [r7, #4]
    2f12:	681b      	ldr	r3, [r3, #0]
    2f14:	f103 0328 	add.w	r3, r3, #40	; 0x28
    2f18:	4618      	mov	r0, r3
    2f1a:	f04f 0100 	mov.w	r1, #0
    2f1e:	f7fe f971 	bl	1204 <read_bit_reg8>
    2f22:	4603      	mov	r3, r0
    2f24:	2b00      	cmp	r3, #0
    2f26:	d00c      	beq.n	2f42 <MSS_UART_isr+0x13e>
                {
                    ASSERT(NULL_HANDLER != this_uart->rto_handler);
    2f28:	687b      	ldr	r3, [r7, #4]
    2f2a:	6adb      	ldr	r3, [r3, #44]	; 0x2c
    2f2c:	2b00      	cmp	r3, #0
    2f2e:	d100      	bne.n	2f32 <MSS_UART_isr+0x12e>
    2f30:	be00      	bkpt	0x0000
                    if(NULL_HANDLER != this_uart->rto_handler)
    2f32:	687b      	ldr	r3, [r7, #4]
    2f34:	6adb      	ldr	r3, [r3, #44]	; 0x2c
    2f36:	2b00      	cmp	r3, #0
    2f38:	d003      	beq.n	2f42 <MSS_UART_isr+0x13e>
                    {
                        (*(this_uart->rto_handler))(this_uart);
    2f3a:	687b      	ldr	r3, [r7, #4]
    2f3c:	6adb      	ldr	r3, [r3, #44]	; 0x2c
    2f3e:	6878      	ldr	r0, [r7, #4]
    2f40:	4798      	blx	r3
                    }
                }
                /* NACK interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,ENACKI))
    2f42:	687b      	ldr	r3, [r7, #4]
    2f44:	681b      	ldr	r3, [r3, #0]
    2f46:	f103 0328 	add.w	r3, r3, #40	; 0x28
    2f4a:	4618      	mov	r0, r3
    2f4c:	f04f 0101 	mov.w	r1, #1
    2f50:	f7fe f958 	bl	1204 <read_bit_reg8>
    2f54:	4603      	mov	r3, r0
    2f56:	2b00      	cmp	r3, #0
    2f58:	d00c      	beq.n	2f74 <MSS_UART_isr+0x170>
                {
                    ASSERT(NULL_HANDLER != this_uart->nack_handler);
    2f5a:	687b      	ldr	r3, [r7, #4]
    2f5c:	6b1b      	ldr	r3, [r3, #48]	; 0x30
    2f5e:	2b00      	cmp	r3, #0
    2f60:	d100      	bne.n	2f64 <MSS_UART_isr+0x160>
    2f62:	be00      	bkpt	0x0000
                    if(NULL_HANDLER != this_uart->nack_handler)
    2f64:	687b      	ldr	r3, [r7, #4]
    2f66:	6b1b      	ldr	r3, [r3, #48]	; 0x30
    2f68:	2b00      	cmp	r3, #0
    2f6a:	d003      	beq.n	2f74 <MSS_UART_isr+0x170>
                    {
                        (*(this_uart->nack_handler))(this_uart);
    2f6c:	687b      	ldr	r3, [r7, #4]
    2f6e:	6b1b      	ldr	r3, [r3, #48]	; 0x30
    2f70:	6878      	ldr	r0, [r7, #4]
    2f72:	4798      	blx	r3
                    }
                }

                /* PID parity error interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,EPID_PEI))
    2f74:	687b      	ldr	r3, [r7, #4]
    2f76:	681b      	ldr	r3, [r3, #0]
    2f78:	f103 0328 	add.w	r3, r3, #40	; 0x28
    2f7c:	4618      	mov	r0, r3
    2f7e:	f04f 0102 	mov.w	r1, #2
    2f82:	f7fe f93f 	bl	1204 <read_bit_reg8>
    2f86:	4603      	mov	r3, r0
    2f88:	2b00      	cmp	r3, #0
    2f8a:	d00c      	beq.n	2fa6 <MSS_UART_isr+0x1a2>
                {
                    ASSERT(NULL_HANDLER != this_uart->pid_pei_handler);
    2f8c:	687b      	ldr	r3, [r7, #4]
    2f8e:	6b5b      	ldr	r3, [r3, #52]	; 0x34
    2f90:	2b00      	cmp	r3, #0
    2f92:	d100      	bne.n	2f96 <MSS_UART_isr+0x192>
    2f94:	be00      	bkpt	0x0000
                    if(NULL_HANDLER != this_uart->pid_pei_handler)
    2f96:	687b      	ldr	r3, [r7, #4]
    2f98:	6b5b      	ldr	r3, [r3, #52]	; 0x34
    2f9a:	2b00      	cmp	r3, #0
    2f9c:	d003      	beq.n	2fa6 <MSS_UART_isr+0x1a2>
                    {
                        (*(this_uart->pid_pei_handler))(this_uart);
    2f9e:	687b      	ldr	r3, [r7, #4]
    2fa0:	6b5b      	ldr	r3, [r3, #52]	; 0x34
    2fa2:	6878      	ldr	r0, [r7, #4]
    2fa4:	4798      	blx	r3
                    }
                }

                /* LIN break detection interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,ELINBI))
    2fa6:	687b      	ldr	r3, [r7, #4]
    2fa8:	681b      	ldr	r3, [r3, #0]
    2faa:	f103 0328 	add.w	r3, r3, #40	; 0x28
    2fae:	4618      	mov	r0, r3
    2fb0:	f04f 0103 	mov.w	r1, #3
    2fb4:	f7fe f926 	bl	1204 <read_bit_reg8>
    2fb8:	4603      	mov	r3, r0
    2fba:	2b00      	cmp	r3, #0
    2fbc:	d00c      	beq.n	2fd8 <MSS_UART_isr+0x1d4>
                {
                    ASSERT(NULL_HANDLER != this_uart->break_handler);
    2fbe:	687b      	ldr	r3, [r7, #4]
    2fc0:	6b9b      	ldr	r3, [r3, #56]	; 0x38
    2fc2:	2b00      	cmp	r3, #0
    2fc4:	d100      	bne.n	2fc8 <MSS_UART_isr+0x1c4>
    2fc6:	be00      	bkpt	0x0000
                    if(NULL_HANDLER != this_uart->break_handler)
    2fc8:	687b      	ldr	r3, [r7, #4]
    2fca:	6b9b      	ldr	r3, [r3, #56]	; 0x38
    2fcc:	2b00      	cmp	r3, #0
    2fce:	d003      	beq.n	2fd8 <MSS_UART_isr+0x1d4>
                    {
                        (*(this_uart->break_handler))(this_uart);
    2fd0:	687b      	ldr	r3, [r7, #4]
    2fd2:	6b9b      	ldr	r3, [r3, #56]	; 0x38
    2fd4:	6878      	ldr	r0, [r7, #4]
    2fd6:	4798      	blx	r3
                    }
                }

                /* LIN Sync detection interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,ELINSI))
    2fd8:	687b      	ldr	r3, [r7, #4]
    2fda:	681b      	ldr	r3, [r3, #0]
    2fdc:	f103 0328 	add.w	r3, r3, #40	; 0x28
    2fe0:	4618      	mov	r0, r3
    2fe2:	f04f 0104 	mov.w	r1, #4
    2fe6:	f7fe f90d 	bl	1204 <read_bit_reg8>
    2fea:	4603      	mov	r3, r0
    2fec:	2b00      	cmp	r3, #0
    2fee:	d017      	beq.n	3020 <MSS_UART_isr+0x21c>
                {
                    ASSERT(NULL_HANDLER != this_uart->sync_handler);
    2ff0:	687b      	ldr	r3, [r7, #4]
    2ff2:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
    2ff4:	2b00      	cmp	r3, #0
    2ff6:	d100      	bne.n	2ffa <MSS_UART_isr+0x1f6>
    2ff8:	be00      	bkpt	0x0000
                    if(NULL_HANDLER != this_uart->sync_handler)
    2ffa:	687b      	ldr	r3, [r7, #4]
    2ffc:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
    2ffe:	2b00      	cmp	r3, #0
    3000:	d010      	beq.n	3024 <MSS_UART_isr+0x220>
                    {
                        (*(this_uart->sync_handler))(this_uart);
    3002:	687b      	ldr	r3, [r7, #4]
    3004:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
    3006:	6878      	ldr	r0, [r7, #4]
    3008:	4798      	blx	r3
                    }
                }
                break;
    300a:	e00c      	b.n	3026 <MSS_UART_isr+0x222>
            }

            default:
            {
                ASSERT(INVALID_INTERRUPT);
    300c:	be00      	bkpt	0x0000
    300e:	e00a      	b.n	3026 <MSS_UART_isr+0x222>
                if(NULL_HANDLER != this_uart->modemsts_handler)
                {
                   (*(this_uart->modemsts_handler))(this_uart);
                }
            }
            break;
    3010:	bf00      	nop
    3012:	e008      	b.n	3026 <MSS_UART_isr+0x222>
                if(NULL_HANDLER != this_uart->tx_handler)
                {
                    (*(this_uart->tx_handler))(this_uart);
                }
            }
            break;
    3014:	bf00      	nop
    3016:	e006      	b.n	3026 <MSS_UART_isr+0x222>
                if(NULL_HANDLER != this_uart->rx_handler)
                {
                    (*(this_uart->rx_handler))(this_uart);
                }
            }
            break;
    3018:	bf00      	nop
    301a:	e004      	b.n	3026 <MSS_UART_isr+0x222>
                if(NULL_HANDLER != this_uart->linests_handler)
                {
                   (*(this_uart->linests_handler))(this_uart);
                }
            }
            break;
    301c:	bf00      	nop
    301e:	e002      	b.n	3026 <MSS_UART_isr+0x222>
                    if(NULL_HANDLER != this_uart->sync_handler)
                    {
                        (*(this_uart->sync_handler))(this_uart);
                    }
                }
                break;
    3020:	bf00      	nop
    3022:	e000      	b.n	3026 <MSS_UART_isr+0x222>
    3024:	bf00      	nop
                ASSERT(INVALID_INTERRUPT);
            }
            break;
        }
    }
}
    3026:	f107 0710 	add.w	r7, r7, #16
    302a:	46bd      	mov	sp, r7
    302c:	bd80      	pop	{r7, pc}
    302e:	bf00      	nop

00003030 <default_tx_handler>:
static void
default_tx_handler
(
    mss_uart_instance_t * this_uart
)
{
    3030:	b580      	push	{r7, lr}
    3032:	b086      	sub	sp, #24
    3034:	af00      	add	r7, sp, #0
    3036:	6078      	str	r0, [r7, #4]
    uint8_t status;

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    3038:	687a      	ldr	r2, [r7, #4]
    303a:	f240 13f8 	movw	r3, #504	; 0x1f8
    303e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3042:	429a      	cmp	r2, r3
    3044:	d007      	beq.n	3056 <default_tx_handler+0x26>
    3046:	687a      	ldr	r2, [r7, #4]
    3048:	f240 13b8 	movw	r3, #440	; 0x1b8
    304c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3050:	429a      	cmp	r2, r3
    3052:	d000      	beq.n	3056 <default_tx_handler+0x26>
    3054:	be00      	bkpt	0x0000
    ASSERT(( (uint8_t *)0 ) != this_uart->tx_buffer);
    3056:	687b      	ldr	r3, [r7, #4]
    3058:	691b      	ldr	r3, [r3, #16]
    305a:	2b00      	cmp	r3, #0
    305c:	d100      	bne.n	3060 <default_tx_handler+0x30>
    305e:	be00      	bkpt	0x0000
    ASSERT(0u < this_uart->tx_buff_size);
    3060:	687b      	ldr	r3, [r7, #4]
    3062:	695b      	ldr	r3, [r3, #20]
    3064:	2b00      	cmp	r3, #0
    3066:	d100      	bne.n	306a <default_tx_handler+0x3a>
    3068:	be00      	bkpt	0x0000

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
    306a:	687a      	ldr	r2, [r7, #4]
    306c:	f240 13f8 	movw	r3, #504	; 0x1f8
    3070:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3074:	429a      	cmp	r2, r3
    3076:	d006      	beq.n	3086 <default_tx_handler+0x56>
    3078:	687a      	ldr	r2, [r7, #4]
    307a:	f240 13b8 	movw	r3, #440	; 0x1b8
    307e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3082:	429a      	cmp	r2, r3
    3084:	d155      	bne.n	3132 <default_tx_handler+0x102>
       (((uint8_t *)0 ) != this_uart->tx_buffer) &&
    3086:	687b      	ldr	r3, [r7, #4]
    3088:	691b      	ldr	r3, [r3, #16]

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(( (uint8_t *)0 ) != this_uart->tx_buffer);
    ASSERT(0u < this_uart->tx_buff_size);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
    308a:	2b00      	cmp	r3, #0
    308c:	d051      	beq.n	3132 <default_tx_handler+0x102>
       (((uint8_t *)0 ) != this_uart->tx_buffer) &&
       (0u < this_uart->tx_buff_size))
    308e:	687b      	ldr	r3, [r7, #4]
    3090:	695b      	ldr	r3, [r3, #20]

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(( (uint8_t *)0 ) != this_uart->tx_buffer);
    ASSERT(0u < this_uart->tx_buff_size);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
    3092:	2b00      	cmp	r3, #0
    3094:	d04d      	beq.n	3132 <default_tx_handler+0x102>
       (((uint8_t *)0 ) != this_uart->tx_buffer) &&
       (0u < this_uart->tx_buff_size))
    {
        /* Read the Line Status Register and update the sticky record. */
        status = this_uart->hw_reg->LSR;
    3096:	687b      	ldr	r3, [r7, #4]
    3098:	681b      	ldr	r3, [r3, #0]
    309a:	7d1b      	ldrb	r3, [r3, #20]
    309c:	72fb      	strb	r3, [r7, #11]
        this_uart->status |= status;
    309e:	687b      	ldr	r3, [r7, #4]
    30a0:	7b5a      	ldrb	r2, [r3, #13]
    30a2:	7afb      	ldrb	r3, [r7, #11]
    30a4:	ea42 0303 	orr.w	r3, r2, r3
    30a8:	b2da      	uxtb	r2, r3
    30aa:	687b      	ldr	r3, [r7, #4]
    30ac:	735a      	strb	r2, [r3, #13]

        /*
         * This function should only be called as a result of a THRE interrupt.
         * Verify that this is true before proceeding to transmit data.
         */
        if(status & MSS_UART_THRE)
    30ae:	7afb      	ldrb	r3, [r7, #11]
    30b0:	f003 0320 	and.w	r3, r3, #32
    30b4:	2b00      	cmp	r3, #0
    30b6:	d029      	beq.n	310c <default_tx_handler+0xdc>
        {
            uint32_t i;
            uint32_t fill_size = TX_FIFO_SIZE;
    30b8:	f04f 0310 	mov.w	r3, #16
    30bc:	613b      	str	r3, [r7, #16]
            uint32_t tx_remain = this_uart->tx_buff_size - this_uart->tx_idx;
    30be:	687b      	ldr	r3, [r7, #4]
    30c0:	695a      	ldr	r2, [r3, #20]
    30c2:	687b      	ldr	r3, [r7, #4]
    30c4:	699b      	ldr	r3, [r3, #24]
    30c6:	ebc3 0302 	rsb	r3, r3, r2
    30ca:	617b      	str	r3, [r7, #20]

            /* Calculate the number of bytes to transmit. */
            if(tx_remain < TX_FIFO_SIZE)
    30cc:	697b      	ldr	r3, [r7, #20]
    30ce:	2b0f      	cmp	r3, #15
    30d0:	d801      	bhi.n	30d6 <default_tx_handler+0xa6>
            {
                fill_size = tx_remain;
    30d2:	697b      	ldr	r3, [r7, #20]
    30d4:	613b      	str	r3, [r7, #16]
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
    30d6:	f04f 0300 	mov.w	r3, #0
    30da:	60fb      	str	r3, [r7, #12]
    30dc:	e012      	b.n	3104 <default_tx_handler+0xd4>
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
    30de:	687b      	ldr	r3, [r7, #4]
    30e0:	681b      	ldr	r3, [r3, #0]
    30e2:	687a      	ldr	r2, [r7, #4]
    30e4:	6911      	ldr	r1, [r2, #16]
    30e6:	687a      	ldr	r2, [r7, #4]
    30e8:	6992      	ldr	r2, [r2, #24]
    30ea:	440a      	add	r2, r1
    30ec:	7812      	ldrb	r2, [r2, #0]
    30ee:	701a      	strb	r2, [r3, #0]
                ++this_uart->tx_idx;
    30f0:	687b      	ldr	r3, [r7, #4]
    30f2:	699b      	ldr	r3, [r3, #24]
    30f4:	f103 0201 	add.w	r2, r3, #1
    30f8:	687b      	ldr	r3, [r7, #4]
    30fa:	619a      	str	r2, [r3, #24]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
    30fc:	68fb      	ldr	r3, [r7, #12]
    30fe:	f103 0301 	add.w	r3, r3, #1
    3102:	60fb      	str	r3, [r7, #12]
    3104:	68fa      	ldr	r2, [r7, #12]
    3106:	693b      	ldr	r3, [r7, #16]
    3108:	429a      	cmp	r2, r3
    310a:	d3e8      	bcc.n	30de <default_tx_handler+0xae>
                ++this_uart->tx_idx;
            }
        }

        /* Flag Tx as complete if all data has been pushed into the Tx FIFO. */
        if(this_uart->tx_idx == this_uart->tx_buff_size)
    310c:	687b      	ldr	r3, [r7, #4]
    310e:	699a      	ldr	r2, [r3, #24]
    3110:	687b      	ldr	r3, [r7, #4]
    3112:	695b      	ldr	r3, [r3, #20]
    3114:	429a      	cmp	r2, r3
    3116:	d10c      	bne.n	3132 <default_tx_handler+0x102>
        {
            this_uart->tx_buff_size = TX_COMPLETE;
    3118:	687b      	ldr	r3, [r7, #4]
    311a:	f04f 0200 	mov.w	r2, #0
    311e:	615a      	str	r2, [r3, #20]
            /* disables TX interrupt */
            clear_bit_reg8(&this_uart->hw_reg->IER,ETBEI);
    3120:	687b      	ldr	r3, [r7, #4]
    3122:	681b      	ldr	r3, [r3, #0]
    3124:	f103 0304 	add.w	r3, r3, #4
    3128:	4618      	mov	r0, r3
    312a:	f04f 0101 	mov.w	r1, #1
    312e:	f7fe f849 	bl	11c4 <clear_bit_reg8>
        }
    }
}
    3132:	f107 0718 	add.w	r7, r7, #24
    3136:	46bd      	mov	sp, r7
    3138:	bd80      	pop	{r7, pc}
    313a:	bf00      	nop

0000313c <NVIC_EnableIRQ>:
    The function enables a device-specific interrupt in the NVIC interrupt controller.

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
    313c:	b480      	push	{r7}
    313e:	b083      	sub	sp, #12
    3140:	af00      	add	r7, sp, #0
    3142:	4603      	mov	r3, r0
    3144:	71fb      	strb	r3, [r7, #7]
  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
    3146:	f24e 1300 	movw	r3, #57600	; 0xe100
    314a:	f2ce 0300 	movt	r3, #57344	; 0xe000
    314e:	f997 2007 	ldrsb.w	r2, [r7, #7]
    3152:	ea4f 1252 	mov.w	r2, r2, lsr #5
    3156:	79f9      	ldrb	r1, [r7, #7]
    3158:	f001 011f 	and.w	r1, r1, #31
    315c:	f04f 0001 	mov.w	r0, #1
    3160:	fa00 f101 	lsl.w	r1, r0, r1
    3164:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
}
    3168:	f107 070c 	add.w	r7, r7, #12
    316c:	46bd      	mov	sp, r7
    316e:	bc80      	pop	{r7}
    3170:	4770      	bx	lr
    3172:	bf00      	nop

00003174 <NVIC_DisableIRQ>:
    The function disables a device-specific interrupt in the NVIC interrupt controller.

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
    3174:	b480      	push	{r7}
    3176:	b083      	sub	sp, #12
    3178:	af00      	add	r7, sp, #0
    317a:	4603      	mov	r3, r0
    317c:	71fb      	strb	r3, [r7, #7]
  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
    317e:	f24e 1300 	movw	r3, #57600	; 0xe100
    3182:	f2ce 0300 	movt	r3, #57344	; 0xe000
    3186:	f997 2007 	ldrsb.w	r2, [r7, #7]
    318a:	ea4f 1252 	mov.w	r2, r2, lsr #5
    318e:	79f9      	ldrb	r1, [r7, #7]
    3190:	f001 011f 	and.w	r1, r1, #31
    3194:	f04f 0001 	mov.w	r0, #1
    3198:	fa00 f101 	lsl.w	r1, r0, r1
    319c:	f102 0220 	add.w	r2, r2, #32
    31a0:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
}
    31a4:	f107 070c 	add.w	r7, r7, #12
    31a8:	46bd      	mov	sp, r7
    31aa:	bc80      	pop	{r7}
    31ac:	4770      	bx	lr
    31ae:	bf00      	nop

000031b0 <NVIC_ClearPendingIRQ>:
    The function clears the pending bit of an external interrupt.

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
    31b0:	b480      	push	{r7}
    31b2:	b083      	sub	sp, #12
    31b4:	af00      	add	r7, sp, #0
    31b6:	4603      	mov	r3, r0
    31b8:	71fb      	strb	r3, [r7, #7]
  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
    31ba:	f24e 1300 	movw	r3, #57600	; 0xe100
    31be:	f2ce 0300 	movt	r3, #57344	; 0xe000
    31c2:	f997 2007 	ldrsb.w	r2, [r7, #7]
    31c6:	ea4f 1252 	mov.w	r2, r2, lsr #5
    31ca:	79f9      	ldrb	r1, [r7, #7]
    31cc:	f001 011f 	and.w	r1, r1, #31
    31d0:	f04f 0001 	mov.w	r0, #1
    31d4:	fa00 f101 	lsl.w	r1, r0, r1
    31d8:	f102 0260 	add.w	r2, r2, #96	; 0x60
    31dc:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
}
    31e0:	f107 070c 	add.w	r7, r7, #12
    31e4:	46bd      	mov	sp, r7
    31e6:	bc80      	pop	{r7}
    31e8:	4770      	bx	lr
    31ea:	bf00      	nop

000031ec <MSS_COMBLK_init>:
void MSS_COMBLK_init
(
    comblk_async_event_handler_t async_event_handler,
    uint8_t* p_response
)
{
    31ec:	b580      	push	{r7, lr}
    31ee:	b082      	sub	sp, #8
    31f0:	af00      	add	r7, sp, #0
    31f2:	6078      	str	r0, [r7, #4]
    31f4:	6039      	str	r1, [r7, #0]
    /*
     * Disable and clear previous interrupts.
     */
    NVIC_DisableIRQ(ComBlk_IRQn);
    31f6:	f04f 0013 	mov.w	r0, #19
    31fa:	f7ff ffbb 	bl	3174 <NVIC_DisableIRQ>
    COMBLK->INT_ENABLE = 0u;
    31fe:	f246 0300 	movw	r3, #24576	; 0x6000
    3202:	f2c4 0301 	movt	r3, #16385	; 0x4001
    3206:	f04f 0200 	mov.w	r2, #0
    320a:	609a      	str	r2, [r3, #8]
    NVIC_ClearPendingIRQ(ComBlk_IRQn);
    320c:	f04f 0013 	mov.w	r0, #19
    3210:	f7ff ffce 	bl	31b0 <NVIC_ClearPendingIRQ>
    
    g_async_event_handler = async_event_handler;
    3214:	f240 1360 	movw	r3, #352	; 0x160
    3218:	f2c2 0300 	movt	r3, #8192	; 0x2000
    321c:	687a      	ldr	r2, [r7, #4]
    321e:	601a      	str	r2, [r3, #0]
    
    /*
     * Initialize COMBLK driver state variables:
     */
    g_request_in_progress = 0u;
    3220:	f240 135c 	movw	r3, #348	; 0x15c
    3224:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3228:	f04f 0200 	mov.w	r2, #0
    322c:	701a      	strb	r2, [r3, #0]
    g_comblk_cmd_opcode = 0u;
    322e:	f240 1338 	movw	r3, #312	; 0x138
    3232:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3236:	f04f 0200 	mov.w	r2, #0
    323a:	701a      	strb	r2, [r3, #0]
    g_comblk_p_cmd = 0u;
    323c:	f240 133c 	movw	r3, #316	; 0x13c
    3240:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3244:	f04f 0200 	mov.w	r2, #0
    3248:	601a      	str	r2, [r3, #0]
    g_comblk_cmd_size = 0u;
    324a:	f240 1340 	movw	r3, #320	; 0x140
    324e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3252:	f04f 0200 	mov.w	r2, #0
    3256:	801a      	strh	r2, [r3, #0]
    g_comblk_p_data = 0u;
    3258:	f240 1344 	movw	r3, #324	; 0x144
    325c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3260:	f04f 0200 	mov.w	r2, #0
    3264:	601a      	str	r2, [r3, #0]
    g_comblk_data_size = 0u;
    3266:	f240 1348 	movw	r3, #328	; 0x148
    326a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    326e:	f04f 0200 	mov.w	r2, #0
    3272:	601a      	str	r2, [r3, #0]
    g_comblk_p_response = p_response;
    3274:	f240 134c 	movw	r3, #332	; 0x14c
    3278:	f2c2 0300 	movt	r3, #8192	; 0x2000
    327c:	683a      	ldr	r2, [r7, #0]
    327e:	601a      	str	r2, [r3, #0]
    g_comblk_response_size = 0u;
    3280:	f240 1350 	movw	r3, #336	; 0x150
    3284:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3288:	f04f 0200 	mov.w	r2, #0
    328c:	801a      	strh	r2, [r3, #0]
    g_comblk_response_idx = 0u;
    328e:	f240 1352 	movw	r3, #338	; 0x152
    3292:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3296:	f04f 0200 	mov.w	r2, #0
    329a:	801a      	strh	r2, [r3, #0]
    g_comblk_completion_handler = 0;
    329c:	f240 1354 	movw	r3, #340	; 0x154
    32a0:	f2c2 0300 	movt	r3, #8192	; 0x2000
    32a4:	f04f 0200 	mov.w	r2, #0
    32a8:	601a      	str	r2, [r3, #0]
    
    g_comblk_state = COMBLK_IDLE;
    32aa:	f240 135d 	movw	r3, #349	; 0x15d
    32ae:	f2c2 0300 	movt	r3, #8192	; 0x2000
    32b2:	f04f 0200 	mov.w	r2, #0
    32b6:	701a      	strb	r2, [r3, #0]
    /*
     * Disable loopback before enabling the MSS COMM_BLK to ensure that any
     * codes waiting in the TX FIFO of the System Controllers COMM_BLK are
     * not lost.
     */
    COMBLK->CONTROL &= ~CR_LOOPBACK_MASK;
    32b8:	f246 0300 	movw	r3, #24576	; 0x6000
    32bc:	f2c4 0301 	movt	r3, #16385	; 0x4001
    32c0:	f246 0200 	movw	r2, #24576	; 0x6000
    32c4:	f2c4 0201 	movt	r2, #16385	; 0x4001
    32c8:	6812      	ldr	r2, [r2, #0]
    32ca:	f022 0220 	bic.w	r2, r2, #32
    32ce:	601a      	str	r2, [r3, #0]
    COMBLK->CONTROL |= CR_ENABLE_MASK;
    32d0:	f246 0300 	movw	r3, #24576	; 0x6000
    32d4:	f2c4 0301 	movt	r3, #16385	; 0x4001
    32d8:	f246 0200 	movw	r2, #24576	; 0x6000
    32dc:	f2c4 0201 	movt	r2, #16385	; 0x4001
    32e0:	6812      	ldr	r2, [r2, #0]
    32e2:	f042 0210 	orr.w	r2, r2, #16
    32e6:	601a      	str	r2, [r3, #0]
    
    /*--------------------------------------------------------------------------
     * Enable receive interrupt to receive asynchronous events from the system
     * controller.
     */
    COMBLK->INT_ENABLE &= ~TXTOKAY_MASK;
    32e8:	f246 0300 	movw	r3, #24576	; 0x6000
    32ec:	f2c4 0301 	movt	r3, #16385	; 0x4001
    32f0:	f246 0200 	movw	r2, #24576	; 0x6000
    32f4:	f2c4 0201 	movt	r2, #16385	; 0x4001
    32f8:	6892      	ldr	r2, [r2, #8]
    32fa:	f022 0201 	bic.w	r2, r2, #1
    32fe:	609a      	str	r2, [r3, #8]
    COMBLK->INT_ENABLE |= RCVOKAY_MASK;
    3300:	f246 0300 	movw	r3, #24576	; 0x6000
    3304:	f2c4 0301 	movt	r3, #16385	; 0x4001
    3308:	f246 0200 	movw	r2, #24576	; 0x6000
    330c:	f2c4 0201 	movt	r2, #16385	; 0x4001
    3310:	6892      	ldr	r2, [r2, #8]
    3312:	f042 0202 	orr.w	r2, r2, #2
    3316:	609a      	str	r2, [r3, #8]
    NVIC_EnableIRQ(ComBlk_IRQn);
    3318:	f04f 0013 	mov.w	r0, #19
    331c:	f7ff ff0e 	bl	313c <NVIC_EnableIRQ>
}
    3320:	f107 0708 	add.w	r7, r7, #8
    3324:	46bd      	mov	sp, r7
    3326:	bd80      	pop	{r7, pc}

00003328 <MSS_COMBLK_send_cmd_with_ptr>:
    uint32_t cmd_params_ptr,
    uint8_t * p_response,
    uint16_t response_size,
    comblk_completion_handler_t completion_handler
)
{
    3328:	b580      	push	{r7, lr}
    332a:	b086      	sub	sp, #24
    332c:	af00      	add	r7, sp, #0
    332e:	60b9      	str	r1, [r7, #8]
    3330:	607a      	str	r2, [r7, #4]
    3332:	4602      	mov	r2, r0
    3334:	73fa      	strb	r2, [r7, #15]
    3336:	807b      	strh	r3, [r7, #2]
    uint32_t tx_okay;
    
    /*--------------------------------------------------------------------------
     * Disable and clear previous interrupts.
     */
    NVIC_DisableIRQ(ComBlk_IRQn);
    3338:	f04f 0013 	mov.w	r0, #19
    333c:	f7ff ff1a 	bl	3174 <NVIC_DisableIRQ>
    COMBLK->INT_ENABLE = 0u;
    3340:	f246 0300 	movw	r3, #24576	; 0x6000
    3344:	f2c4 0301 	movt	r3, #16385	; 0x4001
    3348:	f04f 0200 	mov.w	r2, #0
    334c:	609a      	str	r2, [r3, #8]
    NVIC_ClearPendingIRQ(ComBlk_IRQn);
    334e:	f04f 0013 	mov.w	r0, #19
    3352:	f7ff ff2d 	bl	31b0 <NVIC_ClearPendingIRQ>
    
    /*--------------------------------------------------------------------------
     * Abort current command if any.
     */
    abort_current_cmd();
    3356:	f000 fd73 	bl	3e40 <abort_current_cmd>
    
    /*--------------------------------------------------------------------------
     * Initialize COMBLK driver state variables.
     */
    g_request_in_progress = 1u;
    335a:	f240 135c 	movw	r3, #348	; 0x15c
    335e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3362:	f04f 0201 	mov.w	r2, #1
    3366:	701a      	strb	r2, [r3, #0]
    g_comblk_cmd_opcode = cmd_opcode;
    3368:	f240 1338 	movw	r3, #312	; 0x138
    336c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3370:	7bfa      	ldrb	r2, [r7, #15]
    3372:	701a      	strb	r2, [r3, #0]
    g_comblk_p_cmd = 0u;
    3374:	f240 133c 	movw	r3, #316	; 0x13c
    3378:	f2c2 0300 	movt	r3, #8192	; 0x2000
    337c:	f04f 0200 	mov.w	r2, #0
    3380:	601a      	str	r2, [r3, #0]
    g_comblk_cmd_size = 0u;
    3382:	f240 1340 	movw	r3, #320	; 0x140
    3386:	f2c2 0300 	movt	r3, #8192	; 0x2000
    338a:	f04f 0200 	mov.w	r2, #0
    338e:	801a      	strh	r2, [r3, #0]
    g_comblk_p_data = 0u;
    3390:	f240 1344 	movw	r3, #324	; 0x144
    3394:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3398:	f04f 0200 	mov.w	r2, #0
    339c:	601a      	str	r2, [r3, #0]
    g_comblk_data_size = 0u;
    339e:	f240 1348 	movw	r3, #328	; 0x148
    33a2:	f2c2 0300 	movt	r3, #8192	; 0x2000
    33a6:	f04f 0200 	mov.w	r2, #0
    33aa:	601a      	str	r2, [r3, #0]
    g_comblk_p_response = p_response;
    33ac:	f240 134c 	movw	r3, #332	; 0x14c
    33b0:	f2c2 0300 	movt	r3, #8192	; 0x2000
    33b4:	687a      	ldr	r2, [r7, #4]
    33b6:	601a      	str	r2, [r3, #0]
    g_comblk_response_size = response_size;
    33b8:	f240 1350 	movw	r3, #336	; 0x150
    33bc:	f2c2 0300 	movt	r3, #8192	; 0x2000
    33c0:	887a      	ldrh	r2, [r7, #2]
    33c2:	801a      	strh	r2, [r3, #0]
    g_comblk_response_idx = 0u;
    33c4:	f240 1352 	movw	r3, #338	; 0x152
    33c8:	f2c2 0300 	movt	r3, #8192	; 0x2000
    33cc:	f04f 0200 	mov.w	r2, #0
    33d0:	801a      	strh	r2, [r3, #0]
    g_comblk_page_handler = 0u;
    33d2:	f240 1358 	movw	r3, #344	; 0x158
    33d6:	f2c2 0300 	movt	r3, #8192	; 0x2000
    33da:	f04f 0200 	mov.w	r2, #0
    33de:	601a      	str	r2, [r3, #0]
    g_comblk_completion_handler = completion_handler;
    33e0:	f240 1354 	movw	r3, #340	; 0x154
    33e4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    33e8:	6a3a      	ldr	r2, [r7, #32]
    33ea:	601a      	str	r2, [r3, #0]
    
    /*--------------------------------------------------------------------------
     * Send command opcode as a single byte write to the Tx FIFO.
     */
    send_cmd_opcode(g_comblk_cmd_opcode);
    33ec:	f240 1338 	movw	r3, #312	; 0x138
    33f0:	f2c2 0300 	movt	r3, #8192	; 0x2000
    33f4:	781b      	ldrb	r3, [r3, #0]
    33f6:	b2db      	uxtb	r3, r3
    33f8:	4618      	mov	r0, r3
    33fa:	f000 fd4f 	bl	3e9c <send_cmd_opcode>
    
    /*--------------------------------------------------------------------------
     * Send the command parameters pointer to the Tx FIFO as a single 4 bytes
     * write to the Tx FIFO.
     */
    COMBLK->CONTROL |= CR_SIZETX_MASK;
    33fe:	f246 0300 	movw	r3, #24576	; 0x6000
    3402:	f2c4 0301 	movt	r3, #16385	; 0x4001
    3406:	f246 0200 	movw	r2, #24576	; 0x6000
    340a:	f2c4 0201 	movt	r2, #16385	; 0x4001
    340e:	6812      	ldr	r2, [r2, #0]
    3410:	f042 0204 	orr.w	r2, r2, #4
    3414:	601a      	str	r2, [r3, #0]
    
    /* Wait for space to become available in Tx FIFO. */
    do {
        tx_okay = COMBLK->STATUS & TXTOKAY_MASK;
    3416:	f246 0300 	movw	r3, #24576	; 0x6000
    341a:	f2c4 0301 	movt	r3, #16385	; 0x4001
    341e:	685b      	ldr	r3, [r3, #4]
    3420:	f003 0301 	and.w	r3, r3, #1
    3424:	617b      	str	r3, [r7, #20]
    } while(0u == tx_okay);
    3426:	697b      	ldr	r3, [r7, #20]
    3428:	2b00      	cmp	r3, #0
    342a:	d0f4      	beq.n	3416 <MSS_COMBLK_send_cmd_with_ptr+0xee>
    
    /* Send command opcode. */
    COMBLK->DATA32 = cmd_params_ptr;
    342c:	f246 0300 	movw	r3, #24576	; 0x6000
    3430:	f2c4 0301 	movt	r3, #16385	; 0x4001
    3434:	68ba      	ldr	r2, [r7, #8]
    3436:	615a      	str	r2, [r3, #20]
    
    COMBLK->CONTROL &= ~CR_SIZETX_MASK;
    3438:	f246 0300 	movw	r3, #24576	; 0x6000
    343c:	f2c4 0301 	movt	r3, #16385	; 0x4001
    3440:	f246 0200 	movw	r2, #24576	; 0x6000
    3444:	f2c4 0201 	movt	r2, #16385	; 0x4001
    3448:	6812      	ldr	r2, [r2, #0]
    344a:	f022 0204 	bic.w	r2, r2, #4
    344e:	601a      	str	r2, [r3, #0]
    
    g_comblk_state = COMBLK_WAIT_RESPONSE;
    3450:	f240 135d 	movw	r3, #349	; 0x15d
    3454:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3458:	f04f 0203 	mov.w	r2, #3
    345c:	701a      	strb	r2, [r3, #0]
    
    /*--------------------------------------------------------------------------
     * Enable interrupt.
     */
    COMBLK->INT_ENABLE |= RCVOKAY_MASK;
    345e:	f246 0300 	movw	r3, #24576	; 0x6000
    3462:	f2c4 0301 	movt	r3, #16385	; 0x4001
    3466:	f246 0200 	movw	r2, #24576	; 0x6000
    346a:	f2c4 0201 	movt	r2, #16385	; 0x4001
    346e:	6892      	ldr	r2, [r2, #8]
    3470:	f042 0202 	orr.w	r2, r2, #2
    3474:	609a      	str	r2, [r3, #8]
    NVIC_EnableIRQ(ComBlk_IRQn);
    3476:	f04f 0013 	mov.w	r0, #19
    347a:	f7ff fe5f 	bl	313c <NVIC_EnableIRQ>
}
    347e:	f107 0718 	add.w	r7, r7, #24
    3482:	46bd      	mov	sp, r7
    3484:	bd80      	pop	{r7, pc}
    3486:	bf00      	nop

00003488 <MSS_COMBLK_send_cmd>:
    uint32_t data_size,
    uint8_t * p_response,
    uint16_t response_size,
    comblk_completion_handler_t completion_handler
)
{
    3488:	b580      	push	{r7, lr}
    348a:	b086      	sub	sp, #24
    348c:	af00      	add	r7, sp, #0
    348e:	60f8      	str	r0, [r7, #12]
    3490:	607a      	str	r2, [r7, #4]
    3492:	603b      	str	r3, [r7, #0]
    3494:	460b      	mov	r3, r1
    3496:	817b      	strh	r3, [r7, #10]
    uint32_t size_sent;
    
    ASSERT(cmd_size > 0);
    3498:	897b      	ldrh	r3, [r7, #10]
    349a:	2b00      	cmp	r3, #0
    349c:	d100      	bne.n	34a0 <MSS_COMBLK_send_cmd+0x18>
    349e:	be00      	bkpt	0x0000
    
    /*
     * Disable and clear previous interrupts.
     */
    NVIC_DisableIRQ(ComBlk_IRQn);
    34a0:	f04f 0013 	mov.w	r0, #19
    34a4:	f7ff fe66 	bl	3174 <NVIC_DisableIRQ>
    COMBLK->INT_ENABLE = 0u;
    34a8:	f246 0300 	movw	r3, #24576	; 0x6000
    34ac:	f2c4 0301 	movt	r3, #16385	; 0x4001
    34b0:	f04f 0200 	mov.w	r2, #0
    34b4:	609a      	str	r2, [r3, #8]
    NVIC_ClearPendingIRQ(ComBlk_IRQn);
    34b6:	f04f 0013 	mov.w	r0, #19
    34ba:	f7ff fe79 	bl	31b0 <NVIC_ClearPendingIRQ>
    
    /*
     * Abort current command if any.
     */
    abort_current_cmd();
    34be:	f000 fcbf 	bl	3e40 <abort_current_cmd>
    
    /*
     * Initialize COMBLK driver state variables:
     */
    g_request_in_progress = 1u;
    34c2:	f240 135c 	movw	r3, #348	; 0x15c
    34c6:	f2c2 0300 	movt	r3, #8192	; 0x2000
    34ca:	f04f 0201 	mov.w	r2, #1
    34ce:	701a      	strb	r2, [r3, #0]
    g_comblk_cmd_opcode = p_cmd[0];
    34d0:	68fb      	ldr	r3, [r7, #12]
    34d2:	781a      	ldrb	r2, [r3, #0]
    34d4:	f240 1338 	movw	r3, #312	; 0x138
    34d8:	f2c2 0300 	movt	r3, #8192	; 0x2000
    34dc:	701a      	strb	r2, [r3, #0]
    g_comblk_p_cmd = p_cmd;
    34de:	f240 133c 	movw	r3, #316	; 0x13c
    34e2:	f2c2 0300 	movt	r3, #8192	; 0x2000
    34e6:	68fa      	ldr	r2, [r7, #12]
    34e8:	601a      	str	r2, [r3, #0]
    g_comblk_cmd_size = cmd_size;
    34ea:	f240 1340 	movw	r3, #320	; 0x140
    34ee:	f2c2 0300 	movt	r3, #8192	; 0x2000
    34f2:	897a      	ldrh	r2, [r7, #10]
    34f4:	801a      	strh	r2, [r3, #0]
    g_comblk_p_data = p_data;
    34f6:	f240 1344 	movw	r3, #324	; 0x144
    34fa:	f2c2 0300 	movt	r3, #8192	; 0x2000
    34fe:	687a      	ldr	r2, [r7, #4]
    3500:	601a      	str	r2, [r3, #0]
    g_comblk_data_size = data_size;
    3502:	f240 1348 	movw	r3, #328	; 0x148
    3506:	f2c2 0300 	movt	r3, #8192	; 0x2000
    350a:	683a      	ldr	r2, [r7, #0]
    350c:	601a      	str	r2, [r3, #0]
    g_comblk_p_response = p_response;
    350e:	f240 134c 	movw	r3, #332	; 0x14c
    3512:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3516:	6a3a      	ldr	r2, [r7, #32]
    3518:	601a      	str	r2, [r3, #0]
    g_comblk_response_size = response_size;
    351a:	f240 1350 	movw	r3, #336	; 0x150
    351e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3522:	8cba      	ldrh	r2, [r7, #36]	; 0x24
    3524:	801a      	strh	r2, [r3, #0]
    g_comblk_response_idx = 0u;
    3526:	f240 1352 	movw	r3, #338	; 0x152
    352a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    352e:	f04f 0200 	mov.w	r2, #0
    3532:	801a      	strh	r2, [r3, #0]
    g_comblk_page_handler = 0u;
    3534:	f240 1358 	movw	r3, #344	; 0x158
    3538:	f2c2 0300 	movt	r3, #8192	; 0x2000
    353c:	f04f 0200 	mov.w	r2, #0
    3540:	601a      	str	r2, [r3, #0]
    g_comblk_completion_handler = completion_handler;
    3542:	f240 1354 	movw	r3, #340	; 0x154
    3546:	f2c2 0300 	movt	r3, #8192	; 0x2000
    354a:	6aba      	ldr	r2, [r7, #40]	; 0x28
    354c:	601a      	str	r2, [r3, #0]
    
    COMBLK->INT_ENABLE |= RCVOKAY_MASK;
    354e:	f246 0300 	movw	r3, #24576	; 0x6000
    3552:	f2c4 0301 	movt	r3, #16385	; 0x4001
    3556:	f246 0200 	movw	r2, #24576	; 0x6000
    355a:	f2c4 0201 	movt	r2, #16385	; 0x4001
    355e:	6892      	ldr	r2, [r2, #8]
    3560:	f042 0202 	orr.w	r2, r2, #2
    3564:	609a      	str	r2, [r3, #8]

    /*
     * Fill FIFO with command.
     */
    send_cmd_opcode(g_comblk_cmd_opcode);
    3566:	f240 1338 	movw	r3, #312	; 0x138
    356a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    356e:	781b      	ldrb	r3, [r3, #0]
    3570:	b2db      	uxtb	r3, r3
    3572:	4618      	mov	r0, r3
    3574:	f000 fc92 	bl	3e9c <send_cmd_opcode>
    size_sent = fill_tx_fifo(&p_cmd[1], cmd_size - 1u);
    3578:	68fb      	ldr	r3, [r7, #12]
    357a:	f103 0201 	add.w	r2, r3, #1
    357e:	897b      	ldrh	r3, [r7, #10]
    3580:	f103 33ff 	add.w	r3, r3, #4294967295
    3584:	4610      	mov	r0, r2
    3586:	4619      	mov	r1, r3
    3588:	f000 fcb0 	bl	3eec <fill_tx_fifo>
    358c:	4603      	mov	r3, r0
    358e:	617b      	str	r3, [r7, #20]
    ++size_sent;    /* Adjust for opcode byte sent. */
    3590:	697b      	ldr	r3, [r7, #20]
    3592:	f103 0301 	add.w	r3, r3, #1
    3596:	617b      	str	r3, [r7, #20]
    if(size_sent < cmd_size)
    3598:	897a      	ldrh	r2, [r7, #10]
    359a:	697b      	ldr	r3, [r7, #20]
    359c:	429a      	cmp	r2, r3
    359e:	d923      	bls.n	35e8 <MSS_COMBLK_send_cmd+0x160>
    {
        g_comblk_cmd_size = g_comblk_cmd_size - (uint16_t)size_sent;
    35a0:	f240 1340 	movw	r3, #320	; 0x140
    35a4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    35a8:	881b      	ldrh	r3, [r3, #0]
    35aa:	b29a      	uxth	r2, r3
    35ac:	697b      	ldr	r3, [r7, #20]
    35ae:	b29b      	uxth	r3, r3
    35b0:	ebc3 0302 	rsb	r3, r3, r2
    35b4:	b29a      	uxth	r2, r3
    35b6:	f240 1340 	movw	r3, #320	; 0x140
    35ba:	f2c2 0300 	movt	r3, #8192	; 0x2000
    35be:	801a      	strh	r2, [r3, #0]
        g_comblk_p_cmd = &g_comblk_p_cmd[size_sent];
    35c0:	f240 133c 	movw	r3, #316	; 0x13c
    35c4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    35c8:	681a      	ldr	r2, [r3, #0]
    35ca:	697b      	ldr	r3, [r7, #20]
    35cc:	441a      	add	r2, r3
    35ce:	f240 133c 	movw	r3, #316	; 0x13c
    35d2:	f2c2 0300 	movt	r3, #8192	; 0x2000
    35d6:	601a      	str	r2, [r3, #0]
        
        g_comblk_state = COMBLK_TX_CMD;
    35d8:	f240 135d 	movw	r3, #349	; 0x15d
    35dc:	f2c2 0300 	movt	r3, #8192	; 0x2000
    35e0:	f04f 0201 	mov.w	r2, #1
    35e4:	701a      	strb	r2, [r3, #0]
    35e6:	e01c      	b.n	3622 <MSS_COMBLK_send_cmd+0x19a>
    }
    else
    {
        g_comblk_cmd_size = 0u;
    35e8:	f240 1340 	movw	r3, #320	; 0x140
    35ec:	f2c2 0300 	movt	r3, #8192	; 0x2000
    35f0:	f04f 0200 	mov.w	r2, #0
    35f4:	801a      	strh	r2, [r3, #0]
        if(g_comblk_data_size > 0u)
    35f6:	f240 1348 	movw	r3, #328	; 0x148
    35fa:	f2c2 0300 	movt	r3, #8192	; 0x2000
    35fe:	681b      	ldr	r3, [r3, #0]
    3600:	2b00      	cmp	r3, #0
    3602:	d007      	beq.n	3614 <MSS_COMBLK_send_cmd+0x18c>
        {
            g_comblk_state = COMBLK_TX_DATA;
    3604:	f240 135d 	movw	r3, #349	; 0x15d
    3608:	f2c2 0300 	movt	r3, #8192	; 0x2000
    360c:	f04f 0202 	mov.w	r2, #2
    3610:	701a      	strb	r2, [r3, #0]
    3612:	e006      	b.n	3622 <MSS_COMBLK_send_cmd+0x19a>
        }
        else
        {
            g_comblk_state = COMBLK_WAIT_RESPONSE;
    3614:	f240 135d 	movw	r3, #349	; 0x15d
    3618:	f2c2 0300 	movt	r3, #8192	; 0x2000
    361c:	f04f 0203 	mov.w	r2, #3
    3620:	701a      	strb	r2, [r3, #0]
    }

    /*
     * Enable interrupt.
     */
    NVIC_EnableIRQ(ComBlk_IRQn);
    3622:	f04f 0013 	mov.w	r0, #19
    3626:	f7ff fd89 	bl	313c <NVIC_EnableIRQ>
}
    362a:	f107 0718 	add.w	r7, r7, #24
    362e:	46bd      	mov	sp, r7
    3630:	bd80      	pop	{r7, pc}
    3632:	bf00      	nop

00003634 <MSS_COMBLK_send_paged_cmd>:
    uint8_t * p_response,
    uint16_t response_size,
    comblk_page_handler_t page_read_handler,
    comblk_completion_handler_t completion_handler
)
{
    3634:	b580      	push	{r7, lr}
    3636:	b086      	sub	sp, #24
    3638:	af00      	add	r7, sp, #0
    363a:	60f8      	str	r0, [r7, #12]
    363c:	607a      	str	r2, [r7, #4]
    363e:	460a      	mov	r2, r1
    3640:	817a      	strh	r2, [r7, #10]
    3642:	807b      	strh	r3, [r7, #2]
    uint32_t size_sent;
    uint8_t irq_enable = 0u;
    3644:	f04f 0300 	mov.w	r3, #0
    3648:	75fb      	strb	r3, [r7, #23]
    
    ASSERT(cmd_size > 0u);
    364a:	897b      	ldrh	r3, [r7, #10]
    364c:	2b00      	cmp	r3, #0
    364e:	d100      	bne.n	3652 <MSS_COMBLK_send_paged_cmd+0x1e>
    3650:	be00      	bkpt	0x0000
    
    /*
     * Disable and clear previous interrupts.
     */
    NVIC_DisableIRQ(ComBlk_IRQn);
    3652:	f04f 0013 	mov.w	r0, #19
    3656:	f7ff fd8d 	bl	3174 <NVIC_DisableIRQ>
    COMBLK->INT_ENABLE = 0u;
    365a:	f246 0300 	movw	r3, #24576	; 0x6000
    365e:	f2c4 0301 	movt	r3, #16385	; 0x4001
    3662:	f04f 0200 	mov.w	r2, #0
    3666:	609a      	str	r2, [r3, #8]
    NVIC_ClearPendingIRQ(ComBlk_IRQn);
    3668:	f04f 0013 	mov.w	r0, #19
    366c:	f7ff fda0 	bl	31b0 <NVIC_ClearPendingIRQ>
    
    /*
     * Abort current command if any.
     */
    abort_current_cmd();
    3670:	f000 fbe6 	bl	3e40 <abort_current_cmd>
    
    /*
     * Initialize COMBLK driver state variables:
     */
    g_request_in_progress = 1u;
    3674:	f240 135c 	movw	r3, #348	; 0x15c
    3678:	f2c2 0300 	movt	r3, #8192	; 0x2000
    367c:	f04f 0201 	mov.w	r2, #1
    3680:	701a      	strb	r2, [r3, #0]
    g_comblk_cmd_opcode = p_cmd[0];
    3682:	68fb      	ldr	r3, [r7, #12]
    3684:	781a      	ldrb	r2, [r3, #0]
    3686:	f240 1338 	movw	r3, #312	; 0x138
    368a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    368e:	701a      	strb	r2, [r3, #0]
    g_comblk_p_cmd = p_cmd;
    3690:	f240 133c 	movw	r3, #316	; 0x13c
    3694:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3698:	68fa      	ldr	r2, [r7, #12]
    369a:	601a      	str	r2, [r3, #0]
    g_comblk_cmd_size = cmd_size;
    369c:	f240 1340 	movw	r3, #320	; 0x140
    36a0:	f2c2 0300 	movt	r3, #8192	; 0x2000
    36a4:	897a      	ldrh	r2, [r7, #10]
    36a6:	801a      	strh	r2, [r3, #0]
    g_comblk_p_data = 0;
    36a8:	f240 1344 	movw	r3, #324	; 0x144
    36ac:	f2c2 0300 	movt	r3, #8192	; 0x2000
    36b0:	f04f 0200 	mov.w	r2, #0
    36b4:	601a      	str	r2, [r3, #0]
    g_comblk_data_size = 0u;
    36b6:	f240 1348 	movw	r3, #328	; 0x148
    36ba:	f2c2 0300 	movt	r3, #8192	; 0x2000
    36be:	f04f 0200 	mov.w	r2, #0
    36c2:	601a      	str	r2, [r3, #0]
    g_comblk_p_response = p_response;
    36c4:	f240 134c 	movw	r3, #332	; 0x14c
    36c8:	f2c2 0300 	movt	r3, #8192	; 0x2000
    36cc:	687a      	ldr	r2, [r7, #4]
    36ce:	601a      	str	r2, [r3, #0]
    g_comblk_response_size = response_size;
    36d0:	f240 1350 	movw	r3, #336	; 0x150
    36d4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    36d8:	887a      	ldrh	r2, [r7, #2]
    36da:	801a      	strh	r2, [r3, #0]
    g_comblk_response_idx = 0u;
    36dc:	f240 1352 	movw	r3, #338	; 0x152
    36e0:	f2c2 0300 	movt	r3, #8192	; 0x2000
    36e4:	f04f 0200 	mov.w	r2, #0
    36e8:	801a      	strh	r2, [r3, #0]
    g_comblk_page_handler = page_read_handler;
    36ea:	f240 1358 	movw	r3, #344	; 0x158
    36ee:	f2c2 0300 	movt	r3, #8192	; 0x2000
    36f2:	6a3a      	ldr	r2, [r7, #32]
    36f4:	601a      	str	r2, [r3, #0]
    g_comblk_completion_handler = completion_handler;
    36f6:	f240 1354 	movw	r3, #340	; 0x154
    36fa:	f2c2 0300 	movt	r3, #8192	; 0x2000
    36fe:	6a7a      	ldr	r2, [r7, #36]	; 0x24
    3700:	601a      	str	r2, [r3, #0]
    
    /*
     * Fill FIFO with command.
     */
    send_cmd_opcode(g_comblk_cmd_opcode);
    3702:	f240 1338 	movw	r3, #312	; 0x138
    3706:	f2c2 0300 	movt	r3, #8192	; 0x2000
    370a:	781b      	ldrb	r3, [r3, #0]
    370c:	b2db      	uxtb	r3, r3
    370e:	4618      	mov	r0, r3
    3710:	f000 fbc4 	bl	3e9c <send_cmd_opcode>
    size_sent = fill_tx_fifo(&p_cmd[1], cmd_size - 1u);
    3714:	68fb      	ldr	r3, [r7, #12]
    3716:	f103 0201 	add.w	r2, r3, #1
    371a:	897b      	ldrh	r3, [r7, #10]
    371c:	f103 33ff 	add.w	r3, r3, #4294967295
    3720:	4610      	mov	r0, r2
    3722:	4619      	mov	r1, r3
    3724:	f000 fbe2 	bl	3eec <fill_tx_fifo>
    3728:	4603      	mov	r3, r0
    372a:	613b      	str	r3, [r7, #16]
    ++size_sent;    /* Adjust for opcode byte sent. */
    372c:	693b      	ldr	r3, [r7, #16]
    372e:	f103 0301 	add.w	r3, r3, #1
    3732:	613b      	str	r3, [r7, #16]
    if(size_sent < cmd_size)
    3734:	897a      	ldrh	r2, [r7, #10]
    3736:	693b      	ldr	r3, [r7, #16]
    3738:	429a      	cmp	r2, r3
    373a:	d926      	bls.n	378a <MSS_COMBLK_send_paged_cmd+0x156>
    {
        g_comblk_cmd_size = g_comblk_cmd_size - (uint16_t)size_sent;
    373c:	f240 1340 	movw	r3, #320	; 0x140
    3740:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3744:	881b      	ldrh	r3, [r3, #0]
    3746:	b29a      	uxth	r2, r3
    3748:	693b      	ldr	r3, [r7, #16]
    374a:	b29b      	uxth	r3, r3
    374c:	ebc3 0302 	rsb	r3, r3, r2
    3750:	b29a      	uxth	r2, r3
    3752:	f240 1340 	movw	r3, #320	; 0x140
    3756:	f2c2 0300 	movt	r3, #8192	; 0x2000
    375a:	801a      	strh	r2, [r3, #0]
        g_comblk_p_cmd = &g_comblk_p_cmd[size_sent];
    375c:	f240 133c 	movw	r3, #316	; 0x13c
    3760:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3764:	681a      	ldr	r2, [r3, #0]
    3766:	693b      	ldr	r3, [r7, #16]
    3768:	441a      	add	r2, r3
    376a:	f240 133c 	movw	r3, #316	; 0x13c
    376e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3772:	601a      	str	r2, [r3, #0]
        
        g_comblk_state = COMBLK_TX_CMD;
    3774:	f240 135d 	movw	r3, #349	; 0x15d
    3778:	f2c2 0300 	movt	r3, #8192	; 0x2000
    377c:	f04f 0201 	mov.w	r2, #1
    3780:	701a      	strb	r2, [r3, #0]
        irq_enable = TXTOKAY_MASK | RCVOKAY_MASK;
    3782:	f04f 0303 	mov.w	r3, #3
    3786:	75fb      	strb	r3, [r7, #23]
    3788:	e010      	b.n	37ac <MSS_COMBLK_send_paged_cmd+0x178>
    }
    else
    {
        g_comblk_cmd_size = 0u;
    378a:	f240 1340 	movw	r3, #320	; 0x140
    378e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3792:	f04f 0200 	mov.w	r2, #0
    3796:	801a      	strh	r2, [r3, #0]
        g_comblk_state = COMBLK_TX_PAGED_DATA;
    3798:	f240 135d 	movw	r3, #349	; 0x15d
    379c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    37a0:	f04f 0205 	mov.w	r2, #5
    37a4:	701a      	strb	r2, [r3, #0]
        irq_enable = TXTOKAY_MASK | RCVOKAY_MASK;
    37a6:	f04f 0303 	mov.w	r3, #3
    37aa:	75fb      	strb	r3, [r7, #23]
    }

    /*
     * Enable interrupt.
     */
    COMBLK->INT_ENABLE |= irq_enable;
    37ac:	f246 0300 	movw	r3, #24576	; 0x6000
    37b0:	f2c4 0301 	movt	r3, #16385	; 0x4001
    37b4:	f246 0200 	movw	r2, #24576	; 0x6000
    37b8:	f2c4 0201 	movt	r2, #16385	; 0x4001
    37bc:	6891      	ldr	r1, [r2, #8]
    37be:	7dfa      	ldrb	r2, [r7, #23]
    37c0:	ea41 0202 	orr.w	r2, r1, r2
    37c4:	609a      	str	r2, [r3, #8]
    NVIC_EnableIRQ(ComBlk_IRQn);
    37c6:	f04f 0013 	mov.w	r0, #19
    37ca:	f7ff fcb7 	bl	313c <NVIC_EnableIRQ>
}
    37ce:	f107 0718 	add.w	r7, r7, #24
    37d2:	46bd      	mov	sp, r7
    37d4:	bd80      	pop	{r7, pc}
    37d6:	bf00      	nop

000037d8 <ComBlk_IRQHandler>:

/*==============================================================================
 * COMBLK interrupt handler.
 */
void ComBlk_IRQHandler(void)
{
    37d8:	b580      	push	{r7, lr}
    37da:	b082      	sub	sp, #8
    37dc:	af00      	add	r7, sp, #0
    uint8_t status;
    uint8_t tx_okay;
    uint8_t rcv_okay;
    
    status = (uint8_t)COMBLK->STATUS;
    37de:	f246 0300 	movw	r3, #24576	; 0x6000
    37e2:	f2c4 0301 	movt	r3, #16385	; 0x4001
    37e6:	685b      	ldr	r3, [r3, #4]
    37e8:	717b      	strb	r3, [r7, #5]
    
    /* Mask off interrupt that are not enabled.*/
    status &= COMBLK->INT_ENABLE;
    37ea:	f246 0300 	movw	r3, #24576	; 0x6000
    37ee:	f2c4 0301 	movt	r3, #16385	; 0x4001
    37f2:	689b      	ldr	r3, [r3, #8]
    37f4:	b2da      	uxtb	r2, r3
    37f6:	797b      	ldrb	r3, [r7, #5]
    37f8:	ea02 0303 	and.w	r3, r2, r3
    37fc:	717b      	strb	r3, [r7, #5]
    
    rcv_okay = status & RCVOKAY_MASK;
    37fe:	797b      	ldrb	r3, [r7, #5]
    3800:	f003 0302 	and.w	r3, r3, #2
    3804:	71fb      	strb	r3, [r7, #7]
    
    if(rcv_okay)
    3806:	79fb      	ldrb	r3, [r7, #7]
    3808:	2b00      	cmp	r3, #0
    380a:	d001      	beq.n	3810 <ComBlk_IRQHandler+0x38>
    {
        handle_rx_okay_irq();
    380c:	f000 f970 	bl	3af0 <handle_rx_okay_irq>
    }
        
    tx_okay = status & TXTOKAY_MASK;
    3810:	797b      	ldrb	r3, [r7, #5]
    3812:	f003 0301 	and.w	r3, r3, #1
    3816:	71bb      	strb	r3, [r7, #6]
    if(tx_okay)
    3818:	79bb      	ldrb	r3, [r7, #6]
    381a:	2b00      	cmp	r3, #0
    381c:	d001      	beq.n	3822 <ComBlk_IRQHandler+0x4a>
    {
        handle_tx_okay_irq();
    381e:	f000 f805 	bl	382c <handle_tx_okay_irq>
    }
}
    3822:	f107 0708 	add.w	r7, r7, #8
    3826:	46bd      	mov	sp, r7
    3828:	bd80      	pop	{r7, pc}
    382a:	bf00      	nop

0000382c <handle_tx_okay_irq>:

/*==============================================================================
 *
 */
static void handle_tx_okay_irq(void)
{
    382c:	b580      	push	{r7, lr}
    382e:	b084      	sub	sp, #16
    3830:	af00      	add	r7, sp, #0
    switch(g_comblk_state)
    3832:	f240 135d 	movw	r3, #349	; 0x15d
    3836:	f2c2 0300 	movt	r3, #8192	; 0x2000
    383a:	781b      	ldrb	r3, [r3, #0]
    383c:	2b02      	cmp	r3, #2
    383e:	d067      	beq.n	3910 <handle_tx_okay_irq+0xe4>
    3840:	2b05      	cmp	r3, #5
    3842:	f000 80b6 	beq.w	39b2 <handle_tx_okay_irq+0x186>
    3846:	2b01      	cmp	r3, #1
    3848:	f040 8136 	bne.w	3ab8 <handle_tx_okay_irq+0x28c>
        /*----------------------------------------------------------------------
         * The TX_OKAY interrupt should only be enabled for states COMBLK_TX_CMD
         * and COMBLK_TX_DATA.
         */
        case COMBLK_TX_CMD:
            if(g_comblk_cmd_size > 0u)
    384c:	f240 1340 	movw	r3, #320	; 0x140
    3850:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3854:	881b      	ldrh	r3, [r3, #0]
    3856:	b29b      	uxth	r3, r3
    3858:	2b00      	cmp	r3, #0
    385a:	d055      	beq.n	3908 <handle_tx_okay_irq+0xdc>
            {
                uint32_t size_sent;
                size_sent = fill_tx_fifo(g_comblk_p_cmd, g_comblk_cmd_size);
    385c:	f240 133c 	movw	r3, #316	; 0x13c
    3860:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3864:	681a      	ldr	r2, [r3, #0]
    3866:	f240 1340 	movw	r3, #320	; 0x140
    386a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    386e:	881b      	ldrh	r3, [r3, #0]
    3870:	b29b      	uxth	r3, r3
    3872:	4610      	mov	r0, r2
    3874:	4619      	mov	r1, r3
    3876:	f000 fb39 	bl	3eec <fill_tx_fifo>
    387a:	4603      	mov	r3, r0
    387c:	607b      	str	r3, [r7, #4]
                if(size_sent < g_comblk_cmd_size)
    387e:	f240 1340 	movw	r3, #320	; 0x140
    3882:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3886:	881b      	ldrh	r3, [r3, #0]
    3888:	b29b      	uxth	r3, r3
    388a:	461a      	mov	r2, r3
    388c:	687b      	ldr	r3, [r7, #4]
    388e:	429a      	cmp	r2, r3
    3890:	d91c      	bls.n	38cc <handle_tx_okay_irq+0xa0>
                {
                    g_comblk_cmd_size = g_comblk_cmd_size - (uint16_t)size_sent;
    3892:	f240 1340 	movw	r3, #320	; 0x140
    3896:	f2c2 0300 	movt	r3, #8192	; 0x2000
    389a:	881b      	ldrh	r3, [r3, #0]
    389c:	b29a      	uxth	r2, r3
    389e:	687b      	ldr	r3, [r7, #4]
    38a0:	b29b      	uxth	r3, r3
    38a2:	ebc3 0302 	rsb	r3, r3, r2
    38a6:	b29a      	uxth	r2, r3
    38a8:	f240 1340 	movw	r3, #320	; 0x140
    38ac:	f2c2 0300 	movt	r3, #8192	; 0x2000
    38b0:	801a      	strh	r2, [r3, #0]
                    g_comblk_p_cmd = &g_comblk_p_cmd[size_sent];
    38b2:	f240 133c 	movw	r3, #316	; 0x13c
    38b6:	f2c2 0300 	movt	r3, #8192	; 0x2000
    38ba:	681a      	ldr	r2, [r3, #0]
    38bc:	687b      	ldr	r3, [r7, #4]
    38be:	441a      	add	r2, r3
    38c0:	f240 133c 	movw	r3, #316	; 0x13c
    38c4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    38c8:	601a      	str	r2, [r3, #0]
                 * or corrupted memory.
                 */
                ASSERT(0);
                abort_current_cmd();
            }
        break;
    38ca:	e10c      	b.n	3ae6 <handle_tx_okay_irq+0x2ba>
                    g_comblk_cmd_size = g_comblk_cmd_size - (uint16_t)size_sent;
                    g_comblk_p_cmd = &g_comblk_p_cmd[size_sent];
                }
                else
                {
                    g_comblk_cmd_size = 0u;
    38cc:	f240 1340 	movw	r3, #320	; 0x140
    38d0:	f2c2 0300 	movt	r3, #8192	; 0x2000
    38d4:	f04f 0200 	mov.w	r2, #0
    38d8:	801a      	strh	r2, [r3, #0]
                    if(g_comblk_data_size > 0u)
    38da:	f240 1348 	movw	r3, #328	; 0x148
    38de:	f2c2 0300 	movt	r3, #8192	; 0x2000
    38e2:	681b      	ldr	r3, [r3, #0]
    38e4:	2b00      	cmp	r3, #0
    38e6:	d007      	beq.n	38f8 <handle_tx_okay_irq+0xcc>
                    {
                        g_comblk_state = COMBLK_TX_DATA;
    38e8:	f240 135d 	movw	r3, #349	; 0x15d
    38ec:	f2c2 0300 	movt	r3, #8192	; 0x2000
    38f0:	f04f 0202 	mov.w	r2, #2
    38f4:	701a      	strb	r2, [r3, #0]
                 * or corrupted memory.
                 */
                ASSERT(0);
                abort_current_cmd();
            }
        break;
    38f6:	e0f6      	b.n	3ae6 <handle_tx_okay_irq+0x2ba>
                    {
                        g_comblk_state = COMBLK_TX_DATA;
                    }
                    else
                    {
                        g_comblk_state = COMBLK_WAIT_RESPONSE;
    38f8:	f240 135d 	movw	r3, #349	; 0x15d
    38fc:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3900:	f04f 0203 	mov.w	r2, #3
    3904:	701a      	strb	r2, [r3, #0]
                 * or corrupted memory.
                 */
                ASSERT(0);
                abort_current_cmd();
            }
        break;
    3906:	e0ee      	b.n	3ae6 <handle_tx_okay_irq+0x2ba>
            {
                /*
                 * This is an invalid situation indicating a bug in the driver
                 * or corrupted memory.
                 */
                ASSERT(0);
    3908:	be00      	bkpt	0x0000
                abort_current_cmd();
    390a:	f000 fa99 	bl	3e40 <abort_current_cmd>
            }
        break;
    390e:	e0ea      	b.n	3ae6 <handle_tx_okay_irq+0x2ba>
            
        case COMBLK_TX_DATA:
            if(g_comblk_data_size > 0u)
    3910:	f240 1348 	movw	r3, #328	; 0x148
    3914:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3918:	681b      	ldr	r3, [r3, #0]
    391a:	2b00      	cmp	r3, #0
    391c:	d045      	beq.n	39aa <handle_tx_okay_irq+0x17e>
            {
                uint32_t size_sent;
                size_sent = fill_tx_fifo(g_comblk_p_data, g_comblk_data_size);
    391e:	f240 1344 	movw	r3, #324	; 0x144
    3922:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3926:	681a      	ldr	r2, [r3, #0]
    3928:	f240 1348 	movw	r3, #328	; 0x148
    392c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3930:	681b      	ldr	r3, [r3, #0]
    3932:	4610      	mov	r0, r2
    3934:	4619      	mov	r1, r3
    3936:	f000 fad9 	bl	3eec <fill_tx_fifo>
    393a:	4603      	mov	r3, r0
    393c:	60bb      	str	r3, [r7, #8]
                if(size_sent < g_comblk_data_size)
    393e:	f240 1348 	movw	r3, #328	; 0x148
    3942:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3946:	681b      	ldr	r3, [r3, #0]
    3948:	68ba      	ldr	r2, [r7, #8]
    394a:	429a      	cmp	r2, r3
    394c:	d219      	bcs.n	3982 <handle_tx_okay_irq+0x156>
                {
                    g_comblk_data_size = g_comblk_data_size - size_sent;
    394e:	f240 1348 	movw	r3, #328	; 0x148
    3952:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3956:	681a      	ldr	r2, [r3, #0]
    3958:	68bb      	ldr	r3, [r7, #8]
    395a:	ebc3 0202 	rsb	r2, r3, r2
    395e:	f240 1348 	movw	r3, #328	; 0x148
    3962:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3966:	601a      	str	r2, [r3, #0]
                    g_comblk_p_data = &g_comblk_p_data[size_sent];
    3968:	f240 1344 	movw	r3, #324	; 0x144
    396c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3970:	681a      	ldr	r2, [r3, #0]
    3972:	68bb      	ldr	r3, [r7, #8]
    3974:	441a      	add	r2, r3
    3976:	f240 1344 	movw	r3, #324	; 0x144
    397a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    397e:	601a      	str	r2, [r3, #0]
                 * or corrupted memory.
                 */
                ASSERT(0);
                abort_current_cmd();
            }
        break;
    3980:	e0b1      	b.n	3ae6 <handle_tx_okay_irq+0x2ba>
                    g_comblk_data_size = g_comblk_data_size - size_sent;
                    g_comblk_p_data = &g_comblk_p_data[size_sent];
                }
                else
                {
                    COMBLK->INT_ENABLE &= ~TXTOKAY_MASK;
    3982:	f246 0300 	movw	r3, #24576	; 0x6000
    3986:	f2c4 0301 	movt	r3, #16385	; 0x4001
    398a:	f246 0200 	movw	r2, #24576	; 0x6000
    398e:	f2c4 0201 	movt	r2, #16385	; 0x4001
    3992:	6892      	ldr	r2, [r2, #8]
    3994:	f022 0201 	bic.w	r2, r2, #1
    3998:	609a      	str	r2, [r3, #8]
                    g_comblk_state = COMBLK_WAIT_RESPONSE;
    399a:	f240 135d 	movw	r3, #349	; 0x15d
    399e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    39a2:	f04f 0203 	mov.w	r2, #3
    39a6:	701a      	strb	r2, [r3, #0]
                 * or corrupted memory.
                 */
                ASSERT(0);
                abort_current_cmd();
            }
        break;
    39a8:	e09d      	b.n	3ae6 <handle_tx_okay_irq+0x2ba>
            {
                /*
                 * This is an invalid situation indicating a bug in the driver
                 * or corrupted memory.
                 */
                ASSERT(0);
    39aa:	be00      	bkpt	0x0000
                abort_current_cmd();
    39ac:	f000 fa48 	bl	3e40 <abort_current_cmd>
            }
        break;
    39b0:	e099      	b.n	3ae6 <handle_tx_okay_irq+0x2ba>
           
        case COMBLK_TX_PAGED_DATA:
            /*
             * Read a page of data if required.
             */
            if(0u == g_comblk_data_size)
    39b2:	f240 1348 	movw	r3, #328	; 0x148
    39b6:	f2c2 0300 	movt	r3, #8192	; 0x2000
    39ba:	681b      	ldr	r3, [r3, #0]
    39bc:	2b00      	cmp	r3, #0
    39be:	d136      	bne.n	3a2e <handle_tx_okay_irq+0x202>
            {
                if(g_comblk_page_handler != 0)
    39c0:	f240 1358 	movw	r3, #344	; 0x158
    39c4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    39c8:	681b      	ldr	r3, [r3, #0]
    39ca:	2b00      	cmp	r3, #0
    39cc:	d02a      	beq.n	3a24 <handle_tx_okay_irq+0x1f8>
                {
                    g_comblk_data_size = g_comblk_page_handler(&g_comblk_p_data);
    39ce:	f240 1358 	movw	r3, #344	; 0x158
    39d2:	f2c2 0300 	movt	r3, #8192	; 0x2000
    39d6:	681b      	ldr	r3, [r3, #0]
    39d8:	f240 1044 	movw	r0, #324	; 0x144
    39dc:	f2c2 0000 	movt	r0, #8192	; 0x2000
    39e0:	4798      	blx	r3
    39e2:	4602      	mov	r2, r0
    39e4:	f240 1348 	movw	r3, #328	; 0x148
    39e8:	f2c2 0300 	movt	r3, #8192	; 0x2000
    39ec:	601a      	str	r2, [r3, #0]
                    if(0u == g_comblk_data_size)
    39ee:	f240 1348 	movw	r3, #328	; 0x148
    39f2:	f2c2 0300 	movt	r3, #8192	; 0x2000
    39f6:	681b      	ldr	r3, [r3, #0]
    39f8:	2b00      	cmp	r3, #0
    39fa:	d117      	bne.n	3a2c <handle_tx_okay_irq+0x200>
                    {
                        COMBLK->INT_ENABLE &= ~TXTOKAY_MASK;
    39fc:	f246 0300 	movw	r3, #24576	; 0x6000
    3a00:	f2c4 0301 	movt	r3, #16385	; 0x4001
    3a04:	f246 0200 	movw	r2, #24576	; 0x6000
    3a08:	f2c4 0201 	movt	r2, #16385	; 0x4001
    3a0c:	6892      	ldr	r2, [r2, #8]
    3a0e:	f022 0201 	bic.w	r2, r2, #1
    3a12:	609a      	str	r2, [r3, #8]
                        g_comblk_state = COMBLK_WAIT_RESPONSE;
    3a14:	f240 135d 	movw	r3, #349	; 0x15d
    3a18:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3a1c:	f04f 0203 	mov.w	r2, #3
    3a20:	701a      	strb	r2, [r3, #0]
    3a22:	e004      	b.n	3a2e <handle_tx_okay_irq+0x202>
                    }
                }
                else
                {
                    ASSERT(0);
    3a24:	be00      	bkpt	0x0000
                    abort_current_cmd();
    3a26:	f000 fa0b 	bl	3e40 <abort_current_cmd>
    3a2a:	e000      	b.n	3a2e <handle_tx_okay_irq+0x202>
                {
                    g_comblk_data_size = g_comblk_page_handler(&g_comblk_p_data);
                    if(0u == g_comblk_data_size)
                    {
                        COMBLK->INT_ENABLE &= ~TXTOKAY_MASK;
                        g_comblk_state = COMBLK_WAIT_RESPONSE;
    3a2c:	bf00      	nop
            /*
             * Transmit the page data or move to COMBLK_WAIT_RESPONSE state if
             * no further page data could be obtained by the call to the page
             * handler above.
             */
            if(0u == g_comblk_data_size)
    3a2e:	f240 1348 	movw	r3, #328	; 0x148
    3a32:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3a36:	681b      	ldr	r3, [r3, #0]
    3a38:	2b00      	cmp	r3, #0
    3a3a:	d113      	bne.n	3a64 <handle_tx_okay_irq+0x238>
            {
                COMBLK->INT_ENABLE &= ~TXTOKAY_MASK;
    3a3c:	f246 0300 	movw	r3, #24576	; 0x6000
    3a40:	f2c4 0301 	movt	r3, #16385	; 0x4001
    3a44:	f246 0200 	movw	r2, #24576	; 0x6000
    3a48:	f2c4 0201 	movt	r2, #16385	; 0x4001
    3a4c:	6892      	ldr	r2, [r2, #8]
    3a4e:	f022 0201 	bic.w	r2, r2, #1
    3a52:	609a      	str	r2, [r3, #8]
                g_comblk_state = COMBLK_WAIT_RESPONSE;
    3a54:	f240 135d 	movw	r3, #349	; 0x15d
    3a58:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3a5c:	f04f 0203 	mov.w	r2, #3
    3a60:	701a      	strb	r2, [r3, #0]
                uint32_t size_sent;
                size_sent = fill_tx_fifo(g_comblk_p_data, g_comblk_data_size);
                g_comblk_data_size = g_comblk_data_size - size_sent;
                g_comblk_p_data = &g_comblk_p_data[size_sent];
            }
        break;
    3a62:	e040      	b.n	3ae6 <handle_tx_okay_irq+0x2ba>
                g_comblk_state = COMBLK_WAIT_RESPONSE;
            }
            else
            {
                uint32_t size_sent;
                size_sent = fill_tx_fifo(g_comblk_p_data, g_comblk_data_size);
    3a64:	f240 1344 	movw	r3, #324	; 0x144
    3a68:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3a6c:	681a      	ldr	r2, [r3, #0]
    3a6e:	f240 1348 	movw	r3, #328	; 0x148
    3a72:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3a76:	681b      	ldr	r3, [r3, #0]
    3a78:	4610      	mov	r0, r2
    3a7a:	4619      	mov	r1, r3
    3a7c:	f000 fa36 	bl	3eec <fill_tx_fifo>
    3a80:	4603      	mov	r3, r0
    3a82:	60fb      	str	r3, [r7, #12]
                g_comblk_data_size = g_comblk_data_size - size_sent;
    3a84:	f240 1348 	movw	r3, #328	; 0x148
    3a88:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3a8c:	681a      	ldr	r2, [r3, #0]
    3a8e:	68fb      	ldr	r3, [r7, #12]
    3a90:	ebc3 0202 	rsb	r2, r3, r2
    3a94:	f240 1348 	movw	r3, #328	; 0x148
    3a98:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3a9c:	601a      	str	r2, [r3, #0]
                g_comblk_p_data = &g_comblk_p_data[size_sent];
    3a9e:	f240 1344 	movw	r3, #324	; 0x144
    3aa2:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3aa6:	681a      	ldr	r2, [r3, #0]
    3aa8:	68fb      	ldr	r3, [r7, #12]
    3aaa:	441a      	add	r2, r3
    3aac:	f240 1344 	movw	r3, #324	; 0x144
    3ab0:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3ab4:	601a      	str	r2, [r3, #0]
            }
        break;
    3ab6:	e016      	b.n	3ae6 <handle_tx_okay_irq+0x2ba>
        case COMBLK_WAIT_RESPONSE:
            /* Fall through */
        case COMBLK_RX_RESPONSE:
            /* Fall through */
        default:
            COMBLK->INT_ENABLE &= ~TXTOKAY_MASK;
    3ab8:	f246 0300 	movw	r3, #24576	; 0x6000
    3abc:	f2c4 0301 	movt	r3, #16385	; 0x4001
    3ac0:	f246 0200 	movw	r2, #24576	; 0x6000
    3ac4:	f2c4 0201 	movt	r2, #16385	; 0x4001
    3ac8:	6892      	ldr	r2, [r2, #8]
    3aca:	f022 0201 	bic.w	r2, r2, #1
    3ace:	609a      	str	r2, [r3, #8]
            complete_request(0u);
    3ad0:	f04f 0000 	mov.w	r0, #0
    3ad4:	f000 f988 	bl	3de8 <complete_request>
            g_comblk_state = COMBLK_IDLE;
    3ad8:	f240 135d 	movw	r3, #349	; 0x15d
    3adc:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3ae0:	f04f 0200 	mov.w	r2, #0
    3ae4:	701a      	strb	r2, [r3, #0]
        break;
    }
}
    3ae6:	f107 0710 	add.w	r7, r7, #16
    3aea:	46bd      	mov	sp, r7
    3aec:	bd80      	pop	{r7, pc}
    3aee:	bf00      	nop

00003af0 <handle_rx_okay_irq>:

/*==============================================================================
 *
 */
static void handle_rx_okay_irq(void)
{
    3af0:	b580      	push	{r7, lr}
    3af2:	b084      	sub	sp, #16
    3af4:	af00      	add	r7, sp, #0
    uint16_t data16;
    uint16_t is_command;
    uint8_t data8;
    
    data16 = (uint16_t)COMBLK->DATA8;
    3af6:	f246 0300 	movw	r3, #24576	; 0x6000
    3afa:	f2c4 0301 	movt	r3, #16385	; 0x4001
    3afe:	691b      	ldr	r3, [r3, #16]
    3b00:	80bb      	strh	r3, [r7, #4]
    is_command = data16 & DATA8_COMMAND_MASK;
    3b02:	88bb      	ldrh	r3, [r7, #4]
    3b04:	f423 43fe 	bic.w	r3, r3, #32512	; 0x7f00
    3b08:	f023 03ff 	bic.w	r3, r3, #255	; 0xff
    3b0c:	80fb      	strh	r3, [r7, #6]
    data8 = (uint8_t)data16;
    3b0e:	88bb      	ldrh	r3, [r7, #4]
    3b10:	727b      	strb	r3, [r7, #9]
            
    switch(g_comblk_state)
    3b12:	f240 135d 	movw	r3, #349	; 0x15d
    3b16:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3b1a:	781b      	ldrb	r3, [r3, #0]
    3b1c:	2b05      	cmp	r3, #5
    3b1e:	f200 814b 	bhi.w	3db8 <handle_rx_okay_irq+0x2c8>
    3b22:	a201      	add	r2, pc, #4	; (adr r2, 3b28 <handle_rx_okay_irq+0x38>)
    3b24:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
    3b28:	00003b41 	.word	0x00003b41
    3b2c:	00003da5 	.word	0x00003da5
    3b30:	00003da5 	.word	0x00003da5
    3b34:	00003bd1 	.word	0x00003bd1
    3b38:	00003c4f 	.word	0x00003c4f
    3b3c:	00003d67 	.word	0x00003d67
        * MSS_COMBLK_init() enables the RCV_OKAY interrupt for the COMBLK_IDLE
        * state to receive the asynchronous power-on-reset from the system
        * controller.
        */
        case COMBLK_IDLE:
            if(is_command)
    3b40:	88fb      	ldrh	r3, [r7, #6]
    3b42:	2b00      	cmp	r3, #0
    3b44:	f000 8144 	beq.w	3dd0 <handle_rx_okay_irq+0x2e0>
            {
                if(data8 != POR_DIGEST_ERROR_OPCODE)
    3b48:	7a7b      	ldrb	r3, [r7, #9]
    3b4a:	2bf1      	cmp	r3, #241	; 0xf1
    3b4c:	d006      	beq.n	3b5c <handle_rx_okay_irq+0x6c>
                {
                    uint8_t rxed_opcode;
                    rxed_opcode = data8;
    3b4e:	7a7b      	ldrb	r3, [r7, #9]
    3b50:	72bb      	strb	r3, [r7, #10]
                    process_sys_ctrl_command(rxed_opcode);
    3b52:	7abb      	ldrb	r3, [r7, #10]
    3b54:	4618      	mov	r0, r3
    3b56:	f000 fa09 	bl	3f6c <process_sys_ctrl_command>
                    g_comblk_response_idx++;
                    g_comblk_p_response[g_comblk_response_idx] = 0x00u;                
                    g_comblk_state = COMBLK_RX_RESPONSE;
                }
            }
        break;
    3b5a:	e140      	b.n	3dde <handle_rx_okay_irq+0x2ee>
                    rxed_opcode = data8;
                    process_sys_ctrl_command(rxed_opcode);
                }
                else
                {  
                    g_comblk_response_idx = 0;
    3b5c:	f240 1352 	movw	r3, #338	; 0x152
    3b60:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3b64:	f04f 0200 	mov.w	r2, #0
    3b68:	801a      	strh	r2, [r3, #0]
                    g_comblk_p_response[g_comblk_response_idx] = data8;
    3b6a:	f240 134c 	movw	r3, #332	; 0x14c
    3b6e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3b72:	681a      	ldr	r2, [r3, #0]
    3b74:	f240 1352 	movw	r3, #338	; 0x152
    3b78:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3b7c:	881b      	ldrh	r3, [r3, #0]
    3b7e:	b29b      	uxth	r3, r3
    3b80:	4413      	add	r3, r2
    3b82:	7a7a      	ldrb	r2, [r7, #9]
    3b84:	701a      	strb	r2, [r3, #0]
                    g_comblk_response_idx++;
    3b86:	f240 1352 	movw	r3, #338	; 0x152
    3b8a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3b8e:	881b      	ldrh	r3, [r3, #0]
    3b90:	b29b      	uxth	r3, r3
    3b92:	f103 0301 	add.w	r3, r3, #1
    3b96:	b29a      	uxth	r2, r3
    3b98:	f240 1352 	movw	r3, #338	; 0x152
    3b9c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3ba0:	801a      	strh	r2, [r3, #0]
                    g_comblk_p_response[g_comblk_response_idx] = 0x00u;                
    3ba2:	f240 134c 	movw	r3, #332	; 0x14c
    3ba6:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3baa:	681a      	ldr	r2, [r3, #0]
    3bac:	f240 1352 	movw	r3, #338	; 0x152
    3bb0:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3bb4:	881b      	ldrh	r3, [r3, #0]
    3bb6:	b29b      	uxth	r3, r3
    3bb8:	4413      	add	r3, r2
    3bba:	f04f 0200 	mov.w	r2, #0
    3bbe:	701a      	strb	r2, [r3, #0]
                    g_comblk_state = COMBLK_RX_RESPONSE;
    3bc0:	f240 135d 	movw	r3, #349	; 0x15d
    3bc4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3bc8:	f04f 0204 	mov.w	r2, #4
    3bcc:	701a      	strb	r2, [r3, #0]
                }
            }
        break;
    3bce:	e106      	b.n	3dde <handle_rx_okay_irq+0x2ee>
        /*----------------------------------------------------------------------
         * The RCV_OKAY interrupt should only be enabled for states
         * COMBLK_WAIT_RESPONSE and COMBLK_RX_RESPONSE. 
         */
        case COMBLK_WAIT_RESPONSE:
            if(is_command)
    3bd0:	88fb      	ldrh	r3, [r7, #6]
    3bd2:	2b00      	cmp	r3, #0
    3bd4:	f000 80fe 	beq.w	3dd4 <handle_rx_okay_irq+0x2e4>
            {
                uint8_t rxed_opcode;
                rxed_opcode = data8;
    3bd8:	7a7b      	ldrb	r3, [r7, #9]
    3bda:	72fb      	strb	r3, [r7, #11]
                if(rxed_opcode == g_comblk_cmd_opcode)
    3bdc:	f240 1338 	movw	r3, #312	; 0x138
    3be0:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3be4:	781b      	ldrb	r3, [r3, #0]
    3be6:	b2db      	uxtb	r3, r3
    3be8:	7afa      	ldrb	r2, [r7, #11]
    3bea:	429a      	cmp	r2, r3
    3bec:	d12a      	bne.n	3c44 <handle_rx_okay_irq+0x154>
                {
                    g_comblk_response_idx = 0u;
    3bee:	f240 1352 	movw	r3, #338	; 0x152
    3bf2:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3bf6:	f04f 0200 	mov.w	r2, #0
    3bfa:	801a      	strh	r2, [r3, #0]
                    g_comblk_p_response[g_comblk_response_idx] = rxed_opcode;
    3bfc:	f240 134c 	movw	r3, #332	; 0x14c
    3c00:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3c04:	681a      	ldr	r2, [r3, #0]
    3c06:	f240 1352 	movw	r3, #338	; 0x152
    3c0a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3c0e:	881b      	ldrh	r3, [r3, #0]
    3c10:	b29b      	uxth	r3, r3
    3c12:	4413      	add	r3, r2
    3c14:	7afa      	ldrb	r2, [r7, #11]
    3c16:	701a      	strb	r2, [r3, #0]
                    ++g_comblk_response_idx;
    3c18:	f240 1352 	movw	r3, #338	; 0x152
    3c1c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3c20:	881b      	ldrh	r3, [r3, #0]
    3c22:	b29b      	uxth	r3, r3
    3c24:	f103 0301 	add.w	r3, r3, #1
    3c28:	b29a      	uxth	r2, r3
    3c2a:	f240 1352 	movw	r3, #338	; 0x152
    3c2e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3c32:	801a      	strh	r2, [r3, #0]
                    g_comblk_state = COMBLK_RX_RESPONSE;
    3c34:	f240 135d 	movw	r3, #349	; 0x15d
    3c38:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3c3c:	f04f 0204 	mov.w	r2, #4
    3c40:	701a      	strb	r2, [r3, #0]
                else
                {
                    process_sys_ctrl_command(rxed_opcode);
                }
            }
        break;
    3c42:	e0cc      	b.n	3dde <handle_rx_okay_irq+0x2ee>
                    ++g_comblk_response_idx;
                    g_comblk_state = COMBLK_RX_RESPONSE;
                }
                else
                {
                    process_sys_ctrl_command(rxed_opcode);
    3c44:	7afb      	ldrb	r3, [r7, #11]
    3c46:	4618      	mov	r0, r3
    3c48:	f000 f990 	bl	3f6c <process_sys_ctrl_command>
                }
            }
        break;
    3c4c:	e0c7      	b.n	3dde <handle_rx_okay_irq+0x2ee>
            
        case COMBLK_RX_RESPONSE:
            if(is_command)
    3c4e:	88fb      	ldrh	r3, [r7, #6]
    3c50:	2b00      	cmp	r3, #0
    3c52:	d006      	beq.n	3c62 <handle_rx_okay_irq+0x172>
            {
                uint8_t rxed_opcode;
                rxed_opcode = data8;
    3c54:	7a7b      	ldrb	r3, [r7, #9]
    3c56:	733b      	strb	r3, [r7, #12]
                process_sys_ctrl_command(rxed_opcode);
    3c58:	7b3b      	ldrb	r3, [r7, #12]
    3c5a:	4618      	mov	r0, r3
    3c5c:	f000 f986 	bl	3f6c <process_sys_ctrl_command>
                        complete_request(g_comblk_response_idx);
                        g_comblk_state = COMBLK_IDLE;
                    }
                }
            }
        break;
    3c60:	e0bd      	b.n	3dde <handle_rx_okay_irq+0x2ee>
                rxed_opcode = data8;
                process_sys_ctrl_command(rxed_opcode);
            }
            else
            {
                if( g_comblk_p_response[g_comblk_response_idx-1] == POR_DIGEST_ERROR_OPCODE)
    3c62:	f240 134c 	movw	r3, #332	; 0x14c
    3c66:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3c6a:	681a      	ldr	r2, [r3, #0]
    3c6c:	f240 1352 	movw	r3, #338	; 0x152
    3c70:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3c74:	881b      	ldrh	r3, [r3, #0]
    3c76:	b29b      	uxth	r3, r3
    3c78:	f103 33ff 	add.w	r3, r3, #4294967295
    3c7c:	4413      	add	r3, r2
    3c7e:	781b      	ldrb	r3, [r3, #0]
    3c80:	2bf1      	cmp	r3, #241	; 0xf1
    3c82:	d127      	bne.n	3cd4 <handle_rx_okay_irq+0x1e4>
                {
                    g_comblk_p_response[g_comblk_response_idx] = data8;
    3c84:	f240 134c 	movw	r3, #332	; 0x14c
    3c88:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3c8c:	681a      	ldr	r2, [r3, #0]
    3c8e:	f240 1352 	movw	r3, #338	; 0x152
    3c92:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3c96:	881b      	ldrh	r3, [r3, #0]
    3c98:	b29b      	uxth	r3, r3
    3c9a:	4413      	add	r3, r2
    3c9c:	7a7a      	ldrb	r2, [r7, #9]
    3c9e:	701a      	strb	r2, [r3, #0]
                    process_sys_ctrl_command(g_comblk_p_response[g_comblk_response_idx-1]);
    3ca0:	f240 134c 	movw	r3, #332	; 0x14c
    3ca4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3ca8:	681a      	ldr	r2, [r3, #0]
    3caa:	f240 1352 	movw	r3, #338	; 0x152
    3cae:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3cb2:	881b      	ldrh	r3, [r3, #0]
    3cb4:	b29b      	uxth	r3, r3
    3cb6:	f103 33ff 	add.w	r3, r3, #4294967295
    3cba:	4413      	add	r3, r2
    3cbc:	781b      	ldrb	r3, [r3, #0]
    3cbe:	4618      	mov	r0, r3
    3cc0:	f000 f954 	bl	3f6c <process_sys_ctrl_command>
                    g_comblk_state = COMBLK_IDLE;
    3cc4:	f240 135d 	movw	r3, #349	; 0x15d
    3cc8:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3ccc:	f04f 0200 	mov.w	r2, #0
    3cd0:	701a      	strb	r2, [r3, #0]
                        complete_request(g_comblk_response_idx);
                        g_comblk_state = COMBLK_IDLE;
                    }
                }
            }
        break;
    3cd2:	e084      	b.n	3dde <handle_rx_okay_irq+0x2ee>
                    process_sys_ctrl_command(g_comblk_p_response[g_comblk_response_idx-1]);
                    g_comblk_state = COMBLK_IDLE;
                }
                else
                {
                    if(g_comblk_response_idx < g_comblk_response_size)
    3cd4:	f240 1352 	movw	r3, #338	; 0x152
    3cd8:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3cdc:	881b      	ldrh	r3, [r3, #0]
    3cde:	b29a      	uxth	r2, r3
    3ce0:	f240 1350 	movw	r3, #336	; 0x150
    3ce4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3ce8:	881b      	ldrh	r3, [r3, #0]
    3cea:	429a      	cmp	r2, r3
    3cec:	d21d      	bcs.n	3d2a <handle_rx_okay_irq+0x23a>
                    {
                        uint8_t rxed_data;
                        
                        rxed_data = data8;
    3cee:	7a7b      	ldrb	r3, [r7, #9]
    3cf0:	737b      	strb	r3, [r7, #13]
                        g_comblk_p_response[g_comblk_response_idx] = rxed_data;
    3cf2:	f240 134c 	movw	r3, #332	; 0x14c
    3cf6:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3cfa:	681a      	ldr	r2, [r3, #0]
    3cfc:	f240 1352 	movw	r3, #338	; 0x152
    3d00:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3d04:	881b      	ldrh	r3, [r3, #0]
    3d06:	b29b      	uxth	r3, r3
    3d08:	4413      	add	r3, r2
    3d0a:	7b7a      	ldrb	r2, [r7, #13]
    3d0c:	701a      	strb	r2, [r3, #0]
                        ++g_comblk_response_idx;
    3d0e:	f240 1352 	movw	r3, #338	; 0x152
    3d12:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3d16:	881b      	ldrh	r3, [r3, #0]
    3d18:	b29b      	uxth	r3, r3
    3d1a:	f103 0301 	add.w	r3, r3, #1
    3d1e:	b29a      	uxth	r2, r3
    3d20:	f240 1352 	movw	r3, #338	; 0x152
    3d24:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3d28:	801a      	strh	r2, [r3, #0]
                    }
                    
                    if(g_comblk_response_idx == g_comblk_response_size)
    3d2a:	f240 1352 	movw	r3, #338	; 0x152
    3d2e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3d32:	881b      	ldrh	r3, [r3, #0]
    3d34:	b29a      	uxth	r2, r3
    3d36:	f240 1350 	movw	r3, #336	; 0x150
    3d3a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3d3e:	881b      	ldrh	r3, [r3, #0]
    3d40:	429a      	cmp	r2, r3
    3d42:	d149      	bne.n	3dd8 <handle_rx_okay_irq+0x2e8>
                    {
                        complete_request(g_comblk_response_idx);
    3d44:	f240 1352 	movw	r3, #338	; 0x152
    3d48:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3d4c:	881b      	ldrh	r3, [r3, #0]
    3d4e:	b29b      	uxth	r3, r3
    3d50:	4618      	mov	r0, r3
    3d52:	f000 f849 	bl	3de8 <complete_request>
                        g_comblk_state = COMBLK_IDLE;
    3d56:	f240 135d 	movw	r3, #349	; 0x15d
    3d5a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3d5e:	f04f 0200 	mov.w	r2, #0
    3d62:	701a      	strb	r2, [r3, #0]
                    }
                }
            }
        break;
    3d64:	e03b      	b.n	3dde <handle_rx_okay_irq+0x2ee>
         * The RCV_OKAY interrupt should NOT be enabled for states
         * COMBLK_IDLE, COMBLK_TX_CMD and COMBLK_TX_DATA.
         */
        case COMBLK_TX_PAGED_DATA:
            /* This is needed because when there is an error, we need to terminate loading the data */
            if(!is_command)
    3d66:	88fb      	ldrh	r3, [r7, #6]
    3d68:	2b00      	cmp	r3, #0
    3d6a:	d114      	bne.n	3d96 <handle_rx_okay_irq+0x2a6>
            {
                g_comblk_p_response[1] = data8;
    3d6c:	f240 134c 	movw	r3, #332	; 0x14c
    3d70:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3d74:	681b      	ldr	r3, [r3, #0]
    3d76:	f103 0301 	add.w	r3, r3, #1
    3d7a:	7a7a      	ldrb	r2, [r7, #9]
    3d7c:	701a      	strb	r2, [r3, #0]
                complete_request(2u);
    3d7e:	f04f 0002 	mov.w	r0, #2
    3d82:	f000 f831 	bl	3de8 <complete_request>
                g_comblk_state = COMBLK_IDLE;
    3d86:	f240 135d 	movw	r3, #349	; 0x15d
    3d8a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3d8e:	f04f 0200 	mov.w	r2, #0
    3d92:	701a      	strb	r2, [r3, #0]
            {
                uint8_t rxed_opcode;
                rxed_opcode = data8;
                process_sys_ctrl_command(rxed_opcode);
            }
        break;
    3d94:	e023      	b.n	3dde <handle_rx_okay_irq+0x2ee>
                g_comblk_state = COMBLK_IDLE;
            }
            else
            {
                uint8_t rxed_opcode;
                rxed_opcode = data8;
    3d96:	7a7b      	ldrb	r3, [r7, #9]
    3d98:	73bb      	strb	r3, [r7, #14]
                process_sys_ctrl_command(rxed_opcode);
    3d9a:	7bbb      	ldrb	r3, [r7, #14]
    3d9c:	4618      	mov	r0, r3
    3d9e:	f000 f8e5 	bl	3f6c <process_sys_ctrl_command>
            }
        break;
    3da2:	e01c      	b.n	3dde <handle_rx_okay_irq+0x2ee>
        
        case COMBLK_TX_CMD:
            /* Fall through */
        case COMBLK_TX_DATA:
            /* Fall through */
            if(is_command)
    3da4:	88fb      	ldrh	r3, [r7, #6]
    3da6:	2b00      	cmp	r3, #0
    3da8:	d018      	beq.n	3ddc <handle_rx_okay_irq+0x2ec>
            {
                uint8_t rxed_opcode;
                rxed_opcode = data8;
    3daa:	7a7b      	ldrb	r3, [r7, #9]
    3dac:	73fb      	strb	r3, [r7, #15]
                process_sys_ctrl_command(rxed_opcode);
    3dae:	7bfb      	ldrb	r3, [r7, #15]
    3db0:	4618      	mov	r0, r3
    3db2:	f000 f8db 	bl	3f6c <process_sys_ctrl_command>
            }
        break;
    3db6:	e012      	b.n	3dde <handle_rx_okay_irq+0x2ee>
        
        default:
            complete_request(0u);
    3db8:	f04f 0000 	mov.w	r0, #0
    3dbc:	f000 f814 	bl	3de8 <complete_request>
            g_comblk_state = COMBLK_IDLE;
    3dc0:	f240 135d 	movw	r3, #349	; 0x15d
    3dc4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3dc8:	f04f 0200 	mov.w	r2, #0
    3dcc:	701a      	strb	r2, [r3, #0]
    3dce:	e006      	b.n	3dde <handle_rx_okay_irq+0x2ee>
                    g_comblk_response_idx++;
                    g_comblk_p_response[g_comblk_response_idx] = 0x00u;                
                    g_comblk_state = COMBLK_RX_RESPONSE;
                }
            }
        break;
    3dd0:	bf00      	nop
    3dd2:	e004      	b.n	3dde <handle_rx_okay_irq+0x2ee>
                else
                {
                    process_sys_ctrl_command(rxed_opcode);
                }
            }
        break;
    3dd4:	bf00      	nop
    3dd6:	e002      	b.n	3dde <handle_rx_okay_irq+0x2ee>
                        complete_request(g_comblk_response_idx);
                        g_comblk_state = COMBLK_IDLE;
                    }
                }
            }
        break;
    3dd8:	bf00      	nop
    3dda:	e000      	b.n	3dde <handle_rx_okay_irq+0x2ee>
            {
                uint8_t rxed_opcode;
                rxed_opcode = data8;
                process_sys_ctrl_command(rxed_opcode);
            }
        break;
    3ddc:	bf00      	nop
        default:
            complete_request(0u);
            g_comblk_state = COMBLK_IDLE;
        break;
    }
}
    3dde:	f107 0710 	add.w	r7, r7, #16
    3de2:	46bd      	mov	sp, r7
    3de4:	bd80      	pop	{r7, pc}
    3de6:	bf00      	nop

00003de8 <complete_request>:
 */
static void complete_request
(
    uint16_t response_length
)
{
    3de8:	b580      	push	{r7, lr}
    3dea:	b082      	sub	sp, #8
    3dec:	af00      	add	r7, sp, #0
    3dee:	4603      	mov	r3, r0
    3df0:	80fb      	strh	r3, [r7, #6]
    if(g_comblk_completion_handler != 0)
    3df2:	f240 1354 	movw	r3, #340	; 0x154
    3df6:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3dfa:	681b      	ldr	r3, [r3, #0]
    3dfc:	2b00      	cmp	r3, #0
    3dfe:	d01b      	beq.n	3e38 <complete_request+0x50>
    {
        g_comblk_completion_handler(g_comblk_p_response, response_length);
    3e00:	f240 1354 	movw	r3, #340	; 0x154
    3e04:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3e08:	681a      	ldr	r2, [r3, #0]
    3e0a:	f240 134c 	movw	r3, #332	; 0x14c
    3e0e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3e12:	6819      	ldr	r1, [r3, #0]
    3e14:	88fb      	ldrh	r3, [r7, #6]
    3e16:	4608      	mov	r0, r1
    3e18:	4619      	mov	r1, r3
    3e1a:	4790      	blx	r2
        g_comblk_completion_handler = 0;
    3e1c:	f240 1354 	movw	r3, #340	; 0x154
    3e20:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3e24:	f04f 0200 	mov.w	r2, #0
    3e28:	601a      	str	r2, [r3, #0]
        g_request_in_progress = 0u;
    3e2a:	f240 135c 	movw	r3, #348	; 0x15c
    3e2e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3e32:	f04f 0200 	mov.w	r2, #0
    3e36:	701a      	strb	r2, [r3, #0]
    }
}
    3e38:	f107 0708 	add.w	r7, r7, #8
    3e3c:	46bd      	mov	sp, r7
    3e3e:	bd80      	pop	{r7, pc}

00003e40 <abort_current_cmd>:

/*==============================================================================
 *
 */
static void abort_current_cmd(void)
{
    3e40:	b580      	push	{r7, lr}
    3e42:	b082      	sub	sp, #8
    3e44:	af00      	add	r7, sp, #0
    if(g_request_in_progress)
    3e46:	f240 135c 	movw	r3, #348	; 0x15c
    3e4a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3e4e:	781b      	ldrb	r3, [r3, #0]
    3e50:	2b00      	cmp	r3, #0
    3e52:	d01f      	beq.n	3e94 <abort_current_cmd+0x54>
        
        /*
         * Call completion handler just in case we are in a multi threaded system
         * to avoid a task lockup.
         */
        complete_request(g_comblk_response_idx);
    3e54:	f240 1352 	movw	r3, #338	; 0x152
    3e58:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3e5c:	881b      	ldrh	r3, [r3, #0]
    3e5e:	b29b      	uxth	r3, r3
    3e60:	4618      	mov	r0, r3
    3e62:	f7ff ffc1 	bl	3de8 <complete_request>
        
        /*
         * Flush the FIFOs
         */
        COMBLK->CONTROL |= CR_FLUSHOUT_MASK;
    3e66:	f246 0300 	movw	r3, #24576	; 0x6000
    3e6a:	f2c4 0301 	movt	r3, #16385	; 0x4001
    3e6e:	f246 0200 	movw	r2, #24576	; 0x6000
    3e72:	f2c4 0201 	movt	r2, #16385	; 0x4001
    3e76:	6812      	ldr	r2, [r2, #0]
    3e78:	f042 0201 	orr.w	r2, r2, #1
    3e7c:	601a      	str	r2, [r3, #0]
        do {
            flush_in_progress = COMBLK->CONTROL & CR_FLUSHOUT_MASK;
    3e7e:	f246 0300 	movw	r3, #24576	; 0x6000
    3e82:	f2c4 0301 	movt	r3, #16385	; 0x4001
    3e86:	681b      	ldr	r3, [r3, #0]
    3e88:	f003 0301 	and.w	r3, r3, #1
    3e8c:	607b      	str	r3, [r7, #4]
        } while(flush_in_progress);
    3e8e:	687b      	ldr	r3, [r7, #4]
    3e90:	2b00      	cmp	r3, #0
    3e92:	d1f4      	bne.n	3e7e <abort_current_cmd+0x3e>
    }
}
    3e94:	f107 0708 	add.w	r7, r7, #8
    3e98:	46bd      	mov	sp, r7
    3e9a:	bd80      	pop	{r7, pc}

00003e9c <send_cmd_opcode>:
 */
static void send_cmd_opcode
(
    uint8_t opcode
)
{
    3e9c:	b480      	push	{r7}
    3e9e:	b085      	sub	sp, #20
    3ea0:	af00      	add	r7, sp, #0
    3ea2:	4603      	mov	r3, r0
    3ea4:	71fb      	strb	r3, [r7, #7]
    uint32_t tx_okay;
    
    /* Set transmit FIFO to transfer bytes. */
    COMBLK->CONTROL &= ~CR_SIZETX_MASK;
    3ea6:	f246 0300 	movw	r3, #24576	; 0x6000
    3eaa:	f2c4 0301 	movt	r3, #16385	; 0x4001
    3eae:	f246 0200 	movw	r2, #24576	; 0x6000
    3eb2:	f2c4 0201 	movt	r2, #16385	; 0x4001
    3eb6:	6812      	ldr	r2, [r2, #0]
    3eb8:	f022 0204 	bic.w	r2, r2, #4
    3ebc:	601a      	str	r2, [r3, #0]
    
    /* Wait for space to become available in Tx FIFO. */
    do {
        tx_okay = COMBLK->STATUS & TXTOKAY_MASK;
    3ebe:	f246 0300 	movw	r3, #24576	; 0x6000
    3ec2:	f2c4 0301 	movt	r3, #16385	; 0x4001
    3ec6:	685b      	ldr	r3, [r3, #4]
    3ec8:	f003 0301 	and.w	r3, r3, #1
    3ecc:	60fb      	str	r3, [r7, #12]
    } while(0u == tx_okay);
    3ece:	68fb      	ldr	r3, [r7, #12]
    3ed0:	2b00      	cmp	r3, #0
    3ed2:	d0f4      	beq.n	3ebe <send_cmd_opcode+0x22>
    
    /* Send command opcode. */
    COMBLK->FRAME_START8 = opcode;
    3ed4:	f246 0300 	movw	r3, #24576	; 0x6000
    3ed8:	f2c4 0301 	movt	r3, #16385	; 0x4001
    3edc:	79fa      	ldrb	r2, [r7, #7]
    3ede:	619a      	str	r2, [r3, #24]
}
    3ee0:	f107 0714 	add.w	r7, r7, #20
    3ee4:	46bd      	mov	sp, r7
    3ee6:	bc80      	pop	{r7}
    3ee8:	4770      	bx	lr
    3eea:	bf00      	nop

00003eec <fill_tx_fifo>:
static uint32_t fill_tx_fifo
(
    const uint8_t * p_cmd,
    uint32_t cmd_size
)
{
    3eec:	b480      	push	{r7}
    3eee:	b085      	sub	sp, #20
    3ef0:	af00      	add	r7, sp, #0
    3ef2:	6078      	str	r0, [r7, #4]
    3ef4:	6039      	str	r1, [r7, #0]
    volatile uint32_t tx_okay;
    uint32_t size_sent;

    /* Set transmit FIFO to transfer bytes. */
    COMBLK->CONTROL &= ~CR_SIZETX_MASK;
    3ef6:	f246 0300 	movw	r3, #24576	; 0x6000
    3efa:	f2c4 0301 	movt	r3, #16385	; 0x4001
    3efe:	f246 0200 	movw	r2, #24576	; 0x6000
    3f02:	f2c4 0201 	movt	r2, #16385	; 0x4001
    3f06:	6812      	ldr	r2, [r2, #0]
    3f08:	f022 0204 	bic.w	r2, r2, #4
    3f0c:	601a      	str	r2, [r3, #0]
    
    size_sent = 0u;
    3f0e:	f04f 0300 	mov.w	r3, #0
    3f12:	60fb      	str	r3, [r7, #12]
    tx_okay = COMBLK->STATUS & TXTOKAY_MASK;
    3f14:	f246 0300 	movw	r3, #24576	; 0x6000
    3f18:	f2c4 0301 	movt	r3, #16385	; 0x4001
    3f1c:	685b      	ldr	r3, [r3, #4]
    3f1e:	f003 0301 	and.w	r3, r3, #1
    3f22:	60bb      	str	r3, [r7, #8]
    while((tx_okay != 0u) && (size_sent < cmd_size))
    3f24:	e014      	b.n	3f50 <fill_tx_fifo+0x64>
    {
        COMBLK->DATA8 = p_cmd[size_sent];
    3f26:	f246 0300 	movw	r3, #24576	; 0x6000
    3f2a:	f2c4 0301 	movt	r3, #16385	; 0x4001
    3f2e:	6879      	ldr	r1, [r7, #4]
    3f30:	68fa      	ldr	r2, [r7, #12]
    3f32:	440a      	add	r2, r1
    3f34:	7812      	ldrb	r2, [r2, #0]
    3f36:	611a      	str	r2, [r3, #16]
        ++size_sent;
    3f38:	68fb      	ldr	r3, [r7, #12]
    3f3a:	f103 0301 	add.w	r3, r3, #1
    3f3e:	60fb      	str	r3, [r7, #12]
        tx_okay = COMBLK->STATUS & TXTOKAY_MASK;
    3f40:	f246 0300 	movw	r3, #24576	; 0x6000
    3f44:	f2c4 0301 	movt	r3, #16385	; 0x4001
    3f48:	685b      	ldr	r3, [r3, #4]
    3f4a:	f003 0301 	and.w	r3, r3, #1
    3f4e:	60bb      	str	r3, [r7, #8]
    /* Set transmit FIFO to transfer bytes. */
    COMBLK->CONTROL &= ~CR_SIZETX_MASK;
    
    size_sent = 0u;
    tx_okay = COMBLK->STATUS & TXTOKAY_MASK;
    while((tx_okay != 0u) && (size_sent < cmd_size))
    3f50:	68bb      	ldr	r3, [r7, #8]
    3f52:	2b00      	cmp	r3, #0
    3f54:	d003      	beq.n	3f5e <fill_tx_fifo+0x72>
    3f56:	68fa      	ldr	r2, [r7, #12]
    3f58:	683b      	ldr	r3, [r7, #0]
    3f5a:	429a      	cmp	r2, r3
    3f5c:	d3e3      	bcc.n	3f26 <fill_tx_fifo+0x3a>
        COMBLK->DATA8 = p_cmd[size_sent];
        ++size_sent;
        tx_okay = COMBLK->STATUS & TXTOKAY_MASK;
    }
    
    return size_sent;
    3f5e:	68fb      	ldr	r3, [r7, #12]
}
    3f60:	4618      	mov	r0, r3
    3f62:	f107 0714 	add.w	r7, r7, #20
    3f66:	46bd      	mov	sp, r7
    3f68:	bc80      	pop	{r7}
    3f6a:	4770      	bx	lr

00003f6c <process_sys_ctrl_command>:

/*==============================================================================
 *
 */
static void process_sys_ctrl_command(uint8_t cmd_opcode)
{
    3f6c:	b580      	push	{r7, lr}
    3f6e:	b082      	sub	sp, #8
    3f70:	af00      	add	r7, sp, #0
    3f72:	4603      	mov	r3, r0
    3f74:	71fb      	strb	r3, [r7, #7]
    if(g_async_event_handler != 0)
    3f76:	f240 1360 	movw	r3, #352	; 0x160
    3f7a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3f7e:	681b      	ldr	r3, [r3, #0]
    3f80:	2b00      	cmp	r3, #0
    3f82:	d007      	beq.n	3f94 <process_sys_ctrl_command+0x28>
    {
        g_async_event_handler(cmd_opcode);
    3f84:	f240 1360 	movw	r3, #352	; 0x160
    3f88:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3f8c:	681b      	ldr	r3, [r3, #0]
    3f8e:	79fa      	ldrb	r2, [r7, #7]
    3f90:	4610      	mov	r0, r2
    3f92:	4798      	blx	r3
    }
}
    3f94:	f107 0708 	add.w	r7, r7, #8
    3f98:	46bd      	mov	sp, r7
    3f9a:	bd80      	pop	{r7, pc}

00003f9c <MSS_SYS_init>:

/*==============================================================================
 * See mss_sys_services.h for details.
 */
void MSS_SYS_init(sys_serv_async_event_handler_t event_handler)
{   
    3f9c:	b580      	push	{r7, lr}
    3f9e:	b082      	sub	sp, #8
    3fa0:	af00      	add	r7, sp, #0
    3fa2:	6078      	str	r0, [r7, #4]
    g_event_handler = event_handler;
    3fa4:	f240 1368 	movw	r3, #360	; 0x168
    3fa8:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3fac:	687a      	ldr	r2, [r7, #4]
    3fae:	601a      	str	r2, [r3, #0]
    g_last_response_length = 0u;
    3fb0:	f240 1366 	movw	r3, #358	; 0x166
    3fb4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3fb8:	f04f 0200 	mov.w	r2, #0
    3fbc:	801a      	strh	r2, [r3, #0]
    g_request_in_progress = 0u;
    3fbe:	f240 1364 	movw	r3, #356	; 0x164
    3fc2:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3fc6:	f04f 0200 	mov.w	r2, #0
    3fca:	701a      	strb	r2, [r3, #0]
    
    /*
     * Set a default good value for g_initial_mssddr_facc1_cr used to control
     * the clock dividers coming in and out of Flash*Freeze.
     */
    g_initial_mssddr_facc1_cr = SYSREG->MSSDDR_FACC1_CR;
    3fcc:	f248 0300 	movw	r3, #32768	; 0x8000
    3fd0:	f2c4 0303 	movt	r3, #16387	; 0x4003
    3fd4:	f8d3 2098 	ldr.w	r2, [r3, #152]	; 0x98
    3fd8:	f240 1370 	movw	r3, #368	; 0x170
    3fdc:	f2c2 0300 	movt	r3, #8192	; 0x2000
    3fe0:	601a      	str	r2, [r3, #0]
    
    /*
     * Initialize the COMBLK used to communicate with the System Controller.
     */
    MSS_COMBLK_init(asynchronous_event_handler, g_response);
    3fe2:	f244 0001 	movw	r0, #16385	; 0x4001
    3fe6:	f2c0 0000 	movt	r0, #0
    3fea:	f240 116c 	movw	r1, #364	; 0x16c
    3fee:	f2c2 0100 	movt	r1, #8192	; 0x2000
    3ff2:	f7ff f8fb 	bl	31ec <MSS_COMBLK_init>
}
    3ff6:	f107 0708 	add.w	r7, r7, #8
    3ffa:	46bd      	mov	sp, r7
    3ffc:	bd80      	pop	{r7, pc}
    3ffe:	bf00      	nop

00004000 <asynchronous_event_handler>:
#define TAMPER_HARDWARE_MONITOR_ERROR_OPCODE_RANGE_MAX   0xB7u

#define FACC_GLMUX_SEL_MASK         0x00001000u
#define DELAY_MORE_THAN_10US        5000U
static void asynchronous_event_handler(uint8_t event_opcode)
{
    4000:	b580      	push	{r7, lr}
    4002:	b088      	sub	sp, #32
    4004:	af00      	add	r7, sp, #0
    4006:	4603      	mov	r3, r0
    4008:	71fb      	strb	r3, [r7, #7]
    if (event_opcode == FLASH_FREEZE_SHUTDOWN_OPCODE)
    400a:	79fb      	ldrb	r3, [r7, #7]
    400c:	2be0      	cmp	r3, #224	; 0xe0
    400e:	d13f      	bne.n	4090 <asynchronous_event_handler+0x90>
    {
        uint32_t running_on_standby_clock;
        volatile uint32_t timeout;
        const uint32_t apb_divisors_mask = 0x00000EFCU;
    4010:	f640 63fc 	movw	r3, #3836	; 0xefc
    4014:	61bb      	str	r3, [r7, #24]
        /*
         * Wait for the System Controller to switch the system's clock
         * from the main clock to the  standby clock. This should take place
         * within 10us of receiving the shut-down event.
         */
        timeout = DELAY_MORE_THAN_10US;
    4016:	f241 3388 	movw	r3, #5000	; 0x1388
    401a:	613b      	str	r3, [r7, #16]
        do
        {
            running_on_standby_clock = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK;
    401c:	f248 0300 	movw	r3, #32768	; 0x8000
    4020:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4024:	f8d3 3098 	ldr.w	r3, [r3, #152]	; 0x98
    4028:	f403 5380 	and.w	r3, r3, #4096	; 0x1000
    402c:	617b      	str	r3, [r7, #20]
            --timeout;
    402e:	693b      	ldr	r3, [r7, #16]
    4030:	f103 33ff 	add.w	r3, r3, #4294967295
    4034:	613b      	str	r3, [r7, #16]
        }
        while ((running_on_standby_clock == 0U) && (timeout != 0U));
    4036:	697b      	ldr	r3, [r7, #20]
    4038:	2b00      	cmp	r3, #0
    403a:	d102      	bne.n	4042 <asynchronous_event_handler+0x42>
    403c:	693b      	ldr	r3, [r7, #16]
    403e:	2b00      	cmp	r3, #0
    4040:	d1ec      	bne.n	401c <asynchronous_event_handler+0x1c>
         * Set the clock divisors to zero in order to set the AHB
         * to APB bridge's clock ratio between the AHB and APB busses to 1.
         * This is required to ensure correct bus transactions to the APB
         * peripherals while operating from the standby clock.
         */
        SYSREG->MSSDDR_FACC1_CR &= ~apb_divisors_mask;
    4042:	f248 0300 	movw	r3, #32768	; 0x8000
    4046:	f2c4 0303 	movt	r3, #16387	; 0x4003
    404a:	f248 0200 	movw	r2, #32768	; 0x8000
    404e:	f2c4 0203 	movt	r2, #16387	; 0x4003
    4052:	f8d2 1098 	ldr.w	r1, [r2, #152]	; 0x98
    4056:	69ba      	ldr	r2, [r7, #24]
    4058:	ea6f 0202 	mvn.w	r2, r2
    405c:	ea01 0202 	and.w	r2, r1, r2
    4060:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98
        
        /* Call the user's event handler. */
        if(g_event_handler != 0)
    4064:	f240 1368 	movw	r3, #360	; 0x168
    4068:	f2c2 0300 	movt	r3, #8192	; 0x2000
    406c:	681b      	ldr	r3, [r3, #0]
    406e:	2b00      	cmp	r3, #0
    4070:	d071      	beq.n	4156 <asynchronous_event_handler+0x156>
        {
            g_event_handler(event_opcode, g_response[1]);
    4072:	f240 1368 	movw	r3, #360	; 0x168
    4076:	f2c2 0300 	movt	r3, #8192	; 0x2000
    407a:	681a      	ldr	r2, [r3, #0]
    407c:	f240 136c 	movw	r3, #364	; 0x16c
    4080:	f2c2 0300 	movt	r3, #8192	; 0x2000
    4084:	785b      	ldrb	r3, [r3, #1]
    4086:	79f9      	ldrb	r1, [r7, #7]
    4088:	4608      	mov	r0, r1
    408a:	4619      	mov	r1, r3
    408c:	4790      	blx	r2
    408e:	e065      	b.n	415c <asynchronous_event_handler+0x15c>
        }
    }
    else if (event_opcode == FLASH_FREEZE_EXIT_OPCODE)
    4090:	79fb      	ldrb	r3, [r7, #7]
    4092:	2be1      	cmp	r3, #225	; 0xe1
    4094:	d136      	bne.n	4104 <asynchronous_event_handler+0x104>
        /*
         * Wait for the System Controller to switch the system's clock
         * from the standby clock to the main clock. This should take place
         * within 10us of receiving the shut-down event.
         */
        timeout = DELAY_MORE_THAN_10US;
    4096:	f241 3388 	movw	r3, #5000	; 0x1388
    409a:	60fb      	str	r3, [r7, #12]
        do
        {
            running_on_standby_clock = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK;
    409c:	f248 0300 	movw	r3, #32768	; 0x8000
    40a0:	f2c4 0303 	movt	r3, #16387	; 0x4003
    40a4:	f8d3 3098 	ldr.w	r3, [r3, #152]	; 0x98
    40a8:	f403 5380 	and.w	r3, r3, #4096	; 0x1000
    40ac:	61fb      	str	r3, [r7, #28]
            --timeout;
    40ae:	68fb      	ldr	r3, [r7, #12]
    40b0:	f103 33ff 	add.w	r3, r3, #4294967295
    40b4:	60fb      	str	r3, [r7, #12]
        }
        while ((running_on_standby_clock != 0U) && (timeout != 0U));
    40b6:	69fb      	ldr	r3, [r7, #28]
    40b8:	2b00      	cmp	r3, #0
    40ba:	d002      	beq.n	40c2 <asynchronous_event_handler+0xc2>
    40bc:	68fb      	ldr	r3, [r7, #12]
    40be:	2b00      	cmp	r3, #0
    40c0:	d1ec      	bne.n	409c <asynchronous_event_handler+0x9c>
        
        /* Restore the MSS clock dividers to their normal operations value. */
        SYSREG->MSSDDR_FACC1_CR = g_initial_mssddr_facc1_cr;
    40c2:	f248 0300 	movw	r3, #32768	; 0x8000
    40c6:	f2c4 0303 	movt	r3, #16387	; 0x4003
    40ca:	f240 1270 	movw	r2, #368	; 0x170
    40ce:	f2c2 0200 	movt	r2, #8192	; 0x2000
    40d2:	6812      	ldr	r2, [r2, #0]
    40d4:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98
        
        if(g_event_handler != 0)
    40d8:	f240 1368 	movw	r3, #360	; 0x168
    40dc:	f2c2 0300 	movt	r3, #8192	; 0x2000
    40e0:	681b      	ldr	r3, [r3, #0]
    40e2:	2b00      	cmp	r3, #0
    40e4:	d039      	beq.n	415a <asynchronous_event_handler+0x15a>
        {
            /* Call the user's event handler. */
            g_event_handler(event_opcode, g_response[1]);
    40e6:	f240 1368 	movw	r3, #360	; 0x168
    40ea:	f2c2 0300 	movt	r3, #8192	; 0x2000
    40ee:	681a      	ldr	r2, [r3, #0]
    40f0:	f240 136c 	movw	r3, #364	; 0x16c
    40f4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    40f8:	785b      	ldrb	r3, [r3, #1]
    40fa:	79f9      	ldrb	r1, [r7, #7]
    40fc:	4608      	mov	r0, r1
    40fe:	4619      	mov	r1, r3
    4100:	4790      	blx	r2
    4102:	e02b      	b.n	415c <asynchronous_event_handler+0x15c>
        }
    }
    else
    {
        if ((event_opcode == POR_DIGEST_ERROR_OPCODE) || \
    4104:	79fb      	ldrb	r3, [r7, #7]
    4106:	2bf1      	cmp	r3, #241	; 0xf1
    4108:	d00f      	beq.n	412a <asynchronous_event_handler+0x12a>
            ((event_opcode >= TAMPER_ATTEMPT_DETECT_OPCODE_RANGE_MIN) && \
    410a:	79fb      	ldrb	r3, [r7, #7]
            g_event_handler(event_opcode, g_response[1]);
        }
    }
    else
    {
        if ((event_opcode == POR_DIGEST_ERROR_OPCODE) || \
    410c:	b25b      	sxtb	r3, r3
    410e:	2b00      	cmp	r3, #0
    4110:	da02      	bge.n	4118 <asynchronous_event_handler+0x118>
    4112:	79fb      	ldrb	r3, [r7, #7]
    4114:	2b9f      	cmp	r3, #159	; 0x9f
    4116:	d908      	bls.n	412a <asynchronous_event_handler+0x12a>
    4118:	79fb      	ldrb	r3, [r7, #7]
    411a:	2ba0      	cmp	r3, #160	; 0xa0
    411c:	d005      	beq.n	412a <asynchronous_event_handler+0x12a>
    411e:	79fb      	ldrb	r3, [r7, #7]
    4120:	2bb0      	cmp	r3, #176	; 0xb0
    4122:	d91b      	bls.n	415c <asynchronous_event_handler+0x15c>
    4124:	79fb      	ldrb	r3, [r7, #7]
    4126:	2bb7      	cmp	r3, #183	; 0xb7
    4128:	d818      	bhi.n	415c <asynchronous_event_handler+0x15c>
            /* 
             * Inform to the application that new asynchronous message is received, 
             * only if application call-back function is registered during 
             * initialization. 
             */
            if(g_event_handler != 0)
    412a:	f240 1368 	movw	r3, #360	; 0x168
    412e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    4132:	681b      	ldr	r3, [r3, #0]
    4134:	2b00      	cmp	r3, #0
    4136:	d011      	beq.n	415c <asynchronous_event_handler+0x15c>
            {
                /* Call the user's event handler. */
                g_event_handler(event_opcode, g_response[1]);
    4138:	f240 1368 	movw	r3, #360	; 0x168
    413c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    4140:	681a      	ldr	r2, [r3, #0]
    4142:	f240 136c 	movw	r3, #364	; 0x16c
    4146:	f2c2 0300 	movt	r3, #8192	; 0x2000
    414a:	785b      	ldrb	r3, [r3, #1]
    414c:	79f9      	ldrb	r1, [r7, #7]
    414e:	4608      	mov	r0, r1
    4150:	4619      	mov	r1, r3
    4152:	4790      	blx	r2
    4154:	e002      	b.n	415c <asynchronous_event_handler+0x15c>
        SYSREG->MSSDDR_FACC1_CR &= ~apb_divisors_mask;
        
        /* Call the user's event handler. */
        if(g_event_handler != 0)
        {
            g_event_handler(event_opcode, g_response[1]);
    4156:	bf00      	nop
    4158:	e000      	b.n	415c <asynchronous_event_handler+0x15c>
        SYSREG->MSSDDR_FACC1_CR = g_initial_mssddr_facc1_cr;
        
        if(g_event_handler != 0)
        {
            /* Call the user's event handler. */
            g_event_handler(event_opcode, g_response[1]);
    415a:	bf00      	nop
                /* Call the user's event handler. */
                g_event_handler(event_opcode, g_response[1]);
            }
        }
    }
}
    415c:	f107 0720 	add.w	r7, r7, #32
    4160:	46bd      	mov	sp, r7
    4162:	bd80      	pop	{r7, pc}

00004164 <MSS_SYS_get_serial_number>:
 */
uint8_t MSS_SYS_get_serial_number
(
    uint8_t * p_serial_number
)
{
    4164:	b580      	push	{r7, lr}
    4166:	b084      	sub	sp, #16
    4168:	af00      	add	r7, sp, #0
    416a:	6078      	str	r0, [r7, #4]
    uint8_t response[SERIAL_NUMBER_SERV_RESP_LENGTH];
    uint8_t status;
    
    status = execute_service(SERIAL_NUMBER_REQUEST_CMD,
    416c:	f107 0308 	add.w	r3, r7, #8
    4170:	f04f 0001 	mov.w	r0, #1
    4174:	6879      	ldr	r1, [r7, #4]
    4176:	461a      	mov	r2, r3
    4178:	f04f 0306 	mov.w	r3, #6
    417c:	f001 fd96 	bl	5cac <execute_service>
    4180:	4603      	mov	r3, r0
    4182:	73fb      	strb	r3, [r7, #15]
                             p_serial_number,
                             response,
                             SERIAL_NUMBER_SERV_RESP_LENGTH);
    
    return status;
    4184:	7bfb      	ldrb	r3, [r7, #15]
}
    4186:	4618      	mov	r0, r3
    4188:	f107 0710 	add.w	r7, r7, #16
    418c:	46bd      	mov	sp, r7
    418e:	bd80      	pop	{r7, pc}

00004190 <MSS_SYS_get_user_code>:
 */
uint8_t MSS_SYS_get_user_code
(
    uint8_t * p_user_code
)
{
    4190:	b580      	push	{r7, lr}
    4192:	b084      	sub	sp, #16
    4194:	af00      	add	r7, sp, #0
    4196:	6078      	str	r0, [r7, #4]
    uint8_t response[USERCODE_SERV_RESP_LENGTH];
    uint8_t status;
    
    status = execute_service(USERCODE_REQUEST_CMD,
    4198:	f107 0308 	add.w	r3, r7, #8
    419c:	f04f 0004 	mov.w	r0, #4
    41a0:	6879      	ldr	r1, [r7, #4]
    41a2:	461a      	mov	r2, r3
    41a4:	f04f 0306 	mov.w	r3, #6
    41a8:	f001 fd80 	bl	5cac <execute_service>
    41ac:	4603      	mov	r3, r0
    41ae:	73fb      	strb	r3, [r7, #15]
                             p_user_code,
                             response,
                             USERCODE_SERV_RESP_LENGTH);
    
    return status;
    41b0:	7bfb      	ldrb	r3, [r7, #15]
}
    41b2:	4618      	mov	r0, r3
    41b4:	f107 0710 	add.w	r7, r7, #16
    41b8:	46bd      	mov	sp, r7
    41ba:	bd80      	pop	{r7, pc}

000041bc <MSS_SYS_get_design_version>:
 */
uint8_t MSS_SYS_get_design_version
(
    uint8_t * p_design_version
)
{
    41bc:	b580      	push	{r7, lr}
    41be:	b084      	sub	sp, #16
    41c0:	af00      	add	r7, sp, #0
    41c2:	6078      	str	r0, [r7, #4]
    uint8_t response[DESIGNVER_SERV_RESP_LENGTH];
    uint8_t status;
    
    status = execute_service(DESIGNVER_REQUEST_CMD,
    41c4:	f107 0308 	add.w	r3, r7, #8
    41c8:	f04f 0005 	mov.w	r0, #5
    41cc:	6879      	ldr	r1, [r7, #4]
    41ce:	461a      	mov	r2, r3
    41d0:	f04f 0306 	mov.w	r3, #6
    41d4:	f001 fd6a 	bl	5cac <execute_service>
    41d8:	4603      	mov	r3, r0
    41da:	73fb      	strb	r3, [r7, #15]
                             p_design_version,
                             response,
                             DESIGNVER_SERV_RESP_LENGTH);
    
    return status;
    41dc:	7bfb      	ldrb	r3, [r7, #15]
}
    41de:	4618      	mov	r0, r3
    41e0:	f107 0710 	add.w	r7, r7, #16
    41e4:	46bd      	mov	sp, r7
    41e6:	bd80      	pop	{r7, pc}

000041e8 <MSS_SYS_get_device_certificate>:
 */
uint8_t MSS_SYS_get_device_certificate
(
    uint8_t * p_device_certificate
)
{
    41e8:	b580      	push	{r7, lr}
    41ea:	b084      	sub	sp, #16
    41ec:	af00      	add	r7, sp, #0
    41ee:	6078      	str	r0, [r7, #4]
    uint8_t response[DEVICE_CERT_SERV_RESP_LENGTH];
    uint8_t status;
    
    status = execute_service(DEVICE_CERTIFICATE_REQUEST_CMD,
    41f0:	f107 0308 	add.w	r3, r7, #8
    41f4:	f04f 0000 	mov.w	r0, #0
    41f8:	6879      	ldr	r1, [r7, #4]
    41fa:	461a      	mov	r2, r3
    41fc:	f04f 0306 	mov.w	r3, #6
    4200:	f001 fd54 	bl	5cac <execute_service>
    4204:	4603      	mov	r3, r0
    4206:	73fb      	strb	r3, [r7, #15]
                             p_device_certificate,
                             response,
                             DEVICE_CERT_SERV_RESP_LENGTH);
    
    return status;
    4208:	7bfb      	ldrb	r3, [r7, #15]
}
    420a:	4618      	mov	r0, r3
    420c:	f107 0710 	add.w	r7, r7, #16
    4210:	46bd      	mov	sp, r7
    4212:	bd80      	pop	{r7, pc}

00004214 <MSS_SYS_get_secondary_device_certificate>:
 */
uint8_t MSS_SYS_get_secondary_device_certificate
(
    uint8_t * p_secondary_device_certificate
)
{
    4214:	b580      	push	{r7, lr}
    4216:	b084      	sub	sp, #16
    4218:	af00      	add	r7, sp, #0
    421a:	6078      	str	r0, [r7, #4]

    /*
     * The get secondary device certificate system service is not available on 
     * M2S050 rev A, rev B, rev C and rev D.
     */
    ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION);
    421c:	f248 0300 	movw	r3, #32768	; 0x8000
    4220:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4224:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    4228:	f64f 0302 	movw	r3, #63490	; 0xf802
    422c:	429a      	cmp	r2, r3
    422e:	d100      	bne.n	4232 <MSS_SYS_get_secondary_device_certificate+0x1e>
    4230:	be00      	bkpt	0x0000
    ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION);
    4232:	f248 0300 	movw	r3, #32768	; 0x8000
    4236:	f2c4 0303 	movt	r3, #16387	; 0x4003
    423a:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    423e:	f64f 0302 	movw	r3, #63490	; 0xf802
    4242:	f2c0 0301 	movt	r3, #1
    4246:	429a      	cmp	r2, r3
    4248:	d100      	bne.n	424c <MSS_SYS_get_secondary_device_certificate+0x38>
    424a:	be00      	bkpt	0x0000
    ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION);
    424c:	f248 0300 	movw	r3, #32768	; 0x8000
    4250:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4254:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    4258:	f64f 0302 	movw	r3, #63490	; 0xf802
    425c:	f2c0 0302 	movt	r3, #2
    4260:	429a      	cmp	r2, r3
    4262:	d100      	bne.n	4266 <MSS_SYS_get_secondary_device_certificate+0x52>
    4264:	be00      	bkpt	0x0000
    ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION);
    4266:	f248 0300 	movw	r3, #32768	; 0x8000
    426a:	f2c4 0303 	movt	r3, #16387	; 0x4003
    426e:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    4272:	f64f 0302 	movw	r3, #63490	; 0xf802
    4276:	f2c0 0303 	movt	r3, #3
    427a:	429a      	cmp	r2, r3
    427c:	d100      	bne.n	4280 <MSS_SYS_get_secondary_device_certificate+0x6c>
    427e:	be00      	bkpt	0x0000
    
    status = execute_service(SECONDARY_DEVICE_CERTIFICATE_REQUEST_CMD,
    4280:	f107 0308 	add.w	r3, r7, #8
    4284:	f04f 001e 	mov.w	r0, #30
    4288:	6879      	ldr	r1, [r7, #4]
    428a:	461a      	mov	r2, r3
    428c:	f04f 0306 	mov.w	r3, #6
    4290:	f001 fd0c 	bl	5cac <execute_service>
    4294:	4603      	mov	r3, r0
    4296:	73fb      	strb	r3, [r7, #15]
                             p_secondary_device_certificate,
                             response,
                             SECONDARY_DEVICE_CERT_SERV_RESP_LENGTH);
    
    return status;
    4298:	7bfb      	ldrb	r3, [r7, #15]
}
    429a:	4618      	mov	r0, r3
    429c:	f107 0710 	add.w	r7, r7, #16
    42a0:	46bd      	mov	sp, r7
    42a2:	bd80      	pop	{r7, pc}

000042a4 <MSS_SYS_flash_freeze>:

/*==============================================================================
 * See mss_sys_services.h for details.
 */
uint8_t MSS_SYS_flash_freeze(uint8_t options)
{
    42a4:	b580      	push	{r7, lr}
    42a6:	b08a      	sub	sp, #40	; 0x28
    42a8:	af04      	add	r7, sp, #16
    42aa:	4603      	mov	r3, r0
    42ac:	71fb      	strb	r3, [r7, #7]
    uint8_t response[FLASH_FREEZE_SERV_RESP_LENGTH];

    /*
     * The Flash Freeze system service is not available on M2S050 rev A and rev B.
     */
    ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION);
    42ae:	f248 0300 	movw	r3, #32768	; 0x8000
    42b2:	f2c4 0303 	movt	r3, #16387	; 0x4003
    42b6:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    42ba:	f64f 0302 	movw	r3, #63490	; 0xf802
    42be:	429a      	cmp	r2, r3
    42c0:	d100      	bne.n	42c4 <MSS_SYS_flash_freeze+0x20>
    42c2:	be00      	bkpt	0x0000
    ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION);
    42c4:	f248 0300 	movw	r3, #32768	; 0x8000
    42c8:	f2c4 0303 	movt	r3, #16387	; 0x4003
    42cc:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    42d0:	f64f 0302 	movw	r3, #63490	; 0xf802
    42d4:	f2c0 0301 	movt	r3, #1
    42d8:	429a      	cmp	r2, r3
    42da:	d100      	bne.n	42de <MSS_SYS_flash_freeze+0x3a>
    42dc:	be00      	bkpt	0x0000
    
    /*
     * Keep track of the clocks configuration before entering Flash*Freeze so
     * that it can be restored on Flash*Freeze exit.
     */
    g_initial_mssddr_facc1_cr = SYSREG->MSSDDR_FACC1_CR;
    42de:	f248 0300 	movw	r3, #32768	; 0x8000
    42e2:	f2c4 0303 	movt	r3, #16387	; 0x4003
    42e6:	f8d3 2098 	ldr.w	r2, [r3, #152]	; 0x98
    42ea:	f240 1370 	movw	r3, #368	; 0x170
    42ee:	f2c2 0300 	movt	r3, #8192	; 0x2000
    42f2:	601a      	str	r2, [r3, #0]
    
    /*
     * Enable RTC wake-up interrupt to System Controller and FPGA fabric.
     */
    SYSREG->RTC_WAKEUP_CR |= (RTC_WAKEUP_G4C_EN_MASK | RTC_WAKEUP_FAB_EN_MASK);
    42f4:	f248 0300 	movw	r3, #32768	; 0x8000
    42f8:	f2c4 0303 	movt	r3, #16387	; 0x4003
    42fc:	f248 0200 	movw	r2, #32768	; 0x8000
    4300:	f2c4 0203 	movt	r2, #16387	; 0x4003
    4304:	f8d2 2088 	ldr.w	r2, [r2, #136]	; 0x88
    4308:	f042 0206 	orr.w	r2, r2, #6
    430c:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88

    signal_request_start();
    4310:	f001 fd1a 	bl	5d48 <signal_request_start>

    flash_freeze_req[0] = FLASH_FREEZE_REQUEST_CMD;
    4314:	f04f 0302 	mov.w	r3, #2
    4318:	743b      	strb	r3, [r7, #16]
    flash_freeze_req[1] = options;
    431a:	79fb      	ldrb	r3, [r7, #7]
    431c:	747b      	strb	r3, [r7, #17]

    MSS_COMBLK_send_cmd(flash_freeze_req,               /* p_cmd */
    431e:	f107 0210 	add.w	r2, r7, #16
    4322:	f107 030c 	add.w	r3, r7, #12
    4326:	9300      	str	r3, [sp, #0]
    4328:	f04f 0302 	mov.w	r3, #2
    432c:	9301      	str	r3, [sp, #4]
    432e:	f645 5319 	movw	r3, #23833	; 0x5d19
    4332:	f2c0 0300 	movt	r3, #0
    4336:	9302      	str	r3, [sp, #8]
    4338:	4610      	mov	r0, r2
    433a:	f04f 0102 	mov.w	r1, #2
    433e:	f04f 0200 	mov.w	r2, #0
    4342:	f04f 0300 	mov.w	r3, #0
    4346:	f7ff f89f 	bl	3488 <MSS_COMBLK_send_cmd>
                        0u,                             /* data_size */
                        response,                       /* p_response */
                        FLASH_FREEZE_SERV_RESP_LENGTH,  /* response_size */
                        request_completion_handler);    /* completion_handler */

    actual_response_length = wait_for_request_completion();
    434a:	f001 fd19 	bl	5d80 <wait_for_request_completion>
    434e:	4603      	mov	r3, r0
    4350:	82fb      	strh	r3, [r7, #22]
    
    if((FLASH_FREEZE_SERV_RESP_LENGTH == actual_response_length) &&
    4352:	8afb      	ldrh	r3, [r7, #22]
    4354:	2b02      	cmp	r3, #2
    4356:	d105      	bne.n	4364 <MSS_SYS_flash_freeze+0xc0>
       (FLASH_FREEZE_REQUEST_CMD == response[0]))
    4358:	7b3b      	ldrb	r3, [r7, #12]
                        FLASH_FREEZE_SERV_RESP_LENGTH,  /* response_size */
                        request_completion_handler);    /* completion_handler */

    actual_response_length = wait_for_request_completion();
    
    if((FLASH_FREEZE_SERV_RESP_LENGTH == actual_response_length) &&
    435a:	2b02      	cmp	r3, #2
    435c:	d102      	bne.n	4364 <MSS_SYS_flash_freeze+0xc0>
       (FLASH_FREEZE_REQUEST_CMD == response[0]))
    {
        status = response[1];
    435e:	7b7b      	ldrb	r3, [r7, #13]
    4360:	757b      	strb	r3, [r7, #21]
                        FLASH_FREEZE_SERV_RESP_LENGTH,  /* response_size */
                        request_completion_handler);    /* completion_handler */

    actual_response_length = wait_for_request_completion();
    
    if((FLASH_FREEZE_SERV_RESP_LENGTH == actual_response_length) &&
    4362:	e002      	b.n	436a <MSS_SYS_flash_freeze+0xc6>
    {
        status = response[1];
    }
    else
    {
        status = MSS_SYS_UNEXPECTED_ERROR;
    4364:	f06f 0337 	mvn.w	r3, #55	; 0x37
    4368:	757b      	strb	r3, [r7, #21]
    }
    
    return status;
    436a:	7d7b      	ldrb	r3, [r7, #21]
}
    436c:	4618      	mov	r0, r3
    436e:	f107 0718 	add.w	r7, r7, #24
    4372:	46bd      	mov	sp, r7
    4374:	bd80      	pop	{r7, pc}
    4376:	bf00      	nop

00004378 <MSS_SYS_128bit_aes>:
    const uint8_t * iv,
    uint16_t nb_blocks,
    uint8_t mode,
    uint8_t * dest_addr,
    const uint8_t * src_addr)
{
    4378:	b580      	push	{r7, lr}
    437a:	b092      	sub	sp, #72	; 0x48
    437c:	af00      	add	r7, sp, #0
    437e:	60f8      	str	r0, [r7, #12]
    4380:	60b9      	str	r1, [r7, #8]
    4382:	80fa      	strh	r2, [r7, #6]
    4384:	717b      	strb	r3, [r7, #5]
    uint8_t response[STANDARD_SERV_RESP_LENGTH];
    uint8_t params[44];
    uint8_t status;
    
    memcpy(&params[0], key, AES128_KEY_LENGTH);
    4386:	f107 0314 	add.w	r3, r7, #20
    438a:	4618      	mov	r0, r3
    438c:	68f9      	ldr	r1, [r7, #12]
    438e:	f04f 0210 	mov.w	r2, #16
    4392:	f005 fc05 	bl	9ba0 <memcpy>
    memcpy(&params[16], iv, IV_LENGTH);
    4396:	f107 0314 	add.w	r3, r7, #20
    439a:	f103 0310 	add.w	r3, r3, #16
    439e:	4618      	mov	r0, r3
    43a0:	68b9      	ldr	r1, [r7, #8]
    43a2:	f04f 0210 	mov.w	r2, #16
    43a6:	f005 fbfb 	bl	9ba0 <memcpy>
    
    params[32] = (uint8_t)nb_blocks;
    43aa:	88fb      	ldrh	r3, [r7, #6]
    43ac:	b2db      	uxtb	r3, r3
    43ae:	f887 3034 	strb.w	r3, [r7, #52]	; 0x34
    params[33] = (uint8_t)(nb_blocks >> 8u);
    43b2:	88fb      	ldrh	r3, [r7, #6]
    43b4:	ea4f 2313 	mov.w	r3, r3, lsr #8
    43b8:	b29b      	uxth	r3, r3
    43ba:	b2db      	uxtb	r3, r3
    43bc:	f887 3035 	strb.w	r3, [r7, #53]	; 0x35
    params[34] = mode;
    43c0:	797b      	ldrb	r3, [r7, #5]
    43c2:	f887 3036 	strb.w	r3, [r7, #54]	; 0x36
    params[35] = 0u;
    43c6:	f04f 0300 	mov.w	r3, #0
    43ca:	f887 3037 	strb.w	r3, [r7, #55]	; 0x37

    write_ptr_value_into_array(dest_addr, params, 36u);
    43ce:	f107 0314 	add.w	r3, r7, #20
    43d2:	6d38      	ldr	r0, [r7, #80]	; 0x50
    43d4:	4619      	mov	r1, r3
    43d6:	f04f 0224 	mov.w	r2, #36	; 0x24
    43da:	f001 fce5 	bl	5da8 <write_ptr_value_into_array>
    write_ptr_value_into_array(src_addr, params, 40u);
    43de:	f107 0314 	add.w	r3, r7, #20
    43e2:	6d78      	ldr	r0, [r7, #84]	; 0x54
    43e4:	4619      	mov	r1, r3
    43e6:	f04f 0228 	mov.w	r2, #40	; 0x28
    43ea:	f001 fcdd 	bl	5da8 <write_ptr_value_into_array>

    status = execute_service(AES128_REQUEST_CMD,
    43ee:	f107 0214 	add.w	r2, r7, #20
    43f2:	f107 0340 	add.w	r3, r7, #64	; 0x40
    43f6:	f04f 0003 	mov.w	r0, #3
    43fa:	4611      	mov	r1, r2
    43fc:	461a      	mov	r2, r3
    43fe:	f04f 0306 	mov.w	r3, #6
    4402:	f001 fc53 	bl	5cac <execute_service>
    4406:	4603      	mov	r3, r0
    4408:	f887 3047 	strb.w	r3, [r7, #71]	; 0x47
                             params,
                             response,
                             STANDARD_SERV_RESP_LENGTH);
                             
    return status;
    440c:	f897 3047 	ldrb.w	r3, [r7, #71]	; 0x47
}
    4410:	4618      	mov	r0, r3
    4412:	f107 0748 	add.w	r7, r7, #72	; 0x48
    4416:	46bd      	mov	sp, r7
    4418:	bd80      	pop	{r7, pc}
    441a:	bf00      	nop

0000441c <MSS_SYS_256bit_aes>:
    uint16_t nb_blocks,
    uint8_t mode,
    uint8_t * dest_addr,
    const uint8_t * src_addr
)
{
    441c:	b580      	push	{r7, lr}
    441e:	b096      	sub	sp, #88	; 0x58
    4420:	af00      	add	r7, sp, #0
    4422:	60f8      	str	r0, [r7, #12]
    4424:	60b9      	str	r1, [r7, #8]
    4426:	80fa      	strh	r2, [r7, #6]
    4428:	717b      	strb	r3, [r7, #5]
    uint8_t response[STANDARD_SERV_RESP_LENGTH];
    uint8_t params[60];
    uint8_t status;
    
    memcpy(&params[0], key, AES256_KEY_LENGTH);
    442a:	f107 0314 	add.w	r3, r7, #20
    442e:	4618      	mov	r0, r3
    4430:	68f9      	ldr	r1, [r7, #12]
    4432:	f04f 0220 	mov.w	r2, #32
    4436:	f005 fbb3 	bl	9ba0 <memcpy>
    memcpy(&params[32], iv, IV_LENGTH);
    443a:	f107 0314 	add.w	r3, r7, #20
    443e:	f103 0320 	add.w	r3, r3, #32
    4442:	4618      	mov	r0, r3
    4444:	68b9      	ldr	r1, [r7, #8]
    4446:	f04f 0210 	mov.w	r2, #16
    444a:	f005 fba9 	bl	9ba0 <memcpy>
    
    params[48] = (uint8_t)nb_blocks;
    444e:	88fb      	ldrh	r3, [r7, #6]
    4450:	b2db      	uxtb	r3, r3
    4452:	f887 3044 	strb.w	r3, [r7, #68]	; 0x44
    params[49] = (uint8_t)(nb_blocks >> 8u);
    4456:	88fb      	ldrh	r3, [r7, #6]
    4458:	ea4f 2313 	mov.w	r3, r3, lsr #8
    445c:	b29b      	uxth	r3, r3
    445e:	b2db      	uxtb	r3, r3
    4460:	f887 3045 	strb.w	r3, [r7, #69]	; 0x45
    params[50] = mode;
    4464:	797b      	ldrb	r3, [r7, #5]
    4466:	f887 3046 	strb.w	r3, [r7, #70]	; 0x46
    params[51] = 0u;
    446a:	f04f 0300 	mov.w	r3, #0
    446e:	f887 3047 	strb.w	r3, [r7, #71]	; 0x47

    write_ptr_value_into_array(dest_addr, params, 52u);
    4472:	f107 0314 	add.w	r3, r7, #20
    4476:	6e38      	ldr	r0, [r7, #96]	; 0x60
    4478:	4619      	mov	r1, r3
    447a:	f04f 0234 	mov.w	r2, #52	; 0x34
    447e:	f001 fc93 	bl	5da8 <write_ptr_value_into_array>
    write_ptr_value_into_array(src_addr, params, 56u);
    4482:	f107 0314 	add.w	r3, r7, #20
    4486:	6e78      	ldr	r0, [r7, #100]	; 0x64
    4488:	4619      	mov	r1, r3
    448a:	f04f 0238 	mov.w	r2, #56	; 0x38
    448e:	f001 fc8b 	bl	5da8 <write_ptr_value_into_array>

    status = execute_service(AES256_REQUEST_CMD,
    4492:	f107 0214 	add.w	r2, r7, #20
    4496:	f107 0350 	add.w	r3, r7, #80	; 0x50
    449a:	f04f 0006 	mov.w	r0, #6
    449e:	4611      	mov	r1, r2
    44a0:	461a      	mov	r2, r3
    44a2:	f04f 0306 	mov.w	r3, #6
    44a6:	f001 fc01 	bl	5cac <execute_service>
    44aa:	4603      	mov	r3, r0
    44ac:	f887 3057 	strb.w	r3, [r7, #87]	; 0x57
                             params,
                             response,
                             STANDARD_SERV_RESP_LENGTH);
                             
    return status;
    44b0:	f897 3057 	ldrb.w	r3, [r7, #87]	; 0x57
}
    44b4:	4618      	mov	r0, r3
    44b6:	f107 0758 	add.w	r7, r7, #88	; 0x58
    44ba:	46bd      	mov	sp, r7
    44bc:	bd80      	pop	{r7, pc}
    44be:	bf00      	nop

000044c0 <MSS_SYS_sha256>:
(
    const uint8_t * p_data_in,
    uint32_t length,
    uint8_t * result
)
{
    44c0:	b580      	push	{r7, lr}
    44c2:	b08a      	sub	sp, #40	; 0x28
    44c4:	af00      	add	r7, sp, #0
    44c6:	60f8      	str	r0, [r7, #12]
    44c8:	60b9      	str	r1, [r7, #8]
    44ca:	607a      	str	r2, [r7, #4]
    uint8_t response[STANDARD_SERV_RESP_LENGTH];
    uint8_t params[12];
    uint8_t status;
    
    params[0] = (uint8_t)((uint32_t)length);
    44cc:	68bb      	ldr	r3, [r7, #8]
    44ce:	b2db      	uxtb	r3, r3
    44d0:	753b      	strb	r3, [r7, #20]
    params[1] = (uint8_t)((uint32_t)length >> 8u);
    44d2:	68bb      	ldr	r3, [r7, #8]
    44d4:	ea4f 2313 	mov.w	r3, r3, lsr #8
    44d8:	b2db      	uxtb	r3, r3
    44da:	757b      	strb	r3, [r7, #21]
    params[2] = (uint8_t)((uint32_t)length >> 16u);
    44dc:	68bb      	ldr	r3, [r7, #8]
    44de:	ea4f 4313 	mov.w	r3, r3, lsr #16
    44e2:	b2db      	uxtb	r3, r3
    44e4:	75bb      	strb	r3, [r7, #22]
    params[3] = (uint8_t)((uint32_t)length >> 24u);
    44e6:	68bb      	ldr	r3, [r7, #8]
    44e8:	ea4f 6313 	mov.w	r3, r3, lsr #24
    44ec:	b2db      	uxtb	r3, r3
    44ee:	75fb      	strb	r3, [r7, #23]
    
    write_ptr_value_into_array(result, params, 4u);
    44f0:	f107 0314 	add.w	r3, r7, #20
    44f4:	6878      	ldr	r0, [r7, #4]
    44f6:	4619      	mov	r1, r3
    44f8:	f04f 0204 	mov.w	r2, #4
    44fc:	f001 fc54 	bl	5da8 <write_ptr_value_into_array>
    write_ptr_value_into_array(p_data_in, params, 8u);
    4500:	f107 0314 	add.w	r3, r7, #20
    4504:	68f8      	ldr	r0, [r7, #12]
    4506:	4619      	mov	r1, r3
    4508:	f04f 0208 	mov.w	r2, #8
    450c:	f001 fc4c 	bl	5da8 <write_ptr_value_into_array>

    status = execute_service(SHA256_REQUEST_CMD,
    4510:	f107 0214 	add.w	r2, r7, #20
    4514:	f107 0320 	add.w	r3, r7, #32
    4518:	f04f 000a 	mov.w	r0, #10
    451c:	4611      	mov	r1, r2
    451e:	461a      	mov	r2, r3
    4520:	f04f 0306 	mov.w	r3, #6
    4524:	f001 fbc2 	bl	5cac <execute_service>
    4528:	4603      	mov	r3, r0
    452a:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
                             params,
                             response,
                             STANDARD_SERV_RESP_LENGTH);
                             
    return status;
    452e:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
}
    4532:	4618      	mov	r0, r3
    4534:	f107 0728 	add.w	r7, r7, #40	; 0x28
    4538:	46bd      	mov	sp, r7
    453a:	bd80      	pop	{r7, pc}

0000453c <MSS_SYS_hmac>:
    const uint8_t * key,
    const uint8_t * p_data_in,
    uint32_t length,
    uint8_t * p_result
)
{
    453c:	b580      	push	{r7, lr}
    453e:	b096      	sub	sp, #88	; 0x58
    4540:	af00      	add	r7, sp, #0
    4542:	60f8      	str	r0, [r7, #12]
    4544:	60b9      	str	r1, [r7, #8]
    4546:	607a      	str	r2, [r7, #4]
    4548:	603b      	str	r3, [r7, #0]
    uint8_t response[STANDARD_SERV_RESP_LENGTH];
    uint8_t params[58];
    uint8_t status;
    
    memcpy(&params[0], key, HMAC_KEY_LENGTH);
    454a:	f107 0314 	add.w	r3, r7, #20
    454e:	4618      	mov	r0, r3
    4550:	68f9      	ldr	r1, [r7, #12]
    4552:	f04f 0220 	mov.w	r2, #32
    4556:	f005 fb23 	bl	9ba0 <memcpy>
    
    params[32] = (uint8_t)((uint32_t)length);
    455a:	687b      	ldr	r3, [r7, #4]
    455c:	b2db      	uxtb	r3, r3
    455e:	f887 3034 	strb.w	r3, [r7, #52]	; 0x34
    params[33] = (uint8_t)((uint32_t)length >> 8u);
    4562:	687b      	ldr	r3, [r7, #4]
    4564:	ea4f 2313 	mov.w	r3, r3, lsr #8
    4568:	b2db      	uxtb	r3, r3
    456a:	f887 3035 	strb.w	r3, [r7, #53]	; 0x35
    params[34] = (uint8_t)((uint32_t)length >> 16u);
    456e:	687b      	ldr	r3, [r7, #4]
    4570:	ea4f 4313 	mov.w	r3, r3, lsr #16
    4574:	b2db      	uxtb	r3, r3
    4576:	f887 3036 	strb.w	r3, [r7, #54]	; 0x36
    params[35] = (uint8_t)((uint32_t)length >> 24u);
    457a:	687b      	ldr	r3, [r7, #4]
    457c:	ea4f 6313 	mov.w	r3, r3, lsr #24
    4580:	b2db      	uxtb	r3, r3
    4582:	f887 3037 	strb.w	r3, [r7, #55]	; 0x37

    write_ptr_value_into_array(p_data_in, params, 36u);
    4586:	f107 0314 	add.w	r3, r7, #20
    458a:	68b8      	ldr	r0, [r7, #8]
    458c:	4619      	mov	r1, r3
    458e:	f04f 0224 	mov.w	r2, #36	; 0x24
    4592:	f001 fc09 	bl	5da8 <write_ptr_value_into_array>
    write_ptr_value_into_array(p_result, params, 40u);
    4596:	f107 0314 	add.w	r3, r7, #20
    459a:	6838      	ldr	r0, [r7, #0]
    459c:	4619      	mov	r1, r3
    459e:	f04f 0228 	mov.w	r2, #40	; 0x28
    45a2:	f001 fc01 	bl	5da8 <write_ptr_value_into_array>

    status = execute_service(HMAC_REQUEST_CMD,
    45a6:	f107 0214 	add.w	r2, r7, #20
    45aa:	f107 0350 	add.w	r3, r7, #80	; 0x50
    45ae:	f04f 000c 	mov.w	r0, #12
    45b2:	4611      	mov	r1, r2
    45b4:	461a      	mov	r2, r3
    45b6:	f04f 0306 	mov.w	r3, #6
    45ba:	f001 fb77 	bl	5cac <execute_service>
    45be:	4603      	mov	r3, r0
    45c0:	f887 3057 	strb.w	r3, [r7, #87]	; 0x57
                             params,
                             response,
                             STANDARD_SERV_RESP_LENGTH);
                             
    return status;
    45c4:	f897 3057 	ldrb.w	r3, [r7, #87]	; 0x57
}
    45c8:	4618      	mov	r0, r3
    45ca:	f107 0758 	add.w	r7, r7, #88	; 0x58
    45ce:	46bd      	mov	sp, r7
    45d0:	bd80      	pop	{r7, pc}
    45d2:	bf00      	nop

000045d4 <MSS_SYS_key_tree>:
(
    uint8_t* p_key,
    uint8_t op_type,
    const uint8_t* path
)
{
    45d4:	b580      	push	{r7, lr}
    45d6:	b094      	sub	sp, #80	; 0x50
    45d8:	af00      	add	r7, sp, #0
    45da:	60f8      	str	r0, [r7, #12]
    45dc:	460b      	mov	r3, r1
    45de:	607a      	str	r2, [r7, #4]
    45e0:	72fb      	strb	r3, [r7, #11]
    uint8_t response[STANDARD_SERV_RESP_LENGTH];
    uint8_t params[49];
    uint8_t status;
    
    memcpy(&params[0], p_key, KEYTREE_KEY_LENGTH);
    45e2:	f107 0314 	add.w	r3, r7, #20
    45e6:	4618      	mov	r0, r3
    45e8:	68f9      	ldr	r1, [r7, #12]
    45ea:	f04f 0220 	mov.w	r2, #32
    45ee:	f005 fad7 	bl	9ba0 <memcpy>
    
    params[32] = op_type;
    45f2:	7afb      	ldrb	r3, [r7, #11]
    45f4:	f887 3034 	strb.w	r3, [r7, #52]	; 0x34
    
    memcpy(&params[33], path, KEYTREE_PATH_LENGTH);
    45f8:	f107 0314 	add.w	r3, r7, #20
    45fc:	f103 0321 	add.w	r3, r3, #33	; 0x21
    4600:	4618      	mov	r0, r3
    4602:	6879      	ldr	r1, [r7, #4]
    4604:	f04f 0210 	mov.w	r2, #16
    4608:	f005 faca 	bl	9ba0 <memcpy>
    
    status = execute_service(KEYTREE_REQUEST_CMD,
    460c:	f107 0214 	add.w	r2, r7, #20
    4610:	f107 0348 	add.w	r3, r7, #72	; 0x48
    4614:	f04f 0009 	mov.w	r0, #9
    4618:	4611      	mov	r1, r2
    461a:	461a      	mov	r2, r3
    461c:	f04f 0306 	mov.w	r3, #6
    4620:	f001 fb44 	bl	5cac <execute_service>
    4624:	4603      	mov	r3, r0
    4626:	f887 304f 	strb.w	r3, [r7, #79]	; 0x4f
                             params,
                             response,
                             STANDARD_SERV_RESP_LENGTH);
    
    if(status == MSS_SYS_SUCCESS)
    462a:	f897 304f 	ldrb.w	r3, [r7, #79]	; 0x4f
    462e:	2b00      	cmp	r3, #0
    4630:	d107      	bne.n	4642 <MSS_SYS_key_tree+0x6e>
    {
       memcpy(p_key, &params[0], KEYTREE_KEY_LENGTH);
    4632:	f107 0314 	add.w	r3, r7, #20
    4636:	68f8      	ldr	r0, [r7, #12]
    4638:	4619      	mov	r1, r3
    463a:	f04f 0220 	mov.w	r2, #32
    463e:	f005 faaf 	bl	9ba0 <memcpy>
    }
    
    return status;
    4642:	f897 304f 	ldrb.w	r3, [r7, #79]	; 0x4f
}
    4646:	4618      	mov	r0, r3
    4648:	f107 0750 	add.w	r7, r7, #80	; 0x50
    464c:	46bd      	mov	sp, r7
    464e:	bd80      	pop	{r7, pc}

00004650 <MSS_SYS_challenge_response>:
(
    uint8_t* p_key,
    uint8_t op_type,
    const uint8_t* path
)
{
    4650:	b580      	push	{r7, lr}
    4652:	b08c      	sub	sp, #48	; 0x30
    4654:	af00      	add	r7, sp, #0
    4656:	60f8      	str	r0, [r7, #12]
    4658:	460b      	mov	r3, r1
    465a:	607a      	str	r2, [r7, #4]
    465c:	72fb      	strb	r3, [r7, #11]
    uint8_t response[STANDARD_SERV_RESP_LENGTH];
    uint8_t params[21];
    uint8_t status;
    
    params[0] = (uint8_t)((uint32_t)p_key);
    465e:	68fb      	ldr	r3, [r7, #12]
    4660:	b2db      	uxtb	r3, r3
    4662:	743b      	strb	r3, [r7, #16]
    params[1] = (uint8_t)((uint32_t)p_key >> 8u);
    4664:	68fb      	ldr	r3, [r7, #12]
    4666:	ea4f 2313 	mov.w	r3, r3, lsr #8
    466a:	b2db      	uxtb	r3, r3
    466c:	747b      	strb	r3, [r7, #17]
    params[2] = (uint8_t)((uint32_t)p_key >> 16u);
    466e:	68fb      	ldr	r3, [r7, #12]
    4670:	ea4f 4313 	mov.w	r3, r3, lsr #16
    4674:	b2db      	uxtb	r3, r3
    4676:	74bb      	strb	r3, [r7, #18]
    params[3] = (uint8_t)((uint32_t)p_key >> 24u);
    4678:	68fb      	ldr	r3, [r7, #12]
    467a:	ea4f 6313 	mov.w	r3, r3, lsr #24
    467e:	b2db      	uxtb	r3, r3
    4680:	74fb      	strb	r3, [r7, #19]
    
    params[4] = op_type;
    4682:	7afb      	ldrb	r3, [r7, #11]
    4684:	753b      	strb	r3, [r7, #20]
    
    memcpy(&params[5], path, KEYTREE_PATH_LENGTH);
    4686:	f107 0310 	add.w	r3, r7, #16
    468a:	f103 0305 	add.w	r3, r3, #5
    468e:	4618      	mov	r0, r3
    4690:	6879      	ldr	r1, [r7, #4]
    4692:	f04f 0210 	mov.w	r2, #16
    4696:	f005 fa83 	bl	9ba0 <memcpy>
    
    status = execute_service(PPUF_CHALLENGE_RESP_REQUEST_CMD,
    469a:	f107 0210 	add.w	r2, r7, #16
    469e:	f107 0328 	add.w	r3, r7, #40	; 0x28
    46a2:	f04f 000e 	mov.w	r0, #14
    46a6:	4611      	mov	r1, r2
    46a8:	461a      	mov	r2, r3
    46aa:	f04f 0306 	mov.w	r3, #6
    46ae:	f001 fafd 	bl	5cac <execute_service>
    46b2:	4603      	mov	r3, r0
    46b4:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
                             params,
                             response,
                             STANDARD_SERV_RESP_LENGTH);
                             
    return status;
    46b8:	f897 302f 	ldrb.w	r3, [r7, #47]	; 0x2f
}
    46bc:	4618      	mov	r0, r3
    46be:	f107 0730 	add.w	r7, r7, #48	; 0x30
    46c2:	46bd      	mov	sp, r7
    46c4:	bd80      	pop	{r7, pc}
    46c6:	bf00      	nop

000046c8 <MSS_SYS_nrbg_reset>:

/*==============================================================================
 * See mss_sys_services.h for details.
 */
uint8_t MSS_SYS_nrbg_reset(void)
{
    46c8:	b580      	push	{r7, lr}
    46ca:	b088      	sub	sp, #32
    46cc:	af04      	add	r7, sp, #16
    uint8_t status;
    uint16_t actual_response_length;
    uint8_t reset_cmd[4];
    uint8_t response[NRBG_RESET_SERV_RESP_LENGTH];
    
    signal_request_start();
    46ce:	f001 fb3b 	bl	5d48 <signal_request_start>
    
    reset_cmd[0] = NRBG_RESET_REQUEST_CMD;
    46d2:	f04f 032d 	mov.w	r3, #45	; 0x2d
    46d6:	723b      	strb	r3, [r7, #8]
    reset_cmd[1] = 0u;
    46d8:	f04f 0300 	mov.w	r3, #0
    46dc:	727b      	strb	r3, [r7, #9]
    reset_cmd[2] = 0u;
    46de:	f04f 0300 	mov.w	r3, #0
    46e2:	72bb      	strb	r3, [r7, #10]
    reset_cmd[3] = 0u;
    46e4:	f04f 0300 	mov.w	r3, #0
    46e8:	72fb      	strb	r3, [r7, #11]

    MSS_COMBLK_send_cmd(reset_cmd,                      /* p_cmd */
    46ea:	f107 0208 	add.w	r2, r7, #8
    46ee:	f107 0304 	add.w	r3, r7, #4
    46f2:	9300      	str	r3, [sp, #0]
    46f4:	f04f 0302 	mov.w	r3, #2
    46f8:	9301      	str	r3, [sp, #4]
    46fa:	f645 5319 	movw	r3, #23833	; 0x5d19
    46fe:	f2c0 0300 	movt	r3, #0
    4702:	9302      	str	r3, [sp, #8]
    4704:	4610      	mov	r0, r2
    4706:	f04f 0104 	mov.w	r1, #4
    470a:	f04f 0200 	mov.w	r2, #0
    470e:	f04f 0300 	mov.w	r3, #0
    4712:	f7fe feb9 	bl	3488 <MSS_COMBLK_send_cmd>
                        0,                              /* data_size */
                        response,                       /* p_response */
                        DRBG_RESET_SERV_RESP_LENGTH,    /* response_size */
                        request_completion_handler);    /* completion_handler */
    
     actual_response_length = wait_for_request_completion();
    4716:	f001 fb33 	bl	5d80 <wait_for_request_completion>
    471a:	4603      	mov	r3, r0
    471c:	81fb      	strh	r3, [r7, #14]
    
    if((NRBG_RESET_SERV_RESP_LENGTH == actual_response_length) &&
    471e:	89fb      	ldrh	r3, [r7, #14]
    4720:	2b02      	cmp	r3, #2
    4722:	d105      	bne.n	4730 <MSS_SYS_nrbg_reset+0x68>
       (NRBG_RESET_REQUEST_CMD == response[0]))
    4724:	793b      	ldrb	r3, [r7, #4]
                        DRBG_RESET_SERV_RESP_LENGTH,    /* response_size */
                        request_completion_handler);    /* completion_handler */
    
     actual_response_length = wait_for_request_completion();
    
    if((NRBG_RESET_SERV_RESP_LENGTH == actual_response_length) &&
    4726:	2b2d      	cmp	r3, #45	; 0x2d
    4728:	d102      	bne.n	4730 <MSS_SYS_nrbg_reset+0x68>
       (NRBG_RESET_REQUEST_CMD == response[0]))
    {
        status = response[1];
    472a:	797b      	ldrb	r3, [r7, #5]
    472c:	737b      	strb	r3, [r7, #13]
                        DRBG_RESET_SERV_RESP_LENGTH,    /* response_size */
                        request_completion_handler);    /* completion_handler */
    
     actual_response_length = wait_for_request_completion();
    
    if((NRBG_RESET_SERV_RESP_LENGTH == actual_response_length) &&
    472e:	e002      	b.n	4736 <MSS_SYS_nrbg_reset+0x6e>
    {
        status = response[1];
    }
    else
    {
        status = MSS_SYS_UNEXPECTED_ERROR;
    4730:	f06f 0337 	mvn.w	r3, #55	; 0x37
    4734:	737b      	strb	r3, [r7, #13]
    }
    
    return status;
    4736:	7b7b      	ldrb	r3, [r7, #13]
}
    4738:	4618      	mov	r0, r3
    473a:	f107 0710 	add.w	r7, r7, #16
    473e:	46bd      	mov	sp, r7
    4740:	bd80      	pop	{r7, pc}
    4742:	bf00      	nop

00004744 <MSS_SYS_nrbg_self_test>:

/*==============================================================================
 * See mss_sys_services.h for details.
 */
uint8_t MSS_SYS_nrbg_self_test(void)
{
    4744:	b580      	push	{r7, lr}
    4746:	b086      	sub	sp, #24
    4748:	af04      	add	r7, sp, #16
    uint8_t status;
    uint16_t actual_response_length;
    uint8_t self_test;
    uint8_t response[NRBG_SELF_TEST_SERV_RESP_LENGTH];
    
    signal_request_start();
    474a:	f001 fafd 	bl	5d48 <signal_request_start>
    
    self_test = NRBG_SELF_TEST_REQUEST_CMD;
    474e:	f04f 0328 	mov.w	r3, #40	; 0x28
    4752:	713b      	strb	r3, [r7, #4]

    MSS_COMBLK_send_cmd(&self_test,                         /* p_cmd */
    4754:	f107 0204 	add.w	r2, r7, #4
    4758:	463b      	mov	r3, r7
    475a:	9300      	str	r3, [sp, #0]
    475c:	f04f 0302 	mov.w	r3, #2
    4760:	9301      	str	r3, [sp, #4]
    4762:	f645 5319 	movw	r3, #23833	; 0x5d19
    4766:	f2c0 0300 	movt	r3, #0
    476a:	9302      	str	r3, [sp, #8]
    476c:	4610      	mov	r0, r2
    476e:	f04f 0101 	mov.w	r1, #1
    4772:	f04f 0200 	mov.w	r2, #0
    4776:	f04f 0300 	mov.w	r3, #0
    477a:	f7fe fe85 	bl	3488 <MSS_COMBLK_send_cmd>
                        0,                                  /* data_size */
                        response,                           /* p_response */
                        NRBG_SELF_TEST_SERV_RESP_LENGTH,    /* response_size */
                        request_completion_handler);        /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    477e:	f001 faff 	bl	5d80 <wait_for_request_completion>
    4782:	4603      	mov	r3, r0
    4784:	80fb      	strh	r3, [r7, #6]
    
    if((NRBG_SELF_TEST_SERV_RESP_LENGTH == actual_response_length) &&
    4786:	88fb      	ldrh	r3, [r7, #6]
    4788:	2b02      	cmp	r3, #2
    478a:	d105      	bne.n	4798 <MSS_SYS_nrbg_self_test+0x54>
       (NRBG_SELF_TEST_REQUEST_CMD == response[0]))
    478c:	783b      	ldrb	r3, [r7, #0]
                        NRBG_SELF_TEST_SERV_RESP_LENGTH,    /* response_size */
                        request_completion_handler);        /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    
    if((NRBG_SELF_TEST_SERV_RESP_LENGTH == actual_response_length) &&
    478e:	2b28      	cmp	r3, #40	; 0x28
    4790:	d102      	bne.n	4798 <MSS_SYS_nrbg_self_test+0x54>
       (NRBG_SELF_TEST_REQUEST_CMD == response[0]))
    {
        status = response[1];
    4792:	787b      	ldrb	r3, [r7, #1]
    4794:	717b      	strb	r3, [r7, #5]
                        NRBG_SELF_TEST_SERV_RESP_LENGTH,    /* response_size */
                        request_completion_handler);        /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    
    if((NRBG_SELF_TEST_SERV_RESP_LENGTH == actual_response_length) &&
    4796:	e002      	b.n	479e <MSS_SYS_nrbg_self_test+0x5a>
    {
        status = response[1];
    }
    else
    {
        status = MSS_SYS_UNEXPECTED_ERROR;
    4798:	f06f 0337 	mvn.w	r3, #55	; 0x37
    479c:	717b      	strb	r3, [r7, #5]
    }
    
    return status;
    479e:	797b      	ldrb	r3, [r7, #5]
}
    47a0:	4618      	mov	r0, r3
    47a2:	f107 0708 	add.w	r7, r7, #8
    47a6:	46bd      	mov	sp, r7
    47a8:	bd80      	pop	{r7, pc}
    47aa:	bf00      	nop

000047ac <MSS_SYS_nrbg_instantiate>:
(
    const uint8_t * personalization_str,
    uint16_t personalization_str_length,
    uint8_t * p_nrbg_handle
)
{
    47ac:	b580      	push	{r7, lr}
    47ae:	b088      	sub	sp, #32
    47b0:	af00      	add	r7, sp, #0
    47b2:	60f8      	str	r0, [r7, #12]
    47b4:	460b      	mov	r3, r1
    47b6:	607a      	str	r2, [r7, #4]
    47b8:	817b      	strh	r3, [r7, #10]
    uint8_t response[STANDARD_SERV_RESP_LENGTH];
    uint8_t instantiate_params[7];
    uint8_t status;
    
    write_ptr_value_into_array(personalization_str, instantiate_params, 0u);
    47ba:	f107 0310 	add.w	r3, r7, #16
    47be:	68f8      	ldr	r0, [r7, #12]
    47c0:	4619      	mov	r1, r3
    47c2:	f04f 0200 	mov.w	r2, #0
    47c6:	f001 faef 	bl	5da8 <write_ptr_value_into_array>
    
    instantiate_params[4] = (uint8_t)personalization_str_length;
    47ca:	897b      	ldrh	r3, [r7, #10]
    47cc:	b2db      	uxtb	r3, r3
    47ce:	753b      	strb	r3, [r7, #20]
    instantiate_params[5] = (uint8_t)(personalization_str_length >> 8u);
    47d0:	897b      	ldrh	r3, [r7, #10]
    47d2:	ea4f 2313 	mov.w	r3, r3, lsr #8
    47d6:	b29b      	uxth	r3, r3
    47d8:	b2db      	uxtb	r3, r3
    47da:	757b      	strb	r3, [r7, #21]
    instantiate_params[6] = INVALID_NRBG_HANDLE;
    47dc:	f04f 33ff 	mov.w	r3, #4294967295
    47e0:	75bb      	strb	r3, [r7, #22]
    
    status = execute_service(NRBG_INSTANTIATE_REQUEST_CMD,
    47e2:	f107 0210 	add.w	r2, r7, #16
    47e6:	f107 0318 	add.w	r3, r7, #24
    47ea:	f04f 0029 	mov.w	r0, #41	; 0x29
    47ee:	4611      	mov	r1, r2
    47f0:	461a      	mov	r2, r3
    47f2:	f04f 0306 	mov.w	r3, #6
    47f6:	f001 fa59 	bl	5cac <execute_service>
    47fa:	4603      	mov	r3, r0
    47fc:	77fb      	strb	r3, [r7, #31]
                             instantiate_params,
                             response,
                             STANDARD_SERV_RESP_LENGTH);
                             
    if(MSS_SYS_SUCCESS == status)
    47fe:	7ffb      	ldrb	r3, [r7, #31]
    4800:	2b00      	cmp	r3, #0
    4802:	d102      	bne.n	480a <MSS_SYS_nrbg_instantiate+0x5e>
    {
        *p_nrbg_handle = instantiate_params[6];
    4804:	7dba      	ldrb	r2, [r7, #22]
    4806:	687b      	ldr	r3, [r7, #4]
    4808:	701a      	strb	r2, [r3, #0]
    }
    
    return status;
    480a:	7ffb      	ldrb	r3, [r7, #31]
}
    480c:	4618      	mov	r0, r3
    480e:	f107 0720 	add.w	r7, r7, #32
    4812:	46bd      	mov	sp, r7
    4814:	bd80      	pop	{r7, pc}
    4816:	bf00      	nop

00004818 <MSS_SYS_nrbg_generate>:
    uint8_t requested_length,
    uint8_t additional_input_length,
    uint8_t pr_req,
    uint8_t nrbg_handle
)
{
    4818:	b580      	push	{r7, lr}
    481a:	b08a      	sub	sp, #40	; 0x28
    481c:	af00      	add	r7, sp, #0
    481e:	60f8      	str	r0, [r7, #12]
    4820:	60b9      	str	r1, [r7, #8]
    4822:	71fa      	strb	r2, [r7, #7]
    4824:	71bb      	strb	r3, [r7, #6]
    uint8_t response[STANDARD_SERV_RESP_LENGTH];
    uint8_t generate_params[12];
    uint8_t status;

    write_ptr_value_into_array(p_requested_data, generate_params, 0u);
    4826:	f107 0314 	add.w	r3, r7, #20
    482a:	68f8      	ldr	r0, [r7, #12]
    482c:	4619      	mov	r1, r3
    482e:	f04f 0200 	mov.w	r2, #0
    4832:	f001 fab9 	bl	5da8 <write_ptr_value_into_array>
    write_ptr_value_into_array(p_additional_input, generate_params, 4u);
    4836:	f107 0314 	add.w	r3, r7, #20
    483a:	68b8      	ldr	r0, [r7, #8]
    483c:	4619      	mov	r1, r3
    483e:	f04f 0204 	mov.w	r2, #4
    4842:	f001 fab1 	bl	5da8 <write_ptr_value_into_array>

    generate_params[8] = requested_length;
    4846:	79fb      	ldrb	r3, [r7, #7]
    4848:	773b      	strb	r3, [r7, #28]
    generate_params[9] = additional_input_length;
    484a:	79bb      	ldrb	r3, [r7, #6]
    484c:	777b      	strb	r3, [r7, #29]
    generate_params[10] = pr_req;
    484e:	f897 3030 	ldrb.w	r3, [r7, #48]	; 0x30
    4852:	77bb      	strb	r3, [r7, #30]
    generate_params[11] = nrbg_handle;
    4854:	f897 3034 	ldrb.w	r3, [r7, #52]	; 0x34
    4858:	77fb      	strb	r3, [r7, #31]
    
    status = execute_service(NRBG_GENERATE_REQUEST_CMD,
    485a:	f107 0214 	add.w	r2, r7, #20
    485e:	f107 0320 	add.w	r3, r7, #32
    4862:	f04f 002a 	mov.w	r0, #42	; 0x2a
    4866:	4611      	mov	r1, r2
    4868:	461a      	mov	r2, r3
    486a:	f04f 0306 	mov.w	r3, #6
    486e:	f001 fa1d 	bl	5cac <execute_service>
    4872:	4603      	mov	r3, r0
    4874:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
                             generate_params,
                             response,
                             STANDARD_SERV_RESP_LENGTH);
    
    return status;
    4878:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
}
    487c:	4618      	mov	r0, r3
    487e:	f107 0728 	add.w	r7, r7, #40	; 0x28
    4882:	46bd      	mov	sp, r7
    4884:	bd80      	pop	{r7, pc}
    4886:	bf00      	nop

00004888 <MSS_SYS_nrbg_reseed>:
(
    const uint8_t * p_additional_input,
    uint8_t additional_input_length,
    uint8_t nrbg_handle
)
{
    4888:	b580      	push	{r7, lr}
    488a:	b086      	sub	sp, #24
    488c:	af00      	add	r7, sp, #0
    488e:	6078      	str	r0, [r7, #4]
    4890:	4613      	mov	r3, r2
    4892:	460a      	mov	r2, r1
    4894:	70fa      	strb	r2, [r7, #3]
    4896:	70bb      	strb	r3, [r7, #2]
    uint8_t response[STANDARD_SERV_RESP_LENGTH];
    uint8_t params[6];
    uint8_t status;

    write_ptr_value_into_array(p_additional_input, params, 0u);
    4898:	f107 0308 	add.w	r3, r7, #8
    489c:	6878      	ldr	r0, [r7, #4]
    489e:	4619      	mov	r1, r3
    48a0:	f04f 0200 	mov.w	r2, #0
    48a4:	f001 fa80 	bl	5da8 <write_ptr_value_into_array>

    params[4] = (uint8_t)additional_input_length;
    48a8:	78fb      	ldrb	r3, [r7, #3]
    48aa:	733b      	strb	r3, [r7, #12]
    params[5] = nrbg_handle;
    48ac:	78bb      	ldrb	r3, [r7, #2]
    48ae:	737b      	strb	r3, [r7, #13]
    
    status = execute_service(NRBG_RESEED_REQUEST_CMD,
    48b0:	f107 0208 	add.w	r2, r7, #8
    48b4:	f107 0310 	add.w	r3, r7, #16
    48b8:	f04f 002b 	mov.w	r0, #43	; 0x2b
    48bc:	4611      	mov	r1, r2
    48be:	461a      	mov	r2, r3
    48c0:	f04f 0306 	mov.w	r3, #6
    48c4:	f001 f9f2 	bl	5cac <execute_service>
    48c8:	4603      	mov	r3, r0
    48ca:	75fb      	strb	r3, [r7, #23]
                             params,
                             response,
                             STANDARD_SERV_RESP_LENGTH);
    
    return status;
    48cc:	7dfb      	ldrb	r3, [r7, #23]
}
    48ce:	4618      	mov	r0, r3
    48d0:	f107 0718 	add.w	r7, r7, #24
    48d4:	46bd      	mov	sp, r7
    48d6:	bd80      	pop	{r7, pc}

000048d8 <MSS_SYS_nrbg_uninstantiate>:
 */
uint8_t MSS_SYS_nrbg_uninstantiate
(
    uint8_t nrbg_handle
)
{
    48d8:	b580      	push	{r7, lr}
    48da:	b08a      	sub	sp, #40	; 0x28
    48dc:	af04      	add	r7, sp, #16
    48de:	4603      	mov	r3, r0
    48e0:	71fb      	strb	r3, [r7, #7]
    uint8_t status;
    uint16_t actual_response_length;
    uint8_t uninstantiate_req[2];
    uint8_t response[NRBG_UNINST_SERV_RESP_LENGTH];
    
    signal_request_start();
    48e2:	f001 fa31 	bl	5d48 <signal_request_start>
    
    uninstantiate_req[0] = NRBG_UNINSTANTIATE_REQUEST_CMD;
    48e6:	f04f 032c 	mov.w	r3, #44	; 0x2c
    48ea:	743b      	strb	r3, [r7, #16]
    uninstantiate_req[1] = nrbg_handle;
    48ec:	79fb      	ldrb	r3, [r7, #7]
    48ee:	747b      	strb	r3, [r7, #17]

    MSS_COMBLK_send_cmd(uninstantiate_req,              /* p_cmd */
    48f0:	f107 0210 	add.w	r2, r7, #16
    48f4:	f107 030c 	add.w	r3, r7, #12
    48f8:	9300      	str	r3, [sp, #0]
    48fa:	f04f 0303 	mov.w	r3, #3
    48fe:	9301      	str	r3, [sp, #4]
    4900:	f645 5319 	movw	r3, #23833	; 0x5d19
    4904:	f2c0 0300 	movt	r3, #0
    4908:	9302      	str	r3, [sp, #8]
    490a:	4610      	mov	r0, r2
    490c:	f04f 0102 	mov.w	r1, #2
    4910:	f04f 0200 	mov.w	r2, #0
    4914:	f04f 0300 	mov.w	r3, #0
    4918:	f7fe fdb6 	bl	3488 <MSS_COMBLK_send_cmd>
                        0,                              /* data_size */
                        response,                       /* p_response */
                        NRBG_UNINST_SERV_RESP_LENGTH,   /* response_size */
                        request_completion_handler);    /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    491c:	f001 fa30 	bl	5d80 <wait_for_request_completion>
    4920:	4603      	mov	r3, r0
    4922:	82fb      	strh	r3, [r7, #22]
    
    if((NRBG_UNINST_SERV_RESP_LENGTH == actual_response_length) &&
    4924:	8afb      	ldrh	r3, [r7, #22]
    4926:	2b03      	cmp	r3, #3
    4928:	d105      	bne.n	4936 <MSS_SYS_nrbg_uninstantiate+0x5e>
       (NRBG_UNINSTANTIATE_REQUEST_CMD == response[0]))
    492a:	7b3b      	ldrb	r3, [r7, #12]
                        NRBG_UNINST_SERV_RESP_LENGTH,   /* response_size */
                        request_completion_handler);    /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    
    if((NRBG_UNINST_SERV_RESP_LENGTH == actual_response_length) &&
    492c:	2b2c      	cmp	r3, #44	; 0x2c
    492e:	d102      	bne.n	4936 <MSS_SYS_nrbg_uninstantiate+0x5e>
       (NRBG_UNINSTANTIATE_REQUEST_CMD == response[0]))
    {
        status = response[1];
    4930:	7b7b      	ldrb	r3, [r7, #13]
    4932:	757b      	strb	r3, [r7, #21]
                        NRBG_UNINST_SERV_RESP_LENGTH,   /* response_size */
                        request_completion_handler);    /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    
    if((NRBG_UNINST_SERV_RESP_LENGTH == actual_response_length) &&
    4934:	e002      	b.n	493c <MSS_SYS_nrbg_uninstantiate+0x64>
    {
        status = response[1];
    }
    else
    {
        status = MSS_SYS_UNEXPECTED_ERROR;
    4936:	f06f 0337 	mvn.w	r3, #55	; 0x37
    493a:	757b      	strb	r3, [r7, #21]
    }
    
    return status;
    493c:	7d7b      	ldrb	r3, [r7, #21]
}
    493e:	4618      	mov	r0, r3
    4940:	f107 0718 	add.w	r7, r7, #24
    4944:	46bd      	mov	sp, r7
    4946:	bd80      	pop	{r7, pc}

00004948 <MSS_SYS_zeroize_device>:

/*==============================================================================
 * See mss_sys_services.h for details.
 */
void MSS_SYS_zeroize_device(void)
{
    4948:	b580      	push	{r7, lr}
    494a:	b086      	sub	sp, #24
    494c:	af04      	add	r7, sp, #16
     * We only need to send one command byte to initiate zeroization.
     * The zeroization process should result in the Cortex-M3 being reset. This
     * means we should never reach the end of this function if zeroization is
     * actually performed.
     */
    uint8_t zeroization_req = ZEROIZATION_REQUEST_CMD;
    494e:	f06f 030f 	mvn.w	r3, #15
    4952:	71fb      	strb	r3, [r7, #7]
    
    /*
     * The Zeroization system service is not available on M2S050 rev A, rev B
     * and rev C.
     */
    ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION);
    4954:	f248 0300 	movw	r3, #32768	; 0x8000
    4958:	f2c4 0303 	movt	r3, #16387	; 0x4003
    495c:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    4960:	f64f 0302 	movw	r3, #63490	; 0xf802
    4964:	429a      	cmp	r2, r3
    4966:	d100      	bne.n	496a <MSS_SYS_zeroize_device+0x22>
    4968:	be00      	bkpt	0x0000
    ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION);
    496a:	f248 0300 	movw	r3, #32768	; 0x8000
    496e:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4972:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    4976:	f64f 0302 	movw	r3, #63490	; 0xf802
    497a:	f2c0 0301 	movt	r3, #1
    497e:	429a      	cmp	r2, r3
    4980:	d100      	bne.n	4984 <MSS_SYS_zeroize_device+0x3c>
    4982:	be00      	bkpt	0x0000
    ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION);
    4984:	f248 0300 	movw	r3, #32768	; 0x8000
    4988:	f2c4 0303 	movt	r3, #16387	; 0x4003
    498c:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    4990:	f64f 0302 	movw	r3, #63490	; 0xf802
    4994:	f2c0 0302 	movt	r3, #2
    4998:	429a      	cmp	r2, r3
    499a:	d100      	bne.n	499e <MSS_SYS_zeroize_device+0x56>
    499c:	be00      	bkpt	0x0000
    
    signal_request_start();
    499e:	f001 f9d3 	bl	5d48 <signal_request_start>
    
    MSS_COMBLK_send_cmd(&zeroization_req,               /* p_cmd */
    49a2:	f107 0207 	add.w	r2, r7, #7
    49a6:	f04f 0300 	mov.w	r3, #0
    49aa:	9300      	str	r3, [sp, #0]
    49ac:	f04f 0300 	mov.w	r3, #0
    49b0:	9301      	str	r3, [sp, #4]
    49b2:	f645 5319 	movw	r3, #23833	; 0x5d19
    49b6:	f2c0 0300 	movt	r3, #0
    49ba:	9302      	str	r3, [sp, #8]
    49bc:	4610      	mov	r0, r2
    49be:	f04f 0101 	mov.w	r1, #1
    49c2:	f04f 0200 	mov.w	r2, #0
    49c6:	f04f 0300 	mov.w	r3, #0
    49ca:	f7fe fd5d 	bl	3488 <MSS_COMBLK_send_cmd>
                        request_completion_handler);    /* completion_handler */
    
    /*
     * Handle case where zeroization is not enabled in the device.
     */
    wait_for_request_completion();
    49ce:	f001 f9d7 	bl	5d80 <wait_for_request_completion>
}
    49d2:	f107 0708 	add.w	r7, r7, #8
    49d6:	46bd      	mov	sp, r7
    49d8:	bd80      	pop	{r7, pc}
    49da:	bf00      	nop

000049dc <isp_page_read_handler>:

static uint32_t isp_page_read_handler
(
    uint8_t const ** pp_next_page
)
{
    49dc:	b580      	push	{r7, lr}
    49de:	b086      	sub	sp, #24
    49e0:	af00      	add	r7, sp, #0
    49e2:	6078      	str	r0, [r7, #4]
    uint32_t remaining_length = 0;
    49e4:	f04f 0300 	mov.w	r3, #0
    49e8:	60fb      	str	r3, [r7, #12]
    uint32_t running_on_standby_clock;
    volatile uint32_t timeout;
    const uint32_t apb_divisors_mask = 0x00000EFCU;
    49ea:	f640 63fc 	movw	r3, #3836	; 0xefc
    49ee:	617b      	str	r3, [r7, #20]
    
    if((g_mode !=  MSS_SYS_PROG_AUTHENTICATE) & (wait_for_clock_switch == 1))
    49f0:	f240 1384 	movw	r3, #388	; 0x184
    49f4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    49f8:	781b      	ldrb	r3, [r3, #0]
    49fa:	2b00      	cmp	r3, #0
    49fc:	bf0c      	ite	eq
    49fe:	2300      	moveq	r3, #0
    4a00:	2301      	movne	r3, #1
    4a02:	b2da      	uxtb	r2, r3
    4a04:	f240 030c 	movw	r3, #12
    4a08:	f2c2 0300 	movt	r3, #8192	; 0x2000
    4a0c:	781b      	ldrb	r3, [r3, #0]
    4a0e:	2b01      	cmp	r3, #1
    4a10:	bf14      	ite	ne
    4a12:	2300      	movne	r3, #0
    4a14:	2301      	moveq	r3, #1
    4a16:	b2db      	uxtb	r3, r3
    4a18:	ea02 0303 	and.w	r3, r2, r3
    4a1c:	b2db      	uxtb	r3, r3
    4a1e:	2b00      	cmp	r3, #0
    4a20:	d02d      	beq.n	4a7e <isp_page_read_handler+0xa2>
    {
        timeout = DELAY_MORE_THAN_10US;
    4a22:	f241 3388 	movw	r3, #5000	; 0x1388
    4a26:	60bb      	str	r3, [r7, #8]
        do
        {
            running_on_standby_clock = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK;
    4a28:	f248 0300 	movw	r3, #32768	; 0x8000
    4a2c:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4a30:	f8d3 3098 	ldr.w	r3, [r3, #152]	; 0x98
    4a34:	f403 5380 	and.w	r3, r3, #4096	; 0x1000
    4a38:	613b      	str	r3, [r7, #16]
            --timeout;
    4a3a:	68bb      	ldr	r3, [r7, #8]
    4a3c:	f103 33ff 	add.w	r3, r3, #4294967295
    4a40:	60bb      	str	r3, [r7, #8]
        }
        while ((running_on_standby_clock == 0U) && (timeout != 0U));
    4a42:	693b      	ldr	r3, [r7, #16]
    4a44:	2b00      	cmp	r3, #0
    4a46:	d102      	bne.n	4a4e <isp_page_read_handler+0x72>
    4a48:	68bb      	ldr	r3, [r7, #8]
    4a4a:	2b00      	cmp	r3, #0
    4a4c:	d1ec      	bne.n	4a28 <isp_page_read_handler+0x4c>
        wait_for_clock_switch = 0;
    4a4e:	f240 030c 	movw	r3, #12
    4a52:	f2c2 0300 	movt	r3, #8192	; 0x2000
    4a56:	f04f 0200 	mov.w	r2, #0
    4a5a:	701a      	strb	r2, [r3, #0]
        SYSREG->MSSDDR_FACC1_CR &= ~apb_divisors_mask;
    4a5c:	f248 0300 	movw	r3, #32768	; 0x8000
    4a60:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4a64:	f248 0200 	movw	r2, #32768	; 0x8000
    4a68:	f2c4 0203 	movt	r2, #16387	; 0x4003
    4a6c:	f8d2 1098 	ldr.w	r1, [r2, #152]	; 0x98
    4a70:	697a      	ldr	r2, [r7, #20]
    4a72:	ea6f 0202 	mvn.w	r2, r2
    4a76:	ea01 0202 	and.w	r2, r1, r2
    4a7a:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98
    }
    
    if(g_isp_page_read_handler != 0)
    4a7e:	f240 137c 	movw	r3, #380	; 0x17c
    4a82:	f2c2 0300 	movt	r3, #8192	; 0x2000
    4a86:	681b      	ldr	r3, [r3, #0]
    4a88:	2b00      	cmp	r3, #0
    4a8a:	d008      	beq.n	4a9e <isp_page_read_handler+0xc2>
    {
        remaining_length = g_isp_page_read_handler(pp_next_page);
    4a8c:	f240 137c 	movw	r3, #380	; 0x17c
    4a90:	f2c2 0300 	movt	r3, #8192	; 0x2000
    4a94:	681b      	ldr	r3, [r3, #0]
    4a96:	6878      	ldr	r0, [r7, #4]
    4a98:	4798      	blx	r3
    4a9a:	4603      	mov	r3, r0
    4a9c:	60fb      	str	r3, [r7, #12]
    }
    
    return remaining_length;
    4a9e:	68fb      	ldr	r3, [r7, #12]
}
    4aa0:	4618      	mov	r0, r3
    4aa2:	f107 0718 	add.w	r7, r7, #24
    4aa6:	46bd      	mov	sp, r7
    4aa8:	bd80      	pop	{r7, pc}
    4aaa:	bf00      	nop

00004aac <isp_sys_completion_handler>:
static void isp_sys_completion_handler
(
    uint8_t * p_response, 
    uint16_t length
)
{
    4aac:	b580      	push	{r7, lr}
    4aae:	b082      	sub	sp, #8
    4ab0:	af00      	add	r7, sp, #0
    4ab2:	6078      	str	r0, [r7, #4]
    4ab4:	460b      	mov	r3, r1
    4ab6:	807b      	strh	r3, [r7, #2]
    /*
     * Restore the eNVM's frequency range to the values used before ISP was
     * started.
     */
    SYSREG->ENVM_CR = g_initial_envm_cr;
    4ab8:	f248 0300 	movw	r3, #32768	; 0x8000
    4abc:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4ac0:	f240 0208 	movw	r2, #8
    4ac4:	f2c2 0200 	movt	r2, #8192	; 0x2000
    4ac8:	6812      	ldr	r2, [r2, #0]
    4aca:	60da      	str	r2, [r3, #12]
    
    /*
     * Restore the MSS DDR FACC 2 configuration to the values used before ISP 
     * was started.
     */
    SYSREG->MSSDDR_FACC2_CR = g_initial_mssddr_facc2_cr;
    4acc:	f248 0300 	movw	r3, #32768	; 0x8000
    4ad0:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4ad4:	f240 1280 	movw	r2, #384	; 0x180
    4ad8:	f2c2 0200 	movt	r2, #8192	; 0x2000
    4adc:	6812      	ldr	r2, [r2, #0]
    4ade:	f8c3 209c 	str.w	r2, [r3, #156]	; 0x9c
    
    if(g_isp_completion_handler != 0)
    4ae2:	f240 1378 	movw	r3, #376	; 0x178
    4ae6:	f2c2 0300 	movt	r3, #8192	; 0x2000
    4aea:	681b      	ldr	r3, [r3, #0]
    4aec:	2b00      	cmp	r3, #0
    4aee:	d00a      	beq.n	4b06 <isp_sys_completion_handler+0x5a>
    {
        g_isp_completion_handler(p_response[1]);
    4af0:	f240 1378 	movw	r3, #376	; 0x178
    4af4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    4af8:	681b      	ldr	r3, [r3, #0]
    4afa:	687a      	ldr	r2, [r7, #4]
    4afc:	f102 0201 	add.w	r2, r2, #1
    4b00:	7812      	ldrb	r2, [r2, #0]
    4b02:	4610      	mov	r0, r2
    4b04:	4798      	blx	r3
    }
}
    4b06:	f107 0708 	add.w	r7, r7, #8
    4b0a:	46bd      	mov	sp, r7
    4b0c:	bd80      	pop	{r7, pc}
    4b0e:	bf00      	nop

00004b10 <MSS_SYS_start_isp>:
(
    uint8_t mode,
    comblk_page_handler_t page_read_handler,
    sys_serv_isp_complete_handler_t isp_completion_handler
)
{
    4b10:	b580      	push	{r7, lr}
    4b12:	b088      	sub	sp, #32
    4b14:	af02      	add	r7, sp, #8
    4b16:	4603      	mov	r3, r0
    4b18:	60b9      	str	r1, [r7, #8]
    4b1a:	607a      	str	r2, [r7, #4]
    4b1c:	73fb      	strb	r3, [r7, #15]
    uint8_t isp_prog_request[2];
        
    if(mode == MSS_SYS_PROG_VERIFY)
    4b1e:	7bfb      	ldrb	r3, [r7, #15]
    4b20:	2b02      	cmp	r3, #2
    4b22:	d103      	bne.n	4b2c <MSS_SYS_start_isp+0x1c>
    {
        /*
         * Check fabric digest before performing ISP verify
         */
        MSS_SYS_check_digest(MSS_SYS_DIGEST_CHECK_FABRIC);
    4b24:	f04f 0001 	mov.w	r0, #1
    4b28:	f000 f952 	bl	4dd0 <MSS_SYS_check_digest>
    /*
     * Keep a copy of the initial eNVM configuration used before ISP was
     * initiated. The eNVM configuration will be restored, as part of the ISP
     * completion handler, when ISP completes.
     */
    g_initial_envm_cr = SYSREG->ENVM_CR;
    4b2c:	f248 0300 	movw	r3, #32768	; 0x8000
    4b30:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4b34:	68da      	ldr	r2, [r3, #12]
    4b36:	f240 0308 	movw	r3, #8
    4b3a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    4b3e:	601a      	str	r2, [r3, #0]
    
    /* Store the MSS DDR FACC 2 register value so that its can be restored back 
     * when the ISP operation is completed.asynchronous_event_handler. */
    g_initial_mssddr_facc2_cr = SYSREG->MSSDDR_FACC2_CR;
    4b40:	f248 0300 	movw	r3, #32768	; 0x8000
    4b44:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4b48:	f8d3 209c 	ldr.w	r2, [r3, #156]	; 0x9c
    4b4c:	f240 1380 	movw	r3, #384	; 0x180
    4b50:	f2c2 0300 	movt	r3, #8192	; 0x2000
    4b54:	601a      	str	r2, [r3, #0]

    /*
     * Set the eNVM's frequency range to its maximum. This is required to ensure
     * successful eNVM programming on all devices.
     */
    SYSREG->ENVM_CR = (g_initial_envm_cr & ~NVM_FREQRNG_MASK) | NVM_FREQRNG_MAX;
    4b56:	f248 0300 	movw	r3, #32768	; 0x8000
    4b5a:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4b5e:	f240 0208 	movw	r2, #8
    4b62:	f2c2 0200 	movt	r2, #8192	; 0x2000
    4b66:	6812      	ldr	r2, [r2, #0]
    4b68:	f442 52ff 	orr.w	r2, r2, #8160	; 0x1fe0
    4b6c:	60da      	str	r2, [r3, #12]
    
    g_mode = mode;
    4b6e:	f240 1384 	movw	r3, #388	; 0x184
    4b72:	f2c2 0300 	movt	r3, #8192	; 0x2000
    4b76:	7bfa      	ldrb	r2, [r7, #15]
    4b78:	701a      	strb	r2, [r3, #0]
    
    if(mode != MSS_SYS_PROG_AUTHENTICATE)
    4b7a:	7bfb      	ldrb	r3, [r7, #15]
    4b7c:	2b00      	cmp	r3, #0
    4b7e:	d030      	beq.n	4be2 <MSS_SYS_start_isp+0xd2>
    {  
        /* Select output of MUX 0, MUX 1 and MUX 2 during standby */
        SYSREG->MSSDDR_FACC2_CR = SYSREG->MSSDDR_FACC2_CR & ((uint32_t)(FACC_STANDBY_SEL << FACC_STANDBY_SHIFT) & FACC_STANDBY_SEL_MASK);
    4b80:	f248 0300 	movw	r3, #32768	; 0x8000
    4b84:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4b88:	f8d3 309c 	ldr.w	r3, [r3, #156]	; 0x9c
    4b8c:	f248 0300 	movw	r3, #32768	; 0x8000
    4b90:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4b94:	f04f 0200 	mov.w	r2, #0
    4b98:	f8c3 209c 	str.w	r2, [r3, #156]	; 0x9c
        
        /* Enable the signal for the 50 MHz RC oscillator */
        SYSREG->MSSDDR_FACC2_CR = SYSREG->MSSDDR_FACC2_CR | ((uint32_t)(MSS_25_50MHZ_EN << MSS_25_50MHZ_EN_SHIFT) & MSS_25_50MHZ_EN_MASK);
    4b9c:	f248 0300 	movw	r3, #32768	; 0x8000
    4ba0:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4ba4:	f248 0200 	movw	r2, #32768	; 0x8000
    4ba8:	f2c4 0203 	movt	r2, #16387	; 0x4003
    4bac:	f8d2 209c 	ldr.w	r2, [r2, #156]	; 0x9c
    4bb0:	f442 7200 	orr.w	r2, r2, #512	; 0x200
    4bb4:	f8c3 209c 	str.w	r2, [r3, #156]	; 0x9c
        
        /* Enable the signal for the 1 MHz RC oscillator */
        SYSREG->MSSDDR_FACC2_CR = SYSREG->MSSDDR_FACC2_CR | ((uint32_t)(MSS_1MHZ_EN << MSS_1MHZ_EN_SHIFT) & MSS_1MHZ_EN_MASK);
    4bb8:	f248 0300 	movw	r3, #32768	; 0x8000
    4bbc:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4bc0:	f248 0200 	movw	r2, #32768	; 0x8000
    4bc4:	f2c4 0203 	movt	r2, #16387	; 0x4003
    4bc8:	f8d2 209c 	ldr.w	r2, [r2, #156]	; 0x9c
    4bcc:	f442 6280 	orr.w	r2, r2, #1024	; 0x400
    4bd0:	f8c3 209c 	str.w	r2, [r3, #156]	; 0x9c
        
        wait_for_clock_switch = 1;
    4bd4:	f240 030c 	movw	r3, #12
    4bd8:	f2c2 0300 	movt	r3, #8192	; 0x2000
    4bdc:	f04f 0201 	mov.w	r2, #1
    4be0:	701a      	strb	r2, [r3, #0]
    }
    
    signal_request_start();
    4be2:	f001 f8b1 	bl	5d48 <signal_request_start>
    
    isp_prog_request[0] = ISP_PROGRAMMING_REQUEST_CMD;
    4be6:	f04f 0315 	mov.w	r3, #21
    4bea:	753b      	strb	r3, [r7, #20]
    isp_prog_request[1] = mode;
    4bec:	7bfb      	ldrb	r3, [r7, #15]
    4bee:	757b      	strb	r3, [r7, #21]
    
    g_isp_completion_handler = isp_completion_handler;
    4bf0:	f240 1378 	movw	r3, #376	; 0x178
    4bf4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    4bf8:	687a      	ldr	r2, [r7, #4]
    4bfa:	601a      	str	r2, [r3, #0]
    
    g_isp_page_read_handler = page_read_handler;
    4bfc:	f240 137c 	movw	r3, #380	; 0x17c
    4c00:	f2c2 0300 	movt	r3, #8192	; 0x2000
    4c04:	68ba      	ldr	r2, [r7, #8]
    4c06:	601a      	str	r2, [r3, #0]
    
    MSS_COMBLK_send_paged_cmd(isp_prog_request,                 /* p_cmd */
    4c08:	f107 0214 	add.w	r2, r7, #20
    4c0c:	f644 13dd 	movw	r3, #18909	; 0x49dd
    4c10:	f2c0 0300 	movt	r3, #0
    4c14:	9300      	str	r3, [sp, #0]
    4c16:	f644 23ad 	movw	r3, #19117	; 0x4aad
    4c1a:	f2c0 0300 	movt	r3, #0
    4c1e:	9301      	str	r3, [sp, #4]
    4c20:	4610      	mov	r0, r2
    4c22:	f04f 0102 	mov.w	r1, #2
    4c26:	f240 1274 	movw	r2, #372	; 0x174
    4c2a:	f2c2 0200 	movt	r2, #8192	; 0x2000
    4c2e:	f04f 0302 	mov.w	r3, #2
    4c32:	f7fe fcff 	bl	3634 <MSS_COMBLK_send_paged_cmd>
                              sizeof(isp_prog_request),         /* cmd_size */
                              g_isp_response,                   /* p_response */
                              ISP_PROG_SERV_RESP_LENGTH,        /* response_size */
                              isp_page_read_handler,            /* page_handler */
                              isp_sys_completion_handler);      /* completion_handler */
}
    4c36:	f107 0718 	add.w	r7, r7, #24
    4c3a:	46bd      	mov	sp, r7
    4c3c:	bd80      	pop	{r7, pc}
    4c3e:	bf00      	nop

00004c40 <MSS_SYS_initiate_iap>:
uint8_t MSS_SYS_initiate_iap
(
    uint8_t mode,
    uint32_t bitstream_spi_addr
)
{
    4c40:	b580      	push	{r7, lr}
    4c42:	b08a      	sub	sp, #40	; 0x28
    4c44:	af04      	add	r7, sp, #16
    4c46:	4603      	mov	r3, r0
    4c48:	6039      	str	r1, [r7, #0]
    4c4a:	71fb      	strb	r3, [r7, #7]
    uint8_t status;
    uint16_t actual_response_length;
    uint8_t iap_prog_req[6];
    uint8_t response[IAP_PROG_SERV_RESP_LENGTH];
    
    if(mode == MSS_SYS_PROG_VERIFY)
    4c4c:	79fb      	ldrb	r3, [r7, #7]
    4c4e:	2b02      	cmp	r3, #2
    4c50:	d103      	bne.n	4c5a <MSS_SYS_initiate_iap+0x1a>
    {
        /*
         * Check fabric digest before performing IAP verify
         */
        MSS_SYS_check_digest(MSS_SYS_DIGEST_CHECK_FABRIC);
    4c52:	f04f 0001 	mov.w	r0, #1
    4c56:	f000 f8bb 	bl	4dd0 <MSS_SYS_check_digest>
    /*
     * Keep a copy of the initial eNVM configuration used before IAP was
     * initiated. The eNVM configuration will be restored, as part of the IAP
     * completion handler, when IAP completes.
     */
    g_initial_envm_cr = SYSREG->ENVM_CR;
    4c5a:	f248 0300 	movw	r3, #32768	; 0x8000
    4c5e:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4c62:	68da      	ldr	r2, [r3, #12]
    4c64:	f240 0308 	movw	r3, #8
    4c68:	f2c2 0300 	movt	r3, #8192	; 0x2000
    4c6c:	601a      	str	r2, [r3, #0]

    /* Store the MSS DDR FACC 2 register value so that its can be restored back 
     * when the IAP operation is completed.asynchronous_event_handler. */
    g_initial_mssddr_facc2_cr = SYSREG->MSSDDR_FACC2_CR;
    4c6e:	f248 0300 	movw	r3, #32768	; 0x8000
    4c72:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4c76:	f8d3 209c 	ldr.w	r2, [r3, #156]	; 0x9c
    4c7a:	f240 1380 	movw	r3, #384	; 0x180
    4c7e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    4c82:	601a      	str	r2, [r3, #0]
    
    /*
     * Keep track of the clocks configuration before issuing IAP command so
     * that it can be restored on completion of IAP service.
     */
    g_initial_mssddr_facc1_cr = SYSREG->MSSDDR_FACC1_CR;
    4c84:	f248 0300 	movw	r3, #32768	; 0x8000
    4c88:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4c8c:	f8d3 2098 	ldr.w	r2, [r3, #152]	; 0x98
    4c90:	f240 1370 	movw	r3, #368	; 0x170
    4c94:	f2c2 0300 	movt	r3, #8192	; 0x2000
    4c98:	601a      	str	r2, [r3, #0]
    
    /*
     * Set the eNVM's frequency range to its maximum. This is required to ensure
     * successful eNVM programming on all devices.
     */
    SYSREG->ENVM_CR = (g_initial_envm_cr & ~NVM_FREQRNG_MASK) | NVM_FREQRNG_MAX;
    4c9a:	f248 0300 	movw	r3, #32768	; 0x8000
    4c9e:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4ca2:	f240 0208 	movw	r2, #8
    4ca6:	f2c2 0200 	movt	r2, #8192	; 0x2000
    4caa:	6812      	ldr	r2, [r2, #0]
    4cac:	f442 52ff 	orr.w	r2, r2, #8160	; 0x1fe0
    4cb0:	60da      	str	r2, [r3, #12]

    /* Select output of MUX 0, MUX 1 and MUX 2 during standby */
    SYSREG->MSSDDR_FACC2_CR = SYSREG->MSSDDR_FACC2_CR & ((uint32_t)(FACC_STANDBY_SEL << FACC_STANDBY_SHIFT) & FACC_STANDBY_SEL_MASK);
    4cb2:	f248 0300 	movw	r3, #32768	; 0x8000
    4cb6:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4cba:	f8d3 309c 	ldr.w	r3, [r3, #156]	; 0x9c
    4cbe:	f248 0300 	movw	r3, #32768	; 0x8000
    4cc2:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4cc6:	f04f 0200 	mov.w	r2, #0
    4cca:	f8c3 209c 	str.w	r2, [r3, #156]	; 0x9c
    
    /* Enable the signal for the 50 MHz RC oscillator */
    SYSREG->MSSDDR_FACC2_CR = SYSREG->MSSDDR_FACC2_CR | ((uint32_t)(MSS_25_50MHZ_EN << MSS_25_50MHZ_EN_SHIFT) & MSS_25_50MHZ_EN_MASK);
    4cce:	f248 0300 	movw	r3, #32768	; 0x8000
    4cd2:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4cd6:	f248 0200 	movw	r2, #32768	; 0x8000
    4cda:	f2c4 0203 	movt	r2, #16387	; 0x4003
    4cde:	f8d2 209c 	ldr.w	r2, [r2, #156]	; 0x9c
    4ce2:	f442 7200 	orr.w	r2, r2, #512	; 0x200
    4ce6:	f8c3 209c 	str.w	r2, [r3, #156]	; 0x9c
    
    /* Enable the signal for the 1 MHz RC oscillator */
    SYSREG->MSSDDR_FACC2_CR = SYSREG->MSSDDR_FACC2_CR | ((uint32_t)(MSS_1MHZ_EN << MSS_1MHZ_EN_SHIFT) & MSS_1MHZ_EN_MASK);
    4cea:	f248 0300 	movw	r3, #32768	; 0x8000
    4cee:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4cf2:	f248 0200 	movw	r2, #32768	; 0x8000
    4cf6:	f2c4 0203 	movt	r2, #16387	; 0x4003
    4cfa:	f8d2 209c 	ldr.w	r2, [r2, #156]	; 0x9c
    4cfe:	f442 6280 	orr.w	r2, r2, #1024	; 0x400
    4d02:	f8c3 209c 	str.w	r2, [r3, #156]	; 0x9c
    
    /*
     * There is no response for Program mode because the Cortex-M3 will
     * get reset on completion of the system service.
     */
    iap_prog_req[0] = IAP_PROGRAMMING_REQUEST_CMD;
    4d06:	f04f 0314 	mov.w	r3, #20
    4d0a:	733b      	strb	r3, [r7, #12]
    iap_prog_req[1] = mode;
    4d0c:	79fb      	ldrb	r3, [r7, #7]
    4d0e:	737b      	strb	r3, [r7, #13]

    iap_prog_req[2] = (uint8_t)(bitstream_spi_addr);
    4d10:	683b      	ldr	r3, [r7, #0]
    4d12:	b2db      	uxtb	r3, r3
    4d14:	73bb      	strb	r3, [r7, #14]
    iap_prog_req[3] = (uint8_t)(bitstream_spi_addr >> 8u);
    4d16:	683b      	ldr	r3, [r7, #0]
    4d18:	ea4f 2313 	mov.w	r3, r3, lsr #8
    4d1c:	b2db      	uxtb	r3, r3
    4d1e:	73fb      	strb	r3, [r7, #15]
    iap_prog_req[4] = (uint8_t)(bitstream_spi_addr >> 16u);
    4d20:	683b      	ldr	r3, [r7, #0]
    4d22:	ea4f 4313 	mov.w	r3, r3, lsr #16
    4d26:	b2db      	uxtb	r3, r3
    4d28:	743b      	strb	r3, [r7, #16]
    iap_prog_req[5] = (uint8_t)(bitstream_spi_addr >> 24u);
    4d2a:	683b      	ldr	r3, [r7, #0]
    4d2c:	ea4f 6313 	mov.w	r3, r3, lsr #24
    4d30:	b2db      	uxtb	r3, r3
    4d32:	747b      	strb	r3, [r7, #17]

    signal_request_start();
    4d34:	f001 f808 	bl	5d48 <signal_request_start>
    
    MSS_COMBLK_send_cmd(iap_prog_req,                   /* p_cmd */
    4d38:	f107 020c 	add.w	r2, r7, #12
    4d3c:	f107 0308 	add.w	r3, r7, #8
    4d40:	9300      	str	r3, [sp, #0]
    4d42:	f04f 0302 	mov.w	r3, #2
    4d46:	9301      	str	r3, [sp, #4]
    4d48:	f645 5319 	movw	r3, #23833	; 0x5d19
    4d4c:	f2c0 0300 	movt	r3, #0
    4d50:	9302      	str	r3, [sp, #8]
    4d52:	4610      	mov	r0, r2
    4d54:	f04f 0106 	mov.w	r1, #6
    4d58:	f04f 0200 	mov.w	r2, #0
    4d5c:	f04f 0300 	mov.w	r3, #0
    4d60:	f7fe fb92 	bl	3488 <MSS_COMBLK_send_cmd>
                        request_completion_handler);    /* completion_handler */
        
    /*
     * Handle case where service is not implemented/enabled in the device.
     */
    actual_response_length = wait_for_request_completion();
    4d64:	f001 f80c 	bl	5d80 <wait_for_request_completion>
    4d68:	4603      	mov	r3, r0
    4d6a:	82fb      	strh	r3, [r7, #22]
    
    if((IAP_PROG_SERV_RESP_LENGTH == actual_response_length) &&
    4d6c:	8afb      	ldrh	r3, [r7, #22]
    4d6e:	2b02      	cmp	r3, #2
    4d70:	d105      	bne.n	4d7e <MSS_SYS_initiate_iap+0x13e>
       (IAP_PROGRAMMING_REQUEST_CMD == response[0]))
    4d72:	7a3b      	ldrb	r3, [r7, #8]
    /*
     * Handle case where service is not implemented/enabled in the device.
     */
    actual_response_length = wait_for_request_completion();
    
    if((IAP_PROG_SERV_RESP_LENGTH == actual_response_length) &&
    4d74:	2b14      	cmp	r3, #20
    4d76:	d102      	bne.n	4d7e <MSS_SYS_initiate_iap+0x13e>
       (IAP_PROGRAMMING_REQUEST_CMD == response[0]))
    {
        status = response[1];
    4d78:	7a7b      	ldrb	r3, [r7, #9]
    4d7a:	757b      	strb	r3, [r7, #21]
    /*
     * Handle case where service is not implemented/enabled in the device.
     */
    actual_response_length = wait_for_request_completion();
    
    if((IAP_PROG_SERV_RESP_LENGTH == actual_response_length) &&
    4d7c:	e002      	b.n	4d84 <MSS_SYS_initiate_iap+0x144>
    {
        status = response[1];
    }
    else
    {
        status = MSS_SYS_UNEXPECTED_ERROR;
    4d7e:	f06f 0337 	mvn.w	r3, #55	; 0x37
    4d82:	757b      	strb	r3, [r7, #21]
    }
    
    /* Restore back to original value. */
    SYSREG->ENVM_CR = g_initial_envm_cr;
    4d84:	f248 0300 	movw	r3, #32768	; 0x8000
    4d88:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4d8c:	f240 0208 	movw	r2, #8
    4d90:	f2c2 0200 	movt	r2, #8192	; 0x2000
    4d94:	6812      	ldr	r2, [r2, #0]
    4d96:	60da      	str	r2, [r3, #12]
    SYSREG->MSSDDR_FACC2_CR = g_initial_mssddr_facc2_cr;
    4d98:	f248 0300 	movw	r3, #32768	; 0x8000
    4d9c:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4da0:	f240 1280 	movw	r2, #384	; 0x180
    4da4:	f2c2 0200 	movt	r2, #8192	; 0x2000
    4da8:	6812      	ldr	r2, [r2, #0]
    4daa:	f8c3 209c 	str.w	r2, [r3, #156]	; 0x9c
    SYSREG->MSSDDR_FACC1_CR = g_initial_mssddr_facc1_cr;
    4dae:	f248 0300 	movw	r3, #32768	; 0x8000
    4db2:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4db6:	f240 1270 	movw	r2, #368	; 0x170
    4dba:	f2c2 0200 	movt	r2, #8192	; 0x2000
    4dbe:	6812      	ldr	r2, [r2, #0]
    4dc0:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98

    return status;
    4dc4:	7d7b      	ldrb	r3, [r7, #21]
}
    4dc6:	4618      	mov	r0, r3
    4dc8:	f107 0718 	add.w	r7, r7, #24
    4dcc:	46bd      	mov	sp, r7
    4dce:	bd80      	pop	{r7, pc}

00004dd0 <MSS_SYS_check_digest>:
 */
uint8_t MSS_SYS_check_digest
(
    uint8_t options
)
{
    4dd0:	b580      	push	{r7, lr}
    4dd2:	b08a      	sub	sp, #40	; 0x28
    4dd4:	af04      	add	r7, sp, #16
    4dd6:	4603      	mov	r3, r0
    4dd8:	71fb      	strb	r3, [r7, #7]
    uint8_t response[DIGEST_CHECK_SERV_RESP_LENGTH];
    
    /*
     * The Digest Check system service is not available on M2S050 rev A, rev B and rev C.
     */
    ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION);
    4dda:	f248 0300 	movw	r3, #32768	; 0x8000
    4dde:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4de2:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    4de6:	f64f 0302 	movw	r3, #63490	; 0xf802
    4dea:	429a      	cmp	r2, r3
    4dec:	d100      	bne.n	4df0 <MSS_SYS_check_digest+0x20>
    4dee:	be00      	bkpt	0x0000
    ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION);
    4df0:	f248 0300 	movw	r3, #32768	; 0x8000
    4df4:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4df8:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    4dfc:	f64f 0302 	movw	r3, #63490	; 0xf802
    4e00:	f2c0 0301 	movt	r3, #1
    4e04:	429a      	cmp	r2, r3
    4e06:	d100      	bne.n	4e0a <MSS_SYS_check_digest+0x3a>
    4e08:	be00      	bkpt	0x0000
    ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION);
    4e0a:	f248 0300 	movw	r3, #32768	; 0x8000
    4e0e:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4e12:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    4e16:	f64f 0302 	movw	r3, #63490	; 0xf802
    4e1a:	f2c0 0302 	movt	r3, #2
    4e1e:	429a      	cmp	r2, r3
    4e20:	d100      	bne.n	4e24 <MSS_SYS_check_digest+0x54>
    4e22:	be00      	bkpt	0x0000
    
    /* 
     * Private ENVM factory digest and user digest is available only on G4X 
     * devices
     */
    if((options & 0x30u) != 0x00)
    4e24:	79fb      	ldrb	r3, [r7, #7]
    4e26:	f003 0330 	and.w	r3, r3, #48	; 0x30
    4e2a:	2b00      	cmp	r3, #0
    4e2c:	d00c      	beq.n	4e48 <MSS_SYS_check_digest+0x78>
    {
        ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION);
    4e2e:	f248 0300 	movw	r3, #32768	; 0x8000
    4e32:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4e36:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    4e3a:	f64f 0302 	movw	r3, #63490	; 0xf802
    4e3e:	f2c0 0302 	movt	r3, #2
    4e42:	429a      	cmp	r2, r3
    4e44:	d100      	bne.n	4e48 <MSS_SYS_check_digest+0x78>
    4e46:	be00      	bkpt	0x0000
    }
    
    signal_request_start();
    4e48:	f000 ff7e 	bl	5d48 <signal_request_start>
    
    digest_check_req[0] = DIGEST_CHECK_REQUEST_CMD;
    4e4c:	f04f 0317 	mov.w	r3, #23
    4e50:	743b      	strb	r3, [r7, #16]
    digest_check_req[1] = options;
    4e52:	79fb      	ldrb	r3, [r7, #7]
    4e54:	747b      	strb	r3, [r7, #17]

    MSS_COMBLK_send_cmd(digest_check_req,               /* p_cmd */
    4e56:	f107 0210 	add.w	r2, r7, #16
    4e5a:	f107 030c 	add.w	r3, r7, #12
    4e5e:	9300      	str	r3, [sp, #0]
    4e60:	f04f 0302 	mov.w	r3, #2
    4e64:	9301      	str	r3, [sp, #4]
    4e66:	f645 5319 	movw	r3, #23833	; 0x5d19
    4e6a:	f2c0 0300 	movt	r3, #0
    4e6e:	9302      	str	r3, [sp, #8]
    4e70:	4610      	mov	r0, r2
    4e72:	f04f 0102 	mov.w	r1, #2
    4e76:	f04f 0200 	mov.w	r2, #0
    4e7a:	f04f 0300 	mov.w	r3, #0
    4e7e:	f7fe fb03 	bl	3488 <MSS_COMBLK_send_cmd>
                        0u,                             /* data_size */
                        response,                       /* p_response */
                        DIGEST_CHECK_SERV_RESP_LENGTH,  /* response_size */
                        request_completion_handler);    /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    4e82:	f000 ff7d 	bl	5d80 <wait_for_request_completion>
    4e86:	4603      	mov	r3, r0
    4e88:	82fb      	strh	r3, [r7, #22]
    
    if((DIGEST_CHECK_SERV_RESP_LENGTH == actual_response_length) &&
    4e8a:	8afb      	ldrh	r3, [r7, #22]
    4e8c:	2b02      	cmp	r3, #2
    4e8e:	d105      	bne.n	4e9c <MSS_SYS_check_digest+0xcc>
       (DIGEST_CHECK_REQUEST_CMD == response[0]))
    4e90:	7b3b      	ldrb	r3, [r7, #12]
                        DIGEST_CHECK_SERV_RESP_LENGTH,  /* response_size */
                        request_completion_handler);    /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    
    if((DIGEST_CHECK_SERV_RESP_LENGTH == actual_response_length) &&
    4e92:	2b17      	cmp	r3, #23
    4e94:	d102      	bne.n	4e9c <MSS_SYS_check_digest+0xcc>
       (DIGEST_CHECK_REQUEST_CMD == response[0]))
    {
        status = response[1];
    4e96:	7b7b      	ldrb	r3, [r7, #13]
    4e98:	757b      	strb	r3, [r7, #21]
                        DIGEST_CHECK_SERV_RESP_LENGTH,  /* response_size */
                        request_completion_handler);    /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    
    if((DIGEST_CHECK_SERV_RESP_LENGTH == actual_response_length) &&
    4e9a:	e002      	b.n	4ea2 <MSS_SYS_check_digest+0xd2>
    {
        status = response[1];
    }
    else
    {
        status = MSS_SYS_UNEXPECTED_ERROR;
    4e9c:	f06f 0337 	mvn.w	r3, #55	; 0x37
    4ea0:	757b      	strb	r3, [r7, #21]
    }
    
    return status;
    4ea2:	7d7b      	ldrb	r3, [r7, #21]
}
    4ea4:	4618      	mov	r0, r3
    4ea6:	f107 0718 	add.w	r7, r7, #24
    4eaa:	46bd      	mov	sp, r7
    4eac:	bd80      	pop	{r7, pc}
    4eae:	bf00      	nop

00004eb0 <MSS_SYS_puf_create_activation_code>:
 */
uint8_t MSS_SYS_puf_create_activation_code
(
    void
)
{
    4eb0:	b580      	push	{r7, lr}
    4eb2:	b082      	sub	sp, #8
    4eb4:	af00      	add	r7, sp, #0
    uint8_t response[PUF_USER_ACTIVATION_CODE_RESP_LENGTH];
    uint8_t status;
    uint8_t params;
    uint8_t key_numbers = 0u;
    4eb6:	f04f 0300 	mov.w	r3, #0
    4eba:	70bb      	strb	r3, [r7, #2]
    
    /*
     * The user activation code system service is not available on M2S050 rev A,
     * rev B, rev C and rev D.
     */
    ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION);
    4ebc:	f248 0300 	movw	r3, #32768	; 0x8000
    4ec0:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4ec4:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    4ec8:	f64f 0302 	movw	r3, #63490	; 0xf802
    4ecc:	429a      	cmp	r2, r3
    4ece:	d100      	bne.n	4ed2 <MSS_SYS_puf_create_activation_code+0x22>
    4ed0:	be00      	bkpt	0x0000
    ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION);
    4ed2:	f248 0300 	movw	r3, #32768	; 0x8000
    4ed6:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4eda:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    4ede:	f64f 0302 	movw	r3, #63490	; 0xf802
    4ee2:	f2c0 0301 	movt	r3, #1
    4ee6:	429a      	cmp	r2, r3
    4ee8:	d100      	bne.n	4eec <MSS_SYS_puf_create_activation_code+0x3c>
    4eea:	be00      	bkpt	0x0000
    ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION);
    4eec:	f248 0300 	movw	r3, #32768	; 0x8000
    4ef0:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4ef4:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    4ef8:	f64f 0302 	movw	r3, #63490	; 0xf802
    4efc:	f2c0 0302 	movt	r3, #2
    4f00:	429a      	cmp	r2, r3
    4f02:	d100      	bne.n	4f06 <MSS_SYS_puf_create_activation_code+0x56>
    4f04:	be00      	bkpt	0x0000
    ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION);
    4f06:	f248 0300 	movw	r3, #32768	; 0x8000
    4f0a:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4f0e:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    4f12:	f64f 0302 	movw	r3, #63490	; 0xf802
    4f16:	f2c0 0303 	movt	r3, #3
    4f1a:	429a      	cmp	r2, r3
    4f1c:	d100      	bne.n	4f20 <MSS_SYS_puf_create_activation_code+0x70>
    4f1e:	be00      	bkpt	0x0000

    params = PUF_CREATE_USER_ACTIVATION_CODE;
    4f20:	f04f 0300 	mov.w	r3, #0
    4f24:	70fb      	strb	r3, [r7, #3]
    
    status = execute_service(PUF_ACTIVATION_CODE_REQUEST_CMD,
    4f26:	f107 0203 	add.w	r2, r7, #3
    4f2a:	f107 0304 	add.w	r3, r7, #4
    4f2e:	f04f 0019 	mov.w	r0, #25
    4f32:	4611      	mov	r1, r2
    4f34:	461a      	mov	r2, r3
    4f36:	f04f 0302 	mov.w	r3, #2
    4f3a:	f000 feb7 	bl	5cac <execute_service>
    4f3e:	4603      	mov	r3, r0
    4f40:	71fb      	strb	r3, [r7, #7]
     * code service, but system controller is not releasing back after 
     * completing the operation. In order to unlock eNVM-1, call get number of 
     * key service. PUF get number of key service will release the eNVM-1 lock
     * after reading the number of keys enrolled.
     */
    MSS_SYS_puf_get_number_of_keys(&key_numbers);
    4f42:	f107 0302 	add.w	r3, r7, #2
    4f46:	4618      	mov	r0, r3
    4f48:	f000 f85a 	bl	5000 <MSS_SYS_puf_get_number_of_keys>
    
    return status;
    4f4c:	79fb      	ldrb	r3, [r7, #7]
}
    4f4e:	4618      	mov	r0, r3
    4f50:	f107 0708 	add.w	r7, r7, #8
    4f54:	46bd      	mov	sp, r7
    4f56:	bd80      	pop	{r7, pc}

00004f58 <MSS_SYS_puf_delete_activation_code>:
 */
uint8_t MSS_SYS_puf_delete_activation_code
(
    void
)
{
    4f58:	b580      	push	{r7, lr}
    4f5a:	b082      	sub	sp, #8
    4f5c:	af00      	add	r7, sp, #0
    uint8_t response[PUF_USER_ACTIVATION_CODE_RESP_LENGTH];
    uint8_t status;
    uint8_t params;
    uint8_t key_numbers = 0u;
    4f5e:	f04f 0300 	mov.w	r3, #0
    4f62:	70bb      	strb	r3, [r7, #2]
    
    /*
     * The user activation code system service is not available on M2S050 rev A,
     * rev B, rev C and rev D.
     */
    ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION);
    4f64:	f248 0300 	movw	r3, #32768	; 0x8000
    4f68:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4f6c:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    4f70:	f64f 0302 	movw	r3, #63490	; 0xf802
    4f74:	429a      	cmp	r2, r3
    4f76:	d100      	bne.n	4f7a <MSS_SYS_puf_delete_activation_code+0x22>
    4f78:	be00      	bkpt	0x0000
    ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION);
    4f7a:	f248 0300 	movw	r3, #32768	; 0x8000
    4f7e:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4f82:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    4f86:	f64f 0302 	movw	r3, #63490	; 0xf802
    4f8a:	f2c0 0301 	movt	r3, #1
    4f8e:	429a      	cmp	r2, r3
    4f90:	d100      	bne.n	4f94 <MSS_SYS_puf_delete_activation_code+0x3c>
    4f92:	be00      	bkpt	0x0000
    ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION);
    4f94:	f248 0300 	movw	r3, #32768	; 0x8000
    4f98:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4f9c:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    4fa0:	f64f 0302 	movw	r3, #63490	; 0xf802
    4fa4:	f2c0 0302 	movt	r3, #2
    4fa8:	429a      	cmp	r2, r3
    4faa:	d100      	bne.n	4fae <MSS_SYS_puf_delete_activation_code+0x56>
    4fac:	be00      	bkpt	0x0000
    ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION);
    4fae:	f248 0300 	movw	r3, #32768	; 0x8000
    4fb2:	f2c4 0303 	movt	r3, #16387	; 0x4003
    4fb6:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    4fba:	f64f 0302 	movw	r3, #63490	; 0xf802
    4fbe:	f2c0 0303 	movt	r3, #3
    4fc2:	429a      	cmp	r2, r3
    4fc4:	d100      	bne.n	4fc8 <MSS_SYS_puf_delete_activation_code+0x70>
    4fc6:	be00      	bkpt	0x0000
    
    params = PUF_DELETE_USER_ACTIVATION_CODE;
    4fc8:	f04f 0301 	mov.w	r3, #1
    4fcc:	70fb      	strb	r3, [r7, #3]
    
    status = execute_service(PUF_ACTIVATION_CODE_REQUEST_CMD,
    4fce:	f107 0203 	add.w	r2, r7, #3
    4fd2:	f107 0304 	add.w	r3, r7, #4
    4fd6:	f04f 0019 	mov.w	r0, #25
    4fda:	4611      	mov	r1, r2
    4fdc:	461a      	mov	r2, r3
    4fde:	f04f 0302 	mov.w	r3, #2
    4fe2:	f000 fe63 	bl	5cac <execute_service>
    4fe6:	4603      	mov	r3, r0
    4fe8:	71fb      	strb	r3, [r7, #7]
     * code service, but system controller is not releasing back after 
     * completing the operation. In order to unlock eNVM-1, call get number of 
     * key service. PUF get number of key service will release the eNVM-1 lock
     * after reading the number of keys enrolled.
     */
    MSS_SYS_puf_get_number_of_keys(&key_numbers);
    4fea:	f107 0302 	add.w	r3, r7, #2
    4fee:	4618      	mov	r0, r3
    4ff0:	f000 f806 	bl	5000 <MSS_SYS_puf_get_number_of_keys>
    
    return status;
    4ff4:	79fb      	ldrb	r3, [r7, #7]
}
    4ff6:	4618      	mov	r0, r3
    4ff8:	f107 0708 	add.w	r7, r7, #8
    4ffc:	46bd      	mov	sp, r7
    4ffe:	bd80      	pop	{r7, pc}

00005000 <MSS_SYS_puf_get_number_of_keys>:
 */
uint8_t MSS_SYS_puf_get_number_of_keys
(
    uint8_t* p_number_of_keys
)
{
    5000:	b580      	push	{r7, lr}
    5002:	b088      	sub	sp, #32
    5004:	af00      	add	r7, sp, #0
    5006:	6078      	str	r0, [r7, #4]
    uint8_t response[6u] = { 0x00 };
    5008:	f04f 0300 	mov.w	r3, #0
    500c:	61bb      	str	r3, [r7, #24]
    500e:	f04f 0300 	mov.w	r3, #0
    5012:	83bb      	strh	r3, [r7, #28]
    uint8_t params[11u] =  { 0x00 };
    5014:	f107 030c 	add.w	r3, r7, #12
    5018:	f04f 0200 	mov.w	r2, #0
    501c:	601a      	str	r2, [r3, #0]
    501e:	f103 0304 	add.w	r3, r3, #4
    5022:	f04f 0200 	mov.w	r2, #0
    5026:	601a      	str	r2, [r3, #0]
    5028:	f103 0304 	add.w	r3, r3, #4
    502c:	f04f 0200 	mov.w	r2, #0
    5030:	801a      	strh	r2, [r3, #0]
    5032:	f103 0302 	add.w	r3, r3, #2
    5036:	f04f 0200 	mov.w	r2, #0
    503a:	701a      	strb	r2, [r3, #0]
    503c:	f103 0301 	add.w	r3, r3, #1
    
    /*
     * The user key code system service is not available on M2S050 rev A,
     * rev B, rev C and rev D.
     */
    ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION);
    5040:	f248 0300 	movw	r3, #32768	; 0x8000
    5044:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5048:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    504c:	f64f 0302 	movw	r3, #63490	; 0xf802
    5050:	429a      	cmp	r2, r3
    5052:	d100      	bne.n	5056 <MSS_SYS_puf_get_number_of_keys+0x56>
    5054:	be00      	bkpt	0x0000
    ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION);
    5056:	f248 0300 	movw	r3, #32768	; 0x8000
    505a:	f2c4 0303 	movt	r3, #16387	; 0x4003
    505e:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5062:	f64f 0302 	movw	r3, #63490	; 0xf802
    5066:	f2c0 0301 	movt	r3, #1
    506a:	429a      	cmp	r2, r3
    506c:	d100      	bne.n	5070 <MSS_SYS_puf_get_number_of_keys+0x70>
    506e:	be00      	bkpt	0x0000
    ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION);
    5070:	f248 0300 	movw	r3, #32768	; 0x8000
    5074:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5078:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    507c:	f64f 0302 	movw	r3, #63490	; 0xf802
    5080:	f2c0 0302 	movt	r3, #2
    5084:	429a      	cmp	r2, r3
    5086:	d100      	bne.n	508a <MSS_SYS_puf_get_number_of_keys+0x8a>
    5088:	be00      	bkpt	0x0000
    ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION);
    508a:	f248 0300 	movw	r3, #32768	; 0x8000
    508e:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5092:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5096:	f64f 0302 	movw	r3, #63490	; 0xf802
    509a:	f2c0 0303 	movt	r3, #3
    509e:	429a      	cmp	r2, r3
    50a0:	d100      	bne.n	50a4 <MSS_SYS_puf_get_number_of_keys+0xa4>
    50a2:	be00      	bkpt	0x0000

    params[0] = PUF_GET_NUMBER_OF_KC_SUBCOMMAND;    
    50a4:	f04f 0300 	mov.w	r3, #0
    50a8:	733b      	strb	r3, [r7, #12]
    
    status = execute_service(PUF_USER_KEY_CODE_REQUEST_CMD,
    50aa:	f107 020c 	add.w	r2, r7, #12
    50ae:	f107 0318 	add.w	r3, r7, #24
    50b2:	f04f 001a 	mov.w	r0, #26
    50b6:	4611      	mov	r1, r2
    50b8:	461a      	mov	r2, r3
    50ba:	f04f 0306 	mov.w	r3, #6
    50be:	f000 fdf5 	bl	5cac <execute_service>
    50c2:	4603      	mov	r3, r0
    50c4:	77fb      	strb	r3, [r7, #31]
                             params,
                             response,
                             PUF_GET_NUMBER_OF_KEYS_RESP_LENGTH);
    
    *p_number_of_keys = params[9];
    50c6:	7d7a      	ldrb	r2, [r7, #21]
    50c8:	687b      	ldr	r3, [r7, #4]
    50ca:	701a      	strb	r2, [r3, #0]
    
    return status;
    50cc:	7ffb      	ldrb	r3, [r7, #31]
}
    50ce:	4618      	mov	r0, r3
    50d0:	f107 0720 	add.w	r7, r7, #32
    50d4:	46bd      	mov	sp, r7
    50d6:	bd80      	pop	{r7, pc}

000050d8 <MSS_SYS_puf_enroll_key>:
    uint8_t key_number,
    uint16_t key_size,
    uint8_t* p_key_value,
    uint8_t* p_key_location
)
{
    50d8:	b580      	push	{r7, lr}
    50da:	b08a      	sub	sp, #40	; 0x28
    50dc:	af00      	add	r7, sp, #0
    50de:	60ba      	str	r2, [r7, #8]
    50e0:	607b      	str	r3, [r7, #4]
    50e2:	4603      	mov	r3, r0
    50e4:	73fb      	strb	r3, [r7, #15]
    50e6:	460b      	mov	r3, r1
    50e8:	81bb      	strh	r3, [r7, #12]
    uint8_t response[6u];
    uint8_t params[11u];
    uint8_t status;
    uint8_t key_numbers = 0u;
    50ea:	f04f 0300 	mov.w	r3, #0
    50ee:	74fb      	strb	r3, [r7, #19]
    
    /*
     * The PUF enroll key system service is not available on M2S050 rev A,
     * rev B, rev C and rev D.
     */
    ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION);
    50f0:	f248 0300 	movw	r3, #32768	; 0x8000
    50f4:	f2c4 0303 	movt	r3, #16387	; 0x4003
    50f8:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    50fc:	f64f 0302 	movw	r3, #63490	; 0xf802
    5100:	429a      	cmp	r2, r3
    5102:	d100      	bne.n	5106 <MSS_SYS_puf_enroll_key+0x2e>
    5104:	be00      	bkpt	0x0000
    ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION);
    5106:	f248 0300 	movw	r3, #32768	; 0x8000
    510a:	f2c4 0303 	movt	r3, #16387	; 0x4003
    510e:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5112:	f64f 0302 	movw	r3, #63490	; 0xf802
    5116:	f2c0 0301 	movt	r3, #1
    511a:	429a      	cmp	r2, r3
    511c:	d100      	bne.n	5120 <MSS_SYS_puf_enroll_key+0x48>
    511e:	be00      	bkpt	0x0000
    ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION);
    5120:	f248 0300 	movw	r3, #32768	; 0x8000
    5124:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5128:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    512c:	f64f 0302 	movw	r3, #63490	; 0xf802
    5130:	f2c0 0302 	movt	r3, #2
    5134:	429a      	cmp	r2, r3
    5136:	d100      	bne.n	513a <MSS_SYS_puf_enroll_key+0x62>
    5138:	be00      	bkpt	0x0000
    ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION);
    513a:	f248 0300 	movw	r3, #32768	; 0x8000
    513e:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5142:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5146:	f64f 0302 	movw	r3, #63490	; 0xf802
    514a:	f2c0 0303 	movt	r3, #3
    514e:	429a      	cmp	r2, r3
    5150:	d100      	bne.n	5154 <MSS_SYS_puf_enroll_key+0x7c>
    5152:	be00      	bkpt	0x0000

    if(p_key_value == 0)
    5154:	68bb      	ldr	r3, [r7, #8]
    5156:	2b00      	cmp	r3, #0
    5158:	d103      	bne.n	5162 <MSS_SYS_puf_enroll_key+0x8a>
    {
        params[0] = PUF_CREATE_INT_KC_SUBCOMMAND;
    515a:	f04f 0302 	mov.w	r3, #2
    515e:	753b      	strb	r3, [r7, #20]
    5160:	e002      	b.n	5168 <MSS_SYS_puf_enroll_key+0x90>
    }
    else
    {
        params[0] = PUF_CREATE_EXT_KC_SUBCOMMAND;
    5162:	f04f 0301 	mov.w	r3, #1
    5166:	753b      	strb	r3, [r7, #20]
    }
    
    write_ptr_value_into_array(p_key_location, params, 1u);
    5168:	f107 0314 	add.w	r3, r7, #20
    516c:	6878      	ldr	r0, [r7, #4]
    516e:	4619      	mov	r1, r3
    5170:	f04f 0201 	mov.w	r2, #1
    5174:	f000 fe18 	bl	5da8 <write_ptr_value_into_array>
    write_ptr_value_into_array(p_key_value, params, 5u);
    5178:	f107 0314 	add.w	r3, r7, #20
    517c:	68b8      	ldr	r0, [r7, #8]
    517e:	4619      	mov	r1, r3
    5180:	f04f 0205 	mov.w	r2, #5
    5184:	f000 fe10 	bl	5da8 <write_ptr_value_into_array>
    
    params[9] = key_number;
    5188:	7bfb      	ldrb	r3, [r7, #15]
    518a:	777b      	strb	r3, [r7, #29]
    params[10] = key_size;
    518c:	89bb      	ldrh	r3, [r7, #12]
    518e:	b2db      	uxtb	r3, r3
    5190:	77bb      	strb	r3, [r7, #30]
    
    status = execute_service(PUF_USER_KEY_CODE_REQUEST_CMD,
    5192:	f107 0214 	add.w	r2, r7, #20
    5196:	f107 0320 	add.w	r3, r7, #32
    519a:	f04f 001a 	mov.w	r0, #26
    519e:	4611      	mov	r1, r2
    51a0:	461a      	mov	r2, r3
    51a2:	f04f 0306 	mov.w	r3, #6
    51a6:	f000 fd81 	bl	5cac <execute_service>
    51aa:	4603      	mov	r3, r0
    51ac:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
     * service, but system controller is not releasing back after completing the
     * operation. In order to unlock eNVM-1, call get number of key service. PUF
     * get number of key service will release the eNVM-1 lock after reading the 
     * number of keys enrolled.
     */
    MSS_SYS_puf_get_number_of_keys(&key_numbers);
    51b0:	f107 0313 	add.w	r3, r7, #19
    51b4:	4618      	mov	r0, r3
    51b6:	f7ff ff23 	bl	5000 <MSS_SYS_puf_get_number_of_keys>
       
    return status;
    51ba:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
}
    51be:	4618      	mov	r0, r3
    51c0:	f107 0728 	add.w	r7, r7, #40	; 0x28
    51c4:	46bd      	mov	sp, r7
    51c6:	bd80      	pop	{r7, pc}

000051c8 <MSS_SYS_puf_delete_key>:
 */
uint8_t MSS_SYS_puf_delete_key
(
    uint8_t key_number
)
{
    51c8:	b580      	push	{r7, lr}
    51ca:	b088      	sub	sp, #32
    51cc:	af00      	add	r7, sp, #0
    51ce:	4603      	mov	r3, r0
    51d0:	71fb      	strb	r3, [r7, #7]
    uint8_t response[6u];
    uint8_t params[11u];
    uint8_t status;
    uint8_t key_numbers = 0u;
    51d2:	f04f 0300 	mov.w	r3, #0
    51d6:	72fb      	strb	r3, [r7, #11]
    
    /*
     * The delete PUF key system service is not available on M2S050 rev A,
     * rev B, rev C and rev D.
     */
    ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION);
    51d8:	f248 0300 	movw	r3, #32768	; 0x8000
    51dc:	f2c4 0303 	movt	r3, #16387	; 0x4003
    51e0:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    51e4:	f64f 0302 	movw	r3, #63490	; 0xf802
    51e8:	429a      	cmp	r2, r3
    51ea:	d100      	bne.n	51ee <MSS_SYS_puf_delete_key+0x26>
    51ec:	be00      	bkpt	0x0000
    ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION);
    51ee:	f248 0300 	movw	r3, #32768	; 0x8000
    51f2:	f2c4 0303 	movt	r3, #16387	; 0x4003
    51f6:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    51fa:	f64f 0302 	movw	r3, #63490	; 0xf802
    51fe:	f2c0 0301 	movt	r3, #1
    5202:	429a      	cmp	r2, r3
    5204:	d100      	bne.n	5208 <MSS_SYS_puf_delete_key+0x40>
    5206:	be00      	bkpt	0x0000
    ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION);
    5208:	f248 0300 	movw	r3, #32768	; 0x8000
    520c:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5210:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5214:	f64f 0302 	movw	r3, #63490	; 0xf802
    5218:	f2c0 0302 	movt	r3, #2
    521c:	429a      	cmp	r2, r3
    521e:	d100      	bne.n	5222 <MSS_SYS_puf_delete_key+0x5a>
    5220:	be00      	bkpt	0x0000
    ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION);
    5222:	f248 0300 	movw	r3, #32768	; 0x8000
    5226:	f2c4 0303 	movt	r3, #16387	; 0x4003
    522a:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    522e:	f64f 0302 	movw	r3, #63490	; 0xf802
    5232:	f2c0 0303 	movt	r3, #3
    5236:	429a      	cmp	r2, r3
    5238:	d100      	bne.n	523c <MSS_SYS_puf_delete_key+0x74>
    523a:	be00      	bkpt	0x0000

    params[0] = PUF_DELETE_KC_SUBCOMMAND;
    523c:	f04f 0305 	mov.w	r3, #5
    5240:	733b      	strb	r3, [r7, #12]
    params[9] = key_number;
    5242:	79fb      	ldrb	r3, [r7, #7]
    5244:	757b      	strb	r3, [r7, #21]
        
    status = execute_service(PUF_USER_KEY_CODE_REQUEST_CMD,
    5246:	f107 020c 	add.w	r2, r7, #12
    524a:	f107 0318 	add.w	r3, r7, #24
    524e:	f04f 001a 	mov.w	r0, #26
    5252:	4611      	mov	r1, r2
    5254:	461a      	mov	r2, r3
    5256:	f04f 0306 	mov.w	r3, #6
    525a:	f000 fd27 	bl	5cac <execute_service>
    525e:	4603      	mov	r3, r0
    5260:	77fb      	strb	r3, [r7, #31]
     * service, but system controller is not releasing back after completing the
     * operation. In order to unlock eNVM-1, call get number of key service. PUF
     * get number of key service will release the eNVM-1 lock after reading the 
     * number of keys enrolled.
     */
    MSS_SYS_puf_get_number_of_keys(&key_numbers);
    5262:	f107 030b 	add.w	r3, r7, #11
    5266:	4618      	mov	r0, r3
    5268:	f7ff feca 	bl	5000 <MSS_SYS_puf_get_number_of_keys>
    
    return status;
    526c:	7ffb      	ldrb	r3, [r7, #31]
}
    526e:	4618      	mov	r0, r3
    5270:	f107 0720 	add.w	r7, r7, #32
    5274:	46bd      	mov	sp, r7
    5276:	bd80      	pop	{r7, pc}

00005278 <MSS_SYS_puf_fetch_key>:
uint8_t MSS_SYS_puf_fetch_key
(
    uint8_t key_number,
    uint8_t ** pp_key
)
{
    5278:	b580      	push	{r7, lr}
    527a:	b086      	sub	sp, #24
    527c:	af00      	add	r7, sp, #0
    527e:	4603      	mov	r3, r0
    5280:	6039      	str	r1, [r7, #0]
    5282:	71fb      	strb	r3, [r7, #7]
    
    /*
     * The fetch user key system service is not available on M2S050 rev A,
     * rev B, rev C and rev D.
     */
    ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION);
    5284:	f248 0300 	movw	r3, #32768	; 0x8000
    5288:	f2c4 0303 	movt	r3, #16387	; 0x4003
    528c:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5290:	f64f 0302 	movw	r3, #63490	; 0xf802
    5294:	429a      	cmp	r2, r3
    5296:	d100      	bne.n	529a <MSS_SYS_puf_fetch_key+0x22>
    5298:	be00      	bkpt	0x0000
    ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION);
    529a:	f248 0300 	movw	r3, #32768	; 0x8000
    529e:	f2c4 0303 	movt	r3, #16387	; 0x4003
    52a2:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    52a6:	f64f 0302 	movw	r3, #63490	; 0xf802
    52aa:	f2c0 0301 	movt	r3, #1
    52ae:	429a      	cmp	r2, r3
    52b0:	d100      	bne.n	52b4 <MSS_SYS_puf_fetch_key+0x3c>
    52b2:	be00      	bkpt	0x0000
    ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION);
    52b4:	f248 0300 	movw	r3, #32768	; 0x8000
    52b8:	f2c4 0303 	movt	r3, #16387	; 0x4003
    52bc:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    52c0:	f64f 0302 	movw	r3, #63490	; 0xf802
    52c4:	f2c0 0302 	movt	r3, #2
    52c8:	429a      	cmp	r2, r3
    52ca:	d100      	bne.n	52ce <MSS_SYS_puf_fetch_key+0x56>
    52cc:	be00      	bkpt	0x0000
    ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION);
    52ce:	f248 0300 	movw	r3, #32768	; 0x8000
    52d2:	f2c4 0303 	movt	r3, #16387	; 0x4003
    52d6:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    52da:	f64f 0302 	movw	r3, #63490	; 0xf802
    52de:	f2c0 0303 	movt	r3, #3
    52e2:	429a      	cmp	r2, r3
    52e4:	d100      	bne.n	52e8 <MSS_SYS_puf_fetch_key+0x70>
    52e6:	be00      	bkpt	0x0000
    
    write_ptr_value_into_array(*pp_key, params, 0u);
    52e8:	683b      	ldr	r3, [r7, #0]
    52ea:	681a      	ldr	r2, [r3, #0]
    52ec:	f107 0308 	add.w	r3, r7, #8
    52f0:	4610      	mov	r0, r2
    52f2:	4619      	mov	r1, r3
    52f4:	f04f 0200 	mov.w	r2, #0
    52f8:	f000 fd56 	bl	5da8 <write_ptr_value_into_array>
    
    params[4] = key_number;
    52fc:	79fb      	ldrb	r3, [r7, #7]
    52fe:	733b      	strb	r3, [r7, #12]
    
    status = execute_service(PUF_FETCH_KEY_REQUEST_CMD,
    5300:	f107 0208 	add.w	r2, r7, #8
    5304:	f107 0310 	add.w	r3, r7, #16
    5308:	f04f 001b 	mov.w	r0, #27
    530c:	4611      	mov	r1, r2
    530e:	461a      	mov	r2, r3
    5310:	f04f 0306 	mov.w	r3, #6
    5314:	f000 fcca 	bl	5cac <execute_service>
    5318:	4603      	mov	r3, r0
    531a:	75fb      	strb	r3, [r7, #23]
                             params,
                             response,
                             STANDARD_SERV_RESP_LENGTH);
    if(pp_key != NULL)
    531c:	683b      	ldr	r3, [r7, #0]
    531e:	2b00      	cmp	r3, #0
    5320:	d007      	beq.n	5332 <MSS_SYS_puf_fetch_key+0xba>
    {
        write_array_into_ptr_value(&(*pp_key), params, 0);
    5322:	f107 0308 	add.w	r3, r7, #8
    5326:	6838      	ldr	r0, [r7, #0]
    5328:	4619      	mov	r1, r3
    532a:	f04f 0200 	mov.w	r2, #0
    532e:	f000 fd6b 	bl	5e08 <write_array_into_ptr_value>
    }
    
    return status;
    5332:	7dfb      	ldrb	r3, [r7, #23]
}
    5334:	4618      	mov	r0, r3
    5336:	f107 0718 	add.w	r7, r7, #24
    533a:	46bd      	mov	sp, r7
    533c:	bd80      	pop	{r7, pc}
    533e:	bf00      	nop

00005340 <MSS_SYS_puf_export_keycodes>:
 */
uint8_t MSS_SYS_puf_export_keycodes
(
    uint8_t * p_keycodes
)
{
    5340:	b580      	push	{r7, lr}
    5342:	b088      	sub	sp, #32
    5344:	af00      	add	r7, sp, #0
    5346:	6078      	str	r0, [r7, #4]
    
    /*
     * The export all user key system service is not available on M2S050 rev A,
     * rev B, rev C and rev D.
     */
    ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION);
    5348:	f248 0300 	movw	r3, #32768	; 0x8000
    534c:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5350:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5354:	f64f 0302 	movw	r3, #63490	; 0xf802
    5358:	429a      	cmp	r2, r3
    535a:	d100      	bne.n	535e <MSS_SYS_puf_export_keycodes+0x1e>
    535c:	be00      	bkpt	0x0000
    ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION);
    535e:	f248 0300 	movw	r3, #32768	; 0x8000
    5362:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5366:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    536a:	f64f 0302 	movw	r3, #63490	; 0xf802
    536e:	f2c0 0301 	movt	r3, #1
    5372:	429a      	cmp	r2, r3
    5374:	d100      	bne.n	5378 <MSS_SYS_puf_export_keycodes+0x38>
    5376:	be00      	bkpt	0x0000
    ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION);
    5378:	f248 0300 	movw	r3, #32768	; 0x8000
    537c:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5380:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5384:	f64f 0302 	movw	r3, #63490	; 0xf802
    5388:	f2c0 0302 	movt	r3, #2
    538c:	429a      	cmp	r2, r3
    538e:	d100      	bne.n	5392 <MSS_SYS_puf_export_keycodes+0x52>
    5390:	be00      	bkpt	0x0000
    ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION);
    5392:	f248 0300 	movw	r3, #32768	; 0x8000
    5396:	f2c4 0303 	movt	r3, #16387	; 0x4003
    539a:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    539e:	f64f 0302 	movw	r3, #63490	; 0xf802
    53a2:	f2c0 0303 	movt	r3, #3
    53a6:	429a      	cmp	r2, r3
    53a8:	d100      	bne.n	53ac <MSS_SYS_puf_export_keycodes+0x6c>
    53aa:	be00      	bkpt	0x0000

    params[0] = PUF_EXPORT_ALL_KC_SUBCOMMAND;
    53ac:	f04f 0303 	mov.w	r3, #3
    53b0:	733b      	strb	r3, [r7, #12]
    
    write_ptr_value_into_array(p_keycodes, params, 1u);
    53b2:	f107 030c 	add.w	r3, r7, #12
    53b6:	6878      	ldr	r0, [r7, #4]
    53b8:	4619      	mov	r1, r3
    53ba:	f04f 0201 	mov.w	r2, #1
    53be:	f000 fcf3 	bl	5da8 <write_ptr_value_into_array>
        
    status = execute_service(PUF_USER_KEY_CODE_REQUEST_CMD,
    53c2:	f107 020c 	add.w	r2, r7, #12
    53c6:	f107 0318 	add.w	r3, r7, #24
    53ca:	f04f 001a 	mov.w	r0, #26
    53ce:	4611      	mov	r1, r2
    53d0:	461a      	mov	r2, r3
    53d2:	f04f 0306 	mov.w	r3, #6
    53d6:	f000 fc69 	bl	5cac <execute_service>
    53da:	4603      	mov	r3, r0
    53dc:	77fb      	strb	r3, [r7, #31]
                             params,
                             response,
                             PUF_EXPORT_ALL_KEYCODES_RESP_LENGTH);
       
    return status;
    53de:	7ffb      	ldrb	r3, [r7, #31]
}
    53e0:	4618      	mov	r0, r3
    53e2:	f107 0720 	add.w	r7, r7, #32
    53e6:	46bd      	mov	sp, r7
    53e8:	bd80      	pop	{r7, pc}
    53ea:	bf00      	nop

000053ec <MSS_SYS_puf_import_keycodes>:
 */
uint8_t MSS_SYS_puf_import_keycodes
(
    uint8_t * p_keycodes
)
{
    53ec:	b580      	push	{r7, lr}
    53ee:	b088      	sub	sp, #32
    53f0:	af00      	add	r7, sp, #0
    53f2:	6078      	str	r0, [r7, #4]
    
    /*
     * The import all key code system service is not available on M2S050 rev A,
     * rev B, rev C and rev D.
     */
    ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION);
    53f4:	f248 0300 	movw	r3, #32768	; 0x8000
    53f8:	f2c4 0303 	movt	r3, #16387	; 0x4003
    53fc:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5400:	f64f 0302 	movw	r3, #63490	; 0xf802
    5404:	429a      	cmp	r2, r3
    5406:	d100      	bne.n	540a <MSS_SYS_puf_import_keycodes+0x1e>
    5408:	be00      	bkpt	0x0000
    ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION);
    540a:	f248 0300 	movw	r3, #32768	; 0x8000
    540e:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5412:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5416:	f64f 0302 	movw	r3, #63490	; 0xf802
    541a:	f2c0 0301 	movt	r3, #1
    541e:	429a      	cmp	r2, r3
    5420:	d100      	bne.n	5424 <MSS_SYS_puf_import_keycodes+0x38>
    5422:	be00      	bkpt	0x0000
    ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION);
    5424:	f248 0300 	movw	r3, #32768	; 0x8000
    5428:	f2c4 0303 	movt	r3, #16387	; 0x4003
    542c:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5430:	f64f 0302 	movw	r3, #63490	; 0xf802
    5434:	f2c0 0302 	movt	r3, #2
    5438:	429a      	cmp	r2, r3
    543a:	d100      	bne.n	543e <MSS_SYS_puf_import_keycodes+0x52>
    543c:	be00      	bkpt	0x0000
    ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION);
    543e:	f248 0300 	movw	r3, #32768	; 0x8000
    5442:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5446:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    544a:	f64f 0302 	movw	r3, #63490	; 0xf802
    544e:	f2c0 0303 	movt	r3, #3
    5452:	429a      	cmp	r2, r3
    5454:	d100      	bne.n	5458 <MSS_SYS_puf_import_keycodes+0x6c>
    5456:	be00      	bkpt	0x0000

    params[0] = PUF_IMPORT_ALL_KC_SUBCOMMAND;
    5458:	f04f 0304 	mov.w	r3, #4
    545c:	733b      	strb	r3, [r7, #12]
    
    write_ptr_value_into_array(p_keycodes, params, 1u);
    545e:	f107 030c 	add.w	r3, r7, #12
    5462:	6878      	ldr	r0, [r7, #4]
    5464:	4619      	mov	r1, r3
    5466:	f04f 0201 	mov.w	r2, #1
    546a:	f000 fc9d 	bl	5da8 <write_ptr_value_into_array>
    
    status = execute_service(PUF_USER_KEY_CODE_REQUEST_CMD,
    546e:	f107 020c 	add.w	r2, r7, #12
    5472:	f107 0318 	add.w	r3, r7, #24
    5476:	f04f 001a 	mov.w	r0, #26
    547a:	4611      	mov	r1, r2
    547c:	461a      	mov	r2, r3
    547e:	f04f 0306 	mov.w	r3, #6
    5482:	f000 fc13 	bl	5cac <execute_service>
    5486:	4603      	mov	r3, r0
    5488:	77fb      	strb	r3, [r7, #31]
                             params,
                             response,
                             PUF_IMPORT_ALL_KEYCODES_RESP_LENGTH);
        
    return status;
    548a:	7ffb      	ldrb	r3, [r7, #31]
}
    548c:	4618      	mov	r0, r3
    548e:	f107 0720 	add.w	r7, r7, #32
    5492:	46bd      	mov	sp, r7
    5494:	bd80      	pop	{r7, pc}
    5496:	bf00      	nop

00005498 <MSS_SYS_puf_fetch_ecc_public_key>:
 */
uint8_t MSS_SYS_puf_fetch_ecc_public_key
(
    uint8_t* p_puf_public_key
)
{
    5498:	b580      	push	{r7, lr}
    549a:	b086      	sub	sp, #24
    549c:	af00      	add	r7, sp, #0
    549e:	6078      	str	r0, [r7, #4]

    /*
     * The fetch puf ecc public key system service is not available on M2S050
     * rev A, rev B, rev C and rev D.
     */
    ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION);
    54a0:	f248 0300 	movw	r3, #32768	; 0x8000
    54a4:	f2c4 0303 	movt	r3, #16387	; 0x4003
    54a8:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    54ac:	f64f 0302 	movw	r3, #63490	; 0xf802
    54b0:	429a      	cmp	r2, r3
    54b2:	d100      	bne.n	54b6 <MSS_SYS_puf_fetch_ecc_public_key+0x1e>
    54b4:	be00      	bkpt	0x0000
    ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION);
    54b6:	f248 0300 	movw	r3, #32768	; 0x8000
    54ba:	f2c4 0303 	movt	r3, #16387	; 0x4003
    54be:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    54c2:	f64f 0302 	movw	r3, #63490	; 0xf802
    54c6:	f2c0 0301 	movt	r3, #1
    54ca:	429a      	cmp	r2, r3
    54cc:	d100      	bne.n	54d0 <MSS_SYS_puf_fetch_ecc_public_key+0x38>
    54ce:	be00      	bkpt	0x0000
    ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION);
    54d0:	f248 0300 	movw	r3, #32768	; 0x8000
    54d4:	f2c4 0303 	movt	r3, #16387	; 0x4003
    54d8:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    54dc:	f64f 0302 	movw	r3, #63490	; 0xf802
    54e0:	f2c0 0302 	movt	r3, #2
    54e4:	429a      	cmp	r2, r3
    54e6:	d100      	bne.n	54ea <MSS_SYS_puf_fetch_ecc_public_key+0x52>
    54e8:	be00      	bkpt	0x0000
    ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION);
    54ea:	f248 0300 	movw	r3, #32768	; 0x8000
    54ee:	f2c4 0303 	movt	r3, #16387	; 0x4003
    54f2:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    54f6:	f64f 0302 	movw	r3, #63490	; 0xf802
    54fa:	f2c0 0303 	movt	r3, #3
    54fe:	429a      	cmp	r2, r3
    5500:	d100      	bne.n	5504 <MSS_SYS_puf_fetch_ecc_public_key+0x6c>
    5502:	be00      	bkpt	0x0000
    
    write_ptr_value_into_array(p_puf_public_key, params, 0u);
    5504:	f107 030c 	add.w	r3, r7, #12
    5508:	6878      	ldr	r0, [r7, #4]
    550a:	4619      	mov	r1, r3
    550c:	f04f 0200 	mov.w	r2, #0
    5510:	f000 fc4a 	bl	5da8 <write_ptr_value_into_array>
    
    status = execute_service(PUF_ECC_PUBLIC_KEY_REQUEST_CMD,
    5514:	f107 020c 	add.w	r2, r7, #12
    5518:	f107 0310 	add.w	r3, r7, #16
    551c:	f04f 001c 	mov.w	r0, #28
    5520:	4611      	mov	r1, r2
    5522:	461a      	mov	r2, r3
    5524:	f04f 0306 	mov.w	r3, #6
    5528:	f000 fbc0 	bl	5cac <execute_service>
    552c:	4603      	mov	r3, r0
    552e:	75fb      	strb	r3, [r7, #23]
                             params,
                             response,
                             STANDARD_SERV_RESP_LENGTH);
    
    return status;
    5530:	7dfb      	ldrb	r3, [r7, #23]
}
    5532:	4618      	mov	r0, r3
    5534:	f107 0718 	add.w	r7, r7, #24
    5538:	46bd      	mov	sp, r7
    553a:	bd80      	pop	{r7, pc}

0000553c <MSS_SYS_puf_get_random_seed>:
 */
uint8_t MSS_SYS_puf_get_random_seed
(
    uint8_t* p_puf_seed
)
{
    553c:	b580      	push	{r7, lr}
    553e:	b086      	sub	sp, #24
    5540:	af00      	add	r7, sp, #0
    5542:	6078      	str	r0, [r7, #4]
    
    /*
     * The get puf seed system service is not available on M2S050 rev A, rev B,
     * rev C and rev D.
     */
    ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION);
    5544:	f248 0300 	movw	r3, #32768	; 0x8000
    5548:	f2c4 0303 	movt	r3, #16387	; 0x4003
    554c:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5550:	f64f 0302 	movw	r3, #63490	; 0xf802
    5554:	429a      	cmp	r2, r3
    5556:	d100      	bne.n	555a <MSS_SYS_puf_get_random_seed+0x1e>
    5558:	be00      	bkpt	0x0000
    ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION);
    555a:	f248 0300 	movw	r3, #32768	; 0x8000
    555e:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5562:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5566:	f64f 0302 	movw	r3, #63490	; 0xf802
    556a:	f2c0 0301 	movt	r3, #1
    556e:	429a      	cmp	r2, r3
    5570:	d100      	bne.n	5574 <MSS_SYS_puf_get_random_seed+0x38>
    5572:	be00      	bkpt	0x0000
    ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION);
    5574:	f248 0300 	movw	r3, #32768	; 0x8000
    5578:	f2c4 0303 	movt	r3, #16387	; 0x4003
    557c:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5580:	f64f 0302 	movw	r3, #63490	; 0xf802
    5584:	f2c0 0302 	movt	r3, #2
    5588:	429a      	cmp	r2, r3
    558a:	d100      	bne.n	558e <MSS_SYS_puf_get_random_seed+0x52>
    558c:	be00      	bkpt	0x0000
    ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION);
    558e:	f248 0300 	movw	r3, #32768	; 0x8000
    5592:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5596:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    559a:	f64f 0302 	movw	r3, #63490	; 0xf802
    559e:	f2c0 0303 	movt	r3, #3
    55a2:	429a      	cmp	r2, r3
    55a4:	d100      	bne.n	55a8 <MSS_SYS_puf_get_random_seed+0x6c>
    55a6:	be00      	bkpt	0x0000
    
    write_ptr_value_into_array(p_puf_seed, params, 0u);
    55a8:	f107 030c 	add.w	r3, r7, #12
    55ac:	6878      	ldr	r0, [r7, #4]
    55ae:	4619      	mov	r1, r3
    55b0:	f04f 0200 	mov.w	r2, #0
    55b4:	f000 fbf8 	bl	5da8 <write_ptr_value_into_array>
    
    status = execute_service(PUF_SEED_REQUEST_CMD,
    55b8:	f107 020c 	add.w	r2, r7, #12
    55bc:	f107 0310 	add.w	r3, r7, #16
    55c0:	f04f 001d 	mov.w	r0, #29
    55c4:	4611      	mov	r1, r2
    55c6:	461a      	mov	r2, r3
    55c8:	f04f 0306 	mov.w	r3, #6
    55cc:	f000 fb6e 	bl	5cac <execute_service>
    55d0:	4603      	mov	r3, r0
    55d2:	75fb      	strb	r3, [r7, #23]
                             params,
                             response,
                             STANDARD_SERV_RESP_LENGTH);
    
    return status;
    55d4:	7dfb      	ldrb	r3, [r7, #23]
}
    55d6:	4618      	mov	r0, r3
    55d8:	f107 0718 	add.w	r7, r7, #24
    55dc:	46bd      	mov	sp, r7
    55de:	bd80      	pop	{r7, pc}

000055e0 <MSS_SYS_ecc_point_multiplication>:
(
    uint8_t* p_scalar_d,
    uint8_t* p_point_p,
    uint8_t* p_point_q
)
{
    55e0:	b580      	push	{r7, lr}
    55e2:	b08a      	sub	sp, #40	; 0x28
    55e4:	af00      	add	r7, sp, #0
    55e6:	60f8      	str	r0, [r7, #12]
    55e8:	60b9      	str	r1, [r7, #8]
    55ea:	607a      	str	r2, [r7, #4]
    
    /*
     * The ECC point multiplication system service is not available on M2S050 
     * rev A, rev B, rev C and rev D.
     */
    ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION);
    55ec:	f248 0300 	movw	r3, #32768	; 0x8000
    55f0:	f2c4 0303 	movt	r3, #16387	; 0x4003
    55f4:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    55f8:	f64f 0302 	movw	r3, #63490	; 0xf802
    55fc:	429a      	cmp	r2, r3
    55fe:	d100      	bne.n	5602 <MSS_SYS_ecc_point_multiplication+0x22>
    5600:	be00      	bkpt	0x0000
    ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION);
    5602:	f248 0300 	movw	r3, #32768	; 0x8000
    5606:	f2c4 0303 	movt	r3, #16387	; 0x4003
    560a:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    560e:	f64f 0302 	movw	r3, #63490	; 0xf802
    5612:	f2c0 0301 	movt	r3, #1
    5616:	429a      	cmp	r2, r3
    5618:	d100      	bne.n	561c <MSS_SYS_ecc_point_multiplication+0x3c>
    561a:	be00      	bkpt	0x0000
    ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION);
    561c:	f248 0300 	movw	r3, #32768	; 0x8000
    5620:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5624:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5628:	f64f 0302 	movw	r3, #63490	; 0xf802
    562c:	f2c0 0302 	movt	r3, #2
    5630:	429a      	cmp	r2, r3
    5632:	d100      	bne.n	5636 <MSS_SYS_ecc_point_multiplication+0x56>
    5634:	be00      	bkpt	0x0000
    ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION);
    5636:	f248 0300 	movw	r3, #32768	; 0x8000
    563a:	f2c4 0303 	movt	r3, #16387	; 0x4003
    563e:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5642:	f64f 0302 	movw	r3, #63490	; 0xf802
    5646:	f2c0 0303 	movt	r3, #3
    564a:	429a      	cmp	r2, r3
    564c:	d100      	bne.n	5650 <MSS_SYS_ecc_point_multiplication+0x70>
    564e:	be00      	bkpt	0x0000
    
    write_ptr_value_into_array(p_scalar_d, params, 0u);
    5650:	f107 0314 	add.w	r3, r7, #20
    5654:	68f8      	ldr	r0, [r7, #12]
    5656:	4619      	mov	r1, r3
    5658:	f04f 0200 	mov.w	r2, #0
    565c:	f000 fba4 	bl	5da8 <write_ptr_value_into_array>
    write_ptr_value_into_array(p_point_p, params, 4u);
    5660:	f107 0314 	add.w	r3, r7, #20
    5664:	68b8      	ldr	r0, [r7, #8]
    5666:	4619      	mov	r1, r3
    5668:	f04f 0204 	mov.w	r2, #4
    566c:	f000 fb9c 	bl	5da8 <write_ptr_value_into_array>
    write_ptr_value_into_array(p_point_q, params, 8u);
    5670:	f107 0314 	add.w	r3, r7, #20
    5674:	6878      	ldr	r0, [r7, #4]
    5676:	4619      	mov	r1, r3
    5678:	f04f 0208 	mov.w	r2, #8
    567c:	f000 fb94 	bl	5da8 <write_ptr_value_into_array>
    
    status = execute_service(POINT_MULTIPLICATION_REQUEST_CMD,
    5680:	f107 0214 	add.w	r2, r7, #20
    5684:	f107 0320 	add.w	r3, r7, #32
    5688:	f04f 0010 	mov.w	r0, #16
    568c:	4611      	mov	r1, r2
    568e:	461a      	mov	r2, r3
    5690:	f04f 0306 	mov.w	r3, #6
    5694:	f000 fb0a 	bl	5cac <execute_service>
    5698:	4603      	mov	r3, r0
    569a:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
                             params,
                             response,
                             STANDARD_SERV_RESP_LENGTH);
    
    return status;
    569e:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
}
    56a2:	4618      	mov	r0, r3
    56a4:	f107 0728 	add.w	r7, r7, #40	; 0x28
    56a8:	46bd      	mov	sp, r7
    56aa:	bd80      	pop	{r7, pc}

000056ac <MSS_SYS_ecc_point_addition>:
(
    uint8_t* p_point_p,
    uint8_t* p_point_q,
    uint8_t* p_point_r
)
{
    56ac:	b580      	push	{r7, lr}
    56ae:	b08a      	sub	sp, #40	; 0x28
    56b0:	af00      	add	r7, sp, #0
    56b2:	60f8      	str	r0, [r7, #12]
    56b4:	60b9      	str	r1, [r7, #8]
    56b6:	607a      	str	r2, [r7, #4]
    
    /*
     * The ECC point addition system service is not available on M2S050 
     * rev A, rev B, rev C and rev D.
     */
    ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION);
    56b8:	f248 0300 	movw	r3, #32768	; 0x8000
    56bc:	f2c4 0303 	movt	r3, #16387	; 0x4003
    56c0:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    56c4:	f64f 0302 	movw	r3, #63490	; 0xf802
    56c8:	429a      	cmp	r2, r3
    56ca:	d100      	bne.n	56ce <MSS_SYS_ecc_point_addition+0x22>
    56cc:	be00      	bkpt	0x0000
    ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION);
    56ce:	f248 0300 	movw	r3, #32768	; 0x8000
    56d2:	f2c4 0303 	movt	r3, #16387	; 0x4003
    56d6:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    56da:	f64f 0302 	movw	r3, #63490	; 0xf802
    56de:	f2c0 0301 	movt	r3, #1
    56e2:	429a      	cmp	r2, r3
    56e4:	d100      	bne.n	56e8 <MSS_SYS_ecc_point_addition+0x3c>
    56e6:	be00      	bkpt	0x0000
    ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION);
    56e8:	f248 0300 	movw	r3, #32768	; 0x8000
    56ec:	f2c4 0303 	movt	r3, #16387	; 0x4003
    56f0:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    56f4:	f64f 0302 	movw	r3, #63490	; 0xf802
    56f8:	f2c0 0302 	movt	r3, #2
    56fc:	429a      	cmp	r2, r3
    56fe:	d100      	bne.n	5702 <MSS_SYS_ecc_point_addition+0x56>
    5700:	be00      	bkpt	0x0000
    ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION);
    5702:	f248 0300 	movw	r3, #32768	; 0x8000
    5706:	f2c4 0303 	movt	r3, #16387	; 0x4003
    570a:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    570e:	f64f 0302 	movw	r3, #63490	; 0xf802
    5712:	f2c0 0303 	movt	r3, #3
    5716:	429a      	cmp	r2, r3
    5718:	d100      	bne.n	571c <MSS_SYS_ecc_point_addition+0x70>
    571a:	be00      	bkpt	0x0000
    
    write_ptr_value_into_array(p_point_p, params, 0u);
    571c:	f107 0314 	add.w	r3, r7, #20
    5720:	68f8      	ldr	r0, [r7, #12]
    5722:	4619      	mov	r1, r3
    5724:	f04f 0200 	mov.w	r2, #0
    5728:	f000 fb3e 	bl	5da8 <write_ptr_value_into_array>
    write_ptr_value_into_array(p_point_q, params, 4u);
    572c:	f107 0314 	add.w	r3, r7, #20
    5730:	68b8      	ldr	r0, [r7, #8]
    5732:	4619      	mov	r1, r3
    5734:	f04f 0204 	mov.w	r2, #4
    5738:	f000 fb36 	bl	5da8 <write_ptr_value_into_array>
    write_ptr_value_into_array(p_point_r, params, 8u);
    573c:	f107 0314 	add.w	r3, r7, #20
    5740:	6878      	ldr	r0, [r7, #4]
    5742:	4619      	mov	r1, r3
    5744:	f04f 0208 	mov.w	r2, #8
    5748:	f000 fb2e 	bl	5da8 <write_ptr_value_into_array>
    
    status = execute_service(POINT_ADDITION_REQUEST_CMD,
    574c:	f107 0214 	add.w	r2, r7, #20
    5750:	f107 0320 	add.w	r3, r7, #32
    5754:	f04f 0011 	mov.w	r0, #17
    5758:	4611      	mov	r1, r2
    575a:	461a      	mov	r2, r3
    575c:	f04f 0306 	mov.w	r3, #6
    5760:	f000 faa4 	bl	5cac <execute_service>
    5764:	4603      	mov	r3, r0
    5766:	f887 3027 	strb.w	r3, [r7, #39]	; 0x27
                             params,
                             response,
                             STANDARD_SERV_RESP_LENGTH);
    
    return status;
    576a:	f897 3027 	ldrb.w	r3, [r7, #39]	; 0x27
}
    576e:	4618      	mov	r0, r3
    5770:	f107 0728 	add.w	r7, r7, #40	; 0x28
    5774:	46bd      	mov	sp, r7
    5776:	bd80      	pop	{r7, pc}

00005778 <MSS_SYS_ecc_get_base_point>:
 */
void MSS_SYS_ecc_get_base_point
(
    uint8_t* p_point_g
)
{
    5778:	b580      	push	{r7, lr}
    577a:	b09a      	sub	sp, #104	; 0x68
    577c:	af00      	add	r7, sp, #0
    577e:	6078      	str	r0, [r7, #4]
        0xbf, 0x55, 0x29, 0x6c, 0x3a, 0x54, 0x5e, 0x38, 0x72, 0x76, 0x0a, 0xB7,
        0x36, 0x17, 0xde, 0x4a, 0x96, 0x26, 0x2c, 0x6f, 0x5d, 0x9e, 0x98, 0xbf,
        0x92, 0x92, 0xdc, 0x29, 0xf8, 0xf4, 0x1d, 0xbd, 0x28, 0x9a, 0x14, 0x7c,
        0xe9, 0xda, 0x31, 0x13, 0xb5, 0xf0, 0xb8, 0xc0, 0x0a, 0x60, 0xb1, 0xce,
        0x1d, 0x7e, 0x81, 0x9d, 0x7a, 0x43, 0x1d, 0x7c, 0x90, 0xea, 0x0e, 0x5F
    };
    5780:	f649 6328 	movw	r3, #40488	; 0x9e28
    5784:	f2c0 0300 	movt	r3, #0
    5788:	f107 0108 	add.w	r1, r7, #8
    578c:	461a      	mov	r2, r3
    578e:	f04f 0360 	mov.w	r3, #96	; 0x60
    5792:	4608      	mov	r0, r1
    5794:	4611      	mov	r1, r2
    5796:	461a      	mov	r2, r3
    5798:	f004 fa02 	bl	9ba0 <memcpy>
    
    memcpy(p_point_g, &base_point_g[0], sizeof(base_point_g));
    579c:	f107 0308 	add.w	r3, r7, #8
    57a0:	6878      	ldr	r0, [r7, #4]
    57a2:	4619      	mov	r1, r3
    57a4:	f04f 0260 	mov.w	r2, #96	; 0x60
    57a8:	f004 f9fa 	bl	9ba0 <memcpy>
}
    57ac:	f107 0768 	add.w	r7, r7, #104	; 0x68
    57b0:	46bd      	mov	sp, r7
    57b2:	bd80      	pop	{r7, pc}

000057b4 <MSS_SYS_start_clock_monitor>:
 */
uint8_t MSS_SYS_start_clock_monitor
(
    void
)
{
    57b4:	b580      	push	{r7, lr}
    57b6:	b088      	sub	sp, #32
    57b8:	af04      	add	r7, sp, #16
    
    /*
     * The Start clock monitoring tamper Control service is available only on 
     * G4X device.
     */
    ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION);
    57ba:	f248 0300 	movw	r3, #32768	; 0x8000
    57be:	f2c4 0303 	movt	r3, #16387	; 0x4003
    57c2:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    57c6:	f64f 0302 	movw	r3, #63490	; 0xf802
    57ca:	429a      	cmp	r2, r3
    57cc:	d100      	bne.n	57d0 <MSS_SYS_start_clock_monitor+0x1c>
    57ce:	be00      	bkpt	0x0000
    ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION);
    57d0:	f248 0300 	movw	r3, #32768	; 0x8000
    57d4:	f2c4 0303 	movt	r3, #16387	; 0x4003
    57d8:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    57dc:	f64f 0302 	movw	r3, #63490	; 0xf802
    57e0:	f2c0 0301 	movt	r3, #1
    57e4:	429a      	cmp	r2, r3
    57e6:	d100      	bne.n	57ea <MSS_SYS_start_clock_monitor+0x36>
    57e8:	be00      	bkpt	0x0000
    ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION);
    57ea:	f248 0300 	movw	r3, #32768	; 0x8000
    57ee:	f2c4 0303 	movt	r3, #16387	; 0x4003
    57f2:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    57f6:	f64f 0302 	movw	r3, #63490	; 0xf802
    57fa:	f2c0 0302 	movt	r3, #2
    57fe:	429a      	cmp	r2, r3
    5800:	d100      	bne.n	5804 <MSS_SYS_start_clock_monitor+0x50>
    5802:	be00      	bkpt	0x0000
    ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION);
    5804:	f248 0300 	movw	r3, #32768	; 0x8000
    5808:	f2c4 0303 	movt	r3, #16387	; 0x4003
    580c:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5810:	f64f 0302 	movw	r3, #63490	; 0xf802
    5814:	f2c0 0303 	movt	r3, #3
    5818:	429a      	cmp	r2, r3
    581a:	d100      	bne.n	581e <MSS_SYS_start_clock_monitor+0x6a>
    581c:	be00      	bkpt	0x0000
    
    signal_request_start();
    581e:	f000 fa93 	bl	5d48 <signal_request_start>
    
    tamper_control_req[0] = TAMPER_CONTROL_REQUEST_CMD;
    5822:	f04f 031f 	mov.w	r3, #31
    5826:	723b      	strb	r3, [r7, #8]
    tamper_control_req[1] = 0x01u;
    5828:	f04f 0301 	mov.w	r3, #1
    582c:	727b      	strb	r3, [r7, #9]

    MSS_COMBLK_send_cmd(tamper_control_req,                 /* p_cmd */
    582e:	f107 0208 	add.w	r2, r7, #8
    5832:	f107 0304 	add.w	r3, r7, #4
    5836:	9300      	str	r3, [sp, #0]
    5838:	f04f 0302 	mov.w	r3, #2
    583c:	9301      	str	r3, [sp, #4]
    583e:	f645 5319 	movw	r3, #23833	; 0x5d19
    5842:	f2c0 0300 	movt	r3, #0
    5846:	9302      	str	r3, [sp, #8]
    5848:	4610      	mov	r0, r2
    584a:	f04f 0102 	mov.w	r1, #2
    584e:	f04f 0200 	mov.w	r2, #0
    5852:	f04f 0300 	mov.w	r3, #0
    5856:	f7fd fe17 	bl	3488 <MSS_COMBLK_send_cmd>
                        0u,                                 /* data_size */
                        response,                           /* p_response */
                        TAMPER_CONTROL_SERV_RESP_LENGTH,    /* response_size */
                        request_completion_handler);        /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    585a:	f000 fa91 	bl	5d80 <wait_for_request_completion>
    585e:	4603      	mov	r3, r0
    5860:	81fb      	strh	r3, [r7, #14]
    
    if((TAMPER_CONTROL_SERV_RESP_LENGTH == actual_response_length) &&
    5862:	89fb      	ldrh	r3, [r7, #14]
    5864:	2b02      	cmp	r3, #2
    5866:	d105      	bne.n	5874 <MSS_SYS_start_clock_monitor+0xc0>
       (TAMPER_CONTROL_REQUEST_CMD == response[0]))
    5868:	793b      	ldrb	r3, [r7, #4]
                        TAMPER_CONTROL_SERV_RESP_LENGTH,    /* response_size */
                        request_completion_handler);        /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    
    if((TAMPER_CONTROL_SERV_RESP_LENGTH == actual_response_length) &&
    586a:	2b1f      	cmp	r3, #31
    586c:	d102      	bne.n	5874 <MSS_SYS_start_clock_monitor+0xc0>
       (TAMPER_CONTROL_REQUEST_CMD == response[0]))
    {
        status = response[1];
    586e:	797b      	ldrb	r3, [r7, #5]
    5870:	737b      	strb	r3, [r7, #13]
                        TAMPER_CONTROL_SERV_RESP_LENGTH,    /* response_size */
                        request_completion_handler);        /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    
    if((TAMPER_CONTROL_SERV_RESP_LENGTH == actual_response_length) &&
    5872:	e002      	b.n	587a <MSS_SYS_start_clock_monitor+0xc6>
    {
        status = response[1];
    }
    else
    {
        status = MSS_SYS_UNEXPECTED_ERROR;
    5874:	f06f 0337 	mvn.w	r3, #55	; 0x37
    5878:	737b      	strb	r3, [r7, #13]
    }
    
    return status;
    587a:	7b7b      	ldrb	r3, [r7, #13]
}
    587c:	4618      	mov	r0, r3
    587e:	f107 0710 	add.w	r7, r7, #16
    5882:	46bd      	mov	sp, r7
    5884:	bd80      	pop	{r7, pc}
    5886:	bf00      	nop

00005888 <MSS_SYS_stop_clock_monitor>:
 */
uint8_t MSS_SYS_stop_clock_monitor
(
    void
)
{
    5888:	b580      	push	{r7, lr}
    588a:	b088      	sub	sp, #32
    588c:	af04      	add	r7, sp, #16
    
    /*
     * The Stop clock monitoring tamper Control service is available only on 
     * G4X device.
     */
    ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION);
    588e:	f248 0300 	movw	r3, #32768	; 0x8000
    5892:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5896:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    589a:	f64f 0302 	movw	r3, #63490	; 0xf802
    589e:	429a      	cmp	r2, r3
    58a0:	d100      	bne.n	58a4 <MSS_SYS_stop_clock_monitor+0x1c>
    58a2:	be00      	bkpt	0x0000
    ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION);
    58a4:	f248 0300 	movw	r3, #32768	; 0x8000
    58a8:	f2c4 0303 	movt	r3, #16387	; 0x4003
    58ac:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    58b0:	f64f 0302 	movw	r3, #63490	; 0xf802
    58b4:	f2c0 0301 	movt	r3, #1
    58b8:	429a      	cmp	r2, r3
    58ba:	d100      	bne.n	58be <MSS_SYS_stop_clock_monitor+0x36>
    58bc:	be00      	bkpt	0x0000
    ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION);
    58be:	f248 0300 	movw	r3, #32768	; 0x8000
    58c2:	f2c4 0303 	movt	r3, #16387	; 0x4003
    58c6:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    58ca:	f64f 0302 	movw	r3, #63490	; 0xf802
    58ce:	f2c0 0302 	movt	r3, #2
    58d2:	429a      	cmp	r2, r3
    58d4:	d100      	bne.n	58d8 <MSS_SYS_stop_clock_monitor+0x50>
    58d6:	be00      	bkpt	0x0000
    ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION);
    58d8:	f248 0300 	movw	r3, #32768	; 0x8000
    58dc:	f2c4 0303 	movt	r3, #16387	; 0x4003
    58e0:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    58e4:	f64f 0302 	movw	r3, #63490	; 0xf802
    58e8:	f2c0 0303 	movt	r3, #3
    58ec:	429a      	cmp	r2, r3
    58ee:	d100      	bne.n	58f2 <MSS_SYS_stop_clock_monitor+0x6a>
    58f0:	be00      	bkpt	0x0000
    
    signal_request_start();
    58f2:	f000 fa29 	bl	5d48 <signal_request_start>
    
    tamper_control_req[0] = TAMPER_CONTROL_REQUEST_CMD;
    58f6:	f04f 031f 	mov.w	r3, #31
    58fa:	723b      	strb	r3, [r7, #8]
    tamper_control_req[1] = 0x02u;
    58fc:	f04f 0302 	mov.w	r3, #2
    5900:	727b      	strb	r3, [r7, #9]

    MSS_COMBLK_send_cmd(tamper_control_req,                 /* p_cmd */
    5902:	f107 0208 	add.w	r2, r7, #8
    5906:	f107 0304 	add.w	r3, r7, #4
    590a:	9300      	str	r3, [sp, #0]
    590c:	f04f 0302 	mov.w	r3, #2
    5910:	9301      	str	r3, [sp, #4]
    5912:	f645 5319 	movw	r3, #23833	; 0x5d19
    5916:	f2c0 0300 	movt	r3, #0
    591a:	9302      	str	r3, [sp, #8]
    591c:	4610      	mov	r0, r2
    591e:	f04f 0102 	mov.w	r1, #2
    5922:	f04f 0200 	mov.w	r2, #0
    5926:	f04f 0300 	mov.w	r3, #0
    592a:	f7fd fdad 	bl	3488 <MSS_COMBLK_send_cmd>
                        0u,                                 /* data_size */
                        response,                           /* p_response */
                        TAMPER_CONTROL_SERV_RESP_LENGTH,    /* response_size */
                        request_completion_handler);        /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    592e:	f000 fa27 	bl	5d80 <wait_for_request_completion>
    5932:	4603      	mov	r3, r0
    5934:	81fb      	strh	r3, [r7, #14]
    
    if((TAMPER_CONTROL_SERV_RESP_LENGTH == actual_response_length) &&
    5936:	89fb      	ldrh	r3, [r7, #14]
    5938:	2b02      	cmp	r3, #2
    593a:	d105      	bne.n	5948 <MSS_SYS_stop_clock_monitor+0xc0>
       (TAMPER_CONTROL_REQUEST_CMD == response[0]))
    593c:	793b      	ldrb	r3, [r7, #4]
                        TAMPER_CONTROL_SERV_RESP_LENGTH,    /* response_size */
                        request_completion_handler);        /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    
    if((TAMPER_CONTROL_SERV_RESP_LENGTH == actual_response_length) &&
    593e:	2b1f      	cmp	r3, #31
    5940:	d102      	bne.n	5948 <MSS_SYS_stop_clock_monitor+0xc0>
       (TAMPER_CONTROL_REQUEST_CMD == response[0]))
    {
        status = response[1];
    5942:	797b      	ldrb	r3, [r7, #5]
    5944:	737b      	strb	r3, [r7, #13]
                        TAMPER_CONTROL_SERV_RESP_LENGTH,    /* response_size */
                        request_completion_handler);        /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    
    if((TAMPER_CONTROL_SERV_RESP_LENGTH == actual_response_length) &&
    5946:	e002      	b.n	594e <MSS_SYS_stop_clock_monitor+0xc6>
    {
        status = response[1];
    }
    else
    {
        status = MSS_SYS_UNEXPECTED_ERROR;
    5948:	f06f 0337 	mvn.w	r3, #55	; 0x37
    594c:	737b      	strb	r3, [r7, #13]
    }
    
    return status;
    594e:	7b7b      	ldrb	r3, [r7, #13]
}
    5950:	4618      	mov	r0, r3
    5952:	f107 0710 	add.w	r7, r7, #16
    5956:	46bd      	mov	sp, r7
    5958:	bd80      	pop	{r7, pc}
    595a:	bf00      	nop

0000595c <MSS_SYS_enable_puf_power_down>:
 */
uint8_t MSS_SYS_enable_puf_power_down
(
    void
)
{
    595c:	b580      	push	{r7, lr}
    595e:	b088      	sub	sp, #32
    5960:	af04      	add	r7, sp, #16
    uint16_t actual_response_length;
    
    /*
     * The Enable PUF power down service is available only on G4X device.
     */
    ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION);
    5962:	f248 0300 	movw	r3, #32768	; 0x8000
    5966:	f2c4 0303 	movt	r3, #16387	; 0x4003
    596a:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    596e:	f64f 0302 	movw	r3, #63490	; 0xf802
    5972:	429a      	cmp	r2, r3
    5974:	d100      	bne.n	5978 <MSS_SYS_enable_puf_power_down+0x1c>
    5976:	be00      	bkpt	0x0000
    ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION);
    5978:	f248 0300 	movw	r3, #32768	; 0x8000
    597c:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5980:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5984:	f64f 0302 	movw	r3, #63490	; 0xf802
    5988:	f2c0 0301 	movt	r3, #1
    598c:	429a      	cmp	r2, r3
    598e:	d100      	bne.n	5992 <MSS_SYS_enable_puf_power_down+0x36>
    5990:	be00      	bkpt	0x0000
    ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION);
    5992:	f248 0300 	movw	r3, #32768	; 0x8000
    5996:	f2c4 0303 	movt	r3, #16387	; 0x4003
    599a:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    599e:	f64f 0302 	movw	r3, #63490	; 0xf802
    59a2:	f2c0 0302 	movt	r3, #2
    59a6:	429a      	cmp	r2, r3
    59a8:	d100      	bne.n	59ac <MSS_SYS_enable_puf_power_down+0x50>
    59aa:	be00      	bkpt	0x0000
    ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION);
    59ac:	f248 0300 	movw	r3, #32768	; 0x8000
    59b0:	f2c4 0303 	movt	r3, #16387	; 0x4003
    59b4:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    59b8:	f64f 0302 	movw	r3, #63490	; 0xf802
    59bc:	f2c0 0303 	movt	r3, #3
    59c0:	429a      	cmp	r2, r3
    59c2:	d100      	bne.n	59c6 <MSS_SYS_enable_puf_power_down+0x6a>
    59c4:	be00      	bkpt	0x0000
    
    signal_request_start();
    59c6:	f000 f9bf 	bl	5d48 <signal_request_start>
    
    tamper_control_req[0] = TAMPER_CONTROL_REQUEST_CMD;
    59ca:	f04f 031f 	mov.w	r3, #31
    59ce:	723b      	strb	r3, [r7, #8]
    tamper_control_req[1] = 0x04u;
    59d0:	f04f 0304 	mov.w	r3, #4
    59d4:	727b      	strb	r3, [r7, #9]

    MSS_COMBLK_send_cmd(tamper_control_req,                 /* p_cmd */
    59d6:	f107 0208 	add.w	r2, r7, #8
    59da:	f107 0304 	add.w	r3, r7, #4
    59de:	9300      	str	r3, [sp, #0]
    59e0:	f04f 0302 	mov.w	r3, #2
    59e4:	9301      	str	r3, [sp, #4]
    59e6:	f645 5319 	movw	r3, #23833	; 0x5d19
    59ea:	f2c0 0300 	movt	r3, #0
    59ee:	9302      	str	r3, [sp, #8]
    59f0:	4610      	mov	r0, r2
    59f2:	f04f 0102 	mov.w	r1, #2
    59f6:	f04f 0200 	mov.w	r2, #0
    59fa:	f04f 0300 	mov.w	r3, #0
    59fe:	f7fd fd43 	bl	3488 <MSS_COMBLK_send_cmd>
                        0u,                                 /* data_size */
                        response,                           /* p_response */
                        TAMPER_CONTROL_SERV_RESP_LENGTH,    /* response_size */
                        request_completion_handler);        /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    5a02:	f000 f9bd 	bl	5d80 <wait_for_request_completion>
    5a06:	4603      	mov	r3, r0
    5a08:	81fb      	strh	r3, [r7, #14]
    
    if((TAMPER_CONTROL_SERV_RESP_LENGTH == actual_response_length) &&
    5a0a:	89fb      	ldrh	r3, [r7, #14]
    5a0c:	2b02      	cmp	r3, #2
    5a0e:	d105      	bne.n	5a1c <MSS_SYS_enable_puf_power_down+0xc0>
       (TAMPER_CONTROL_REQUEST_CMD == response[0]))
    5a10:	793b      	ldrb	r3, [r7, #4]
                        TAMPER_CONTROL_SERV_RESP_LENGTH,    /* response_size */
                        request_completion_handler);        /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    
    if((TAMPER_CONTROL_SERV_RESP_LENGTH == actual_response_length) &&
    5a12:	2b1f      	cmp	r3, #31
    5a14:	d102      	bne.n	5a1c <MSS_SYS_enable_puf_power_down+0xc0>
       (TAMPER_CONTROL_REQUEST_CMD == response[0]))
    {
        status = response[1];
    5a16:	797b      	ldrb	r3, [r7, #5]
    5a18:	737b      	strb	r3, [r7, #13]
                        TAMPER_CONTROL_SERV_RESP_LENGTH,    /* response_size */
                        request_completion_handler);        /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    
    if((TAMPER_CONTROL_SERV_RESP_LENGTH == actual_response_length) &&
    5a1a:	e002      	b.n	5a22 <MSS_SYS_enable_puf_power_down+0xc6>
    {
        status = response[1];
    }
    else
    {
        status = MSS_SYS_UNEXPECTED_ERROR;
    5a1c:	f06f 0337 	mvn.w	r3, #55	; 0x37
    5a20:	737b      	strb	r3, [r7, #13]
    }
    
    return status;
    5a22:	7b7b      	ldrb	r3, [r7, #13]
}
    5a24:	4618      	mov	r0, r3
    5a26:	f107 0710 	add.w	r7, r7, #16
    5a2a:	46bd      	mov	sp, r7
    5a2c:	bd80      	pop	{r7, pc}
    5a2e:	bf00      	nop

00005a30 <MSS_SYS_disable_puf_power_down>:
 */
uint8_t MSS_SYS_disable_puf_power_down
(
    void
)
{
    5a30:	b580      	push	{r7, lr}
    5a32:	b088      	sub	sp, #32
    5a34:	af04      	add	r7, sp, #16
    uint16_t actual_response_length;
    
    /*
     * Disable PUF power down is available only on G4X device.
     */
    ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION);
    5a36:	f248 0300 	movw	r3, #32768	; 0x8000
    5a3a:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5a3e:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5a42:	f64f 0302 	movw	r3, #63490	; 0xf802
    5a46:	429a      	cmp	r2, r3
    5a48:	d100      	bne.n	5a4c <MSS_SYS_disable_puf_power_down+0x1c>
    5a4a:	be00      	bkpt	0x0000
    ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION);
    5a4c:	f248 0300 	movw	r3, #32768	; 0x8000
    5a50:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5a54:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5a58:	f64f 0302 	movw	r3, #63490	; 0xf802
    5a5c:	f2c0 0301 	movt	r3, #1
    5a60:	429a      	cmp	r2, r3
    5a62:	d100      	bne.n	5a66 <MSS_SYS_disable_puf_power_down+0x36>
    5a64:	be00      	bkpt	0x0000
    ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION);
    5a66:	f248 0300 	movw	r3, #32768	; 0x8000
    5a6a:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5a6e:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5a72:	f64f 0302 	movw	r3, #63490	; 0xf802
    5a76:	f2c0 0302 	movt	r3, #2
    5a7a:	429a      	cmp	r2, r3
    5a7c:	d100      	bne.n	5a80 <MSS_SYS_disable_puf_power_down+0x50>
    5a7e:	be00      	bkpt	0x0000
    ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION);
    5a80:	f248 0300 	movw	r3, #32768	; 0x8000
    5a84:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5a88:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5a8c:	f64f 0302 	movw	r3, #63490	; 0xf802
    5a90:	f2c0 0303 	movt	r3, #3
    5a94:	429a      	cmp	r2, r3
    5a96:	d100      	bne.n	5a9a <MSS_SYS_disable_puf_power_down+0x6a>
    5a98:	be00      	bkpt	0x0000
    
    signal_request_start();
    5a9a:	f000 f955 	bl	5d48 <signal_request_start>
    
    tamper_control_req[0] = TAMPER_CONTROL_REQUEST_CMD;
    5a9e:	f04f 031f 	mov.w	r3, #31
    5aa2:	723b      	strb	r3, [r7, #8]
    tamper_control_req[1] = 0x08u;
    5aa4:	f04f 0308 	mov.w	r3, #8
    5aa8:	727b      	strb	r3, [r7, #9]

    MSS_COMBLK_send_cmd(tamper_control_req,                 /* p_cmd */
    5aaa:	f107 0208 	add.w	r2, r7, #8
    5aae:	f107 0304 	add.w	r3, r7, #4
    5ab2:	9300      	str	r3, [sp, #0]
    5ab4:	f04f 0302 	mov.w	r3, #2
    5ab8:	9301      	str	r3, [sp, #4]
    5aba:	f645 5319 	movw	r3, #23833	; 0x5d19
    5abe:	f2c0 0300 	movt	r3, #0
    5ac2:	9302      	str	r3, [sp, #8]
    5ac4:	4610      	mov	r0, r2
    5ac6:	f04f 0102 	mov.w	r1, #2
    5aca:	f04f 0200 	mov.w	r2, #0
    5ace:	f04f 0300 	mov.w	r3, #0
    5ad2:	f7fd fcd9 	bl	3488 <MSS_COMBLK_send_cmd>
                        0u,                                 /* data_size */
                        response,                           /* p_response */
                        TAMPER_CONTROL_SERV_RESP_LENGTH,    /* response_size */
                        request_completion_handler);        /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    5ad6:	f000 f953 	bl	5d80 <wait_for_request_completion>
    5ada:	4603      	mov	r3, r0
    5adc:	81fb      	strh	r3, [r7, #14]
    
    if((TAMPER_CONTROL_SERV_RESP_LENGTH == actual_response_length) &&
    5ade:	89fb      	ldrh	r3, [r7, #14]
    5ae0:	2b02      	cmp	r3, #2
    5ae2:	d105      	bne.n	5af0 <MSS_SYS_disable_puf_power_down+0xc0>
       (TAMPER_CONTROL_REQUEST_CMD == response[0]))
    5ae4:	793b      	ldrb	r3, [r7, #4]
                        TAMPER_CONTROL_SERV_RESP_LENGTH,    /* response_size */
                        request_completion_handler);        /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    
    if((TAMPER_CONTROL_SERV_RESP_LENGTH == actual_response_length) &&
    5ae6:	2b1f      	cmp	r3, #31
    5ae8:	d102      	bne.n	5af0 <MSS_SYS_disable_puf_power_down+0xc0>
       (TAMPER_CONTROL_REQUEST_CMD == response[0]))
    {
        status = response[1];
    5aea:	797b      	ldrb	r3, [r7, #5]
    5aec:	737b      	strb	r3, [r7, #13]
                        TAMPER_CONTROL_SERV_RESP_LENGTH,    /* response_size */
                        request_completion_handler);        /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    
    if((TAMPER_CONTROL_SERV_RESP_LENGTH == actual_response_length) &&
    5aee:	e002      	b.n	5af6 <MSS_SYS_disable_puf_power_down+0xc6>
    {
        status = response[1];
    }
    else
    {
        status = MSS_SYS_UNEXPECTED_ERROR;
    5af0:	f06f 0337 	mvn.w	r3, #55	; 0x37
    5af4:	737b      	strb	r3, [r7, #13]
    }
    
    return status;
    5af6:	7b7b      	ldrb	r3, [r7, #13]
}
    5af8:	4618      	mov	r0, r3
    5afa:	f107 0710 	add.w	r7, r7, #16
    5afe:	46bd      	mov	sp, r7
    5b00:	bd80      	pop	{r7, pc}
    5b02:	bf00      	nop

00005b04 <MSS_SYS_clear_lock_parity>:
 */
uint8_t MSS_SYS_clear_lock_parity
(
    void
)
{
    5b04:	b580      	push	{r7, lr}
    5b06:	b088      	sub	sp, #32
    5b08:	af04      	add	r7, sp, #16
    uint16_t actual_response_length;
    
    /*
     * The Clear Lock parity is available only on G4X device.
     */
    ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION);
    5b0a:	f248 0300 	movw	r3, #32768	; 0x8000
    5b0e:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5b12:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5b16:	f64f 0302 	movw	r3, #63490	; 0xf802
    5b1a:	429a      	cmp	r2, r3
    5b1c:	d100      	bne.n	5b20 <MSS_SYS_clear_lock_parity+0x1c>
    5b1e:	be00      	bkpt	0x0000
    ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION);
    5b20:	f248 0300 	movw	r3, #32768	; 0x8000
    5b24:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5b28:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5b2c:	f64f 0302 	movw	r3, #63490	; 0xf802
    5b30:	f2c0 0301 	movt	r3, #1
    5b34:	429a      	cmp	r2, r3
    5b36:	d100      	bne.n	5b3a <MSS_SYS_clear_lock_parity+0x36>
    5b38:	be00      	bkpt	0x0000
    ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION);
    5b3a:	f248 0300 	movw	r3, #32768	; 0x8000
    5b3e:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5b42:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5b46:	f64f 0302 	movw	r3, #63490	; 0xf802
    5b4a:	f2c0 0302 	movt	r3, #2
    5b4e:	429a      	cmp	r2, r3
    5b50:	d100      	bne.n	5b54 <MSS_SYS_clear_lock_parity+0x50>
    5b52:	be00      	bkpt	0x0000
    ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION);
    5b54:	f248 0300 	movw	r3, #32768	; 0x8000
    5b58:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5b5c:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5b60:	f64f 0302 	movw	r3, #63490	; 0xf802
    5b64:	f2c0 0303 	movt	r3, #3
    5b68:	429a      	cmp	r2, r3
    5b6a:	d100      	bne.n	5b6e <MSS_SYS_clear_lock_parity+0x6a>
    5b6c:	be00      	bkpt	0x0000
    
    signal_request_start();
    5b6e:	f000 f8eb 	bl	5d48 <signal_request_start>
    
    tamper_control_req[0] = TAMPER_CONTROL_REQUEST_CMD;
    5b72:	f04f 031f 	mov.w	r3, #31
    5b76:	723b      	strb	r3, [r7, #8]
    tamper_control_req[1] = 0x10u;
    5b78:	f04f 0310 	mov.w	r3, #16
    5b7c:	727b      	strb	r3, [r7, #9]

    MSS_COMBLK_send_cmd(tamper_control_req,                 /* p_cmd */
    5b7e:	f107 0208 	add.w	r2, r7, #8
    5b82:	f107 0304 	add.w	r3, r7, #4
    5b86:	9300      	str	r3, [sp, #0]
    5b88:	f04f 0302 	mov.w	r3, #2
    5b8c:	9301      	str	r3, [sp, #4]
    5b8e:	f645 5319 	movw	r3, #23833	; 0x5d19
    5b92:	f2c0 0300 	movt	r3, #0
    5b96:	9302      	str	r3, [sp, #8]
    5b98:	4610      	mov	r0, r2
    5b9a:	f04f 0102 	mov.w	r1, #2
    5b9e:	f04f 0200 	mov.w	r2, #0
    5ba2:	f04f 0300 	mov.w	r3, #0
    5ba6:	f7fd fc6f 	bl	3488 <MSS_COMBLK_send_cmd>
                        0u,                                 /* data_size */
                        response,                           /* p_response */
                        TAMPER_CONTROL_SERV_RESP_LENGTH,    /* response_size */
                        request_completion_handler);        /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    5baa:	f000 f8e9 	bl	5d80 <wait_for_request_completion>
    5bae:	4603      	mov	r3, r0
    5bb0:	81fb      	strh	r3, [r7, #14]
    
    if((TAMPER_CONTROL_SERV_RESP_LENGTH == actual_response_length) &&
    5bb2:	89fb      	ldrh	r3, [r7, #14]
    5bb4:	2b02      	cmp	r3, #2
    5bb6:	d105      	bne.n	5bc4 <MSS_SYS_clear_lock_parity+0xc0>
       (TAMPER_CONTROL_REQUEST_CMD == response[0]))
    5bb8:	793b      	ldrb	r3, [r7, #4]
                        TAMPER_CONTROL_SERV_RESP_LENGTH,    /* response_size */
                        request_completion_handler);        /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    
    if((TAMPER_CONTROL_SERV_RESP_LENGTH == actual_response_length) &&
    5bba:	2b1f      	cmp	r3, #31
    5bbc:	d102      	bne.n	5bc4 <MSS_SYS_clear_lock_parity+0xc0>
       (TAMPER_CONTROL_REQUEST_CMD == response[0]))
    {
        status = response[1];
    5bbe:	797b      	ldrb	r3, [r7, #5]
    5bc0:	737b      	strb	r3, [r7, #13]
                        TAMPER_CONTROL_SERV_RESP_LENGTH,    /* response_size */
                        request_completion_handler);        /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    
    if((TAMPER_CONTROL_SERV_RESP_LENGTH == actual_response_length) &&
    5bc2:	e002      	b.n	5bca <MSS_SYS_clear_lock_parity+0xc6>
    {
        status = response[1];
    }
    else
    {
        status = MSS_SYS_UNEXPECTED_ERROR;
    5bc4:	f06f 0337 	mvn.w	r3, #55	; 0x37
    5bc8:	737b      	strb	r3, [r7, #13]
    }
    
    return status;
    5bca:	7b7b      	ldrb	r3, [r7, #13]
}
    5bcc:	4618      	mov	r0, r3
    5bce:	f107 0710 	add.w	r7, r7, #16
    5bd2:	46bd      	mov	sp, r7
    5bd4:	bd80      	pop	{r7, pc}
    5bd6:	bf00      	nop

00005bd8 <MSS_SYS_clear_mesh_short>:
 */
uint8_t MSS_SYS_clear_mesh_short
(
    void
)
{
    5bd8:	b580      	push	{r7, lr}
    5bda:	b088      	sub	sp, #32
    5bdc:	af04      	add	r7, sp, #16
    uint16_t actual_response_length;
    
    /*
     * The Clear mesh short service is available only on G4X device.
     */
    ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION);
    5bde:	f248 0300 	movw	r3, #32768	; 0x8000
    5be2:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5be6:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5bea:	f64f 0302 	movw	r3, #63490	; 0xf802
    5bee:	429a      	cmp	r2, r3
    5bf0:	d100      	bne.n	5bf4 <MSS_SYS_clear_mesh_short+0x1c>
    5bf2:	be00      	bkpt	0x0000
    ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION);
    5bf4:	f248 0300 	movw	r3, #32768	; 0x8000
    5bf8:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5bfc:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5c00:	f64f 0302 	movw	r3, #63490	; 0xf802
    5c04:	f2c0 0301 	movt	r3, #1
    5c08:	429a      	cmp	r2, r3
    5c0a:	d100      	bne.n	5c0e <MSS_SYS_clear_mesh_short+0x36>
    5c0c:	be00      	bkpt	0x0000
    ASSERT(0x0002F802u != SYSREG->DEVICE_VERSION);
    5c0e:	f248 0300 	movw	r3, #32768	; 0x8000
    5c12:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5c16:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5c1a:	f64f 0302 	movw	r3, #63490	; 0xf802
    5c1e:	f2c0 0302 	movt	r3, #2
    5c22:	429a      	cmp	r2, r3
    5c24:	d100      	bne.n	5c28 <MSS_SYS_clear_mesh_short+0x50>
    5c26:	be00      	bkpt	0x0000
    ASSERT(0x0003F802u != SYSREG->DEVICE_VERSION);
    5c28:	f248 0300 	movw	r3, #32768	; 0x8000
    5c2c:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5c30:	f8d3 214c 	ldr.w	r2, [r3, #332]	; 0x14c
    5c34:	f64f 0302 	movw	r3, #63490	; 0xf802
    5c38:	f2c0 0303 	movt	r3, #3
    5c3c:	429a      	cmp	r2, r3
    5c3e:	d100      	bne.n	5c42 <MSS_SYS_clear_mesh_short+0x6a>
    5c40:	be00      	bkpt	0x0000
    
    signal_request_start();
    5c42:	f000 f881 	bl	5d48 <signal_request_start>
    
    tamper_control_req[0] = TAMPER_CONTROL_REQUEST_CMD;
    5c46:	f04f 031f 	mov.w	r3, #31
    5c4a:	723b      	strb	r3, [r7, #8]
    tamper_control_req[1] = 0x20u;
    5c4c:	f04f 0320 	mov.w	r3, #32
    5c50:	727b      	strb	r3, [r7, #9]

    MSS_COMBLK_send_cmd(tamper_control_req,                 /* p_cmd */
    5c52:	f107 0208 	add.w	r2, r7, #8
    5c56:	f107 0304 	add.w	r3, r7, #4
    5c5a:	9300      	str	r3, [sp, #0]
    5c5c:	f04f 0302 	mov.w	r3, #2
    5c60:	9301      	str	r3, [sp, #4]
    5c62:	f645 5319 	movw	r3, #23833	; 0x5d19
    5c66:	f2c0 0300 	movt	r3, #0
    5c6a:	9302      	str	r3, [sp, #8]
    5c6c:	4610      	mov	r0, r2
    5c6e:	f04f 0102 	mov.w	r1, #2
    5c72:	f04f 0200 	mov.w	r2, #0
    5c76:	f04f 0300 	mov.w	r3, #0
    5c7a:	f7fd fc05 	bl	3488 <MSS_COMBLK_send_cmd>
                        0u,                                 /* data_size */
                        response,                           /* p_response */
                        TAMPER_CONTROL_SERV_RESP_LENGTH,    /* response_size */
                        request_completion_handler);        /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    5c7e:	f000 f87f 	bl	5d80 <wait_for_request_completion>
    5c82:	4603      	mov	r3, r0
    5c84:	81fb      	strh	r3, [r7, #14]
    
    if((TAMPER_CONTROL_SERV_RESP_LENGTH == actual_response_length) &&
    5c86:	89fb      	ldrh	r3, [r7, #14]
    5c88:	2b02      	cmp	r3, #2
    5c8a:	d105      	bne.n	5c98 <MSS_SYS_clear_mesh_short+0xc0>
       (TAMPER_CONTROL_REQUEST_CMD == response[0]))
    5c8c:	793b      	ldrb	r3, [r7, #4]
                        TAMPER_CONTROL_SERV_RESP_LENGTH,    /* response_size */
                        request_completion_handler);        /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    
    if((TAMPER_CONTROL_SERV_RESP_LENGTH == actual_response_length) &&
    5c8e:	2b1f      	cmp	r3, #31
    5c90:	d102      	bne.n	5c98 <MSS_SYS_clear_mesh_short+0xc0>
       (TAMPER_CONTROL_REQUEST_CMD == response[0]))
    {
        status = response[1];
    5c92:	797b      	ldrb	r3, [r7, #5]
    5c94:	737b      	strb	r3, [r7, #13]
                        TAMPER_CONTROL_SERV_RESP_LENGTH,    /* response_size */
                        request_completion_handler);        /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    
    if((TAMPER_CONTROL_SERV_RESP_LENGTH == actual_response_length) &&
    5c96:	e002      	b.n	5c9e <MSS_SYS_clear_mesh_short+0xc6>
    {
        status = response[1];
    }
    else
    {
        status = MSS_SYS_UNEXPECTED_ERROR;
    5c98:	f06f 0337 	mvn.w	r3, #55	; 0x37
    5c9c:	737b      	strb	r3, [r7, #13]
    }
    
    return status;
    5c9e:	7b7b      	ldrb	r3, [r7, #13]
}
    5ca0:	4618      	mov	r0, r3
    5ca2:	f107 0710 	add.w	r7, r7, #16
    5ca6:	46bd      	mov	sp, r7
    5ca8:	bd80      	pop	{r7, pc}
    5caa:	bf00      	nop

00005cac <execute_service>:
    uint8_t cmd_opcode,
    uint8_t * cmd_params_ptr,
    uint8_t * response,
    uint16_t response_length
)
{
    5cac:	b580      	push	{r7, lr}
    5cae:	b088      	sub	sp, #32
    5cb0:	af02      	add	r7, sp, #8
    5cb2:	60b9      	str	r1, [r7, #8]
    5cb4:	607a      	str	r2, [r7, #4]
    5cb6:	4602      	mov	r2, r0
    5cb8:	73fa      	strb	r2, [r7, #15]
    5cba:	807b      	strh	r3, [r7, #2]
    uint8_t status;
    uint16_t actual_response_length;
    
    signal_request_start();
    5cbc:	f000 f844 	bl	5d48 <signal_request_start>
    
    MSS_COMBLK_send_cmd_with_ptr(cmd_opcode,                    /* cmd_opcode */
    5cc0:	68ba      	ldr	r2, [r7, #8]
    5cc2:	7bf9      	ldrb	r1, [r7, #15]
    5cc4:	f8b7 c002 	ldrh.w	ip, [r7, #2]
    5cc8:	f645 5319 	movw	r3, #23833	; 0x5d19
    5ccc:	f2c0 0300 	movt	r3, #0
    5cd0:	9300      	str	r3, [sp, #0]
    5cd2:	4608      	mov	r0, r1
    5cd4:	4611      	mov	r1, r2
    5cd6:	687a      	ldr	r2, [r7, #4]
    5cd8:	4663      	mov	r3, ip
    5cda:	f7fd fb25 	bl	3328 <MSS_COMBLK_send_cmd_with_ptr>
                                 (uint32_t)cmd_params_ptr,      /* cmd_params_ptr */
                                 response,                      /* p_response */
                                 response_length,               /* response_size */
                                 request_completion_handler);   /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    5cde:	f000 f84f 	bl	5d80 <wait_for_request_completion>
    5ce2:	4603      	mov	r3, r0
    5ce4:	82fb      	strh	r3, [r7, #22]
    
    if((response_length == actual_response_length) && (cmd_opcode == response[0]))
    5ce6:	887a      	ldrh	r2, [r7, #2]
    5ce8:	8afb      	ldrh	r3, [r7, #22]
    5cea:	429a      	cmp	r2, r3
    5cec:	d10a      	bne.n	5d04 <execute_service+0x58>
    5cee:	687b      	ldr	r3, [r7, #4]
    5cf0:	781b      	ldrb	r3, [r3, #0]
    5cf2:	7bfa      	ldrb	r2, [r7, #15]
    5cf4:	429a      	cmp	r2, r3
    5cf6:	d105      	bne.n	5d04 <execute_service+0x58>
    {
        status = response[1];
    5cf8:	687b      	ldr	r3, [r7, #4]
    5cfa:	f103 0301 	add.w	r3, r3, #1
    5cfe:	781b      	ldrb	r3, [r3, #0]
    5d00:	757b      	strb	r3, [r7, #21]
                                 response_length,               /* response_size */
                                 request_completion_handler);   /* completion_handler */
    
    actual_response_length = wait_for_request_completion();
    
    if((response_length == actual_response_length) && (cmd_opcode == response[0]))
    5d02:	e002      	b.n	5d0a <execute_service+0x5e>
    {
        status = response[1];
    }
    else
    {
        status = MSS_SYS_UNEXPECTED_ERROR;
    5d04:	f06f 0337 	mvn.w	r3, #55	; 0x37
    5d08:	757b      	strb	r3, [r7, #21]
    }
    
    return status;
    5d0a:	7d7b      	ldrb	r3, [r7, #21]
}
    5d0c:	4618      	mov	r0, r3
    5d0e:	f107 0718 	add.w	r7, r7, #24
    5d12:	46bd      	mov	sp, r7
    5d14:	bd80      	pop	{r7, pc}
    5d16:	bf00      	nop

00005d18 <request_completion_handler>:
static void request_completion_handler
(
    uint8_t * p_response,
    uint16_t response_size
)
{
    5d18:	b480      	push	{r7}
    5d1a:	b083      	sub	sp, #12
    5d1c:	af00      	add	r7, sp, #0
    5d1e:	6078      	str	r0, [r7, #4]
    5d20:	460b      	mov	r3, r1
    5d22:	807b      	strh	r3, [r7, #2]
    g_request_in_progress = 0u;
    5d24:	f240 1364 	movw	r3, #356	; 0x164
    5d28:	f2c2 0300 	movt	r3, #8192	; 0x2000
    5d2c:	f04f 0200 	mov.w	r2, #0
    5d30:	701a      	strb	r2, [r3, #0]
    g_last_response_length = response_size;
    5d32:	f240 1366 	movw	r3, #358	; 0x166
    5d36:	f2c2 0300 	movt	r3, #8192	; 0x2000
    5d3a:	887a      	ldrh	r2, [r7, #2]
    5d3c:	801a      	strh	r2, [r3, #0]
}
    5d3e:	f107 070c 	add.w	r7, r7, #12
    5d42:	46bd      	mov	sp, r7
    5d44:	bc80      	pop	{r7}
    5d46:	4770      	bx	lr

00005d48 <signal_request_start>:

/*==============================================================================
 *
 */
static void signal_request_start(void)
{
    5d48:	b480      	push	{r7}
    5d4a:	af00      	add	r7, sp, #0
    /* Wait for current request to complete. */
    while(g_request_in_progress)
    5d4c:	f240 1364 	movw	r3, #356	; 0x164
    5d50:	f2c2 0300 	movt	r3, #8192	; 0x2000
    5d54:	781b      	ldrb	r3, [r3, #0]
    5d56:	b2db      	uxtb	r3, r3
    5d58:	2b00      	cmp	r3, #0
    5d5a:	d1f7      	bne.n	5d4c <signal_request_start+0x4>
    {
        ;
    }
    
    g_request_in_progress = 1u;
    5d5c:	f240 1364 	movw	r3, #356	; 0x164
    5d60:	f2c2 0300 	movt	r3, #8192	; 0x2000
    5d64:	f04f 0201 	mov.w	r2, #1
    5d68:	701a      	strb	r2, [r3, #0]
    g_last_response_length = 0u;
    5d6a:	f240 1366 	movw	r3, #358	; 0x166
    5d6e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    5d72:	f04f 0200 	mov.w	r2, #0
    5d76:	801a      	strh	r2, [r3, #0]
}
    5d78:	46bd      	mov	sp, r7
    5d7a:	bc80      	pop	{r7}
    5d7c:	4770      	bx	lr
    5d7e:	bf00      	nop

00005d80 <wait_for_request_completion>:

/*==============================================================================
 *
 */
static uint16_t wait_for_request_completion(void)
{
    5d80:	b480      	push	{r7}
    5d82:	af00      	add	r7, sp, #0
    while(g_request_in_progress)
    5d84:	f240 1364 	movw	r3, #356	; 0x164
    5d88:	f2c2 0300 	movt	r3, #8192	; 0x2000
    5d8c:	781b      	ldrb	r3, [r3, #0]
    5d8e:	b2db      	uxtb	r3, r3
    5d90:	2b00      	cmp	r3, #0
    5d92:	d1f7      	bne.n	5d84 <wait_for_request_completion+0x4>
    {
        ;
    }
    
    return g_last_response_length;
    5d94:	f240 1366 	movw	r3, #358	; 0x166
    5d98:	f2c2 0300 	movt	r3, #8192	; 0x2000
    5d9c:	881b      	ldrh	r3, [r3, #0]
    5d9e:	b29b      	uxth	r3, r3
}
    5da0:	4618      	mov	r0, r3
    5da2:	46bd      	mov	sp, r7
    5da4:	bc80      	pop	{r7}
    5da6:	4770      	bx	lr

00005da8 <write_ptr_value_into_array>:
(
    const uint8_t * pointer,
    uint8_t target_array[],
    uint32_t array_index
)
{
    5da8:	b480      	push	{r7}
    5daa:	b085      	sub	sp, #20
    5dac:	af00      	add	r7, sp, #0
    5dae:	60f8      	str	r0, [r7, #12]
    5db0:	60b9      	str	r1, [r7, #8]
    5db2:	607a      	str	r2, [r7, #4]
    target_array[array_index] = (uint8_t)((uint32_t)pointer);
    5db4:	68ba      	ldr	r2, [r7, #8]
    5db6:	687b      	ldr	r3, [r7, #4]
    5db8:	4413      	add	r3, r2
    5dba:	68fa      	ldr	r2, [r7, #12]
    5dbc:	b2d2      	uxtb	r2, r2
    5dbe:	701a      	strb	r2, [r3, #0]
    target_array[array_index + 1] = (uint8_t)((uint32_t)pointer >> 8u);
    5dc0:	687b      	ldr	r3, [r7, #4]
    5dc2:	f103 0201 	add.w	r2, r3, #1
    5dc6:	68bb      	ldr	r3, [r7, #8]
    5dc8:	4413      	add	r3, r2
    5dca:	68fa      	ldr	r2, [r7, #12]
    5dcc:	ea4f 2212 	mov.w	r2, r2, lsr #8
    5dd0:	b2d2      	uxtb	r2, r2
    5dd2:	701a      	strb	r2, [r3, #0]
    target_array[array_index + 2] = (uint8_t)((uint32_t)pointer >> 16u);
    5dd4:	687b      	ldr	r3, [r7, #4]
    5dd6:	f103 0202 	add.w	r2, r3, #2
    5dda:	68bb      	ldr	r3, [r7, #8]
    5ddc:	4413      	add	r3, r2
    5dde:	68fa      	ldr	r2, [r7, #12]
    5de0:	ea4f 4212 	mov.w	r2, r2, lsr #16
    5de4:	b2d2      	uxtb	r2, r2
    5de6:	701a      	strb	r2, [r3, #0]
    target_array[array_index + 3] = (uint8_t)((uint32_t)pointer >> 24u);
    5de8:	687b      	ldr	r3, [r7, #4]
    5dea:	f103 0203 	add.w	r2, r3, #3
    5dee:	68bb      	ldr	r3, [r7, #8]
    5df0:	4413      	add	r3, r2
    5df2:	68fa      	ldr	r2, [r7, #12]
    5df4:	ea4f 6212 	mov.w	r2, r2, lsr #24
    5df8:	b2d2      	uxtb	r2, r2
    5dfa:	701a      	strb	r2, [r3, #0]
}
    5dfc:	f107 0714 	add.w	r7, r7, #20
    5e00:	46bd      	mov	sp, r7
    5e02:	bc80      	pop	{r7}
    5e04:	4770      	bx	lr
    5e06:	bf00      	nop

00005e08 <write_array_into_ptr_value>:
(
    uint8_t** pointer,
    uint8_t target_array[],
    uint32_t array_index
)
{
    5e08:	b480      	push	{r7}
    5e0a:	b087      	sub	sp, #28
    5e0c:	af00      	add	r7, sp, #0
    5e0e:	60f8      	str	r0, [r7, #12]
    5e10:	60b9      	str	r1, [r7, #8]
    5e12:	607a      	str	r2, [r7, #4]
    uint32_t var;
    
    var = (uint32_t)target_array[array_index + 3];
    5e14:	687b      	ldr	r3, [r7, #4]
    5e16:	f103 0203 	add.w	r2, r3, #3
    5e1a:	68bb      	ldr	r3, [r7, #8]
    5e1c:	4413      	add	r3, r2
    5e1e:	781b      	ldrb	r3, [r3, #0]
    5e20:	617b      	str	r3, [r7, #20]
    var = ((var << 8u) & 0xFFFFFF00) | target_array[array_index + 2];
    5e22:	697b      	ldr	r3, [r7, #20]
    5e24:	ea4f 2203 	mov.w	r2, r3, lsl #8
    5e28:	687b      	ldr	r3, [r7, #4]
    5e2a:	f103 0102 	add.w	r1, r3, #2
    5e2e:	68bb      	ldr	r3, [r7, #8]
    5e30:	440b      	add	r3, r1
    5e32:	781b      	ldrb	r3, [r3, #0]
    5e34:	ea42 0303 	orr.w	r3, r2, r3
    5e38:	617b      	str	r3, [r7, #20]
    var = ((var << 8u) & 0xFFFFFF00) | target_array[array_index + 1];
    5e3a:	697b      	ldr	r3, [r7, #20]
    5e3c:	ea4f 2203 	mov.w	r2, r3, lsl #8
    5e40:	687b      	ldr	r3, [r7, #4]
    5e42:	f103 0101 	add.w	r1, r3, #1
    5e46:	68bb      	ldr	r3, [r7, #8]
    5e48:	440b      	add	r3, r1
    5e4a:	781b      	ldrb	r3, [r3, #0]
    5e4c:	ea42 0303 	orr.w	r3, r2, r3
    5e50:	617b      	str	r3, [r7, #20]
    var = ((var << 8u) & 0xFFFFFF00) | target_array[array_index];
    5e52:	697b      	ldr	r3, [r7, #20]
    5e54:	ea4f 2203 	mov.w	r2, r3, lsl #8
    5e58:	68b9      	ldr	r1, [r7, #8]
    5e5a:	687b      	ldr	r3, [r7, #4]
    5e5c:	440b      	add	r3, r1
    5e5e:	781b      	ldrb	r3, [r3, #0]
    5e60:	ea42 0303 	orr.w	r3, r2, r3
    5e64:	617b      	str	r3, [r7, #20]
    
    *pointer = (uint8_t*)var;
    5e66:	697a      	ldr	r2, [r7, #20]
    5e68:	68fb      	ldr	r3, [r7, #12]
    5e6a:	601a      	str	r2, [r3, #0]
}
    5e6c:	f107 071c 	add.w	r7, r7, #28
    5e70:	46bd      	mov	sp, r7
    5e72:	bc80      	pop	{r7}
    5e74:	4770      	bx	lr
    5e76:	bf00      	nop

00005e78 <NVIC_EnableIRQ>:
    The function enables a device-specific interrupt in the NVIC interrupt controller.

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
    5e78:	b480      	push	{r7}
    5e7a:	b083      	sub	sp, #12
    5e7c:	af00      	add	r7, sp, #0
    5e7e:	4603      	mov	r3, r0
    5e80:	71fb      	strb	r3, [r7, #7]
  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
    5e82:	f24e 1300 	movw	r3, #57600	; 0xe100
    5e86:	f2ce 0300 	movt	r3, #57344	; 0xe000
    5e8a:	f997 2007 	ldrsb.w	r2, [r7, #7]
    5e8e:	ea4f 1252 	mov.w	r2, r2, lsr #5
    5e92:	79f9      	ldrb	r1, [r7, #7]
    5e94:	f001 011f 	and.w	r1, r1, #31
    5e98:	f04f 0001 	mov.w	r0, #1
    5e9c:	fa00 f101 	lsl.w	r1, r0, r1
    5ea0:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
}
    5ea4:	f107 070c 	add.w	r7, r7, #12
    5ea8:	46bd      	mov	sp, r7
    5eaa:	bc80      	pop	{r7}
    5eac:	4770      	bx	lr
    5eae:	bf00      	nop

00005eb0 <NVIC_DisableIRQ>:
    The function disables a device-specific interrupt in the NVIC interrupt controller.

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
    5eb0:	b480      	push	{r7}
    5eb2:	b083      	sub	sp, #12
    5eb4:	af00      	add	r7, sp, #0
    5eb6:	4603      	mov	r3, r0
    5eb8:	71fb      	strb	r3, [r7, #7]
  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
    5eba:	f24e 1300 	movw	r3, #57600	; 0xe100
    5ebe:	f2ce 0300 	movt	r3, #57344	; 0xe000
    5ec2:	f997 2007 	ldrsb.w	r2, [r7, #7]
    5ec6:	ea4f 1252 	mov.w	r2, r2, lsr #5
    5eca:	79f9      	ldrb	r1, [r7, #7]
    5ecc:	f001 011f 	and.w	r1, r1, #31
    5ed0:	f04f 0001 	mov.w	r0, #1
    5ed4:	fa00 f101 	lsl.w	r1, r0, r1
    5ed8:	f102 0220 	add.w	r2, r2, #32
    5edc:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
}
    5ee0:	f107 070c 	add.w	r7, r7, #12
    5ee4:	46bd      	mov	sp, r7
    5ee6:	bc80      	pop	{r7}
    5ee8:	4770      	bx	lr
    5eea:	bf00      	nop

00005eec <NVIC_ClearPendingIRQ>:
    The function clears the pending bit of an external interrupt.

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
    5eec:	b480      	push	{r7}
    5eee:	b083      	sub	sp, #12
    5ef0:	af00      	add	r7, sp, #0
    5ef2:	4603      	mov	r3, r0
    5ef4:	71fb      	strb	r3, [r7, #7]
  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
    5ef6:	f24e 1300 	movw	r3, #57600	; 0xe100
    5efa:	f2ce 0300 	movt	r3, #57344	; 0xe000
    5efe:	f997 2007 	ldrsb.w	r2, [r7, #7]
    5f02:	ea4f 1252 	mov.w	r2, r2, lsr #5
    5f06:	79f9      	ldrb	r1, [r7, #7]
    5f08:	f001 011f 	and.w	r1, r1, #31
    5f0c:	f04f 0001 	mov.w	r0, #1
    5f10:	fa00 f101 	lsl.w	r1, r0, r1
    5f14:	f102 0260 	add.w	r2, r2, #96	; 0x60
    5f18:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
}
    5f1c:	f107 070c 	add.w	r7, r7, #12
    5f20:	46bd      	mov	sp, r7
    5f22:	bc80      	pop	{r7}
    5f24:	4770      	bx	lr
    5f26:	bf00      	nop

00005f28 <MSS_SPI_init>:
 */
void MSS_SPI_init
(
    mss_spi_instance_t * this_spi
)
{
    5f28:	b580      	push	{r7, lr}
    5f2a:	b084      	sub	sp, #16
    5f2c:	af00      	add	r7, sp, #0
    5f2e:	6078      	str	r0, [r7, #4]
    uint16_t slave;
    
    ASSERT((this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1));
    5f30:	687a      	ldr	r2, [r7, #4]
    5f32:	f240 23bc 	movw	r3, #700	; 0x2bc
    5f36:	f2c2 0300 	movt	r3, #8192	; 0x2000
    5f3a:	429a      	cmp	r2, r3
    5f3c:	d007      	beq.n	5f4e <MSS_SPI_init+0x26>
    5f3e:	687a      	ldr	r2, [r7, #4]
    5f40:	f240 2338 	movw	r3, #568	; 0x238
    5f44:	f2c2 0300 	movt	r3, #8192	; 0x2000
    5f48:	429a      	cmp	r2, r3
    5f4a:	d000      	beq.n	5f4e <MSS_SPI_init+0x26>
    5f4c:	be00      	bkpt	0x0000
     * Initialize SPI driver instance data. Relies on the majority
     * of data requiring 0 for initial state so we just need to fill
     * with 0s and finish off with a small number of non zero values.
     */
    /* Shut down interrupts from the MSS SPI while we do this */
    NVIC_DisableIRQ( this_spi->irqn );
    5f4e:	687b      	ldr	r3, [r7, #4]
    5f50:	791b      	ldrb	r3, [r3, #4]
    5f52:	b25b      	sxtb	r3, r3
    5f54:	4618      	mov	r0, r3
    5f56:	f7ff ffab 	bl	5eb0 <NVIC_DisableIRQ>

    memset(this_spi, 0, sizeof(mss_spi_instance_t));
    5f5a:	6878      	ldr	r0, [r7, #4]
    5f5c:	f04f 0100 	mov.w	r1, #0
    5f60:	f04f 0284 	mov.w	r2, #132	; 0x84
    5f64:	f003 fee4 	bl	9d30 <memset>
    
    this_spi->cmd_done = 1u;
    5f68:	687b      	ldr	r3, [r7, #4]
    5f6a:	f04f 0201 	mov.w	r2, #1
    5f6e:	625a      	str	r2, [r3, #36]	; 0x24

    for(slave = 0u; slave < (uint16_t)MSS_SPI_MAX_NB_OF_SLAVES; ++slave)
    5f70:	f04f 0300 	mov.w	r3, #0
    5f74:	81fb      	strh	r3, [r7, #14]
    5f76:	e00d      	b.n	5f94 <MSS_SPI_init+0x6c>
    {
        this_spi->slaves_cfg[slave].ctrl_reg = NOT_CONFIGURED;
    5f78:	89fb      	ldrh	r3, [r7, #14]
    5f7a:	687a      	ldr	r2, [r7, #4]
    5f7c:	f103 0306 	add.w	r3, r3, #6
    5f80:	ea4f 03c3 	mov.w	r3, r3, lsl #3
    5f84:	4413      	add	r3, r2
    5f86:	f04f 32ff 	mov.w	r2, #4294967295
    5f8a:	605a      	str	r2, [r3, #4]

    memset(this_spi, 0, sizeof(mss_spi_instance_t));
    
    this_spi->cmd_done = 1u;

    for(slave = 0u; slave < (uint16_t)MSS_SPI_MAX_NB_OF_SLAVES; ++slave)
    5f8c:	89fb      	ldrh	r3, [r7, #14]
    5f8e:	f103 0301 	add.w	r3, r3, #1
    5f92:	81fb      	strh	r3, [r7, #14]
    5f94:	89fb      	ldrh	r3, [r7, #14]
    5f96:	2b07      	cmp	r3, #7
    5f98:	d9ee      	bls.n	5f78 <MSS_SPI_init+0x50>
    {
        this_spi->slaves_cfg[slave].ctrl_reg = NOT_CONFIGURED;
    }

    if(this_spi == &g_mss_spi0)
    5f9a:	687a      	ldr	r2, [r7, #4]
    5f9c:	f240 23bc 	movw	r3, #700	; 0x2bc
    5fa0:	f2c2 0300 	movt	r3, #8192	; 0x2000
    5fa4:	429a      	cmp	r2, r3
    5fa6:	d126      	bne.n	5ff6 <MSS_SPI_init+0xce>
    {
        this_spi->hw_reg = ((SPI_TypeDef *) SPI0_BASE);
    5fa8:	687a      	ldr	r2, [r7, #4]
    5faa:	f241 0300 	movw	r3, #4096	; 0x1000
    5fae:	f2c4 0300 	movt	r3, #16384	; 0x4000
    5fb2:	6013      	str	r3, [r2, #0]
        this_spi->irqn = SPI0_IRQn;
    5fb4:	687b      	ldr	r3, [r7, #4]
    5fb6:	f04f 0202 	mov.w	r2, #2
    5fba:	711a      	strb	r2, [r3, #4]

        /* reset SPI0 */
        SYSREG->SOFT_RST_CR |= SYSREG_SPI0_SOFTRESET_MASK;
    5fbc:	f248 0300 	movw	r3, #32768	; 0x8000
    5fc0:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5fc4:	f248 0200 	movw	r2, #32768	; 0x8000
    5fc8:	f2c4 0203 	movt	r2, #16387	; 0x4003
    5fcc:	6c92      	ldr	r2, [r2, #72]	; 0x48
    5fce:	f442 7200 	orr.w	r2, r2, #512	; 0x200
    5fd2:	649a      	str	r2, [r3, #72]	; 0x48
        /* Clear any previously pended SPI0 interrupt */
        NVIC_ClearPendingIRQ(SPI0_IRQn);
    5fd4:	f04f 0002 	mov.w	r0, #2
    5fd8:	f7ff ff88 	bl	5eec <NVIC_ClearPendingIRQ>
        /* Take SPI0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_SPI0_SOFTRESET_MASK;
    5fdc:	f248 0300 	movw	r3, #32768	; 0x8000
    5fe0:	f2c4 0303 	movt	r3, #16387	; 0x4003
    5fe4:	f248 0200 	movw	r2, #32768	; 0x8000
    5fe8:	f2c4 0203 	movt	r2, #16387	; 0x4003
    5fec:	6c92      	ldr	r2, [r2, #72]	; 0x48
    5fee:	f422 7200 	bic.w	r2, r2, #512	; 0x200
    5ff2:	649a      	str	r2, [r3, #72]	; 0x48
    5ff4:	e025      	b.n	6042 <MSS_SPI_init+0x11a>
    }
    else
    {
        this_spi->hw_reg = ((SPI_TypeDef *) SPI1_BASE);
    5ff6:	687a      	ldr	r2, [r7, #4]
    5ff8:	f241 0300 	movw	r3, #4096	; 0x1000
    5ffc:	f2c4 0301 	movt	r3, #16385	; 0x4001
    6000:	6013      	str	r3, [r2, #0]
        this_spi->irqn = SPI1_IRQn;
    6002:	687b      	ldr	r3, [r7, #4]
    6004:	f04f 0203 	mov.w	r2, #3
    6008:	711a      	strb	r2, [r3, #4]
        
        /* reset SPI1 */
        SYSREG->SOFT_RST_CR |= SYSREG_SPI1_SOFTRESET_MASK;
    600a:	f248 0300 	movw	r3, #32768	; 0x8000
    600e:	f2c4 0303 	movt	r3, #16387	; 0x4003
    6012:	f248 0200 	movw	r2, #32768	; 0x8000
    6016:	f2c4 0203 	movt	r2, #16387	; 0x4003
    601a:	6c92      	ldr	r2, [r2, #72]	; 0x48
    601c:	f442 6280 	orr.w	r2, r2, #1024	; 0x400
    6020:	649a      	str	r2, [r3, #72]	; 0x48
        /* Clear any previously pended SPI1 interrupt */
        NVIC_ClearPendingIRQ(SPI1_IRQn);
    6022:	f04f 0003 	mov.w	r0, #3
    6026:	f7ff ff61 	bl	5eec <NVIC_ClearPendingIRQ>
        /* Take SPI1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_SPI1_SOFTRESET_MASK;
    602a:	f248 0300 	movw	r3, #32768	; 0x8000
    602e:	f2c4 0303 	movt	r3, #16387	; 0x4003
    6032:	f248 0200 	movw	r2, #32768	; 0x8000
    6036:	f2c4 0203 	movt	r2, #16387	; 0x4003
    603a:	6c92      	ldr	r2, [r2, #72]	; 0x48
    603c:	f422 6280 	bic.w	r2, r2, #1024	; 0x400
    6040:	649a      	str	r2, [r3, #72]	; 0x48
    }
    
    /* De-assert reset bit. */
    this_spi->hw_reg->CONTROL &= ~CTRL_REG_RESET_MASK;
    6042:	687b      	ldr	r3, [r7, #4]
    6044:	681b      	ldr	r3, [r3, #0]
    6046:	687a      	ldr	r2, [r7, #4]
    6048:	6812      	ldr	r2, [r2, #0]
    604a:	6812      	ldr	r2, [r2, #0]
    604c:	f022 4200 	bic.w	r2, r2, #2147483648	; 0x80000000
    6050:	601a      	str	r2, [r3, #0]
}
    6052:	f107 0710 	add.w	r7, r7, #16
    6056:	46bd      	mov	sp, r7
    6058:	bd80      	pop	{r7, pc}
    605a:	bf00      	nop

0000605c <recover_from_rx_overflow>:
 */
static void recover_from_rx_overflow
(
    mss_spi_instance_t * this_spi
)
{
    605c:	b580      	push	{r7, lr}
    605e:	b08a      	sub	sp, #40	; 0x28
    6060:	af00      	add	r7, sp, #0
    6062:	6078      	str	r0, [r7, #4]
    uint32_t slave_select;
    
    /*
     * Read current SPI hardware block configuration.
     */
    control_reg = this_spi->hw_reg->CONTROL;
    6064:	687b      	ldr	r3, [r7, #4]
    6066:	681b      	ldr	r3, [r3, #0]
    6068:	681b      	ldr	r3, [r3, #0]
    606a:	60fb      	str	r3, [r7, #12]
    clk_gen = this_spi->hw_reg->CLK_GEN;
    606c:	687b      	ldr	r3, [r7, #4]
    606e:	681b      	ldr	r3, [r3, #0]
    6070:	699b      	ldr	r3, [r3, #24]
    6072:	613b      	str	r3, [r7, #16]
    frame_size = this_spi->hw_reg->TXRXDF_SIZE;
    6074:	687b      	ldr	r3, [r7, #4]
    6076:	681b      	ldr	r3, [r3, #0]
    6078:	685b      	ldr	r3, [r3, #4]
    607a:	617b      	str	r3, [r7, #20]
    control2 = this_spi->hw_reg->CONTROL2;
    607c:	687b      	ldr	r3, [r7, #4]
    607e:	681b      	ldr	r3, [r3, #0]
    6080:	6a9b      	ldr	r3, [r3, #40]	; 0x28
    6082:	61bb      	str	r3, [r7, #24]
    packet_size = this_spi->hw_reg->PKTSIZE;
    6084:	687b      	ldr	r3, [r7, #4]
    6086:	681b      	ldr	r3, [r3, #0]
    6088:	6b1b      	ldr	r3, [r3, #48]	; 0x30
    608a:	61fb      	str	r3, [r7, #28]
    cmd_size = this_spi->hw_reg->CMDSIZE;
    608c:	687b      	ldr	r3, [r7, #4]
    608e:	681b      	ldr	r3, [r3, #0]
    6090:	6b5b      	ldr	r3, [r3, #52]	; 0x34
    6092:	623b      	str	r3, [r7, #32]
    slave_select = this_spi->hw_reg->SLAVE_SELECT;
    6094:	687b      	ldr	r3, [r7, #4]
    6096:	681b      	ldr	r3, [r3, #0]
    6098:	69db      	ldr	r3, [r3, #28]
    609a:	627b      	str	r3, [r7, #36]	; 0x24
     
    /*
     * Reset the SPI hardware block.
     */
    if(this_spi == &g_mss_spi0)
    609c:	687a      	ldr	r2, [r7, #4]
    609e:	f240 23bc 	movw	r3, #700	; 0x2bc
    60a2:	f2c2 0300 	movt	r3, #8192	; 0x2000
    60a6:	429a      	cmp	r2, r3
    60a8:	d12e      	bne.n	6108 <recover_from_rx_overflow+0xac>
    {
        this_spi->hw_reg = ((SPI_TypeDef *) SPI0_BASE);
    60aa:	687a      	ldr	r2, [r7, #4]
    60ac:	f241 0300 	movw	r3, #4096	; 0x1000
    60b0:	f2c4 0300 	movt	r3, #16384	; 0x4000
    60b4:	6013      	str	r3, [r2, #0]
        this_spi->irqn = SPI0_IRQn;
    60b6:	687b      	ldr	r3, [r7, #4]
    60b8:	f04f 0202 	mov.w	r2, #2
    60bc:	711a      	strb	r2, [r3, #4]

        /* reset SPI0 */
        SYSREG->SOFT_RST_CR |= SYSREG_SPI0_SOFTRESET_MASK;
    60be:	f248 0300 	movw	r3, #32768	; 0x8000
    60c2:	f2c4 0303 	movt	r3, #16387	; 0x4003
    60c6:	f248 0200 	movw	r2, #32768	; 0x8000
    60ca:	f2c4 0203 	movt	r2, #16387	; 0x4003
    60ce:	6c92      	ldr	r2, [r2, #72]	; 0x48
    60d0:	f442 7200 	orr.w	r2, r2, #512	; 0x200
    60d4:	649a      	str	r2, [r3, #72]	; 0x48
        /* Clear any previously pended SPI0 interrupt */
        NVIC_ClearPendingIRQ(SPI0_IRQn);
    60d6:	f04f 0002 	mov.w	r0, #2
    60da:	f7ff ff07 	bl	5eec <NVIC_ClearPendingIRQ>
        /* Take SPI0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_SPI0_SOFTRESET_MASK;
    60de:	f248 0300 	movw	r3, #32768	; 0x8000
    60e2:	f2c4 0303 	movt	r3, #16387	; 0x4003
    60e6:	f248 0200 	movw	r2, #32768	; 0x8000
    60ea:	f2c4 0203 	movt	r2, #16387	; 0x4003
    60ee:	6c92      	ldr	r2, [r2, #72]	; 0x48
    60f0:	f422 7200 	bic.w	r2, r2, #512	; 0x200
    60f4:	649a      	str	r2, [r3, #72]	; 0x48

        this_spi->hw_reg->CONTROL &= ~CTRL_REG_RESET_MASK;
    60f6:	687b      	ldr	r3, [r7, #4]
    60f8:	681b      	ldr	r3, [r3, #0]
    60fa:	687a      	ldr	r2, [r7, #4]
    60fc:	6812      	ldr	r2, [r2, #0]
    60fe:	6812      	ldr	r2, [r2, #0]
    6100:	f022 4200 	bic.w	r2, r2, #2147483648	; 0x80000000
    6104:	601a      	str	r2, [r3, #0]
    6106:	e02d      	b.n	6164 <recover_from_rx_overflow+0x108>
    }
    else
    {
        this_spi->hw_reg = ((SPI_TypeDef *) SPI1_BASE);
    6108:	687a      	ldr	r2, [r7, #4]
    610a:	f241 0300 	movw	r3, #4096	; 0x1000
    610e:	f2c4 0301 	movt	r3, #16385	; 0x4001
    6112:	6013      	str	r3, [r2, #0]
        this_spi->irqn = SPI1_IRQn;
    6114:	687b      	ldr	r3, [r7, #4]
    6116:	f04f 0203 	mov.w	r2, #3
    611a:	711a      	strb	r2, [r3, #4]
        
        /* reset SPI1 */
        SYSREG->SOFT_RST_CR |= SYSREG_SPI1_SOFTRESET_MASK;
    611c:	f248 0300 	movw	r3, #32768	; 0x8000
    6120:	f2c4 0303 	movt	r3, #16387	; 0x4003
    6124:	f248 0200 	movw	r2, #32768	; 0x8000
    6128:	f2c4 0203 	movt	r2, #16387	; 0x4003
    612c:	6c92      	ldr	r2, [r2, #72]	; 0x48
    612e:	f442 6280 	orr.w	r2, r2, #1024	; 0x400
    6132:	649a      	str	r2, [r3, #72]	; 0x48
        /* Clear any previously pended SPI1 interrupt */
        NVIC_ClearPendingIRQ(SPI1_IRQn);
    6134:	f04f 0003 	mov.w	r0, #3
    6138:	f7ff fed8 	bl	5eec <NVIC_ClearPendingIRQ>
        /* Take SPI1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_SPI1_SOFTRESET_MASK;
    613c:	f248 0300 	movw	r3, #32768	; 0x8000
    6140:	f2c4 0303 	movt	r3, #16387	; 0x4003
    6144:	f248 0200 	movw	r2, #32768	; 0x8000
    6148:	f2c4 0203 	movt	r2, #16387	; 0x4003
    614c:	6c92      	ldr	r2, [r2, #72]	; 0x48
    614e:	f422 6280 	bic.w	r2, r2, #1024	; 0x400
    6152:	649a      	str	r2, [r3, #72]	; 0x48
        
        this_spi->hw_reg->CONTROL &= ~CTRL_REG_RESET_MASK;
    6154:	687b      	ldr	r3, [r7, #4]
    6156:	681b      	ldr	r3, [r3, #0]
    6158:	687a      	ldr	r2, [r7, #4]
    615a:	6812      	ldr	r2, [r2, #0]
    615c:	6812      	ldr	r2, [r2, #0]
    615e:	f022 4200 	bic.w	r2, r2, #2147483648	; 0x80000000
    6162:	601a      	str	r2, [r3, #0]
    }
    
    /*
     * Restore SPI hardware block configuration.
     */
    control_reg &= ~(uint32_t)CTRL_ENABLE_MASK;
    6164:	68fb      	ldr	r3, [r7, #12]
    6166:	f023 0301 	bic.w	r3, r3, #1
    616a:	60fb      	str	r3, [r7, #12]
    this_spi->hw_reg->CONTROL = control_reg;
    616c:	687b      	ldr	r3, [r7, #4]
    616e:	681b      	ldr	r3, [r3, #0]
    6170:	68fa      	ldr	r2, [r7, #12]
    6172:	601a      	str	r2, [r3, #0]
    this_spi->hw_reg->CLK_GEN = clk_gen;
    6174:	687b      	ldr	r3, [r7, #4]
    6176:	681b      	ldr	r3, [r3, #0]
    6178:	693a      	ldr	r2, [r7, #16]
    617a:	619a      	str	r2, [r3, #24]
    this_spi->hw_reg->TXRXDF_SIZE = frame_size;
    617c:	687b      	ldr	r3, [r7, #4]
    617e:	681b      	ldr	r3, [r3, #0]
    6180:	697a      	ldr	r2, [r7, #20]
    6182:	605a      	str	r2, [r3, #4]
    this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK;
    6184:	687b      	ldr	r3, [r7, #4]
    6186:	681b      	ldr	r3, [r3, #0]
    6188:	687a      	ldr	r2, [r7, #4]
    618a:	6812      	ldr	r2, [r2, #0]
    618c:	6812      	ldr	r2, [r2, #0]
    618e:	f042 0201 	orr.w	r2, r2, #1
    6192:	601a      	str	r2, [r3, #0]
    this_spi->hw_reg->CONTROL2 = control2;
    6194:	687b      	ldr	r3, [r7, #4]
    6196:	681b      	ldr	r3, [r3, #0]
    6198:	69ba      	ldr	r2, [r7, #24]
    619a:	629a      	str	r2, [r3, #40]	; 0x28
    this_spi->hw_reg->PKTSIZE = packet_size;
    619c:	687b      	ldr	r3, [r7, #4]
    619e:	681b      	ldr	r3, [r3, #0]
    61a0:	69fa      	ldr	r2, [r7, #28]
    61a2:	631a      	str	r2, [r3, #48]	; 0x30
    this_spi->hw_reg->CMDSIZE = cmd_size;
    61a4:	687b      	ldr	r3, [r7, #4]
    61a6:	681b      	ldr	r3, [r3, #0]
    61a8:	6a3a      	ldr	r2, [r7, #32]
    61aa:	635a      	str	r2, [r3, #52]	; 0x34
    this_spi->hw_reg->SLAVE_SELECT = slave_select;
    61ac:	687b      	ldr	r3, [r7, #4]
    61ae:	681b      	ldr	r3, [r3, #0]
    61b0:	6a7a      	ldr	r2, [r7, #36]	; 0x24
    61b2:	61da      	str	r2, [r3, #28]
}
    61b4:	f107 0728 	add.w	r7, r7, #40	; 0x28
    61b8:	46bd      	mov	sp, r7
    61ba:	bd80      	pop	{r7, pc}

000061bc <MSS_SPI_configure_slave_mode>:
(
    mss_spi_instance_t * this_spi,
    mss_spi_protocol_mode_t protocol_mode,
    uint8_t frame_bit_length
)
{
    61bc:	b580      	push	{r7, lr}
    61be:	b084      	sub	sp, #16
    61c0:	af00      	add	r7, sp, #0
    61c2:	60f8      	str	r0, [r7, #12]
    61c4:	60b9      	str	r1, [r7, #8]
    61c6:	4613      	mov	r3, r2
    61c8:	71fb      	strb	r3, [r7, #7]
    ASSERT((this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1));
    61ca:	68fa      	ldr	r2, [r7, #12]
    61cc:	f240 23bc 	movw	r3, #700	; 0x2bc
    61d0:	f2c2 0300 	movt	r3, #8192	; 0x2000
    61d4:	429a      	cmp	r2, r3
    61d6:	d007      	beq.n	61e8 <MSS_SPI_configure_slave_mode+0x2c>
    61d8:	68fa      	ldr	r2, [r7, #12]
    61da:	f240 2338 	movw	r3, #568	; 0x238
    61de:	f2c2 0300 	movt	r3, #8192	; 0x2000
    61e2:	429a      	cmp	r2, r3
    61e4:	d000      	beq.n	61e8 <MSS_SPI_configure_slave_mode+0x2c>
    61e6:	be00      	bkpt	0x0000
    ASSERT(frame_bit_length <= MAX_FRAME_LENGTH);
    61e8:	79fb      	ldrb	r3, [r7, #7]
    61ea:	2b20      	cmp	r3, #32
    61ec:	d900      	bls.n	61f0 <MSS_SPI_configure_slave_mode+0x34>
    61ee:	be00      	bkpt	0x0000
    
    /* Shut down interrupts from the MSS SPI while we do this */
    NVIC_DisableIRQ( this_spi->irqn );
    61f0:	68fb      	ldr	r3, [r7, #12]
    61f2:	791b      	ldrb	r3, [r3, #4]
    61f4:	b25b      	sxtb	r3, r3
    61f6:	4618      	mov	r0, r3
    61f8:	f7ff fe5a 	bl	5eb0 <NVIC_DisableIRQ>

    /* Don't yet know what slave transfer mode will be used */
    this_spi->slave_xfer_mode = MSS_SPI_SLAVE_XFER_NONE;
    61fc:	68fb      	ldr	r3, [r7, #12]
    61fe:	f04f 0200 	mov.w	r2, #0
    6202:	f883 2080 	strb.w	r2, [r3, #128]	; 0x80

    /* Set the mode. */
    this_spi->hw_reg->CONTROL &= ~(uint32_t)CTRL_MASTER_MASK;
    6206:	68fb      	ldr	r3, [r7, #12]
    6208:	681b      	ldr	r3, [r3, #0]
    620a:	68fa      	ldr	r2, [r7, #12]
    620c:	6812      	ldr	r2, [r2, #0]
    620e:	6812      	ldr	r2, [r2, #0]
    6210:	f022 0202 	bic.w	r2, r2, #2
    6214:	601a      	str	r2, [r3, #0]

    /* Set the protocol mode */
    this_spi->hw_reg->CONTROL &= ~(uint32_t)CTRL_ENABLE_MASK;
    6216:	68fb      	ldr	r3, [r7, #12]
    6218:	681b      	ldr	r3, [r3, #0]
    621a:	68fa      	ldr	r2, [r7, #12]
    621c:	6812      	ldr	r2, [r2, #0]
    621e:	6812      	ldr	r2, [r2, #0]
    6220:	f022 0201 	bic.w	r2, r2, #1
    6224:	601a      	str	r2, [r3, #0]
    this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~PROTOCOL_MODE_MASK) |
    6226:	68fb      	ldr	r3, [r7, #12]
    6228:	681a      	ldr	r2, [r3, #0]
    622a:	68fb      	ldr	r3, [r7, #12]
    622c:	681b      	ldr	r3, [r3, #0]
    622e:	681b      	ldr	r3, [r3, #0]
    6230:	f023 7340 	bic.w	r3, r3, #50331648	; 0x3000000
    6234:	f023 030c 	bic.w	r3, r3, #12
                                (uint32_t)protocol_mode | BIGFIFO_MASK;
    6238:	68b9      	ldr	r1, [r7, #8]
    623a:	ea43 0301 	orr.w	r3, r3, r1
    /* Set the mode. */
    this_spi->hw_reg->CONTROL &= ~(uint32_t)CTRL_MASTER_MASK;

    /* Set the protocol mode */
    this_spi->hw_reg->CONTROL &= ~(uint32_t)CTRL_ENABLE_MASK;
    this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~PROTOCOL_MODE_MASK) |
    623e:	f043 5300 	orr.w	r3, r3, #536870912	; 0x20000000
    6242:	6013      	str	r3, [r2, #0]
                                (uint32_t)protocol_mode | BIGFIFO_MASK;
    
    /* Set number of data frames to 1 by default */
    this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK) |
    6244:	68fb      	ldr	r3, [r7, #12]
    6246:	681a      	ldr	r2, [r3, #0]
    6248:	68fb      	ldr	r3, [r7, #12]
    624a:	681b      	ldr	r3, [r3, #0]
    624c:	6819      	ldr	r1, [r3, #0]
    624e:	f240 03ff 	movw	r3, #255	; 0xff
    6252:	f6cf 7300 	movt	r3, #65280	; 0xff00
    6256:	ea01 0303 	and.w	r3, r1, r3
    625a:	f443 7380 	orr.w	r3, r3, #256	; 0x100
    625e:	6013      	str	r3, [r2, #0]
                                ((uint32_t)1 << TXRXDFCOUNT_SHIFT);
    this_spi->hw_reg->TXRXDF_SIZE = frame_bit_length;
    6260:	68fb      	ldr	r3, [r7, #12]
    6262:	681b      	ldr	r3, [r3, #0]
    6264:	79fa      	ldrb	r2, [r7, #7]
    6266:	605a      	str	r2, [r3, #4]
    this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK;
    6268:	68fb      	ldr	r3, [r7, #12]
    626a:	681b      	ldr	r3, [r3, #0]
    626c:	68fa      	ldr	r2, [r7, #12]
    626e:	6812      	ldr	r2, [r2, #0]
    6270:	6812      	ldr	r2, [r2, #0]
    6272:	f042 0201 	orr.w	r2, r2, #1
    6276:	601a      	str	r2, [r3, #0]
    /* Reenable interrupts */
    NVIC_EnableIRQ( this_spi->irqn );
    6278:	68fb      	ldr	r3, [r7, #12]
    627a:	791b      	ldrb	r3, [r3, #4]
    627c:	b25b      	sxtb	r3, r3
    627e:	4618      	mov	r0, r3
    6280:	f7ff fdfa 	bl	5e78 <NVIC_EnableIRQ>
}
    6284:	f107 0710 	add.w	r7, r7, #16
    6288:	46bd      	mov	sp, r7
    628a:	bd80      	pop	{r7, pc}

0000628c <MSS_SPI_configure_master_mode>:
    mss_spi_slave_t         slave,
    mss_spi_protocol_mode_t protocol_mode,
    uint32_t                clk_div,
    uint8_t                 frame_bit_length
)
{
    628c:	b580      	push	{r7, lr}
    628e:	b086      	sub	sp, #24
    6290:	af00      	add	r7, sp, #0
    6292:	60f8      	str	r0, [r7, #12]
    6294:	607a      	str	r2, [r7, #4]
    6296:	603b      	str	r3, [r7, #0]
    6298:	460b      	mov	r3, r1
    629a:	72fb      	strb	r3, [r7, #11]
    ASSERT((this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1));
    629c:	68fa      	ldr	r2, [r7, #12]
    629e:	f240 23bc 	movw	r3, #700	; 0x2bc
    62a2:	f2c2 0300 	movt	r3, #8192	; 0x2000
    62a6:	429a      	cmp	r2, r3
    62a8:	d007      	beq.n	62ba <MSS_SPI_configure_master_mode+0x2e>
    62aa:	68fa      	ldr	r2, [r7, #12]
    62ac:	f240 2338 	movw	r3, #568	; 0x238
    62b0:	f2c2 0300 	movt	r3, #8192	; 0x2000
    62b4:	429a      	cmp	r2, r3
    62b6:	d000      	beq.n	62ba <MSS_SPI_configure_master_mode+0x2e>
    62b8:	be00      	bkpt	0x0000
    ASSERT(slave < MSS_SPI_MAX_NB_OF_SLAVES);
    62ba:	7afb      	ldrb	r3, [r7, #11]
    62bc:	2b07      	cmp	r3, #7
    62be:	d900      	bls.n	62c2 <MSS_SPI_configure_master_mode+0x36>
    62c0:	be00      	bkpt	0x0000
    ASSERT(frame_bit_length <= MAX_FRAME_LENGTH);
    62c2:	f897 3020 	ldrb.w	r3, [r7, #32]
    62c6:	2b20      	cmp	r3, #32
    62c8:	d900      	bls.n	62cc <MSS_SPI_configure_master_mode+0x40>
    62ca:	be00      	bkpt	0x0000
     /* Check that the requested clock divider is within range and an even number. */
    ASSERT(clk_div >= 2u);
    62cc:	683b      	ldr	r3, [r7, #0]
    62ce:	2b01      	cmp	r3, #1
    62d0:	d800      	bhi.n	62d4 <MSS_SPI_configure_master_mode+0x48>
    62d2:	be00      	bkpt	0x0000
    ASSERT(clk_div <= 512u);
    62d4:	683b      	ldr	r3, [r7, #0]
    62d6:	f5b3 7f00 	cmp.w	r3, #512	; 0x200
    62da:	d900      	bls.n	62de <MSS_SPI_configure_master_mode+0x52>
    62dc:	be00      	bkpt	0x0000
    ASSERT(0u == (clk_div & 0x00000001));
    62de:	683b      	ldr	r3, [r7, #0]
    62e0:	f003 0301 	and.w	r3, r3, #1
    62e4:	2b00      	cmp	r3, #0
    62e6:	d000      	beq.n	62ea <MSS_SPI_configure_master_mode+0x5e>
    62e8:	be00      	bkpt	0x0000
   
    /* Shut down interrupts from the MSS SPI while we do this */
    NVIC_DisableIRQ( this_spi->irqn );
    62ea:	68fb      	ldr	r3, [r7, #12]
    62ec:	791b      	ldrb	r3, [r3, #4]
    62ee:	b25b      	sxtb	r3, r3
    62f0:	4618      	mov	r0, r3
    62f2:	f7ff fddd 	bl	5eb0 <NVIC_DisableIRQ>

    /* Reset slave transfer mode to unknown to wipe slate clean */
    this_spi->slave_xfer_mode = MSS_SPI_SLAVE_XFER_NONE;
    62f6:	68fb      	ldr	r3, [r7, #12]
    62f8:	f04f 0200 	mov.w	r2, #0
    62fc:	f883 2080 	strb.w	r2, [r3, #128]	; 0x80

    /* Set the mode. */
    this_spi->hw_reg->CONTROL &= ~(uint32_t)CTRL_ENABLE_MASK;
    6300:	68fb      	ldr	r3, [r7, #12]
    6302:	681b      	ldr	r3, [r3, #0]
    6304:	68fa      	ldr	r2, [r7, #12]
    6306:	6812      	ldr	r2, [r2, #0]
    6308:	6812      	ldr	r2, [r2, #0]
    630a:	f022 0201 	bic.w	r2, r2, #1
    630e:	601a      	str	r2, [r3, #0]
    this_spi->hw_reg->CONTROL |= CTRL_MASTER_MASK;
    6310:	68fb      	ldr	r3, [r7, #12]
    6312:	681b      	ldr	r3, [r3, #0]
    6314:	68fa      	ldr	r2, [r7, #12]
    6316:	6812      	ldr	r2, [r2, #0]
    6318:	6812      	ldr	r2, [r2, #0]
    631a:	f042 0202 	orr.w	r2, r2, #2
    631e:	601a      	str	r2, [r3, #0]
    this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK;
    6320:	68fb      	ldr	r3, [r7, #12]
    6322:	681b      	ldr	r3, [r3, #0]
    6324:	68fa      	ldr	r2, [r7, #12]
    6326:	6812      	ldr	r2, [r2, #0]
    6328:	6812      	ldr	r2, [r2, #0]
    632a:	f042 0201 	orr.w	r2, r2, #1
    632e:	601a      	str	r2, [r3, #0]
    /*
     * Keep track of the required register configuration for this slave. These
     * values will be used by the MSS_SPI_set_slave_select() function to configure
     * the master to match the slave being selected.
     */
    if(slave < MSS_SPI_MAX_NB_OF_SLAVES)     
    6330:	7afb      	ldrb	r3, [r7, #11]
    6332:	2b07      	cmp	r3, #7
    6334:	d847      	bhi.n	63c6 <MSS_SPI_configure_master_mode+0x13a>
        * Setting the SPS bit ensures the slave select remains asserted even
        * if we don't keep the TX FIFO filled in block mode. We only do it for
        * Motorola modes and if you need the slave selected deselected between
        * frames in modes 0 or 2 then remove SPS_MASK from below.
        */
        if((MSS_SPI_MODE0 == protocol_mode) || (MSS_SPI_MODE1 == protocol_mode) ||
    6336:	687b      	ldr	r3, [r7, #4]
    6338:	2b00      	cmp	r3, #0
    633a:	d00b      	beq.n	6354 <MSS_SPI_configure_master_mode+0xc8>
    633c:	687b      	ldr	r3, [r7, #4]
    633e:	f1b3 7f00 	cmp.w	r3, #33554432	; 0x2000000
    6342:	d007      	beq.n	6354 <MSS_SPI_configure_master_mode+0xc8>
    6344:	687b      	ldr	r3, [r7, #4]
    6346:	f1b3 7f80 	cmp.w	r3, #16777216	; 0x1000000
    634a:	d003      	beq.n	6354 <MSS_SPI_configure_master_mode+0xc8>
    634c:	687b      	ldr	r3, [r7, #4]
    634e:	f1b3 7f40 	cmp.w	r3, #50331648	; 0x3000000
    6352:	d10f      	bne.n	6374 <MSS_SPI_configure_master_mode+0xe8>
           (MSS_SPI_MODE2 == protocol_mode) || (MSS_SPI_MODE3 == protocol_mode))
        {
            this_spi->slaves_cfg[slave].ctrl_reg = MASTER_MODE_MASK | SPS_MASK |
    6354:	7afa      	ldrb	r2, [r7, #11]
    6356:	6879      	ldr	r1, [r7, #4]
    6358:	f240 1302 	movw	r3, #258	; 0x102
    635c:	f2c3 4300 	movt	r3, #13312	; 0x3400
    6360:	ea41 0303 	orr.w	r3, r1, r3
    6364:	68f9      	ldr	r1, [r7, #12]
    6366:	f102 0206 	add.w	r2, r2, #6
    636a:	ea4f 02c2 	mov.w	r2, r2, lsl #3
    636e:	440a      	add	r2, r1
    6370:	6053      	str	r3, [r2, #4]
        * Setting the SPS bit ensures the slave select remains asserted even
        * if we don't keep the TX FIFO filled in block mode. We only do it for
        * Motorola modes and if you need the slave selected deselected between
        * frames in modes 0 or 2 then remove SPS_MASK from below.
        */
        if((MSS_SPI_MODE0 == protocol_mode) || (MSS_SPI_MODE1 == protocol_mode) ||
    6372:	e00e      	b.n	6392 <MSS_SPI_configure_master_mode+0x106>
                                                   (uint32_t)protocol_mode | 
                                                   ((uint32_t)1 << TXRXDFCOUNT_SHIFT);
        }
        else
        {
            this_spi->slaves_cfg[slave].ctrl_reg = MASTER_MODE_MASK |
    6374:	7afa      	ldrb	r2, [r7, #11]
    6376:	6879      	ldr	r1, [r7, #4]
    6378:	f240 1302 	movw	r3, #258	; 0x102
    637c:	f2c3 0300 	movt	r3, #12288	; 0x3000
    6380:	ea41 0303 	orr.w	r3, r1, r3
    6384:	68f9      	ldr	r1, [r7, #12]
    6386:	f102 0206 	add.w	r2, r2, #6
    638a:	ea4f 02c2 	mov.w	r2, r2, lsl #3
    638e:	440a      	add	r2, r1
    6390:	6053      	str	r3, [r2, #4]
                                                   BIGFIFO_MASK | CTRL_CLKMODE_MASK |
                                                   (uint32_t)protocol_mode | 
                                                   ((uint32_t)1 << TXRXDFCOUNT_SHIFT);
        }
        this_spi->slaves_cfg[slave].txrxdf_size_reg = frame_bit_length;
    6392:	7afb      	ldrb	r3, [r7, #11]
    6394:	68fa      	ldr	r2, [r7, #12]
    6396:	f103 0306 	add.w	r3, r3, #6
    639a:	ea4f 03c3 	mov.w	r3, r3, lsl #3
    639e:	4413      	add	r3, r2
    63a0:	f897 2020 	ldrb.w	r2, [r7, #32]
    63a4:	721a      	strb	r2, [r3, #8]

        clk_gen = (clk_div / 2u) - 1u;
    63a6:	683b      	ldr	r3, [r7, #0]
    63a8:	ea4f 0353 	mov.w	r3, r3, lsr #1
    63ac:	f103 33ff 	add.w	r3, r3, #4294967295
    63b0:	617b      	str	r3, [r7, #20]
        this_spi->slaves_cfg[slave].clk_gen = (uint8_t)clk_gen;
    63b2:	7afb      	ldrb	r3, [r7, #11]
    63b4:	697a      	ldr	r2, [r7, #20]
    63b6:	b2d2      	uxtb	r2, r2
    63b8:	68f9      	ldr	r1, [r7, #12]
    63ba:	f103 0306 	add.w	r3, r3, #6
    63be:	ea4f 03c3 	mov.w	r3, r3, lsl #3
    63c2:	440b      	add	r3, r1
    63c4:	725a      	strb	r2, [r3, #9]
    }
    /* Reenable interrupts */
    NVIC_EnableIRQ( this_spi->irqn );
    63c6:	68fb      	ldr	r3, [r7, #12]
    63c8:	791b      	ldrb	r3, [r3, #4]
    63ca:	b25b      	sxtb	r3, r3
    63cc:	4618      	mov	r0, r3
    63ce:	f7ff fd53 	bl	5e78 <NVIC_EnableIRQ>
}
    63d2:	f107 0718 	add.w	r7, r7, #24
    63d6:	46bd      	mov	sp, r7
    63d8:	bd80      	pop	{r7, pc}
    63da:	bf00      	nop

000063dc <MSS_SPI_set_slave_select>:
void MSS_SPI_set_slave_select
(
    mss_spi_instance_t * this_spi,
    mss_spi_slave_t slave
)
{
    63dc:	b580      	push	{r7, lr}
    63de:	b084      	sub	sp, #16
    63e0:	af00      	add	r7, sp, #0
    63e2:	6078      	str	r0, [r7, #4]
    63e4:	460b      	mov	r3, r1
    63e6:	70fb      	strb	r3, [r7, #3]
    uint32_t rx_overflow;
    
    ASSERT((this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1));
    63e8:	687a      	ldr	r2, [r7, #4]
    63ea:	f240 23bc 	movw	r3, #700	; 0x2bc
    63ee:	f2c2 0300 	movt	r3, #8192	; 0x2000
    63f2:	429a      	cmp	r2, r3
    63f4:	d007      	beq.n	6406 <MSS_SPI_set_slave_select+0x2a>
    63f6:	687a      	ldr	r2, [r7, #4]
    63f8:	f240 2338 	movw	r3, #568	; 0x238
    63fc:	f2c2 0300 	movt	r3, #8192	; 0x2000
    6400:	429a      	cmp	r2, r3
    6402:	d000      	beq.n	6406 <MSS_SPI_set_slave_select+0x2a>
    6404:	be00      	bkpt	0x0000
    
    /* This function is only intended to be used with an SPI master. */
    ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK) == CTRL_MASTER_MASK);
    6406:	687b      	ldr	r3, [r7, #4]
    6408:	681b      	ldr	r3, [r3, #0]
    640a:	681b      	ldr	r3, [r3, #0]
    640c:	f003 0302 	and.w	r3, r3, #2
    6410:	2b00      	cmp	r3, #0
    6412:	d100      	bne.n	6416 <MSS_SPI_set_slave_select+0x3a>
    6414:	be00      	bkpt	0x0000
    
    ASSERT(this_spi->slaves_cfg[slave].ctrl_reg != NOT_CONFIGURED);
    6416:	78fb      	ldrb	r3, [r7, #3]
    6418:	687a      	ldr	r2, [r7, #4]
    641a:	f103 0306 	add.w	r3, r3, #6
    641e:	ea4f 03c3 	mov.w	r3, r3, lsl #3
    6422:	4413      	add	r3, r2
    6424:	685b      	ldr	r3, [r3, #4]
    6426:	f1b3 3fff 	cmp.w	r3, #4294967295
    642a:	d100      	bne.n	642e <MSS_SPI_set_slave_select+0x52>
    642c:	be00      	bkpt	0x0000

    /* Shut down interrupts from the MSS SPI while we do this */
    NVIC_DisableIRQ( this_spi->irqn );
    642e:	687b      	ldr	r3, [r7, #4]
    6430:	791b      	ldrb	r3, [r3, #4]
    6432:	b25b      	sxtb	r3, r3
    6434:	4618      	mov	r0, r3
    6436:	f7ff fd3b 	bl	5eb0 <NVIC_DisableIRQ>

    /* Recover from receive overflow. */
    rx_overflow = this_spi->hw_reg->STATUS & RX_OVERFLOW_MASK;
    643a:	687b      	ldr	r3, [r7, #4]
    643c:	681b      	ldr	r3, [r3, #0]
    643e:	689b      	ldr	r3, [r3, #8]
    6440:	f003 0304 	and.w	r3, r3, #4
    6444:	60fb      	str	r3, [r7, #12]
    if(rx_overflow)
    6446:	68fb      	ldr	r3, [r7, #12]
    6448:	2b00      	cmp	r3, #0
    644a:	d002      	beq.n	6452 <MSS_SPI_set_slave_select+0x76>
    {
         recover_from_rx_overflow(this_spi);
    644c:	6878      	ldr	r0, [r7, #4]
    644e:	f7ff fe05 	bl	605c <recover_from_rx_overflow>
    }
    
    /* Set the clock rate. */
    this_spi->hw_reg->CONTROL &= ~(uint32_t)CTRL_ENABLE_MASK;
    6452:	687b      	ldr	r3, [r7, #4]
    6454:	681b      	ldr	r3, [r3, #0]
    6456:	687a      	ldr	r2, [r7, #4]
    6458:	6812      	ldr	r2, [r2, #0]
    645a:	6812      	ldr	r2, [r2, #0]
    645c:	f022 0201 	bic.w	r2, r2, #1
    6460:	601a      	str	r2, [r3, #0]
    this_spi->hw_reg->CONTROL = this_spi->slaves_cfg[slave].ctrl_reg;
    6462:	687b      	ldr	r3, [r7, #4]
    6464:	681a      	ldr	r2, [r3, #0]
    6466:	78fb      	ldrb	r3, [r7, #3]
    6468:	6879      	ldr	r1, [r7, #4]
    646a:	f103 0306 	add.w	r3, r3, #6
    646e:	ea4f 03c3 	mov.w	r3, r3, lsl #3
    6472:	440b      	add	r3, r1
    6474:	685b      	ldr	r3, [r3, #4]
    6476:	6013      	str	r3, [r2, #0]
    this_spi->hw_reg->CLK_GEN = this_spi->slaves_cfg[slave].clk_gen;
    6478:	687b      	ldr	r3, [r7, #4]
    647a:	681a      	ldr	r2, [r3, #0]
    647c:	78fb      	ldrb	r3, [r7, #3]
    647e:	6879      	ldr	r1, [r7, #4]
    6480:	f103 0306 	add.w	r3, r3, #6
    6484:	ea4f 03c3 	mov.w	r3, r3, lsl #3
    6488:	440b      	add	r3, r1
    648a:	7a5b      	ldrb	r3, [r3, #9]
    648c:	6193      	str	r3, [r2, #24]
    this_spi->hw_reg->TXRXDF_SIZE = this_spi->slaves_cfg[slave].txrxdf_size_reg;
    648e:	687b      	ldr	r3, [r7, #4]
    6490:	681a      	ldr	r2, [r3, #0]
    6492:	78fb      	ldrb	r3, [r7, #3]
    6494:	6879      	ldr	r1, [r7, #4]
    6496:	f103 0306 	add.w	r3, r3, #6
    649a:	ea4f 03c3 	mov.w	r3, r3, lsl #3
    649e:	440b      	add	r3, r1
    64a0:	7a1b      	ldrb	r3, [r3, #8]
    64a2:	6053      	str	r3, [r2, #4]
    this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK;
    64a4:	687b      	ldr	r3, [r7, #4]
    64a6:	681b      	ldr	r3, [r3, #0]
    64a8:	687a      	ldr	r2, [r7, #4]
    64aa:	6812      	ldr	r2, [r2, #0]
    64ac:	6812      	ldr	r2, [r2, #0]
    64ae:	f042 0201 	orr.w	r2, r2, #1
    64b2:	601a      	str	r2, [r3, #0]
    
    /* Set slave select */
    this_spi->hw_reg->SLAVE_SELECT |= ((uint32_t)1 << (uint32_t)slave);
    64b4:	687b      	ldr	r3, [r7, #4]
    64b6:	681b      	ldr	r3, [r3, #0]
    64b8:	687a      	ldr	r2, [r7, #4]
    64ba:	6812      	ldr	r2, [r2, #0]
    64bc:	69d1      	ldr	r1, [r2, #28]
    64be:	78fa      	ldrb	r2, [r7, #3]
    64c0:	f04f 0001 	mov.w	r0, #1
    64c4:	fa00 f202 	lsl.w	r2, r0, r2
    64c8:	ea41 0202 	orr.w	r2, r1, r2
    64cc:	61da      	str	r2, [r3, #28]
    /* Reenable interrupts */
    NVIC_EnableIRQ( this_spi->irqn );
    64ce:	687b      	ldr	r3, [r7, #4]
    64d0:	791b      	ldrb	r3, [r3, #4]
    64d2:	b25b      	sxtb	r3, r3
    64d4:	4618      	mov	r0, r3
    64d6:	f7ff fccf 	bl	5e78 <NVIC_EnableIRQ>
}
    64da:	f107 0710 	add.w	r7, r7, #16
    64de:	46bd      	mov	sp, r7
    64e0:	bd80      	pop	{r7, pc}
    64e2:	bf00      	nop

000064e4 <MSS_SPI_clear_slave_select>:
void MSS_SPI_clear_slave_select
(
    mss_spi_instance_t * this_spi,
    mss_spi_slave_t slave
)
{
    64e4:	b580      	push	{r7, lr}
    64e6:	b084      	sub	sp, #16
    64e8:	af00      	add	r7, sp, #0
    64ea:	6078      	str	r0, [r7, #4]
    64ec:	460b      	mov	r3, r1
    64ee:	70fb      	strb	r3, [r7, #3]
    uint32_t rx_overflow;
    
    ASSERT((this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1));
    64f0:	687a      	ldr	r2, [r7, #4]
    64f2:	f240 23bc 	movw	r3, #700	; 0x2bc
    64f6:	f2c2 0300 	movt	r3, #8192	; 0x2000
    64fa:	429a      	cmp	r2, r3
    64fc:	d007      	beq.n	650e <MSS_SPI_clear_slave_select+0x2a>
    64fe:	687a      	ldr	r2, [r7, #4]
    6500:	f240 2338 	movw	r3, #568	; 0x238
    6504:	f2c2 0300 	movt	r3, #8192	; 0x2000
    6508:	429a      	cmp	r2, r3
    650a:	d000      	beq.n	650e <MSS_SPI_clear_slave_select+0x2a>
    650c:	be00      	bkpt	0x0000
    
    /* This function is only intended to be used with an SPI master. */
    ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK) == CTRL_MASTER_MASK);
    650e:	687b      	ldr	r3, [r7, #4]
    6510:	681b      	ldr	r3, [r3, #0]
    6512:	681b      	ldr	r3, [r3, #0]
    6514:	f003 0302 	and.w	r3, r3, #2
    6518:	2b00      	cmp	r3, #0
    651a:	d100      	bne.n	651e <MSS_SPI_clear_slave_select+0x3a>
    651c:	be00      	bkpt	0x0000

    /* Shut down interrupts from the MSS SPI while we do this */
    NVIC_DisableIRQ( this_spi->irqn );
    651e:	687b      	ldr	r3, [r7, #4]
    6520:	791b      	ldrb	r3, [r3, #4]
    6522:	b25b      	sxtb	r3, r3
    6524:	4618      	mov	r0, r3
    6526:	f7ff fcc3 	bl	5eb0 <NVIC_DisableIRQ>

    /* Recover from receive overflow. */
    rx_overflow = this_spi->hw_reg->STATUS & RX_OVERFLOW_MASK;
    652a:	687b      	ldr	r3, [r7, #4]
    652c:	681b      	ldr	r3, [r3, #0]
    652e:	689b      	ldr	r3, [r3, #8]
    6530:	f003 0304 	and.w	r3, r3, #4
    6534:	60fb      	str	r3, [r7, #12]
    if(rx_overflow)
    6536:	68fb      	ldr	r3, [r7, #12]
    6538:	2b00      	cmp	r3, #0
    653a:	d002      	beq.n	6542 <MSS_SPI_clear_slave_select+0x5e>
    {
         recover_from_rx_overflow(this_spi);
    653c:	6878      	ldr	r0, [r7, #4]
    653e:	f7ff fd8d 	bl	605c <recover_from_rx_overflow>
    }
    
    this_spi->hw_reg->SLAVE_SELECT &= ~((uint32_t)1 << (uint32_t)slave);
    6542:	687b      	ldr	r3, [r7, #4]
    6544:	681b      	ldr	r3, [r3, #0]
    6546:	687a      	ldr	r2, [r7, #4]
    6548:	6812      	ldr	r2, [r2, #0]
    654a:	69d1      	ldr	r1, [r2, #28]
    654c:	78fa      	ldrb	r2, [r7, #3]
    654e:	f04f 0001 	mov.w	r0, #1
    6552:	fa00 f202 	lsl.w	r2, r0, r2
    6556:	ea6f 0202 	mvn.w	r2, r2
    655a:	ea01 0202 	and.w	r2, r1, r2
    655e:	61da      	str	r2, [r3, #28]
    /* Reenable interrupts */
    NVIC_EnableIRQ( this_spi->irqn );
    6560:	687b      	ldr	r3, [r7, #4]
    6562:	791b      	ldrb	r3, [r3, #4]
    6564:	b25b      	sxtb	r3, r3
    6566:	4618      	mov	r0, r3
    6568:	f7ff fc86 	bl	5e78 <NVIC_EnableIRQ>
}
    656c:	f107 0710 	add.w	r7, r7, #16
    6570:	46bd      	mov	sp, r7
    6572:	bd80      	pop	{r7, pc}

00006574 <MSS_SPI_transfer_frame>:
uint32_t MSS_SPI_transfer_frame
(
    mss_spi_instance_t * this_spi,
    uint32_t tx_bits
)
{
    6574:	b480      	push	{r7}
    6576:	b085      	sub	sp, #20
    6578:	af00      	add	r7, sp, #0
    657a:	6078      	str	r0, [r7, #4]
    657c:	6039      	str	r1, [r7, #0]
    uint32_t rx_ready;
    uint32_t tx_done;
    
    ASSERT((this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1));
    657e:	687a      	ldr	r2, [r7, #4]
    6580:	f240 23bc 	movw	r3, #700	; 0x2bc
    6584:	f2c2 0300 	movt	r3, #8192	; 0x2000
    6588:	429a      	cmp	r2, r3
    658a:	d007      	beq.n	659c <MSS_SPI_transfer_frame+0x28>
    658c:	687a      	ldr	r2, [r7, #4]
    658e:	f240 2338 	movw	r3, #568	; 0x238
    6592:	f2c2 0300 	movt	r3, #8192	; 0x2000
    6596:	429a      	cmp	r2, r3
    6598:	d000      	beq.n	659c <MSS_SPI_transfer_frame+0x28>
    659a:	be00      	bkpt	0x0000
    
    /* This function is only intended to be used with an SPI master. */
    ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK) == CTRL_MASTER_MASK);
    659c:	687b      	ldr	r3, [r7, #4]
    659e:	681b      	ldr	r3, [r3, #0]
    65a0:	681b      	ldr	r3, [r3, #0]
    65a2:	f003 0302 	and.w	r3, r3, #2
    65a6:	2b00      	cmp	r3, #0
    65a8:	d100      	bne.n	65ac <MSS_SPI_transfer_frame+0x38>
    65aa:	be00      	bkpt	0x0000
    
    /* Ensure single frame transfer selected so interrupts work correctly */
    this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK)
    65ac:	687b      	ldr	r3, [r7, #4]
    65ae:	681a      	ldr	r2, [r3, #0]
    65b0:	687b      	ldr	r3, [r7, #4]
    65b2:	681b      	ldr	r3, [r3, #0]
    65b4:	6819      	ldr	r1, [r3, #0]
    65b6:	f240 03ff 	movw	r3, #255	; 0xff
    65ba:	f6cf 7300 	movt	r3, #65280	; 0xff00
    65be:	ea01 0303 	and.w	r3, r1, r3
    65c2:	f443 7380 	orr.w	r3, r3, #256	; 0x100
    65c6:	6013      	str	r3, [r2, #0]
                                | ((uint32_t)1u << TXRXDFCOUNT_SHIFT);

    /* Flush the Tx and Rx FIFOs. */
    this_spi->hw_reg->COMMAND |= (TX_FIFO_RESET_MASK | RX_FIFO_RESET_MASK);
    65c8:	687b      	ldr	r3, [r7, #4]
    65ca:	681b      	ldr	r3, [r3, #0]
    65cc:	687a      	ldr	r2, [r7, #4]
    65ce:	6812      	ldr	r2, [r2, #0]
    65d0:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
    65d2:	f042 020c 	orr.w	r2, r2, #12
    65d6:	62da      	str	r2, [r3, #44]	; 0x2c
    
    /* Send frame. */
    this_spi->hw_reg->TX_DATA = tx_bits;
    65d8:	687b      	ldr	r3, [r7, #4]
    65da:	681b      	ldr	r3, [r3, #0]
    65dc:	683a      	ldr	r2, [r7, #0]
    65de:	615a      	str	r2, [r3, #20]
    
    /* Wait for frame Tx to complete. */
    tx_done = this_spi->hw_reg->STATUS & TX_DONE_MASK;
    65e0:	687b      	ldr	r3, [r7, #4]
    65e2:	681b      	ldr	r3, [r3, #0]
    65e4:	689b      	ldr	r3, [r3, #8]
    65e6:	f003 0301 	and.w	r3, r3, #1
    65ea:	60fb      	str	r3, [r7, #12]
    while(0u == tx_done)
    65ec:	e005      	b.n	65fa <MSS_SPI_transfer_frame+0x86>
    {
        tx_done = this_spi->hw_reg->STATUS & TX_DONE_MASK;
    65ee:	687b      	ldr	r3, [r7, #4]
    65f0:	681b      	ldr	r3, [r3, #0]
    65f2:	689b      	ldr	r3, [r3, #8]
    65f4:	f003 0301 	and.w	r3, r3, #1
    65f8:	60fb      	str	r3, [r7, #12]
    /* Send frame. */
    this_spi->hw_reg->TX_DATA = tx_bits;
    
    /* Wait for frame Tx to complete. */
    tx_done = this_spi->hw_reg->STATUS & TX_DONE_MASK;
    while(0u == tx_done)
    65fa:	68fb      	ldr	r3, [r7, #12]
    65fc:	2b00      	cmp	r3, #0
    65fe:	d0f6      	beq.n	65ee <MSS_SPI_transfer_frame+0x7a>
        tx_done = this_spi->hw_reg->STATUS & TX_DONE_MASK;
    }
    
    /* Read received frame. */
    /* Wait for Rx complete. */
    rx_ready = this_spi->hw_reg->STATUS & RX_DATA_READY_MASK;
    6600:	687b      	ldr	r3, [r7, #4]
    6602:	681b      	ldr	r3, [r3, #0]
    6604:	689b      	ldr	r3, [r3, #8]
    6606:	f003 0302 	and.w	r3, r3, #2
    660a:	60bb      	str	r3, [r7, #8]
    while(0u == rx_ready)
    660c:	e005      	b.n	661a <MSS_SPI_transfer_frame+0xa6>
    {
        rx_ready = this_spi->hw_reg->STATUS & RX_DATA_READY_MASK;
    660e:	687b      	ldr	r3, [r7, #4]
    6610:	681b      	ldr	r3, [r3, #0]
    6612:	689b      	ldr	r3, [r3, #8]
    6614:	f003 0302 	and.w	r3, r3, #2
    6618:	60bb      	str	r3, [r7, #8]
    }
    
    /* Read received frame. */
    /* Wait for Rx complete. */
    rx_ready = this_spi->hw_reg->STATUS & RX_DATA_READY_MASK;
    while(0u == rx_ready)
    661a:	68bb      	ldr	r3, [r7, #8]
    661c:	2b00      	cmp	r3, #0
    661e:	d0f6      	beq.n	660e <MSS_SPI_transfer_frame+0x9a>
    {
        rx_ready = this_spi->hw_reg->STATUS & RX_DATA_READY_MASK;
    }
    /* Return Rx data. */
    return( this_spi->hw_reg->RX_DATA );
    6620:	687b      	ldr	r3, [r7, #4]
    6622:	681b      	ldr	r3, [r3, #0]
    6624:	691b      	ldr	r3, [r3, #16]
}
    6626:	4618      	mov	r0, r3
    6628:	f107 0714 	add.w	r7, r7, #20
    662c:	46bd      	mov	sp, r7
    662e:	bc80      	pop	{r7}
    6630:	4770      	bx	lr
    6632:	bf00      	nop

00006634 <MSS_SPI_transfer_block>:
    const uint8_t * cmd_buffer,
    uint16_t cmd_byte_size,
    uint8_t * rd_buffer,
    uint16_t rd_byte_size
)
{
    6634:	b580      	push	{r7, lr}
    6636:	b08e      	sub	sp, #56	; 0x38
    6638:	af00      	add	r7, sp, #0
    663a:	60f8      	str	r0, [r7, #12]
    663c:	60b9      	str	r1, [r7, #8]
    663e:	603b      	str	r3, [r7, #0]
    6640:	4613      	mov	r3, r2
    6642:	80fb      	strh	r3, [r7, #6]
    uint16_t transfer_idx = 0u;
    6644:	f04f 0300 	mov.w	r3, #0
    6648:	837b      	strh	r3, [r7, #26]
    uint16_t tx_idx;
    uint16_t rx_idx;
    uint32_t frame_count;
    volatile uint32_t rx_raw;
    uint16_t transit = 0u;
    664a:	f04f 0300 	mov.w	r3, #0
    664e:	84fb      	strh	r3, [r7, #38]	; 0x26
    uint32_t rx_overflow;
    uint32_t rx_fifo_empty;
    
    uint16_t transfer_size;     /* Total number of bytes transfered. */
    
    ASSERT((this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1));
    6650:	68fa      	ldr	r2, [r7, #12]
    6652:	f240 23bc 	movw	r3, #700	; 0x2bc
    6656:	f2c2 0300 	movt	r3, #8192	; 0x2000
    665a:	429a      	cmp	r2, r3
    665c:	d007      	beq.n	666e <MSS_SPI_transfer_block+0x3a>
    665e:	68fa      	ldr	r2, [r7, #12]
    6660:	f240 2338 	movw	r3, #568	; 0x238
    6664:	f2c2 0300 	movt	r3, #8192	; 0x2000
    6668:	429a      	cmp	r2, r3
    666a:	d000      	beq.n	666e <MSS_SPI_transfer_block+0x3a>
    666c:	be00      	bkpt	0x0000
    
    /* This function is only intended to be used with an SPI master. */
    ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK) == CTRL_MASTER_MASK);
    666e:	68fb      	ldr	r3, [r7, #12]
    6670:	681b      	ldr	r3, [r3, #0]
    6672:	681b      	ldr	r3, [r3, #0]
    6674:	f003 0302 	and.w	r3, r3, #2
    6678:	2b00      	cmp	r3, #0
    667a:	d100      	bne.n	667e <MSS_SPI_transfer_block+0x4a>
    667c:	be00      	bkpt	0x0000
    
    /* Compute number of bytes to transfer. */
    transfer_size = cmd_byte_size + rd_byte_size;
    667e:	88fa      	ldrh	r2, [r7, #6]
    6680:	f8b7 3040 	ldrh.w	r3, [r7, #64]	; 0x40
    6684:	4413      	add	r3, r2
    6686:	86fb      	strh	r3, [r7, #54]	; 0x36
    
    /* Adjust to 1 byte transfer to cater for DMA transfers. */
    if(0u == transfer_size)
    6688:	8efb      	ldrh	r3, [r7, #54]	; 0x36
    668a:	2b00      	cmp	r3, #0
    668c:	d103      	bne.n	6696 <MSS_SPI_transfer_block+0x62>
    {
        frame_count = 1u;
    668e:	f04f 0301 	mov.w	r3, #1
    6692:	623b      	str	r3, [r7, #32]
    6694:	e001      	b.n	669a <MSS_SPI_transfer_block+0x66>
    }
    else
    {
        frame_count = transfer_size;
    6696:	8efb      	ldrh	r3, [r7, #54]	; 0x36
    6698:	623b      	str	r3, [r7, #32]
    }

    /* Flush the Tx and Rx FIFOs. */
    this_spi->hw_reg->COMMAND |= (TX_FIFO_RESET_MASK | RX_FIFO_RESET_MASK);
    669a:	68fb      	ldr	r3, [r7, #12]
    669c:	681b      	ldr	r3, [r3, #0]
    669e:	68fa      	ldr	r2, [r7, #12]
    66a0:	6812      	ldr	r2, [r2, #0]
    66a2:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
    66a4:	f042 020c 	orr.w	r2, r2, #12
    66a8:	62da      	str	r2, [r3, #44]	; 0x2c
    
    /* Recover from receive overflow. */
    rx_overflow = this_spi->hw_reg->STATUS & RX_OVERFLOW_MASK;
    66aa:	68fb      	ldr	r3, [r7, #12]
    66ac:	681b      	ldr	r3, [r3, #0]
    66ae:	689b      	ldr	r3, [r3, #8]
    66b0:	f003 0304 	and.w	r3, r3, #4
    66b4:	62fb      	str	r3, [r7, #44]	; 0x2c
    if(rx_overflow)
    66b6:	6afb      	ldr	r3, [r7, #44]	; 0x2c
    66b8:	2b00      	cmp	r3, #0
    66ba:	d002      	beq.n	66c2 <MSS_SPI_transfer_block+0x8e>
    {
         recover_from_rx_overflow(this_spi);
    66bc:	68f8      	ldr	r0, [r7, #12]
    66be:	f7ff fccd 	bl	605c <recover_from_rx_overflow>
    }
    
    /* Set frame size to 8 bits and the frame count to the transfer size. */
    this_spi->hw_reg->CONTROL &= ~(uint32_t)CTRL_ENABLE_MASK;
    66c2:	68fb      	ldr	r3, [r7, #12]
    66c4:	681b      	ldr	r3, [r3, #0]
    66c6:	68fa      	ldr	r2, [r7, #12]
    66c8:	6812      	ldr	r2, [r2, #0]
    66ca:	6812      	ldr	r2, [r2, #0]
    66cc:	f022 0201 	bic.w	r2, r2, #1
    66d0:	601a      	str	r2, [r3, #0]
    this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK) | ( (frame_count << TXRXDFCOUNT_SHIFT) & TXRXDFCOUNT_MASK);
    66d2:	68fb      	ldr	r3, [r7, #12]
    66d4:	6819      	ldr	r1, [r3, #0]
    66d6:	68fb      	ldr	r3, [r7, #12]
    66d8:	681b      	ldr	r3, [r3, #0]
    66da:	681b      	ldr	r3, [r3, #0]
    66dc:	f240 02ff 	movw	r2, #255	; 0xff
    66e0:	f6cf 7200 	movt	r2, #65280	; 0xff00
    66e4:	ea03 0202 	and.w	r2, r3, r2
    66e8:	6a3b      	ldr	r3, [r7, #32]
    66ea:	ea4f 2003 	mov.w	r0, r3, lsl #8
    66ee:	f64f 7300 	movw	r3, #65280	; 0xff00
    66f2:	f2c0 03ff 	movt	r3, #255	; 0xff
    66f6:	ea00 0303 	and.w	r3, r0, r3
    66fa:	ea42 0303 	orr.w	r3, r2, r3
    66fe:	600b      	str	r3, [r1, #0]
    this_spi->hw_reg->TXRXDF_SIZE = MSS_SPI_BLOCK_TRANSFER_FRAME_SIZE;
    6700:	68fb      	ldr	r3, [r7, #12]
    6702:	681b      	ldr	r3, [r3, #0]
    6704:	f04f 0208 	mov.w	r2, #8
    6708:	605a      	str	r2, [r3, #4]
    this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK;
    670a:	68fb      	ldr	r3, [r7, #12]
    670c:	681b      	ldr	r3, [r3, #0]
    670e:	68fa      	ldr	r2, [r7, #12]
    6710:	6812      	ldr	r2, [r2, #0]
    6712:	6812      	ldr	r2, [r2, #0]
    6714:	f042 0201 	orr.w	r2, r2, #1
    6718:	601a      	str	r2, [r3, #0]

    /* Flush the receive FIFO. */
    rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK;
    671a:	68fb      	ldr	r3, [r7, #12]
    671c:	681b      	ldr	r3, [r3, #0]
    671e:	689b      	ldr	r3, [r3, #8]
    6720:	f003 0340 	and.w	r3, r3, #64	; 0x40
    6724:	633b      	str	r3, [r7, #48]	; 0x30
    while(0u == rx_fifo_empty)
    6726:	e009      	b.n	673c <MSS_SPI_transfer_block+0x108>
    {
        rx_raw = this_spi->hw_reg->RX_DATA;
    6728:	68fb      	ldr	r3, [r7, #12]
    672a:	681b      	ldr	r3, [r3, #0]
    672c:	691b      	ldr	r3, [r3, #16]
    672e:	617b      	str	r3, [r7, #20]
        rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK;
    6730:	68fb      	ldr	r3, [r7, #12]
    6732:	681b      	ldr	r3, [r3, #0]
    6734:	689b      	ldr	r3, [r3, #8]
    6736:	f003 0340 	and.w	r3, r3, #64	; 0x40
    673a:	633b      	str	r3, [r7, #48]	; 0x30
    this_spi->hw_reg->TXRXDF_SIZE = MSS_SPI_BLOCK_TRANSFER_FRAME_SIZE;
    this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK;

    /* Flush the receive FIFO. */
    rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK;
    while(0u == rx_fifo_empty)
    673c:	6b3b      	ldr	r3, [r7, #48]	; 0x30
    673e:	2b00      	cmp	r3, #0
    6740:	d0f2      	beq.n	6728 <MSS_SPI_transfer_block+0xf4>
    {
        rx_raw = this_spi->hw_reg->RX_DATA;
        rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK;
    }
    
    tx_idx = 0u;
    6742:	f04f 0300 	mov.w	r3, #0
    6746:	83bb      	strh	r3, [r7, #28]
    rx_idx = 0u;
    6748:	f04f 0300 	mov.w	r3, #0
    674c:	83fb      	strh	r3, [r7, #30]
    if(tx_idx < cmd_byte_size)
    674e:	8bba      	ldrh	r2, [r7, #28]
    6750:	88fb      	ldrh	r3, [r7, #6]
    6752:	429a      	cmp	r2, r3
    6754:	d20f      	bcs.n	6776 <MSS_SPI_transfer_block+0x142>
    {
        this_spi->hw_reg->TX_DATA = cmd_buffer[tx_idx];
    6756:	68fb      	ldr	r3, [r7, #12]
    6758:	681b      	ldr	r3, [r3, #0]
    675a:	8bb9      	ldrh	r1, [r7, #28]
    675c:	68ba      	ldr	r2, [r7, #8]
    675e:	440a      	add	r2, r1
    6760:	7812      	ldrb	r2, [r2, #0]
    6762:	615a      	str	r2, [r3, #20]
        ++tx_idx;
    6764:	8bbb      	ldrh	r3, [r7, #28]
    6766:	f103 0301 	add.w	r3, r3, #1
    676a:	83bb      	strh	r3, [r7, #28]
        ++transit;
    676c:	8cfb      	ldrh	r3, [r7, #38]	; 0x26
    676e:	f103 0301 	add.w	r3, r3, #1
    6772:	84fb      	strh	r3, [r7, #38]	; 0x26
        }
    }
    /* Perform the remainder of the transfer by sending a byte every time a byte
     * has been received. This should ensure that no Rx overflow can happen in
     * case of an interrupt occurs during this function. */
    while(transfer_idx < transfer_size)
    6774:	e06a      	b.n	684c <MSS_SPI_transfer_block+0x218>
        ++tx_idx;
        ++transit;
    }
    else
    {
        if(tx_idx < transfer_size)
    6776:	8bba      	ldrh	r2, [r7, #28]
    6778:	8efb      	ldrh	r3, [r7, #54]	; 0x36
    677a:	429a      	cmp	r2, r3
    677c:	d266      	bcs.n	684c <MSS_SPI_transfer_block+0x218>
        {
            this_spi->hw_reg->TX_DATA = 0x00u;
    677e:	68fb      	ldr	r3, [r7, #12]
    6780:	681b      	ldr	r3, [r3, #0]
    6782:	f04f 0200 	mov.w	r2, #0
    6786:	615a      	str	r2, [r3, #20]
            ++tx_idx;
    6788:	8bbb      	ldrh	r3, [r7, #28]
    678a:	f103 0301 	add.w	r3, r3, #1
    678e:	83bb      	strh	r3, [r7, #28]
            ++transit;
    6790:	8cfb      	ldrh	r3, [r7, #38]	; 0x26
    6792:	f103 0301 	add.w	r3, r3, #1
    6796:	84fb      	strh	r3, [r7, #38]	; 0x26
        }
    }
    /* Perform the remainder of the transfer by sending a byte every time a byte
     * has been received. This should ensure that no Rx overflow can happen in
     * case of an interrupt occurs during this function. */
    while(transfer_idx < transfer_size)
    6798:	e058      	b.n	684c <MSS_SPI_transfer_block+0x218>
    {
        rx_fifo_empty = this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK;
    679a:	68fb      	ldr	r3, [r7, #12]
    679c:	681b      	ldr	r3, [r3, #0]
    679e:	689b      	ldr	r3, [r3, #8]
    67a0:	f003 0340 	and.w	r3, r3, #64	; 0x40
    67a4:	633b      	str	r3, [r7, #48]	; 0x30
        if(0u == rx_fifo_empty)
    67a6:	6b3b      	ldr	r3, [r7, #48]	; 0x30
    67a8:	2b00      	cmp	r3, #0
    67aa:	d11e      	bne.n	67ea <MSS_SPI_transfer_block+0x1b6>
        {
            /* Process received byte. */
            rx_raw = this_spi->hw_reg->RX_DATA;
    67ac:	68fb      	ldr	r3, [r7, #12]
    67ae:	681b      	ldr	r3, [r3, #0]
    67b0:	691b      	ldr	r3, [r3, #16]
    67b2:	617b      	str	r3, [r7, #20]
            if(transfer_idx >= cmd_byte_size)
    67b4:	8b7a      	ldrh	r2, [r7, #26]
    67b6:	88fb      	ldrh	r3, [r7, #6]
    67b8:	429a      	cmp	r2, r3
    67ba:	d30e      	bcc.n	67da <MSS_SPI_transfer_block+0x1a6>
            {
                if(rx_idx < rd_byte_size)
    67bc:	8bfa      	ldrh	r2, [r7, #30]
    67be:	f8b7 3040 	ldrh.w	r3, [r7, #64]	; 0x40
    67c2:	429a      	cmp	r2, r3
    67c4:	d205      	bcs.n	67d2 <MSS_SPI_transfer_block+0x19e>
                {
                    rd_buffer[rx_idx] = (uint8_t)rx_raw;   
    67c6:	8bfa      	ldrh	r2, [r7, #30]
    67c8:	683b      	ldr	r3, [r7, #0]
    67ca:	4413      	add	r3, r2
    67cc:	697a      	ldr	r2, [r7, #20]
    67ce:	b2d2      	uxtb	r2, r2
    67d0:	701a      	strb	r2, [r3, #0]
                }
                ++rx_idx;
    67d2:	8bfb      	ldrh	r3, [r7, #30]
    67d4:	f103 0301 	add.w	r3, r3, #1
    67d8:	83fb      	strh	r3, [r7, #30]
            }
            ++transfer_idx;
    67da:	8b7b      	ldrh	r3, [r7, #26]
    67dc:	f103 0301 	add.w	r3, r3, #1
    67e0:	837b      	strh	r3, [r7, #26]
            --transit;
    67e2:	8cfb      	ldrh	r3, [r7, #38]	; 0x26
    67e4:	f103 33ff 	add.w	r3, r3, #4294967295
    67e8:	84fb      	strh	r3, [r7, #38]	; 0x26
        }

        tx_fifo_full = this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK;
    67ea:	68fb      	ldr	r3, [r7, #12]
    67ec:	681b      	ldr	r3, [r3, #0]
    67ee:	689b      	ldr	r3, [r3, #8]
    67f0:	f403 7380 	and.w	r3, r3, #256	; 0x100
    67f4:	62bb      	str	r3, [r7, #40]	; 0x28
        if(0u == tx_fifo_full)
    67f6:	6abb      	ldr	r3, [r7, #40]	; 0x28
    67f8:	2b00      	cmp	r3, #0
    67fa:	d127      	bne.n	684c <MSS_SPI_transfer_block+0x218>
        {
            if(transit < RX_FIFO_SIZE)
    67fc:	8cfb      	ldrh	r3, [r7, #38]	; 0x26
    67fe:	2b03      	cmp	r3, #3
    6800:	d824      	bhi.n	684c <MSS_SPI_transfer_block+0x218>
            {
                /* Send another byte. */
                if(tx_idx < cmd_byte_size)
    6802:	8bba      	ldrh	r2, [r7, #28]
    6804:	88fb      	ldrh	r3, [r7, #6]
    6806:	429a      	cmp	r2, r3
    6808:	d20f      	bcs.n	682a <MSS_SPI_transfer_block+0x1f6>
                {
                    this_spi->hw_reg->TX_DATA = cmd_buffer[tx_idx];
    680a:	68fb      	ldr	r3, [r7, #12]
    680c:	681b      	ldr	r3, [r3, #0]
    680e:	8bb9      	ldrh	r1, [r7, #28]
    6810:	68ba      	ldr	r2, [r7, #8]
    6812:	440a      	add	r2, r1
    6814:	7812      	ldrb	r2, [r2, #0]
    6816:	615a      	str	r2, [r3, #20]
                    ++tx_idx;
    6818:	8bbb      	ldrh	r3, [r7, #28]
    681a:	f103 0301 	add.w	r3, r3, #1
    681e:	83bb      	strh	r3, [r7, #28]
                    ++transit;
    6820:	8cfb      	ldrh	r3, [r7, #38]	; 0x26
    6822:	f103 0301 	add.w	r3, r3, #1
    6826:	84fb      	strh	r3, [r7, #38]	; 0x26
    6828:	e010      	b.n	684c <MSS_SPI_transfer_block+0x218>
                }
                else
                {
                    if(tx_idx < transfer_size)
    682a:	8bba      	ldrh	r2, [r7, #28]
    682c:	8efb      	ldrh	r3, [r7, #54]	; 0x36
    682e:	429a      	cmp	r2, r3
    6830:	d20c      	bcs.n	684c <MSS_SPI_transfer_block+0x218>
                    {
                        this_spi->hw_reg->TX_DATA = 0x00u;
    6832:	68fb      	ldr	r3, [r7, #12]
    6834:	681b      	ldr	r3, [r3, #0]
    6836:	f04f 0200 	mov.w	r2, #0
    683a:	615a      	str	r2, [r3, #20]
                        ++tx_idx;
    683c:	8bbb      	ldrh	r3, [r7, #28]
    683e:	f103 0301 	add.w	r3, r3, #1
    6842:	83bb      	strh	r3, [r7, #28]
                        ++transit;
    6844:	8cfb      	ldrh	r3, [r7, #38]	; 0x26
    6846:	f103 0301 	add.w	r3, r3, #1
    684a:	84fb      	strh	r3, [r7, #38]	; 0x26
        }
    }
    /* Perform the remainder of the transfer by sending a byte every time a byte
     * has been received. This should ensure that no Rx overflow can happen in
     * case of an interrupt occurs during this function. */
    while(transfer_idx < transfer_size)
    684c:	8b7a      	ldrh	r2, [r7, #26]
    684e:	8efb      	ldrh	r3, [r7, #54]	; 0x36
    6850:	429a      	cmp	r2, r3
    6852:	d3a2      	bcc.n	679a <MSS_SPI_transfer_block+0x166>
                    }
                }
            }
        }
    }
}
    6854:	f107 0738 	add.w	r7, r7, #56	; 0x38
    6858:	46bd      	mov	sp, r7
    685a:	bd80      	pop	{r7, pc}

0000685c <MSS_SPI_set_frame_rx_handler>:
void MSS_SPI_set_frame_rx_handler
(
    mss_spi_instance_t * this_spi,
    mss_spi_frame_rx_handler_t rx_handler
)
{
    685c:	b580      	push	{r7, lr}
    685e:	b084      	sub	sp, #16
    6860:	af00      	add	r7, sp, #0
    6862:	6078      	str	r0, [r7, #4]
    6864:	6039      	str	r1, [r7, #0]
    uint32_t tx_fifo_empty;
    
    ASSERT((this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1));
    6866:	687a      	ldr	r2, [r7, #4]
    6868:	f240 23bc 	movw	r3, #700	; 0x2bc
    686c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    6870:	429a      	cmp	r2, r3
    6872:	d007      	beq.n	6884 <MSS_SPI_set_frame_rx_handler+0x28>
    6874:	687a      	ldr	r2, [r7, #4]
    6876:	f240 2338 	movw	r3, #568	; 0x238
    687a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    687e:	429a      	cmp	r2, r3
    6880:	d000      	beq.n	6884 <MSS_SPI_set_frame_rx_handler+0x28>
    6882:	be00      	bkpt	0x0000
    
    /* This function is only intended to be used with an SPI slave. */
    ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK) != CTRL_MASTER_MASK);
    6884:	687b      	ldr	r3, [r7, #4]
    6886:	681b      	ldr	r3, [r3, #0]
    6888:	681b      	ldr	r3, [r3, #0]
    688a:	f003 0302 	and.w	r3, r3, #2
    688e:	2b00      	cmp	r3, #0
    6890:	d000      	beq.n	6894 <MSS_SPI_set_frame_rx_handler+0x38>
    6892:	be00      	bkpt	0x0000
    
    /* Shut down interrupts from the MSS SPI while we do this */
    NVIC_DisableIRQ( this_spi->irqn );
    6894:	687b      	ldr	r3, [r7, #4]
    6896:	791b      	ldrb	r3, [r3, #4]
    6898:	b25b      	sxtb	r3, r3
    689a:	4618      	mov	r0, r3
    689c:	f7ff fb08 	bl	5eb0 <NVIC_DisableIRQ>

    /* Disable block Rx handlers as they are mutually exclusive. */
    this_spi->block_rx_handler = 0u;
    68a0:	687b      	ldr	r3, [r7, #4]
    68a2:	f04f 0200 	mov.w	r2, #0
    68a6:	67da      	str	r2, [r3, #124]	; 0x7c
    this_spi->cmd_handler = 0u;
    68a8:	687b      	ldr	r3, [r7, #4]
    68aa:	f04f 0200 	mov.w	r2, #0
    68ae:	621a      	str	r2, [r3, #32]
    
    /* Keep a copy of the pointer to the rx handler function. */
    this_spi->frame_rx_handler = rx_handler;
    68b0:	687b      	ldr	r3, [r7, #4]
    68b2:	683a      	ldr	r2, [r7, #0]
    68b4:	675a      	str	r2, [r3, #116]	; 0x74
    
    /* Make sure correct mode is selected */
    this_spi->slave_xfer_mode = MSS_SPI_SLAVE_XFER_FRAME;
    68b6:	687b      	ldr	r3, [r7, #4]
    68b8:	f04f 0202 	mov.w	r2, #2
    68bc:	f883 2080 	strb.w	r2, [r3, #128]	; 0x80

    /* Automatically fill the TX FIFO with zeroes if no slave tx frame set.*/
    tx_fifo_empty = this_spi->hw_reg->STATUS & TX_FIFO_EMPTY_MASK;
    68c0:	687b      	ldr	r3, [r7, #4]
    68c2:	681b      	ldr	r3, [r3, #0]
    68c4:	689b      	ldr	r3, [r3, #8]
    68c6:	f403 6380 	and.w	r3, r3, #1024	; 0x400
    68ca:	60fb      	str	r3, [r7, #12]
    if(tx_fifo_empty)
    68cc:	68fb      	ldr	r3, [r7, #12]
    68ce:	2b00      	cmp	r3, #0
    68d0:	d007      	beq.n	68e2 <MSS_SPI_set_frame_rx_handler+0x86>
    {
        this_spi->hw_reg->COMMAND |= AUTOFILL_MASK;
    68d2:	687b      	ldr	r3, [r7, #4]
    68d4:	681b      	ldr	r3, [r3, #0]
    68d6:	687a      	ldr	r2, [r7, #4]
    68d8:	6812      	ldr	r2, [r2, #0]
    68da:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
    68dc:	f042 0201 	orr.w	r2, r2, #1
    68e0:	62da      	str	r2, [r3, #44]	; 0x2c
    }
    
    /* Ensure single frame transfer selected so interrupts work correctly */
    this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK)
    68e2:	687b      	ldr	r3, [r7, #4]
    68e4:	681a      	ldr	r2, [r3, #0]
    68e6:	687b      	ldr	r3, [r7, #4]
    68e8:	681b      	ldr	r3, [r3, #0]
    68ea:	6819      	ldr	r1, [r3, #0]
    68ec:	f240 03ff 	movw	r3, #255	; 0xff
    68f0:	f6cf 7300 	movt	r3, #65280	; 0xff00
    68f4:	ea01 0303 	and.w	r3, r1, r3
    68f8:	f443 7380 	orr.w	r3, r3, #256	; 0x100
    68fc:	6013      	str	r3, [r2, #0]
                                | ((uint32_t)1u << TXRXDFCOUNT_SHIFT);

    /* Disable block specific interrupts */
    this_spi->hw_reg->CONTROL2 &= ~(uint32_t)C2_ENABLE_CMD_IRQ_MASK;
    68fe:	687b      	ldr	r3, [r7, #4]
    6900:	681b      	ldr	r3, [r3, #0]
    6902:	687a      	ldr	r2, [r7, #4]
    6904:	6812      	ldr	r2, [r2, #0]
    6906:	6a92      	ldr	r2, [r2, #40]	; 0x28
    6908:	f022 0210 	bic.w	r2, r2, #16
    690c:	629a      	str	r2, [r3, #40]	; 0x28
    this_spi->hw_reg->CONTROL2 &= ~(uint32_t)C2_ENABLE_SSEND_IRQ_MASK;
    690e:	687b      	ldr	r3, [r7, #4]
    6910:	681b      	ldr	r3, [r3, #0]
    6912:	687a      	ldr	r2, [r7, #4]
    6914:	6812      	ldr	r2, [r2, #0]
    6916:	6a92      	ldr	r2, [r2, #40]	; 0x28
    6918:	f022 0220 	bic.w	r2, r2, #32
    691c:	629a      	str	r2, [r3, #40]	; 0x28

    /* Clear down ints to avoid stale ints triggering when we enable them below */
    this_spi->hw_reg->INT_CLEAR = TXURUN_IRQ_MASK | RXOVFLOW_IRQ_MASK |
    691e:	687b      	ldr	r3, [r7, #4]
    6920:	681b      	ldr	r3, [r3, #0]
    6922:	f04f 020e 	mov.w	r2, #14
    6926:	60da      	str	r2, [r3, #12]
                                  RXDONE_IRQ_MASK;
    /*
     * Enable TX underrun and RX overflow interrupts to improve error
     * recovery and the Rx interrupt.
     */
    this_spi->hw_reg->CONTROL |= CTRL_URUN_IRQ_EN_MASK | CTRL_OVFLOW_IRQ_EN_MASK |
    6928:	687b      	ldr	r3, [r7, #4]
    692a:	681b      	ldr	r3, [r3, #0]
    692c:	687a      	ldr	r2, [r7, #4]
    692e:	6812      	ldr	r2, [r2, #0]
    6930:	6812      	ldr	r2, [r2, #0]
    6932:	f042 02d0 	orr.w	r2, r2, #208	; 0xd0
    6936:	601a      	str	r2, [r3, #0]
                                 CTRL_RX_IRQ_EN_MASK;
    NVIC_EnableIRQ( this_spi->irqn );
    6938:	687b      	ldr	r3, [r7, #4]
    693a:	791b      	ldrb	r3, [r3, #4]
    693c:	b25b      	sxtb	r3, r3
    693e:	4618      	mov	r0, r3
    6940:	f7ff fa9a 	bl	5e78 <NVIC_EnableIRQ>
}
    6944:	f107 0710 	add.w	r7, r7, #16
    6948:	46bd      	mov	sp, r7
    694a:	bd80      	pop	{r7, pc}

0000694c <MSS_SPI_set_slave_tx_frame>:
void MSS_SPI_set_slave_tx_frame
(
    mss_spi_instance_t * this_spi,
    uint32_t frame_value
)
{
    694c:	b580      	push	{r7, lr}
    694e:	b082      	sub	sp, #8
    6950:	af00      	add	r7, sp, #0
    6952:	6078      	str	r0, [r7, #4]
    6954:	6039      	str	r1, [r7, #0]
    ASSERT((this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1));
    6956:	687a      	ldr	r2, [r7, #4]
    6958:	f240 23bc 	movw	r3, #700	; 0x2bc
    695c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    6960:	429a      	cmp	r2, r3
    6962:	d007      	beq.n	6974 <MSS_SPI_set_slave_tx_frame+0x28>
    6964:	687a      	ldr	r2, [r7, #4]
    6966:	f240 2338 	movw	r3, #568	; 0x238
    696a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    696e:	429a      	cmp	r2, r3
    6970:	d000      	beq.n	6974 <MSS_SPI_set_slave_tx_frame+0x28>
    6972:	be00      	bkpt	0x0000

    /* This function is only intended to be used with an SPI slave. */
    ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK) != CTRL_MASTER_MASK);
    6974:	687b      	ldr	r3, [r7, #4]
    6976:	681b      	ldr	r3, [r3, #0]
    6978:	681b      	ldr	r3, [r3, #0]
    697a:	f003 0302 	and.w	r3, r3, #2
    697e:	2b00      	cmp	r3, #0
    6980:	d000      	beq.n	6984 <MSS_SPI_set_slave_tx_frame+0x38>
    6982:	be00      	bkpt	0x0000
    
    /* Shut down interrupts from the MSS SPI while we do this */
    NVIC_DisableIRQ( this_spi->irqn );
    6984:	687b      	ldr	r3, [r7, #4]
    6986:	791b      	ldrb	r3, [r3, #4]
    6988:	b25b      	sxtb	r3, r3
    698a:	4618      	mov	r0, r3
    698c:	f7ff fa90 	bl	5eb0 <NVIC_DisableIRQ>

    /* Make sure correct mode is selected */
    this_spi->slave_xfer_mode = MSS_SPI_SLAVE_XFER_FRAME;
    6990:	687b      	ldr	r3, [r7, #4]
    6992:	f04f 0202 	mov.w	r2, #2
    6996:	f883 2080 	strb.w	r2, [r3, #128]	; 0x80

    /* Disable block Rx handlers as they are mutually exclusive. */
    this_spi->block_rx_handler = 0u;
    699a:	687b      	ldr	r3, [r7, #4]
    699c:	f04f 0200 	mov.w	r2, #0
    69a0:	67da      	str	r2, [r3, #124]	; 0x7c
    this_spi->cmd_handler = 0u;
    69a2:	687b      	ldr	r3, [r7, #4]
    69a4:	f04f 0200 	mov.w	r2, #0
    69a8:	621a      	str	r2, [r3, #32]

    /* Disable slave block tx buffer as it is mutually exclusive with frame
     * level handling. */    
    this_spi->slave_tx_buffer = 0u;
    69aa:	687b      	ldr	r3, [r7, #4]
    69ac:	f04f 0200 	mov.w	r2, #0
    69b0:	609a      	str	r2, [r3, #8]
    this_spi->slave_tx_size = 0u;
    69b2:	687b      	ldr	r3, [r7, #4]
    69b4:	f04f 0200 	mov.w	r2, #0
    69b8:	60da      	str	r2, [r3, #12]
    this_spi->slave_tx_idx = 0u;
    69ba:	687b      	ldr	r3, [r7, #4]
    69bc:	f04f 0200 	mov.w	r2, #0
    69c0:	611a      	str	r2, [r3, #16]
    
    /* Keep a copy of the slave tx frame value. */
    this_spi->slave_tx_frame = frame_value;
    69c2:	687b      	ldr	r3, [r7, #4]
    69c4:	683a      	ldr	r2, [r7, #0]
    69c6:	679a      	str	r2, [r3, #120]	; 0x78
    
    /* Disable automatic fill of the TX FIFO with zeroes.*/
    this_spi->hw_reg->COMMAND &= ~(uint32_t)AUTOFILL_MASK;
    69c8:	687b      	ldr	r3, [r7, #4]
    69ca:	681b      	ldr	r3, [r3, #0]
    69cc:	687a      	ldr	r2, [r7, #4]
    69ce:	6812      	ldr	r2, [r2, #0]
    69d0:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
    69d2:	f022 0201 	bic.w	r2, r2, #1
    69d6:	62da      	str	r2, [r3, #44]	; 0x2c
    this_spi->hw_reg->COMMAND |= TX_FIFO_RESET_MASK;
    69d8:	687b      	ldr	r3, [r7, #4]
    69da:	681b      	ldr	r3, [r3, #0]
    69dc:	687a      	ldr	r2, [r7, #4]
    69de:	6812      	ldr	r2, [r2, #0]
    69e0:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
    69e2:	f042 0208 	orr.w	r2, r2, #8
    69e6:	62da      	str	r2, [r3, #44]	; 0x2c
     *
     * IMPORTANT: Note this must be done before writing to the TX_DATA register
     * as it seems that doing these in the opposite order causes the receive
     * and transmit interrupts to be disabled.
     */
    this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK)
    69e8:	687b      	ldr	r3, [r7, #4]
    69ea:	681a      	ldr	r2, [r3, #0]
    69ec:	687b      	ldr	r3, [r7, #4]
    69ee:	681b      	ldr	r3, [r3, #0]
    69f0:	6819      	ldr	r1, [r3, #0]
    69f2:	f240 03ff 	movw	r3, #255	; 0xff
    69f6:	f6cf 7300 	movt	r3, #65280	; 0xff00
    69fa:	ea01 0303 	and.w	r3, r1, r3
    69fe:	f443 7380 	orr.w	r3, r3, #256	; 0x100
    6a02:	6013      	str	r3, [r2, #0]
                                | ((uint32_t)1u << TXRXDFCOUNT_SHIFT);

    /* Load frame into Tx data register. */
    this_spi->hw_reg->TX_DATA = this_spi->slave_tx_frame;
    6a04:	687b      	ldr	r3, [r7, #4]
    6a06:	681b      	ldr	r3, [r3, #0]
    6a08:	687a      	ldr	r2, [r7, #4]
    6a0a:	6f92      	ldr	r2, [r2, #120]	; 0x78
    6a0c:	615a      	str	r2, [r3, #20]

   /* Disable block specific interrupts */
    this_spi->hw_reg->CONTROL2 &= ~(uint32_t)C2_ENABLE_CMD_IRQ_MASK;
    6a0e:	687b      	ldr	r3, [r7, #4]
    6a10:	681b      	ldr	r3, [r3, #0]
    6a12:	687a      	ldr	r2, [r7, #4]
    6a14:	6812      	ldr	r2, [r2, #0]
    6a16:	6a92      	ldr	r2, [r2, #40]	; 0x28
    6a18:	f022 0210 	bic.w	r2, r2, #16
    6a1c:	629a      	str	r2, [r3, #40]	; 0x28
    this_spi->hw_reg->CONTROL2 &= ~(uint32_t)C2_ENABLE_SSEND_IRQ_MASK;
    6a1e:	687b      	ldr	r3, [r7, #4]
    6a20:	681b      	ldr	r3, [r3, #0]
    6a22:	687a      	ldr	r2, [r7, #4]
    6a24:	6812      	ldr	r2, [r2, #0]
    6a26:	6a92      	ldr	r2, [r2, #40]	; 0x28
    6a28:	f022 0220 	bic.w	r2, r2, #32
    6a2c:	629a      	str	r2, [r3, #40]	; 0x28

    /* Clear down ints to avoid stale ints triggering when we enable them below */
    this_spi->hw_reg->INT_CLEAR = TXURUN_IRQ_MASK | RXOVFLOW_IRQ_MASK |
    6a2e:	687b      	ldr	r3, [r7, #4]
    6a30:	681b      	ldr	r3, [r3, #0]
    6a32:	f04f 020d 	mov.w	r2, #13
    6a36:	60da      	str	r2, [r3, #12]
     * time it has been sent.
     *
     * Enable TX underrun and RX overflow interrupts to improve error
     * recovery.
     */
    this_spi->hw_reg->CONTROL |= CTRL_TX_IRQ_EN_MASK | CTRL_URUN_IRQ_EN_MASK |
    6a38:	687b      	ldr	r3, [r7, #4]
    6a3a:	681b      	ldr	r3, [r3, #0]
    6a3c:	687a      	ldr	r2, [r7, #4]
    6a3e:	6812      	ldr	r2, [r2, #0]
    6a40:	6812      	ldr	r2, [r2, #0]
    6a42:	f042 02e0 	orr.w	r2, r2, #224	; 0xe0
    6a46:	601a      	str	r2, [r3, #0]
                                 CTRL_OVFLOW_IRQ_EN_MASK;

    NVIC_EnableIRQ( this_spi->irqn );
    6a48:	687b      	ldr	r3, [r7, #4]
    6a4a:	791b      	ldrb	r3, [r3, #4]
    6a4c:	b25b      	sxtb	r3, r3
    6a4e:	4618      	mov	r0, r3
    6a50:	f7ff fa12 	bl	5e78 <NVIC_EnableIRQ>
}
    6a54:	f107 0708 	add.w	r7, r7, #8
    6a58:	46bd      	mov	sp, r7
    6a5a:	bd80      	pop	{r7, pc}

00006a5c <MSS_SPI_set_slave_block_buffers>:
    uint32_t tx_buff_size,
    uint8_t * rx_buffer,
    uint32_t rx_buff_size,
    mss_spi_block_rx_handler_t block_rx_handler
)
{
    6a5c:	b580      	push	{r7, lr}
    6a5e:	b088      	sub	sp, #32
    6a60:	af00      	add	r7, sp, #0
    6a62:	60f8      	str	r0, [r7, #12]
    6a64:	60b9      	str	r1, [r7, #8]
    6a66:	607a      	str	r2, [r7, #4]
    6a68:	603b      	str	r3, [r7, #0]
    uint32_t frame_count;
    uint32_t done = 0u;
    6a6a:	f04f 0300 	mov.w	r3, #0
    6a6e:	61fb      	str	r3, [r7, #28]
    
    ASSERT((this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1));
    6a70:	68fa      	ldr	r2, [r7, #12]
    6a72:	f240 23bc 	movw	r3, #700	; 0x2bc
    6a76:	f2c2 0300 	movt	r3, #8192	; 0x2000
    6a7a:	429a      	cmp	r2, r3
    6a7c:	d007      	beq.n	6a8e <MSS_SPI_set_slave_block_buffers+0x32>
    6a7e:	68fa      	ldr	r2, [r7, #12]
    6a80:	f240 2338 	movw	r3, #568	; 0x238
    6a84:	f2c2 0300 	movt	r3, #8192	; 0x2000
    6a88:	429a      	cmp	r2, r3
    6a8a:	d000      	beq.n	6a8e <MSS_SPI_set_slave_block_buffers+0x32>
    6a8c:	be00      	bkpt	0x0000
    
    /* This function is only intended to be used with an SPI slave. */
    ASSERT((this_spi->hw_reg->CONTROL & CTRL_MASTER_MASK) != CTRL_MASTER_MASK);
    6a8e:	68fb      	ldr	r3, [r7, #12]
    6a90:	681b      	ldr	r3, [r3, #0]
    6a92:	681b      	ldr	r3, [r3, #0]
    6a94:	f003 0302 	and.w	r3, r3, #2
    6a98:	2b00      	cmp	r3, #0
    6a9a:	d000      	beq.n	6a9e <MSS_SPI_set_slave_block_buffers+0x42>
    6a9c:	be00      	bkpt	0x0000
    
    /* Shut down interrupts from the MSS SPI while we do this */
    NVIC_DisableIRQ( this_spi->irqn );
    6a9e:	68fb      	ldr	r3, [r7, #12]
    6aa0:	791b      	ldrb	r3, [r3, #4]
    6aa2:	b25b      	sxtb	r3, r3
    6aa4:	4618      	mov	r0, r3
    6aa6:	f7ff fa03 	bl	5eb0 <NVIC_DisableIRQ>

    /* Make sure correct mode is selected */
    this_spi->slave_xfer_mode = MSS_SPI_SLAVE_XFER_BLOCK;
    6aaa:	68fb      	ldr	r3, [r7, #12]
    6aac:	f04f 0201 	mov.w	r2, #1
    6ab0:	f883 2080 	strb.w	r2, [r3, #128]	; 0x80

    /* Set cmd_done correctly to ensure 0 padding works. */
    if(0u == this_spi->cmd_handler)
    6ab4:	68fb      	ldr	r3, [r7, #12]
    6ab6:	6a1b      	ldr	r3, [r3, #32]
    6ab8:	2b00      	cmp	r3, #0
    6aba:	d104      	bne.n	6ac6 <MSS_SPI_set_slave_block_buffers+0x6a>
    {
        this_spi->cmd_done = 1u;
    6abc:	68fb      	ldr	r3, [r7, #12]
    6abe:	f04f 0201 	mov.w	r2, #1
    6ac2:	625a      	str	r2, [r3, #36]	; 0x24
    6ac4:	e003      	b.n	6ace <MSS_SPI_set_slave_block_buffers+0x72>
    }
    else
    {
        this_spi->cmd_done = 0u;
    6ac6:	68fb      	ldr	r3, [r7, #12]
    6ac8:	f04f 0200 	mov.w	r2, #0
    6acc:	625a      	str	r2, [r3, #36]	; 0x24
    }

    /* Disable Rx frame handler as it is mutually exclusive with block rx handler. */
    this_spi->frame_rx_handler = 0u;
    6ace:	68fb      	ldr	r3, [r7, #12]
    6ad0:	f04f 0200 	mov.w	r2, #0
    6ad4:	675a      	str	r2, [r3, #116]	; 0x74
    
    /* Keep a copy of the pointer to the block rx handler function. */
    this_spi->block_rx_handler = block_rx_handler;
    6ad6:	68fb      	ldr	r3, [r7, #12]
    6ad8:	6afa      	ldr	r2, [r7, #44]	; 0x2c
    6ada:	67da      	str	r2, [r3, #124]	; 0x7c
    
    this_spi->slave_rx_buffer = rx_buffer;
    6adc:	68fb      	ldr	r3, [r7, #12]
    6ade:	683a      	ldr	r2, [r7, #0]
    6ae0:	629a      	str	r2, [r3, #40]	; 0x28
    this_spi->slave_rx_size = rx_buff_size;
    6ae2:	68fb      	ldr	r3, [r7, #12]
    6ae4:	6aba      	ldr	r2, [r7, #40]	; 0x28
    6ae6:	62da      	str	r2, [r3, #44]	; 0x2c
    this_spi->slave_rx_idx = 0u;
    6ae8:	68fb      	ldr	r3, [r7, #12]
    6aea:	f04f 0200 	mov.w	r2, #0
    6aee:	631a      	str	r2, [r3, #48]	; 0x30
    
    /* Initialise the transmit state data. */
    this_spi->slave_tx_buffer = tx_buffer;
    6af0:	68fb      	ldr	r3, [r7, #12]
    6af2:	68ba      	ldr	r2, [r7, #8]
    6af4:	609a      	str	r2, [r3, #8]
    this_spi->slave_tx_size = tx_buff_size;
    6af6:	68fb      	ldr	r3, [r7, #12]
    6af8:	687a      	ldr	r2, [r7, #4]
    6afa:	60da      	str	r2, [r3, #12]
    this_spi->slave_tx_idx = 0u;
    6afc:	68fb      	ldr	r3, [r7, #12]
    6afe:	f04f 0200 	mov.w	r2, #0
    6b02:	611a      	str	r2, [r3, #16]

    /* Flush the Tx and Rx FIFOs. Please note this does not have any effect on A2F200. */
    this_spi->hw_reg->COMMAND |= (TX_FIFO_RESET_MASK | RX_FIFO_RESET_MASK);
    6b04:	68fb      	ldr	r3, [r7, #12]
    6b06:	681b      	ldr	r3, [r3, #0]
    6b08:	68fa      	ldr	r2, [r7, #12]
    6b0a:	6812      	ldr	r2, [r2, #0]
    6b0c:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
    6b0e:	f042 020c 	orr.w	r2, r2, #12
    6b12:	62da      	str	r2, [r3, #44]	; 0x2c

    /* Recover from receive overflow if needs be */
    if(0u != (this_spi->hw_reg->STATUS & RX_OVERFLOW_MASK))
    6b14:	68fb      	ldr	r3, [r7, #12]
    6b16:	681b      	ldr	r3, [r3, #0]
    6b18:	689b      	ldr	r3, [r3, #8]
    6b1a:	f003 0304 	and.w	r3, r3, #4
    6b1e:	2b00      	cmp	r3, #0
    6b20:	d00a      	beq.n	6b38 <MSS_SPI_set_slave_block_buffers+0xdc>
    {
         recover_from_rx_overflow(this_spi);
    6b22:	68f8      	ldr	r0, [r7, #12]
    6b24:	f7ff fa9a 	bl	605c <recover_from_rx_overflow>
    }

    /* Flush Rx FIFO in case we are executing on A2F200. */
    while(0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK))
    6b28:	e007      	b.n	6b3a <MSS_SPI_set_slave_block_buffers+0xde>
    {
        volatile uint32_t dummy;
        dummy = this_spi->hw_reg->RX_DATA;
    6b2a:	68fb      	ldr	r3, [r7, #12]
    6b2c:	681b      	ldr	r3, [r3, #0]
    6b2e:	691b      	ldr	r3, [r3, #16]
    6b30:	617b      	str	r3, [r7, #20]
        dummy = dummy;  /* Prevent Lint warning. */
    6b32:	697b      	ldr	r3, [r7, #20]
    6b34:	617b      	str	r3, [r7, #20]
    6b36:	e000      	b.n	6b3a <MSS_SPI_set_slave_block_buffers+0xde>
    {
         recover_from_rx_overflow(this_spi);
    }

    /* Flush Rx FIFO in case we are executing on A2F200. */
    while(0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK))
    6b38:	bf00      	nop
    6b3a:	68fb      	ldr	r3, [r7, #12]
    6b3c:	681b      	ldr	r3, [r3, #0]
    6b3e:	689b      	ldr	r3, [r3, #8]
    6b40:	f003 0340 	and.w	r3, r3, #64	; 0x40
    6b44:	2b00      	cmp	r3, #0
    6b46:	d0f0      	beq.n	6b2a <MSS_SPI_set_slave_block_buffers+0xce>
        dummy = this_spi->hw_reg->RX_DATA;
        dummy = dummy;  /* Prevent Lint warning. */
    }

    /* Use the frame counter to control how often receive interrupts are generated. */
    frame_count = RX_IRQ_THRESHOLD;
    6b48:	f04f 0310 	mov.w	r3, #16
    6b4c:	61bb      	str	r3, [r7, #24]
    
    this_spi->hw_reg->CONTROL &= ~(uint32_t)CTRL_ENABLE_MASK;
    6b4e:	68fb      	ldr	r3, [r7, #12]
    6b50:	681b      	ldr	r3, [r3, #0]
    6b52:	68fa      	ldr	r2, [r7, #12]
    6b54:	6812      	ldr	r2, [r2, #0]
    6b56:	6812      	ldr	r2, [r2, #0]
    6b58:	f022 0201 	bic.w	r2, r2, #1
    6b5c:	601a      	str	r2, [r3, #0]
    this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK) |
    6b5e:	68fb      	ldr	r3, [r7, #12]
    6b60:	681a      	ldr	r2, [r3, #0]
    6b62:	68fb      	ldr	r3, [r7, #12]
    6b64:	681b      	ldr	r3, [r3, #0]
    6b66:	6819      	ldr	r1, [r3, #0]
    6b68:	f240 03ff 	movw	r3, #255	; 0xff
    6b6c:	f6cf 7300 	movt	r3, #65280	; 0xff00
    6b70:	ea01 0303 	and.w	r3, r1, r3
                                (frame_count << TXRXDFCOUNT_SHIFT);
    6b74:	69b9      	ldr	r1, [r7, #24]
    6b76:	ea4f 2101 	mov.w	r1, r1, lsl #8

    /* Use the frame counter to control how often receive interrupts are generated. */
    frame_count = RX_IRQ_THRESHOLD;
    
    this_spi->hw_reg->CONTROL &= ~(uint32_t)CTRL_ENABLE_MASK;
    this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK) |
    6b7a:	ea43 0301 	orr.w	r3, r3, r1
    6b7e:	6013      	str	r3, [r2, #0]
                                (frame_count << TXRXDFCOUNT_SHIFT);
    this_spi->hw_reg->TXRXDF_SIZE = MSS_SPI_BLOCK_TRANSFER_FRAME_SIZE;
    6b80:	68fb      	ldr	r3, [r7, #12]
    6b82:	681b      	ldr	r3, [r3, #0]
    6b84:	f04f 0208 	mov.w	r2, #8
    6b88:	605a      	str	r2, [r3, #4]
    this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK;
    6b8a:	68fb      	ldr	r3, [r7, #12]
    6b8c:	681b      	ldr	r3, [r3, #0]
    6b8e:	68fa      	ldr	r2, [r7, #12]
    6b90:	6812      	ldr	r2, [r2, #0]
    6b92:	6812      	ldr	r2, [r2, #0]
    6b94:	f042 0201 	orr.w	r2, r2, #1
    6b98:	601a      	str	r2, [r3, #0]
    
    /* Load the transmit FIFO. */
    while((0u == (this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK)) && (0u == done))
    6b9a:	e022      	b.n	6be2 <MSS_SPI_set_slave_block_buffers+0x186>
    {
        if(this_spi->slave_tx_idx < this_spi->slave_tx_size)
    6b9c:	68fb      	ldr	r3, [r7, #12]
    6b9e:	691a      	ldr	r2, [r3, #16]
    6ba0:	68fb      	ldr	r3, [r7, #12]
    6ba2:	68db      	ldr	r3, [r3, #12]
    6ba4:	429a      	cmp	r2, r3
    6ba6:	d209      	bcs.n	6bbc <MSS_SPI_set_slave_block_buffers+0x160>
        {
            this_spi->hw_reg->TX_DATA = this_spi->slave_tx_buffer[this_spi->slave_tx_idx];
    6ba8:	68fb      	ldr	r3, [r7, #12]
    6baa:	681b      	ldr	r3, [r3, #0]
    6bac:	68fa      	ldr	r2, [r7, #12]
    6bae:	6891      	ldr	r1, [r2, #8]
    6bb0:	68fa      	ldr	r2, [r7, #12]
    6bb2:	6912      	ldr	r2, [r2, #16]
    6bb4:	440a      	add	r2, r1
    6bb6:	7812      	ldrb	r2, [r2, #0]
    6bb8:	615a      	str	r2, [r3, #20]
    6bba:	e00c      	b.n	6bd6 <MSS_SPI_set_slave_block_buffers+0x17a>
        }
        else if(0u != this_spi->cmd_done)
    6bbc:	68fb      	ldr	r3, [r7, #12]
    6bbe:	6a5b      	ldr	r3, [r3, #36]	; 0x24
    6bc0:	2b00      	cmp	r3, #0
    6bc2:	d005      	beq.n	6bd0 <MSS_SPI_set_slave_block_buffers+0x174>
        {
            /* Fill with 0s if no need to insert command response */
            this_spi->hw_reg->TX_DATA = 0x00u;
    6bc4:	68fb      	ldr	r3, [r7, #12]
    6bc6:	681b      	ldr	r3, [r3, #0]
    6bc8:	f04f 0200 	mov.w	r2, #0
    6bcc:	615a      	str	r2, [r3, #20]
    6bce:	e002      	b.n	6bd6 <MSS_SPI_set_slave_block_buffers+0x17a>
        }
        else
        {
            /* Exit loop early as command response needs to be inserted next */
            done = 1u;
    6bd0:	f04f 0301 	mov.w	r3, #1
    6bd4:	61fb      	str	r3, [r7, #28]
        }
        ++this_spi->slave_tx_idx;
    6bd6:	68fb      	ldr	r3, [r7, #12]
    6bd8:	691b      	ldr	r3, [r3, #16]
    6bda:	f103 0201 	add.w	r2, r3, #1
    6bde:	68fb      	ldr	r3, [r7, #12]
    6be0:	611a      	str	r2, [r3, #16]
                                (frame_count << TXRXDFCOUNT_SHIFT);
    this_spi->hw_reg->TXRXDF_SIZE = MSS_SPI_BLOCK_TRANSFER_FRAME_SIZE;
    this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK;
    
    /* Load the transmit FIFO. */
    while((0u == (this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK)) && (0u == done))
    6be2:	68fb      	ldr	r3, [r7, #12]
    6be4:	681b      	ldr	r3, [r3, #0]
    6be6:	689b      	ldr	r3, [r3, #8]
    6be8:	f403 7380 	and.w	r3, r3, #256	; 0x100
    6bec:	2b00      	cmp	r3, #0
    6bee:	d102      	bne.n	6bf6 <MSS_SPI_set_slave_block_buffers+0x19a>
    6bf0:	69fb      	ldr	r3, [r7, #28]
    6bf2:	2b00      	cmp	r3, #0
    6bf4:	d0d2      	beq.n	6b9c <MSS_SPI_set_slave_block_buffers+0x140>
            done = 1u;
        }
        ++this_spi->slave_tx_idx;
    }

    if(tx_buff_size > 0u)
    6bf6:	687b      	ldr	r3, [r7, #4]
    6bf8:	2b00      	cmp	r3, #0
    6bfa:	d015      	beq.n	6c28 <MSS_SPI_set_slave_block_buffers+0x1cc>
    {
        /* Clear and enable TX interrupt. Also disable autofill */
        this_spi->hw_reg->COMMAND &= ~(uint32_t)AUTOFILL_MASK;
    6bfc:	68fb      	ldr	r3, [r7, #12]
    6bfe:	681b      	ldr	r3, [r3, #0]
    6c00:	68fa      	ldr	r2, [r7, #12]
    6c02:	6812      	ldr	r2, [r2, #0]
    6c04:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
    6c06:	f022 0201 	bic.w	r2, r2, #1
    6c0a:	62da      	str	r2, [r3, #44]	; 0x2c
        this_spi->hw_reg->INT_CLEAR = TXDONE_IRQ_MASK;
    6c0c:	68fb      	ldr	r3, [r7, #12]
    6c0e:	681b      	ldr	r3, [r3, #0]
    6c10:	f04f 0201 	mov.w	r2, #1
    6c14:	60da      	str	r2, [r3, #12]
        this_spi->hw_reg->CONTROL |= CTRL_TX_IRQ_EN_MASK;
    6c16:	68fb      	ldr	r3, [r7, #12]
    6c18:	681b      	ldr	r3, [r3, #0]
    6c1a:	68fa      	ldr	r2, [r7, #12]
    6c1c:	6812      	ldr	r2, [r2, #0]
    6c1e:	6812      	ldr	r2, [r2, #0]
    6c20:	f042 0220 	orr.w	r2, r2, #32
    6c24:	601a      	str	r2, [r3, #0]
    6c26:	e007      	b.n	6c38 <MSS_SPI_set_slave_block_buffers+0x1dc>
    }
    else
    {
        this_spi->hw_reg->COMMAND |= AUTOFILL_MASK;
    6c28:	68fb      	ldr	r3, [r7, #12]
    6c2a:	681b      	ldr	r3, [r3, #0]
    6c2c:	68fa      	ldr	r2, [r7, #12]
    6c2e:	6812      	ldr	r2, [r2, #0]
    6c30:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
    6c32:	f042 0201 	orr.w	r2, r2, #1
    6c36:	62da      	str	r2, [r3, #44]	; 0x2c
    }
    
    /* Ensure command interrupt disabled if no handler */
    if(0u == this_spi->cmd_handler)
    6c38:	68fb      	ldr	r3, [r7, #12]
    6c3a:	6a1b      	ldr	r3, [r3, #32]
    6c3c:	2b00      	cmp	r3, #0
    6c3e:	d107      	bne.n	6c50 <MSS_SPI_set_slave_block_buffers+0x1f4>
    {
        this_spi->hw_reg->CONTROL2 &= ~(uint32_t)C2_ENABLE_CMD_IRQ_MASK;
    6c40:	68fb      	ldr	r3, [r7, #12]
    6c42:	681b      	ldr	r3, [r3, #0]
    6c44:	68fa      	ldr	r2, [r7, #12]
    6c46:	6812      	ldr	r2, [r2, #0]
    6c48:	6a92      	ldr	r2, [r2, #40]	; 0x28
    6c4a:	f022 0210 	bic.w	r2, r2, #16
    6c4e:	629a      	str	r2, [r3, #40]	; 0x28
     * the next transaction.
     *
     * Make sure to clear any pending send ints otherwise we will trigger
     * an immediate interrupt.
     */
    this_spi->hw_reg->INT_CLEAR = SSEND_IRQ_MASK;
    6c50:	68fb      	ldr	r3, [r7, #12]
    6c52:	681b      	ldr	r3, [r3, #0]
    6c54:	f04f 0220 	mov.w	r2, #32
    6c58:	60da      	str	r2, [r3, #12]
    this_spi->hw_reg->CONTROL2 |= C2_ENABLE_SSEND_IRQ_MASK;
    6c5a:	68fb      	ldr	r3, [r7, #12]
    6c5c:	681b      	ldr	r3, [r3, #0]
    6c5e:	68fa      	ldr	r2, [r7, #12]
    6c60:	6812      	ldr	r2, [r2, #0]
    6c62:	6a92      	ldr	r2, [r2, #40]	; 0x28
    6c64:	f042 0220 	orr.w	r2, r2, #32
    6c68:	629a      	str	r2, [r3, #40]	; 0x28
    
    /* Clear down ints to avoid stale ints triggering when we enable them below */
    this_spi->hw_reg->INT_CLEAR = TXURUN_IRQ_MASK | RXOVFLOW_IRQ_MASK |
    6c6a:	68fb      	ldr	r3, [r7, #12]
    6c6c:	681b      	ldr	r3, [r3, #0]
    6c6e:	f04f 020e 	mov.w	r2, #14
    6c72:	60da      	str	r2, [r3, #12]
                                  RXDONE_IRQ_MASK;
    /*
     * Enable TX underrun and RX overflow interrupts to improve error
     * recovery and enable Rx interrupt.
     */
    this_spi->hw_reg->CONTROL |= CTRL_RX_IRQ_EN_MASK | CTRL_URUN_IRQ_EN_MASK |
    6c74:	68fb      	ldr	r3, [r7, #12]
    6c76:	681b      	ldr	r3, [r3, #0]
    6c78:	68fa      	ldr	r2, [r7, #12]
    6c7a:	6812      	ldr	r2, [r2, #0]
    6c7c:	6812      	ldr	r2, [r2, #0]
    6c7e:	f042 02d0 	orr.w	r2, r2, #208	; 0xd0
    6c82:	601a      	str	r2, [r3, #0]
                                 CTRL_OVFLOW_IRQ_EN_MASK;

    NVIC_EnableIRQ(this_spi->irqn);
    6c84:	68fb      	ldr	r3, [r7, #12]
    6c86:	791b      	ldrb	r3, [r3, #4]
    6c88:	b25b      	sxtb	r3, r3
    6c8a:	4618      	mov	r0, r3
    6c8c:	f7ff f8f4 	bl	5e78 <NVIC_EnableIRQ>
}
    6c90:	f107 0720 	add.w	r7, r7, #32
    6c94:	46bd      	mov	sp, r7
    6c96:	bd80      	pop	{r7, pc}

00006c98 <MSS_SPI_set_cmd_handler>:
(
    mss_spi_instance_t * this_spi,
    mss_spi_block_rx_handler_t cmd_handler,
    uint32_t cmd_size
)
{
    6c98:	b580      	push	{r7, lr}
    6c9a:	b084      	sub	sp, #16
    6c9c:	af00      	add	r7, sp, #0
    6c9e:	60f8      	str	r0, [r7, #12]
    6ca0:	60b9      	str	r1, [r7, #8]
    6ca2:	607a      	str	r2, [r7, #4]
    /* Shut down interrupts from the MSS SPI while we do this */
    NVIC_DisableIRQ( this_spi->irqn );
    6ca4:	68fb      	ldr	r3, [r7, #12]
    6ca6:	791b      	ldrb	r3, [r3, #4]
    6ca8:	b25b      	sxtb	r3, r3
    6caa:	4618      	mov	r0, r3
    6cac:	f7ff f900 	bl	5eb0 <NVIC_DisableIRQ>

    /* Make sure response state is cleared down */
    this_spi->resp_tx_buffer   = 0u;
    6cb0:	68fb      	ldr	r3, [r7, #12]
    6cb2:	f04f 0200 	mov.w	r2, #0
    6cb6:	615a      	str	r2, [r3, #20]
    this_spi->resp_buff_size   = 0u;
    6cb8:	68fb      	ldr	r3, [r7, #12]
    6cba:	f04f 0200 	mov.w	r2, #0
    6cbe:	619a      	str	r2, [r3, #24]
    this_spi->resp_buff_tx_idx = 0u;
    6cc0:	68fb      	ldr	r3, [r7, #12]
    6cc2:	f04f 0200 	mov.w	r2, #0
    6cc6:	61da      	str	r2, [r3, #28]
    
    if(0u == cmd_handler)
    6cc8:	68bb      	ldr	r3, [r7, #8]
    6cca:	2b00      	cmp	r3, #0
    6ccc:	d115      	bne.n	6cfa <MSS_SPI_set_cmd_handler+0x62>
    {
        /*
         * Set this flag so zero padding is enabled
         */
        this_spi->cmd_done = 1u;
    6cce:	68fb      	ldr	r3, [r7, #12]
    6cd0:	f04f 0201 	mov.w	r2, #1
    6cd4:	625a      	str	r2, [r3, #36]	; 0x24
        /*
         * Ensure command interrupt disabled if no handler 
         * and handler pointer is wiped clean.
         */
        this_spi->cmd_handler = 0u;
    6cd6:	68fb      	ldr	r3, [r7, #12]
    6cd8:	f04f 0200 	mov.w	r2, #0
    6cdc:	621a      	str	r2, [r3, #32]
        this_spi->hw_reg->CMDSIZE = 0u;
    6cde:	68fb      	ldr	r3, [r7, #12]
    6ce0:	681b      	ldr	r3, [r3, #0]
    6ce2:	f04f 0200 	mov.w	r2, #0
    6ce6:	635a      	str	r2, [r3, #52]	; 0x34
        this_spi->hw_reg->CONTROL2 &= ~(uint32_t)C2_ENABLE_CMD_IRQ_MASK;
    6ce8:	68fb      	ldr	r3, [r7, #12]
    6cea:	681b      	ldr	r3, [r3, #0]
    6cec:	68fa      	ldr	r2, [r7, #12]
    6cee:	6812      	ldr	r2, [r2, #0]
    6cf0:	6a92      	ldr	r2, [r2, #40]	; 0x28
    6cf2:	f022 0210 	bic.w	r2, r2, #16
    6cf6:	629a      	str	r2, [r3, #40]	; 0x28
    6cf8:	e026      	b.n	6d48 <MSS_SPI_set_cmd_handler+0xb0>
    {
        /*
         * Clear this flag so zero padding is disabled until command response
         * has been taken care of.
         */
        this_spi->cmd_done = 0u;
    6cfa:	68fb      	ldr	r3, [r7, #12]
    6cfc:	f04f 0200 	mov.w	r2, #0
    6d00:	625a      	str	r2, [r3, #36]	; 0x24

        this_spi->cmd_handler = cmd_handler;
    6d02:	68fb      	ldr	r3, [r7, #12]
    6d04:	68ba      	ldr	r2, [r7, #8]
    6d06:	621a      	str	r2, [r3, #32]
        this_spi->hw_reg->CMDSIZE = cmd_size;
    6d08:	68fb      	ldr	r3, [r7, #12]
    6d0a:	681b      	ldr	r3, [r3, #0]
    6d0c:	687a      	ldr	r2, [r7, #4]
    6d0e:	635a      	str	r2, [r3, #52]	; 0x34
        /* Flush the Tx FIFO. Please note this does not have any effect on A2F200. */
        this_spi->hw_reg->COMMAND |= (TX_FIFO_RESET_MASK | RX_FIFO_RESET_MASK);
    6d10:	68fb      	ldr	r3, [r7, #12]
    6d12:	681b      	ldr	r3, [r3, #0]
    6d14:	68fa      	ldr	r2, [r7, #12]
    6d16:	6812      	ldr	r2, [r2, #0]
    6d18:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
    6d1a:	f042 020c 	orr.w	r2, r2, #12
    6d1e:	62da      	str	r2, [r3, #44]	; 0x2c
        /*
         * Reload TX FIFO as MSS_SPI_set_slave_block_buffers() may have zero filled
         * the FIFO if command handler was not in place when it was called and so 
         * the first frame sent could be wrong.
         */
        this_spi->slave_tx_idx    = 0u;
    6d20:	68fb      	ldr	r3, [r7, #12]
    6d22:	f04f 0200 	mov.w	r2, #0
    6d26:	611a      	str	r2, [r3, #16]
        fill_slave_tx_fifo(this_spi);
    6d28:	68f8      	ldr	r0, [r7, #12]
    6d2a:	f000 f8bf 	bl	6eac <fill_slave_tx_fifo>
        /*
         * Make sure to clear any pending command ints otherwise we will trigger
         * an immediate interrupt.
         */
        this_spi->hw_reg->INT_CLEAR = CMD_IRQ_MASK;
    6d2e:	68fb      	ldr	r3, [r7, #12]
    6d30:	681b      	ldr	r3, [r3, #0]
    6d32:	f04f 0210 	mov.w	r2, #16
    6d36:	60da      	str	r2, [r3, #12]
        this_spi->hw_reg->CONTROL2 |= C2_ENABLE_CMD_IRQ_MASK;
    6d38:	68fb      	ldr	r3, [r7, #12]
    6d3a:	681b      	ldr	r3, [r3, #0]
    6d3c:	68fa      	ldr	r2, [r7, #12]
    6d3e:	6812      	ldr	r2, [r2, #0]
    6d40:	6a92      	ldr	r2, [r2, #40]	; 0x28
    6d42:	f042 0210 	orr.w	r2, r2, #16
    6d46:	629a      	str	r2, [r3, #40]	; 0x28
    }
    
    NVIC_EnableIRQ(this_spi->irqn); /* Safe to allow interrupts again */
    6d48:	68fb      	ldr	r3, [r7, #12]
    6d4a:	791b      	ldrb	r3, [r3, #4]
    6d4c:	b25b      	sxtb	r3, r3
    6d4e:	4618      	mov	r0, r3
    6d50:	f7ff f892 	bl	5e78 <NVIC_EnableIRQ>
}
    6d54:	f107 0710 	add.w	r7, r7, #16
    6d58:	46bd      	mov	sp, r7
    6d5a:	bd80      	pop	{r7, pc}

00006d5c <MSS_SPI_set_cmd_response>:
(
    mss_spi_instance_t * this_spi,
    const uint8_t * resp_tx_buffer,
    uint32_t resp_buff_size
)
{
    6d5c:	b580      	push	{r7, lr}
    6d5e:	b084      	sub	sp, #16
    6d60:	af00      	add	r7, sp, #0
    6d62:	60f8      	str	r0, [r7, #12]
    6d64:	60b9      	str	r1, [r7, #8]
    6d66:	607a      	str	r2, [r7, #4]
    this_spi->resp_tx_buffer = resp_tx_buffer;
    6d68:	68fb      	ldr	r3, [r7, #12]
    6d6a:	68ba      	ldr	r2, [r7, #8]
    6d6c:	615a      	str	r2, [r3, #20]
    this_spi->resp_buff_size = resp_buff_size;
    6d6e:	68fb      	ldr	r3, [r7, #12]
    6d70:	687a      	ldr	r2, [r7, #4]
    6d72:	619a      	str	r2, [r3, #24]
    this_spi->resp_buff_tx_idx = 0u;
    6d74:	68fb      	ldr	r3, [r7, #12]
    6d76:	f04f 0200 	mov.w	r2, #0
    6d7a:	61da      	str	r2, [r3, #28]
    /* Note that we have provided response and start getting it into the FIFO */
    this_spi->cmd_done = 1u;
    6d7c:	68fb      	ldr	r3, [r7, #12]
    6d7e:	f04f 0201 	mov.w	r2, #1
    6d82:	625a      	str	r2, [r3, #36]	; 0x24
    fill_slave_tx_fifo(this_spi);
    6d84:	68f8      	ldr	r0, [r7, #12]
    6d86:	f000 f891 	bl	6eac <fill_slave_tx_fifo>
}
    6d8a:	f107 0710 	add.w	r7, r7, #16
    6d8e:	46bd      	mov	sp, r7
    6d90:	bd80      	pop	{r7, pc}
    6d92:	bf00      	nop

00006d94 <MSS_SPI_enable>:
 */
void MSS_SPI_enable
(
    mss_spi_instance_t * this_spi
)
{
    6d94:	b580      	push	{r7, lr}
    6d96:	b082      	sub	sp, #8
    6d98:	af00      	add	r7, sp, #0
    6d9a:	6078      	str	r0, [r7, #4]
    /* Shut down interrupts from the MSS SPI while we do this */
    NVIC_DisableIRQ( this_spi->irqn );
    6d9c:	687b      	ldr	r3, [r7, #4]
    6d9e:	791b      	ldrb	r3, [r3, #4]
    6da0:	b25b      	sxtb	r3, r3
    6da2:	4618      	mov	r0, r3
    6da4:	f7ff f884 	bl	5eb0 <NVIC_DisableIRQ>

    this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK;
    6da8:	687b      	ldr	r3, [r7, #4]
    6daa:	681b      	ldr	r3, [r3, #0]
    6dac:	687a      	ldr	r2, [r7, #4]
    6dae:	6812      	ldr	r2, [r2, #0]
    6db0:	6812      	ldr	r2, [r2, #0]
    6db2:	f042 0201 	orr.w	r2, r2, #1
    6db6:	601a      	str	r2, [r3, #0]
    
    /* Reenable interrupts */
    NVIC_EnableIRQ( this_spi->irqn );
    6db8:	687b      	ldr	r3, [r7, #4]
    6dba:	791b      	ldrb	r3, [r3, #4]
    6dbc:	b25b      	sxtb	r3, r3
    6dbe:	4618      	mov	r0, r3
    6dc0:	f7ff f85a 	bl	5e78 <NVIC_EnableIRQ>
}
    6dc4:	f107 0708 	add.w	r7, r7, #8
    6dc8:	46bd      	mov	sp, r7
    6dca:	bd80      	pop	{r7, pc}

00006dcc <MSS_SPI_disable>:
 */
void MSS_SPI_disable
(
    mss_spi_instance_t * this_spi
)
{
    6dcc:	b580      	push	{r7, lr}
    6dce:	b082      	sub	sp, #8
    6dd0:	af00      	add	r7, sp, #0
    6dd2:	6078      	str	r0, [r7, #4]
    /* Shut down interrupts from the MSS SPI while we do this */
    NVIC_DisableIRQ( this_spi->irqn );
    6dd4:	687b      	ldr	r3, [r7, #4]
    6dd6:	791b      	ldrb	r3, [r3, #4]
    6dd8:	b25b      	sxtb	r3, r3
    6dda:	4618      	mov	r0, r3
    6ddc:	f7ff f868 	bl	5eb0 <NVIC_DisableIRQ>

    this_spi->hw_reg->CONTROL &= ~(uint32_t)CTRL_ENABLE_MASK;
    6de0:	687b      	ldr	r3, [r7, #4]
    6de2:	681b      	ldr	r3, [r3, #0]
    6de4:	687a      	ldr	r2, [r7, #4]
    6de6:	6812      	ldr	r2, [r2, #0]
    6de8:	6812      	ldr	r2, [r2, #0]
    6dea:	f022 0201 	bic.w	r2, r2, #1
    6dee:	601a      	str	r2, [r3, #0]

    /* Reenable interrupts */
    NVIC_EnableIRQ( this_spi->irqn );
    6df0:	687b      	ldr	r3, [r7, #4]
    6df2:	791b      	ldrb	r3, [r3, #4]
    6df4:	b25b      	sxtb	r3, r3
    6df6:	4618      	mov	r0, r3
    6df8:	f7ff f83e 	bl	5e78 <NVIC_EnableIRQ>
}
    6dfc:	f107 0708 	add.w	r7, r7, #8
    6e00:	46bd      	mov	sp, r7
    6e02:	bd80      	pop	{r7, pc}

00006e04 <MSS_SPI_set_transfer_byte_count>:
void MSS_SPI_set_transfer_byte_count
(
    mss_spi_instance_t * this_spi,
    uint16_t byte_count
)
{
    6e04:	b580      	push	{r7, lr}
    6e06:	b082      	sub	sp, #8
    6e08:	af00      	add	r7, sp, #0
    6e0a:	6078      	str	r0, [r7, #4]
    6e0c:	460b      	mov	r3, r1
    6e0e:	807b      	strh	r3, [r7, #2]
    /* Shut down interrupts from the MSS SPI while we do this */
    NVIC_DisableIRQ( this_spi->irqn );
    6e10:	687b      	ldr	r3, [r7, #4]
    6e12:	791b      	ldrb	r3, [r3, #4]
    6e14:	b25b      	sxtb	r3, r3
    6e16:	4618      	mov	r0, r3
    6e18:	f7ff f84a 	bl	5eb0 <NVIC_DisableIRQ>

    this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK)
    6e1c:	687b      	ldr	r3, [r7, #4]
    6e1e:	6819      	ldr	r1, [r3, #0]
    6e20:	687b      	ldr	r3, [r7, #4]
    6e22:	681b      	ldr	r3, [r3, #0]
    6e24:	681b      	ldr	r3, [r3, #0]
    6e26:	f240 02ff 	movw	r2, #255	; 0xff
    6e2a:	f6cf 7200 	movt	r2, #65280	; 0xff00
    6e2e:	ea03 0202 	and.w	r2, r3, r2
                                | (((uint32_t)byte_count << TXRXDFCOUNT_SHIFT) & TXRXDFCOUNT_MASK);
    6e32:	887b      	ldrh	r3, [r7, #2]
    6e34:	ea4f 2003 	mov.w	r0, r3, lsl #8
    6e38:	f64f 7300 	movw	r3, #65280	; 0xff00
    6e3c:	f2c0 03ff 	movt	r3, #255	; 0xff
    6e40:	ea00 0303 	and.w	r3, r0, r3
)
{
    /* Shut down interrupts from the MSS SPI while we do this */
    NVIC_DisableIRQ( this_spi->irqn );

    this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK)
    6e44:	ea42 0303 	orr.w	r3, r2, r3
    6e48:	600b      	str	r3, [r1, #0]
                                | (((uint32_t)byte_count << TXRXDFCOUNT_SHIFT) & TXRXDFCOUNT_MASK);
                                
    /* This value can only be updated when the MSS SPI is disabled */
    this_spi->hw_reg->CONTROL &= ~(uint32_t)CTRL_ENABLE_MASK;
    6e4a:	687b      	ldr	r3, [r7, #4]
    6e4c:	681b      	ldr	r3, [r3, #0]
    6e4e:	687a      	ldr	r2, [r7, #4]
    6e50:	6812      	ldr	r2, [r2, #0]
    6e52:	6812      	ldr	r2, [r2, #0]
    6e54:	f022 0201 	bic.w	r2, r2, #1
    6e58:	601a      	str	r2, [r3, #0]
    this_spi->hw_reg->TXRXDF_SIZE = MSS_SPI_BLOCK_TRANSFER_FRAME_SIZE;
    6e5a:	687b      	ldr	r3, [r7, #4]
    6e5c:	681b      	ldr	r3, [r3, #0]
    6e5e:	f04f 0208 	mov.w	r2, #8
    6e62:	605a      	str	r2, [r3, #4]
    this_spi->hw_reg->CONTROL |= CTRL_ENABLE_MASK;
    6e64:	687b      	ldr	r3, [r7, #4]
    6e66:	681b      	ldr	r3, [r3, #0]
    6e68:	687a      	ldr	r2, [r7, #4]
    6e6a:	6812      	ldr	r2, [r2, #0]
    6e6c:	6812      	ldr	r2, [r2, #0]
    6e6e:	f042 0201 	orr.w	r2, r2, #1
    6e72:	601a      	str	r2, [r3, #0]
    /* Reenable interrupts */
    NVIC_EnableIRQ( this_spi->irqn );
    6e74:	687b      	ldr	r3, [r7, #4]
    6e76:	791b      	ldrb	r3, [r3, #4]
    6e78:	b25b      	sxtb	r3, r3
    6e7a:	4618      	mov	r0, r3
    6e7c:	f7fe fffc 	bl	5e78 <NVIC_EnableIRQ>
}
    6e80:	f107 0708 	add.w	r7, r7, #8
    6e84:	46bd      	mov	sp, r7
    6e86:	bd80      	pop	{r7, pc}

00006e88 <MSS_SPI_tx_done>:
 */
uint32_t MSS_SPI_tx_done
(
    mss_spi_instance_t * this_spi
)
{
    6e88:	b480      	push	{r7}
    6e8a:	b085      	sub	sp, #20
    6e8c:	af00      	add	r7, sp, #0
    6e8e:	6078      	str	r0, [r7, #4]
    uint32_t tx_done;
    
    tx_done = this_spi->hw_reg->STATUS & TX_DONE_MASK;
    6e90:	687b      	ldr	r3, [r7, #4]
    6e92:	681b      	ldr	r3, [r3, #0]
    6e94:	689b      	ldr	r3, [r3, #8]
    6e96:	f003 0301 	and.w	r3, r3, #1
    6e9a:	60fb      	str	r3, [r7, #12]
    
    return tx_done;
    6e9c:	68fb      	ldr	r3, [r7, #12]
}
    6e9e:	4618      	mov	r0, r3
    6ea0:	f107 0714 	add.w	r7, r7, #20
    6ea4:	46bd      	mov	sp, r7
    6ea6:	bc80      	pop	{r7}
    6ea8:	4770      	bx	lr
    6eaa:	bf00      	nop

00006eac <fill_slave_tx_fifo>:
 */
static void fill_slave_tx_fifo
(
    mss_spi_instance_t * this_spi
)
{
    6eac:	b480      	push	{r7}
    6eae:	b085      	sub	sp, #20
    6eb0:	af00      	add	r7, sp, #0
    6eb2:	6078      	str	r0, [r7, #4]
    uint32_t guard = 0u;
    6eb4:	f04f 0300 	mov.w	r3, #0
    6eb8:	60fb      	str	r3, [r7, #12]

    while((0u == (this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK)) &&
    6eba:	e00e      	b.n	6eda <fill_slave_tx_fifo+0x2e>
          (this_spi->slave_tx_idx < this_spi->slave_tx_size))
    {
        /* Sending from primary slave transmit buffer */
        this_spi->hw_reg->TX_DATA = this_spi->slave_tx_buffer[this_spi->slave_tx_idx];
    6ebc:	687b      	ldr	r3, [r7, #4]
    6ebe:	681b      	ldr	r3, [r3, #0]
    6ec0:	687a      	ldr	r2, [r7, #4]
    6ec2:	6891      	ldr	r1, [r2, #8]
    6ec4:	687a      	ldr	r2, [r7, #4]
    6ec6:	6912      	ldr	r2, [r2, #16]
    6ec8:	440a      	add	r2, r1
    6eca:	7812      	ldrb	r2, [r2, #0]
    6ecc:	615a      	str	r2, [r3, #20]
        ++this_spi->slave_tx_idx;
    6ece:	687b      	ldr	r3, [r7, #4]
    6ed0:	691b      	ldr	r3, [r3, #16]
    6ed2:	f103 0201 	add.w	r2, r3, #1
    6ed6:	687b      	ldr	r3, [r7, #4]
    6ed8:	611a      	str	r2, [r3, #16]
    mss_spi_instance_t * this_spi
)
{
    uint32_t guard = 0u;

    while((0u == (this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK)) &&
    6eda:	687b      	ldr	r3, [r7, #4]
    6edc:	681b      	ldr	r3, [r3, #0]
    6ede:	689b      	ldr	r3, [r3, #8]
    6ee0:	f403 7380 	and.w	r3, r3, #256	; 0x100
    6ee4:	2b00      	cmp	r3, #0
    6ee6:	d105      	bne.n	6ef4 <fill_slave_tx_fifo+0x48>
          (this_spi->slave_tx_idx < this_spi->slave_tx_size))
    6ee8:	687b      	ldr	r3, [r7, #4]
    6eea:	691a      	ldr	r2, [r3, #16]
    6eec:	687b      	ldr	r3, [r7, #4]
    6eee:	68db      	ldr	r3, [r3, #12]
    mss_spi_instance_t * this_spi
)
{
    uint32_t guard = 0u;

    while((0u == (this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK)) &&
    6ef0:	429a      	cmp	r2, r3
    6ef2:	d3e3      	bcc.n	6ebc <fill_slave_tx_fifo+0x10>
        /* Sending from primary slave transmit buffer */
        this_spi->hw_reg->TX_DATA = this_spi->slave_tx_buffer[this_spi->slave_tx_idx];
        ++this_spi->slave_tx_idx;
    }

    if(this_spi->slave_tx_idx >= this_spi->slave_tx_size)
    6ef4:	687b      	ldr	r3, [r7, #4]
    6ef6:	691a      	ldr	r2, [r3, #16]
    6ef8:	687b      	ldr	r3, [r7, #4]
    6efa:	68db      	ldr	r3, [r3, #12]
    6efc:	429a      	cmp	r2, r3
    6efe:	d31c      	bcc.n	6f3a <fill_slave_tx_fifo+0x8e>
    {
        while((0u == (this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK)) &&
    6f00:	e00e      	b.n	6f20 <fill_slave_tx_fifo+0x74>
              (this_spi->resp_buff_tx_idx < this_spi->resp_buff_size))
        {
            /* Sending from command response buffer */
            this_spi->hw_reg->TX_DATA = this_spi->resp_tx_buffer[this_spi->resp_buff_tx_idx];
    6f02:	687b      	ldr	r3, [r7, #4]
    6f04:	681b      	ldr	r3, [r3, #0]
    6f06:	687a      	ldr	r2, [r7, #4]
    6f08:	6951      	ldr	r1, [r2, #20]
    6f0a:	687a      	ldr	r2, [r7, #4]
    6f0c:	69d2      	ldr	r2, [r2, #28]
    6f0e:	440a      	add	r2, r1
    6f10:	7812      	ldrb	r2, [r2, #0]
    6f12:	615a      	str	r2, [r3, #20]
            ++this_spi->resp_buff_tx_idx;
    6f14:	687b      	ldr	r3, [r7, #4]
    6f16:	69db      	ldr	r3, [r3, #28]
    6f18:	f103 0201 	add.w	r2, r3, #1
    6f1c:	687b      	ldr	r3, [r7, #4]
    6f1e:	61da      	str	r2, [r3, #28]
        ++this_spi->slave_tx_idx;
    }

    if(this_spi->slave_tx_idx >= this_spi->slave_tx_size)
    {
        while((0u == (this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK)) &&
    6f20:	687b      	ldr	r3, [r7, #4]
    6f22:	681b      	ldr	r3, [r3, #0]
    6f24:	689b      	ldr	r3, [r3, #8]
    6f26:	f403 7380 	and.w	r3, r3, #256	; 0x100
    6f2a:	2b00      	cmp	r3, #0
    6f2c:	d105      	bne.n	6f3a <fill_slave_tx_fifo+0x8e>
              (this_spi->resp_buff_tx_idx < this_spi->resp_buff_size))
    6f2e:	687b      	ldr	r3, [r7, #4]
    6f30:	69da      	ldr	r2, [r3, #28]
    6f32:	687b      	ldr	r3, [r7, #4]
    6f34:	699b      	ldr	r3, [r3, #24]
        ++this_spi->slave_tx_idx;
    }

    if(this_spi->slave_tx_idx >= this_spi->slave_tx_size)
    {
        while((0u == (this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK)) &&
    6f36:	429a      	cmp	r2, r3
    6f38:	d3e3      	bcc.n	6f02 <fill_slave_tx_fifo+0x56>
            this_spi->hw_reg->TX_DATA = this_spi->resp_tx_buffer[this_spi->resp_buff_tx_idx];
            ++this_spi->resp_buff_tx_idx;
        }
    }

    if((0u != this_spi->cmd_done) && (this_spi->slave_tx_idx >= this_spi->slave_tx_size) &&
    6f3a:	687b      	ldr	r3, [r7, #4]
    6f3c:	6a5b      	ldr	r3, [r3, #36]	; 0x24
    6f3e:	2b00      	cmp	r3, #0
    6f40:	d01f      	beq.n	6f82 <fill_slave_tx_fifo+0xd6>
    6f42:	687b      	ldr	r3, [r7, #4]
    6f44:	691a      	ldr	r2, [r3, #16]
    6f46:	687b      	ldr	r3, [r7, #4]
    6f48:	68db      	ldr	r3, [r3, #12]
    6f4a:	429a      	cmp	r2, r3
    6f4c:	d319      	bcc.n	6f82 <fill_slave_tx_fifo+0xd6>
       (this_spi->resp_buff_tx_idx >= this_spi->resp_buff_size))
    6f4e:	687b      	ldr	r3, [r7, #4]
    6f50:	69da      	ldr	r2, [r3, #28]
    6f52:	687b      	ldr	r3, [r7, #4]
    6f54:	699b      	ldr	r3, [r3, #24]
            this_spi->hw_reg->TX_DATA = this_spi->resp_tx_buffer[this_spi->resp_buff_tx_idx];
            ++this_spi->resp_buff_tx_idx;
        }
    }

    if((0u != this_spi->cmd_done) && (this_spi->slave_tx_idx >= this_spi->slave_tx_size) &&
    6f56:	429a      	cmp	r2, r3
    6f58:	d313      	bcc.n	6f82 <fill_slave_tx_fifo+0xd6>
       (this_spi->resp_buff_tx_idx >= this_spi->resp_buff_size))
    {
        while((0u == (this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK)) &&
    6f5a:	e008      	b.n	6f6e <fill_slave_tx_fifo+0xc2>
              (guard < BIG_FIFO_SIZE))
        {
            /* Nothing left so pad with 0s for consistency */
            this_spi->hw_reg->TX_DATA = 0x00u;
    6f5c:	687b      	ldr	r3, [r7, #4]
    6f5e:	681b      	ldr	r3, [r3, #0]
    6f60:	f04f 0200 	mov.w	r2, #0
    6f64:	615a      	str	r2, [r3, #20]
             * We use the guard count to cover the unlikely event that we are
             * never seeing the TX FIFO full because the data is being pulled
             * out as fast as we can stuff it in. In this event we never spend
             * more than a full FIFOs worth of time spinning here.
             */
            guard++;
    6f66:	68fb      	ldr	r3, [r7, #12]
    6f68:	f103 0301 	add.w	r3, r3, #1
    6f6c:	60fb      	str	r3, [r7, #12]
    }

    if((0u != this_spi->cmd_done) && (this_spi->slave_tx_idx >= this_spi->slave_tx_size) &&
       (this_spi->resp_buff_tx_idx >= this_spi->resp_buff_size))
    {
        while((0u == (this_spi->hw_reg->STATUS & TX_FIFO_FULL_MASK)) &&
    6f6e:	687b      	ldr	r3, [r7, #4]
    6f70:	681b      	ldr	r3, [r3, #0]
    6f72:	689b      	ldr	r3, [r3, #8]
    6f74:	f403 7380 	and.w	r3, r3, #256	; 0x100
    6f78:	2b00      	cmp	r3, #0
    6f7a:	d102      	bne.n	6f82 <fill_slave_tx_fifo+0xd6>
    6f7c:	68fb      	ldr	r3, [r7, #12]
    6f7e:	2b1f      	cmp	r3, #31
    6f80:	d9ec      	bls.n	6f5c <fill_slave_tx_fifo+0xb0>
             */
            guard++;
        }
    }

}
    6f82:	f107 0714 	add.w	r7, r7, #20
    6f86:	46bd      	mov	sp, r7
    6f88:	bc80      	pop	{r7}
    6f8a:	4770      	bx	lr

00006f8c <read_slave_rx_fifo>:
 */
static void read_slave_rx_fifo
(
    mss_spi_instance_t * this_spi
)
{
    6f8c:	b580      	push	{r7, lr}
    6f8e:	b084      	sub	sp, #16
    6f90:	af00      	add	r7, sp, #0
    6f92:	6078      	str	r0, [r7, #4]
    volatile uint32_t rx_frame;
    
    if(MSS_SPI_SLAVE_XFER_FRAME == this_spi->slave_xfer_mode)
    6f94:	687b      	ldr	r3, [r7, #4]
    6f96:	f893 3080 	ldrb.w	r3, [r3, #128]	; 0x80
    6f9a:	2b02      	cmp	r3, #2
    6f9c:	d115      	bne.n	6fca <read_slave_rx_fifo+0x3e>
    {
        while(0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK))
    6f9e:	e00c      	b.n	6fba <read_slave_rx_fifo+0x2e>
        {
            /* Single frame handling mode. */
            rx_frame = this_spi->hw_reg->RX_DATA;
    6fa0:	687b      	ldr	r3, [r7, #4]
    6fa2:	681b      	ldr	r3, [r3, #0]
    6fa4:	691b      	ldr	r3, [r3, #16]
    6fa6:	60fb      	str	r3, [r7, #12]
            if(0u != this_spi->frame_rx_handler)
    6fa8:	687b      	ldr	r3, [r7, #4]
    6faa:	6f5b      	ldr	r3, [r3, #116]	; 0x74
    6fac:	2b00      	cmp	r3, #0
    6fae:	d004      	beq.n	6fba <read_slave_rx_fifo+0x2e>
            {
                this_spi->frame_rx_handler( rx_frame );
    6fb0:	687b      	ldr	r3, [r7, #4]
    6fb2:	6f5b      	ldr	r3, [r3, #116]	; 0x74
    6fb4:	68fa      	ldr	r2, [r7, #12]
    6fb6:	4610      	mov	r0, r2
    6fb8:	4798      	blx	r3
{
    volatile uint32_t rx_frame;
    
    if(MSS_SPI_SLAVE_XFER_FRAME == this_spi->slave_xfer_mode)
    {
        while(0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK))
    6fba:	687b      	ldr	r3, [r7, #4]
    6fbc:	681b      	ldr	r3, [r3, #0]
    6fbe:	689b      	ldr	r3, [r3, #8]
    6fc0:	f003 0340 	and.w	r3, r3, #64	; 0x40
    6fc4:	2b00      	cmp	r3, #0
    6fc6:	d0eb      	beq.n	6fa0 <read_slave_rx_fifo+0x14>
    6fc8:	e032      	b.n	7030 <read_slave_rx_fifo+0xa4>
            {
                this_spi->frame_rx_handler( rx_frame );
            }
        }
    }
    else if(MSS_SPI_SLAVE_XFER_BLOCK == this_spi->slave_xfer_mode)
    6fca:	687b      	ldr	r3, [r7, #4]
    6fcc:	f893 3080 	ldrb.w	r3, [r3, #128]	; 0x80
    6fd0:	2b01      	cmp	r3, #1
    6fd2:	d125      	bne.n	7020 <read_slave_rx_fifo+0x94>
    {
        /* Block handling mode. */
        while(0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK)) /* Something needs to be read from FIFO */
    6fd4:	e017      	b.n	7006 <read_slave_rx_fifo+0x7a>
        {
            rx_frame = this_spi->hw_reg->RX_DATA;
    6fd6:	687b      	ldr	r3, [r7, #4]
    6fd8:	681b      	ldr	r3, [r3, #0]
    6fda:	691b      	ldr	r3, [r3, #16]
    6fdc:	60fb      	str	r3, [r7, #12]
            if(this_spi->slave_rx_idx < this_spi->slave_rx_size)
    6fde:	687b      	ldr	r3, [r7, #4]
    6fe0:	6b1a      	ldr	r2, [r3, #48]	; 0x30
    6fe2:	687b      	ldr	r3, [r7, #4]
    6fe4:	6adb      	ldr	r3, [r3, #44]	; 0x2c
    6fe6:	429a      	cmp	r2, r3
    6fe8:	d207      	bcs.n	6ffa <read_slave_rx_fifo+0x6e>
            {
                this_spi->slave_rx_buffer[this_spi->slave_rx_idx] = (uint8_t)rx_frame;
    6fea:	687b      	ldr	r3, [r7, #4]
    6fec:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    6fee:	687b      	ldr	r3, [r7, #4]
    6ff0:	6b1b      	ldr	r3, [r3, #48]	; 0x30
    6ff2:	4413      	add	r3, r2
    6ff4:	68fa      	ldr	r2, [r7, #12]
    6ff6:	b2d2      	uxtb	r2, r2
    6ff8:	701a      	strb	r2, [r3, #0]
            }

            ++this_spi->slave_rx_idx;
    6ffa:	687b      	ldr	r3, [r7, #4]
    6ffc:	6b1b      	ldr	r3, [r3, #48]	; 0x30
    6ffe:	f103 0201 	add.w	r2, r3, #1
    7002:	687b      	ldr	r3, [r7, #4]
    7004:	631a      	str	r2, [r3, #48]	; 0x30
        }
    }
    else if(MSS_SPI_SLAVE_XFER_BLOCK == this_spi->slave_xfer_mode)
    {
        /* Block handling mode. */
        while(0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK)) /* Something needs to be read from FIFO */
    7006:	687b      	ldr	r3, [r7, #4]
    7008:	681b      	ldr	r3, [r3, #0]
    700a:	689b      	ldr	r3, [r3, #8]
    700c:	f003 0340 	and.w	r3, r3, #64	; 0x40
    7010:	2b00      	cmp	r3, #0
    7012:	d0e0      	beq.n	6fd6 <read_slave_rx_fifo+0x4a>
    7014:	e00c      	b.n	7030 <read_slave_rx_fifo+0xa4>
    else
    {
        /* Should not happen... Just purge FIFO */
        while(0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK))
        {
            rx_frame = this_spi->hw_reg->RX_DATA;
    7016:	687b      	ldr	r3, [r7, #4]
    7018:	681b      	ldr	r3, [r3, #0]
    701a:	691b      	ldr	r3, [r3, #16]
    701c:	60fb      	str	r3, [r7, #12]
    701e:	e000      	b.n	7022 <read_slave_rx_fifo+0x96>
        }
    }
    else
    {
        /* Should not happen... Just purge FIFO */
        while(0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK))
    7020:	bf00      	nop
    7022:	687b      	ldr	r3, [r7, #4]
    7024:	681b      	ldr	r3, [r3, #0]
    7026:	689b      	ldr	r3, [r3, #8]
    7028:	f003 0340 	and.w	r3, r3, #64	; 0x40
    702c:	2b00      	cmp	r3, #0
    702e:	d0f2      	beq.n	7016 <read_slave_rx_fifo+0x8a>
        {
            rx_frame = this_spi->hw_reg->RX_DATA;
        }
    }
}
    7030:	f107 0710 	add.w	r7, r7, #16
    7034:	46bd      	mov	sp, r7
    7036:	bd80      	pop	{r7, pc}

00007038 <mss_spi_isr>:
 */
static void mss_spi_isr
(
    mss_spi_instance_t * this_spi
)
{    
    7038:	b580      	push	{r7, lr}
    703a:	b086      	sub	sp, #24
    703c:	af00      	add	r7, sp, #0
    703e:	6078      	str	r0, [r7, #4]
    volatile uint32_t rx_frame;
    __I  uint32_t *this_mis = &this_spi->hw_reg->MIS;
    7040:	687b      	ldr	r3, [r7, #4]
    7042:	681b      	ldr	r3, [r3, #0]
    7044:	f103 0320 	add.w	r3, r3, #32
    7048:	613b      	str	r3, [r7, #16]

    ASSERT((this_spi == &g_mss_spi0) || (this_spi == &g_mss_spi1));
    704a:	687a      	ldr	r2, [r7, #4]
    704c:	f240 23bc 	movw	r3, #700	; 0x2bc
    7050:	f2c2 0300 	movt	r3, #8192	; 0x2000
    7054:	429a      	cmp	r2, r3
    7056:	d007      	beq.n	7068 <mss_spi_isr+0x30>
    7058:	687a      	ldr	r2, [r7, #4]
    705a:	f240 2338 	movw	r3, #568	; 0x238
    705e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    7062:	429a      	cmp	r2, r3
    7064:	d000      	beq.n	7068 <mss_spi_isr+0x30>
    7066:	be00      	bkpt	0x0000
  
    if(0u != (*this_mis & RXDONE_IRQ_MASK))
    7068:	693b      	ldr	r3, [r7, #16]
    706a:	681b      	ldr	r3, [r3, #0]
    706c:	f003 0302 	and.w	r3, r3, #2
    7070:	2b00      	cmp	r3, #0
    7072:	d052      	beq.n	711a <mss_spi_isr+0xe2>
    {
        if(MSS_SPI_SLAVE_XFER_FRAME == this_spi->slave_xfer_mode)
    7074:	687b      	ldr	r3, [r7, #4]
    7076:	f893 3080 	ldrb.w	r3, [r3, #128]	; 0x80
    707a:	2b02      	cmp	r3, #2
    707c:	d115      	bne.n	70aa <mss_spi_isr+0x72>
        {
            /* Single frame handling mode. */
            while(0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK))
    707e:	e00c      	b.n	709a <mss_spi_isr+0x62>
            {
                rx_frame = this_spi->hw_reg->RX_DATA;
    7080:	687b      	ldr	r3, [r7, #4]
    7082:	681b      	ldr	r3, [r3, #0]
    7084:	691b      	ldr	r3, [r3, #16]
    7086:	60fb      	str	r3, [r7, #12]
                if(0u != this_spi->frame_rx_handler)
    7088:	687b      	ldr	r3, [r7, #4]
    708a:	6f5b      	ldr	r3, [r3, #116]	; 0x74
    708c:	2b00      	cmp	r3, #0
    708e:	d004      	beq.n	709a <mss_spi_isr+0x62>
                {
                    this_spi->frame_rx_handler( rx_frame );
    7090:	687b      	ldr	r3, [r7, #4]
    7092:	6f5b      	ldr	r3, [r3, #116]	; 0x74
    7094:	68fa      	ldr	r2, [r7, #12]
    7096:	4610      	mov	r0, r2
    7098:	4798      	blx	r3
    if(0u != (*this_mis & RXDONE_IRQ_MASK))
    {
        if(MSS_SPI_SLAVE_XFER_FRAME == this_spi->slave_xfer_mode)
        {
            /* Single frame handling mode. */
            while(0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK))
    709a:	687b      	ldr	r3, [r7, #4]
    709c:	681b      	ldr	r3, [r3, #0]
    709e:	689b      	ldr	r3, [r3, #8]
    70a0:	f003 0340 	and.w	r3, r3, #64	; 0x40
    70a4:	2b00      	cmp	r3, #0
    70a6:	d0eb      	beq.n	7080 <mss_spi_isr+0x48>
    70a8:	e032      	b.n	7110 <mss_spi_isr+0xd8>
                {
                    this_spi->frame_rx_handler( rx_frame );
                }
            }
        }
        else if(MSS_SPI_SLAVE_XFER_BLOCK == this_spi->slave_xfer_mode)
    70aa:	687b      	ldr	r3, [r7, #4]
    70ac:	f893 3080 	ldrb.w	r3, [r3, #128]	; 0x80
    70b0:	2b01      	cmp	r3, #1
    70b2:	d125      	bne.n	7100 <mss_spi_isr+0xc8>
        {
            /* Block handling mode. */
            while(0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK)) /* Something needs to be read from FIFO */
    70b4:	e017      	b.n	70e6 <mss_spi_isr+0xae>
            {
                rx_frame = this_spi->hw_reg->RX_DATA;                /* Read from FIFO irrespective */
    70b6:	687b      	ldr	r3, [r7, #4]
    70b8:	681b      	ldr	r3, [r3, #0]
    70ba:	691b      	ldr	r3, [r3, #16]
    70bc:	60fb      	str	r3, [r7, #12]
                if(this_spi->slave_rx_idx < this_spi->slave_rx_size) /* Write to array if required */
    70be:	687b      	ldr	r3, [r7, #4]
    70c0:	6b1a      	ldr	r2, [r3, #48]	; 0x30
    70c2:	687b      	ldr	r3, [r7, #4]
    70c4:	6adb      	ldr	r3, [r3, #44]	; 0x2c
    70c6:	429a      	cmp	r2, r3
    70c8:	d207      	bcs.n	70da <mss_spi_isr+0xa2>
                {
                    this_spi->slave_rx_buffer[this_spi->slave_rx_idx] = (uint8_t)rx_frame;
    70ca:	687b      	ldr	r3, [r7, #4]
    70cc:	6a9a      	ldr	r2, [r3, #40]	; 0x28
    70ce:	687b      	ldr	r3, [r7, #4]
    70d0:	6b1b      	ldr	r3, [r3, #48]	; 0x30
    70d2:	4413      	add	r3, r2
    70d4:	68fa      	ldr	r2, [r7, #12]
    70d6:	b2d2      	uxtb	r2, r2
    70d8:	701a      	strb	r2, [r3, #0]
                }

                ++this_spi->slave_rx_idx;            
    70da:	687b      	ldr	r3, [r7, #4]
    70dc:	6b1b      	ldr	r3, [r3, #48]	; 0x30
    70de:	f103 0201 	add.w	r2, r3, #1
    70e2:	687b      	ldr	r3, [r7, #4]
    70e4:	631a      	str	r2, [r3, #48]	; 0x30
            }
        }
        else if(MSS_SPI_SLAVE_XFER_BLOCK == this_spi->slave_xfer_mode)
        {
            /* Block handling mode. */
            while(0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK)) /* Something needs to be read from FIFO */
    70e6:	687b      	ldr	r3, [r7, #4]
    70e8:	681b      	ldr	r3, [r3, #0]
    70ea:	689b      	ldr	r3, [r3, #8]
    70ec:	f003 0340 	and.w	r3, r3, #64	; 0x40
    70f0:	2b00      	cmp	r3, #0
    70f2:	d0e0      	beq.n	70b6 <mss_spi_isr+0x7e>
    70f4:	e00c      	b.n	7110 <mss_spi_isr+0xd8>
        else
        {
            /* No slave handling in place so just purge FIFO */
            while(0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK))
            {
                rx_frame = this_spi->hw_reg->RX_DATA;
    70f6:	687b      	ldr	r3, [r7, #4]
    70f8:	681b      	ldr	r3, [r3, #0]
    70fa:	691b      	ldr	r3, [r3, #16]
    70fc:	60fb      	str	r3, [r7, #12]
    70fe:	e000      	b.n	7102 <mss_spi_isr+0xca>
            }
        }
        else
        {
            /* No slave handling in place so just purge FIFO */
            while(0u == (this_spi->hw_reg->STATUS & RX_FIFO_EMPTY_MASK))
    7100:	bf00      	nop
    7102:	687b      	ldr	r3, [r7, #4]
    7104:	681b      	ldr	r3, [r3, #0]
    7106:	689b      	ldr	r3, [r3, #8]
    7108:	f003 0340 	and.w	r3, r3, #64	; 0x40
    710c:	2b00      	cmp	r3, #0
    710e:	d0f2      	beq.n	70f6 <mss_spi_isr+0xbe>
            {
                rx_frame = this_spi->hw_reg->RX_DATA;
            }
        }

        this_spi->hw_reg->INT_CLEAR = RXDONE_IRQ_MASK;
    7110:	687b      	ldr	r3, [r7, #4]
    7112:	681b      	ldr	r3, [r3, #0]
    7114:	f04f 0202 	mov.w	r2, #2
    7118:	60da      	str	r2, [r3, #12]
    }

   /* Handle transmit. */
    if(0u != (*this_mis & TXDONE_IRQ_MASK))
    711a:	693b      	ldr	r3, [r7, #16]
    711c:	681b      	ldr	r3, [r3, #0]
    711e:	f003 0301 	and.w	r3, r3, #1
    7122:	b2db      	uxtb	r3, r3
    7124:	2b00      	cmp	r3, #0
    7126:	d012      	beq.n	714e <mss_spi_isr+0x116>
    {
        if( MSS_SPI_SLAVE_XFER_FRAME == this_spi->slave_xfer_mode )
    7128:	687b      	ldr	r3, [r7, #4]
    712a:	f893 3080 	ldrb.w	r3, [r3, #128]	; 0x80
    712e:	2b02      	cmp	r3, #2
    7130:	d105      	bne.n	713e <mss_spi_isr+0x106>
        {
           /* Reload slave tx frame into Tx data register. */
            this_spi->hw_reg->TX_DATA = this_spi->slave_tx_frame;
    7132:	687b      	ldr	r3, [r7, #4]
    7134:	681b      	ldr	r3, [r3, #0]
    7136:	687a      	ldr	r2, [r7, #4]
    7138:	6f92      	ldr	r2, [r2, #120]	; 0x78
    713a:	615a      	str	r2, [r3, #20]
    713c:	e002      	b.n	7144 <mss_spi_isr+0x10c>
        }
        else /* Must be block mode so load FIFO to the max */
        {
            fill_slave_tx_fifo(this_spi);
    713e:	6878      	ldr	r0, [r7, #4]
    7140:	f7ff feb4 	bl	6eac <fill_slave_tx_fifo>
        }

        this_spi->hw_reg->INT_CLEAR = TXDONE_IRQ_MASK;
    7144:	687b      	ldr	r3, [r7, #4]
    7146:	681b      	ldr	r3, [r3, #0]
    7148:	f04f 0201 	mov.w	r2, #1
    714c:	60da      	str	r2, [r3, #12]
    }
    
    /* Handle command interrupt. */
    if(0u != (*this_mis & CMD_IRQ_MASK))
    714e:	693b      	ldr	r3, [r7, #16]
    7150:	681b      	ldr	r3, [r3, #0]
    7152:	f003 0310 	and.w	r3, r3, #16
    7156:	2b00      	cmp	r3, #0
    7158:	d023      	beq.n	71a2 <mss_spi_isr+0x16a>
    {
        read_slave_rx_fifo(this_spi);
    715a:	6878      	ldr	r0, [r7, #4]
    715c:	f7ff ff16 	bl	6f8c <read_slave_rx_fifo>
        
        /*
         * Call the command handler if one exists.
         */
        if(0u != this_spi->cmd_handler)
    7160:	687b      	ldr	r3, [r7, #4]
    7162:	6a1b      	ldr	r3, [r3, #32]
    7164:	2b00      	cmp	r3, #0
    7166:	d00b      	beq.n	7180 <mss_spi_isr+0x148>
        {
            (*this_spi->cmd_handler)(this_spi->slave_rx_buffer, this_spi->slave_rx_idx);
    7168:	687b      	ldr	r3, [r7, #4]
    716a:	6a1b      	ldr	r3, [r3, #32]
    716c:	687a      	ldr	r2, [r7, #4]
    716e:	6a91      	ldr	r1, [r2, #40]	; 0x28
    7170:	687a      	ldr	r2, [r7, #4]
    7172:	6b12      	ldr	r2, [r2, #48]	; 0x30
    7174:	4608      	mov	r0, r1
    7176:	4611      	mov	r1, r2
    7178:	4798      	blx	r3
            fill_slave_tx_fifo(this_spi);
    717a:	6878      	ldr	r0, [r7, #4]
    717c:	f7ff fe96 	bl	6eac <fill_slave_tx_fifo>
        }
        /* Set cmd_done to indicate it is now safe to 0 fill TX FIFO */
        this_spi->cmd_done = 1u;
    7180:	687b      	ldr	r3, [r7, #4]
    7182:	f04f 0201 	mov.w	r2, #1
    7186:	625a      	str	r2, [r3, #36]	; 0x24
        /* Disable command interrupt until slave select becomes de-asserted to avoid retriggering. */
        this_spi->hw_reg->CONTROL2 &= ~(uint32_t)C2_ENABLE_CMD_IRQ_MASK;
    7188:	687b      	ldr	r3, [r7, #4]
    718a:	681b      	ldr	r3, [r3, #0]
    718c:	687a      	ldr	r2, [r7, #4]
    718e:	6812      	ldr	r2, [r2, #0]
    7190:	6a92      	ldr	r2, [r2, #40]	; 0x28
    7192:	f022 0210 	bic.w	r2, r2, #16
    7196:	629a      	str	r2, [r3, #40]	; 0x28
        this_spi->hw_reg->INT_CLEAR = CMD_IRQ_MASK;
    7198:	687b      	ldr	r3, [r7, #4]
    719a:	681b      	ldr	r3, [r3, #0]
    719c:	f04f 0210 	mov.w	r2, #16
    71a0:	60da      	str	r2, [r3, #12]
    }

    if(0u != (*this_mis & RXOVFLOW_IRQ_MASK))
    71a2:	693b      	ldr	r3, [r7, #16]
    71a4:	681b      	ldr	r3, [r3, #0]
    71a6:	f003 0304 	and.w	r3, r3, #4
    71aa:	2b00      	cmp	r3, #0
    71ac:	d00f      	beq.n	71ce <mss_spi_isr+0x196>
    {
        /*
         * Receive overflow, not a lot we can do for this. Reset the receive
         *  FIFO, clear the interrupt and hope it doesn't happen again...
         */
        this_spi->hw_reg->COMMAND |= RX_FIFO_RESET_MASK;
    71ae:	687b      	ldr	r3, [r7, #4]
    71b0:	681b      	ldr	r3, [r3, #0]
    71b2:	687a      	ldr	r2, [r7, #4]
    71b4:	6812      	ldr	r2, [r2, #0]
    71b6:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
    71b8:	f042 0204 	orr.w	r2, r2, #4
    71bc:	62da      	str	r2, [r3, #44]	; 0x2c
        recover_from_rx_overflow(this_spi);
    71be:	6878      	ldr	r0, [r7, #4]
    71c0:	f7fe ff4c 	bl	605c <recover_from_rx_overflow>
        this_spi->hw_reg->INT_CLEAR = RXOVFLOW_IRQ_MASK;
    71c4:	687b      	ldr	r3, [r7, #4]
    71c6:	681b      	ldr	r3, [r3, #0]
    71c8:	f04f 0204 	mov.w	r2, #4
    71cc:	60da      	str	r2, [r3, #12]
     * slave TX FIFO data setup (if there is one).
     * In block mode this will probably not be very successful as we will
     * be out of synch with the master but the reset on SSEND will hopefully
     * take care of that for the next transfer.
     */
    if(0u != (*this_mis & TXURUN_IRQ_MASK))
    71ce:	693b      	ldr	r3, [r7, #16]
    71d0:	681b      	ldr	r3, [r3, #0]
    71d2:	f003 0308 	and.w	r3, r3, #8
    71d6:	2b00      	cmp	r3, #0
    71d8:	d031      	beq.n	723e <mss_spi_isr+0x206>
    {
        this_spi->hw_reg->COMMAND |= TX_FIFO_RESET_MASK;
    71da:	687b      	ldr	r3, [r7, #4]
    71dc:	681b      	ldr	r3, [r3, #0]
    71de:	687a      	ldr	r2, [r7, #4]
    71e0:	6812      	ldr	r2, [r2, #0]
    71e2:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
    71e4:	f042 0208 	orr.w	r2, r2, #8
    71e8:	62da      	str	r2, [r3, #44]	; 0x2c
        if( MSS_SPI_SLAVE_XFER_FRAME == this_spi->slave_xfer_mode )
    71ea:	687b      	ldr	r3, [r7, #4]
    71ec:	f893 3080 	ldrb.w	r3, [r3, #128]	; 0x80
    71f0:	2b02      	cmp	r3, #2
    71f2:	d113      	bne.n	721c <mss_spi_isr+0x1e4>
        {
            this_spi->hw_reg->CONTROL = (this_spi->hw_reg->CONTROL & ~TXRXDFCOUNT_MASK)
    71f4:	687b      	ldr	r3, [r7, #4]
    71f6:	681a      	ldr	r2, [r3, #0]
    71f8:	687b      	ldr	r3, [r7, #4]
    71fa:	681b      	ldr	r3, [r3, #0]
    71fc:	6819      	ldr	r1, [r3, #0]
    71fe:	f240 03ff 	movw	r3, #255	; 0xff
    7202:	f6cf 7300 	movt	r3, #65280	; 0xff00
    7206:	ea01 0303 	and.w	r3, r1, r3
    720a:	f443 7380 	orr.w	r3, r3, #256	; 0x100
    720e:	6013      	str	r3, [r2, #0]
                                        | ((uint32_t)1u << TXRXDFCOUNT_SHIFT);
           /* Reload slave tx frame into Tx data register. */
            this_spi->hw_reg->TX_DATA = this_spi->slave_tx_frame;
    7210:	687b      	ldr	r3, [r7, #4]
    7212:	681b      	ldr	r3, [r3, #0]
    7214:	687a      	ldr	r2, [r7, #4]
    7216:	6f92      	ldr	r2, [r2, #120]	; 0x78
    7218:	615a      	str	r2, [r3, #20]
    721a:	e00b      	b.n	7234 <mss_spi_isr+0x1fc>
        }
        else if( MSS_SPI_SLAVE_XFER_BLOCK == this_spi->slave_xfer_mode )
    721c:	687b      	ldr	r3, [r7, #4]
    721e:	f893 3080 	ldrb.w	r3, [r3, #128]	; 0x80
    7222:	2b01      	cmp	r3, #1
    7224:	d106      	bne.n	7234 <mss_spi_isr+0x1fc>
        {
            /* Block mode so reload FIFO to the max */
            this_spi->slave_tx_idx = 0u;
    7226:	687b      	ldr	r3, [r7, #4]
    7228:	f04f 0200 	mov.w	r2, #0
    722c:	611a      	str	r2, [r3, #16]
            fill_slave_tx_fifo(this_spi);
    722e:	6878      	ldr	r0, [r7, #4]
    7230:	f7ff fe3c 	bl	6eac <fill_slave_tx_fifo>
        else
        {
            /* Not frame or block mode? Can't do anything here... */
        }

        this_spi->hw_reg->INT_CLEAR = TXURUN_IRQ_MASK;
    7234:	687b      	ldr	r3, [r7, #4]
    7236:	681b      	ldr	r3, [r3, #0]
    7238:	f04f 0208 	mov.w	r2, #8
    723c:	60da      	str	r2, [r3, #12]
    /*
     * Handle slave select becoming de-asserted. Only enables if
     * we are operating in block mode, in frame mode we do everything
     * in the receive and transmit interrupt handlers.
     */
    if(0u != (*this_mis & SSEND_IRQ_MASK))
    723e:	693b      	ldr	r3, [r7, #16]
    7240:	681b      	ldr	r3, [r3, #0]
    7242:	f003 0320 	and.w	r3, r3, #32
    7246:	2b00      	cmp	r3, #0
    7248:	d049      	beq.n	72de <mss_spi_isr+0x2a6>
    {
        uint32_t rx_size;
        
        read_slave_rx_fifo(this_spi);
    724a:	6878      	ldr	r0, [r7, #4]
    724c:	f7ff fe9e 	bl	6f8c <read_slave_rx_fifo>
        rx_size = this_spi->slave_rx_idx;
    7250:	687b      	ldr	r3, [r7, #4]
    7252:	6b1b      	ldr	r3, [r3, #48]	; 0x30
    7254:	617b      	str	r3, [r7, #20]
        /*
         * Re-enable command interrupt if required and clear all the response
         * buffer state in readiness for next response. This must be done
         * before reloading the TX FIFO.
         */
        if(0 != this_spi->cmd_handler)
    7256:	687b      	ldr	r3, [r7, #4]
    7258:	6a1b      	ldr	r3, [r3, #32]
    725a:	2b00      	cmp	r3, #0
    725c:	d01c      	beq.n	7298 <mss_spi_isr+0x260>
        {
            this_spi->cmd_done = 0u;
    725e:	687b      	ldr	r3, [r7, #4]
    7260:	f04f 0200 	mov.w	r2, #0
    7264:	625a      	str	r2, [r3, #36]	; 0x24
            this_spi->resp_tx_buffer = 0u;
    7266:	687b      	ldr	r3, [r7, #4]
    7268:	f04f 0200 	mov.w	r2, #0
    726c:	615a      	str	r2, [r3, #20]
            this_spi->resp_buff_size = 0u;
    726e:	687b      	ldr	r3, [r7, #4]
    7270:	f04f 0200 	mov.w	r2, #0
    7274:	619a      	str	r2, [r3, #24]
            this_spi->resp_buff_tx_idx = 0u;
    7276:	687b      	ldr	r3, [r7, #4]
    7278:	f04f 0200 	mov.w	r2, #0
    727c:	61da      	str	r2, [r3, #28]
            this_spi->hw_reg->INT_CLEAR = CMD_IRQ_MASK;
    727e:	687b      	ldr	r3, [r7, #4]
    7280:	681b      	ldr	r3, [r3, #0]
    7282:	f04f 0210 	mov.w	r2, #16
    7286:	60da      	str	r2, [r3, #12]
            this_spi->hw_reg->CONTROL2 |= C2_ENABLE_CMD_IRQ_MASK;
    7288:	687b      	ldr	r3, [r7, #4]
    728a:	681b      	ldr	r3, [r3, #0]
    728c:	687a      	ldr	r2, [r7, #4]
    728e:	6812      	ldr	r2, [r2, #0]
    7290:	6a92      	ldr	r2, [r2, #40]	; 0x28
    7292:	f042 0210 	orr.w	r2, r2, #16
    7296:	629a      	str	r2, [r3, #40]	; 0x28
        /* 
         * Reset the transmit index to 0 to restart transmit at the start of the
         * transmit buffer in the next transaction. This also requires flushing
         * the Tx FIFO and refilling it with the start of Tx data buffer.
         */
        this_spi->slave_tx_idx = 0u;
    7298:	687b      	ldr	r3, [r7, #4]
    729a:	f04f 0200 	mov.w	r2, #0
    729e:	611a      	str	r2, [r3, #16]
        this_spi->hw_reg->COMMAND |= (TX_FIFO_RESET_MASK | RX_FIFO_RESET_MASK);
    72a0:	687b      	ldr	r3, [r7, #4]
    72a2:	681b      	ldr	r3, [r3, #0]
    72a4:	687a      	ldr	r2, [r7, #4]
    72a6:	6812      	ldr	r2, [r2, #0]
    72a8:	6ad2      	ldr	r2, [r2, #44]	; 0x2c
    72aa:	f042 020c 	orr.w	r2, r2, #12
    72ae:	62da      	str	r2, [r3, #44]	; 0x2c
        fill_slave_tx_fifo(this_spi);
    72b0:	6878      	ldr	r0, [r7, #4]
    72b2:	f7ff fdfb 	bl	6eac <fill_slave_tx_fifo>
        
        /* Prepare to receive next packet. */
        this_spi->slave_rx_idx = 0u;
    72b6:	687b      	ldr	r3, [r7, #4]
    72b8:	f04f 0200 	mov.w	r2, #0
    72bc:	631a      	str	r2, [r3, #48]	; 0x30
        /*
         * Call the receive handler if one exists.
         */
        if(0u != this_spi->block_rx_handler)
    72be:	687b      	ldr	r3, [r7, #4]
    72c0:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
    72c2:	2b00      	cmp	r3, #0
    72c4:	d006      	beq.n	72d4 <mss_spi_isr+0x29c>
        {
            (*this_spi->block_rx_handler)(this_spi->slave_rx_buffer, rx_size);
    72c6:	687b      	ldr	r3, [r7, #4]
    72c8:	6fdb      	ldr	r3, [r3, #124]	; 0x7c
    72ca:	687a      	ldr	r2, [r7, #4]
    72cc:	6a92      	ldr	r2, [r2, #40]	; 0x28
    72ce:	4610      	mov	r0, r2
    72d0:	6979      	ldr	r1, [r7, #20]
    72d2:	4798      	blx	r3
        }
        
        this_spi->hw_reg->INT_CLEAR = SSEND_IRQ_MASK;
    72d4:	687b      	ldr	r3, [r7, #4]
    72d6:	681b      	ldr	r3, [r3, #0]
    72d8:	f04f 0220 	mov.w	r2, #32
    72dc:	60da      	str	r2, [r3, #12]
    }
}
    72de:	f107 0718 	add.w	r7, r7, #24
    72e2:	46bd      	mov	sp, r7
    72e4:	bd80      	pop	{r7, pc}
    72e6:	bf00      	nop

000072e8 <SPI0_IRQHandler>:
#if defined(__GNUC__)
__attribute__((__interrupt__)) void SPI0_IRQHandler(void)
#else
void SPI0_IRQHandler( void )
#endif
{
    72e8:	4668      	mov	r0, sp
    72ea:	f020 0107 	bic.w	r1, r0, #7
    72ee:	468d      	mov	sp, r1
    72f0:	b589      	push	{r0, r3, r7, lr}
    72f2:	af00      	add	r7, sp, #0
    mss_spi_isr(&g_mss_spi0);
    72f4:	f240 20bc 	movw	r0, #700	; 0x2bc
    72f8:	f2c2 0000 	movt	r0, #8192	; 0x2000
    72fc:	f7ff fe9c 	bl	7038 <mss_spi_isr>
}
    7300:	46bd      	mov	sp, r7
    7302:	e8bd 4089 	ldmia.w	sp!, {r0, r3, r7, lr}
    7306:	4685      	mov	sp, r0
    7308:	4770      	bx	lr
    730a:	bf00      	nop

0000730c <SPI1_IRQHandler>:
#if defined(__GNUC__)
__attribute__((__interrupt__)) void SPI1_IRQHandler(void)
#else
void SPI1_IRQHandler(void)
#endif
{
    730c:	4668      	mov	r0, sp
    730e:	f020 0107 	bic.w	r1, r0, #7
    7312:	468d      	mov	sp, r1
    7314:	b589      	push	{r0, r3, r7, lr}
    7316:	af00      	add	r7, sp, #0
    mss_spi_isr(&g_mss_spi1);
    7318:	f240 2038 	movw	r0, #568	; 0x238
    731c:	f2c2 0000 	movt	r0, #8192	; 0x2000
    7320:	f7ff fe8a 	bl	7038 <mss_spi_isr>
}
    7324:	46bd      	mov	sp, r7
    7326:	e8bd 4089 	ldmia.w	sp!, {r0, r3, r7, lr}
    732a:	4685      	mov	sp, r0
    732c:	4770      	bx	lr
    732e:	bf00      	nop

00007330 <NVM_write>:
    uint32_t start_addr,
    const uint8_t * pidata,
    uint32_t length,
    uint32_t lock_page
)
{
    7330:	b580      	push	{r7, lr}
    7332:	b08e      	sub	sp, #56	; 0x38
    7334:	af02      	add	r7, sp, #8
    7336:	60f8      	str	r0, [r7, #12]
    7338:	60b9      	str	r1, [r7, #8]
    733a:	607a      	str	r2, [r7, #4]
    733c:	603b      	str	r3, [r7, #0]
     * to its maximum value (i.e. 15) to ensure successful writes to eNVM. 
     * Store the value of the eNVM configuration before updating it, so 
     * that the prior configuration can be restored when the eNVM write
     * operation has completed. 
     */
    initial_nvm_config = SYSREG->ENVM_CR;
    733e:	f248 0300 	movw	r3, #32768	; 0x8000
    7342:	f2c4 0303 	movt	r3, #16387	; 0x4003
    7346:	68db      	ldr	r3, [r3, #12]
    7348:	623b      	str	r3, [r7, #32]
    SYSREG->ENVM_CR = (initial_nvm_config & NVM_FREQRNG_MASK) | NVM_FREQRNG_MAX;
    734a:	f248 0300 	movw	r3, #32768	; 0x8000
    734e:	f2c4 0303 	movt	r3, #16387	; 0x4003
    7352:	6a3a      	ldr	r2, [r7, #32]
    7354:	f442 52ff 	orr.w	r2, r2, #8160	; 0x1fe0
    7358:	60da      	str	r2, [r3, #12]

    /* Check input parameters */
    if((start_addr >= (NVM_BASE_ADDRESS + NVM_TOP_OFFSET)) || \
    735a:	68fa      	ldr	r2, [r7, #12]
    735c:	f64f 73fe 	movw	r3, #65534	; 0xfffe
    7360:	f2c6 0307 	movt	r3, #24583	; 0x6007
    7364:	429a      	cmp	r2, r3
    7366:	d814      	bhi.n	7392 <NVM_write+0x62>
    7368:	68fa      	ldr	r2, [r7, #12]
    736a:	f64f 73fe 	movw	r3, #65534	; 0xfffe
    736e:	f2c0 0307 	movt	r3, #7
    7372:	429a      	cmp	r2, r3
    7374:	d904      	bls.n	7380 <NVM_write+0x50>
    7376:	68fa      	ldr	r2, [r7, #12]
    7378:	f06f 4320 	mvn.w	r3, #2684354560	; 0xa0000000
    737c:	429a      	cmp	r2, r3
    737e:	d908      	bls.n	7392 <NVM_write+0x62>
    7380:	68bb      	ldr	r3, [r7, #8]
    7382:	2b00      	cmp	r3, #0
    7384:	d005      	beq.n	7392 <NVM_write+0x62>
    7386:	687b      	ldr	r3, [r7, #4]
    7388:	2b00      	cmp	r3, #0
    738a:	d002      	beq.n	7392 <NVM_write+0x62>
    738c:	683b      	ldr	r3, [r7, #0]
    738e:	2b02      	cmp	r3, #2
    7390:	d903      	bls.n	739a <NVM_write+0x6a>
        (start_addr < NVM_BASE_ADDRESS)) || \
        (!pidata) || \
        (!length) || \
        (lock_page > PARAM_LOCK_PAGE_FLAG))
    {
        status =  NVM_INVALID_PARAMETER;
    7392:	f04f 0306 	mov.w	r3, #6
    7396:	75fb      	strb	r3, [r7, #23]
     */
    initial_nvm_config = SYSREG->ENVM_CR;
    SYSREG->ENVM_CR = (initial_nvm_config & NVM_FREQRNG_MASK) | NVM_FREQRNG_MAX;

    /* Check input parameters */
    if((start_addr >= (NVM_BASE_ADDRESS + NVM_TOP_OFFSET)) || \
    7398:	e077      	b.n	748a <NVM_write+0x15a>
    {
        /*
         * Prevent pages being locked for silicon versions which do not allow
         * locked pages to be unlocked.
         */
        device_version = SYSREG->DEVICE_VERSION;
    739a:	f248 0300 	movw	r3, #32768	; 0x8000
    739e:	f2c4 0303 	movt	r3, #16387	; 0x4003
    73a2:	f8d3 314c 	ldr.w	r3, [r3, #332]	; 0x14c
    73a6:	61fb      	str	r3, [r7, #28]
        if((0x0000F802u == device_version) || (0x0001F802u == device_version))
    73a8:	69fa      	ldr	r2, [r7, #28]
    73aa:	f64f 0302 	movw	r3, #63490	; 0xf802
    73ae:	429a      	cmp	r2, r3
    73b0:	d006      	beq.n	73c0 <NVM_write+0x90>
    73b2:	69fa      	ldr	r2, [r7, #28]
    73b4:	f64f 0302 	movw	r3, #63490	; 0xf802
    73b8:	f2c0 0301 	movt	r3, #1
    73bc:	429a      	cmp	r2, r3
    73be:	d102      	bne.n	73c6 <NVM_write+0x96>
        {
            lock_page = NVM_DO_NOT_LOCK_PAGE;
    73c0:	f04f 0300 	mov.w	r3, #0
    73c4:	603b      	str	r3, [r7, #0]
        }

        /* Ignore upper address bits to ignore remapping setting. */
        nvm_offset = start_addr & NVM_OFFSET_SIGNIFICANT_BITS;  /* Ignore remapping. */
    73c6:	68fb      	ldr	r3, [r7, #12]
    73c8:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
    73cc:	f423 0378 	bic.w	r3, r3, #16252928	; 0xf80000
    73d0:	61bb      	str	r3, [r7, #24]

        status = check_protection_reserved_nvm(nvm_offset, length);
    73d2:	69b8      	ldr	r0, [r7, #24]
    73d4:	6879      	ldr	r1, [r7, #4]
    73d6:	f000 fcc1 	bl	7d5c <check_protection_reserved_nvm>
    73da:	4603      	mov	r3, r0
    73dc:	75fb      	strb	r3, [r7, #23]

        /* Check  */
        if(NVM_SUCCESS == status)
    73de:	7dfb      	ldrb	r3, [r7, #23]
    73e0:	2b00      	cmp	r3, #0
    73e2:	d152      	bne.n	748a <NVM_write+0x15a>
        {
            /* Gain exclusive access to eNVM controller */
            status = get_ctrl_access(nvm_offset, length);
    73e4:	69b8      	ldr	r0, [r7, #24]
    73e6:	6879      	ldr	r1, [r7, #4]
    73e8:	f000 f9f2 	bl	77d0 <get_ctrl_access>
    73ec:	4603      	mov	r3, r0
    73ee:	75fb      	strb	r3, [r7, #23]

            /* Write eNVM one page at a time. */
            if(NVM_SUCCESS == status)
    73f0:	7dfb      	ldrb	r3, [r7, #23]
    73f2:	2b00      	cmp	r3, #0
    73f4:	d149      	bne.n	748a <NVM_write+0x15a>
            {
                uint32_t remaining_length = length;
    73f6:	687b      	ldr	r3, [r7, #4]
    73f8:	627b      	str	r3, [r7, #36]	; 0x24
                uint32_t errors_and_warnings;
                
                while(remaining_length > 0u)
    73fa:	e041      	b.n	7480 <NVM_write+0x150>
                {
                    uint32_t length_written;
                    uint32_t nvm_hw_status = 0u;
    73fc:	f04f 0300 	mov.w	r3, #0
    7400:	613b      	str	r3, [r7, #16]

                    length_written = write_nvm(start_addr + (length - remaining_length),
    7402:	687a      	ldr	r2, [r7, #4]
    7404:	6a7b      	ldr	r3, [r7, #36]	; 0x24
    7406:	ebc3 0202 	rsb	r2, r3, r2
    740a:	68fb      	ldr	r3, [r7, #12]
    740c:	441a      	add	r2, r3
                                                &pidata[length - remaining_length],
    740e:	6879      	ldr	r1, [r7, #4]
    7410:	6a7b      	ldr	r3, [r7, #36]	; 0x24
    7412:	ebc3 0101 	rsb	r1, r3, r1
                while(remaining_length > 0u)
                {
                    uint32_t length_written;
                    uint32_t nvm_hw_status = 0u;

                    length_written = write_nvm(start_addr + (length - remaining_length),
    7416:	68bb      	ldr	r3, [r7, #8]
    7418:	440b      	add	r3, r1
    741a:	f107 0110 	add.w	r1, r7, #16
    741e:	9100      	str	r1, [sp, #0]
    7420:	4610      	mov	r0, r2
    7422:	4619      	mov	r1, r3
    7424:	6a7a      	ldr	r2, [r7, #36]	; 0x24
    7426:	683b      	ldr	r3, [r7, #0]
    7428:	f000 fa84 	bl	7934 <write_nvm>
    742c:	4603      	mov	r3, r0
    742e:	62fb      	str	r3, [r7, #44]	; 0x2c
                                                remaining_length,
                                                lock_page,
                                                &nvm_hw_status);

                    /* Check for errors and warnings. */
                    errors_and_warnings = nvm_hw_status & (WRITE_ERROR_MASK | MSS_NVM_WRCNT_OVER);
    7430:	693a      	ldr	r2, [r7, #16]
    7432:	f240 033e 	movw	r3, #62	; 0x3e
    7436:	f2c0 0304 	movt	r3, #4
    743a:	ea02 0303 	and.w	r3, r2, r3
    743e:	62bb      	str	r3, [r7, #40]	; 0x28
                    if(errors_and_warnings)
    7440:	6abb      	ldr	r3, [r7, #40]	; 0x28
    7442:	2b00      	cmp	r3, #0
    7444:	d005      	beq.n	7452 <NVM_write+0x122>
                        * Ensure that the status returned by the NVM_write()
                        * function is NVM_WRITE_THRESHOLD_WARNING if at least one
                        * of the written eNVM pages indicate a write over
                        * threshold condition.
                        */ 
                        status = get_error_code(nvm_hw_status);
    7446:	693b      	ldr	r3, [r7, #16]
    7448:	4618      	mov	r0, r3
    744a:	f000 f82b 	bl	74a4 <get_error_code>
    744e:	4603      	mov	r3, r0
    7450:	75fb      	strb	r3, [r7, #23]
                    }

                    if((NVM_SUCCESS == status) || (NVM_WRITE_THRESHOLD_WARNING == status ))
    7452:	7dfb      	ldrb	r3, [r7, #23]
    7454:	2b00      	cmp	r3, #0
    7456:	d002      	beq.n	745e <NVM_write+0x12e>
    7458:	7dfb      	ldrb	r3, [r7, #23]
    745a:	2b04      	cmp	r3, #4
    745c:	d10d      	bne.n	747a <NVM_write+0x14a>
                    {
                        if(remaining_length > length_written)
    745e:	6a7a      	ldr	r2, [r7, #36]	; 0x24
    7460:	6afb      	ldr	r3, [r7, #44]	; 0x2c
    7462:	429a      	cmp	r2, r3
    7464:	d905      	bls.n	7472 <NVM_write+0x142>
                        {
                            remaining_length -= length_written;
    7466:	6a7a      	ldr	r2, [r7, #36]	; 0x24
    7468:	6afb      	ldr	r3, [r7, #44]	; 0x2c
    746a:	ebc3 0302 	rsb	r3, r3, r2
    746e:	627b      	str	r3, [r7, #36]	; 0x24
                        * threshold condition.
                        */ 
                        status = get_error_code(nvm_hw_status);
                    }

                    if((NVM_SUCCESS == status) || (NVM_WRITE_THRESHOLD_WARNING == status ))
    7470:	e006      	b.n	7480 <NVM_write+0x150>
                        {
                            remaining_length -= length_written;
                        }
                        else
                        {
                            remaining_length = 0u;
    7472:	f04f 0300 	mov.w	r3, #0
    7476:	627b      	str	r3, [r7, #36]	; 0x24
                        * threshold condition.
                        */ 
                        status = get_error_code(nvm_hw_status);
                    }

                    if((NVM_SUCCESS == status) || (NVM_WRITE_THRESHOLD_WARNING == status ))
    7478:	e002      	b.n	7480 <NVM_write+0x150>
                            remaining_length = 0u;
                        }
                    }
                    else
                    {
                        remaining_length = 0u;
    747a:	f04f 0300 	mov.w	r3, #0
    747e:	627b      	str	r3, [r7, #36]	; 0x24
            if(NVM_SUCCESS == status)
            {
                uint32_t remaining_length = length;
                uint32_t errors_and_warnings;
                
                while(remaining_length > 0u)
    7480:	6a7b      	ldr	r3, [r7, #36]	; 0x24
    7482:	2b00      	cmp	r3, #0
    7484:	d1ba      	bne.n	73fc <NVM_write+0xcc>
                        remaining_length = 0u;
                    }
                }

                /* Release eNVM controllers so that other masters can gain access to it. */
                release_ctrl_access();
    7486:	f000 f9e3 	bl	7850 <release_ctrl_access>
            }
        }
    }
    
    /* Restore back to original value. */
    SYSREG->ENVM_CR = initial_nvm_config;
    748a:	f248 0300 	movw	r3, #32768	; 0x8000
    748e:	f2c4 0303 	movt	r3, #16387	; 0x4003
    7492:	6a3a      	ldr	r2, [r7, #32]
    7494:	60da      	str	r2, [r3, #12]
    
    return status;
    7496:	7dfb      	ldrb	r3, [r7, #23]
}
    7498:	4618      	mov	r0, r3
    749a:	f107 0730 	add.w	r7, r7, #48	; 0x30
    749e:	46bd      	mov	sp, r7
    74a0:	bd80      	pop	{r7, pc}
    74a2:	bf00      	nop

000074a4 <get_error_code>:
                 MSS_NVM_WRCNT_OVER | \
                 MSS_NVM_WR_DENIED)
  
 */
static nvm_status_t get_error_code(uint32_t nvm_hw_status)
{
    74a4:	b480      	push	{r7}
    74a6:	b085      	sub	sp, #20
    74a8:	af00      	add	r7, sp, #0
    74aa:	6078      	str	r0, [r7, #4]
    nvm_status_t status;
    
    if(nvm_hw_status & MSS_NVM_WR_DENIED)
    74ac:	687b      	ldr	r3, [r7, #4]
    74ae:	f403 2380 	and.w	r3, r3, #262144	; 0x40000
    74b2:	2b00      	cmp	r3, #0
    74b4:	d003      	beq.n	74be <get_error_code+0x1a>
    {
        status = NVM_PROTECTION_ERROR;
    74b6:	f04f 0301 	mov.w	r3, #1
    74ba:	73fb      	strb	r3, [r7, #15]
    74bc:	e01d      	b.n	74fa <get_error_code+0x56>
    }
    else if(nvm_hw_status & MSS_NVM_PEFAIL_LOCK)
    74be:	687b      	ldr	r3, [r7, #4]
    74c0:	f003 0310 	and.w	r3, r3, #16
    74c4:	2b00      	cmp	r3, #0
    74c6:	d003      	beq.n	74d0 <get_error_code+0x2c>
    {
        status = NVM_PAGE_LOCK_ERROR;
    74c8:	f04f 0303 	mov.w	r3, #3
    74cc:	73fb      	strb	r3, [r7, #15]
    74ce:	e014      	b.n	74fa <get_error_code+0x56>
    }
    else if(nvm_hw_status & (MSS_NVM_VERIFY_FAIL |
    74d0:	687b      	ldr	r3, [r7, #4]
    74d2:	f003 030e 	and.w	r3, r3, #14
    74d6:	2b00      	cmp	r3, #0
    74d8:	d003      	beq.n	74e2 <get_error_code+0x3e>
            MSS_NVM_EVERIFY_FAIL | MSS_NVM_WVERIFY_FAIL))
    {
        status = NVM_VERIFY_FAILURE;
    74da:	f04f 0302 	mov.w	r3, #2
    74de:	73fb      	strb	r3, [r7, #15]
    74e0:	e00b      	b.n	74fa <get_error_code+0x56>
    }
    else if(nvm_hw_status & MSS_NVM_WRCNT_OVER)
    74e2:	687b      	ldr	r3, [r7, #4]
    74e4:	f003 0320 	and.w	r3, r3, #32
    74e8:	2b00      	cmp	r3, #0
    74ea:	d003      	beq.n	74f4 <get_error_code+0x50>
    {
        status = NVM_WRITE_THRESHOLD_WARNING;
    74ec:	f04f 0304 	mov.w	r3, #4
    74f0:	73fb      	strb	r3, [r7, #15]
    74f2:	e002      	b.n	74fa <get_error_code+0x56>
    }
    else
    {
        status = NVM_SUCCESS;
    74f4:	f04f 0300 	mov.w	r3, #0
    74f8:	73fb      	strb	r3, [r7, #15]
    }
    
    return status;
    74fa:	7bfb      	ldrb	r3, [r7, #15]
}
    74fc:	4618      	mov	r0, r3
    74fe:	f107 0714 	add.w	r7, r7, #20
    7502:	46bd      	mov	sp, r7
    7504:	bc80      	pop	{r7}
    7506:	4770      	bx	lr

00007508 <NVM_unlock>:
NVM_unlock
(
    uint32_t start_addr,
    uint32_t length
)
{
    7508:	b580      	push	{r7, lr}
    750a:	b090      	sub	sp, #64	; 0x40
    750c:	af00      	add	r7, sp, #0
    750e:	6078      	str	r0, [r7, #4]
    7510:	6039      	str	r1, [r7, #0]
     * to its maximum value (i.e. 15) to ensure successful writes to eNVM. 
     * Store the value of the eNVM configuration before updating it, so 
     * that the prior configuration can be restored when the eNVM write
     * operation has completed. 
     */
    initial_nvm_config = SYSREG->ENVM_CR;
    7512:	f248 0300 	movw	r3, #32768	; 0x8000
    7516:	f2c4 0303 	movt	r3, #16387	; 0x4003
    751a:	68db      	ldr	r3, [r3, #12]
    751c:	627b      	str	r3, [r7, #36]	; 0x24
    SYSREG->ENVM_CR = (initial_nvm_config & NVM_FREQRNG_MASK) | NVM_FREQRNG_MAX;
    751e:	f248 0300 	movw	r3, #32768	; 0x8000
    7522:	f2c4 0303 	movt	r3, #16387	; 0x4003
    7526:	6a7a      	ldr	r2, [r7, #36]	; 0x24
    7528:	f442 52ff 	orr.w	r2, r2, #8160	; 0x1fe0
    752c:	60da      	str	r2, [r3, #12]
    
    /* Check input parameters */
    if((start_addr >= (NVM_BASE_ADDRESS + NVM_TOP_OFFSET)) || \
    752e:	687a      	ldr	r2, [r7, #4]
    7530:	f64f 73fe 	movw	r3, #65534	; 0xfffe
    7534:	f2c6 0307 	movt	r3, #24583	; 0x6007
    7538:	429a      	cmp	r2, r3
    753a:	d80e      	bhi.n	755a <NVM_unlock+0x52>
    753c:	687a      	ldr	r2, [r7, #4]
    753e:	f64f 73fe 	movw	r3, #65534	; 0xfffe
    7542:	f2c0 0307 	movt	r3, #7
    7546:	429a      	cmp	r2, r3
    7548:	d904      	bls.n	7554 <NVM_unlock+0x4c>
    754a:	687a      	ldr	r2, [r7, #4]
    754c:	f06f 4320 	mvn.w	r3, #2684354560	; 0xa0000000
    7550:	429a      	cmp	r2, r3
    7552:	d902      	bls.n	755a <NVM_unlock+0x52>
    7554:	683b      	ldr	r3, [r7, #0]
    7556:	2b00      	cmp	r3, #0
    7558:	d103      	bne.n	7562 <NVM_unlock+0x5a>
        ((start_addr >= NVM_TOP_OFFSET) && \
        (start_addr < NVM_BASE_ADDRESS)) || \
        (!length))
    {
        status =  NVM_INVALID_PARAMETER;
    755a:	f04f 0306 	mov.w	r3, #6
    755e:	73fb      	strb	r3, [r7, #15]
     */
    initial_nvm_config = SYSREG->ENVM_CR;
    SYSREG->ENVM_CR = (initial_nvm_config & NVM_FREQRNG_MASK) | NVM_FREQRNG_MAX;
    
    /* Check input parameters */
    if((start_addr >= (NVM_BASE_ADDRESS + NVM_TOP_OFFSET)) || \
    7560:	e0d5      	b.n	770e <NVM_unlock+0x206>
        status =  NVM_INVALID_PARAMETER;
    }
    else
    {
        /* Ignore upper address bits to ignore remapping setting. */
        nvm_offset = start_addr & NVM_OFFSET_SIGNIFICANT_BITS;  /* Ignore remapping. */
    7562:	687b      	ldr	r3, [r7, #4]
    7564:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
    7568:	f423 0378 	bic.w	r3, r3, #16252928	; 0xf80000
    756c:	613b      	str	r3, [r7, #16]

        status = check_protection_reserved_nvm(nvm_offset, length);
    756e:	6938      	ldr	r0, [r7, #16]
    7570:	6839      	ldr	r1, [r7, #0]
    7572:	f000 fbf3 	bl	7d5c <check_protection_reserved_nvm>
    7576:	4603      	mov	r3, r0
    7578:	73fb      	strb	r3, [r7, #15]

        /* Check  */
        if(NVM_SUCCESS == status)
    757a:	7bfb      	ldrb	r3, [r7, #15]
    757c:	2b00      	cmp	r3, #0
    757e:	f040 80c6 	bne.w	770e <NVM_unlock+0x206>
        {

            first_page = nvm_offset / BYTES_PER_PAGE;
    7582:	693b      	ldr	r3, [r7, #16]
    7584:	ea4f 13d3 	mov.w	r3, r3, lsr #7
    7588:	617b      	str	r3, [r7, #20]
            last_page = (nvm_offset + (length - 1u)) / BYTES_PER_PAGE;
    758a:	683a      	ldr	r2, [r7, #0]
    758c:	693b      	ldr	r3, [r7, #16]
    758e:	4413      	add	r3, r2
    7590:	f103 33ff 	add.w	r3, r3, #4294967295
    7594:	ea4f 13d3 	mov.w	r3, r3, lsr #7
    7598:	61bb      	str	r3, [r7, #24]

            /* Gain exclusive access to eNVM controller */
            status = get_ctrl_access(nvm_offset, length);
    759a:	6938      	ldr	r0, [r7, #16]
    759c:	6839      	ldr	r1, [r7, #0]
    759e:	f000 f917 	bl	77d0 <get_ctrl_access>
    75a2:	4603      	mov	r3, r0
    75a4:	73fb      	strb	r3, [r7, #15]

            /* Unlock eNVM one page at a time. */
            if(NVM_SUCCESS == status)
    75a6:	7bfb      	ldrb	r3, [r7, #15]
    75a8:	2b00      	cmp	r3, #0
    75aa:	f040 80b0 	bne.w	770e <NVM_unlock+0x206>
                uint32_t inc;
                uint32_t * p_nvm32;
                uint32_t errors_and_warnings;


                for(current_page = first_page; (current_page <= last_page) &&
    75ae:	697b      	ldr	r3, [r7, #20]
    75b0:	61fb      	str	r3, [r7, #28]
    75b2:	e09e      	b.n	76f2 <NVM_unlock+0x1ea>
                    ((NVM_SUCCESS == status) ||(NVM_WRITE_THRESHOLD_WARNING == status));
                    ++current_page)
                {
                    uint32_t ctrl_status;

                    if(current_page > PAGES_PER_BLOCK)
    75b4:	69fb      	ldr	r3, [r7, #28]
    75b6:	f5b3 6f00 	cmp.w	r3, #2048	; 0x800
    75ba:	d903      	bls.n	75c4 <NVM_unlock+0xbc>
                    {
                        block = NVM_BLOCK_1;
    75bc:	f04f 0301 	mov.w	r3, #1
    75c0:	62bb      	str	r3, [r7, #40]	; 0x28
    75c2:	e002      	b.n	75ca <NVM_unlock+0xc2>
                    }
                    else
                    {
                        block = NVM_BLOCK_0;
    75c4:	f04f 0300 	mov.w	r3, #0
    75c8:	62bb      	str	r3, [r7, #40]	; 0x28
                    }

                    if(g_nvm[block]->STATUS & MSS_NVM_WR_DENIED)
    75ca:	6aba      	ldr	r2, [r7, #40]	; 0x28
    75cc:	f649 6388 	movw	r3, #40584	; 0x9e88
    75d0:	f2c0 0300 	movt	r3, #0
    75d4:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
    75d8:	f8d3 3120 	ldr.w	r3, [r3, #288]	; 0x120
    75dc:	f403 2380 	and.w	r3, r3, #262144	; 0x40000
    75e0:	2b00      	cmp	r3, #0
    75e2:	d013      	beq.n	760c <NVM_unlock+0x104>
                    {
                        /* Clear the access denied flag */
                        g_nvm[block]->CLRHINT |= ACCESS_DENIED_FLAG_CLEAR;
    75e4:	6aba      	ldr	r2, [r7, #40]	; 0x28
    75e6:	f649 6388 	movw	r3, #40584	; 0x9e88
    75ea:	f2c0 0300 	movt	r3, #0
    75ee:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    75f2:	6ab9      	ldr	r1, [r7, #40]	; 0x28
    75f4:	f649 6388 	movw	r3, #40584	; 0x9e88
    75f8:	f2c0 0300 	movt	r3, #0
    75fc:	f853 3021 	ldr.w	r3, [r3, r1, lsl #2]
    7600:	f8d3 3158 	ldr.w	r3, [r3, #344]	; 0x158
    7604:	f043 0302 	orr.w	r3, r3, #2
    7608:	f8c2 3158 	str.w	r3, [r2, #344]	; 0x158
                    }

                    current_offset = (current_page << 0x7u);
    760c:	69fb      	ldr	r3, [r7, #28]
    760e:	ea4f 13c3 	mov.w	r3, r3, lsl #7
    7612:	623b      	str	r3, [r7, #32]
                    p_nvm32 = (uint32_t *)(NVM_BASE_ADDRESS + current_offset);
    7614:	6a3b      	ldr	r3, [r7, #32]
    7616:	f103 43c0 	add.w	r3, r3, #1610612736	; 0x60000000
    761a:	633b      	str	r3, [r7, #48]	; 0x30
                     
                    for(inc = 0u; inc < WD_WORD_SIZE; ++inc)
    761c:	f04f 0300 	mov.w	r3, #0
    7620:	62fb      	str	r3, [r7, #44]	; 0x2c
    7622:	e015      	b.n	7650 <NVM_unlock+0x148>
                    {
                        g_nvm32[block]->WD[inc] = p_nvm32[inc];
    7624:	6aba      	ldr	r2, [r7, #40]	; 0x28
    7626:	f649 6390 	movw	r3, #40592	; 0x9e90
    762a:	f2c0 0300 	movt	r3, #0
    762e:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
    7632:	6afa      	ldr	r2, [r7, #44]	; 0x2c
    7634:	6af9      	ldr	r1, [r7, #44]	; 0x2c
    7636:	ea4f 0081 	mov.w	r0, r1, lsl #2
    763a:	6b39      	ldr	r1, [r7, #48]	; 0x30
    763c:	4401      	add	r1, r0
    763e:	6809      	ldr	r1, [r1, #0]
    7640:	f102 0220 	add.w	r2, r2, #32
    7644:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
                    }

                    current_offset = (current_page << 0x7u);
                    p_nvm32 = (uint32_t *)(NVM_BASE_ADDRESS + current_offset);
                     
                    for(inc = 0u; inc < WD_WORD_SIZE; ++inc)
    7648:	6afb      	ldr	r3, [r7, #44]	; 0x2c
    764a:	f103 0301 	add.w	r3, r3, #1
    764e:	62fb      	str	r3, [r7, #44]	; 0x2c
    7650:	6afb      	ldr	r3, [r7, #44]	; 0x2c
    7652:	2b1f      	cmp	r3, #31
    7654:	d9e6      	bls.n	7624 <NVM_unlock+0x11c>
                    {
                        g_nvm32[block]->WD[inc] = p_nvm32[inc];
                    }
                    
                    g_nvm[block]->PAGE_LOCK = NVM_DO_NOT_LOCK_PAGE;
    7656:	6aba      	ldr	r2, [r7, #40]	; 0x28
    7658:	f649 6388 	movw	r3, #40584	; 0x9e88
    765c:	f2c0 0300 	movt	r3, #0
    7660:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
    7664:	f04f 0200 	mov.w	r2, #0
    7668:	f8c3 2140 	str.w	r2, [r3, #320]	; 0x140
                    g_nvm[block]->CMD = USER_UNLOCK | (current_offset & PAGE_ADDR_MASK);
    766c:	6aba      	ldr	r2, [r7, #40]	; 0x28
    766e:	f649 6388 	movw	r3, #40584	; 0x9e88
    7672:	f2c0 0300 	movt	r3, #0
    7676:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    767a:	6a3b      	ldr	r3, [r7, #32]
    767c:	f023 5398 	bic.w	r3, r3, #318767104	; 0x13000000
    7680:	f023 037f 	bic.w	r3, r3, #127	; 0x7f
    7684:	f043 5398 	orr.w	r3, r3, #318767104	; 0x13000000
    7688:	f8c2 3148 	str.w	r3, [r2, #328]	; 0x148

                    /* Issue program command */
                    g_nvm[block]->CMD = PROG_ADS | (current_offset & PAGE_ADDR_MASK);
    768c:	6aba      	ldr	r2, [r7, #40]	; 0x28
    768e:	f649 6388 	movw	r3, #40584	; 0x9e88
    7692:	f2c0 0300 	movt	r3, #0
    7696:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    769a:	6a3b      	ldr	r3, [r7, #32]
    769c:	f023 6300 	bic.w	r3, r3, #134217728	; 0x8000000
    76a0:	f023 037f 	bic.w	r3, r3, #127	; 0x7f
    76a4:	f043 6300 	orr.w	r3, r3, #134217728	; 0x8000000
    76a8:	f8c2 3148 	str.w	r3, [r2, #328]	; 0x148

                    /* Wait for NVM to become ready. */
                    ctrl_status = wait_nvm_ready(block);
    76ac:	6ab8      	ldr	r0, [r7, #40]	; 0x28
    76ae:	f000 f919 	bl	78e4 <wait_nvm_ready>
    76b2:	4603      	mov	r3, r0
    76b4:	63bb      	str	r3, [r7, #56]	; 0x38

                    /* Check for errors and warnings. */
                    errors_and_warnings = ctrl_status & (WRITE_ERROR_MASK | MSS_NVM_WRCNT_OVER);
    76b6:	6bba      	ldr	r2, [r7, #56]	; 0x38
    76b8:	f240 033e 	movw	r3, #62	; 0x3e
    76bc:	f2c0 0304 	movt	r3, #4
    76c0:	ea02 0303 	and.w	r3, r2, r3
    76c4:	637b      	str	r3, [r7, #52]	; 0x34
                    if(errors_and_warnings)
    76c6:	6b7b      	ldr	r3, [r7, #52]	; 0x34
    76c8:	2b00      	cmp	r3, #0
    76ca:	d00e      	beq.n	76ea <NVM_unlock+0x1e2>
                    {
                        uint32_t nvm_hw_status;
                        nvm_hw_status = g_nvm[block]->STATUS;
    76cc:	6aba      	ldr	r2, [r7, #40]	; 0x28
    76ce:	f649 6388 	movw	r3, #40584	; 0x9e88
    76d2:	f2c0 0300 	movt	r3, #0
    76d6:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
    76da:	f8d3 3120 	ldr.w	r3, [r3, #288]	; 0x120
    76de:	63fb      	str	r3, [r7, #60]	; 0x3c
                        status = get_error_code(nvm_hw_status);
    76e0:	6bf8      	ldr	r0, [r7, #60]	; 0x3c
    76e2:	f7ff fedf 	bl	74a4 <get_error_code>
    76e6:	4603      	mov	r3, r0
    76e8:	73fb      	strb	r3, [r7, #15]
                uint32_t errors_and_warnings;


                for(current_page = first_page; (current_page <= last_page) &&
                    ((NVM_SUCCESS == status) ||(NVM_WRITE_THRESHOLD_WARNING == status));
                    ++current_page)
    76ea:	69fb      	ldr	r3, [r7, #28]
    76ec:	f103 0301 	add.w	r3, r3, #1
    76f0:	61fb      	str	r3, [r7, #28]
                uint32_t inc;
                uint32_t * p_nvm32;
                uint32_t errors_and_warnings;


                for(current_page = first_page; (current_page <= last_page) &&
    76f2:	69fa      	ldr	r2, [r7, #28]
    76f4:	69bb      	ldr	r3, [r7, #24]
    76f6:	429a      	cmp	r2, r3
    76f8:	d807      	bhi.n	770a <NVM_unlock+0x202>
    76fa:	7bfb      	ldrb	r3, [r7, #15]
    76fc:	2b00      	cmp	r3, #0
    76fe:	f43f af59 	beq.w	75b4 <NVM_unlock+0xac>
    7702:	7bfb      	ldrb	r3, [r7, #15]
    7704:	2b04      	cmp	r3, #4
    7706:	f43f af55 	beq.w	75b4 <NVM_unlock+0xac>
                        status = get_error_code(nvm_hw_status);
                    }
                }

                /* Release eNVM controllers so that other masters can gain access to it. */
                release_ctrl_access();
    770a:	f000 f8a1 	bl	7850 <release_ctrl_access>
            }
        }
    }
    
    /* Restore back to original value. */
    SYSREG->ENVM_CR = initial_nvm_config;
    770e:	f248 0300 	movw	r3, #32768	; 0x8000
    7712:	f2c4 0303 	movt	r3, #16387	; 0x4003
    7716:	6a7a      	ldr	r2, [r7, #36]	; 0x24
    7718:	60da      	str	r2, [r3, #12]
    
    return status;
    771a:	7bfb      	ldrb	r3, [r7, #15]
}
    771c:	4618      	mov	r0, r3
    771e:	f107 0740 	add.w	r7, r7, #64	; 0x40
    7722:	46bd      	mov	sp, r7
    7724:	bd80      	pop	{r7, pc}
    7726:	bf00      	nop

00007728 <request_nvm_access>:
#define CORTEX_M3_ACCESS_GRANTED    0x05u

static uint8_t g_envm_ctrl_locks = 0x00u;

static nvm_status_t request_nvm_access(uint32_t nvm_block_id)
{
    7728:	b480      	push	{r7}
    772a:	b087      	sub	sp, #28
    772c:	af00      	add	r7, sp, #0
    772e:	6078      	str	r0, [r7, #4]
    nvm_status_t status = NVM_SUCCESS;
    7730:	f04f 0300 	mov.w	r3, #0
    7734:	74fb      	strb	r3, [r7, #19]
    
    /*
     * Use the SystemCoreClock frequency to compute a delay counter value giving
     * us a delay in the 500ms range. This is a very approximate delay.
     */
    timeout_counter = SystemCoreClock / 16u;
    7736:	f240 0310 	movw	r3, #16
    773a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    773e:	681b      	ldr	r3, [r3, #0]
    7740:	ea4f 1313 	mov.w	r3, r3, lsr #4
    7744:	60fb      	str	r3, [r7, #12]
    
    /*
     * Gain access to eNVM controller.
     */
    do {
        g_nvm[nvm_block_id]->REQ_ACCESS = REQUEST_NVM_ACCESS;
    7746:	687a      	ldr	r2, [r7, #4]
    7748:	f649 6388 	movw	r3, #40584	; 0x9e88
    774c:	f2c0 0300 	movt	r3, #0
    7750:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
    7754:	f04f 0201 	mov.w	r2, #1
    7758:	f8c3 21fc 	str.w	r2, [r3, #508]	; 0x1fc
        access = g_nvm[nvm_block_id]->REQ_ACCESS;
    775c:	687a      	ldr	r2, [r7, #4]
    775e:	f649 6388 	movw	r3, #40584	; 0x9e88
    7762:	f2c0 0300 	movt	r3, #0
    7766:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
    776a:	f8d3 31fc 	ldr.w	r3, [r3, #508]	; 0x1fc
    776e:	617b      	str	r3, [r7, #20]
        if(access != CORTEX_M3_ACCESS_GRANTED)
    7770:	697b      	ldr	r3, [r7, #20]
    7772:	2b05      	cmp	r3, #5
    7774:	d009      	beq.n	778a <request_nvm_access+0x62>
            /*
             * Time out if another AHB master locked access to eNVM to prevent
             * the Cortex-M3 from locking up on eNVM write if some other part
             * of the system fails from releasing the eNVM.
             */
            --timeout_counter;
    7776:	68fb      	ldr	r3, [r7, #12]
    7778:	f103 33ff 	add.w	r3, r3, #4294967295
    777c:	60fb      	str	r3, [r7, #12]
            if(0u == timeout_counter)
    777e:	68fb      	ldr	r3, [r7, #12]
    7780:	2b00      	cmp	r3, #0
    7782:	d102      	bne.n	778a <request_nvm_access+0x62>
            {
                status = NVM_IN_USE_BY_OTHER_MASTER;
    7784:	f04f 0305 	mov.w	r3, #5
    7788:	74fb      	strb	r3, [r7, #19]
            }
        }
    } while((access != CORTEX_M3_ACCESS_GRANTED) && (NVM_SUCCESS == status));
    778a:	697b      	ldr	r3, [r7, #20]
    778c:	2b05      	cmp	r3, #5
    778e:	d002      	beq.n	7796 <request_nvm_access+0x6e>
    7790:	7cfb      	ldrb	r3, [r7, #19]
    7792:	2b00      	cmp	r3, #0
    7794:	d0d7      	beq.n	7746 <request_nvm_access+0x1e>
    
    /*
     * Mark controller as locked if successful so that it will be unlocked by a
     * call to release_ctrl_access.
     */
    if(NVM_SUCCESS == status)
    7796:	7cfb      	ldrb	r3, [r7, #19]
    7798:	2b00      	cmp	r3, #0
    779a:	d112      	bne.n	77c2 <request_nvm_access+0x9a>
    {
        g_envm_ctrl_locks |= (uint8_t)((uint32_t)0x01 << nvm_block_id);
    779c:	687b      	ldr	r3, [r7, #4]
    779e:	f04f 0201 	mov.w	r2, #1
    77a2:	fa02 f303 	lsl.w	r3, r2, r3
    77a6:	b2da      	uxtb	r2, r3
    77a8:	f240 1388 	movw	r3, #392	; 0x188
    77ac:	f2c2 0300 	movt	r3, #8192	; 0x2000
    77b0:	781b      	ldrb	r3, [r3, #0]
    77b2:	ea42 0303 	orr.w	r3, r2, r3
    77b6:	b2da      	uxtb	r2, r3
    77b8:	f240 1388 	movw	r3, #392	; 0x188
    77bc:	f2c2 0300 	movt	r3, #8192	; 0x2000
    77c0:	701a      	strb	r2, [r3, #0]
    }
    
    return status;
    77c2:	7cfb      	ldrb	r3, [r7, #19]
}
    77c4:	4618      	mov	r0, r3
    77c6:	f107 071c 	add.w	r7, r7, #28
    77ca:	46bd      	mov	sp, r7
    77cc:	bc80      	pop	{r7}
    77ce:	4770      	bx	lr

000077d0 <get_ctrl_access>:

/**************************************************************************//**
 * Get access to eNVM controller for eNVM0 and eNVM1
 */
static nvm_status_t get_ctrl_access(uint32_t nvm_offset, uint32_t length)
{
    77d0:	b580      	push	{r7, lr}
    77d2:	b084      	sub	sp, #16
    77d4:	af00      	add	r7, sp, #0
    77d6:	6078      	str	r0, [r7, #4]
    77d8:	6039      	str	r1, [r7, #0]
    nvm_status_t access_req_status;
    
    /*
     * Gain access to eNVM controller(s).
     */
    if(nvm_offset < NVM1_BOTTOM_OFFSET)
    77da:	687a      	ldr	r2, [r7, #4]
    77dc:	f64f 73ff 	movw	r3, #65535	; 0xffff
    77e0:	f2c0 0303 	movt	r3, #3
    77e4:	429a      	cmp	r2, r3
    77e6:	d821      	bhi.n	782c <get_ctrl_access+0x5c>
    {
        access_req_status = request_nvm_access(NVM_BLOCK_0);
    77e8:	f04f 0000 	mov.w	r0, #0
    77ec:	f7ff ff9c 	bl	7728 <request_nvm_access>
    77f0:	4603      	mov	r3, r0
    77f2:	72fb      	strb	r3, [r7, #11]
        if(NVM_SUCCESS == access_req_status)
    77f4:	7afb      	ldrb	r3, [r7, #11]
    77f6:	2b00      	cmp	r3, #0
    77f8:	d11f      	bne.n	783a <get_ctrl_access+0x6a>
        {
            uint32_t last_offset;
            last_offset = nvm_offset + (length - 0x1u);
    77fa:	683a      	ldr	r2, [r7, #0]
    77fc:	687b      	ldr	r3, [r7, #4]
    77fe:	4413      	add	r3, r2
    7800:	f103 33ff 	add.w	r3, r3, #4294967295
    7804:	60fb      	str	r3, [r7, #12]
            if(last_offset >= NVM1_BOTTOM_OFFSET)
    7806:	68fa      	ldr	r2, [r7, #12]
    7808:	f64f 73ff 	movw	r3, #65535	; 0xffff
    780c:	f2c0 0303 	movt	r3, #3
    7810:	429a      	cmp	r2, r3
    7812:	d914      	bls.n	783e <get_ctrl_access+0x6e>
            {
                access_req_status = request_nvm_access(NVM_BLOCK_1);
    7814:	f04f 0001 	mov.w	r0, #1
    7818:	f7ff ff86 	bl	7728 <request_nvm_access>
    781c:	4603      	mov	r3, r0
    781e:	72fb      	strb	r3, [r7, #11]
                if(NVM_IN_USE_BY_OTHER_MASTER == access_req_status)
    7820:	7afb      	ldrb	r3, [r7, #11]
    7822:	2b05      	cmp	r3, #5
    7824:	d10d      	bne.n	7842 <get_ctrl_access+0x72>
                {
                    release_ctrl_access();
    7826:	f000 f813 	bl	7850 <release_ctrl_access>
    782a:	e00b      	b.n	7844 <get_ctrl_access+0x74>
            }
        }
    }
    else
    {
        access_req_status = request_nvm_access(NVM_BLOCK_1);
    782c:	f04f 0001 	mov.w	r0, #1
    7830:	f7ff ff7a 	bl	7728 <request_nvm_access>
    7834:	4603      	mov	r3, r0
    7836:	72fb      	strb	r3, [r7, #11]
    7838:	e004      	b.n	7844 <get_ctrl_access+0x74>
            if(last_offset >= NVM1_BOTTOM_OFFSET)
            {
                access_req_status = request_nvm_access(NVM_BLOCK_1);
                if(NVM_IN_USE_BY_OTHER_MASTER == access_req_status)
                {
                    release_ctrl_access();
    783a:	bf00      	nop
    783c:	e002      	b.n	7844 <get_ctrl_access+0x74>
    783e:	bf00      	nop
    7840:	e000      	b.n	7844 <get_ctrl_access+0x74>
    7842:	bf00      	nop
    else
    {
        access_req_status = request_nvm_access(NVM_BLOCK_1);
    }
    
    return access_req_status;
    7844:	7afb      	ldrb	r3, [r7, #11]
}
    7846:	4618      	mov	r0, r3
    7848:	f107 0710 	add.w	r7, r7, #16
    784c:	46bd      	mov	sp, r7
    784e:	bd80      	pop	{r7, pc}

00007850 <release_ctrl_access>:
 */
#define NVM_BLOCK_0_LOCK_MASK   0x01u
#define NVM_BLOCK_1_LOCK_MASK   0x02u

static void release_ctrl_access(void)
{
    7850:	b480      	push	{r7}
    7852:	b083      	sub	sp, #12
    7854:	af00      	add	r7, sp, #0
    uint8_t block_locked;
    
    block_locked = g_envm_ctrl_locks & NVM_BLOCK_0_LOCK_MASK;
    7856:	f240 1388 	movw	r3, #392	; 0x188
    785a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    785e:	781b      	ldrb	r3, [r3, #0]
    7860:	f003 0301 	and.w	r3, r3, #1
    7864:	71fb      	strb	r3, [r7, #7]
    if(block_locked)
    7866:	79fb      	ldrb	r3, [r7, #7]
    7868:	2b00      	cmp	r3, #0
    786a:	d015      	beq.n	7898 <release_ctrl_access+0x48>
    {
        g_nvm[NVM_BLOCK_0]->REQ_ACCESS = 0x00u;
    786c:	f649 6388 	movw	r3, #40584	; 0x9e88
    7870:	f2c0 0300 	movt	r3, #0
    7874:	681b      	ldr	r3, [r3, #0]
    7876:	f04f 0200 	mov.w	r2, #0
    787a:	f8c3 21fc 	str.w	r2, [r3, #508]	; 0x1fc
        g_envm_ctrl_locks &= ~NVM_BLOCK_0_LOCK_MASK;
    787e:	f240 1388 	movw	r3, #392	; 0x188
    7882:	f2c2 0300 	movt	r3, #8192	; 0x2000
    7886:	781b      	ldrb	r3, [r3, #0]
    7888:	461a      	mov	r2, r3
    788a:	f002 02fe 	and.w	r2, r2, #254	; 0xfe
    788e:	f240 1388 	movw	r3, #392	; 0x188
    7892:	f2c2 0300 	movt	r3, #8192	; 0x2000
    7896:	701a      	strb	r2, [r3, #0]
    }
    
    block_locked = g_envm_ctrl_locks & NVM_BLOCK_1_LOCK_MASK;
    7898:	f240 1388 	movw	r3, #392	; 0x188
    789c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    78a0:	781b      	ldrb	r3, [r3, #0]
    78a2:	f003 0302 	and.w	r3, r3, #2
    78a6:	71fb      	strb	r3, [r7, #7]
    if(block_locked)
    78a8:	79fb      	ldrb	r3, [r7, #7]
    78aa:	2b00      	cmp	r3, #0
    78ac:	d015      	beq.n	78da <release_ctrl_access+0x8a>
    {
        g_nvm[NVM_BLOCK_1]->REQ_ACCESS = 0x00u;
    78ae:	f649 6388 	movw	r3, #40584	; 0x9e88
    78b2:	f2c0 0300 	movt	r3, #0
    78b6:	685b      	ldr	r3, [r3, #4]
    78b8:	f04f 0200 	mov.w	r2, #0
    78bc:	f8c3 21fc 	str.w	r2, [r3, #508]	; 0x1fc
        g_envm_ctrl_locks &= ~NVM_BLOCK_1_LOCK_MASK;
    78c0:	f240 1388 	movw	r3, #392	; 0x188
    78c4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    78c8:	781b      	ldrb	r3, [r3, #0]
    78ca:	461a      	mov	r2, r3
    78cc:	f002 02fd 	and.w	r2, r2, #253	; 0xfd
    78d0:	f240 1388 	movw	r3, #392	; 0x188
    78d4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    78d8:	701a      	strb	r2, [r3, #0]
    }
}
    78da:	f107 070c 	add.w	r7, r7, #12
    78de:	46bd      	mov	sp, r7
    78e0:	bc80      	pop	{r7}
    78e2:	4770      	bx	lr

000078e4 <wait_nvm_ready>:

/**************************************************************************//**
 * Wait for NVM to become ready from busy state
 */
static uint32_t wait_nvm_ready(uint32_t block) 
{
    78e4:	b480      	push	{r7}
    78e6:	b087      	sub	sp, #28
    78e8:	af00      	add	r7, sp, #0
    78ea:	6078      	str	r0, [r7, #4]
    /*
     * Wait for NVM to become ready.
     * We must ensure that we can read the ready bit set to 1 twice before we
     * can assume that the other status bits are valid. See SmartFusion2 errata.
     */
    for(inc = 0u; inc < 2u; ++inc)
    78ec:	f04f 0300 	mov.w	r3, #0
    78f0:	617b      	str	r3, [r7, #20]
    78f2:	e014      	b.n	791e <wait_nvm_ready+0x3a>
    {
        do {
            ctrl_status = g_nvm[block]->STATUS;
    78f4:	687a      	ldr	r2, [r7, #4]
    78f6:	f649 6388 	movw	r3, #40584	; 0x9e88
    78fa:	f2c0 0300 	movt	r3, #0
    78fe:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
    7902:	f8d3 3120 	ldr.w	r3, [r3, #288]	; 0x120
    7906:	60fb      	str	r3, [r7, #12]
            ctrl_ready = ctrl_status  & MSS_NVM_BUSY_B;
    7908:	68fb      	ldr	r3, [r7, #12]
    790a:	f003 0301 	and.w	r3, r3, #1
    790e:	613b      	str	r3, [r7, #16]
        } while(0u == ctrl_ready);
    7910:	693b      	ldr	r3, [r7, #16]
    7912:	2b00      	cmp	r3, #0
    7914:	d0ee      	beq.n	78f4 <wait_nvm_ready+0x10>
    /*
     * Wait for NVM to become ready.
     * We must ensure that we can read the ready bit set to 1 twice before we
     * can assume that the other status bits are valid. See SmartFusion2 errata.
     */
    for(inc = 0u; inc < 2u; ++inc)
    7916:	697b      	ldr	r3, [r7, #20]
    7918:	f103 0301 	add.w	r3, r3, #1
    791c:	617b      	str	r3, [r7, #20]
    791e:	697b      	ldr	r3, [r7, #20]
    7920:	2b01      	cmp	r3, #1
    7922:	d9e7      	bls.n	78f4 <wait_nvm_ready+0x10>
            ctrl_status = g_nvm[block]->STATUS;
            ctrl_ready = ctrl_status  & MSS_NVM_BUSY_B;
        } while(0u == ctrl_ready);
    }
    
    return ctrl_status;
    7924:	68fb      	ldr	r3, [r7, #12]
}
    7926:	4618      	mov	r0, r3
    7928:	f107 071c 	add.w	r7, r7, #28
    792c:	46bd      	mov	sp, r7
    792e:	bc80      	pop	{r7}
    7930:	4770      	bx	lr
    7932:	bf00      	nop

00007934 <write_nvm>:
    const uint8_t * pidata,
    uint32_t  length,
    uint32_t  lock_page,
    uint32_t * p_status
)
{
    7934:	b580      	push	{r7, lr}
    7936:	b08a      	sub	sp, #40	; 0x28
    7938:	af00      	add	r7, sp, #0
    793a:	60f8      	str	r0, [r7, #12]
    793c:	60b9      	str	r1, [r7, #8]
    793e:	607a      	str	r2, [r7, #4]
    7940:	603b      	str	r3, [r7, #0]
    uint32_t length_written;
    uint32_t offset;
   
    *p_status = 0u;
    7942:	6b3b      	ldr	r3, [r7, #48]	; 0x30
    7944:	f04f 0200 	mov.w	r2, #0
    7948:	601a      	str	r2, [r3, #0]
    
    offset = addr & NVM_OFFSET_SIGNIFICANT_BITS;  /* Ignore remapping. */
    794a:	68fb      	ldr	r3, [r7, #12]
    794c:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
    7950:	f423 0378 	bic.w	r3, r3, #16252928	; 0xf80000
    7954:	61fb      	str	r3, [r7, #28]
    
    ASSERT(offset <= NVM1_TOP_OFFSET);
    7956:	69fa      	ldr	r2, [r7, #28]
    7958:	f64f 73ff 	movw	r3, #65535	; 0xffff
    795c:	f2c0 0307 	movt	r3, #7
    7960:	429a      	cmp	r2, r3
    7962:	d900      	bls.n	7966 <write_nvm+0x32>
    7964:	be00      	bkpt	0x0000
    
    /* Adjust length to fit within one page. */
    length_written = get_remaining_page_length(offset, length);
    7966:	69f8      	ldr	r0, [r7, #28]
    7968:	6879      	ldr	r1, [r7, #4]
    796a:	f000 f89f 	bl	7aac <get_remaining_page_length>
    796e:	4603      	mov	r3, r0
    7970:	61bb      	str	r3, [r7, #24]
    
    if(offset <= NVM1_TOP_OFFSET)
    7972:	69fa      	ldr	r2, [r7, #28]
    7974:	f64f 73ff 	movw	r3, #65535	; 0xffff
    7978:	f2c0 0307 	movt	r3, #7
    797c:	429a      	cmp	r2, r3
    797e:	f200 808f 	bhi.w	7aa0 <write_nvm+0x16c>
    {
        uint32_t block;
        volatile uint32_t ctrl_status;
        uint32_t errors;
        
        if(offset < NVM1_BOTTOM_OFFSET)
    7982:	69fa      	ldr	r2, [r7, #28]
    7984:	f64f 73ff 	movw	r3, #65535	; 0xffff
    7988:	f2c0 0303 	movt	r3, #3
    798c:	429a      	cmp	r2, r3
    798e:	d803      	bhi.n	7998 <write_nvm+0x64>
        {
            block = NVM_BLOCK_0;
    7990:	f04f 0300 	mov.w	r3, #0
    7994:	623b      	str	r3, [r7, #32]
    7996:	e006      	b.n	79a6 <write_nvm+0x72>
        }
        else
        {
            block = NVM_BLOCK_1;
    7998:	f04f 0301 	mov.w	r3, #1
    799c:	623b      	str	r3, [r7, #32]
            offset = offset - NVM1_BOTTOM_OFFSET;
    799e:	69fb      	ldr	r3, [r7, #28]
    79a0:	f5a3 2380 	sub.w	r3, r3, #262144	; 0x40000
    79a4:	61fb      	str	r3, [r7, #28]
        }
        
        if(g_nvm[block]->STATUS & MSS_NVM_WR_DENIED)
    79a6:	6a3a      	ldr	r2, [r7, #32]
    79a8:	f649 6388 	movw	r3, #40584	; 0x9e88
    79ac:	f2c0 0300 	movt	r3, #0
    79b0:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
    79b4:	f8d3 3120 	ldr.w	r3, [r3, #288]	; 0x120
    79b8:	f403 2380 	and.w	r3, r3, #262144	; 0x40000
    79bc:	2b00      	cmp	r3, #0
    79be:	d013      	beq.n	79e8 <write_nvm+0xb4>
        {
            /* Clear the access denied flag */
            g_nvm[block]->CLRHINT |= ACCESS_DENIED_FLAG_CLEAR;
    79c0:	6a3a      	ldr	r2, [r7, #32]
    79c2:	f649 6388 	movw	r3, #40584	; 0x9e88
    79c6:	f2c0 0300 	movt	r3, #0
    79ca:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    79ce:	6a39      	ldr	r1, [r7, #32]
    79d0:	f649 6388 	movw	r3, #40584	; 0x9e88
    79d4:	f2c0 0300 	movt	r3, #0
    79d8:	f853 3021 	ldr.w	r3, [r3, r1, lsl #2]
    79dc:	f8d3 3158 	ldr.w	r3, [r3, #344]	; 0x158
    79e0:	f043 0302 	orr.w	r3, r3, #2
    79e4:	f8c2 3158 	str.w	r3, [r2, #344]	; 0x158
        }

        fill_wd_buffer(pidata, length_written, block, offset);
    79e8:	68b8      	ldr	r0, [r7, #8]
    79ea:	69b9      	ldr	r1, [r7, #24]
    79ec:	6a3a      	ldr	r2, [r7, #32]
    79ee:	69fb      	ldr	r3, [r7, #28]
    79f0:	f000 f87e 	bl	7af0 <fill_wd_buffer>

        /* Set requested locking option. */
        g_nvm[block]->PAGE_LOCK = lock_page;
    79f4:	6a3a      	ldr	r2, [r7, #32]
    79f6:	f649 6388 	movw	r3, #40584	; 0x9e88
    79fa:	f2c0 0300 	movt	r3, #0
    79fe:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
    7a02:	683a      	ldr	r2, [r7, #0]
    7a04:	f8c3 2140 	str.w	r2, [r3, #320]	; 0x140
        
        /* Issue program command */
        g_nvm[block]->CMD = PROG_ADS | (offset & PAGE_ADDR_MASK);
    7a08:	6a3a      	ldr	r2, [r7, #32]
    7a0a:	f649 6388 	movw	r3, #40584	; 0x9e88
    7a0e:	f2c0 0300 	movt	r3, #0
    7a12:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    7a16:	69fb      	ldr	r3, [r7, #28]
    7a18:	f023 6300 	bic.w	r3, r3, #134217728	; 0x8000000
    7a1c:	f023 037f 	bic.w	r3, r3, #127	; 0x7f
    7a20:	f043 6300 	orr.w	r3, r3, #134217728	; 0x8000000
    7a24:	f8c2 3148 	str.w	r3, [r2, #328]	; 0x148
        
        /* Wait for NVM to become ready. */
        ctrl_status = wait_nvm_ready(block);
    7a28:	6a38      	ldr	r0, [r7, #32]
    7a2a:	f7ff ff5b 	bl	78e4 <wait_nvm_ready>
    7a2e:	4603      	mov	r3, r0
    7a30:	617b      	str	r3, [r7, #20]

        /* Check for errors. */
        errors = ctrl_status & WRITE_ERROR_MASK;
    7a32:	697a      	ldr	r2, [r7, #20]
    7a34:	f240 031e 	movw	r3, #30
    7a38:	f2c0 0304 	movt	r3, #4
    7a3c:	ea02 0303 	and.w	r3, r2, r3
    7a40:	627b      	str	r3, [r7, #36]	; 0x24
        if(errors)
    7a42:	6a7b      	ldr	r3, [r7, #36]	; 0x24
    7a44:	2b00      	cmp	r3, #0
    7a46:	d00b      	beq.n	7a60 <write_nvm+0x12c>
        {
            *p_status = g_nvm[block]->STATUS;
    7a48:	6a3a      	ldr	r2, [r7, #32]
    7a4a:	f649 6388 	movw	r3, #40584	; 0x9e88
    7a4e:	f2c0 0300 	movt	r3, #0
    7a52:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
    7a56:	f8d3 2120 	ldr.w	r2, [r3, #288]	; 0x120
    7a5a:	6b3b      	ldr	r3, [r7, #48]	; 0x30
    7a5c:	601a      	str	r2, [r3, #0]
    7a5e:	e01f      	b.n	7aa0 <write_nvm+0x16c>
        }
        else
        {
            /* Perform a verify. */
            g_nvm[block]->CMD = VERIFY_ADS | (offset & PAGE_ADDR_MASK);
    7a60:	6a3a      	ldr	r2, [r7, #32]
    7a62:	f649 6388 	movw	r3, #40584	; 0x9e88
    7a66:	f2c0 0300 	movt	r3, #0
    7a6a:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    7a6e:	69fb      	ldr	r3, [r7, #28]
    7a70:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
    7a74:	f023 037f 	bic.w	r3, r3, #127	; 0x7f
    7a78:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
    7a7c:	f8c2 3148 	str.w	r3, [r2, #328]	; 0x148
            /* Wait for NVM to become ready. */
            ctrl_status = wait_nvm_ready(block);
    7a80:	6a38      	ldr	r0, [r7, #32]
    7a82:	f7ff ff2f 	bl	78e4 <wait_nvm_ready>
    7a86:	4603      	mov	r3, r0
    7a88:	617b      	str	r3, [r7, #20]

            *p_status = g_nvm[block]->STATUS;
    7a8a:	6a3a      	ldr	r2, [r7, #32]
    7a8c:	f649 6388 	movw	r3, #40584	; 0x9e88
    7a90:	f2c0 0300 	movt	r3, #0
    7a94:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
    7a98:	f8d3 2120 	ldr.w	r2, [r3, #288]	; 0x120
    7a9c:	6b3b      	ldr	r3, [r7, #48]	; 0x30
    7a9e:	601a      	str	r2, [r3, #0]
        }
    }
    
    return length_written;
    7aa0:	69bb      	ldr	r3, [r7, #24]
}
    7aa2:	4618      	mov	r0, r3
    7aa4:	f107 0728 	add.w	r7, r7, #40	; 0x28
    7aa8:	46bd      	mov	sp, r7
    7aaa:	bd80      	pop	{r7, pc}

00007aac <get_remaining_page_length>:
  indicates that the WD[] buffer will have to be seeded with the existing
  content of the eNVM before copying the data to program to eNVM into the WD[]
  buffer.
 */
static uint32_t get_remaining_page_length(uint32_t offset, uint32_t length)
{
    7aac:	b480      	push	{r7}
    7aae:	b085      	sub	sp, #20
    7ab0:	af00      	add	r7, sp, #0
    7ab2:	6078      	str	r0, [r7, #4]
    7ab4:	6039      	str	r1, [r7, #0]
    uint32_t start_page_plus_one;
    uint32_t last_page;
    
    start_page_plus_one = (offset / BYTES_PER_PAGE) + 1u;
    7ab6:	687b      	ldr	r3, [r7, #4]
    7ab8:	ea4f 13d3 	mov.w	r3, r3, lsr #7
    7abc:	f103 0301 	add.w	r3, r3, #1
    7ac0:	60bb      	str	r3, [r7, #8]
    last_page = (offset + length) / BYTES_PER_PAGE;
    7ac2:	687a      	ldr	r2, [r7, #4]
    7ac4:	683b      	ldr	r3, [r7, #0]
    7ac6:	4413      	add	r3, r2
    7ac8:	ea4f 13d3 	mov.w	r3, r3, lsr #7
    7acc:	60fb      	str	r3, [r7, #12]
    if(last_page >= start_page_plus_one)
    7ace:	68fa      	ldr	r2, [r7, #12]
    7ad0:	68bb      	ldr	r3, [r7, #8]
    7ad2:	429a      	cmp	r2, r3
    7ad4:	d305      	bcc.n	7ae2 <get_remaining_page_length+0x36>
    {
        length = BYTES_PER_PAGE - (offset % BYTES_PER_PAGE);
    7ad6:	687b      	ldr	r3, [r7, #4]
    7ad8:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    7adc:	f1c3 0380 	rsb	r3, r3, #128	; 0x80
    7ae0:	603b      	str	r3, [r7, #0]
    }
    
    return length;
    7ae2:	683b      	ldr	r3, [r7, #0]
}
    7ae4:	4618      	mov	r0, r3
    7ae6:	f107 0714 	add.w	r7, r7, #20
    7aea:	46bd      	mov	sp, r7
    7aec:	bc80      	pop	{r7}
    7aee:	4770      	bx	lr

00007af0 <fill_wd_buffer>:
    const uint8_t * p_data,
    uint32_t  length,
    uint32_t block,
    uint32_t offset
)
{
    7af0:	b480      	push	{r7}
    7af2:	b08b      	sub	sp, #44	; 0x2c
    7af4:	af00      	add	r7, sp, #0
    7af6:	60f8      	str	r0, [r7, #12]
    7af8:	60b9      	str	r1, [r7, #8]
    7afa:	607a      	str	r2, [r7, #4]
    7afc:	603b      	str	r3, [r7, #0]
    uint32_t inc;
    uint32_t wd_offset;
    
    if(length != BYTES_PER_PAGE)
    7afe:	68bb      	ldr	r3, [r7, #8]
    7b00:	2b80      	cmp	r3, #128	; 0x80
    7b02:	d067      	beq.n	7bd4 <fill_wd_buffer+0xe4>
        uint32_t first_non_written_word;
        /* 
         * Fill beginning of WD[] with current content of NVM page that must not
         * be overwritten.
         */
        p_nvm32 = (uint32_t *)((NVM_BASE_ADDRESS + offset + (block * NVM1_BOTTOM_OFFSET)) & PAGE_ADDR_MASK);
    7b04:	687b      	ldr	r3, [r7, #4]
    7b06:	ea4f 4283 	mov.w	r2, r3, lsl #18
    7b0a:	683b      	ldr	r3, [r7, #0]
    7b0c:	4413      	add	r3, r2
    7b0e:	f103 43c0 	add.w	r3, r3, #1610612736	; 0x60000000
    7b12:	f023 037f 	bic.w	r3, r3, #127	; 0x7f
    7b16:	61fb      	str	r3, [r7, #28]
        nb_non_written_words = (offset % BYTES_PER_PAGE) / NB_OF_BYTES_IN_A_WORD;
    7b18:	683b      	ldr	r3, [r7, #0]
    7b1a:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    7b1e:	ea4f 0393 	mov.w	r3, r3, lsr #2
    7b22:	623b      	str	r3, [r7, #32]
        if((offset % NB_OF_BYTES_IN_A_WORD) > 0u)
    7b24:	683b      	ldr	r3, [r7, #0]
    7b26:	f003 0303 	and.w	r3, r3, #3
    7b2a:	2b00      	cmp	r3, #0
    7b2c:	d003      	beq.n	7b36 <fill_wd_buffer+0x46>
        {
            ++nb_non_written_words;
    7b2e:	6a3b      	ldr	r3, [r7, #32]
    7b30:	f103 0301 	add.w	r3, r3, #1
    7b34:	623b      	str	r3, [r7, #32]
        }
        for(inc = 0u; (inc < WD_WORD_SIZE) && (inc < nb_non_written_words); ++inc)
    7b36:	f04f 0300 	mov.w	r3, #0
    7b3a:	617b      	str	r3, [r7, #20]
    7b3c:	e015      	b.n	7b6a <fill_wd_buffer+0x7a>
        {
            g_nvm32[block]->WD[inc] = p_nvm32[inc];
    7b3e:	687a      	ldr	r2, [r7, #4]
    7b40:	f649 6390 	movw	r3, #40592	; 0x9e90
    7b44:	f2c0 0300 	movt	r3, #0
    7b48:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
    7b4c:	697a      	ldr	r2, [r7, #20]
    7b4e:	6979      	ldr	r1, [r7, #20]
    7b50:	ea4f 0081 	mov.w	r0, r1, lsl #2
    7b54:	69f9      	ldr	r1, [r7, #28]
    7b56:	4401      	add	r1, r0
    7b58:	6809      	ldr	r1, [r1, #0]
    7b5a:	f102 0220 	add.w	r2, r2, #32
    7b5e:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
        nb_non_written_words = (offset % BYTES_PER_PAGE) / NB_OF_BYTES_IN_A_WORD;
        if((offset % NB_OF_BYTES_IN_A_WORD) > 0u)
        {
            ++nb_non_written_words;
        }
        for(inc = 0u; (inc < WD_WORD_SIZE) && (inc < nb_non_written_words); ++inc)
    7b62:	697b      	ldr	r3, [r7, #20]
    7b64:	f103 0301 	add.w	r3, r3, #1
    7b68:	617b      	str	r3, [r7, #20]
    7b6a:	697b      	ldr	r3, [r7, #20]
    7b6c:	2b1f      	cmp	r3, #31
    7b6e:	d803      	bhi.n	7b78 <fill_wd_buffer+0x88>
    7b70:	697a      	ldr	r2, [r7, #20]
    7b72:	6a3b      	ldr	r3, [r7, #32]
    7b74:	429a      	cmp	r2, r3
    7b76:	d3e2      	bcc.n	7b3e <fill_wd_buffer+0x4e>
        
        /*
         * Fill end of WD[] with current content of NVM page that must not be
         * overwritten.
         */
        first_non_written_word = ((offset + length) % BYTES_PER_PAGE) / NB_OF_BYTES_IN_A_WORD;
    7b78:	683a      	ldr	r2, [r7, #0]
    7b7a:	68bb      	ldr	r3, [r7, #8]
    7b7c:	4413      	add	r3, r2
    7b7e:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    7b82:	ea4f 0393 	mov.w	r3, r3, lsr #2
    7b86:	627b      	str	r3, [r7, #36]	; 0x24
        nb_non_written_words = (BYTES_PER_PAGE / NB_OF_BYTES_IN_A_WORD) - first_non_written_word;
    7b88:	6a7b      	ldr	r3, [r7, #36]	; 0x24
    7b8a:	f1c3 0320 	rsb	r3, r3, #32
    7b8e:	623b      	str	r3, [r7, #32]
        
        for(inc = 0u; inc < nb_non_written_words; ++inc)
    7b90:	f04f 0300 	mov.w	r3, #0
    7b94:	617b      	str	r3, [r7, #20]
    7b96:	e019      	b.n	7bcc <fill_wd_buffer+0xdc>
        {
            g_nvm32[block]->WD[first_non_written_word + inc] = p_nvm32[first_non_written_word + inc];
    7b98:	687a      	ldr	r2, [r7, #4]
    7b9a:	f649 6390 	movw	r3, #40592	; 0x9e90
    7b9e:	f2c0 0300 	movt	r3, #0
    7ba2:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
    7ba6:	6a79      	ldr	r1, [r7, #36]	; 0x24
    7ba8:	697a      	ldr	r2, [r7, #20]
    7baa:	440a      	add	r2, r1
    7bac:	6a78      	ldr	r0, [r7, #36]	; 0x24
    7bae:	6979      	ldr	r1, [r7, #20]
    7bb0:	4401      	add	r1, r0
    7bb2:	ea4f 0081 	mov.w	r0, r1, lsl #2
    7bb6:	69f9      	ldr	r1, [r7, #28]
    7bb8:	4401      	add	r1, r0
    7bba:	6809      	ldr	r1, [r1, #0]
    7bbc:	f102 0220 	add.w	r2, r2, #32
    7bc0:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
         * overwritten.
         */
        first_non_written_word = ((offset + length) % BYTES_PER_PAGE) / NB_OF_BYTES_IN_A_WORD;
        nb_non_written_words = (BYTES_PER_PAGE / NB_OF_BYTES_IN_A_WORD) - first_non_written_word;
        
        for(inc = 0u; inc < nb_non_written_words; ++inc)
    7bc4:	697b      	ldr	r3, [r7, #20]
    7bc6:	f103 0301 	add.w	r3, r3, #1
    7bca:	617b      	str	r3, [r7, #20]
    7bcc:	697a      	ldr	r2, [r7, #20]
    7bce:	6a3b      	ldr	r3, [r7, #32]
    7bd0:	429a      	cmp	r2, r3
    7bd2:	d3e1      	bcc.n	7b98 <fill_wd_buffer+0xa8>
    }
    
    /*
     * Fill WD[] with data requested to be written into NVM.
     */
    wd_offset = offset % BYTES_PER_PAGE;
    7bd4:	683b      	ldr	r3, [r7, #0]
    7bd6:	f003 037f 	and.w	r3, r3, #127	; 0x7f
    7bda:	61bb      	str	r3, [r7, #24]
    for(inc = 0u; inc < length; ++inc)
    7bdc:	f04f 0300 	mov.w	r3, #0
    7be0:	617b      	str	r3, [r7, #20]
    7be2:	e014      	b.n	7c0e <fill_wd_buffer+0x11e>
    {
        g_nvm[block]->WD[wd_offset + inc] = p_data[inc];
    7be4:	687a      	ldr	r2, [r7, #4]
    7be6:	f649 6388 	movw	r3, #40584	; 0x9e88
    7bea:	f2c0 0300 	movt	r3, #0
    7bee:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
    7bf2:	69b9      	ldr	r1, [r7, #24]
    7bf4:	697a      	ldr	r2, [r7, #20]
    7bf6:	4411      	add	r1, r2
    7bf8:	68f8      	ldr	r0, [r7, #12]
    7bfa:	697a      	ldr	r2, [r7, #20]
    7bfc:	4402      	add	r2, r0
    7bfe:	7812      	ldrb	r2, [r2, #0]
    7c00:	440b      	add	r3, r1
    7c02:	f883 2080 	strb.w	r2, [r3, #128]	; 0x80
    
    /*
     * Fill WD[] with data requested to be written into NVM.
     */
    wd_offset = offset % BYTES_PER_PAGE;
    for(inc = 0u; inc < length; ++inc)
    7c06:	697b      	ldr	r3, [r7, #20]
    7c08:	f103 0301 	add.w	r3, r3, #1
    7c0c:	617b      	str	r3, [r7, #20]
    7c0e:	697a      	ldr	r2, [r7, #20]
    7c10:	68bb      	ldr	r3, [r7, #8]
    7c12:	429a      	cmp	r2, r3
    7c14:	d3e6      	bcc.n	7be4 <fill_wd_buffer+0xf4>
    {
        g_nvm[block]->WD[wd_offset + inc] = p_data[inc];
    }
}
    7c16:	f107 072c 	add.w	r7, r7, #44	; 0x2c
    7c1a:	46bd      	mov	sp, r7
    7c1c:	bc80      	pop	{r7}
    7c1e:	4770      	bx	lr

00007c20 <NVM_read_page_write_count>:
uint32_t
NVM_read_page_write_count
(
    uint32_t addr
)
{
    7c20:	b580      	push	{r7, lr}
    7c22:	b086      	sub	sp, #24
    7c24:	af00      	add	r7, sp, #0
    7c26:	6078      	str	r0, [r7, #4]
    uint32_t write_count = 0u;
    7c28:	f04f 0300 	mov.w	r3, #0
    7c2c:	60bb      	str	r3, [r7, #8]
    uint32_t block;
    uint32_t offset;
    uint32_t status;

    if((addr >= (NVM_BASE_ADDRESS + NVM_TOP_OFFSET)) || \
    7c2e:	687a      	ldr	r2, [r7, #4]
    7c30:	f64f 73fe 	movw	r3, #65534	; 0xfffe
    7c34:	f2c6 0307 	movt	r3, #24583	; 0x6007
    7c38:	429a      	cmp	r2, r3
    7c3a:	d80b      	bhi.n	7c54 <NVM_read_page_write_count+0x34>
    7c3c:	687a      	ldr	r2, [r7, #4]
    7c3e:	f64f 73fe 	movw	r3, #65534	; 0xfffe
    7c42:	f2c0 0307 	movt	r3, #7
    7c46:	429a      	cmp	r2, r3
    7c48:	d908      	bls.n	7c5c <NVM_read_page_write_count+0x3c>
    7c4a:	687a      	ldr	r2, [r7, #4]
    7c4c:	f06f 4320 	mvn.w	r3, #2684354560	; 0xa0000000
    7c50:	429a      	cmp	r2, r3
    7c52:	d803      	bhi.n	7c5c <NVM_read_page_write_count+0x3c>
       ((addr >= NVM_TOP_OFFSET) && (addr < NVM_BASE_ADDRESS)))
    {
        write_count = 0u;
    7c54:	f04f 0300 	mov.w	r3, #0
    7c58:	60bb      	str	r3, [r7, #8]
    uint32_t write_count = 0u;
    uint32_t block;
    uint32_t offset;
    uint32_t status;

    if((addr >= (NVM_BASE_ADDRESS + NVM_TOP_OFFSET)) || \
    7c5a:	e079      	b.n	7d50 <NVM_read_page_write_count+0x130>
    {
        write_count = 0u;
    }
    else
    {
        write_count = 0u;
    7c5c:	f04f 0300 	mov.w	r3, #0
    7c60:	60bb      	str	r3, [r7, #8]
        offset = addr & NVM_OFFSET_SIGNIFICANT_BITS;
    7c62:	687b      	ldr	r3, [r7, #4]
    7c64:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
    7c68:	f423 0378 	bic.w	r3, r3, #16252928	; 0xf80000
    7c6c:	613b      	str	r3, [r7, #16]

        status = check_protection_reserved_nvm(offset, 0u);
    7c6e:	6938      	ldr	r0, [r7, #16]
    7c70:	f04f 0100 	mov.w	r1, #0
    7c74:	f000 f872 	bl	7d5c <check_protection_reserved_nvm>
    7c78:	4603      	mov	r3, r0
    7c7a:	617b      	str	r3, [r7, #20]
        
        if(NVM_SUCCESS == status)
    7c7c:	697b      	ldr	r3, [r7, #20]
    7c7e:	2b00      	cmp	r3, #0
    7c80:	d166      	bne.n	7d50 <NVM_read_page_write_count+0x130>
        {  
            /* Gain exclusive access to eNVM controller */
            status = get_ctrl_access(offset, 1u);
    7c82:	6938      	ldr	r0, [r7, #16]
    7c84:	f04f 0101 	mov.w	r1, #1
    7c88:	f7ff fda2 	bl	77d0 <get_ctrl_access>
    7c8c:	4603      	mov	r3, r0
    7c8e:	617b      	str	r3, [r7, #20]
        
            /* Read page write counter. */
            if(NVM_SUCCESS == status)
    7c90:	697b      	ldr	r3, [r7, #20]
    7c92:	2b00      	cmp	r3, #0
    7c94:	d152      	bne.n	7d3c <NVM_read_page_write_count+0x11c>
            {
                if(offset < NVM1_BOTTOM_OFFSET)
    7c96:	693a      	ldr	r2, [r7, #16]
    7c98:	f64f 73ff 	movw	r3, #65535	; 0xffff
    7c9c:	f2c0 0303 	movt	r3, #3
    7ca0:	429a      	cmp	r2, r3
    7ca2:	d803      	bhi.n	7cac <NVM_read_page_write_count+0x8c>
                {
                    block = NVM_BLOCK_0;
    7ca4:	f04f 0300 	mov.w	r3, #0
    7ca8:	60fb      	str	r3, [r7, #12]
    7caa:	e006      	b.n	7cba <NVM_read_page_write_count+0x9a>
                }
                else
                {
                    block = NVM_BLOCK_1;
    7cac:	f04f 0301 	mov.w	r3, #1
    7cb0:	60fb      	str	r3, [r7, #12]
                    offset = offset - NVM1_BOTTOM_OFFSET;
    7cb2:	693b      	ldr	r3, [r7, #16]
    7cb4:	f5a3 2380 	sub.w	r3, r3, #262144	; 0x40000
    7cb8:	613b      	str	r3, [r7, #16]
                }
        
                g_nvm[block]->NV_PAGE_STATUS |= 0x2u;
    7cba:	68fa      	ldr	r2, [r7, #12]
    7cbc:	f649 6388 	movw	r3, #40584	; 0x9e88
    7cc0:	f2c0 0300 	movt	r3, #0
    7cc4:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    7cc8:	68f9      	ldr	r1, [r7, #12]
    7cca:	f649 6388 	movw	r3, #40584	; 0x9e88
    7cce:	f2c0 0300 	movt	r3, #0
    7cd2:	f853 3021 	ldr.w	r3, [r3, r1, lsl #2]
    7cd6:	f8d3 3128 	ldr.w	r3, [r3, #296]	; 0x128
    7cda:	f043 0302 	orr.w	r3, r3, #2
    7cde:	f8c2 3128 	str.w	r3, [r2, #296]	; 0x128
        
                if(block == NVM_BLOCK_0)
    7ce2:	68fb      	ldr	r3, [r7, #12]
    7ce4:	2b00      	cmp	r3, #0
    7ce6:	d107      	bne.n	7cf8 <NVM_read_page_write_count+0xd8>
                {
                    write_count = *((uint32_t *)((NVM0_BASE_ADDRESS + offset) & PAGE_ADDR_MASK));
    7ce8:	693b      	ldr	r3, [r7, #16]
    7cea:	f103 43c0 	add.w	r3, r3, #1610612736	; 0x60000000
    7cee:	f023 037f 	bic.w	r3, r3, #127	; 0x7f
    7cf2:	681b      	ldr	r3, [r3, #0]
    7cf4:	60bb      	str	r3, [r7, #8]
    7cf6:	e008      	b.n	7d0a <NVM_read_page_write_count+0xea>
                }
                else
                {
                    write_count = *((uint32_t *)((NVM1_BASE_ADDRESS + offset) & PAGE_ADDR_MASK));
    7cf8:	693b      	ldr	r3, [r7, #16]
    7cfa:	f103 43c0 	add.w	r3, r3, #1610612736	; 0x60000000
    7cfe:	f503 2380 	add.w	r3, r3, #262144	; 0x40000
    7d02:	f023 037f 	bic.w	r3, r3, #127	; 0x7f
    7d06:	681b      	ldr	r3, [r3, #0]
    7d08:	60bb      	str	r3, [r7, #8]
                }
        
                /* Wait for NVM to become ready. */
                status = wait_nvm_ready(block);
    7d0a:	68f8      	ldr	r0, [r7, #12]
    7d0c:	f7ff fdea 	bl	78e4 <wait_nvm_ready>
    7d10:	4603      	mov	r3, r0
    7d12:	617b      	str	r3, [r7, #20]
        
                g_nvm[block]->NV_PAGE_STATUS &= ~(0x2u);
    7d14:	68fa      	ldr	r2, [r7, #12]
    7d16:	f649 6388 	movw	r3, #40584	; 0x9e88
    7d1a:	f2c0 0300 	movt	r3, #0
    7d1e:	f853 2022 	ldr.w	r2, [r3, r2, lsl #2]
    7d22:	68f9      	ldr	r1, [r7, #12]
    7d24:	f649 6388 	movw	r3, #40584	; 0x9e88
    7d28:	f2c0 0300 	movt	r3, #0
    7d2c:	f853 3021 	ldr.w	r3, [r3, r1, lsl #2]
    7d30:	f8d3 3128 	ldr.w	r3, [r3, #296]	; 0x128
    7d34:	f023 0302 	bic.w	r3, r3, #2
    7d38:	f8c2 3128 	str.w	r3, [r2, #296]	; 0x128
            }
        
            /* Release eNVM controllers so that other masters can gain access to it. */
            release_ctrl_access();
    7d3c:	f7ff fd88 	bl	7850 <release_ctrl_access>
        
            /* The write count is contained in bits [24:4] of the page's auxiliary data. */
            write_count = (write_count & AUX_DATA_WC_MASK) >> AUX_DATA_WC_SHIFT;
    7d40:	68bb      	ldr	r3, [r7, #8]
    7d42:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
    7d46:	f023 030f 	bic.w	r3, r3, #15
    7d4a:	ea4f 1313 	mov.w	r3, r3, lsr #4
    7d4e:	60bb      	str	r3, [r7, #8]
        }
    }
    return write_count;
    7d50:	68bb      	ldr	r3, [r7, #8]
}
    7d52:	4618      	mov	r0, r3
    7d54:	f107 0718 	add.w	r7, r7, #24
    7d58:	46bd      	mov	sp, r7
    7d5a:	bd80      	pop	{r7, pc}

00007d5c <check_protection_reserved_nvm>:
 *  0x7C000 - 0x7CFFF - 4KB(32 pages) user lower1(bottom) protected area of eNVM1 memory.
 *  0x7B000 - 0x7BFFF - 4KB(32 pages) user upper1(top) protected area of eNVM1 memory.          
 *
 */
static nvm_status_t check_protection_reserved_nvm(uint32_t offset, uint32_t length)
{
    7d5c:	b580      	push	{r7, lr}
    7d5e:	b08c      	sub	sp, #48	; 0x30
    7d60:	af00      	add	r7, sp, #0
    7d62:	6078      	str	r0, [r7, #4]
    7d64:	6039      	str	r1, [r7, #0]
    uint32_t device_version;
    uint32_t protection_data;
    uint32_t protection_flag = 0u;
    7d66:	f04f 0300 	mov.w	r3, #0
    7d6a:	617b      	str	r3, [r7, #20]
    uint32_t protection_user0;
    uint32_t protection_user1;
    uint32_t protection_user2;
    uint32_t protection_user3;
    uint32_t length_minus_one = 0u;
    7d6c:	f04f 0300 	mov.w	r3, #0
    7d70:	62bb      	str	r3, [r7, #40]	; 0x28
    nvm_status_t status = NVM_SUCCESS;
    7d72:	f04f 0300 	mov.w	r3, #0
    7d76:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
    
    if(0u != length)
    7d7a:	683b      	ldr	r3, [r7, #0]
    7d7c:	2b00      	cmp	r3, #0
    7d7e:	d003      	beq.n	7d88 <check_protection_reserved_nvm+0x2c>
    {
        length_minus_one = length - 1u;
    7d80:	683b      	ldr	r3, [r7, #0]
    7d82:	f103 33ff 	add.w	r3, r3, #4294967295
    7d86:	62bb      	str	r3, [r7, #40]	; 0x28
    }

    device_version = (SYSREG->DEVICE_VERSION & 0xFFFFu);
    7d88:	f248 0300 	movw	r3, #32768	; 0x8000
    7d8c:	f2c4 0303 	movt	r3, #16387	; 0x4003
    7d90:	f8d3 314c 	ldr.w	r3, [r3, #332]	; 0x14c
    7d94:	ea4f 4303 	mov.w	r3, r3, lsl #16
    7d98:	ea4f 4313 	mov.w	r3, r3, lsr #16
    7d9c:	60fb      	str	r3, [r7, #12]
    
    /* 005 device */
    if((0xF805u == device_version))
    7d9e:	68fa      	ldr	r2, [r7, #12]
    7da0:	f64f 0305 	movw	r3, #63493	; 0xf805
    7da4:	429a      	cmp	r2, r3
    7da6:	f040 80a2 	bne.w	7eee <check_protection_reserved_nvm+0x192>
    {
        protection_flag = PROTECTION_OFF;
    7daa:	f04f 0300 	mov.w	r3, #0
    7dae:	617b      	str	r3, [r7, #20]
        /* Read eNVM user protect register for lower and upper area protection data */
        protection_data = (SYSREG->ENVM_PROTECT_USER & PROTECT_USER_MASK);
    7db0:	f248 0300 	movw	r3, #32768	; 0x8000
    7db4:	f2c4 0303 	movt	r3, #16387	; 0x4003
    7db8:	f8d3 3144 	ldr.w	r3, [r3, #324]	; 0x144
    7dbc:	ea4f 4303 	mov.w	r3, r3, lsl #16
    7dc0:	ea4f 4313 	mov.w	r3, r3, lsr #16
    7dc4:	613b      	str	r3, [r7, #16]
        /* Check whether the eNVM0 lower or upper area is protected or not */
        if(PROTECT_USER_MASK != protection_data)
    7dc6:	693a      	ldr	r2, [r7, #16]
    7dc8:	f64f 73ff 	movw	r3, #65535	; 0xffff
    7dcc:	429a      	cmp	r2, r3
    7dce:	d04f      	beq.n	7e70 <check_protection_reserved_nvm+0x114>
        {
            protection_user0 = (protection_data & 0x000Fu) & READ_WRITE_MASK;
    7dd0:	693b      	ldr	r3, [r7, #16]
    7dd2:	f003 0309 	and.w	r3, r3, #9
    7dd6:	61bb      	str	r3, [r7, #24]
            protection_user1 = ((protection_data & 0x00F0u) >> 4u) & READ_WRITE_MASK;
    7dd8:	693b      	ldr	r3, [r7, #16]
    7dda:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
    7dde:	ea4f 1313 	mov.w	r3, r3, lsr #4
    7de2:	f003 0309 	and.w	r3, r3, #9
    7de6:	61fb      	str	r3, [r7, #28]
            /* Checking NVM0 lower protected area is Read or Write or 'No R/W' access */
            if((READ_ONLY == protection_user0) ||(WRITE_ONLY == protection_user0) || \
    7de8:	69bb      	ldr	r3, [r7, #24]
    7dea:	2b01      	cmp	r3, #1
    7dec:	d005      	beq.n	7dfa <check_protection_reserved_nvm+0x9e>
    7dee:	69bb      	ldr	r3, [r7, #24]
    7df0:	2b08      	cmp	r3, #8
    7df2:	d002      	beq.n	7dfa <check_protection_reserved_nvm+0x9e>
    7df4:	69bb      	ldr	r3, [r7, #24]
    7df6:	2b00      	cmp	r3, #0
    7df8:	d10d      	bne.n	7e16 <check_protection_reserved_nvm+0xba>
               (NO_READ_WRITE == protection_user0))
            {   
                /* Check offset is in the range of lower protect memory if it is
                 * then memory protected.
                 */
                if((offset > LOWER0_PROTECT_BOTTOM_OFFSET) && \
    7dfa:	687b      	ldr	r3, [r7, #4]
    7dfc:	2b00      	cmp	r3, #0
    7dfe:	d00a      	beq.n	7e16 <check_protection_reserved_nvm+0xba>
    7e00:	687a      	ldr	r2, [r7, #4]
    7e02:	f640 73ff 	movw	r3, #4095	; 0xfff
    7e06:	429a      	cmp	r2, r3
    7e08:	d805      	bhi.n	7e16 <check_protection_reserved_nvm+0xba>
                    (offset <= LOWER0_PROTECT_TOP_OFFSET))
                {
                    protection_flag = protection_check(protection_user0, length);
    7e0a:	69b8      	ldr	r0, [r7, #24]
    7e0c:	6839      	ldr	r1, [r7, #0]
    7e0e:	f000 faf5 	bl	83fc <protection_check>
    7e12:	4603      	mov	r3, r0
    7e14:	617b      	str	r3, [r7, #20]
                }
            }
            /* Checking NVM0 upper protected area is Read or Write or 'No R/W' access */
            if((READ_ONLY == protection_user1) ||(WRITE_ONLY == protection_user1) || \
    7e16:	69fb      	ldr	r3, [r7, #28]
    7e18:	2b01      	cmp	r3, #1
    7e1a:	d005      	beq.n	7e28 <check_protection_reserved_nvm+0xcc>
    7e1c:	69fb      	ldr	r3, [r7, #28]
    7e1e:	2b08      	cmp	r3, #8
    7e20:	d002      	beq.n	7e28 <check_protection_reserved_nvm+0xcc>
    7e22:	69fb      	ldr	r3, [r7, #28]
    7e24:	2b00      	cmp	r3, #0
    7e26:	d123      	bne.n	7e70 <check_protection_reserved_nvm+0x114>
               (NO_READ_WRITE == protection_user1))
            {
                /* Check offset or (offset + length) is in the range of upper 
                 *  protect memory if it is then memory protected.
                 */
                if(((offset >= OO5_UPPER0_PROTECT_BOTTOM_OFFSET) && \
    7e28:	687a      	ldr	r2, [r7, #4]
    7e2a:	f64e 73ff 	movw	r3, #61439	; 0xefff
    7e2e:	f2c0 0301 	movt	r3, #1
    7e32:	429a      	cmp	r2, r3
    7e34:	d906      	bls.n	7e44 <check_protection_reserved_nvm+0xe8>
    7e36:	687a      	ldr	r2, [r7, #4]
    7e38:	f64f 73ff 	movw	r3, #65535	; 0xffff
    7e3c:	f2c0 0301 	movt	r3, #1
    7e40:	429a      	cmp	r2, r3
    7e42:	d90f      	bls.n	7e64 <check_protection_reserved_nvm+0x108>
                    (offset <= OO5_UPPER0_PROTECT_TOP_OFFSET)) || \
                    (((offset + length_minus_one) >= OO5_UPPER0_PROTECT_BOTTOM_OFFSET) && \
    7e44:	687a      	ldr	r2, [r7, #4]
    7e46:	6abb      	ldr	r3, [r7, #40]	; 0x28
    7e48:	441a      	add	r2, r3
               (NO_READ_WRITE == protection_user1))
            {
                /* Check offset or (offset + length) is in the range of upper 
                 *  protect memory if it is then memory protected.
                 */
                if(((offset >= OO5_UPPER0_PROTECT_BOTTOM_OFFSET) && \
    7e4a:	f64e 73ff 	movw	r3, #61439	; 0xefff
    7e4e:	f2c0 0301 	movt	r3, #1
    7e52:	429a      	cmp	r2, r3
    7e54:	d90c      	bls.n	7e70 <check_protection_reserved_nvm+0x114>
    7e56:	687a      	ldr	r2, [r7, #4]
    7e58:	f64e 73ff 	movw	r3, #61439	; 0xefff
    7e5c:	f2c0 0301 	movt	r3, #1
    7e60:	429a      	cmp	r2, r3
    7e62:	d805      	bhi.n	7e70 <check_protection_reserved_nvm+0x114>
                    (offset <= OO5_UPPER0_PROTECT_TOP_OFFSET)) || \
                    (((offset + length_minus_one) >= OO5_UPPER0_PROTECT_BOTTOM_OFFSET) && \
                    (offset < OO5_UPPER0_PROTECT_BOTTOM_OFFSET)))
                {
                    protection_flag = protection_check(protection_user1, length);
    7e64:	69f8      	ldr	r0, [r7, #28]
    7e66:	6839      	ldr	r1, [r7, #0]
    7e68:	f000 fac8 	bl	83fc <protection_check>
    7e6c:	4603      	mov	r3, r0
    7e6e:	617b      	str	r3, [r7, #20]
                }
            }
        }
        /* Check memory is protected or not */
        if(PROTECTION_ON == protection_flag)
    7e70:	697b      	ldr	r3, [r7, #20]
    7e72:	2b01      	cmp	r3, #1
    7e74:	d104      	bne.n	7e80 <check_protection_reserved_nvm+0x124>
        {
            /* Status is protection error if lower or upper area of eNVM0 is protected */
            status = NVM_PROTECTION_ERROR;
    7e76:	f04f 0301 	mov.w	r3, #1
    7e7a:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
                else
                {
                    /* Status is success if offset or (offset + length) is 
                     * in RW access of eNVM memory(not protected)
                     */
                    status = NVM_SUCCESS;
    7e7e:	e2b6      	b.n	83ee <check_protection_reserved_nvm+0x692>
            status = NVM_PROTECTION_ERROR;
        }
        else
        {
            /* Check (offset + length) is out of eNVM memory */
            if((offset + length_minus_one) > OO5_UPPER0_PROTECT_TOP_OFFSET)
    7e80:	687a      	ldr	r2, [r7, #4]
    7e82:	6abb      	ldr	r3, [r7, #40]	; 0x28
    7e84:	441a      	add	r2, r3
    7e86:	f64f 73ff 	movw	r3, #65535	; 0xffff
    7e8a:	f2c0 0301 	movt	r3, #1
    7e8e:	429a      	cmp	r2, r3
    7e90:	d904      	bls.n	7e9c <check_protection_reserved_nvm+0x140>
            {
                status = NVM_INVALID_PARAMETER;
    7e92:	f04f 0306 	mov.w	r3, #6
    7e96:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
                else
                {
                    /* Status is success if offset or (offset + length) is 
                     * in RW access of eNVM memory(not protected)
                     */
                    status = NVM_SUCCESS;
    7e9a:	e2a8      	b.n	83ee <check_protection_reserved_nvm+0x692>
                status = NVM_INVALID_PARAMETER;
            }
            else
            {
                /* Check offset is in eNVM reserved memory - 16 pages reserved */
                if(((offset >= OO5_NVM_RSV_OFFSET) && (offset <= OO5_UPPER0_PROTECT_TOP_OFFSET)) || \
    7e9c:	687a      	ldr	r2, [r7, #4]
    7e9e:	f24f 73ff 	movw	r3, #63487	; 0xf7ff
    7ea2:	f2c0 0301 	movt	r3, #1
    7ea6:	429a      	cmp	r2, r3
    7ea8:	d906      	bls.n	7eb8 <check_protection_reserved_nvm+0x15c>
    7eaa:	687a      	ldr	r2, [r7, #4]
    7eac:	f64f 73ff 	movw	r3, #65535	; 0xffff
    7eb0:	f2c0 0301 	movt	r3, #1
    7eb4:	429a      	cmp	r2, r3
    7eb6:	d90f      	bls.n	7ed8 <check_protection_reserved_nvm+0x17c>
                    (((offset + length_minus_one) >= OO5_NVM_RSV_OFFSET) && \
    7eb8:	687a      	ldr	r2, [r7, #4]
    7eba:	6abb      	ldr	r3, [r7, #40]	; 0x28
    7ebc:	441a      	add	r2, r3
                status = NVM_INVALID_PARAMETER;
            }
            else
            {
                /* Check offset is in eNVM reserved memory - 16 pages reserved */
                if(((offset >= OO5_NVM_RSV_OFFSET) && (offset <= OO5_UPPER0_PROTECT_TOP_OFFSET)) || \
    7ebe:	f24f 73ff 	movw	r3, #63487	; 0xf7ff
    7ec2:	f2c0 0301 	movt	r3, #1
    7ec6:	429a      	cmp	r2, r3
    7ec8:	d90c      	bls.n	7ee4 <check_protection_reserved_nvm+0x188>
    7eca:	687a      	ldr	r2, [r7, #4]
    7ecc:	f24f 73ff 	movw	r3, #63487	; 0xf7ff
    7ed0:	f2c0 0301 	movt	r3, #1
    7ed4:	429a      	cmp	r2, r3
    7ed6:	d805      	bhi.n	7ee4 <check_protection_reserved_nvm+0x188>
                     (offset < OO5_NVM_RSV_OFFSET)))
                {
                    /* Status is protection error if offset or (offset + length) is 
                     * in reserved area of eNVM
                    */
                    status = NVM_PROTECTION_ERROR;
    7ed8:	f04f 0301 	mov.w	r3, #1
    7edc:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
                status = NVM_INVALID_PARAMETER;
            }
            else
            {
                /* Check offset is in eNVM reserved memory - 16 pages reserved */
                if(((offset >= OO5_NVM_RSV_OFFSET) && (offset <= OO5_UPPER0_PROTECT_TOP_OFFSET)) || \
    7ee0:	bf00      	nop
    7ee2:	e284      	b.n	83ee <check_protection_reserved_nvm+0x692>
                else
                {
                    /* Status is success if offset or (offset + length) is 
                     * in RW access of eNVM memory(not protected)
                     */
                    status = NVM_SUCCESS;
    7ee4:	f04f 0300 	mov.w	r3, #0
    7ee8:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
    7eec:	e27f      	b.n	83ee <check_protection_reserved_nvm+0x692>
                }
            }
        }
    }
    /* 010/025/050 device */
    else if((0xF802u == device_version) || (0xF803u == device_version) || (0xF804u == device_version))
    7eee:	68fa      	ldr	r2, [r7, #12]
    7ef0:	f64f 0302 	movw	r3, #63490	; 0xf802
    7ef4:	429a      	cmp	r2, r3
    7ef6:	d00a      	beq.n	7f0e <check_protection_reserved_nvm+0x1b2>
    7ef8:	68fa      	ldr	r2, [r7, #12]
    7efa:	f64f 0303 	movw	r3, #63491	; 0xf803
    7efe:	429a      	cmp	r2, r3
    7f00:	d005      	beq.n	7f0e <check_protection_reserved_nvm+0x1b2>
    7f02:	68fa      	ldr	r2, [r7, #12]
    7f04:	f64f 0304 	movw	r3, #63492	; 0xf804
    7f08:	429a      	cmp	r2, r3
    7f0a:	f040 80a2 	bne.w	8052 <check_protection_reserved_nvm+0x2f6>
    {    
        protection_flag = PROTECTION_OFF;
    7f0e:	f04f 0300 	mov.w	r3, #0
    7f12:	617b      	str	r3, [r7, #20]
        /* Read eNVM user protect register for lower and upper area protection data */
        protection_data = (SYSREG->ENVM_PROTECT_USER & PROTECT_USER_MASK);
    7f14:	f248 0300 	movw	r3, #32768	; 0x8000
    7f18:	f2c4 0303 	movt	r3, #16387	; 0x4003
    7f1c:	f8d3 3144 	ldr.w	r3, [r3, #324]	; 0x144
    7f20:	ea4f 4303 	mov.w	r3, r3, lsl #16
    7f24:	ea4f 4313 	mov.w	r3, r3, lsr #16
    7f28:	613b      	str	r3, [r7, #16]
        /* Check whether the eNVM0 lower or upper area is protected or not */        
        if(PROTECT_USER_MASK != protection_data)
    7f2a:	693a      	ldr	r2, [r7, #16]
    7f2c:	f64f 73ff 	movw	r3, #65535	; 0xffff
    7f30:	429a      	cmp	r2, r3
    7f32:	d04f      	beq.n	7fd4 <check_protection_reserved_nvm+0x278>
        {
            protection_user0 = (protection_data & 0x000Fu) & READ_WRITE_MASK;
    7f34:	693b      	ldr	r3, [r7, #16]
    7f36:	f003 0309 	and.w	r3, r3, #9
    7f3a:	61bb      	str	r3, [r7, #24]
            protection_user1 = ((protection_data & 0x00F0u) >> 4u) & READ_WRITE_MASK;
    7f3c:	693b      	ldr	r3, [r7, #16]
    7f3e:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
    7f42:	ea4f 1313 	mov.w	r3, r3, lsr #4
    7f46:	f003 0309 	and.w	r3, r3, #9
    7f4a:	61fb      	str	r3, [r7, #28]
            /* Check NVM0 lower protected area is Read or Write or 'No R/W' access */
            if((READ_ONLY == protection_user0) ||(WRITE_ONLY == protection_user0) || \
    7f4c:	69bb      	ldr	r3, [r7, #24]
    7f4e:	2b01      	cmp	r3, #1
    7f50:	d005      	beq.n	7f5e <check_protection_reserved_nvm+0x202>
    7f52:	69bb      	ldr	r3, [r7, #24]
    7f54:	2b08      	cmp	r3, #8
    7f56:	d002      	beq.n	7f5e <check_protection_reserved_nvm+0x202>
    7f58:	69bb      	ldr	r3, [r7, #24]
    7f5a:	2b00      	cmp	r3, #0
    7f5c:	d10d      	bne.n	7f7a <check_protection_reserved_nvm+0x21e>
               (NO_READ_WRITE == protection_user0))
            {
                /* Check offset is in the range of lower protect memory if it is
                 * then memory protected.
                 */            
                if((offset > LOWER0_PROTECT_BOTTOM_OFFSET) && \
    7f5e:	687b      	ldr	r3, [r7, #4]
    7f60:	2b00      	cmp	r3, #0
    7f62:	d00a      	beq.n	7f7a <check_protection_reserved_nvm+0x21e>
    7f64:	687a      	ldr	r2, [r7, #4]
    7f66:	f640 73ff 	movw	r3, #4095	; 0xfff
    7f6a:	429a      	cmp	r2, r3
    7f6c:	d805      	bhi.n	7f7a <check_protection_reserved_nvm+0x21e>
                    (offset <= LOWER0_PROTECT_TOP_OFFSET))
                {
                    protection_flag = protection_check(protection_user0, length);
    7f6e:	69b8      	ldr	r0, [r7, #24]
    7f70:	6839      	ldr	r1, [r7, #0]
    7f72:	f000 fa43 	bl	83fc <protection_check>
    7f76:	4603      	mov	r3, r0
    7f78:	617b      	str	r3, [r7, #20]
                }
            }
            /* Check NVM0 upper protected area is Read or Write or 'No R/W' access */
            if((READ_ONLY == protection_user1) ||(WRITE_ONLY == protection_user1) || \
    7f7a:	69fb      	ldr	r3, [r7, #28]
    7f7c:	2b01      	cmp	r3, #1
    7f7e:	d005      	beq.n	7f8c <check_protection_reserved_nvm+0x230>
    7f80:	69fb      	ldr	r3, [r7, #28]
    7f82:	2b08      	cmp	r3, #8
    7f84:	d002      	beq.n	7f8c <check_protection_reserved_nvm+0x230>
    7f86:	69fb      	ldr	r3, [r7, #28]
    7f88:	2b00      	cmp	r3, #0
    7f8a:	d123      	bne.n	7fd4 <check_protection_reserved_nvm+0x278>
               (NO_READ_WRITE == protection_user1))
            {
                /* Check offset or (offset + length) is in the range of upper 
                 * protect memory if it is then memory protected.
                 */
                if(((offset >= UPPER0_PROTECT_BOTTOM_OFFSET) && \
    7f8c:	687a      	ldr	r2, [r7, #4]
    7f8e:	f64e 73ff 	movw	r3, #61439	; 0xefff
    7f92:	f2c0 0303 	movt	r3, #3
    7f96:	429a      	cmp	r2, r3
    7f98:	d906      	bls.n	7fa8 <check_protection_reserved_nvm+0x24c>
    7f9a:	687a      	ldr	r2, [r7, #4]
    7f9c:	f64f 73ff 	movw	r3, #65535	; 0xffff
    7fa0:	f2c0 0303 	movt	r3, #3
    7fa4:	429a      	cmp	r2, r3
    7fa6:	d90f      	bls.n	7fc8 <check_protection_reserved_nvm+0x26c>
                    (offset <= UPPER0_PROTECT_TOP_OFFSET)) || \
                    (((offset + length_minus_one) >= UPPER0_PROTECT_BOTTOM_OFFSET) && \
    7fa8:	687a      	ldr	r2, [r7, #4]
    7faa:	6abb      	ldr	r3, [r7, #40]	; 0x28
    7fac:	441a      	add	r2, r3
               (NO_READ_WRITE == protection_user1))
            {
                /* Check offset or (offset + length) is in the range of upper 
                 * protect memory if it is then memory protected.
                 */
                if(((offset >= UPPER0_PROTECT_BOTTOM_OFFSET) && \
    7fae:	f64e 73ff 	movw	r3, #61439	; 0xefff
    7fb2:	f2c0 0303 	movt	r3, #3
    7fb6:	429a      	cmp	r2, r3
    7fb8:	d90c      	bls.n	7fd4 <check_protection_reserved_nvm+0x278>
    7fba:	687a      	ldr	r2, [r7, #4]
    7fbc:	f64e 73ff 	movw	r3, #61439	; 0xefff
    7fc0:	f2c0 0303 	movt	r3, #3
    7fc4:	429a      	cmp	r2, r3
    7fc6:	d805      	bhi.n	7fd4 <check_protection_reserved_nvm+0x278>
                    (offset <= UPPER0_PROTECT_TOP_OFFSET)) || \
                    (((offset + length_minus_one) >= UPPER0_PROTECT_BOTTOM_OFFSET) && \
                    (offset < UPPER0_PROTECT_BOTTOM_OFFSET)))
                {
                    protection_flag = protection_check(protection_user1, length);
    7fc8:	69f8      	ldr	r0, [r7, #28]
    7fca:	6839      	ldr	r1, [r7, #0]
    7fcc:	f000 fa16 	bl	83fc <protection_check>
    7fd0:	4603      	mov	r3, r0
    7fd2:	617b      	str	r3, [r7, #20]
                }
            }
        }
        /* Check lower or upper memory is protected or not */
        if(PROTECTION_ON == protection_flag)
    7fd4:	697b      	ldr	r3, [r7, #20]
    7fd6:	2b01      	cmp	r3, #1
    7fd8:	d104      	bne.n	7fe4 <check_protection_reserved_nvm+0x288>
        {
            /* Status is protection error if lower or upper area of eNVM0 is protected */        
            status = NVM_PROTECTION_ERROR;
    7fda:	f04f 0301 	mov.w	r3, #1
    7fde:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
                }
            }
        }
    }
    /* 010/025/050 device */
    else if((0xF802u == device_version) || (0xF803u == device_version) || (0xF804u == device_version))
    7fe2:	e204      	b.n	83ee <check_protection_reserved_nvm+0x692>
            status = NVM_PROTECTION_ERROR;
        }
        else
        {
             /* Check (offset + length) is out of eNVM memory */
            if((offset + length_minus_one) > UPPER0_PROTECT_TOP_OFFSET)
    7fe4:	687a      	ldr	r2, [r7, #4]
    7fe6:	6abb      	ldr	r3, [r7, #40]	; 0x28
    7fe8:	441a      	add	r2, r3
    7fea:	f64f 73ff 	movw	r3, #65535	; 0xffff
    7fee:	f2c0 0303 	movt	r3, #3
    7ff2:	429a      	cmp	r2, r3
    7ff4:	d904      	bls.n	8000 <check_protection_reserved_nvm+0x2a4>
            {
                status = NVM_INVALID_PARAMETER;
    7ff6:	f04f 0306 	mov.w	r3, #6
    7ffa:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
                }
            }
        }
    }
    /* 010/025/050 device */
    else if((0xF802u == device_version) || (0xF803u == device_version) || (0xF804u == device_version))
    7ffe:	e1f6      	b.n	83ee <check_protection_reserved_nvm+0x692>
                status = NVM_INVALID_PARAMETER;
            }
            else
            {
                /* Check offset is in eNVM reserved memory - 16 pages reserved */
                if(((offset >= NVM0_RSV_OFFSET) && (offset <= UPPER0_PROTECT_TOP_OFFSET)) || \
    8000:	687a      	ldr	r2, [r7, #4]
    8002:	f24f 73ff 	movw	r3, #63487	; 0xf7ff
    8006:	f2c0 0303 	movt	r3, #3
    800a:	429a      	cmp	r2, r3
    800c:	d906      	bls.n	801c <check_protection_reserved_nvm+0x2c0>
    800e:	687a      	ldr	r2, [r7, #4]
    8010:	f64f 73ff 	movw	r3, #65535	; 0xffff
    8014:	f2c0 0303 	movt	r3, #3
    8018:	429a      	cmp	r2, r3
    801a:	d90f      	bls.n	803c <check_protection_reserved_nvm+0x2e0>
                    (((offset + length_minus_one) >= NVM0_RSV_OFFSET) && (offset < NVM0_RSV_OFFSET)))
    801c:	687a      	ldr	r2, [r7, #4]
    801e:	6abb      	ldr	r3, [r7, #40]	; 0x28
    8020:	441a      	add	r2, r3
                status = NVM_INVALID_PARAMETER;
            }
            else
            {
                /* Check offset is in eNVM reserved memory - 16 pages reserved */
                if(((offset >= NVM0_RSV_OFFSET) && (offset <= UPPER0_PROTECT_TOP_OFFSET)) || \
    8022:	f24f 73ff 	movw	r3, #63487	; 0xf7ff
    8026:	f2c0 0303 	movt	r3, #3
    802a:	429a      	cmp	r2, r3
    802c:	d90c      	bls.n	8048 <check_protection_reserved_nvm+0x2ec>
    802e:	687a      	ldr	r2, [r7, #4]
    8030:	f24f 73ff 	movw	r3, #63487	; 0xf7ff
    8034:	f2c0 0303 	movt	r3, #3
    8038:	429a      	cmp	r2, r3
    803a:	d805      	bhi.n	8048 <check_protection_reserved_nvm+0x2ec>
                    (((offset + length_minus_one) >= NVM0_RSV_OFFSET) && (offset < NVM0_RSV_OFFSET)))
                {
                    /* Status is protection error if offset or (offset + length) is 
                     * in reserved area of eNVM
                    */
                    status = NVM_PROTECTION_ERROR;
    803c:	f04f 0301 	mov.w	r3, #1
    8040:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
                status = NVM_INVALID_PARAMETER;
            }
            else
            {
                /* Check offset is in eNVM reserved memory - 16 pages reserved */
                if(((offset >= NVM0_RSV_OFFSET) && (offset <= UPPER0_PROTECT_TOP_OFFSET)) || \
    8044:	bf00      	nop
                }
            }
        }
    }
    /* 010/025/050 device */
    else if((0xF802u == device_version) || (0xF803u == device_version) || (0xF804u == device_version))
    8046:	e1d2      	b.n	83ee <check_protection_reserved_nvm+0x692>
                else
                {
                    /* Status is success if offset or (offset + length) is 
                     * in RW access of eNVM memory(not protected)
                     */
                    status = NVM_SUCCESS;
    8048:	f04f 0300 	mov.w	r3, #0
    804c:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
                }
            }
        }
    }
    /* 010/025/050 device */
    else if((0xF802u == device_version) || (0xF803u == device_version) || (0xF804u == device_version))
    8050:	e1cd      	b.n	83ee <check_protection_reserved_nvm+0x692>
                }
            }
        }
    }
    /* 060 device */
    else if(0xF808u == device_version)
    8052:	68fa      	ldr	r2, [r7, #12]
    8054:	f64f 0308 	movw	r3, #63496	; 0xf808
    8058:	429a      	cmp	r2, r3
    805a:	f040 80b2 	bne.w	81c2 <check_protection_reserved_nvm+0x466>
    {
        protection_flag = PROTECTION_OFF;
    805e:	f04f 0300 	mov.w	r3, #0
    8062:	617b      	str	r3, [r7, #20]
        /* Read eNVM user protect register for lower and upper area protection data */
        protection_data = (SYSREG->ENVM_PROTECT_USER & PROTECT_USER_MASK);
    8064:	f248 0300 	movw	r3, #32768	; 0x8000
    8068:	f2c4 0303 	movt	r3, #16387	; 0x4003
    806c:	f8d3 3144 	ldr.w	r3, [r3, #324]	; 0x144
    8070:	ea4f 4303 	mov.w	r3, r3, lsl #16
    8074:	ea4f 4313 	mov.w	r3, r3, lsr #16
    8078:	613b      	str	r3, [r7, #16]
        /* Check whether the eNVM0 lower0/1 or upper0/1 area is protected or not */
        if(PROTECT_USER_MASK != protection_data)
    807a:	693a      	ldr	r2, [r7, #16]
    807c:	f64f 73ff 	movw	r3, #65535	; 0xffff
    8080:	429a      	cmp	r2, r3
    8082:	d05f      	beq.n	8144 <check_protection_reserved_nvm+0x3e8>
        {
            protection_user0 = (protection_data & 0x000Fu) & READ_WRITE_MASK;
    8084:	693b      	ldr	r3, [r7, #16]
    8086:	f003 0309 	and.w	r3, r3, #9
    808a:	61bb      	str	r3, [r7, #24]
            protection_user1 = ((protection_data & 0x00F0u) >> 4u) & READ_WRITE_MASK;
    808c:	693b      	ldr	r3, [r7, #16]
    808e:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
    8092:	ea4f 1313 	mov.w	r3, r3, lsr #4
    8096:	f003 0309 	and.w	r3, r3, #9
    809a:	61fb      	str	r3, [r7, #28]
            protection_user2 = ((protection_data & 0x0F00u) >> 8u) & READ_WRITE_MASK;
    809c:	693b      	ldr	r3, [r7, #16]
    809e:	f403 6370 	and.w	r3, r3, #3840	; 0xf00
    80a2:	ea4f 2313 	mov.w	r3, r3, lsr #8
    80a6:	f003 0309 	and.w	r3, r3, #9
    80aa:	623b      	str	r3, [r7, #32]
            protection_user3 = ((protection_data & 0xF000u) >> 12u) & READ_WRITE_MASK;
    80ac:	693b      	ldr	r3, [r7, #16]
    80ae:	f403 4370 	and.w	r3, r3, #61440	; 0xf000
    80b2:	ea4f 3313 	mov.w	r3, r3, lsr #12
    80b6:	f003 0309 	and.w	r3, r3, #9
    80ba:	627b      	str	r3, [r7, #36]	; 0x24
            
            /* Check NVM0 lower0 protected area is Read or Write or 'No R/W' access */
            if((READ_ONLY == protection_user0) ||(WRITE_ONLY == protection_user0) || \
    80bc:	69bb      	ldr	r3, [r7, #24]
    80be:	2b01      	cmp	r3, #1
    80c0:	d005      	beq.n	80ce <check_protection_reserved_nvm+0x372>
    80c2:	69bb      	ldr	r3, [r7, #24]
    80c4:	2b08      	cmp	r3, #8
    80c6:	d002      	beq.n	80ce <check_protection_reserved_nvm+0x372>
    80c8:	69bb      	ldr	r3, [r7, #24]
    80ca:	2b00      	cmp	r3, #0
    80cc:	d10d      	bne.n	80ea <check_protection_reserved_nvm+0x38e>
               (NO_READ_WRITE == protection_user0))
            {
                /* Check offset is in the range of lower0 protect memory if it is
                 * then memory protected.
                 */
                if((offset > LOWER0_PROTECT_BOTTOM_OFFSET) && \
    80ce:	687b      	ldr	r3, [r7, #4]
    80d0:	2b00      	cmp	r3, #0
    80d2:	d00a      	beq.n	80ea <check_protection_reserved_nvm+0x38e>
    80d4:	687a      	ldr	r2, [r7, #4]
    80d6:	f640 73ff 	movw	r3, #4095	; 0xfff
    80da:	429a      	cmp	r2, r3
    80dc:	d805      	bhi.n	80ea <check_protection_reserved_nvm+0x38e>
                    (offset <= LOWER0_PROTECT_TOP_OFFSET))
                {
                    protection_flag = protection_check(protection_user0, length);
    80de:	69b8      	ldr	r0, [r7, #24]
    80e0:	6839      	ldr	r1, [r7, #0]
    80e2:	f000 f98b 	bl	83fc <protection_check>
    80e6:	4603      	mov	r3, r0
    80e8:	617b      	str	r3, [r7, #20]
                }
            }
            /* Check NVM0 upper1 protected area is Read or Write or 'No R/W' access */
            if((READ_ONLY == protection_user3) ||(WRITE_ONLY == protection_user3) || \
    80ea:	6a7b      	ldr	r3, [r7, #36]	; 0x24
    80ec:	2b01      	cmp	r3, #1
    80ee:	d005      	beq.n	80fc <check_protection_reserved_nvm+0x3a0>
    80f0:	6a7b      	ldr	r3, [r7, #36]	; 0x24
    80f2:	2b08      	cmp	r3, #8
    80f4:	d002      	beq.n	80fc <check_protection_reserved_nvm+0x3a0>
    80f6:	6a7b      	ldr	r3, [r7, #36]	; 0x24
    80f8:	2b00      	cmp	r3, #0
    80fa:	d123      	bne.n	8144 <check_protection_reserved_nvm+0x3e8>
               (NO_READ_WRITE == protection_user3))
            {
                /* Check offset or (offset + length) is in the range of upper1 
                 *  protect memory if it is then memory protected.
                 */
                if(((offset >= NVM0_UPPER1_PROTECT_BOTTOM_OFFSET) && \
    80fc:	687a      	ldr	r2, [r7, #4]
    80fe:	f64c 73ff 	movw	r3, #53247	; 0xcfff
    8102:	f2c0 0303 	movt	r3, #3
    8106:	429a      	cmp	r2, r3
    8108:	d906      	bls.n	8118 <check_protection_reserved_nvm+0x3bc>
    810a:	687a      	ldr	r2, [r7, #4]
    810c:	f64d 73ff 	movw	r3, #57343	; 0xdfff
    8110:	f2c0 0303 	movt	r3, #3
    8114:	429a      	cmp	r2, r3
    8116:	d90f      	bls.n	8138 <check_protection_reserved_nvm+0x3dc>
                    (offset <= NVM0_UPPER1_PROTECT_TOP_OFFSET)) || \
                    (((offset + length_minus_one) >= NVM0_UPPER1_PROTECT_BOTTOM_OFFSET) && \
    8118:	687a      	ldr	r2, [r7, #4]
    811a:	6abb      	ldr	r3, [r7, #40]	; 0x28
    811c:	441a      	add	r2, r3
               (NO_READ_WRITE == protection_user3))
            {
                /* Check offset or (offset + length) is in the range of upper1 
                 *  protect memory if it is then memory protected.
                 */
                if(((offset >= NVM0_UPPER1_PROTECT_BOTTOM_OFFSET) && \
    811e:	f64c 73ff 	movw	r3, #53247	; 0xcfff
    8122:	f2c0 0303 	movt	r3, #3
    8126:	429a      	cmp	r2, r3
    8128:	d90c      	bls.n	8144 <check_protection_reserved_nvm+0x3e8>
    812a:	687a      	ldr	r2, [r7, #4]
    812c:	f64c 73ff 	movw	r3, #53247	; 0xcfff
    8130:	f2c0 0303 	movt	r3, #3
    8134:	429a      	cmp	r2, r3
    8136:	d805      	bhi.n	8144 <check_protection_reserved_nvm+0x3e8>
                    (offset <= NVM0_UPPER1_PROTECT_TOP_OFFSET)) || \
                    (((offset + length_minus_one) >= NVM0_UPPER1_PROTECT_BOTTOM_OFFSET) && \
                    (offset < NVM0_UPPER1_PROTECT_BOTTOM_OFFSET)))
                {
                    protection_flag = protection_check(protection_user3, length);
    8138:	6a78      	ldr	r0, [r7, #36]	; 0x24
    813a:	6839      	ldr	r1, [r7, #0]
    813c:	f000 f95e 	bl	83fc <protection_check>
    8140:	4603      	mov	r3, r0
    8142:	617b      	str	r3, [r7, #20]
        }
        /* Check lower0 or upper1 memory is protected or not.
         * No protection check for  0x3F000 - 0x3FFFF and 0x3E000 - 0x3EFFF lower1/upper0 
         * protected area of eNVM0 memory because it's fall under eNVM reserved area    
         */
        if(PROTECTION_ON == protection_flag)
    8144:	697b      	ldr	r3, [r7, #20]
    8146:	2b01      	cmp	r3, #1
    8148:	d104      	bne.n	8154 <check_protection_reserved_nvm+0x3f8>
        {
            /* Status is protection error if lower0 or upper1 area of eNVM0 is protected */
            status = NVM_PROTECTION_ERROR;
    814a:	f04f 0301 	mov.w	r3, #1
    814e:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
                     */
                    status = NVM_PROTECTION_ERROR;
                }
                else
                {
                    status = NVM_SUCCESS;
    8152:	e14c      	b.n	83ee <check_protection_reserved_nvm+0x692>
            status = NVM_PROTECTION_ERROR;
        }
        else
        {
            /* Check (offset + length) is out of eNVM memory*/
            if((offset + length_minus_one) > UPPER0_PROTECT_TOP_OFFSET)
    8154:	687a      	ldr	r2, [r7, #4]
    8156:	6abb      	ldr	r3, [r7, #40]	; 0x28
    8158:	441a      	add	r2, r3
    815a:	f64f 73ff 	movw	r3, #65535	; 0xffff
    815e:	f2c0 0303 	movt	r3, #3
    8162:	429a      	cmp	r2, r3
    8164:	d904      	bls.n	8170 <check_protection_reserved_nvm+0x414>
            {
                status = NVM_INVALID_PARAMETER;
    8166:	f04f 0306 	mov.w	r3, #6
    816a:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
                     */
                    status = NVM_PROTECTION_ERROR;
                }
                else
                {
                    status = NVM_SUCCESS;
    816e:	e13e      	b.n	83ee <check_protection_reserved_nvm+0x692>
                status = NVM_INVALID_PARAMETER;
            }
            else
            {
                /* Check offset is in eNVM reserved memory - 64 pages reserved */
                if(((offset >= O60_NVM_RSV_OFFSET) && (offset <= UPPER0_PROTECT_TOP_OFFSET)) || \
    8170:	687a      	ldr	r2, [r7, #4]
    8172:	f64d 73ff 	movw	r3, #57343	; 0xdfff
    8176:	f2c0 0303 	movt	r3, #3
    817a:	429a      	cmp	r2, r3
    817c:	d906      	bls.n	818c <check_protection_reserved_nvm+0x430>
    817e:	687a      	ldr	r2, [r7, #4]
    8180:	f64f 73ff 	movw	r3, #65535	; 0xffff
    8184:	f2c0 0303 	movt	r3, #3
    8188:	429a      	cmp	r2, r3
    818a:	d90f      	bls.n	81ac <check_protection_reserved_nvm+0x450>
                   (((offset + length_minus_one) >= O60_NVM_RSV_OFFSET) && \
    818c:	687a      	ldr	r2, [r7, #4]
    818e:	6abb      	ldr	r3, [r7, #40]	; 0x28
    8190:	441a      	add	r2, r3
                status = NVM_INVALID_PARAMETER;
            }
            else
            {
                /* Check offset is in eNVM reserved memory - 64 pages reserved */
                if(((offset >= O60_NVM_RSV_OFFSET) && (offset <= UPPER0_PROTECT_TOP_OFFSET)) || \
    8192:	f64d 73ff 	movw	r3, #57343	; 0xdfff
    8196:	f2c0 0303 	movt	r3, #3
    819a:	429a      	cmp	r2, r3
    819c:	d90c      	bls.n	81b8 <check_protection_reserved_nvm+0x45c>
    819e:	687a      	ldr	r2, [r7, #4]
    81a0:	f64d 73ff 	movw	r3, #57343	; 0xdfff
    81a4:	f2c0 0303 	movt	r3, #3
    81a8:	429a      	cmp	r2, r3
    81aa:	d805      	bhi.n	81b8 <check_protection_reserved_nvm+0x45c>
                   (offset < O60_NVM_RSV_OFFSET)))
                {
                    /* Status is protection error if offset or (offset + length) is 
                     * in reserved area of eNVM
                     */
                    status = NVM_PROTECTION_ERROR;
    81ac:	f04f 0301 	mov.w	r3, #1
    81b0:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
                status = NVM_INVALID_PARAMETER;
            }
            else
            {
                /* Check offset is in eNVM reserved memory - 64 pages reserved */
                if(((offset >= O60_NVM_RSV_OFFSET) && (offset <= UPPER0_PROTECT_TOP_OFFSET)) || \
    81b4:	bf00      	nop
    81b6:	e11a      	b.n	83ee <check_protection_reserved_nvm+0x692>
                     */
                    status = NVM_PROTECTION_ERROR;
                }
                else
                {
                    status = NVM_SUCCESS;
    81b8:	f04f 0300 	mov.w	r3, #0
    81bc:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
    81c0:	e115      	b.n	83ee <check_protection_reserved_nvm+0x692>
                }
            }
        }    
    }
    /* 090/150 device */
    else if((0xF807u == device_version) || (0xF806u == device_version))
    81c2:	68fa      	ldr	r2, [r7, #12]
    81c4:	f64f 0307 	movw	r3, #63495	; 0xf807
    81c8:	429a      	cmp	r2, r3
    81ca:	d005      	beq.n	81d8 <check_protection_reserved_nvm+0x47c>
    81cc:	68fa      	ldr	r2, [r7, #12]
    81ce:	f64f 0306 	movw	r3, #63494	; 0xf806
    81d2:	429a      	cmp	r2, r3
    81d4:	f040 810b 	bne.w	83ee <check_protection_reserved_nvm+0x692>
    {
        protection_flag = PROTECTION_OFF;
    81d8:	f04f 0300 	mov.w	r3, #0
    81dc:	617b      	str	r3, [r7, #20]
        /* Read eNVM user protect register for lower and upper area protection data */
        protection_data = (SYSREG->ENVM_PROTECT_USER & PROTECT_USER_MASK);
    81de:	f248 0300 	movw	r3, #32768	; 0x8000
    81e2:	f2c4 0303 	movt	r3, #16387	; 0x4003
    81e6:	f8d3 3144 	ldr.w	r3, [r3, #324]	; 0x144
    81ea:	ea4f 4303 	mov.w	r3, r3, lsl #16
    81ee:	ea4f 4313 	mov.w	r3, r3, lsr #16
    81f2:	613b      	str	r3, [r7, #16]
        /* Check whether the eNVM0 and eNVM1 lower or upper area is protected or not */        
        if(PROTECT_USER_MASK != protection_data)
    81f4:	693a      	ldr	r2, [r7, #16]
    81f6:	f64f 73ff 	movw	r3, #65535	; 0xffff
    81fa:	429a      	cmp	r2, r3
    81fc:	f000 80ba 	beq.w	8374 <check_protection_reserved_nvm+0x618>
        {
            protection_user0 = (protection_data & 0x000Fu) & READ_WRITE_MASK;
    8200:	693b      	ldr	r3, [r7, #16]
    8202:	f003 0309 	and.w	r3, r3, #9
    8206:	61bb      	str	r3, [r7, #24]
            protection_user1 = ((protection_data & 0x00F0u) >> 4u) & READ_WRITE_MASK;
    8208:	693b      	ldr	r3, [r7, #16]
    820a:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
    820e:	ea4f 1313 	mov.w	r3, r3, lsr #4
    8212:	f003 0309 	and.w	r3, r3, #9
    8216:	61fb      	str	r3, [r7, #28]
            protection_user2 = ((protection_data & 0x0F00u) >> 8u) & READ_WRITE_MASK;
    8218:	693b      	ldr	r3, [r7, #16]
    821a:	f403 6370 	and.w	r3, r3, #3840	; 0xf00
    821e:	ea4f 2313 	mov.w	r3, r3, lsr #8
    8222:	f003 0309 	and.w	r3, r3, #9
    8226:	623b      	str	r3, [r7, #32]
            protection_user3 = ((protection_data & 0xF000u) >> 12u) & READ_WRITE_MASK;
    8228:	693b      	ldr	r3, [r7, #16]
    822a:	f403 4370 	and.w	r3, r3, #61440	; 0xf000
    822e:	ea4f 3313 	mov.w	r3, r3, lsr #12
    8232:	f003 0309 	and.w	r3, r3, #9
    8236:	627b      	str	r3, [r7, #36]	; 0x24
            
            /* Check eNVM0 lower0 protected area is Read or Write or 'No R/W' access */
            if((READ_ONLY == protection_user0) ||(WRITE_ONLY == protection_user0) || \
    8238:	69bb      	ldr	r3, [r7, #24]
    823a:	2b01      	cmp	r3, #1
    823c:	d005      	beq.n	824a <check_protection_reserved_nvm+0x4ee>
    823e:	69bb      	ldr	r3, [r7, #24]
    8240:	2b08      	cmp	r3, #8
    8242:	d002      	beq.n	824a <check_protection_reserved_nvm+0x4ee>
    8244:	69bb      	ldr	r3, [r7, #24]
    8246:	2b00      	cmp	r3, #0
    8248:	d10d      	bne.n	8266 <check_protection_reserved_nvm+0x50a>
               (NO_READ_WRITE == protection_user0))
            {
                /* Check offset is in the range of lower0 protect memory if it is
                 * then memory protected.
                 */
                if((offset > LOWER0_PROTECT_BOTTOM_OFFSET) && \
    824a:	687b      	ldr	r3, [r7, #4]
    824c:	2b00      	cmp	r3, #0
    824e:	d00a      	beq.n	8266 <check_protection_reserved_nvm+0x50a>
    8250:	687a      	ldr	r2, [r7, #4]
    8252:	f640 73ff 	movw	r3, #4095	; 0xfff
    8256:	429a      	cmp	r2, r3
    8258:	d805      	bhi.n	8266 <check_protection_reserved_nvm+0x50a>
                    (offset <= LOWER0_PROTECT_TOP_OFFSET))
                {
                    protection_flag = protection_check(protection_user0, length);
    825a:	69b8      	ldr	r0, [r7, #24]
    825c:	6839      	ldr	r1, [r7, #0]
    825e:	f000 f8cd 	bl	83fc <protection_check>
    8262:	4603      	mov	r3, r0
    8264:	617b      	str	r3, [r7, #20]
                }
            }
            /* Check eNVM0 upper0 protected area(in eNVM1) is Read or Write or 'No R/W' access */
            if((READ_ONLY == protection_user1) ||(WRITE_ONLY == protection_user1) || \
    8266:	69fb      	ldr	r3, [r7, #28]
    8268:	2b01      	cmp	r3, #1
    826a:	d005      	beq.n	8278 <check_protection_reserved_nvm+0x51c>
    826c:	69fb      	ldr	r3, [r7, #28]
    826e:	2b08      	cmp	r3, #8
    8270:	d002      	beq.n	8278 <check_protection_reserved_nvm+0x51c>
    8272:	69fb      	ldr	r3, [r7, #28]
    8274:	2b00      	cmp	r3, #0
    8276:	d123      	bne.n	82c0 <check_protection_reserved_nvm+0x564>
               (NO_READ_WRITE == protection_user1))
            {
                /* Check offset or (offset + length) is in the range of upper0
                 *  protect memory if it is then memory protected.
                 */
                if(((offset >= NVM0_UPPER0_PROTECT_BOTTOM_OFFSET) && \
    8278:	687a      	ldr	r2, [r7, #4]
    827a:	f64c 73ff 	movw	r3, #53247	; 0xcfff
    827e:	f2c0 0307 	movt	r3, #7
    8282:	429a      	cmp	r2, r3
    8284:	d906      	bls.n	8294 <check_protection_reserved_nvm+0x538>
    8286:	687a      	ldr	r2, [r7, #4]
    8288:	f64d 73ff 	movw	r3, #57343	; 0xdfff
    828c:	f2c0 0307 	movt	r3, #7
    8290:	429a      	cmp	r2, r3
    8292:	d90f      	bls.n	82b4 <check_protection_reserved_nvm+0x558>
                    (offset <= NVM0_UPPER0_PROTECT_TOP_OFFSET)) || \
                    (((offset + length_minus_one) >= NVM0_UPPER0_PROTECT_BOTTOM_OFFSET) && \
    8294:	687a      	ldr	r2, [r7, #4]
    8296:	6abb      	ldr	r3, [r7, #40]	; 0x28
    8298:	441a      	add	r2, r3
               (NO_READ_WRITE == protection_user1))
            {
                /* Check offset or (offset + length) is in the range of upper0
                 *  protect memory if it is then memory protected.
                 */
                if(((offset >= NVM0_UPPER0_PROTECT_BOTTOM_OFFSET) && \
    829a:	f64c 73ff 	movw	r3, #53247	; 0xcfff
    829e:	f2c0 0307 	movt	r3, #7
    82a2:	429a      	cmp	r2, r3
    82a4:	d90c      	bls.n	82c0 <check_protection_reserved_nvm+0x564>
    82a6:	687a      	ldr	r2, [r7, #4]
    82a8:	f64c 73ff 	movw	r3, #53247	; 0xcfff
    82ac:	f2c0 0307 	movt	r3, #7
    82b0:	429a      	cmp	r2, r3
    82b2:	d805      	bhi.n	82c0 <check_protection_reserved_nvm+0x564>
                    (offset <= NVM0_UPPER0_PROTECT_TOP_OFFSET)) || \
                    (((offset + length_minus_one) >= NVM0_UPPER0_PROTECT_BOTTOM_OFFSET) && \
                    (offset < NVM0_UPPER0_PROTECT_BOTTOM_OFFSET)))
                {
                    protection_flag = protection_check(protection_user1, length);
    82b4:	69f8      	ldr	r0, [r7, #28]
    82b6:	6839      	ldr	r1, [r7, #0]
    82b8:	f000 f8a0 	bl	83fc <protection_check>
    82bc:	4603      	mov	r3, r0
    82be:	617b      	str	r3, [r7, #20]
                }
            }
            /* Check NVM1 lower1 protected area is Read or Write or 'No R/W' access */
            if((READ_ONLY == protection_user2) ||(WRITE_ONLY == protection_user2) || \
    82c0:	6a3b      	ldr	r3, [r7, #32]
    82c2:	2b01      	cmp	r3, #1
    82c4:	d005      	beq.n	82d2 <check_protection_reserved_nvm+0x576>
    82c6:	6a3b      	ldr	r3, [r7, #32]
    82c8:	2b08      	cmp	r3, #8
    82ca:	d002      	beq.n	82d2 <check_protection_reserved_nvm+0x576>
    82cc:	6a3b      	ldr	r3, [r7, #32]
    82ce:	2b00      	cmp	r3, #0
    82d0:	d123      	bne.n	831a <check_protection_reserved_nvm+0x5be>
               (NO_READ_WRITE == protection_user2))
            {
                /* Check offset or (offset + length)is in the range of lower1 
                 * protect memory if it is then memory protected.
                 */
                if(((offset >= LOWER1_PROTECT_BOTTOM_OFFSET) && \
    82d2:	687a      	ldr	r2, [r7, #4]
    82d4:	f64b 73ff 	movw	r3, #49151	; 0xbfff
    82d8:	f2c0 0307 	movt	r3, #7
    82dc:	429a      	cmp	r2, r3
    82de:	d906      	bls.n	82ee <check_protection_reserved_nvm+0x592>
    82e0:	687a      	ldr	r2, [r7, #4]
    82e2:	f64c 73ff 	movw	r3, #53247	; 0xcfff
    82e6:	f2c0 0307 	movt	r3, #7
    82ea:	429a      	cmp	r2, r3
    82ec:	d90f      	bls.n	830e <check_protection_reserved_nvm+0x5b2>
                    (offset <= LOWER1_PROTECT_TOP_OFFSET)) || \
                    (((offset + length_minus_one) >= LOWER1_PROTECT_BOTTOM_OFFSET) && \
    82ee:	687a      	ldr	r2, [r7, #4]
    82f0:	6abb      	ldr	r3, [r7, #40]	; 0x28
    82f2:	441a      	add	r2, r3
               (NO_READ_WRITE == protection_user2))
            {
                /* Check offset or (offset + length)is in the range of lower1 
                 * protect memory if it is then memory protected.
                 */
                if(((offset >= LOWER1_PROTECT_BOTTOM_OFFSET) && \
    82f4:	f64b 73ff 	movw	r3, #49151	; 0xbfff
    82f8:	f2c0 0307 	movt	r3, #7
    82fc:	429a      	cmp	r2, r3
    82fe:	d90c      	bls.n	831a <check_protection_reserved_nvm+0x5be>
    8300:	687a      	ldr	r2, [r7, #4]
    8302:	f64b 73ff 	movw	r3, #49151	; 0xbfff
    8306:	f2c0 0307 	movt	r3, #7
    830a:	429a      	cmp	r2, r3
    830c:	d805      	bhi.n	831a <check_protection_reserved_nvm+0x5be>
                    (offset <= LOWER1_PROTECT_TOP_OFFSET)) || \
                    (((offset + length_minus_one) >= LOWER1_PROTECT_BOTTOM_OFFSET) && \
                    (offset < LOWER1_PROTECT_BOTTOM_OFFSET)))
                {
                    protection_flag = protection_check(protection_user2, length);
    830e:	6a38      	ldr	r0, [r7, #32]
    8310:	6839      	ldr	r1, [r7, #0]
    8312:	f000 f873 	bl	83fc <protection_check>
    8316:	4603      	mov	r3, r0
    8318:	617b      	str	r3, [r7, #20]
                }
            }
            /* Checking NVM1 upper protected area for Read or Write or 'No R/W' access */
            if((READ_ONLY == protection_user3) ||(WRITE_ONLY == protection_user3) || \
    831a:	6a7b      	ldr	r3, [r7, #36]	; 0x24
    831c:	2b01      	cmp	r3, #1
    831e:	d005      	beq.n	832c <check_protection_reserved_nvm+0x5d0>
    8320:	6a7b      	ldr	r3, [r7, #36]	; 0x24
    8322:	2b08      	cmp	r3, #8
    8324:	d002      	beq.n	832c <check_protection_reserved_nvm+0x5d0>
    8326:	6a7b      	ldr	r3, [r7, #36]	; 0x24
    8328:	2b00      	cmp	r3, #0
    832a:	d123      	bne.n	8374 <check_protection_reserved_nvm+0x618>
               (NO_READ_WRITE == protection_user3))
            {
                /* Check offset or (offset + length)is in the range of upper1 
                 * protect memory if it is then memory protected.
                 */
                if(((offset >= UPPER1_PROTECT_BOTTOM_OFFSET) && \
    832c:	687a      	ldr	r2, [r7, #4]
    832e:	f64a 73ff 	movw	r3, #45055	; 0xafff
    8332:	f2c0 0307 	movt	r3, #7
    8336:	429a      	cmp	r2, r3
    8338:	d906      	bls.n	8348 <check_protection_reserved_nvm+0x5ec>
    833a:	687a      	ldr	r2, [r7, #4]
    833c:	f64b 73ff 	movw	r3, #49151	; 0xbfff
    8340:	f2c0 0307 	movt	r3, #7
    8344:	429a      	cmp	r2, r3
    8346:	d90f      	bls.n	8368 <check_protection_reserved_nvm+0x60c>
                    (offset <= UPPER1_PROTECT_TOP_OFFSET)) || \
                    (((offset + length_minus_one) >= UPPER1_PROTECT_BOTTOM_OFFSET) && \
    8348:	687a      	ldr	r2, [r7, #4]
    834a:	6abb      	ldr	r3, [r7, #40]	; 0x28
    834c:	441a      	add	r2, r3
               (NO_READ_WRITE == protection_user3))
            {
                /* Check offset or (offset + length)is in the range of upper1 
                 * protect memory if it is then memory protected.
                 */
                if(((offset >= UPPER1_PROTECT_BOTTOM_OFFSET) && \
    834e:	f64a 73ff 	movw	r3, #45055	; 0xafff
    8352:	f2c0 0307 	movt	r3, #7
    8356:	429a      	cmp	r2, r3
    8358:	d90c      	bls.n	8374 <check_protection_reserved_nvm+0x618>
    835a:	687a      	ldr	r2, [r7, #4]
    835c:	f64a 73ff 	movw	r3, #45055	; 0xafff
    8360:	f2c0 0307 	movt	r3, #7
    8364:	429a      	cmp	r2, r3
    8366:	d805      	bhi.n	8374 <check_protection_reserved_nvm+0x618>
                    (offset <= UPPER1_PROTECT_TOP_OFFSET)) || \
                    (((offset + length_minus_one) >= UPPER1_PROTECT_BOTTOM_OFFSET) && \
                    (offset < UPPER1_PROTECT_BOTTOM_OFFSET)))
                {
                    protection_flag = protection_check(protection_user3, length);
    8368:	6a78      	ldr	r0, [r7, #36]	; 0x24
    836a:	6839      	ldr	r1, [r7, #0]
    836c:	f000 f846 	bl	83fc <protection_check>
    8370:	4603      	mov	r3, r0
    8372:	617b      	str	r3, [r7, #20]
                }
            }
        }
        /* Check lower0/1 and upper0/1 memory is protected or not */
        if(PROTECTION_ON == protection_flag)
    8374:	697b      	ldr	r3, [r7, #20]
    8376:	2b01      	cmp	r3, #1
    8378:	d104      	bne.n	8384 <check_protection_reserved_nvm+0x628>
        {
           /* Status is protection error if lower or upper area of eNVM0 or 
            * eNVM1 is protected 
            */
            status = NVM_PROTECTION_ERROR;
    837a:	f04f 0301 	mov.w	r3, #1
    837e:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
    8382:	e034      	b.n	83ee <check_protection_reserved_nvm+0x692>
        }
        else
        {
            /* Check (offset + length) is out of eNVM memory */
            if((offset + length_minus_one) > NVM1_TOP_OFFSET)
    8384:	687a      	ldr	r2, [r7, #4]
    8386:	6abb      	ldr	r3, [r7, #40]	; 0x28
    8388:	441a      	add	r2, r3
    838a:	f64f 73ff 	movw	r3, #65535	; 0xffff
    838e:	f2c0 0307 	movt	r3, #7
    8392:	429a      	cmp	r2, r3
    8394:	d904      	bls.n	83a0 <check_protection_reserved_nvm+0x644>
            {
                status = NVM_INVALID_PARAMETER;
    8396:	f04f 0306 	mov.w	r3, #6
    839a:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
    839e:	e026      	b.n	83ee <check_protection_reserved_nvm+0x692>
            }
            else
            {
                /* Check offset is in eNVM reserved memory - 64 pages reserved */
                if(((offset >= NVM1_RSV_OFFSET) && (offset <= NVM1_TOP_OFFSET)) || \
    83a0:	687a      	ldr	r2, [r7, #4]
    83a2:	f64d 73ff 	movw	r3, #57343	; 0xdfff
    83a6:	f2c0 0307 	movt	r3, #7
    83aa:	429a      	cmp	r2, r3
    83ac:	d906      	bls.n	83bc <check_protection_reserved_nvm+0x660>
    83ae:	687a      	ldr	r2, [r7, #4]
    83b0:	f64f 73ff 	movw	r3, #65535	; 0xffff
    83b4:	f2c0 0307 	movt	r3, #7
    83b8:	429a      	cmp	r2, r3
    83ba:	d90f      	bls.n	83dc <check_protection_reserved_nvm+0x680>
                   (((offset + length_minus_one) >= NVM1_RSV_OFFSET) && \
    83bc:	687a      	ldr	r2, [r7, #4]
    83be:	6abb      	ldr	r3, [r7, #40]	; 0x28
    83c0:	441a      	add	r2, r3
                status = NVM_INVALID_PARAMETER;
            }
            else
            {
                /* Check offset is in eNVM reserved memory - 64 pages reserved */
                if(((offset >= NVM1_RSV_OFFSET) && (offset <= NVM1_TOP_OFFSET)) || \
    83c2:	f64d 73ff 	movw	r3, #57343	; 0xdfff
    83c6:	f2c0 0307 	movt	r3, #7
    83ca:	429a      	cmp	r2, r3
    83cc:	d90b      	bls.n	83e6 <check_protection_reserved_nvm+0x68a>
    83ce:	687a      	ldr	r2, [r7, #4]
    83d0:	f64d 73ff 	movw	r3, #57343	; 0xdfff
    83d4:	f2c0 0307 	movt	r3, #7
    83d8:	429a      	cmp	r2, r3
    83da:	d804      	bhi.n	83e6 <check_protection_reserved_nvm+0x68a>
                   (offset < NVM1_RSV_OFFSET)))
                {
                    /* Status is protection error if offset or (offset + length) is 
                     * in reserved area of eNVM
                     */
                    status = NVM_PROTECTION_ERROR;
    83dc:	f04f 0301 	mov.w	r3, #1
    83e0:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
                status = NVM_INVALID_PARAMETER;
            }
            else
            {
                /* Check offset is in eNVM reserved memory - 64 pages reserved */
                if(((offset >= NVM1_RSV_OFFSET) && (offset <= NVM1_TOP_OFFSET)) || \
    83e4:	e003      	b.n	83ee <check_protection_reserved_nvm+0x692>
                else
                {
                    /* Status is success if offset or (offset + length) is 
                     * in RW access of eNVM memory
                     */
                    status = NVM_SUCCESS;
    83e6:	f04f 0300 	mov.w	r3, #0
    83ea:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
                }
            }
        }
    }
    return status;
    83ee:	f897 302f 	ldrb.w	r3, [r7, #47]	; 0x2f
}
    83f2:	4618      	mov	r0, r3
    83f4:	f107 0730 	add.w	r7, r7, #48	; 0x30
    83f8:	46bd      	mov	sp, r7
    83fa:	bd80      	pop	{r7, pc}

000083fc <protection_check>:
 *
 * if the eNVM0 or eNVM1 lower/upper protected area with W-Only or No_RW
 * access then return with protection on
 */
static uint32_t protection_check(uint32_t protect_user, uint32_t length)
{    
    83fc:	b480      	push	{r7}
    83fe:	b085      	sub	sp, #20
    8400:	af00      	add	r7, sp, #0
    8402:	6078      	str	r0, [r7, #4]
    8404:	6039      	str	r1, [r7, #0]
    uint32_t protect_flag;
    
    /* Check Read Only access for page write count */
    if((READ_ONLY == protect_user) && (0x0u == length))
    8406:	687b      	ldr	r3, [r7, #4]
    8408:	2b01      	cmp	r3, #1
    840a:	d106      	bne.n	841a <protection_check+0x1e>
    840c:	683b      	ldr	r3, [r7, #0]
    840e:	2b00      	cmp	r3, #0
    8410:	d103      	bne.n	841a <protection_check+0x1e>
    {
        protect_flag = PROTECTION_OFF;
    8412:	f04f 0300 	mov.w	r3, #0
    8416:	60fb      	str	r3, [r7, #12]
static uint32_t protection_check(uint32_t protect_user, uint32_t length)
{    
    uint32_t protect_flag;
    
    /* Check Read Only access for page write count */
    if((READ_ONLY == protect_user) && (0x0u == length))
    8418:	e002      	b.n	8420 <protection_check+0x24>
    {
        protect_flag = PROTECTION_OFF;
    }
    else
    {
        protect_flag = PROTECTION_ON;
    841a:	f04f 0301 	mov.w	r3, #1
    841e:	60fb      	str	r3, [r7, #12]
    }
    return protect_flag;
    8420:	68fb      	ldr	r3, [r7, #12]
}
    8422:	4618      	mov	r0, r3
    8424:	f107 0714 	add.w	r7, r7, #20
    8428:	46bd      	mov	sp, r7
    842a:	bc80      	pop	{r7}
    842c:	4770      	bx	lr
    842e:	bf00      	nop

00008430 <NVIC_EnableIRQ>:
    The function enables a device-specific interrupt in the NVIC interrupt controller.

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
    8430:	b480      	push	{r7}
    8432:	b083      	sub	sp, #12
    8434:	af00      	add	r7, sp, #0
    8436:	4603      	mov	r3, r0
    8438:	71fb      	strb	r3, [r7, #7]
  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
    843a:	f24e 1300 	movw	r3, #57600	; 0xe100
    843e:	f2ce 0300 	movt	r3, #57344	; 0xe000
    8442:	f997 2007 	ldrsb.w	r2, [r7, #7]
    8446:	ea4f 1252 	mov.w	r2, r2, lsr #5
    844a:	79f9      	ldrb	r1, [r7, #7]
    844c:	f001 011f 	and.w	r1, r1, #31
    8450:	f04f 0001 	mov.w	r0, #1
    8454:	fa00 f101 	lsl.w	r1, r0, r1
    8458:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
}
    845c:	f107 070c 	add.w	r7, r7, #12
    8460:	46bd      	mov	sp, r7
    8462:	bc80      	pop	{r7}
    8464:	4770      	bx	lr
    8466:	bf00      	nop

00008468 <NVIC_DisableIRQ>:
    The function disables a device-specific interrupt in the NVIC interrupt controller.

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
    8468:	b480      	push	{r7}
    846a:	b083      	sub	sp, #12
    846c:	af00      	add	r7, sp, #0
    846e:	4603      	mov	r3, r0
    8470:	71fb      	strb	r3, [r7, #7]
  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
    8472:	f24e 1300 	movw	r3, #57600	; 0xe100
    8476:	f2ce 0300 	movt	r3, #57344	; 0xe000
    847a:	f997 2007 	ldrsb.w	r2, [r7, #7]
    847e:	ea4f 1252 	mov.w	r2, r2, lsr #5
    8482:	79f9      	ldrb	r1, [r7, #7]
    8484:	f001 011f 	and.w	r1, r1, #31
    8488:	f04f 0001 	mov.w	r0, #1
    848c:	fa00 f101 	lsl.w	r1, r0, r1
    8490:	f102 0220 	add.w	r2, r2, #32
    8494:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
}
    8498:	f107 070c 	add.w	r7, r7, #12
    849c:	46bd      	mov	sp, r7
    849e:	bc80      	pop	{r7}
    84a0:	4770      	bx	lr
    84a2:	bf00      	nop

000084a4 <NVIC_ClearPendingIRQ>:
    The function clears the pending bit of an external interrupt.

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
    84a4:	b480      	push	{r7}
    84a6:	b083      	sub	sp, #12
    84a8:	af00      	add	r7, sp, #0
    84aa:	4603      	mov	r3, r0
    84ac:	71fb      	strb	r3, [r7, #7]
  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
    84ae:	f24e 1300 	movw	r3, #57600	; 0xe100
    84b2:	f2ce 0300 	movt	r3, #57344	; 0xe000
    84b6:	f997 2007 	ldrsb.w	r2, [r7, #7]
    84ba:	ea4f 1252 	mov.w	r2, r2, lsr #5
    84be:	79f9      	ldrb	r1, [r7, #7]
    84c0:	f001 011f 	and.w	r1, r1, #31
    84c4:	f04f 0001 	mov.w	r0, #1
    84c8:	fa00 f101 	lsl.w	r1, r0, r1
    84cc:	f102 0260 	add.w	r2, r2, #96	; 0x60
    84d0:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
}
    84d4:	f107 070c 	add.w	r7, r7, #12
    84d8:	46bd      	mov	sp, r7
    84da:	bc80      	pop	{r7}
    84dc:	4770      	bx	lr
    84de:	bf00      	nop

000084e0 <MSS_HPDMA_init>:
void
MSS_HPDMA_init
(
    void
)
{
    84e0:	b580      	push	{r7, lr}
    84e2:	b082      	sub	sp, #8
    84e4:	af00      	add	r7, sp, #0
    uint8_t inc;
    
    /* Reset HPDMA block. */
    SYSREG->SOFT_RST_CR |= HPDMA_SOFT_RESET;
    84e6:	f248 0300 	movw	r3, #32768	; 0x8000
    84ea:	f2c4 0303 	movt	r3, #16387	; 0x4003
    84ee:	f248 0200 	movw	r2, #32768	; 0x8000
    84f2:	f2c4 0203 	movt	r2, #16387	; 0x4003
    84f6:	6c92      	ldr	r2, [r2, #72]	; 0x48
    84f8:	f442 3200 	orr.w	r2, r2, #131072	; 0x20000
    84fc:	649a      	str	r2, [r3, #72]	; 0x48

    /* Take HPDMA controller out of reset. */
    SYSREG->SOFT_RST_CR &= ~HPDMA_SOFT_RESET;
    84fe:	f248 0300 	movw	r3, #32768	; 0x8000
    8502:	f2c4 0303 	movt	r3, #16387	; 0x4003
    8506:	f248 0200 	movw	r2, #32768	; 0x8000
    850a:	f2c4 0203 	movt	r2, #16387	; 0x4003
    850e:	6c92      	ldr	r2, [r2, #72]	; 0x48
    8510:	f422 3200 	bic.w	r2, r2, #131072	; 0x20000
    8514:	649a      	str	r2, [r3, #72]	; 0x48

    /* Initialize data structures. */
    g_transfer.xfr_size = 0u;
    8516:	f240 138c 	movw	r3, #396	; 0x18c
    851a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    851e:	f04f 0200 	mov.w	r2, #0
    8522:	611a      	str	r2, [r3, #16]
    g_transfer.completion_handler = NULL_HANDLER;
    8524:	f240 138c 	movw	r3, #396	; 0x18c
    8528:	f2c2 0300 	movt	r3, #8192	; 0x2000
    852c:	f04f 0200 	mov.w	r2, #0
    8530:	605a      	str	r2, [r3, #4]
    g_transfer.state = HPDMA_COMPLETED;
    8532:	f240 138c 	movw	r3, #396	; 0x18c
    8536:	f2c2 0300 	movt	r3, #8192	; 0x2000
    853a:	f04f 0201 	mov.w	r2, #1
    853e:	701a      	strb	r2, [r3, #0]
    
    for(inc = 0u; inc < NO_OF_HPDMA_DESCRIPTORS; inc++)
    8540:	f04f 0300 	mov.w	r3, #0
    8544:	71fb      	strb	r3, [r7, #7]
    8546:	e035      	b.n	85b4 <MSS_HPDMA_init+0xd4>
    {
        /* Pause transfer. */
        HPDMA_BITBAND->Descriptor[inc].HPDMACR_DCP_PAUSE = HPDMA_ENABLE;
    8548:	f240 0200 	movw	r2, #0
    854c:	f2c4 2228 	movt	r2, #16936	; 0x4228
    8550:	79f9      	ldrb	r1, [r7, #7]
    8552:	460b      	mov	r3, r1
    8554:	ea4f 0383 	mov.w	r3, r3, lsl #2
    8558:	440b      	add	r3, r1
    855a:	ea4f 13c3 	mov.w	r3, r3, lsl #7
    855e:	4413      	add	r3, r2
    8560:	f503 73e6 	add.w	r3, r3, #460	; 0x1cc
    8564:	f04f 0201 	mov.w	r2, #1
    8568:	601a      	str	r2, [r3, #0]
        /* Disable Interrupt. */
        HPDMA->Descriptor[inc].HPDMACR_REG &= ~HPDMACR_ALL_IRQ_ENABLE_MASK;
    856a:	f244 0200 	movw	r2, #16384	; 0x4000
    856e:	f2c4 0201 	movt	r2, #16385	; 0x4001
    8572:	79f8      	ldrb	r0, [r7, #7]
    8574:	f244 0100 	movw	r1, #16384	; 0x4000
    8578:	f2c4 0101 	movt	r1, #16385	; 0x4001
    857c:	f897 c007 	ldrb.w	ip, [r7, #7]
    8580:	4663      	mov	r3, ip
    8582:	ea4f 0383 	mov.w	r3, r3, lsl #2
    8586:	4463      	add	r3, ip
    8588:	ea4f 0383 	mov.w	r3, r3, lsl #2
    858c:	440b      	add	r3, r1
    858e:	f103 030c 	add.w	r3, r3, #12
    8592:	681b      	ldr	r3, [r3, #0]
    8594:	f423 01e0 	bic.w	r1, r3, #7340032	; 0x700000
    8598:	4603      	mov	r3, r0
    859a:	ea4f 0383 	mov.w	r3, r3, lsl #2
    859e:	4403      	add	r3, r0
    85a0:	ea4f 0383 	mov.w	r3, r3, lsl #2
    85a4:	4413      	add	r3, r2
    85a6:	f103 030c 	add.w	r3, r3, #12
    85aa:	6019      	str	r1, [r3, #0]
    /* Initialize data structures. */
    g_transfer.xfr_size = 0u;
    g_transfer.completion_handler = NULL_HANDLER;
    g_transfer.state = HPDMA_COMPLETED;
    
    for(inc = 0u; inc < NO_OF_HPDMA_DESCRIPTORS; inc++)
    85ac:	79fb      	ldrb	r3, [r7, #7]
    85ae:	f103 0301 	add.w	r3, r3, #1
    85b2:	71fb      	strb	r3, [r7, #7]
    85b4:	79fb      	ldrb	r3, [r7, #7]
    85b6:	2b03      	cmp	r3, #3
    85b8:	d9c6      	bls.n	8548 <MSS_HPDMA_init+0x68>
        HPDMA_BITBAND->Descriptor[inc].HPDMACR_DCP_PAUSE = HPDMA_ENABLE;
        /* Disable Interrupt. */
        HPDMA->Descriptor[inc].HPDMACR_REG &= ~HPDMACR_ALL_IRQ_ENABLE_MASK;
    }     

    NVIC_DisableIRQ(HPDMA_Complete_IRQn);
    85ba:	f04f 001b 	mov.w	r0, #27
    85be:	f7ff ff53 	bl	8468 <NVIC_DisableIRQ>
    NVIC_DisableIRQ(HPDMA_Error_IRQn);
    85c2:	f04f 001c 	mov.w	r0, #28
    85c6:	f7ff ff4f 	bl	8468 <NVIC_DisableIRQ>
    /* Clear any previously pending MSS HPDMA interrupt. */
    NVIC_ClearPendingIRQ(HPDMA_Error_IRQn);
    85ca:	f04f 001c 	mov.w	r0, #28
    85ce:	f7ff ff69 	bl	84a4 <NVIC_ClearPendingIRQ>
    NVIC_ClearPendingIRQ(HPDMA_Complete_IRQn);
    85d2:	f04f 001b 	mov.w	r0, #27
    85d6:	f7ff ff65 	bl	84a4 <NVIC_ClearPendingIRQ>
    
    /* Clear all interrupts. */
    HPDMA->HPDMAICR_REG = HPDMAICR_CLEAR_ALL_IRQ;
    85da:	f244 0300 	movw	r3, #16384	; 0x4000
    85de:	f2c4 0301 	movt	r3, #16385	; 0x4001
    85e2:	f04f 02ff 	mov.w	r2, #255	; 0xff
    85e6:	655a      	str	r2, [r3, #84]	; 0x54
}
    85e8:	f107 0708 	add.w	r7, r7, #8
    85ec:	46bd      	mov	sp, r7
    85ee:	bd80      	pop	{r7, pc}

000085f0 <MSS_HPDMA_start>:
    uint32_t src_addr,
    uint32_t dest_addr,
    uint32_t transfer_size,
    uint8_t transfer_dir
)
{
    85f0:	b580      	push	{r7, lr}
    85f2:	b086      	sub	sp, #24
    85f4:	af00      	add	r7, sp, #0
    85f6:	60f8      	str	r0, [r7, #12]
    85f8:	60b9      	str	r1, [r7, #8]
    85fa:	607a      	str	r2, [r7, #4]
    85fc:	70fb      	strb	r3, [r7, #3]
    uint32_t hpdma_total_desc = 0u;
    85fe:	f04f 0300 	mov.w	r3, #0
    8602:	617b      	str	r3, [r7, #20]

    ASSERT((src_addr & ADDRESS_NON_WORD_ALIGNED_MASK) == 0u); 
    8604:	68fb      	ldr	r3, [r7, #12]
    8606:	f003 0303 	and.w	r3, r3, #3
    860a:	2b00      	cmp	r3, #0
    860c:	d000      	beq.n	8610 <MSS_HPDMA_start+0x20>
    860e:	be00      	bkpt	0x0000
    ASSERT((dest_addr & ADDRESS_NON_WORD_ALIGNED_MASK) == 0u);      
    8610:	68bb      	ldr	r3, [r7, #8]
    8612:	f003 0303 	and.w	r3, r3, #3
    8616:	2b00      	cmp	r3, #0
    8618:	d000      	beq.n	861c <MSS_HPDMA_start+0x2c>
    861a:	be00      	bkpt	0x0000
    ASSERT((g_transfer.state != HPDMA_IN_PROGRESS) && (transfer_size > 0u));
    861c:	f240 138c 	movw	r3, #396	; 0x18c
    8620:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8624:	781b      	ldrb	r3, [r3, #0]
    8626:	b2db      	uxtb	r3, r3
    8628:	2b00      	cmp	r3, #0
    862a:	d002      	beq.n	8632 <MSS_HPDMA_start+0x42>
    862c:	687b      	ldr	r3, [r7, #4]
    862e:	2b00      	cmp	r3, #0
    8630:	d100      	bne.n	8634 <MSS_HPDMA_start+0x44>
    8632:	be00      	bkpt	0x0000
    
    /* Check transfer_size is not zero and that a transfer is not in progress */   
    if((g_transfer.state != HPDMA_IN_PROGRESS) && (transfer_size > 0u))
    8634:	f240 138c 	movw	r3, #396	; 0x18c
    8638:	f2c2 0300 	movt	r3, #8192	; 0x2000
    863c:	781b      	ldrb	r3, [r3, #0]
    863e:	b2db      	uxtb	r3, r3
    8640:	2b00      	cmp	r3, #0
    8642:	d071      	beq.n	8728 <MSS_HPDMA_start+0x138>
    8644:	687b      	ldr	r3, [r7, #4]
    8646:	2b00      	cmp	r3, #0
    8648:	d06e      	beq.n	8728 <MSS_HPDMA_start+0x138>
    {        
        NVIC_EnableIRQ(HPDMA_Complete_IRQn);
    864a:	f04f 001b 	mov.w	r0, #27
    864e:	f7ff feef 	bl	8430 <NVIC_EnableIRQ>
        NVIC_EnableIRQ(HPDMA_Error_IRQn);
    8652:	f04f 001c 	mov.w	r0, #28
    8656:	f7ff feeb 	bl	8430 <NVIC_EnableIRQ>
   
        g_transfer.xfr_size = transfer_size;
    865a:	f240 138c 	movw	r3, #396	; 0x18c
    865e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8662:	687a      	ldr	r2, [r7, #4]
    8664:	611a      	str	r2, [r3, #16]
        g_transfer.des_addr = dest_addr;
    8666:	f240 138c 	movw	r3, #396	; 0x18c
    866a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    866e:	68ba      	ldr	r2, [r7, #8]
    8670:	60da      	str	r2, [r3, #12]
        g_transfer.src_addr = src_addr; 
    8672:	f240 138c 	movw	r3, #396	; 0x18c
    8676:	f2c2 0300 	movt	r3, #8192	; 0x2000
    867a:	68fa      	ldr	r2, [r7, #12]
    867c:	609a      	str	r2, [r3, #8]
        g_transfer.xfr_dir = transfer_dir;
    867e:	f240 138c 	movw	r3, #396	; 0x18c
    8682:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8686:	78fa      	ldrb	r2, [r7, #3]
    8688:	751a      	strb	r2, [r3, #20]
        /* Total no of descriptors used for transfer */
        hpdma_total_desc = ((transfer_size - 1u) / MAX_SIZE_PER_DMA_XFR) + 1u;
    868a:	687b      	ldr	r3, [r7, #4]
    868c:	f103 33ff 	add.w	r3, r3, #4294967295
    8690:	ea4f 4313 	mov.w	r3, r3, lsr #16
    8694:	f103 0301 	add.w	r3, r3, #1
    8698:	617b      	str	r3, [r7, #20]
        /* Current HPDMA descriptor */
        g_hpdma_current_desc = 0u;         
    869a:	f240 13a8 	movw	r3, #424	; 0x1a8
    869e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    86a2:	f04f 0200 	mov.w	r2, #0
    86a6:	601a      	str	r2, [r3, #0]
        g_hpdma_end_desc = 0u; 
    86a8:	f240 13a4 	movw	r3, #420	; 0x1a4
    86ac:	f2c2 0300 	movt	r3, #8192	; 0x2000
    86b0:	f04f 0200 	mov.w	r2, #0
    86b4:	601a      	str	r2, [r3, #0]
        
        /* Start transfer */
        g_transfer.state = HPDMA_IN_PROGRESS; 
    86b6:	f240 138c 	movw	r3, #396	; 0x18c
    86ba:	f2c2 0300 	movt	r3, #8192	; 0x2000
    86be:	f04f 0200 	mov.w	r2, #0
    86c2:	701a      	strb	r2, [r3, #0]
        
        while((g_hpdma_end_desc < hpdma_total_desc) && (g_hpdma_end_desc < NO_OF_HPDMA_DESCRIPTORS))  
    86c4:	e021      	b.n	870a <MSS_HPDMA_start+0x11a>
        {          
            start_transfer(g_transfer.src_addr,
    86c6:	f240 138c 	movw	r3, #396	; 0x18c
    86ca:	f2c2 0300 	movt	r3, #8192	; 0x2000
    86ce:	6898      	ldr	r0, [r3, #8]
    86d0:	f240 138c 	movw	r3, #396	; 0x18c
    86d4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    86d8:	68d9      	ldr	r1, [r3, #12]
    86da:	f240 138c 	movw	r3, #396	; 0x18c
    86de:	f2c2 0300 	movt	r3, #8192	; 0x2000
    86e2:	691a      	ldr	r2, [r3, #16]
    86e4:	f240 138c 	movw	r3, #396	; 0x18c
    86e8:	f2c2 0300 	movt	r3, #8192	; 0x2000
    86ec:	7d1b      	ldrb	r3, [r3, #20]
    86ee:	f000 f81f 	bl	8730 <start_transfer>
                            g_transfer.des_addr,
                            g_transfer.xfr_size,
                            g_transfer.xfr_dir);
                        
            ++g_hpdma_end_desc;            
    86f2:	f240 13a4 	movw	r3, #420	; 0x1a4
    86f6:	f2c2 0300 	movt	r3, #8192	; 0x2000
    86fa:	681b      	ldr	r3, [r3, #0]
    86fc:	f103 0201 	add.w	r2, r3, #1
    8700:	f240 13a4 	movw	r3, #420	; 0x1a4
    8704:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8708:	601a      	str	r2, [r3, #0]
        g_hpdma_end_desc = 0u; 
        
        /* Start transfer */
        g_transfer.state = HPDMA_IN_PROGRESS; 
        
        while((g_hpdma_end_desc < hpdma_total_desc) && (g_hpdma_end_desc < NO_OF_HPDMA_DESCRIPTORS))  
    870a:	f240 13a4 	movw	r3, #420	; 0x1a4
    870e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8712:	681a      	ldr	r2, [r3, #0]
    8714:	697b      	ldr	r3, [r7, #20]
    8716:	429a      	cmp	r2, r3
    8718:	d206      	bcs.n	8728 <MSS_HPDMA_start+0x138>
    871a:	f240 13a4 	movw	r3, #420	; 0x1a4
    871e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8722:	681b      	ldr	r3, [r3, #0]
    8724:	2b03      	cmp	r3, #3
    8726:	d9ce      	bls.n	86c6 <MSS_HPDMA_start+0xd6>
                            g_transfer.xfr_dir);
                        
            ++g_hpdma_end_desc;            
        }
   }
}
    8728:	f107 0718 	add.w	r7, r7, #24
    872c:	46bd      	mov	sp, r7
    872e:	bd80      	pop	{r7, pc}

00008730 <start_transfer>:
    uint32_t src_addr,
    uint32_t dest_addr,
    uint32_t transfer_size,
    uint8_t transfer_dir
)
{
    8730:	b480      	push	{r7}
    8732:	b085      	sub	sp, #20
    8734:	af00      	add	r7, sp, #0
    8736:	60f8      	str	r0, [r7, #12]
    8738:	60b9      	str	r1, [r7, #8]
    873a:	607a      	str	r2, [r7, #4]
    873c:	70fb      	strb	r3, [r7, #3]
    /* Set descriptor transfer direction */
    HPDMA_BITBAND->Descriptor[g_hpdma_end_desc].HPDMACR_DCP_XFR_DIR = transfer_dir;
    873e:	f240 0200 	movw	r2, #0
    8742:	f2c4 2228 	movt	r2, #16936	; 0x4228
    8746:	f240 13a4 	movw	r3, #420	; 0x1a4
    874a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    874e:	6819      	ldr	r1, [r3, #0]
    8750:	78f8      	ldrb	r0, [r7, #3]
    8752:	460b      	mov	r3, r1
    8754:	ea4f 0383 	mov.w	r3, r3, lsl #2
    8758:	440b      	add	r3, r1
    875a:	ea4f 13c3 	mov.w	r3, r3, lsl #7
    875e:	4413      	add	r3, r2
    8760:	f503 73e2 	add.w	r3, r3, #452	; 0x1c4
    8764:	6018      	str	r0, [r3, #0]
    
    /* Store Source and destination Address */
    HPDMA->Descriptor[g_hpdma_end_desc].HPDMASAR_REG = src_addr;
    8766:	f244 0200 	movw	r2, #16384	; 0x4000
    876a:	f2c4 0201 	movt	r2, #16385	; 0x4001
    876e:	f240 13a4 	movw	r3, #420	; 0x1a4
    8772:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8776:	6819      	ldr	r1, [r3, #0]
    8778:	460b      	mov	r3, r1
    877a:	ea4f 0383 	mov.w	r3, r3, lsl #2
    877e:	440b      	add	r3, r1
    8780:	ea4f 0383 	mov.w	r3, r3, lsl #2
    8784:	4413      	add	r3, r2
    8786:	f103 0304 	add.w	r3, r3, #4
    878a:	68fa      	ldr	r2, [r7, #12]
    878c:	601a      	str	r2, [r3, #0]
    HPDMA->Descriptor[g_hpdma_end_desc].HPDMADAR_REG = dest_addr;
    878e:	f244 0200 	movw	r2, #16384	; 0x4000
    8792:	f2c4 0201 	movt	r2, #16385	; 0x4001
    8796:	f240 13a4 	movw	r3, #420	; 0x1a4
    879a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    879e:	6819      	ldr	r1, [r3, #0]
    87a0:	460b      	mov	r3, r1
    87a2:	ea4f 0383 	mov.w	r3, r3, lsl #2
    87a6:	440b      	add	r3, r1
    87a8:	ea4f 0383 	mov.w	r3, r3, lsl #2
    87ac:	4413      	add	r3, r2
    87ae:	f103 0308 	add.w	r3, r3, #8
    87b2:	68ba      	ldr	r2, [r7, #8]
    87b4:	601a      	str	r2, [r3, #0]
    
    /* Set the transfer size to 64K */
    HPDMA->Descriptor[g_hpdma_end_desc].HPDMACR_REG &= HPDMA_XFR_SIZE_MASK;
    87b6:	f244 0100 	movw	r1, #16384	; 0x4000
    87ba:	f2c4 0101 	movt	r1, #16385	; 0x4001
    87be:	f240 13a4 	movw	r3, #420	; 0x1a4
    87c2:	f2c2 0300 	movt	r3, #8192	; 0x2000
    87c6:	6818      	ldr	r0, [r3, #0]
    87c8:	f244 0200 	movw	r2, #16384	; 0x4000
    87cc:	f2c4 0201 	movt	r2, #16385	; 0x4001
    87d0:	f240 13a4 	movw	r3, #420	; 0x1a4
    87d4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    87d8:	f8d3 c000 	ldr.w	ip, [r3]
    87dc:	4663      	mov	r3, ip
    87de:	ea4f 0383 	mov.w	r3, r3, lsl #2
    87e2:	4463      	add	r3, ip
    87e4:	ea4f 0383 	mov.w	r3, r3, lsl #2
    87e8:	4413      	add	r3, r2
    87ea:	f103 030c 	add.w	r3, r3, #12
    87ee:	681b      	ldr	r3, [r3, #0]
    87f0:	ea4f 4213 	mov.w	r2, r3, lsr #16
    87f4:	ea4f 4202 	mov.w	r2, r2, lsl #16
    87f8:	4603      	mov	r3, r0
    87fa:	ea4f 0383 	mov.w	r3, r3, lsl #2
    87fe:	4403      	add	r3, r0
    8800:	ea4f 0383 	mov.w	r3, r3, lsl #2
    8804:	440b      	add	r3, r1
    8806:	f103 030c 	add.w	r3, r3, #12
    880a:	601a      	str	r2, [r3, #0]
    
    if(transfer_size > MAX_SIZE_PER_DMA_XFR)
    880c:	687b      	ldr	r3, [r7, #4]
    880e:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
    8812:	d918      	bls.n	8846 <start_transfer+0x116>
    {
        g_transfer.xfr_size = transfer_size - MAX_SIZE_PER_DMA_XFR;
    8814:	687b      	ldr	r3, [r7, #4]
    8816:	f5a3 3280 	sub.w	r2, r3, #65536	; 0x10000
    881a:	f240 138c 	movw	r3, #396	; 0x18c
    881e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8822:	611a      	str	r2, [r3, #16]
        g_transfer.des_addr = dest_addr + MAX_SIZE_PER_DMA_XFR;
    8824:	68bb      	ldr	r3, [r7, #8]
    8826:	f503 3280 	add.w	r2, r3, #65536	; 0x10000
    882a:	f240 138c 	movw	r3, #396	; 0x18c
    882e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8832:	60da      	str	r2, [r3, #12]
        g_transfer.src_addr = src_addr + MAX_SIZE_PER_DMA_XFR; 
    8834:	68fb      	ldr	r3, [r7, #12]
    8836:	f503 3280 	add.w	r2, r3, #65536	; 0x10000
    883a:	f240 138c 	movw	r3, #396	; 0x18c
    883e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8842:	609a      	str	r2, [r3, #8]
    8844:	e031      	b.n	88aa <start_transfer+0x17a>
    }
    else
    {
        /* Set descriptor transfer size */
        HPDMA->Descriptor[g_hpdma_end_desc].HPDMACR_REG |= (uint16_t)transfer_size;
    8846:	f244 0200 	movw	r2, #16384	; 0x4000
    884a:	f2c4 0201 	movt	r2, #16385	; 0x4001
    884e:	f240 13a4 	movw	r3, #420	; 0x1a4
    8852:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8856:	6818      	ldr	r0, [r3, #0]
    8858:	f244 0100 	movw	r1, #16384	; 0x4000
    885c:	f2c4 0101 	movt	r1, #16385	; 0x4001
    8860:	f240 13a4 	movw	r3, #420	; 0x1a4
    8864:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8868:	f8d3 c000 	ldr.w	ip, [r3]
    886c:	4663      	mov	r3, ip
    886e:	ea4f 0383 	mov.w	r3, r3, lsl #2
    8872:	4463      	add	r3, ip
    8874:	ea4f 0383 	mov.w	r3, r3, lsl #2
    8878:	440b      	add	r3, r1
    887a:	f103 030c 	add.w	r3, r3, #12
    887e:	6819      	ldr	r1, [r3, #0]
    8880:	687b      	ldr	r3, [r7, #4]
    8882:	b29b      	uxth	r3, r3
    8884:	ea41 0103 	orr.w	r1, r1, r3
    8888:	4603      	mov	r3, r0
    888a:	ea4f 0383 	mov.w	r3, r3, lsl #2
    888e:	4403      	add	r3, r0
    8890:	ea4f 0383 	mov.w	r3, r3, lsl #2
    8894:	4413      	add	r3, r2
    8896:	f103 030c 	add.w	r3, r3, #12
    889a:	6019      	str	r1, [r3, #0]
        g_transfer.xfr_size = 0u;     
    889c:	f240 138c 	movw	r3, #396	; 0x18c
    88a0:	f2c2 0300 	movt	r3, #8192	; 0x2000
    88a4:	f04f 0200 	mov.w	r2, #0
    88a8:	611a      	str	r2, [r3, #16]
    }    
    /* Enable interrupts for the requested descriptor. */
    HPDMA->Descriptor[g_hpdma_end_desc].HPDMACR_REG |= HPDMACR_ALL_IRQ_ENABLE_MASK;       
    88aa:	f244 0200 	movw	r2, #16384	; 0x4000
    88ae:	f2c4 0201 	movt	r2, #16385	; 0x4001
    88b2:	f240 13a4 	movw	r3, #420	; 0x1a4
    88b6:	f2c2 0300 	movt	r3, #8192	; 0x2000
    88ba:	6818      	ldr	r0, [r3, #0]
    88bc:	f244 0100 	movw	r1, #16384	; 0x4000
    88c0:	f2c4 0101 	movt	r1, #16385	; 0x4001
    88c4:	f240 13a4 	movw	r3, #420	; 0x1a4
    88c8:	f2c2 0300 	movt	r3, #8192	; 0x2000
    88cc:	f8d3 c000 	ldr.w	ip, [r3]
    88d0:	4663      	mov	r3, ip
    88d2:	ea4f 0383 	mov.w	r3, r3, lsl #2
    88d6:	4463      	add	r3, ip
    88d8:	ea4f 0383 	mov.w	r3, r3, lsl #2
    88dc:	440b      	add	r3, r1
    88de:	f103 030c 	add.w	r3, r3, #12
    88e2:	681b      	ldr	r3, [r3, #0]
    88e4:	f443 01e0 	orr.w	r1, r3, #7340032	; 0x700000
    88e8:	4603      	mov	r3, r0
    88ea:	ea4f 0383 	mov.w	r3, r3, lsl #2
    88ee:	4403      	add	r3, r0
    88f0:	ea4f 0383 	mov.w	r3, r3, lsl #2
    88f4:	4413      	add	r3, r2
    88f6:	f103 030c 	add.w	r3, r3, #12
    88fa:	6019      	str	r1, [r3, #0]
    /* Set valid descriptor to start transfer */
    HPDMA_BITBAND->Descriptor[g_hpdma_end_desc].HPDMACR_DCP_VALID = HPDMA_ENABLE;  
    88fc:	f240 0200 	movw	r2, #0
    8900:	f2c4 2228 	movt	r2, #16936	; 0x4228
    8904:	f240 13a4 	movw	r3, #420	; 0x1a4
    8908:	f2c2 0300 	movt	r3, #8192	; 0x2000
    890c:	6819      	ldr	r1, [r3, #0]
    890e:	460b      	mov	r3, r1
    8910:	ea4f 0383 	mov.w	r3, r3, lsl #2
    8914:	440b      	add	r3, r1
    8916:	ea4f 13c3 	mov.w	r3, r3, lsl #7
    891a:	4413      	add	r3, r2
    891c:	f503 73e0 	add.w	r3, r3, #448	; 0x1c0
    8920:	f04f 0201 	mov.w	r2, #1
    8924:	601a      	str	r2, [r3, #0]
    /* Start transfer */
    HPDMA_BITBAND->Descriptor[g_hpdma_end_desc].HPDMACR_DCP_PAUSE = HPDMA_DISABLE;        
    8926:	f240 0200 	movw	r2, #0
    892a:	f2c4 2228 	movt	r2, #16936	; 0x4228
    892e:	f240 13a4 	movw	r3, #420	; 0x1a4
    8932:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8936:	6819      	ldr	r1, [r3, #0]
    8938:	460b      	mov	r3, r1
    893a:	ea4f 0383 	mov.w	r3, r3, lsl #2
    893e:	440b      	add	r3, r1
    8940:	ea4f 13c3 	mov.w	r3, r3, lsl #7
    8944:	4413      	add	r3, r2
    8946:	f503 73e6 	add.w	r3, r3, #460	; 0x1cc
    894a:	f04f 0200 	mov.w	r2, #0
    894e:	601a      	str	r2, [r3, #0]
}
    8950:	f107 0714 	add.w	r7, r7, #20
    8954:	46bd      	mov	sp, r7
    8956:	bc80      	pop	{r7}
    8958:	4770      	bx	lr
    895a:	bf00      	nop

0000895c <MSS_HPDMA_pause>:
void
MSS_HPDMA_pause
(
    void
)
{
    895c:	b480      	push	{r7}
    895e:	af00      	add	r7, sp, #0
    /* Pause transfer */
    HPDMA_BITBAND->Descriptor[g_hpdma_current_desc].HPDMACR_DCP_PAUSE = HPDMA_ENABLE;
    8960:	f240 0200 	movw	r2, #0
    8964:	f2c4 2228 	movt	r2, #16936	; 0x4228
    8968:	f240 13a8 	movw	r3, #424	; 0x1a8
    896c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8970:	6819      	ldr	r1, [r3, #0]
    8972:	460b      	mov	r3, r1
    8974:	ea4f 0383 	mov.w	r3, r3, lsl #2
    8978:	440b      	add	r3, r1
    897a:	ea4f 13c3 	mov.w	r3, r3, lsl #7
    897e:	4413      	add	r3, r2
    8980:	f503 73e6 	add.w	r3, r3, #460	; 0x1cc
    8984:	f04f 0201 	mov.w	r2, #1
    8988:	601a      	str	r2, [r3, #0]
}
    898a:	46bd      	mov	sp, r7
    898c:	bc80      	pop	{r7}
    898e:	4770      	bx	lr

00008990 <MSS_HPDMA_resume>:
void
MSS_HPDMA_resume
(
    void
)
{
    8990:	b480      	push	{r7}
    8992:	af00      	add	r7, sp, #0
    /* Resume transfer */
    HPDMA_BITBAND->Descriptor[g_hpdma_current_desc].HPDMACR_DCP_PAUSE = HPDMA_DISABLE;
    8994:	f240 0200 	movw	r2, #0
    8998:	f2c4 2228 	movt	r2, #16936	; 0x4228
    899c:	f240 13a8 	movw	r3, #424	; 0x1a8
    89a0:	f2c2 0300 	movt	r3, #8192	; 0x2000
    89a4:	6819      	ldr	r1, [r3, #0]
    89a6:	460b      	mov	r3, r1
    89a8:	ea4f 0383 	mov.w	r3, r3, lsl #2
    89ac:	440b      	add	r3, r1
    89ae:	ea4f 13c3 	mov.w	r3, r3, lsl #7
    89b2:	4413      	add	r3, r2
    89b4:	f503 73e6 	add.w	r3, r3, #460	; 0x1cc
    89b8:	f04f 0200 	mov.w	r2, #0
    89bc:	601a      	str	r2, [r3, #0]
}
    89be:	46bd      	mov	sp, r7
    89c0:	bc80      	pop	{r7}
    89c2:	4770      	bx	lr

000089c4 <MSS_HPDMA_abort>:
void
MSS_HPDMA_abort
(
    void
)
{
    89c4:	b480      	push	{r7}
    89c6:	b083      	sub	sp, #12
    89c8:	af00      	add	r7, sp, #0
    uint32_t inc;
    
    for(inc = 0u; inc < NO_OF_HPDMA_DESCRIPTORS; inc++)
    89ca:	f04f 0300 	mov.w	r3, #0
    89ce:	607b      	str	r3, [r7, #4]
    89d0:	e014      	b.n	89fc <MSS_HPDMA_abort+0x38>
    {
        /* Abort transfer. */
        HPDMA_BITBAND->Descriptor[inc].HPDMACR_DCP_CLR = HPDMA_ENABLE;
    89d2:	f240 0200 	movw	r2, #0
    89d6:	f2c4 2228 	movt	r2, #16936	; 0x4228
    89da:	6879      	ldr	r1, [r7, #4]
    89dc:	460b      	mov	r3, r1
    89de:	ea4f 0383 	mov.w	r3, r3, lsl #2
    89e2:	440b      	add	r3, r1
    89e4:	ea4f 13c3 	mov.w	r3, r3, lsl #7
    89e8:	4413      	add	r3, r2
    89ea:	f503 73e4 	add.w	r3, r3, #456	; 0x1c8
    89ee:	f04f 0201 	mov.w	r2, #1
    89f2:	601a      	str	r2, [r3, #0]
    void
)
{
    uint32_t inc;
    
    for(inc = 0u; inc < NO_OF_HPDMA_DESCRIPTORS; inc++)
    89f4:	687b      	ldr	r3, [r7, #4]
    89f6:	f103 0301 	add.w	r3, r3, #1
    89fa:	607b      	str	r3, [r7, #4]
    89fc:	687b      	ldr	r3, [r7, #4]
    89fe:	2b03      	cmp	r3, #3
    8a00:	d9e7      	bls.n	89d2 <MSS_HPDMA_abort+0xe>
    {
        /* Abort transfer. */
        HPDMA_BITBAND->Descriptor[inc].HPDMACR_DCP_CLR = HPDMA_ENABLE;
    }
    g_transfer.state = HPDMA_COMPLETED;
    8a02:	f240 138c 	movw	r3, #396	; 0x18c
    8a06:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8a0a:	f04f 0201 	mov.w	r2, #1
    8a0e:	701a      	strb	r2, [r3, #0]
}
    8a10:	f107 070c 	add.w	r7, r7, #12
    8a14:	46bd      	mov	sp, r7
    8a16:	bc80      	pop	{r7}
    8a18:	4770      	bx	lr
    8a1a:	bf00      	nop

00008a1c <MSS_HPDMA_get_transfer_status>:
hpdma_status_t
MSS_HPDMA_get_transfer_status
(
    void
)
{
    8a1c:	b480      	push	{r7}
    8a1e:	af00      	add	r7, sp, #0
    return g_transfer.state;
    8a20:	f240 138c 	movw	r3, #396	; 0x18c
    8a24:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8a28:	781b      	ldrb	r3, [r3, #0]
    8a2a:	b2db      	uxtb	r3, r3
}
    8a2c:	4618      	mov	r0, r3
    8a2e:	46bd      	mov	sp, r7
    8a30:	bc80      	pop	{r7}
    8a32:	4770      	bx	lr

00008a34 <MSS_HPDMA_set_handler>:
 */
void MSS_HPDMA_set_handler
(
    mss_hpdma_handler_t handler
)
{
    8a34:	b480      	push	{r7}
    8a36:	b083      	sub	sp, #12
    8a38:	af00      	add	r7, sp, #0
    8a3a:	6078      	str	r0, [r7, #4]
    if(handler == NULL_HANDLER)
    8a3c:	687b      	ldr	r3, [r7, #4]
    8a3e:	2b00      	cmp	r3, #0
    8a40:	d107      	bne.n	8a52 <MSS_HPDMA_set_handler+0x1e>
    {
        g_transfer.completion_handler = NULL_HANDLER;
    8a42:	f240 138c 	movw	r3, #396	; 0x18c
    8a46:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8a4a:	f04f 0200 	mov.w	r2, #0
    8a4e:	605a      	str	r2, [r3, #4]
    8a50:	e005      	b.n	8a5e <MSS_HPDMA_set_handler+0x2a>
    }
    else
    {
        g_transfer.completion_handler = handler;
    8a52:	f240 138c 	movw	r3, #396	; 0x18c
    8a56:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8a5a:	687a      	ldr	r2, [r7, #4]
    8a5c:	605a      	str	r2, [r3, #4]
    }
}
    8a5e:	f107 070c 	add.w	r7, r7, #12
    8a62:	46bd      	mov	sp, r7
    8a64:	bc80      	pop	{r7}
    8a66:	4770      	bx	lr

00008a68 <HPDMA_Complete_IRQHandler>:
#if defined(__GNUC__)
__attribute__((__interrupt__)) void HPDMA_Complete_IRQHandler(void)
#else
void HPDMA_Complete_IRQHandler(void)
#endif 
{
    8a68:	4668      	mov	r0, sp
    8a6a:	f020 0107 	bic.w	r1, r0, #7
    8a6e:	468d      	mov	sp, r1
    8a70:	b589      	push	{r0, r3, r7, lr}
    8a72:	af00      	add	r7, sp, #0
    /* Clear interrupt */
    HPDMA_BITBAND->HPDMAICR_CLR_XFR_INT[g_hpdma_current_desc] = HPDMA_ENABLE;
    8a74:	f240 0300 	movw	r3, #0
    8a78:	f2c4 2328 	movt	r3, #16936	; 0x4228
    8a7c:	f240 12a8 	movw	r2, #424	; 0x1a8
    8a80:	f2c2 0200 	movt	r2, #8192	; 0x2000
    8a84:	6812      	ldr	r2, [r2, #0]
    8a86:	f502 7228 	add.w	r2, r2, #672	; 0x2a0
    8a8a:	f04f 0101 	mov.w	r1, #1
    8a8e:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
    /* Disable interrupts */
    HPDMA->Descriptor[g_hpdma_current_desc].HPDMACR_REG &= ~HPDMACR_ALL_IRQ_ENABLE_MASK;
    8a92:	f244 0200 	movw	r2, #16384	; 0x4000
    8a96:	f2c4 0201 	movt	r2, #16385	; 0x4001
    8a9a:	f240 13a8 	movw	r3, #424	; 0x1a8
    8a9e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8aa2:	6818      	ldr	r0, [r3, #0]
    8aa4:	f244 0100 	movw	r1, #16384	; 0x4000
    8aa8:	f2c4 0101 	movt	r1, #16385	; 0x4001
    8aac:	f240 13a8 	movw	r3, #424	; 0x1a8
    8ab0:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8ab4:	f8d3 c000 	ldr.w	ip, [r3]
    8ab8:	4663      	mov	r3, ip
    8aba:	ea4f 0383 	mov.w	r3, r3, lsl #2
    8abe:	4463      	add	r3, ip
    8ac0:	ea4f 0383 	mov.w	r3, r3, lsl #2
    8ac4:	440b      	add	r3, r1
    8ac6:	f103 030c 	add.w	r3, r3, #12
    8aca:	681b      	ldr	r3, [r3, #0]
    8acc:	f423 01e0 	bic.w	r1, r3, #7340032	; 0x700000
    8ad0:	4603      	mov	r3, r0
    8ad2:	ea4f 0383 	mov.w	r3, r3, lsl #2
    8ad6:	4403      	add	r3, r0
    8ad8:	ea4f 0383 	mov.w	r3, r3, lsl #2
    8adc:	4413      	add	r3, r2
    8ade:	f103 030c 	add.w	r3, r3, #12
    8ae2:	6019      	str	r1, [r3, #0]
    
    ++g_hpdma_current_desc;
    8ae4:	f240 13a8 	movw	r3, #424	; 0x1a8
    8ae8:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8aec:	681b      	ldr	r3, [r3, #0]
    8aee:	f103 0201 	add.w	r2, r3, #1
    8af2:	f240 13a8 	movw	r3, #424	; 0x1a8
    8af6:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8afa:	601a      	str	r2, [r3, #0]
    
    if(NO_OF_HPDMA_DESCRIPTORS == g_hpdma_current_desc)
    8afc:	f240 13a8 	movw	r3, #424	; 0x1a8
    8b00:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8b04:	681b      	ldr	r3, [r3, #0]
    8b06:	2b04      	cmp	r3, #4
    8b08:	d106      	bne.n	8b18 <HPDMA_Complete_IRQHandler+0xb0>
    {
        g_hpdma_current_desc = 0u;
    8b0a:	f240 13a8 	movw	r3, #424	; 0x1a8
    8b0e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8b12:	f04f 0200 	mov.w	r2, #0
    8b16:	601a      	str	r2, [r3, #0]
    } 
    
    if(g_transfer.xfr_size > 0u)
    8b18:	f240 138c 	movw	r3, #396	; 0x18c
    8b1c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8b20:	691b      	ldr	r3, [r3, #16]
    8b22:	2b00      	cmp	r3, #0
    8b24:	d031      	beq.n	8b8a <HPDMA_Complete_IRQHandler+0x122>
    {
        if(NO_OF_HPDMA_DESCRIPTORS == g_hpdma_end_desc)
    8b26:	f240 13a4 	movw	r3, #420	; 0x1a4
    8b2a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8b2e:	681b      	ldr	r3, [r3, #0]
    8b30:	2b04      	cmp	r3, #4
    8b32:	d107      	bne.n	8b44 <HPDMA_Complete_IRQHandler+0xdc>
        {
            g_hpdma_end_desc = 0u;
    8b34:	f240 13a4 	movw	r3, #420	; 0x1a4
    8b38:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8b3c:	f04f 0200 	mov.w	r2, #0
    8b40:	601a      	str	r2, [r3, #0]
    8b42:	e00b      	b.n	8b5c <HPDMA_Complete_IRQHandler+0xf4>
        }
        else
        {
            ++g_hpdma_end_desc;
    8b44:	f240 13a4 	movw	r3, #420	; 0x1a4
    8b48:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8b4c:	681b      	ldr	r3, [r3, #0]
    8b4e:	f103 0201 	add.w	r2, r3, #1
    8b52:	f240 13a4 	movw	r3, #420	; 0x1a4
    8b56:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8b5a:	601a      	str	r2, [r3, #0]
        }
        start_transfer(g_transfer.src_addr,
    8b5c:	f240 138c 	movw	r3, #396	; 0x18c
    8b60:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8b64:	6898      	ldr	r0, [r3, #8]
    8b66:	f240 138c 	movw	r3, #396	; 0x18c
    8b6a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8b6e:	68d9      	ldr	r1, [r3, #12]
    8b70:	f240 138c 	movw	r3, #396	; 0x18c
    8b74:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8b78:	691a      	ldr	r2, [r3, #16]
    8b7a:	f240 138c 	movw	r3, #396	; 0x18c
    8b7e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8b82:	7d1b      	ldrb	r3, [r3, #20]
    8b84:	f7ff fdd4 	bl	8730 <start_transfer>
    8b88:	e03a      	b.n	8c00 <HPDMA_Complete_IRQHandler+0x198>
                        g_transfer.xfr_size,
                        g_transfer.xfr_dir);
    }
    else
    {
        if(((HPDMA->Descriptor[g_hpdma_current_desc].HPDMACR_REG) & HPDMACR_ALL_IRQ_ENABLE_MASK) == 0u)  
    8b8a:	f244 0200 	movw	r2, #16384	; 0x4000
    8b8e:	f2c4 0201 	movt	r2, #16385	; 0x4001
    8b92:	f240 13a8 	movw	r3, #424	; 0x1a8
    8b96:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8b9a:	6819      	ldr	r1, [r3, #0]
    8b9c:	460b      	mov	r3, r1
    8b9e:	ea4f 0383 	mov.w	r3, r3, lsl #2
    8ba2:	440b      	add	r3, r1
    8ba4:	ea4f 0383 	mov.w	r3, r3, lsl #2
    8ba8:	4413      	add	r3, r2
    8baa:	f103 030c 	add.w	r3, r3, #12
    8bae:	681b      	ldr	r3, [r3, #0]
    8bb0:	f403 03e0 	and.w	r3, r3, #7340032	; 0x700000
    8bb4:	2b00      	cmp	r3, #0
    8bb6:	d123      	bne.n	8c00 <HPDMA_Complete_IRQHandler+0x198>
        {
            g_hpdma_current_desc = 0u;
    8bb8:	f240 13a8 	movw	r3, #424	; 0x1a8
    8bbc:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8bc0:	f04f 0200 	mov.w	r2, #0
    8bc4:	601a      	str	r2, [r3, #0]
            g_hpdma_end_desc = 0u;
    8bc6:	f240 13a4 	movw	r3, #420	; 0x1a4
    8bca:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8bce:	f04f 0200 	mov.w	r2, #0
    8bd2:	601a      	str	r2, [r3, #0]
        
            g_transfer.state = HPDMA_COMPLETED;
    8bd4:	f240 138c 	movw	r3, #396	; 0x18c
    8bd8:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8bdc:	f04f 0201 	mov.w	r2, #1
    8be0:	701a      	strb	r2, [r3, #0]
            if(g_transfer.completion_handler != NULL_HANDLER)
    8be2:	f240 138c 	movw	r3, #396	; 0x18c
    8be6:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8bea:	685b      	ldr	r3, [r3, #4]
    8bec:	2b00      	cmp	r3, #0
    8bee:	d007      	beq.n	8c00 <HPDMA_Complete_IRQHandler+0x198>
            {
                (*(g_transfer.completion_handler))(HPDMA_COMPLETED);
    8bf0:	f240 138c 	movw	r3, #396	; 0x18c
    8bf4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8bf8:	685b      	ldr	r3, [r3, #4]
    8bfa:	f04f 0001 	mov.w	r0, #1
    8bfe:	4798      	blx	r3
            }  
        }
    }
}
    8c00:	46bd      	mov	sp, r7
    8c02:	e8bd 4089 	ldmia.w	sp!, {r0, r3, r7, lr}
    8c06:	4685      	mov	sp, r0
    8c08:	4770      	bx	lr
    8c0a:	bf00      	nop

00008c0c <HPDMA_Error_IRQHandler>:
#if defined(__GNUC__)
__attribute__((__interrupt__)) void HPDMA_Error_IRQHandler(void)
#else
void HPDMA_Error_IRQHandler(void)
#endif 
{
    8c0c:	4668      	mov	r0, sp
    8c0e:	f020 0107 	bic.w	r1, r0, #7
    8c12:	468d      	mov	sp, r1
    8c14:	b581      	push	{r0, r7, lr}
    8c16:	b083      	sub	sp, #12
    8c18:	af00      	add	r7, sp, #0
    uint32_t inc;

    /*
     * Handle source/destination errors.
     */
    error_bits = HPDMA->HPDMAEDR_REG;
    8c1a:	f244 0300 	movw	r3, #16384	; 0x4000
    8c1e:	f2c4 0301 	movt	r3, #16385	; 0x4001
    8c22:	681b      	ldr	r3, [r3, #0]
    8c24:	603b      	str	r3, [r7, #0]
    error_bits = error_bits & HPDMAEDR_DCP_ERR_MASK;
    8c26:	683b      	ldr	r3, [r7, #0]
    8c28:	f403 6370 	and.w	r3, r3, #3840	; 0xf00
    8c2c:	603b      	str	r3, [r7, #0]
    
    if(error_bits != 0u)
    8c2e:	683b      	ldr	r3, [r7, #0]
    8c30:	2b00      	cmp	r3, #0
    8c32:	d055      	beq.n	8ce0 <HPDMA_Error_IRQHandler+0xd4>
    {
        if(HPDMA_BITBAND->Descriptor[g_hpdma_current_desc].HPDMASR_DCP_SERR != 0u)
    8c34:	f240 0200 	movw	r2, #0
    8c38:	f2c4 2228 	movt	r2, #16936	; 0x4228
    8c3c:	f240 13a8 	movw	r3, #424	; 0x1a8
    8c40:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8c44:	6819      	ldr	r1, [r3, #0]
    8c46:	460b      	mov	r3, r1
    8c48:	ea4f 0383 	mov.w	r3, r3, lsl #2
    8c4c:	440b      	add	r3, r1
    8c4e:	ea4f 13c3 	mov.w	r3, r3, lsl #7
    8c52:	4413      	add	r3, r2
    8c54:	f503 7302 	add.w	r3, r3, #520	; 0x208
    8c58:	681b      	ldr	r3, [r3, #0]
    8c5a:	2b00      	cmp	r3, #0
    8c5c:	d015      	beq.n	8c8a <HPDMA_Error_IRQHandler+0x7e>
        {
            g_transfer.state = HPDMA_SOURCE_ERROR;
    8c5e:	f240 138c 	movw	r3, #396	; 0x18c
    8c62:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8c66:	f04f 0202 	mov.w	r2, #2
    8c6a:	701a      	strb	r2, [r3, #0]
            if(g_transfer.completion_handler != NULL_HANDLER)
    8c6c:	f240 138c 	movw	r3, #396	; 0x18c
    8c70:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8c74:	685b      	ldr	r3, [r3, #4]
    8c76:	2b00      	cmp	r3, #0
    8c78:	d007      	beq.n	8c8a <HPDMA_Error_IRQHandler+0x7e>
            {                        
                (*(g_transfer.completion_handler))(HPDMA_SOURCE_ERROR);
    8c7a:	f240 138c 	movw	r3, #396	; 0x18c
    8c7e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8c82:	685b      	ldr	r3, [r3, #4]
    8c84:	f04f 0002 	mov.w	r0, #2
    8c88:	4798      	blx	r3
            }
        }
        
        if(HPDMA_BITBAND->Descriptor[g_hpdma_current_desc].HPDMASR_DCP_DERR != 0u)
    8c8a:	f240 0200 	movw	r2, #0
    8c8e:	f2c4 2228 	movt	r2, #16936	; 0x4228
    8c92:	f240 13a8 	movw	r3, #424	; 0x1a8
    8c96:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8c9a:	6819      	ldr	r1, [r3, #0]
    8c9c:	460b      	mov	r3, r1
    8c9e:	ea4f 0383 	mov.w	r3, r3, lsl #2
    8ca2:	440b      	add	r3, r1
    8ca4:	ea4f 13c3 	mov.w	r3, r3, lsl #7
    8ca8:	4413      	add	r3, r2
    8caa:	f503 7303 	add.w	r3, r3, #524	; 0x20c
    8cae:	681b      	ldr	r3, [r3, #0]
    8cb0:	2b00      	cmp	r3, #0
    8cb2:	d015      	beq.n	8ce0 <HPDMA_Error_IRQHandler+0xd4>
        {
            g_transfer.state = HPDMA_DESTINATION_ERROR;
    8cb4:	f240 138c 	movw	r3, #396	; 0x18c
    8cb8:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8cbc:	f04f 0203 	mov.w	r2, #3
    8cc0:	701a      	strb	r2, [r3, #0]
            if(g_transfer.completion_handler != NULL_HANDLER)
    8cc2:	f240 138c 	movw	r3, #396	; 0x18c
    8cc6:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8cca:	685b      	ldr	r3, [r3, #4]
    8ccc:	2b00      	cmp	r3, #0
    8cce:	d007      	beq.n	8ce0 <HPDMA_Error_IRQHandler+0xd4>
            {                        
                (*(g_transfer.completion_handler))(HPDMA_DESTINATION_ERROR);
    8cd0:	f240 138c 	movw	r3, #396	; 0x18c
    8cd4:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8cd8:	685b      	ldr	r3, [r3, #4]
    8cda:	f04f 0003 	mov.w	r0, #3
    8cde:	4798      	blx	r3
    }
    
    /*
     * Handle non word aligned errors.
     */
    error_bits = HPDMA->HPDMAEDR_REG;
    8ce0:	f244 0300 	movw	r3, #16384	; 0x4000
    8ce4:	f2c4 0301 	movt	r3, #16385	; 0x4001
    8ce8:	681b      	ldr	r3, [r3, #0]
    8cea:	603b      	str	r3, [r7, #0]
    error_bits = error_bits & HPDMAEDR_NON_WORD_ERR_MASK;
    8cec:	683b      	ldr	r3, [r7, #0]
    8cee:	f403 4370 	and.w	r3, r3, #61440	; 0xf000
    8cf2:	603b      	str	r3, [r7, #0]
    
    if(error_bits != 0u)
    8cf4:	683b      	ldr	r3, [r7, #0]
    8cf6:	2b00      	cmp	r3, #0
    8cf8:	d015      	beq.n	8d26 <HPDMA_Error_IRQHandler+0x11a>
    {
        g_transfer.state = HPDMA_WORD_ALIGN_ERROR;
    8cfa:	f240 138c 	movw	r3, #396	; 0x18c
    8cfe:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8d02:	f04f 0204 	mov.w	r2, #4
    8d06:	701a      	strb	r2, [r3, #0]
        /* Call handler. */
        if(g_transfer.completion_handler != NULL_HANDLER)
    8d08:	f240 138c 	movw	r3, #396	; 0x18c
    8d0c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8d10:	685b      	ldr	r3, [r3, #4]
    8d12:	2b00      	cmp	r3, #0
    8d14:	d007      	beq.n	8d26 <HPDMA_Error_IRQHandler+0x11a>
        {
            (*(g_transfer.completion_handler))(HPDMA_WORD_ALIGN_ERROR);
    8d16:	f240 138c 	movw	r3, #396	; 0x18c
    8d1a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    8d1e:	685b      	ldr	r3, [r3, #4]
    8d20:	f04f 0004 	mov.w	r0, #4
    8d24:	4798      	blx	r3
        }
    }
    
    for(inc = 0u; inc < NO_OF_HPDMA_DESCRIPTORS; inc++)
    8d26:	f04f 0300 	mov.w	r3, #0
    8d2a:	607b      	str	r3, [r7, #4]
    8d2c:	e01f      	b.n	8d6e <HPDMA_Error_IRQHandler+0x162>
    {
        /* Abort transfer. */
        HPDMA_BITBAND->Descriptor[inc].HPDMACR_DCP_CLR = HPDMA_ENABLE;
    8d2e:	f240 0200 	movw	r2, #0
    8d32:	f2c4 2228 	movt	r2, #16936	; 0x4228
    8d36:	6879      	ldr	r1, [r7, #4]
    8d38:	460b      	mov	r3, r1
    8d3a:	ea4f 0383 	mov.w	r3, r3, lsl #2
    8d3e:	440b      	add	r3, r1
    8d40:	ea4f 13c3 	mov.w	r3, r3, lsl #7
    8d44:	4413      	add	r3, r2
    8d46:	f503 73e4 	add.w	r3, r3, #456	; 0x1c8
    8d4a:	f04f 0201 	mov.w	r2, #1
    8d4e:	601a      	str	r2, [r3, #0]
        /* Clear interrupt. */
        HPDMA_BITBAND->HPDMAICR_CLR_XFR_INT[inc] = HPDMA_ENABLE;
    8d50:	f240 0300 	movw	r3, #0
    8d54:	f2c4 2328 	movt	r3, #16936	; 0x4228
    8d58:	687a      	ldr	r2, [r7, #4]
    8d5a:	f502 7228 	add.w	r2, r2, #672	; 0x2a0
    8d5e:	f04f 0101 	mov.w	r1, #1
    8d62:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
        {
            (*(g_transfer.completion_handler))(HPDMA_WORD_ALIGN_ERROR);
        }
    }
    
    for(inc = 0u; inc < NO_OF_HPDMA_DESCRIPTORS; inc++)
    8d66:	687b      	ldr	r3, [r7, #4]
    8d68:	f103 0301 	add.w	r3, r3, #1
    8d6c:	607b      	str	r3, [r7, #4]
    8d6e:	687b      	ldr	r3, [r7, #4]
    8d70:	2b03      	cmp	r3, #3
    8d72:	d9dc      	bls.n	8d2e <HPDMA_Error_IRQHandler+0x122>
        /* Abort transfer. */
        HPDMA_BITBAND->Descriptor[inc].HPDMACR_DCP_CLR = HPDMA_ENABLE;
        /* Clear interrupt. */
        HPDMA_BITBAND->HPDMAICR_CLR_XFR_INT[inc] = HPDMA_ENABLE;
    }
}
    8d74:	f107 070c 	add.w	r7, r7, #12
    8d78:	46bd      	mov	sp, r7
    8d7a:	e8bd 4081 	ldmia.w	sp!, {r0, r7, lr}
    8d7e:	4685      	mov	sp, r0
    8d80:	4770      	bx	lr
    8d82:	bf00      	nop

00008d84 <NVIC_EnableIRQ>:
    The function enables a device-specific interrupt in the NVIC interrupt controller.

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
    8d84:	b480      	push	{r7}
    8d86:	b083      	sub	sp, #12
    8d88:	af00      	add	r7, sp, #0
    8d8a:	4603      	mov	r3, r0
    8d8c:	71fb      	strb	r3, [r7, #7]
  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
    8d8e:	f24e 1300 	movw	r3, #57600	; 0xe100
    8d92:	f2ce 0300 	movt	r3, #57344	; 0xe000
    8d96:	f997 2007 	ldrsb.w	r2, [r7, #7]
    8d9a:	ea4f 1252 	mov.w	r2, r2, lsr #5
    8d9e:	79f9      	ldrb	r1, [r7, #7]
    8da0:	f001 011f 	and.w	r1, r1, #31
    8da4:	f04f 0001 	mov.w	r0, #1
    8da8:	fa00 f101 	lsl.w	r1, r0, r1
    8dac:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
}
    8db0:	f107 070c 	add.w	r7, r7, #12
    8db4:	46bd      	mov	sp, r7
    8db6:	bc80      	pop	{r7}
    8db8:	4770      	bx	lr
    8dba:	bf00      	nop

00008dbc <NVIC_DisableIRQ>:
    The function disables a device-specific interrupt in the NVIC interrupt controller.

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
    8dbc:	b480      	push	{r7}
    8dbe:	b083      	sub	sp, #12
    8dc0:	af00      	add	r7, sp, #0
    8dc2:	4603      	mov	r3, r0
    8dc4:	71fb      	strb	r3, [r7, #7]
  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
    8dc6:	f24e 1300 	movw	r3, #57600	; 0xe100
    8dca:	f2ce 0300 	movt	r3, #57344	; 0xe000
    8dce:	f997 2007 	ldrsb.w	r2, [r7, #7]
    8dd2:	ea4f 1252 	mov.w	r2, r2, lsr #5
    8dd6:	79f9      	ldrb	r1, [r7, #7]
    8dd8:	f001 011f 	and.w	r1, r1, #31
    8ddc:	f04f 0001 	mov.w	r0, #1
    8de0:	fa00 f101 	lsl.w	r1, r0, r1
    8de4:	f102 0220 	add.w	r2, r2, #32
    8de8:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
}
    8dec:	f107 070c 	add.w	r7, r7, #12
    8df0:	46bd      	mov	sp, r7
    8df2:	bc80      	pop	{r7}
    8df4:	4770      	bx	lr
    8df6:	bf00      	nop

00008df8 <NVIC_ClearPendingIRQ>:
    The function clears the pending bit of an external interrupt.

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
    8df8:	b480      	push	{r7}
    8dfa:	b083      	sub	sp, #12
    8dfc:	af00      	add	r7, sp, #0
    8dfe:	4603      	mov	r3, r0
    8e00:	71fb      	strb	r3, [r7, #7]
  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
    8e02:	f24e 1300 	movw	r3, #57600	; 0xe100
    8e06:	f2ce 0300 	movt	r3, #57344	; 0xe000
    8e0a:	f997 2007 	ldrsb.w	r2, [r7, #7]
    8e0e:	ea4f 1252 	mov.w	r2, r2, lsr #5
    8e12:	79f9      	ldrb	r1, [r7, #7]
    8e14:	f001 011f 	and.w	r1, r1, #31
    8e18:	f04f 0001 	mov.w	r0, #1
    8e1c:	fa00 f101 	lsl.w	r1, r0, r1
    8e20:	f102 0260 	add.w	r2, r2, #96	; 0x60
    8e24:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
}
    8e28:	f107 070c 	add.w	r7, r7, #12
    8e2c:	46bd      	mov	sp, r7
    8e2e:	bc80      	pop	{r7}
    8e30:	4770      	bx	lr
    8e32:	bf00      	nop

00008e34 <MSS_GPIO_init>:
/*-------------------------------------------------------------------------*//**
 * MSS_GPIO_init
 * See "mss_gpio.h" for details of how to use this function.
 */
void MSS_GPIO_init( void )
{
    8e34:	b580      	push	{r7, lr}
    8e36:	b082      	sub	sp, #8
    8e38:	af00      	add	r7, sp, #0
    uint32_t inc;
    
    /* reset MSS GPIO hardware */
    SYSREG->SOFT_RST_CR |= SYSREG_GPIO_SOFTRESET_MASK;
    8e3a:	f248 0300 	movw	r3, #32768	; 0x8000
    8e3e:	f2c4 0303 	movt	r3, #16387	; 0x4003
    8e42:	f248 0200 	movw	r2, #32768	; 0x8000
    8e46:	f2c4 0203 	movt	r2, #16387	; 0x4003
    8e4a:	6c92      	ldr	r2, [r2, #72]	; 0x48
    8e4c:	f442 1280 	orr.w	r2, r2, #1048576	; 0x100000
    8e50:	649a      	str	r2, [r3, #72]	; 0x48
    SYSREG->SOFT_RST_CR |= (SYSREG_GPIO_7_0_SOFTRESET_MASK |
    8e52:	f248 0300 	movw	r3, #32768	; 0x8000
    8e56:	f2c4 0303 	movt	r3, #16387	; 0x4003
    8e5a:	f248 0200 	movw	r2, #32768	; 0x8000
    8e5e:	f2c4 0203 	movt	r2, #16387	; 0x4003
    8e62:	6c92      	ldr	r2, [r2, #72]	; 0x48
    8e64:	f042 72f0 	orr.w	r2, r2, #31457280	; 0x1e00000
    8e68:	649a      	str	r2, [r3, #72]	; 0x48
                            SYSREG_GPIO_15_8_SOFTRESET_MASK |
                            SYSREG_GPIO_23_16_SOFTRESET_MASK |
                            SYSREG_GPIO_31_24_SOFTRESET_MASK);
                            
    /* Clear any previously pended MSS GPIO interrupt */
    for(inc = 0U; inc < NB_OF_GPIO; ++inc)
    8e6a:	f04f 0300 	mov.w	r3, #0
    8e6e:	607b      	str	r3, [r7, #4]
    8e70:	e017      	b.n	8ea2 <MSS_GPIO_init+0x6e>
    {
        NVIC_DisableIRQ(g_gpio_irqn_lut[inc]);
    8e72:	687a      	ldr	r2, [r7, #4]
    8e74:	f649 7318 	movw	r3, #40728	; 0x9f18
    8e78:	f2c0 0300 	movt	r3, #0
    8e7c:	5c9b      	ldrb	r3, [r3, r2]
    8e7e:	b25b      	sxtb	r3, r3
    8e80:	4618      	mov	r0, r3
    8e82:	f7ff ff9b 	bl	8dbc <NVIC_DisableIRQ>
        NVIC_ClearPendingIRQ(g_gpio_irqn_lut[inc]);
    8e86:	687a      	ldr	r2, [r7, #4]
    8e88:	f649 7318 	movw	r3, #40728	; 0x9f18
    8e8c:	f2c0 0300 	movt	r3, #0
    8e90:	5c9b      	ldrb	r3, [r3, r2]
    8e92:	b25b      	sxtb	r3, r3
    8e94:	4618      	mov	r0, r3
    8e96:	f7ff ffaf 	bl	8df8 <NVIC_ClearPendingIRQ>
                            SYSREG_GPIO_15_8_SOFTRESET_MASK |
                            SYSREG_GPIO_23_16_SOFTRESET_MASK |
                            SYSREG_GPIO_31_24_SOFTRESET_MASK);
                            
    /* Clear any previously pended MSS GPIO interrupt */
    for(inc = 0U; inc < NB_OF_GPIO; ++inc)
    8e9a:	687b      	ldr	r3, [r7, #4]
    8e9c:	f103 0301 	add.w	r3, r3, #1
    8ea0:	607b      	str	r3, [r7, #4]
    8ea2:	687b      	ldr	r3, [r7, #4]
    8ea4:	2b1f      	cmp	r3, #31
    8ea6:	d9e4      	bls.n	8e72 <MSS_GPIO_init+0x3e>
    {
        NVIC_DisableIRQ(g_gpio_irqn_lut[inc]);
        NVIC_ClearPendingIRQ(g_gpio_irqn_lut[inc]);
    }
    /* Take MSS GPIO hardware out of reset. */
    SYSREG->SOFT_RST_CR &= ~(SYSREG_GPIO_7_0_SOFTRESET_MASK |
    8ea8:	f248 0300 	movw	r3, #32768	; 0x8000
    8eac:	f2c4 0303 	movt	r3, #16387	; 0x4003
    8eb0:	f248 0200 	movw	r2, #32768	; 0x8000
    8eb4:	f2c4 0203 	movt	r2, #16387	; 0x4003
    8eb8:	6c92      	ldr	r2, [r2, #72]	; 0x48
    8eba:	f022 72f0 	bic.w	r2, r2, #31457280	; 0x1e00000
    8ebe:	649a      	str	r2, [r3, #72]	; 0x48
                             SYSREG_GPIO_15_8_SOFTRESET_MASK |
                             SYSREG_GPIO_23_16_SOFTRESET_MASK |
                             SYSREG_GPIO_31_24_SOFTRESET_MASK);
    SYSREG->SOFT_RST_CR &= ~SYSREG_GPIO_SOFTRESET_MASK;
    8ec0:	f248 0300 	movw	r3, #32768	; 0x8000
    8ec4:	f2c4 0303 	movt	r3, #16387	; 0x4003
    8ec8:	f248 0200 	movw	r2, #32768	; 0x8000
    8ecc:	f2c4 0203 	movt	r2, #16387	; 0x4003
    8ed0:	6c92      	ldr	r2, [r2, #72]	; 0x48
    8ed2:	f422 1280 	bic.w	r2, r2, #1048576	; 0x100000
    8ed6:	649a      	str	r2, [r3, #72]	; 0x48
}
    8ed8:	f107 0708 	add.w	r7, r7, #8
    8edc:	46bd      	mov	sp, r7
    8ede:	bd80      	pop	{r7, pc}

00008ee0 <MSS_GPIO_config>:
void MSS_GPIO_config
(
    mss_gpio_id_t port_id,
    uint32_t config
)
{
    8ee0:	b480      	push	{r7}
    8ee2:	b085      	sub	sp, #20
    8ee4:	af00      	add	r7, sp, #0
    8ee6:	4603      	mov	r3, r0
    8ee8:	6039      	str	r1, [r7, #0]
    8eea:	71fb      	strb	r3, [r7, #7]
    uint32_t gpio_idx = (uint32_t)port_id;
    8eec:	79fb      	ldrb	r3, [r7, #7]
    8eee:	60fb      	str	r3, [r7, #12]
    
    ASSERT(gpio_idx < NB_OF_GPIO);
    8ef0:	68fb      	ldr	r3, [r7, #12]
    8ef2:	2b1f      	cmp	r3, #31
    8ef4:	d900      	bls.n	8ef8 <MSS_GPIO_config+0x18>
    8ef6:	be00      	bkpt	0x0000

    if(gpio_idx < NB_OF_GPIO)
    8ef8:	68fb      	ldr	r3, [r7, #12]
    8efa:	2b1f      	cmp	r3, #31
    8efc:	d808      	bhi.n	8f10 <MSS_GPIO_config+0x30>
    {
        *(g_config_reg_lut[gpio_idx]) = config;
    8efe:	68fa      	ldr	r2, [r7, #12]
    8f00:	f649 6398 	movw	r3, #40600	; 0x9e98
    8f04:	f2c0 0300 	movt	r3, #0
    8f08:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
    8f0c:	683a      	ldr	r2, [r7, #0]
    8f0e:	601a      	str	r2, [r3, #0]
    }
}
    8f10:	f107 0714 	add.w	r7, r7, #20
    8f14:	46bd      	mov	sp, r7
    8f16:	bc80      	pop	{r7}
    8f18:	4770      	bx	lr
    8f1a:	bf00      	nop

00008f1c <MSS_GPIO_set_output>:
void MSS_GPIO_set_output
(
    mss_gpio_id_t port_id,
    uint8_t value
)
{
    8f1c:	b480      	push	{r7}
    8f1e:	b085      	sub	sp, #20
    8f20:	af00      	add	r7, sp, #0
    8f22:	4602      	mov	r2, r0
    8f24:	460b      	mov	r3, r1
    8f26:	71fa      	strb	r2, [r7, #7]
    8f28:	71bb      	strb	r3, [r7, #6]
    uint32_t gpio_setting;
    uint32_t gpio_idx = (uint32_t)port_id;
    8f2a:	79fb      	ldrb	r3, [r7, #7]
    8f2c:	60fb      	str	r3, [r7, #12]
    
    ASSERT(gpio_idx < NB_OF_GPIO);
    8f2e:	68fb      	ldr	r3, [r7, #12]
    8f30:	2b1f      	cmp	r3, #31
    8f32:	d900      	bls.n	8f36 <MSS_GPIO_set_output+0x1a>
    8f34:	be00      	bkpt	0x0000
    
    if(gpio_idx < NB_OF_GPIO)
    8f36:	68fb      	ldr	r3, [r7, #12]
    8f38:	2b1f      	cmp	r3, #31
    8f3a:	d822      	bhi.n	8f82 <MSS_GPIO_set_output+0x66>
    {
        gpio_setting = GPIO->GPIO_OUT;
    8f3c:	f243 0300 	movw	r3, #12288	; 0x3000
    8f40:	f2c4 0301 	movt	r3, #16385	; 0x4001
    8f44:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
    8f48:	60bb      	str	r3, [r7, #8]
        gpio_setting &= ~((uint32_t)0x01u << gpio_idx);
    8f4a:	68fb      	ldr	r3, [r7, #12]
    8f4c:	f04f 0201 	mov.w	r2, #1
    8f50:	fa02 f303 	lsl.w	r3, r2, r3
    8f54:	ea6f 0303 	mvn.w	r3, r3
    8f58:	68ba      	ldr	r2, [r7, #8]
    8f5a:	ea02 0303 	and.w	r3, r2, r3
    8f5e:	60bb      	str	r3, [r7, #8]
        gpio_setting |= ((uint32_t)value & 0x01u) << gpio_idx;
    8f60:	79bb      	ldrb	r3, [r7, #6]
    8f62:	f003 0201 	and.w	r2, r3, #1
    8f66:	68fb      	ldr	r3, [r7, #12]
    8f68:	fa02 f303 	lsl.w	r3, r2, r3
    8f6c:	68ba      	ldr	r2, [r7, #8]
    8f6e:	ea42 0303 	orr.w	r3, r2, r3
    8f72:	60bb      	str	r3, [r7, #8]
        GPIO->GPIO_OUT = gpio_setting;
    8f74:	f243 0300 	movw	r3, #12288	; 0x3000
    8f78:	f2c4 0301 	movt	r3, #16385	; 0x4001
    8f7c:	68ba      	ldr	r2, [r7, #8]
    8f7e:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
    }
}
    8f82:	f107 0714 	add.w	r7, r7, #20
    8f86:	46bd      	mov	sp, r7
    8f88:	bc80      	pop	{r7}
    8f8a:	4770      	bx	lr

00008f8c <MSS_GPIO_drive_inout>:
void MSS_GPIO_drive_inout
(
    mss_gpio_id_t port_id,
    mss_gpio_inout_state_t inout_state
)
{
    8f8c:	b480      	push	{r7}
    8f8e:	b087      	sub	sp, #28
    8f90:	af00      	add	r7, sp, #0
    8f92:	4602      	mov	r2, r0
    8f94:	460b      	mov	r3, r1
    8f96:	71fa      	strb	r2, [r7, #7]
    8f98:	71bb      	strb	r3, [r7, #6]
    uint32_t outputs_state;
    uint32_t config;
    uint32_t gpio_idx = (uint32_t)port_id;
    8f9a:	79fb      	ldrb	r3, [r7, #7]
    8f9c:	617b      	str	r3, [r7, #20]
    
    ASSERT(gpio_idx < NB_OF_GPIO);
    8f9e:	697b      	ldr	r3, [r7, #20]
    8fa0:	2b1f      	cmp	r3, #31
    8fa2:	d900      	bls.n	8fa6 <MSS_GPIO_drive_inout+0x1a>
    8fa4:	be00      	bkpt	0x0000
    
    if(gpio_idx < NB_OF_GPIO)
    8fa6:	697b      	ldr	r3, [r7, #20]
    8fa8:	2b1f      	cmp	r3, #31
    8faa:	d87d      	bhi.n	90a8 <MSS_GPIO_drive_inout+0x11c>
    {
        switch(inout_state)
    8fac:	79bb      	ldrb	r3, [r7, #6]
    8fae:	2b01      	cmp	r3, #1
    8fb0:	d004      	beq.n	8fbc <MSS_GPIO_drive_inout+0x30>
    8fb2:	2b02      	cmp	r3, #2
    8fb4:	d060      	beq.n	9078 <MSS_GPIO_drive_inout+0xec>
    8fb6:	2b00      	cmp	r3, #0
    8fb8:	d02e      	beq.n	9018 <MSS_GPIO_drive_inout+0x8c>
    8fba:	e074      	b.n	90a6 <MSS_GPIO_drive_inout+0x11a>
        {
            case MSS_GPIO_DRIVE_HIGH:
                /* Set output high */
                outputs_state = GPIO->GPIO_OUT;
    8fbc:	f243 0300 	movw	r3, #12288	; 0x3000
    8fc0:	f2c4 0301 	movt	r3, #16385	; 0x4001
    8fc4:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
    8fc8:	60fb      	str	r3, [r7, #12]
                outputs_state |= (uint32_t)1 << gpio_idx;
    8fca:	697b      	ldr	r3, [r7, #20]
    8fcc:	f04f 0201 	mov.w	r2, #1
    8fd0:	fa02 f303 	lsl.w	r3, r2, r3
    8fd4:	68fa      	ldr	r2, [r7, #12]
    8fd6:	ea42 0303 	orr.w	r3, r2, r3
    8fda:	60fb      	str	r3, [r7, #12]
                GPIO->GPIO_OUT = outputs_state;
    8fdc:	f243 0300 	movw	r3, #12288	; 0x3000
    8fe0:	f2c4 0301 	movt	r3, #16385	; 0x4001
    8fe4:	68fa      	ldr	r2, [r7, #12]
    8fe6:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
                /* Enable output buffer */
                config = *(g_config_reg_lut[gpio_idx]);
    8fea:	697a      	ldr	r2, [r7, #20]
    8fec:	f649 6398 	movw	r3, #40600	; 0x9e98
    8ff0:	f2c0 0300 	movt	r3, #0
    8ff4:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
    8ff8:	681b      	ldr	r3, [r3, #0]
    8ffa:	613b      	str	r3, [r7, #16]
                config |= OUTPUT_BUFFER_ENABLE_MASK;
    8ffc:	693b      	ldr	r3, [r7, #16]
    8ffe:	f043 0304 	orr.w	r3, r3, #4
    9002:	613b      	str	r3, [r7, #16]
                *(g_config_reg_lut[gpio_idx]) = config;
    9004:	697a      	ldr	r2, [r7, #20]
    9006:	f649 6398 	movw	r3, #40600	; 0x9e98
    900a:	f2c0 0300 	movt	r3, #0
    900e:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
    9012:	693a      	ldr	r2, [r7, #16]
    9014:	601a      	str	r2, [r3, #0]
            break;
    9016:	e047      	b.n	90a8 <MSS_GPIO_drive_inout+0x11c>
                
            case MSS_GPIO_DRIVE_LOW:
                /* Set output low */
                outputs_state = GPIO->GPIO_OUT;
    9018:	f243 0300 	movw	r3, #12288	; 0x3000
    901c:	f2c4 0301 	movt	r3, #16385	; 0x4001
    9020:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
    9024:	60fb      	str	r3, [r7, #12]
                outputs_state &= ~((uint32_t)((uint32_t)1 << gpio_idx));
    9026:	697b      	ldr	r3, [r7, #20]
    9028:	f04f 0201 	mov.w	r2, #1
    902c:	fa02 f303 	lsl.w	r3, r2, r3
    9030:	ea6f 0303 	mvn.w	r3, r3
    9034:	68fa      	ldr	r2, [r7, #12]
    9036:	ea02 0303 	and.w	r3, r2, r3
    903a:	60fb      	str	r3, [r7, #12]
                GPIO->GPIO_OUT = outputs_state;
    903c:	f243 0300 	movw	r3, #12288	; 0x3000
    9040:	f2c4 0301 	movt	r3, #16385	; 0x4001
    9044:	68fa      	ldr	r2, [r7, #12]
    9046:	f8c3 2088 	str.w	r2, [r3, #136]	; 0x88
                /* Enable output buffer */
                config = *(g_config_reg_lut[gpio_idx]);
    904a:	697a      	ldr	r2, [r7, #20]
    904c:	f649 6398 	movw	r3, #40600	; 0x9e98
    9050:	f2c0 0300 	movt	r3, #0
    9054:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
    9058:	681b      	ldr	r3, [r3, #0]
    905a:	613b      	str	r3, [r7, #16]
                config |= OUTPUT_BUFFER_ENABLE_MASK;
    905c:	693b      	ldr	r3, [r7, #16]
    905e:	f043 0304 	orr.w	r3, r3, #4
    9062:	613b      	str	r3, [r7, #16]
                *(g_config_reg_lut[gpio_idx]) = config;
    9064:	697a      	ldr	r2, [r7, #20]
    9066:	f649 6398 	movw	r3, #40600	; 0x9e98
    906a:	f2c0 0300 	movt	r3, #0
    906e:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
    9072:	693a      	ldr	r2, [r7, #16]
    9074:	601a      	str	r2, [r3, #0]
            break;
    9076:	e017      	b.n	90a8 <MSS_GPIO_drive_inout+0x11c>
                
            case MSS_GPIO_HIGH_Z:
                /* Disable output buffer */
                config = *(g_config_reg_lut[gpio_idx]);
    9078:	697a      	ldr	r2, [r7, #20]
    907a:	f649 6398 	movw	r3, #40600	; 0x9e98
    907e:	f2c0 0300 	movt	r3, #0
    9082:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
    9086:	681b      	ldr	r3, [r3, #0]
    9088:	613b      	str	r3, [r7, #16]
                config &= ~OUTPUT_BUFFER_ENABLE_MASK;
    908a:	693b      	ldr	r3, [r7, #16]
    908c:	f023 0304 	bic.w	r3, r3, #4
    9090:	613b      	str	r3, [r7, #16]
                *(g_config_reg_lut[gpio_idx]) = config;
    9092:	697a      	ldr	r2, [r7, #20]
    9094:	f649 6398 	movw	r3, #40600	; 0x9e98
    9098:	f2c0 0300 	movt	r3, #0
    909c:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
    90a0:	693a      	ldr	r2, [r7, #16]
    90a2:	601a      	str	r2, [r3, #0]
            break;
    90a4:	e000      	b.n	90a8 <MSS_GPIO_drive_inout+0x11c>
                
            default:
                ASSERT(0);
    90a6:	be00      	bkpt	0x0000
            break;
        }
    }
}
    90a8:	f107 071c 	add.w	r7, r7, #28
    90ac:	46bd      	mov	sp, r7
    90ae:	bc80      	pop	{r7}
    90b0:	4770      	bx	lr
    90b2:	bf00      	nop

000090b4 <MSS_GPIO_enable_irq>:
 */
void MSS_GPIO_enable_irq
(
    mss_gpio_id_t port_id
)
{
    90b4:	b580      	push	{r7, lr}
    90b6:	b084      	sub	sp, #16
    90b8:	af00      	add	r7, sp, #0
    90ba:	4603      	mov	r3, r0
    90bc:	71fb      	strb	r3, [r7, #7]
    uint32_t cfg_value;
    uint32_t gpio_idx = (uint32_t)port_id;
    90be:	79fb      	ldrb	r3, [r7, #7]
    90c0:	60fb      	str	r3, [r7, #12]
    
    ASSERT(gpio_idx < NB_OF_GPIO);
    90c2:	68fb      	ldr	r3, [r7, #12]
    90c4:	2b1f      	cmp	r3, #31
    90c6:	d900      	bls.n	90ca <MSS_GPIO_enable_irq+0x16>
    90c8:	be00      	bkpt	0x0000
    
    if(gpio_idx < NB_OF_GPIO)
    90ca:	68fb      	ldr	r3, [r7, #12]
    90cc:	2b1f      	cmp	r3, #31
    90ce:	d81d      	bhi.n	910c <MSS_GPIO_enable_irq+0x58>
    {
        cfg_value = *(g_config_reg_lut[gpio_idx]);
    90d0:	68fa      	ldr	r2, [r7, #12]
    90d2:	f649 6398 	movw	r3, #40600	; 0x9e98
    90d6:	f2c0 0300 	movt	r3, #0
    90da:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
    90de:	681b      	ldr	r3, [r3, #0]
    90e0:	60bb      	str	r3, [r7, #8]
        *(g_config_reg_lut[gpio_idx]) = (cfg_value | GPIO_INT_ENABLE_MASK);
    90e2:	68fa      	ldr	r2, [r7, #12]
    90e4:	f649 6398 	movw	r3, #40600	; 0x9e98
    90e8:	f2c0 0300 	movt	r3, #0
    90ec:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
    90f0:	68ba      	ldr	r2, [r7, #8]
    90f2:	f042 0208 	orr.w	r2, r2, #8
    90f6:	601a      	str	r2, [r3, #0]
        NVIC_EnableIRQ(g_gpio_irqn_lut[gpio_idx]);
    90f8:	68fa      	ldr	r2, [r7, #12]
    90fa:	f649 7318 	movw	r3, #40728	; 0x9f18
    90fe:	f2c0 0300 	movt	r3, #0
    9102:	5c9b      	ldrb	r3, [r3, r2]
    9104:	b25b      	sxtb	r3, r3
    9106:	4618      	mov	r0, r3
    9108:	f7ff fe3c 	bl	8d84 <NVIC_EnableIRQ>
    }
}
    910c:	f107 0710 	add.w	r7, r7, #16
    9110:	46bd      	mov	sp, r7
    9112:	bd80      	pop	{r7, pc}

00009114 <MSS_GPIO_disable_irq>:
 */
void MSS_GPIO_disable_irq
(
    mss_gpio_id_t port_id
)
{
    9114:	b480      	push	{r7}
    9116:	b085      	sub	sp, #20
    9118:	af00      	add	r7, sp, #0
    911a:	4603      	mov	r3, r0
    911c:	71fb      	strb	r3, [r7, #7]
    uint32_t cfg_value;
    uint32_t gpio_idx = (uint32_t)port_id;
    911e:	79fb      	ldrb	r3, [r7, #7]
    9120:	60fb      	str	r3, [r7, #12]
    
    ASSERT(gpio_idx < NB_OF_GPIO);
    9122:	68fb      	ldr	r3, [r7, #12]
    9124:	2b1f      	cmp	r3, #31
    9126:	d900      	bls.n	912a <MSS_GPIO_disable_irq+0x16>
    9128:	be00      	bkpt	0x0000

    if(gpio_idx < NB_OF_GPIO)
    912a:	68fb      	ldr	r3, [r7, #12]
    912c:	2b1f      	cmp	r3, #31
    912e:	d813      	bhi.n	9158 <MSS_GPIO_disable_irq+0x44>
    {
        cfg_value = *(g_config_reg_lut[gpio_idx]);
    9130:	68fa      	ldr	r2, [r7, #12]
    9132:	f649 6398 	movw	r3, #40600	; 0x9e98
    9136:	f2c0 0300 	movt	r3, #0
    913a:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
    913e:	681b      	ldr	r3, [r3, #0]
    9140:	60bb      	str	r3, [r7, #8]
        *(g_config_reg_lut[gpio_idx]) = (cfg_value & ~GPIO_INT_ENABLE_MASK);
    9142:	68fa      	ldr	r2, [r7, #12]
    9144:	f649 6398 	movw	r3, #40600	; 0x9e98
    9148:	f2c0 0300 	movt	r3, #0
    914c:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
    9150:	68ba      	ldr	r2, [r7, #8]
    9152:	f022 0208 	bic.w	r2, r2, #8
    9156:	601a      	str	r2, [r3, #0]
    }
}
    9158:	f107 0714 	add.w	r7, r7, #20
    915c:	46bd      	mov	sp, r7
    915e:	bc80      	pop	{r7}
    9160:	4770      	bx	lr
    9162:	bf00      	nop

00009164 <MSS_GPIO_clear_irq>:
 */
void MSS_GPIO_clear_irq
(
    mss_gpio_id_t port_id
)
{
    9164:	b480      	push	{r7}
    9166:	b085      	sub	sp, #20
    9168:	af00      	add	r7, sp, #0
    916a:	4603      	mov	r3, r0
    916c:	71fb      	strb	r3, [r7, #7]
    uint32_t gpio_idx = (uint32_t)port_id;
    916e:	79fb      	ldrb	r3, [r7, #7]
    9170:	60fb      	str	r3, [r7, #12]
    
    ASSERT(gpio_idx < NB_OF_GPIO);
    9172:	68fb      	ldr	r3, [r7, #12]
    9174:	2b1f      	cmp	r3, #31
    9176:	d900      	bls.n	917a <MSS_GPIO_clear_irq+0x16>
    9178:	be00      	bkpt	0x0000
    
    if(gpio_idx < NB_OF_GPIO)
    917a:	68fb      	ldr	r3, [r7, #12]
    917c:	2b1f      	cmp	r3, #31
    917e:	d80a      	bhi.n	9196 <MSS_GPIO_clear_irq+0x32>
    {
        GPIO->GPIO_IRQ = ((uint32_t)1) << gpio_idx;
    9180:	f243 0300 	movw	r3, #12288	; 0x3000
    9184:	f2c4 0301 	movt	r3, #16385	; 0x4001
    9188:	68fa      	ldr	r2, [r7, #12]
    918a:	f04f 0101 	mov.w	r1, #1
    918e:	fa01 f202 	lsl.w	r2, r1, r2
    9192:	f8c3 2080 	str.w	r2, [r3, #128]	; 0x80
    }
    __ASM volatile ("dsb");
    9196:	f3bf 8f4f 	dsb	sy

}
    919a:	f107 0714 	add.w	r7, r7, #20
    919e:	46bd      	mov	sp, r7
    91a0:	bc80      	pop	{r7}
    91a2:	4770      	bx	lr

000091a4 <_close>:

/*==============================================================================
 * Close a file.
 */
int _close(int file)
{
    91a4:	b480      	push	{r7}
    91a6:	b083      	sub	sp, #12
    91a8:	af00      	add	r7, sp, #0
    91aa:	6078      	str	r0, [r7, #4]
    return -1;
    91ac:	f04f 33ff 	mov.w	r3, #4294967295
}
    91b0:	4618      	mov	r0, r3
    91b2:	f107 070c 	add.w	r7, r7, #12
    91b6:	46bd      	mov	sp, r7
    91b8:	bc80      	pop	{r7}
    91ba:	4770      	bx	lr

000091bc <_execve>:

/*==============================================================================
 * Transfer control to a new process.
 */
int _execve(char *name, char **argv, char **env)
{
    91bc:	b580      	push	{r7, lr}
    91be:	b084      	sub	sp, #16
    91c0:	af00      	add	r7, sp, #0
    91c2:	60f8      	str	r0, [r7, #12]
    91c4:	60b9      	str	r1, [r7, #8]
    91c6:	607a      	str	r2, [r7, #4]
    errno = ENOMEM;
    91c8:	f000 fcbc 	bl	9b44 <__errno>
    91cc:	4603      	mov	r3, r0
    91ce:	f04f 020c 	mov.w	r2, #12
    91d2:	601a      	str	r2, [r3, #0]
    return -1;
    91d4:	f04f 33ff 	mov.w	r3, #4294967295
}
    91d8:	4618      	mov	r0, r3
    91da:	f107 0710 	add.w	r7, r7, #16
    91de:	46bd      	mov	sp, r7
    91e0:	bd80      	pop	{r7, pc}
    91e2:	bf00      	nop

000091e4 <_exit>:
{
    /* Should we force a system reset? */
    while( 1 )
    {
        ;
    }
    91e4:	b480      	push	{r7}
    91e6:	b083      	sub	sp, #12
    91e8:	af00      	add	r7, sp, #0
    91ea:	6078      	str	r0, [r7, #4]
    91ec:	e7fe      	b.n	91ec <_exit+0x8>
    91ee:	bf00      	nop

000091f0 <_fork>:

/*==============================================================================
 * Create a new process.
 */
int _fork(void)
{
    91f0:	b580      	push	{r7, lr}
    91f2:	af00      	add	r7, sp, #0
    errno = EAGAIN;
    91f4:	f000 fca6 	bl	9b44 <__errno>
    91f8:	4603      	mov	r3, r0
    91fa:	f04f 020b 	mov.w	r2, #11
    91fe:	601a      	str	r2, [r3, #0]
    return -1;
    9200:	f04f 33ff 	mov.w	r3, #4294967295
}
    9204:	4618      	mov	r0, r3
    9206:	bd80      	pop	{r7, pc}

00009208 <_fstat>:

/*==============================================================================
 * Status of an open file.
 */
int _fstat(int file, struct stat *st)
{
    9208:	b480      	push	{r7}
    920a:	b083      	sub	sp, #12
    920c:	af00      	add	r7, sp, #0
    920e:	6078      	str	r0, [r7, #4]
    9210:	6039      	str	r1, [r7, #0]
    st->st_mode = S_IFCHR;
    9212:	683b      	ldr	r3, [r7, #0]
    9214:	f44f 5200 	mov.w	r2, #8192	; 0x2000
    9218:	605a      	str	r2, [r3, #4]
    return 0;
    921a:	f04f 0300 	mov.w	r3, #0
}
    921e:	4618      	mov	r0, r3
    9220:	f107 070c 	add.w	r7, r7, #12
    9224:	46bd      	mov	sp, r7
    9226:	bc80      	pop	{r7}
    9228:	4770      	bx	lr
    922a:	bf00      	nop

0000922c <_getpid>:

/*==============================================================================
 * Process-ID
 */
int _getpid(void)
{
    922c:	b480      	push	{r7}
    922e:	af00      	add	r7, sp, #0
    return 1;
    9230:	f04f 0301 	mov.w	r3, #1
}
    9234:	4618      	mov	r0, r3
    9236:	46bd      	mov	sp, r7
    9238:	bc80      	pop	{r7}
    923a:	4770      	bx	lr

0000923c <_isatty>:

/*==============================================================================
 * Query whether output stream is a terminal.
 */
int _isatty(int file)
{
    923c:	b480      	push	{r7}
    923e:	b083      	sub	sp, #12
    9240:	af00      	add	r7, sp, #0
    9242:	6078      	str	r0, [r7, #4]
    return 1;
    9244:	f04f 0301 	mov.w	r3, #1
}
    9248:	4618      	mov	r0, r3
    924a:	f107 070c 	add.w	r7, r7, #12
    924e:	46bd      	mov	sp, r7
    9250:	bc80      	pop	{r7}
    9252:	4770      	bx	lr

00009254 <_kill>:

/*==============================================================================
 * Send a signal.
 */
int _kill(int pid, int sig)
{
    9254:	b580      	push	{r7, lr}
    9256:	b082      	sub	sp, #8
    9258:	af00      	add	r7, sp, #0
    925a:	6078      	str	r0, [r7, #4]
    925c:	6039      	str	r1, [r7, #0]
    errno = EINVAL;
    925e:	f000 fc71 	bl	9b44 <__errno>
    9262:	4603      	mov	r3, r0
    9264:	f04f 0216 	mov.w	r2, #22
    9268:	601a      	str	r2, [r3, #0]
    return -1;
    926a:	f04f 33ff 	mov.w	r3, #4294967295
}
    926e:	4618      	mov	r0, r3
    9270:	f107 0708 	add.w	r7, r7, #8
    9274:	46bd      	mov	sp, r7
    9276:	bd80      	pop	{r7, pc}

00009278 <_link>:

/*==============================================================================
 * Establish a new name for an existing file.
 */
int _link(char *old, char *new)
{
    9278:	b580      	push	{r7, lr}
    927a:	b082      	sub	sp, #8
    927c:	af00      	add	r7, sp, #0
    927e:	6078      	str	r0, [r7, #4]
    9280:	6039      	str	r1, [r7, #0]
    errno = EMLINK;
    9282:	f000 fc5f 	bl	9b44 <__errno>
    9286:	4603      	mov	r3, r0
    9288:	f04f 021f 	mov.w	r2, #31
    928c:	601a      	str	r2, [r3, #0]
    return -1;
    928e:	f04f 33ff 	mov.w	r3, #4294967295
}
    9292:	4618      	mov	r0, r3
    9294:	f107 0708 	add.w	r7, r7, #8
    9298:	46bd      	mov	sp, r7
    929a:	bd80      	pop	{r7, pc}

0000929c <_lseek>:

/*==============================================================================
 * Set position in a file.
 */
int _lseek(int file, int ptr, int dir)
{
    929c:	b480      	push	{r7}
    929e:	b085      	sub	sp, #20
    92a0:	af00      	add	r7, sp, #0
    92a2:	60f8      	str	r0, [r7, #12]
    92a4:	60b9      	str	r1, [r7, #8]
    92a6:	607a      	str	r2, [r7, #4]
    return 0;
    92a8:	f04f 0300 	mov.w	r3, #0
}
    92ac:	4618      	mov	r0, r3
    92ae:	f107 0714 	add.w	r7, r7, #20
    92b2:	46bd      	mov	sp, r7
    92b4:	bc80      	pop	{r7}
    92b6:	4770      	bx	lr

000092b8 <_open>:

/*==============================================================================
 * Open a file.
 */
int _open(const char *name, int flags, int mode)
{
    92b8:	b480      	push	{r7}
    92ba:	b085      	sub	sp, #20
    92bc:	af00      	add	r7, sp, #0
    92be:	60f8      	str	r0, [r7, #12]
    92c0:	60b9      	str	r1, [r7, #8]
    92c2:	607a      	str	r2, [r7, #4]
    return -1;
    92c4:	f04f 33ff 	mov.w	r3, #4294967295
}
    92c8:	4618      	mov	r0, r3
    92ca:	f107 0714 	add.w	r7, r7, #20
    92ce:	46bd      	mov	sp, r7
    92d0:	bc80      	pop	{r7}
    92d2:	4770      	bx	lr

000092d4 <_read>:

/*==============================================================================
 * Read from a file.
 */
int _read(int file, char *ptr, int len)
{
    92d4:	b480      	push	{r7}
    92d6:	b085      	sub	sp, #20
    92d8:	af00      	add	r7, sp, #0
    92da:	60f8      	str	r0, [r7, #12]
    92dc:	60b9      	str	r1, [r7, #8]
    92de:	607a      	str	r2, [r7, #4]
    return 0;
    92e0:	f04f 0300 	mov.w	r3, #0
}
    92e4:	4618      	mov	r0, r3
    92e6:	f107 0714 	add.w	r7, r7, #20
    92ea:	46bd      	mov	sp, r7
    92ec:	bc80      	pop	{r7}
    92ee:	4770      	bx	lr

000092f0 <_write_r>:
 * all files, including stdoutso if you need to generate any output, for
 * example to a serial port for debugging, you should make your minimal write
 * capable of doing this.
 */
int _write_r( void * reent, int file, char * ptr, int len )
{
    92f0:	b480      	push	{r7}
    92f2:	b085      	sub	sp, #20
    92f4:	af00      	add	r7, sp, #0
    92f6:	60f8      	str	r0, [r7, #12]
    92f8:	60b9      	str	r1, [r7, #8]
    92fa:	607a      	str	r2, [r7, #4]
    92fc:	603b      	str	r3, [r7, #0]
     */
    MSS_UART_polled_tx(gp_my_uart, (uint8_t *)ptr, len);
    
    return len;
#else   /* MICROSEMI_STDIO_THRU_UART */
    return 0;
    92fe:	f04f 0300 	mov.w	r3, #0
#endif  /* MICROSEMI_STDIO_THRU_UART */
}
    9302:	4618      	mov	r0, r3
    9304:	f107 0714 	add.w	r7, r7, #20
    9308:	46bd      	mov	sp, r7
    930a:	bc80      	pop	{r7}
    930c:	4770      	bx	lr
    930e:	bf00      	nop

00009310 <_sbrk>:
 * it is useful to have a working implementation. The following suffices for a
 * standalone system; it exploits the symbol _end automatically defined by the
 * GNU linker. 
 */
caddr_t _sbrk(int incr)
{
    9310:	b580      	push	{r7, lr}
    9312:	b086      	sub	sp, #24
    9314:	af00      	add	r7, sp, #0
    9316:	6078      	str	r0, [r7, #4]
    extern char _end;       /* Defined by the linker */
    static char *heap_end;
    char *prev_heap_end;
    char * stack_ptr;
    
    if (heap_end == 0)
    9318:	f240 13b0 	movw	r3, #432	; 0x1b0
    931c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    9320:	681b      	ldr	r3, [r3, #0]
    9322:	2b00      	cmp	r3, #0
    9324:	d108      	bne.n	9338 <_sbrk+0x28>
    {
      heap_end = &_end;
    9326:	f240 13b0 	movw	r3, #432	; 0x1b0
    932a:	f2c2 0300 	movt	r3, #8192	; 0x2000
    932e:	f240 3240 	movw	r2, #832	; 0x340
    9332:	f2c2 0200 	movt	r2, #8192	; 0x2000
    9336:	601a      	str	r2, [r3, #0]
    }
    
    prev_heap_end = heap_end;
    9338:	f240 13b0 	movw	r3, #432	; 0x1b0
    933c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    9340:	681b      	ldr	r3, [r3, #0]
    9342:	60fb      	str	r3, [r7, #12]
    
    asm volatile ("MRS %0, msp" : "=r" (stack_ptr) );
    9344:	f3ef 8308 	mrs	r3, MSP
    9348:	613b      	str	r3, [r7, #16]
    if(heap_end < stack_ptr)
    934a:	f240 13b0 	movw	r3, #432	; 0x1b0
    934e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    9352:	681a      	ldr	r2, [r3, #0]
    9354:	693b      	ldr	r3, [r7, #16]
    9356:	429a      	cmp	r2, r3
    9358:	d219      	bcs.n	938e <_sbrk+0x7e>
        /*
         * Heap is at an address below the stack, growing up toward the stack.
         * The stack is above the heap, growing down towards the heap.
         * Make sure the stack and heap do not run into each other.
         */
        if (heap_end + incr > stack_ptr)
    935a:	f240 13b0 	movw	r3, #432	; 0x1b0
    935e:	f2c2 0300 	movt	r3, #8192	; 0x2000
    9362:	681a      	ldr	r2, [r3, #0]
    9364:	687b      	ldr	r3, [r7, #4]
    9366:	441a      	add	r2, r3
    9368:	693b      	ldr	r3, [r7, #16]
    936a:	429a      	cmp	r2, r3
    936c:	d92e      	bls.n	93cc <_sbrk+0xbc>
        {
          _write_r ((void *)0, 1, "Heap and stack collision\n", 25);
    936e:	f04f 0000 	mov.w	r0, #0
    9372:	f04f 0101 	mov.w	r1, #1
    9376:	f649 7240 	movw	r2, #40768	; 0x9f40
    937a:	f2c0 0200 	movt	r2, #0
    937e:	f04f 0319 	mov.w	r3, #25
    9382:	f7ff ffb5 	bl	92f0 <_write_r>
          _exit (1);
    9386:	f04f 0001 	mov.w	r0, #1
    938a:	f7ff ff2b 	bl	91e4 <_exit>
         * SmartFusion2 cache design.
         */
        extern char _eheap;     /* Defined by the linker */
        char *top_of_heap;
        
        top_of_heap = &_eheap;
    938e:	f24f 0300 	movw	r3, #61440	; 0xf000
    9392:	f2c2 0300 	movt	r3, #8192	; 0x2000
    9396:	617b      	str	r3, [r7, #20]
        if(heap_end + incr  > top_of_heap)
    9398:	f240 13b0 	movw	r3, #432	; 0x1b0
    939c:	f2c2 0300 	movt	r3, #8192	; 0x2000
    93a0:	681a      	ldr	r2, [r3, #0]
    93a2:	687b      	ldr	r3, [r7, #4]
    93a4:	441a      	add	r2, r3
    93a6:	697b      	ldr	r3, [r7, #20]
    93a8:	429a      	cmp	r2, r3
    93aa:	d910      	bls.n	93ce <_sbrk+0xbe>
        {
          _write_r ((void *)0, 1, "Out of heap memory\n", 25);
    93ac:	f04f 0000 	mov.w	r0, #0
    93b0:	f04f 0101 	mov.w	r1, #1
    93b4:	f649 725c 	movw	r2, #40796	; 0x9f5c
    93b8:	f2c0 0200 	movt	r2, #0
    93bc:	f04f 0319 	mov.w	r3, #25
    93c0:	f7ff ff96 	bl	92f0 <_write_r>
          _exit (1);
    93c4:	f04f 0001 	mov.w	r0, #1
    93c8:	f7ff ff0c 	bl	91e4 <_exit>
         * Make sure the stack and heap do not run into each other.
         */
        if (heap_end + incr > stack_ptr)
        {
          _write_r ((void *)0, 1, "Heap and stack collision\n", 25);
          _exit (1);
    93cc:	bf00      	nop
          _write_r ((void *)0, 1, "Out of heap memory\n", 25);
          _exit (1);
        }
    }
  
    heap_end += incr;
    93ce:	f240 13b0 	movw	r3, #432	; 0x1b0
    93d2:	f2c2 0300 	movt	r3, #8192	; 0x2000
    93d6:	681a      	ldr	r2, [r3, #0]
    93d8:	687b      	ldr	r3, [r7, #4]
    93da:	441a      	add	r2, r3
    93dc:	f240 13b0 	movw	r3, #432	; 0x1b0
    93e0:	f2c2 0300 	movt	r3, #8192	; 0x2000
    93e4:	601a      	str	r2, [r3, #0]
    return (caddr_t) prev_heap_end;
    93e6:	68fb      	ldr	r3, [r7, #12]
}
    93e8:	4618      	mov	r0, r3
    93ea:	f107 0718 	add.w	r7, r7, #24
    93ee:	46bd      	mov	sp, r7
    93f0:	bd80      	pop	{r7, pc}
    93f2:	bf00      	nop

000093f4 <_stat>:

/*==============================================================================
 * Status of a file (by name).
 */
int _stat(char *file, struct stat *st)
{
    93f4:	b480      	push	{r7}
    93f6:	b083      	sub	sp, #12
    93f8:	af00      	add	r7, sp, #0
    93fa:	6078      	str	r0, [r7, #4]
    93fc:	6039      	str	r1, [r7, #0]
    st->st_mode = S_IFCHR;
    93fe:	683b      	ldr	r3, [r7, #0]
    9400:	f44f 5200 	mov.w	r2, #8192	; 0x2000
    9404:	605a      	str	r2, [r3, #4]
    return 0;
    9406:	f04f 0300 	mov.w	r3, #0
}
    940a:	4618      	mov	r0, r3
    940c:	f107 070c 	add.w	r7, r7, #12
    9410:	46bd      	mov	sp, r7
    9412:	bc80      	pop	{r7}
    9414:	4770      	bx	lr
    9416:	bf00      	nop

00009418 <_times>:

/*==============================================================================
 * Timing information for current process.
 */
int _times(struct tms *buf)
{
    9418:	b480      	push	{r7}
    941a:	b083      	sub	sp, #12
    941c:	af00      	add	r7, sp, #0
    941e:	6078      	str	r0, [r7, #4]
    return -1;
    9420:	f04f 33ff 	mov.w	r3, #4294967295
}
    9424:	4618      	mov	r0, r3
    9426:	f107 070c 	add.w	r7, r7, #12
    942a:	46bd      	mov	sp, r7
    942c:	bc80      	pop	{r7}
    942e:	4770      	bx	lr

00009430 <_unlink>:

/*==============================================================================
 * Remove a file's directory entry.
 */
int _unlink(char *name)
{
    9430:	b580      	push	{r7, lr}
    9432:	b082      	sub	sp, #8
    9434:	af00      	add	r7, sp, #0
    9436:	6078      	str	r0, [r7, #4]
    errno = ENOENT;
    9438:	f000 fb84 	bl	9b44 <__errno>
    943c:	4603      	mov	r3, r0
    943e:	f04f 0202 	mov.w	r2, #2
    9442:	601a      	str	r2, [r3, #0]
    return -1;
    9444:	f04f 33ff 	mov.w	r3, #4294967295
}
    9448:	4618      	mov	r0, r3
    944a:	f107 0708 	add.w	r7, r7, #8
    944e:	46bd      	mov	sp, r7
    9450:	bd80      	pop	{r7, pc}
    9452:	bf00      	nop

00009454 <_wait>:

/*==============================================================================
 * Wait for a child process.
 */
int _wait(int *status)
{
    9454:	b580      	push	{r7, lr}
    9456:	b082      	sub	sp, #8
    9458:	af00      	add	r7, sp, #0
    945a:	6078      	str	r0, [r7, #4]
    errno = ECHILD;
    945c:	f000 fb72 	bl	9b44 <__errno>
    9460:	4603      	mov	r3, r0
    9462:	f04f 020a 	mov.w	r2, #10
    9466:	601a      	str	r2, [r3, #0]
    return -1;
    9468:	f04f 33ff 	mov.w	r3, #4294967295
}
    946c:	4618      	mov	r0, r3
    946e:	f107 0708 	add.w	r7, r7, #8
    9472:	46bd      	mov	sp, r7
    9474:	bd80      	pop	{r7, pc}
    9476:	bf00      	nop

00009478 <FLASH_init>:
);
/*******************************************************************************
 *
 */
void FLASH_init( void )
{
    9478:	b580      	push	{r7, lr}
    947a:	b082      	sub	sp, #8
    947c:	af02      	add	r7, sp, #8
    /*--------------------------------------------------------------------------
     * Configure SPI.
     */
    MSS_SPI_init( &g_mss_spi0 );
    947e:	f240 20bc 	movw	r0, #700	; 0x2bc
    9482:	f2c2 0000 	movt	r0, #8192	; 0x2000
    9486:	f7fc fd4f 	bl	5f28 <MSS_SPI_init>
    
    MSS_SPI_configure_master_mode
    948a:	f04f 0308 	mov.w	r3, #8
    948e:	9300      	str	r3, [sp, #0]
    9490:	f240 20bc 	movw	r0, #700	; 0x2bc
    9494:	f2c2 0000 	movt	r0, #8192	; 0x2000
    9498:	f04f 0100 	mov.w	r1, #0
    949c:	f04f 7240 	mov.w	r2, #50331648	; 0x3000000
    94a0:	f04f 0320 	mov.w	r3, #32
    94a4:	f7fc fef2 	bl	628c <MSS_SPI_configure_master_mode>
            PDMA_TO_SPI_1,
            PDMA_LOW_PRIORITY | PDMA_BYTE_TRANSFER | PDMA_INC_SRC_ONE_BYTE,
            PDMA_DEFAULT_WRITE_ADJ
        );
*/
}
    94a8:	46bd      	mov	sp, r7
    94aa:	bd80      	pop	{r7, pc}

000094ac <FLASH_read_device_id>:
void FLASH_read_device_id
(
    uint8_t * manufacturer_id,
    uint8_t * device_id
)
{
    94ac:	b580      	push	{r7, lr}
    94ae:	b086      	sub	sp, #24
    94b0:	af02      	add	r7, sp, #8
    94b2:	6078      	str	r0, [r7, #4]
    94b4:	6039      	str	r1, [r7, #0]
    uint8_t read_device_id_cmd = DEVICE_ID_READ;
    94b6:	f06f 0360 	mvn.w	r3, #96	; 0x60
    94ba:	73fb      	strb	r3, [r7, #15]
    uint8_t read_buffer[2];
    *manufacturer_id = 0;
    94bc:	687b      	ldr	r3, [r7, #4]
    94be:	f04f 0200 	mov.w	r2, #0
    94c2:	701a      	strb	r2, [r3, #0]
	*device_id = 0;
    94c4:	683b      	ldr	r3, [r7, #0]
    94c6:	f04f 0200 	mov.w	r2, #0
    94ca:	701a      	strb	r2, [r3, #0]
    MSS_SPI_set_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );
    94cc:	f240 20bc 	movw	r0, #700	; 0x2bc
    94d0:	f2c2 0000 	movt	r0, #8192	; 0x2000
    94d4:	f04f 0100 	mov.w	r1, #0
    94d8:	f7fc ff80 	bl	63dc <MSS_SPI_set_slave_select>
    MSS_SPI_transfer_block( &g_mss_spi0, &read_device_id_cmd, 1, read_buffer, sizeof(read_buffer) );
    94dc:	f107 020f 	add.w	r2, r7, #15
    94e0:	f107 030c 	add.w	r3, r7, #12
    94e4:	f04f 0102 	mov.w	r1, #2
    94e8:	9100      	str	r1, [sp, #0]
    94ea:	f240 20bc 	movw	r0, #700	; 0x2bc
    94ee:	f2c2 0000 	movt	r0, #8192	; 0x2000
    94f2:	4611      	mov	r1, r2
    94f4:	f04f 0201 	mov.w	r2, #1
    94f8:	f7fd f89c 	bl	6634 <MSS_SPI_transfer_block>
    MSS_SPI_clear_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );
    94fc:	f240 20bc 	movw	r0, #700	; 0x2bc
    9500:	f2c2 0000 	movt	r0, #8192	; 0x2000
    9504:	f04f 0100 	mov.w	r1, #0
    9508:	f7fc ffec 	bl	64e4 <MSS_SPI_clear_slave_select>
    *manufacturer_id = read_buffer[0];
    950c:	7b3a      	ldrb	r2, [r7, #12]
    950e:	687b      	ldr	r3, [r7, #4]
    9510:	701a      	strb	r2, [r3, #0]
    *device_id = read_buffer[1];
    9512:	7b7a      	ldrb	r2, [r7, #13]
    9514:	683b      	ldr	r3, [r7, #0]
    9516:	701a      	strb	r2, [r3, #0]
}
    9518:	f107 0710 	add.w	r7, r7, #16
    951c:	46bd      	mov	sp, r7
    951e:	bd80      	pop	{r7, pc}

00009520 <FLASH_read>:
(
    uint32_t address,
    uint8_t * rx_buffer,
    size_t size_in_bytes
)
{
    9520:	b580      	push	{r7, lr}
    9522:	b088      	sub	sp, #32
    9524:	af02      	add	r7, sp, #8
    9526:	60f8      	str	r0, [r7, #12]
    9528:	60b9      	str	r1, [r7, #8]
    952a:	607a      	str	r2, [r7, #4]
    uint8_t cmd_buffer[5];

    write_enable();
    952c:	f000 f9b0 	bl	9890 <write_enable>
    enter_4byte_address_mode();
    9530:	f000 f9d8 	bl	98e4 <enter_4byte_address_mode>

    cmd_buffer[0] = READ_ARRAY_OPCODE;
    9534:	f04f 0303 	mov.w	r3, #3
    9538:	743b      	strb	r3, [r7, #16]
    cmd_buffer[1] = (uint8_t)((address >> 24) & 0xFF);
    953a:	68fb      	ldr	r3, [r7, #12]
    953c:	ea4f 6313 	mov.w	r3, r3, lsr #24
    9540:	b2db      	uxtb	r3, r3
    9542:	747b      	strb	r3, [r7, #17]
    cmd_buffer[2] = (uint8_t)((address >> 16) & 0xFF);
    9544:	68fb      	ldr	r3, [r7, #12]
    9546:	ea4f 4313 	mov.w	r3, r3, lsr #16
    954a:	b2db      	uxtb	r3, r3
    954c:	74bb      	strb	r3, [r7, #18]
    cmd_buffer[3] = (uint8_t)((address >> 8) & 0xFF);
    954e:	68fb      	ldr	r3, [r7, #12]
    9550:	ea4f 2313 	mov.w	r3, r3, lsr #8
    9554:	b2db      	uxtb	r3, r3
    9556:	74fb      	strb	r3, [r7, #19]
    cmd_buffer[4] = (uint8_t)(address & 0xFF);
    9558:	68fb      	ldr	r3, [r7, #12]
    955a:	b2db      	uxtb	r3, r3
    955c:	753b      	strb	r3, [r7, #20]
    MSS_SPI_set_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );
    955e:	f240 20bc 	movw	r0, #700	; 0x2bc
    9562:	f2c2 0000 	movt	r0, #8192	; 0x2000
    9566:	f04f 0100 	mov.w	r1, #0
    956a:	f7fc ff37 	bl	63dc <MSS_SPI_set_slave_select>
    //wait_ready();
    MSS_SPI_transfer_block( &g_mss_spi0, cmd_buffer, 5, rx_buffer, size_in_bytes );
    956e:	687b      	ldr	r3, [r7, #4]
    9570:	b29a      	uxth	r2, r3
    9572:	f107 0310 	add.w	r3, r7, #16
    9576:	9200      	str	r2, [sp, #0]
    9578:	f240 20bc 	movw	r0, #700	; 0x2bc
    957c:	f2c2 0000 	movt	r0, #8192	; 0x2000
    9580:	4619      	mov	r1, r3
    9582:	f04f 0205 	mov.w	r2, #5
    9586:	68bb      	ldr	r3, [r7, #8]
    9588:	f7fd f854 	bl	6634 <MSS_SPI_transfer_block>
    //wait_ready();
    MSS_SPI_clear_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );
    958c:	f240 20bc 	movw	r0, #700	; 0x2bc
    9590:	f2c2 0000 	movt	r0, #8192	; 0x2000
    9594:	f04f 0100 	mov.w	r1, #0
    9598:	f7fc ffa4 	bl	64e4 <MSS_SPI_clear_slave_select>

    write_enable();
    959c:	f000 f978 	bl	9890 <write_enable>
    exit_4byte_address_mode();
    95a0:	f000 f9ca 	bl	9938 <exit_4byte_address_mode>

}
    95a4:	f107 0718 	add.w	r7, r7, #24
    95a8:	46bd      	mov	sp, r7
    95aa:	bd80      	pop	{r7, pc}

000095ac <FLASH_global_unprotect>:

/*******************************************************************************
 *
 */
void FLASH_global_unprotect( void )
{
    95ac:	b580      	push	{r7, lr}
    95ae:	b084      	sub	sp, #16
    95b0:	af02      	add	r7, sp, #8
    uint8_t cmd_buffer[2];
    write_enable();
    95b2:	f000 f96d 	bl	9890 <write_enable>
    cmd_buffer[0] = WRITE_STATUS1_OPCODE;
    95b6:	f04f 0301 	mov.w	r3, #1
    95ba:	713b      	strb	r3, [r7, #4]
    cmd_buffer[1] = 0;
    95bc:	f04f 0300 	mov.w	r3, #0
    95c0:	717b      	strb	r3, [r7, #5]

    MSS_SPI_set_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );
    95c2:	f240 20bc 	movw	r0, #700	; 0x2bc
    95c6:	f2c2 0000 	movt	r0, #8192	; 0x2000
    95ca:	f04f 0100 	mov.w	r1, #0
    95ce:	f7fc ff05 	bl	63dc <MSS_SPI_set_slave_select>
    //wait_ready();
    MSS_SPI_transfer_block( &g_mss_spi0, cmd_buffer, 2, 0, 0 );
    95d2:	f107 0304 	add.w	r3, r7, #4
    95d6:	f04f 0200 	mov.w	r2, #0
    95da:	9200      	str	r2, [sp, #0]
    95dc:	f240 20bc 	movw	r0, #700	; 0x2bc
    95e0:	f2c2 0000 	movt	r0, #8192	; 0x2000
    95e4:	4619      	mov	r1, r3
    95e6:	f04f 0202 	mov.w	r2, #2
    95ea:	f04f 0300 	mov.w	r3, #0
    95ee:	f7fd f821 	bl	6634 <MSS_SPI_transfer_block>
    //wait_ready();
    wait_program_or_erase_controller_ready();
    95f2:	f000 fa63 	bl	9abc <wait_program_or_erase_controller_ready>
    wait_program_or_erase_controller_ready();
    95f6:	f000 fa61 	bl	9abc <wait_program_or_erase_controller_ready>
    wait_program_or_erase_controller_ready();
    95fa:	f000 fa5f 	bl	9abc <wait_program_or_erase_controller_ready>
    wait_program_or_erase_controller_ready();
    95fe:	f000 fa5d 	bl	9abc <wait_program_or_erase_controller_ready>
    MSS_SPI_clear_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );
    9602:	f240 20bc 	movw	r0, #700	; 0x2bc
    9606:	f2c2 0000 	movt	r0, #8192	; 0x2000
    960a:	f04f 0100 	mov.w	r1, #0
    960e:	f7fc ff69 	bl	64e4 <MSS_SPI_clear_slave_select>

}
    9612:	f107 0708 	add.w	r7, r7, #8
    9616:	46bd      	mov	sp, r7
    9618:	bd80      	pop	{r7, pc}
    961a:	bf00      	nop

0000961c <FLASH_die_256MB_erase>:

/*******************************************************************************
 *
 */
void FLASH_die_256MB_erase( uint8_t flag )
{
    961c:	b580      	push	{r7, lr}
    961e:	b088      	sub	sp, #32
    9620:	af02      	add	r7, sp, #8
    9622:	4603      	mov	r3, r0
    9624:	71fb      	strb	r3, [r7, #7]
    uint8_t cmd_buffer[5];
    uint32_t address;
    /* Send Write Enable command */
    write_enable();
    9626:	f000 f933 	bl	9890 <write_enable>
    enter_4byte_address_mode();
    962a:	f000 f95b 	bl	98e4 <enter_4byte_address_mode>
    write_enable();
    962e:	f000 f92f 	bl	9890 <write_enable>

    switch(flag)
    9632:	79fb      	ldrb	r3, [r7, #7]
    9634:	2b03      	cmp	r3, #3
    9636:	d81b      	bhi.n	9670 <FLASH_die_256MB_erase+0x54>
    9638:	a201      	add	r2, pc, #4	; (adr r2, 9640 <FLASH_die_256MB_erase+0x24>)
    963a:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
    963e:	bf00      	nop
    9640:	00009651 	.word	0x00009651
    9644:	00009659 	.word	0x00009659
    9648:	00009661 	.word	0x00009661
    964c:	00009669 	.word	0x00009669
    {
    case DIE_ERASE_0_256MB:
    	address = 0x0;
    9650:	f04f 0300 	mov.w	r3, #0
    9654:	617b      	str	r3, [r7, #20]
    	break;
    9656:	e00e      	b.n	9676 <FLASH_die_256MB_erase+0x5a>
    case DIE_ERASE_256MB_512MB:
    	address = 0x10000000;
    9658:	f04f 5380 	mov.w	r3, #268435456	; 0x10000000
    965c:	617b      	str	r3, [r7, #20]
    	break;
    965e:	e00a      	b.n	9676 <FLASH_die_256MB_erase+0x5a>
    case DIE_ERASE_512MB_768MB:
    	address = 0x20000000;
    9660:	f04f 5300 	mov.w	r3, #536870912	; 0x20000000
    9664:	617b      	str	r3, [r7, #20]
    	break;
    9666:	e006      	b.n	9676 <FLASH_die_256MB_erase+0x5a>
    case DIE_ERASE_768MB_1GB:
    	address = 0x30000000;
    9668:	f04f 5340 	mov.w	r3, #805306368	; 0x30000000
    966c:	617b      	str	r3, [r7, #20]
    	break;
    966e:	e002      	b.n	9676 <FLASH_die_256MB_erase+0x5a>
    default:
    	address = 0x0;
    9670:	f04f 0300 	mov.w	r3, #0
    9674:	617b      	str	r3, [r7, #20]
    	break;
    }


    MSS_SPI_set_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );
    9676:	f240 20bc 	movw	r0, #700	; 0x2bc
    967a:	f2c2 0000 	movt	r0, #8192	; 0x2000
    967e:	f04f 0100 	mov.w	r1, #0
    9682:	f7fc feab 	bl	63dc <MSS_SPI_set_slave_select>
    cmd_buffer[0] = DIE_256MB_ERASE_OPCODE;
    9686:	f06f 033b 	mvn.w	r3, #59	; 0x3b
    968a:	733b      	strb	r3, [r7, #12]
    cmd_buffer[1] = (uint8_t)((address >> 24) & 0xFF);
    968c:	697b      	ldr	r3, [r7, #20]
    968e:	ea4f 6313 	mov.w	r3, r3, lsr #24
    9692:	b2db      	uxtb	r3, r3
    9694:	737b      	strb	r3, [r7, #13]
   	cmd_buffer[2] = (uint8_t)((address >> 16) & 0xFF);
    9696:	697b      	ldr	r3, [r7, #20]
    9698:	ea4f 4313 	mov.w	r3, r3, lsr #16
    969c:	b2db      	uxtb	r3, r3
    969e:	73bb      	strb	r3, [r7, #14]
   	cmd_buffer[3] = (uint8_t)((address >> 8) & 0xFF);
    96a0:	697b      	ldr	r3, [r7, #20]
    96a2:	ea4f 2313 	mov.w	r3, r3, lsr #8
    96a6:	b2db      	uxtb	r3, r3
    96a8:	73fb      	strb	r3, [r7, #15]
   	cmd_buffer[4] = (uint8_t)(address & 0xFF);
    96aa:	697b      	ldr	r3, [r7, #20]
    96ac:	b2db      	uxtb	r3, r3
    96ae:	743b      	strb	r3, [r7, #16]
    //wait_ready();
    MSS_SPI_transfer_block( &g_mss_spi0, cmd_buffer, 5, 0, 0 );
    96b0:	f107 030c 	add.w	r3, r7, #12
    96b4:	f04f 0200 	mov.w	r2, #0
    96b8:	9200      	str	r2, [sp, #0]
    96ba:	f240 20bc 	movw	r0, #700	; 0x2bc
    96be:	f2c2 0000 	movt	r0, #8192	; 0x2000
    96c2:	4619      	mov	r1, r3
    96c4:	f04f 0205 	mov.w	r2, #5
    96c8:	f04f 0300 	mov.w	r3, #0
    96cc:	f7fc ffb2 	bl	6634 <MSS_SPI_transfer_block>
    wait_program_or_erase_controller_ready();
    96d0:	f000 f9f4 	bl	9abc <wait_program_or_erase_controller_ready>
    MSS_SPI_clear_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );
    96d4:	f240 20bc 	movw	r0, #700	; 0x2bc
    96d8:	f2c2 0000 	movt	r0, #8192	; 0x2000
    96dc:	f04f 0100 	mov.w	r1, #0
    96e0:	f7fc ff00 	bl	64e4 <MSS_SPI_clear_slave_select>
}
    96e4:	f107 0718 	add.w	r7, r7, #24
    96e8:	46bd      	mov	sp, r7
    96ea:	bd80      	pop	{r7, pc}

000096ec <FLASH_erase_xk_block>:
 */
void FLASH_erase_xk_block
(
    uint32_t address, uint8_t xk_block
)
{
    96ec:	b580      	push	{r7, lr}
    96ee:	b086      	sub	sp, #24
    96f0:	af02      	add	r7, sp, #8
    96f2:	6078      	str	r0, [r7, #4]
    96f4:	460b      	mov	r3, r1
    96f6:	70fb      	strb	r3, [r7, #3]
    uint8_t cmd_buffer[5];
    /* Send Write Enable command */

   write_enable();
    96f8:	f000 f8ca 	bl	9890 <write_enable>
   enter_4byte_address_mode();
    96fc:	f000 f8f2 	bl	98e4 <enter_4byte_address_mode>
   write_enable();
    9700:	f000 f8c6 	bl	9890 <write_enable>


    MSS_SPI_set_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );
    9704:	f240 20bc 	movw	r0, #700	; 0x2bc
    9708:	f2c2 0000 	movt	r0, #8192	; 0x2000
    970c:	f04f 0100 	mov.w	r1, #0
    9710:	f7fc fe64 	bl	63dc <MSS_SPI_set_slave_select>
    /* Send Chip Erase command */
    if(xk_block == ERASE_4K_BLOCK)
    9714:	78fb      	ldrb	r3, [r7, #3]
    9716:	2b00      	cmp	r3, #0
    9718:	d103      	bne.n	9722 <FLASH_erase_xk_block+0x36>
    	cmd_buffer[0] = ERASE_4K_BLOCK_OPCODE;
    971a:	f04f 0320 	mov.w	r3, #32
    971e:	723b      	strb	r3, [r7, #8]
    9720:	e002      	b.n	9728 <FLASH_erase_xk_block+0x3c>
    else
    	cmd_buffer[0] = ERASE_64K_BLOCK_OPCODE;
    9722:	f06f 0327 	mvn.w	r3, #39	; 0x27
    9726:	723b      	strb	r3, [r7, #8]
    cmd_buffer[1] = (uint8_t)((address >> 24) & 0xFF);
    9728:	687b      	ldr	r3, [r7, #4]
    972a:	ea4f 6313 	mov.w	r3, r3, lsr #24
    972e:	b2db      	uxtb	r3, r3
    9730:	727b      	strb	r3, [r7, #9]
	cmd_buffer[2] = (uint8_t)((address >> 16) & 0xFF);
    9732:	687b      	ldr	r3, [r7, #4]
    9734:	ea4f 4313 	mov.w	r3, r3, lsr #16
    9738:	b2db      	uxtb	r3, r3
    973a:	72bb      	strb	r3, [r7, #10]
	cmd_buffer[3] = (uint8_t)((address >> 8) & 0xFF);
    973c:	687b      	ldr	r3, [r7, #4]
    973e:	ea4f 2313 	mov.w	r3, r3, lsr #8
    9742:	b2db      	uxtb	r3, r3
    9744:	72fb      	strb	r3, [r7, #11]
	cmd_buffer[4] = (uint8_t)(address & 0xFF);
    9746:	687b      	ldr	r3, [r7, #4]
    9748:	b2db      	uxtb	r3, r3
    974a:	733b      	strb	r3, [r7, #12]
    //wait_ready();
    MSS_SPI_transfer_block( &g_mss_spi0, cmd_buffer,5, 0, 0 );
    974c:	f107 0308 	add.w	r3, r7, #8
    9750:	f04f 0200 	mov.w	r2, #0
    9754:	9200      	str	r2, [sp, #0]
    9756:	f240 20bc 	movw	r0, #700	; 0x2bc
    975a:	f2c2 0000 	movt	r0, #8192	; 0x2000
    975e:	4619      	mov	r1, r3
    9760:	f04f 0205 	mov.w	r2, #5
    9764:	f04f 0300 	mov.w	r3, #0
    9768:	f7fc ff64 	bl	6634 <MSS_SPI_transfer_block>
    //wait_ready();
    wait_program_or_erase_controller_ready();
    976c:	f000 f9a6 	bl	9abc <wait_program_or_erase_controller_ready>
    MSS_SPI_clear_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );
    9770:	f240 20bc 	movw	r0, #700	; 0x2bc
    9774:	f2c2 0000 	movt	r0, #8192	; 0x2000
    9778:	f04f 0100 	mov.w	r1, #0
    977c:	f7fc feb2 	bl	64e4 <MSS_SPI_clear_slave_select>

    write_enable();
    9780:	f000 f886 	bl	9890 <write_enable>
    exit_4byte_address_mode();
    9784:	f000 f8d8 	bl	9938 <exit_4byte_address_mode>

}
    9788:	f107 0710 	add.w	r7, r7, #16
    978c:	46bd      	mov	sp, r7
    978e:	bd80      	pop	{r7, pc}

00009790 <write_cmd_data>:
    const uint8_t * cmd_buffer,
    uint16_t cmd_byte_size,
    uint8_t * data_buffer,
    uint16_t data_byte_size
)
{
    9790:	b580      	push	{r7, lr}
    9792:	f5ad 7d0a 	sub.w	sp, sp, #552	; 0x228
    9796:	af02      	add	r7, sp, #8
    9798:	f107 0c0c 	add.w	ip, r7, #12
    979c:	f8cc 0000 	str.w	r0, [ip]
    97a0:	f107 0008 	add.w	r0, r7, #8
    97a4:	6001      	str	r1, [r0, #0]
    97a6:	4639      	mov	r1, r7
    97a8:	600b      	str	r3, [r1, #0]
    97aa:	f107 0308 	add.w	r3, r7, #8
    97ae:	f1a3 0302 	sub.w	r3, r3, #2
    97b2:	801a      	strh	r2, [r3, #0]
    MSS_SPI_enable( this_spi );
#else

    uint8_t tx_buffer[520];
    uint16_t transfer_size;
    uint16_t idx = 0;
    97b4:	f04f 0300 	mov.w	r3, #0
    97b8:	f8a7 321e 	strh.w	r3, [r7, #542]	; 0x21e
    
    transfer_size = cmd_byte_size + data_byte_size;
    97bc:	f107 0308 	add.w	r3, r7, #8
    97c0:	f1a3 0302 	sub.w	r3, r3, #2
    97c4:	881a      	ldrh	r2, [r3, #0]
    97c6:	f8b7 3228 	ldrh.w	r3, [r7, #552]	; 0x228
    97ca:	4413      	add	r3, r2
    97cc:	f8a7 321c 	strh.w	r3, [r7, #540]	; 0x21c
    
    for(idx = 0; idx < cmd_byte_size; ++idx)
    97d0:	f04f 0300 	mov.w	r3, #0
    97d4:	f8a7 321e 	strh.w	r3, [r7, #542]	; 0x21e
    97d8:	e011      	b.n	97fe <write_cmd_data+0x6e>
    {
        tx_buffer[idx] = cmd_buffer[idx];
    97da:	f8b7 321e 	ldrh.w	r3, [r7, #542]	; 0x21e
    97de:	f8b7 121e 	ldrh.w	r1, [r7, #542]	; 0x21e
    97e2:	f107 0208 	add.w	r2, r7, #8
    97e6:	6812      	ldr	r2, [r2, #0]
    97e8:	440a      	add	r2, r1
    97ea:	7811      	ldrb	r1, [r2, #0]
    97ec:	f107 0214 	add.w	r2, r7, #20
    97f0:	54d1      	strb	r1, [r2, r3]
    uint16_t transfer_size;
    uint16_t idx = 0;
    
    transfer_size = cmd_byte_size + data_byte_size;
    
    for(idx = 0; idx < cmd_byte_size; ++idx)
    97f2:	f8b7 321e 	ldrh.w	r3, [r7, #542]	; 0x21e
    97f6:	f103 0301 	add.w	r3, r3, #1
    97fa:	f8a7 321e 	strh.w	r3, [r7, #542]	; 0x21e
    97fe:	f107 0308 	add.w	r3, r7, #8
    9802:	f1a3 0302 	sub.w	r3, r3, #2
    9806:	f8b7 221e 	ldrh.w	r2, [r7, #542]	; 0x21e
    980a:	881b      	ldrh	r3, [r3, #0]
    980c:	429a      	cmp	r2, r3
    980e:	d3e4      	bcc.n	97da <write_cmd_data+0x4a>
    {
        tx_buffer[idx] = cmd_buffer[idx];
    }

    for(idx = 0; idx < data_byte_size; ++idx)
    9810:	f04f 0300 	mov.w	r3, #0
    9814:	f8a7 321e 	strh.w	r3, [r7, #542]	; 0x21e
    9818:	e016      	b.n	9848 <write_cmd_data+0xb8>
    {
        tx_buffer[cmd_byte_size + idx] = data_buffer[idx];
    981a:	f107 0308 	add.w	r3, r7, #8
    981e:	f1a3 0302 	sub.w	r3, r3, #2
    9822:	881a      	ldrh	r2, [r3, #0]
    9824:	f8b7 321e 	ldrh.w	r3, [r7, #542]	; 0x21e
    9828:	4413      	add	r3, r2
    982a:	f8b7 121e 	ldrh.w	r1, [r7, #542]	; 0x21e
    982e:	463a      	mov	r2, r7
    9830:	6812      	ldr	r2, [r2, #0]
    9832:	440a      	add	r2, r1
    9834:	7811      	ldrb	r1, [r2, #0]
    9836:	f107 0214 	add.w	r2, r7, #20
    983a:	54d1      	strb	r1, [r2, r3]
    for(idx = 0; idx < cmd_byte_size; ++idx)
    {
        tx_buffer[idx] = cmd_buffer[idx];
    }

    for(idx = 0; idx < data_byte_size; ++idx)
    983c:	f8b7 321e 	ldrh.w	r3, [r7, #542]	; 0x21e
    9840:	f103 0301 	add.w	r3, r3, #1
    9844:	f8a7 321e 	strh.w	r3, [r7, #542]	; 0x21e
    9848:	f8b7 221e 	ldrh.w	r2, [r7, #542]	; 0x21e
    984c:	f8b7 3228 	ldrh.w	r3, [r7, #552]	; 0x228
    9850:	429a      	cmp	r2, r3
    9852:	d3e2      	bcc.n	981a <write_cmd_data+0x8a>
    {
        tx_buffer[cmd_byte_size + idx] = data_buffer[idx];
    }
    
    MSS_SPI_transfer_block( &g_mss_spi0, tx_buffer, transfer_size, 0, 0 );
    9854:	f107 0214 	add.w	r2, r7, #20
    9858:	f8b7 321c 	ldrh.w	r3, [r7, #540]	; 0x21c
    985c:	f04f 0100 	mov.w	r1, #0
    9860:	9100      	str	r1, [sp, #0]
    9862:	f240 20bc 	movw	r0, #700	; 0x2bc
    9866:	f2c2 0000 	movt	r0, #8192	; 0x2000
    986a:	4611      	mov	r1, r2
    986c:	461a      	mov	r2, r3
    986e:	f04f 0300 	mov.w	r3, #0
    9872:	f7fc fedf 	bl	6634 <MSS_SPI_transfer_block>
    
#endif    
    while ( !MSS_SPI_tx_done(this_spi) )
    9876:	f107 030c 	add.w	r3, r7, #12
    987a:	6818      	ldr	r0, [r3, #0]
    987c:	f7fd fb04 	bl	6e88 <MSS_SPI_tx_done>
    9880:	4603      	mov	r3, r0
    9882:	2b00      	cmp	r3, #0
    9884:	d0f7      	beq.n	9876 <write_cmd_data+0xe6>
    {
        ;
    }
}
    9886:	f507 7708 	add.w	r7, r7, #544	; 0x220
    988a:	46bd      	mov	sp, r7
    988c:	bd80      	pop	{r7, pc}
    988e:	bf00      	nop

00009890 <write_enable>:
static void write_enable()
{
    9890:	b580      	push	{r7, lr}
    9892:	b084      	sub	sp, #16
    9894:	af02      	add	r7, sp, #8
	uint8_t cmd_buffer;
	MSS_SPI_set_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );
    9896:	f240 20bc 	movw	r0, #700	; 0x2bc
    989a:	f2c2 0000 	movt	r0, #8192	; 0x2000
    989e:	f04f 0100 	mov.w	r1, #0
    98a2:	f7fc fd9b 	bl	63dc <MSS_SPI_set_slave_select>
   /* Send Write Enable command */
   cmd_buffer = WRITE_ENABLE_CMD;
    98a6:	f04f 0306 	mov.w	r3, #6
    98aa:	71fb      	strb	r3, [r7, #7]
   //wait_ready();
   MSS_SPI_transfer_block( &g_mss_spi0, &cmd_buffer, 1, 0, 0 );
    98ac:	f107 0307 	add.w	r3, r7, #7
    98b0:	f04f 0200 	mov.w	r2, #0
    98b4:	9200      	str	r2, [sp, #0]
    98b6:	f240 20bc 	movw	r0, #700	; 0x2bc
    98ba:	f2c2 0000 	movt	r0, #8192	; 0x2000
    98be:	4619      	mov	r1, r3
    98c0:	f04f 0201 	mov.w	r2, #1
    98c4:	f04f 0300 	mov.w	r3, #0
    98c8:	f7fc feb4 	bl	6634 <MSS_SPI_transfer_block>
  // wait_ready();
   MSS_SPI_clear_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0);
    98cc:	f240 20bc 	movw	r0, #700	; 0x2bc
    98d0:	f2c2 0000 	movt	r0, #8192	; 0x2000
    98d4:	f04f 0100 	mov.w	r1, #0
    98d8:	f7fc fe04 	bl	64e4 <MSS_SPI_clear_slave_select>
}
    98dc:	f107 0708 	add.w	r7, r7, #8
    98e0:	46bd      	mov	sp, r7
    98e2:	bd80      	pop	{r7, pc}

000098e4 <enter_4byte_address_mode>:
static void enter_4byte_address_mode()
{
    98e4:	b580      	push	{r7, lr}
    98e6:	b084      	sub	sp, #16
    98e8:	af02      	add	r7, sp, #8
	uint8_t cmd_buffer;
	MSS_SPI_set_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );
    98ea:	f240 20bc 	movw	r0, #700	; 0x2bc
    98ee:	f2c2 0000 	movt	r0, #8192	; 0x2000
    98f2:	f04f 0100 	mov.w	r1, #0
    98f6:	f7fc fd71 	bl	63dc <MSS_SPI_set_slave_select>
   cmd_buffer = ADDRESS_MODE_4BYTE;
    98fa:	f06f 0348 	mvn.w	r3, #72	; 0x48
    98fe:	71fb      	strb	r3, [r7, #7]
   //wait_ready();
   MSS_SPI_transfer_block( &g_mss_spi0, &cmd_buffer, 1, 0, 0 );
    9900:	f107 0307 	add.w	r3, r7, #7
    9904:	f04f 0200 	mov.w	r2, #0
    9908:	9200      	str	r2, [sp, #0]
    990a:	f240 20bc 	movw	r0, #700	; 0x2bc
    990e:	f2c2 0000 	movt	r0, #8192	; 0x2000
    9912:	4619      	mov	r1, r3
    9914:	f04f 0201 	mov.w	r2, #1
    9918:	f04f 0300 	mov.w	r3, #0
    991c:	f7fc fe8a 	bl	6634 <MSS_SPI_transfer_block>
   //wait_ready();
   MSS_SPI_clear_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0);
    9920:	f240 20bc 	movw	r0, #700	; 0x2bc
    9924:	f2c2 0000 	movt	r0, #8192	; 0x2000
    9928:	f04f 0100 	mov.w	r1, #0
    992c:	f7fc fdda 	bl	64e4 <MSS_SPI_clear_slave_select>
}
    9930:	f107 0708 	add.w	r7, r7, #8
    9934:	46bd      	mov	sp, r7
    9936:	bd80      	pop	{r7, pc}

00009938 <exit_4byte_address_mode>:

static void exit_4byte_address_mode()
{
    9938:	b580      	push	{r7, lr}
    993a:	b084      	sub	sp, #16
    993c:	af02      	add	r7, sp, #8
	uint8_t cmd_buffer;
	MSS_SPI_set_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );
    993e:	f240 20bc 	movw	r0, #700	; 0x2bc
    9942:	f2c2 0000 	movt	r0, #8192	; 0x2000
    9946:	f04f 0100 	mov.w	r1, #0
    994a:	f7fc fd47 	bl	63dc <MSS_SPI_set_slave_select>
    cmd_buffer = EXIT_ADDRESS_MODE_4BYTE;
    994e:	f06f 0316 	mvn.w	r3, #22
    9952:	71fb      	strb	r3, [r7, #7]
   //wait_ready();
   MSS_SPI_transfer_block( &g_mss_spi0, &cmd_buffer, 1, 0, 0 );
    9954:	f107 0307 	add.w	r3, r7, #7
    9958:	f04f 0200 	mov.w	r2, #0
    995c:	9200      	str	r2, [sp, #0]
    995e:	f240 20bc 	movw	r0, #700	; 0x2bc
    9962:	f2c2 0000 	movt	r0, #8192	; 0x2000
    9966:	4619      	mov	r1, r3
    9968:	f04f 0201 	mov.w	r2, #1
    996c:	f04f 0300 	mov.w	r3, #0
    9970:	f7fc fe60 	bl	6634 <MSS_SPI_transfer_block>
   //wait_ready();
   MSS_SPI_clear_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0);
    9974:	f240 20bc 	movw	r0, #700	; 0x2bc
    9978:	f2c2 0000 	movt	r0, #8192	; 0x2000
    997c:	f04f 0100 	mov.w	r1, #0
    9980:	f7fc fdb0 	bl	64e4 <MSS_SPI_clear_slave_select>
}
    9984:	f107 0708 	add.w	r7, r7, #8
    9988:	46bd      	mov	sp, r7
    998a:	bd80      	pop	{r7, pc}

0000998c <FLASH_program>:
(
    uint32_t address,
    uint8_t * write_buffer,
    size_t size_in_bytes
)
{
    998c:	b580      	push	{r7, lr}
    998e:	b08c      	sub	sp, #48	; 0x30
    9990:	af02      	add	r7, sp, #8
    9992:	60f8      	str	r0, [r7, #12]
    9994:	60b9      	str	r1, [r7, #8]
    9996:	607a      	str	r2, [r7, #4]
    uint32_t in_buffer_idx;
    uint32_t nb_bytes_to_write;
    uint32_t target_addr;


    write_enable();
    9998:	f7ff ff7a 	bl	9890 <write_enable>
    enter_4byte_address_mode();
    999c:	f7ff ffa2 	bl	98e4 <enter_4byte_address_mode>
    
    in_buffer_idx = 0;
    99a0:	f04f 0300 	mov.w	r3, #0
    99a4:	61bb      	str	r3, [r7, #24]
    nb_bytes_to_write = size_in_bytes;
    99a6:	687b      	ldr	r3, [r7, #4]
    99a8:	61fb      	str	r3, [r7, #28]
    target_addr = address;
    99aa:	68fb      	ldr	r3, [r7, #12]
    99ac:	623b      	str	r3, [r7, #32]
    
    while ( in_buffer_idx < size_in_bytes )
    99ae:	e056      	b.n	9a5e <FLASH_program+0xd2>
    {
        uint32_t size_left;
        nb_bytes_to_write = 0x100 - (target_addr & 0xFF);   /* adjust max possible size to page boundary. */
    99b0:	6a3b      	ldr	r3, [r7, #32]
    99b2:	f003 03ff 	and.w	r3, r3, #255	; 0xff
    99b6:	f5c3 7380 	rsb	r3, r3, #256	; 0x100
    99ba:	61fb      	str	r3, [r7, #28]
        size_left = size_in_bytes - in_buffer_idx;
    99bc:	687a      	ldr	r2, [r7, #4]
    99be:	69bb      	ldr	r3, [r7, #24]
    99c0:	ebc3 0302 	rsb	r3, r3, r2
    99c4:	627b      	str	r3, [r7, #36]	; 0x24
        if ( size_left < nb_bytes_to_write )
    99c6:	6a7a      	ldr	r2, [r7, #36]	; 0x24
    99c8:	69fb      	ldr	r3, [r7, #28]
    99ca:	429a      	cmp	r2, r3
    99cc:	d201      	bcs.n	99d2 <FLASH_program+0x46>
        {
            nb_bytes_to_write = size_left;
    99ce:	6a7b      	ldr	r3, [r7, #36]	; 0x24
    99d0:	61fb      	str	r3, [r7, #28]
        }
        
        write_enable();
    99d2:	f7ff ff5d 	bl	9890 <write_enable>
		enter_4byte_address_mode();
    99d6:	f7ff ff85 	bl	98e4 <enter_4byte_address_mode>
        write_enable();
    99da:	f7ff ff59 	bl	9890 <write_enable>
        /* Program page */


        cmd_buffer[0] = PROGRAM_PAGE_CMD;
    99de:	f04f 0302 	mov.w	r3, #2
    99e2:	743b      	strb	r3, [r7, #16]
        cmd_buffer[1] = (uint8_t)((target_addr >> 24) & 0xFF);
    99e4:	6a3b      	ldr	r3, [r7, #32]
    99e6:	ea4f 6313 	mov.w	r3, r3, lsr #24
    99ea:	b2db      	uxtb	r3, r3
    99ec:	747b      	strb	r3, [r7, #17]
		cmd_buffer[2] = (uint8_t)((target_addr >> 16) & 0xFF);
    99ee:	6a3b      	ldr	r3, [r7, #32]
    99f0:	ea4f 4313 	mov.w	r3, r3, lsr #16
    99f4:	b2db      	uxtb	r3, r3
    99f6:	74bb      	strb	r3, [r7, #18]
		cmd_buffer[3] = (uint8_t)((target_addr >> 8) & 0xFF);
    99f8:	6a3b      	ldr	r3, [r7, #32]
    99fa:	ea4f 2313 	mov.w	r3, r3, lsr #8
    99fe:	b2db      	uxtb	r3, r3
    9a00:	74fb      	strb	r3, [r7, #19]
		cmd_buffer[4] = (uint8_t)(target_addr & 0xFF);
    9a02:	6a3b      	ldr	r3, [r7, #32]
    9a04:	b2db      	uxtb	r3, r3
    9a06:	753b      	strb	r3, [r7, #20]
		MSS_SPI_set_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );
    9a08:	f240 20bc 	movw	r0, #700	; 0x2bc
    9a0c:	f2c2 0000 	movt	r0, #8192	; 0x2000
    9a10:	f04f 0100 	mov.w	r1, #0
    9a14:	f7fc fce2 	bl	63dc <MSS_SPI_set_slave_select>
        //wait_ready();
        write_cmd_data
    9a18:	68ba      	ldr	r2, [r7, #8]
    9a1a:	69bb      	ldr	r3, [r7, #24]
    9a1c:	4413      	add	r3, r2
    9a1e:	69fa      	ldr	r2, [r7, #28]
    9a20:	b291      	uxth	r1, r2
    9a22:	f107 0210 	add.w	r2, r7, #16
    9a26:	9100      	str	r1, [sp, #0]
    9a28:	f240 20bc 	movw	r0, #700	; 0x2bc
    9a2c:	f2c2 0000 	movt	r0, #8192	; 0x2000
    9a30:	4611      	mov	r1, r2
    9a32:	f04f 0205 	mov.w	r2, #5
    9a36:	f7ff feab 	bl	9790 <write_cmd_data>
            sizeof(cmd_buffer),
            &write_buffer[in_buffer_idx],
            nb_bytes_to_write
          );
       // wait_ready();
        wait_program_or_erase_controller_ready();
    9a3a:	f000 f83f 	bl	9abc <wait_program_or_erase_controller_ready>
        MSS_SPI_clear_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );
    9a3e:	f240 20bc 	movw	r0, #700	; 0x2bc
    9a42:	f2c2 0000 	movt	r0, #8192	; 0x2000
    9a46:	f04f 0100 	mov.w	r1, #0
    9a4a:	f7fc fd4b 	bl	64e4 <MSS_SPI_clear_slave_select>
        target_addr += nb_bytes_to_write;
    9a4e:	6a3a      	ldr	r2, [r7, #32]
    9a50:	69fb      	ldr	r3, [r7, #28]
    9a52:	4413      	add	r3, r2
    9a54:	623b      	str	r3, [r7, #32]
        in_buffer_idx += nb_bytes_to_write;
    9a56:	69ba      	ldr	r2, [r7, #24]
    9a58:	69fb      	ldr	r3, [r7, #28]
    9a5a:	4413      	add	r3, r2
    9a5c:	61bb      	str	r3, [r7, #24]
    
    in_buffer_idx = 0;
    nb_bytes_to_write = size_in_bytes;
    target_addr = address;
    
    while ( in_buffer_idx < size_in_bytes )
    9a5e:	69ba      	ldr	r2, [r7, #24]
    9a60:	687b      	ldr	r3, [r7, #4]
    9a62:	429a      	cmp	r2, r3
    9a64:	d3a4      	bcc.n	99b0 <FLASH_program+0x24>
        target_addr += nb_bytes_to_write;
        in_buffer_idx += nb_bytes_to_write;
    }
    
    /* Send Write Disable command. */
    MSS_SPI_set_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );
    9a66:	f240 20bc 	movw	r0, #700	; 0x2bc
    9a6a:	f2c2 0000 	movt	r0, #8192	; 0x2000
    9a6e:	f04f 0100 	mov.w	r1, #0
    9a72:	f7fc fcb3 	bl	63dc <MSS_SPI_set_slave_select>
    cmd_buffer[0] = WRITE_DISABLE_CMD;
    9a76:	f04f 0304 	mov.w	r3, #4
    9a7a:	743b      	strb	r3, [r7, #16]
    //wait_ready();
    MSS_SPI_transfer_block( &g_mss_spi0, cmd_buffer, 1, 0, 0 );
    9a7c:	f107 0310 	add.w	r3, r7, #16
    9a80:	f04f 0200 	mov.w	r2, #0
    9a84:	9200      	str	r2, [sp, #0]
    9a86:	f240 20bc 	movw	r0, #700	; 0x2bc
    9a8a:	f2c2 0000 	movt	r0, #8192	; 0x2000
    9a8e:	4619      	mov	r1, r3
    9a90:	f04f 0201 	mov.w	r2, #1
    9a94:	f04f 0300 	mov.w	r3, #0
    9a98:	f7fc fdcc 	bl	6634 <MSS_SPI_transfer_block>
    //wait_ready();
    MSS_SPI_clear_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );
    9a9c:	f240 20bc 	movw	r0, #700	; 0x2bc
    9aa0:	f2c2 0000 	movt	r0, #8192	; 0x2000
    9aa4:	f04f 0100 	mov.w	r1, #0
    9aa8:	f7fc fd1c 	bl	64e4 <MSS_SPI_clear_slave_select>
    write_enable();
    9aac:	f7ff fef0 	bl	9890 <write_enable>
    exit_4byte_address_mode();
    9ab0:	f7ff ff42 	bl	9938 <exit_4byte_address_mode>
}
    9ab4:	f107 0728 	add.w	r7, r7, #40	; 0x28
    9ab8:	46bd      	mov	sp, r7
    9aba:	bd80      	pop	{r7, pc}

00009abc <wait_program_or_erase_controller_ready>:


 static void wait_program_or_erase_controller_ready(void  )
{
    9abc:	b580      	push	{r7, lr}
    9abe:	b084      	sub	sp, #16
    9ac0:	af02      	add	r7, sp, #8
    uint8_t ready_bit;
    uint8_t command = READ_FLAG_STATUS_REGISTER;
    9ac2:	f04f 0370 	mov.w	r3, #112	; 0x70
    9ac6:	71bb      	strb	r3, [r7, #6]
    //MSS_SPI_set_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );
    do {

        MSS_SPI_transfer_block( &g_mss_spi0, &command, 1, &ready_bit, sizeof(ready_bit) );
    9ac8:	f107 0206 	add.w	r2, r7, #6
    9acc:	f107 0307 	add.w	r3, r7, #7
    9ad0:	f04f 0101 	mov.w	r1, #1
    9ad4:	9100      	str	r1, [sp, #0]
    9ad6:	f240 20bc 	movw	r0, #700	; 0x2bc
    9ada:	f2c2 0000 	movt	r0, #8192	; 0x2000
    9ade:	4611      	mov	r1, r2
    9ae0:	f04f 0201 	mov.w	r2, #1
    9ae4:	f7fc fda6 	bl	6634 <MSS_SPI_transfer_block>
        ready_bit = ready_bit & 0x80;
    9ae8:	79fb      	ldrb	r3, [r7, #7]
    9aea:	f003 0380 	and.w	r3, r3, #128	; 0x80
    9aee:	71fb      	strb	r3, [r7, #7]

     } while( ready_bit == 0 );
    9af0:	79fb      	ldrb	r3, [r7, #7]
    9af2:	2b00      	cmp	r3, #0
    9af4:	d0e8      	beq.n	9ac8 <wait_program_or_erase_controller_ready+0xc>
    //MSS_SPI_clear_slave_select( &g_mss_spi0, MSS_SPI_SLAVE_0 );
}
    9af6:	f107 0708 	add.w	r7, r7, #8
    9afa:	46bd      	mov	sp, r7
    9afc:	bd80      	pop	{r7, pc}
    9afe:	bf00      	nop

00009b00 <wait_ready>:
/*******************************************************************************
 *
 */

static void wait_ready( void )
{
    9b00:	b580      	push	{r7, lr}
    9b02:	b084      	sub	sp, #16
    9b04:	af02      	add	r7, sp, #8
    uint8_t ready_bit;
    uint8_t command = READ_STATUS;
    9b06:	f04f 0305 	mov.w	r3, #5
    9b0a:	71bb      	strb	r3, [r7, #6]

    do {

        MSS_SPI_transfer_block( &g_mss_spi0, &command, sizeof(command), &ready_bit, sizeof(ready_bit) );
    9b0c:	f107 0206 	add.w	r2, r7, #6
    9b10:	f107 0307 	add.w	r3, r7, #7
    9b14:	f04f 0101 	mov.w	r1, #1
    9b18:	9100      	str	r1, [sp, #0]
    9b1a:	f240 20bc 	movw	r0, #700	; 0x2bc
    9b1e:	f2c2 0000 	movt	r0, #8192	; 0x2000
    9b22:	4611      	mov	r1, r2
    9b24:	f04f 0201 	mov.w	r2, #1
    9b28:	f7fc fd84 	bl	6634 <MSS_SPI_transfer_block>
        ready_bit = ready_bit & READY_BIT_MASK;
    9b2c:	79fb      	ldrb	r3, [r7, #7]
    9b2e:	f003 0301 	and.w	r3, r3, #1
    9b32:	71fb      	strb	r3, [r7, #7]

    } while( ready_bit == 1 );
    9b34:	79fb      	ldrb	r3, [r7, #7]
    9b36:	2b01      	cmp	r3, #1
    9b38:	d0e8      	beq.n	9b0c <wait_ready+0xc>

}
    9b3a:	f107 0708 	add.w	r7, r7, #8
    9b3e:	46bd      	mov	sp, r7
    9b40:	bd80      	pop	{r7, pc}
    9b42:	bf00      	nop

00009b44 <__errno>:
    9b44:	f240 0330 	movw	r3, #48	; 0x30
    9b48:	f2c2 0300 	movt	r3, #8192	; 0x2000
    9b4c:	6818      	ldr	r0, [r3, #0]
    9b4e:	4770      	bx	lr

00009b50 <__libc_init_array>:
    9b50:	b570      	push	{r4, r5, r6, lr}
    9b52:	f649 7690 	movw	r6, #40848	; 0x9f90
    9b56:	f649 7590 	movw	r5, #40848	; 0x9f90
    9b5a:	f2c0 0600 	movt	r6, #0
    9b5e:	f2c0 0500 	movt	r5, #0
    9b62:	1b76      	subs	r6, r6, r5
    9b64:	10b6      	asrs	r6, r6, #2
    9b66:	d006      	beq.n	9b76 <__libc_init_array+0x26>
    9b68:	2400      	movs	r4, #0
    9b6a:	f855 3024 	ldr.w	r3, [r5, r4, lsl #2]
    9b6e:	3401      	adds	r4, #1
    9b70:	4798      	blx	r3
    9b72:	42a6      	cmp	r6, r4
    9b74:	d8f9      	bhi.n	9b6a <__libc_init_array+0x1a>
    9b76:	f649 7590 	movw	r5, #40848	; 0x9f90
    9b7a:	f649 7694 	movw	r6, #40852	; 0x9f94
    9b7e:	f2c0 0500 	movt	r5, #0
    9b82:	f2c0 0600 	movt	r6, #0
    9b86:	1b76      	subs	r6, r6, r5
    9b88:	f000 f9f6 	bl	9f78 <_init>
    9b8c:	10b6      	asrs	r6, r6, #2
    9b8e:	d006      	beq.n	9b9e <__libc_init_array+0x4e>
    9b90:	2400      	movs	r4, #0
    9b92:	f855 3024 	ldr.w	r3, [r5, r4, lsl #2]
    9b96:	3401      	adds	r4, #1
    9b98:	4798      	blx	r3
    9b9a:	42a6      	cmp	r6, r4
    9b9c:	d8f9      	bhi.n	9b92 <__libc_init_array+0x42>
    9b9e:	bd70      	pop	{r4, r5, r6, pc}

00009ba0 <memcpy>:
    9ba0:	2a03      	cmp	r2, #3
    9ba2:	e92d 07f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl}
    9ba6:	d80b      	bhi.n	9bc0 <memcpy+0x20>
    9ba8:	b13a      	cbz	r2, 9bba <memcpy+0x1a>
    9baa:	2300      	movs	r3, #0
    9bac:	f811 c003 	ldrb.w	ip, [r1, r3]
    9bb0:	f800 c003 	strb.w	ip, [r0, r3]
    9bb4:	3301      	adds	r3, #1
    9bb6:	4293      	cmp	r3, r2
    9bb8:	d1f8      	bne.n	9bac <memcpy+0xc>
    9bba:	e8bd 07f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl}
    9bbe:	4770      	bx	lr
    9bc0:	1882      	adds	r2, r0, r2
    9bc2:	460c      	mov	r4, r1
    9bc4:	4603      	mov	r3, r0
    9bc6:	e003      	b.n	9bd0 <memcpy+0x30>
    9bc8:	f814 1c01 	ldrb.w	r1, [r4, #-1]
    9bcc:	f803 1c01 	strb.w	r1, [r3, #-1]
    9bd0:	f003 0603 	and.w	r6, r3, #3
    9bd4:	4619      	mov	r1, r3
    9bd6:	46a4      	mov	ip, r4
    9bd8:	3301      	adds	r3, #1
    9bda:	3401      	adds	r4, #1
    9bdc:	2e00      	cmp	r6, #0
    9bde:	d1f3      	bne.n	9bc8 <memcpy+0x28>
    9be0:	f01c 0403 	ands.w	r4, ip, #3
    9be4:	4663      	mov	r3, ip
    9be6:	bf08      	it	eq
    9be8:	ebc1 0c02 	rsbeq	ip, r1, r2
    9bec:	d068      	beq.n	9cc0 <memcpy+0x120>
    9bee:	4265      	negs	r5, r4
    9bf0:	f1c4 0a04 	rsb	sl, r4, #4
    9bf4:	eb0c 0705 	add.w	r7, ip, r5
    9bf8:	4633      	mov	r3, r6
    9bfa:	ea4f 0aca 	mov.w	sl, sl, lsl #3
    9bfe:	f85c 6005 	ldr.w	r6, [ip, r5]
    9c02:	ea4f 08c4 	mov.w	r8, r4, lsl #3
    9c06:	1a55      	subs	r5, r2, r1
    9c08:	e008      	b.n	9c1c <memcpy+0x7c>
    9c0a:	f857 4f04 	ldr.w	r4, [r7, #4]!
    9c0e:	4626      	mov	r6, r4
    9c10:	fa04 f40a 	lsl.w	r4, r4, sl
    9c14:	ea49 0404 	orr.w	r4, r9, r4
    9c18:	50cc      	str	r4, [r1, r3]
    9c1a:	3304      	adds	r3, #4
    9c1c:	185c      	adds	r4, r3, r1
    9c1e:	2d03      	cmp	r5, #3
    9c20:	fa26 f908 	lsr.w	r9, r6, r8
    9c24:	f1a5 0504 	sub.w	r5, r5, #4
    9c28:	eb0c 0603 	add.w	r6, ip, r3
    9c2c:	dced      	bgt.n	9c0a <memcpy+0x6a>
    9c2e:	2300      	movs	r3, #0
    9c30:	e002      	b.n	9c38 <memcpy+0x98>
    9c32:	5cf1      	ldrb	r1, [r6, r3]
    9c34:	54e1      	strb	r1, [r4, r3]
    9c36:	3301      	adds	r3, #1
    9c38:	1919      	adds	r1, r3, r4
    9c3a:	4291      	cmp	r1, r2
    9c3c:	d3f9      	bcc.n	9c32 <memcpy+0x92>
    9c3e:	e7bc      	b.n	9bba <memcpy+0x1a>
    9c40:	f853 4c40 	ldr.w	r4, [r3, #-64]
    9c44:	f841 4c40 	str.w	r4, [r1, #-64]
    9c48:	f853 4c3c 	ldr.w	r4, [r3, #-60]
    9c4c:	f841 4c3c 	str.w	r4, [r1, #-60]
    9c50:	f853 4c38 	ldr.w	r4, [r3, #-56]
    9c54:	f841 4c38 	str.w	r4, [r1, #-56]
    9c58:	f853 4c34 	ldr.w	r4, [r3, #-52]
    9c5c:	f841 4c34 	str.w	r4, [r1, #-52]
    9c60:	f853 4c30 	ldr.w	r4, [r3, #-48]
    9c64:	f841 4c30 	str.w	r4, [r1, #-48]
    9c68:	f853 4c2c 	ldr.w	r4, [r3, #-44]
    9c6c:	f841 4c2c 	str.w	r4, [r1, #-44]
    9c70:	f853 4c28 	ldr.w	r4, [r3, #-40]
    9c74:	f841 4c28 	str.w	r4, [r1, #-40]
    9c78:	f853 4c24 	ldr.w	r4, [r3, #-36]
    9c7c:	f841 4c24 	str.w	r4, [r1, #-36]
    9c80:	f853 4c20 	ldr.w	r4, [r3, #-32]
    9c84:	f841 4c20 	str.w	r4, [r1, #-32]
    9c88:	f853 4c1c 	ldr.w	r4, [r3, #-28]
    9c8c:	f841 4c1c 	str.w	r4, [r1, #-28]
    9c90:	f853 4c18 	ldr.w	r4, [r3, #-24]
    9c94:	f841 4c18 	str.w	r4, [r1, #-24]
    9c98:	f853 4c14 	ldr.w	r4, [r3, #-20]
    9c9c:	f841 4c14 	str.w	r4, [r1, #-20]
    9ca0:	f853 4c10 	ldr.w	r4, [r3, #-16]
    9ca4:	f841 4c10 	str.w	r4, [r1, #-16]
    9ca8:	f853 4c0c 	ldr.w	r4, [r3, #-12]
    9cac:	f841 4c0c 	str.w	r4, [r1, #-12]
    9cb0:	f853 4c08 	ldr.w	r4, [r3, #-8]
    9cb4:	f841 4c08 	str.w	r4, [r1, #-8]
    9cb8:	f853 4c04 	ldr.w	r4, [r3, #-4]
    9cbc:	f841 4c04 	str.w	r4, [r1, #-4]
    9cc0:	461c      	mov	r4, r3
    9cc2:	460d      	mov	r5, r1
    9cc4:	3340      	adds	r3, #64	; 0x40
    9cc6:	3140      	adds	r1, #64	; 0x40
    9cc8:	f1bc 0f3f 	cmp.w	ip, #63	; 0x3f
    9ccc:	f1ac 0c40 	sub.w	ip, ip, #64	; 0x40
    9cd0:	dcb6      	bgt.n	9c40 <memcpy+0xa0>
    9cd2:	4621      	mov	r1, r4
    9cd4:	462b      	mov	r3, r5
    9cd6:	1b54      	subs	r4, r2, r5
    9cd8:	e00f      	b.n	9cfa <memcpy+0x15a>
    9cda:	f851 5c10 	ldr.w	r5, [r1, #-16]
    9cde:	f843 5c10 	str.w	r5, [r3, #-16]
    9ce2:	f851 5c0c 	ldr.w	r5, [r1, #-12]
    9ce6:	f843 5c0c 	str.w	r5, [r3, #-12]
    9cea:	f851 5c08 	ldr.w	r5, [r1, #-8]
    9cee:	f843 5c08 	str.w	r5, [r3, #-8]
    9cf2:	f851 5c04 	ldr.w	r5, [r1, #-4]
    9cf6:	f843 5c04 	str.w	r5, [r3, #-4]
    9cfa:	2c0f      	cmp	r4, #15
    9cfc:	460d      	mov	r5, r1
    9cfe:	469c      	mov	ip, r3
    9d00:	f101 0110 	add.w	r1, r1, #16
    9d04:	f103 0310 	add.w	r3, r3, #16
    9d08:	f1a4 0410 	sub.w	r4, r4, #16
    9d0c:	dce5      	bgt.n	9cda <memcpy+0x13a>
    9d0e:	ebcc 0102 	rsb	r1, ip, r2
    9d12:	2300      	movs	r3, #0
    9d14:	e003      	b.n	9d1e <memcpy+0x17e>
    9d16:	58ec      	ldr	r4, [r5, r3]
    9d18:	f84c 4003 	str.w	r4, [ip, r3]
    9d1c:	3304      	adds	r3, #4
    9d1e:	195e      	adds	r6, r3, r5
    9d20:	2903      	cmp	r1, #3
    9d22:	eb03 040c 	add.w	r4, r3, ip
    9d26:	f1a1 0104 	sub.w	r1, r1, #4
    9d2a:	dcf4      	bgt.n	9d16 <memcpy+0x176>
    9d2c:	e77f      	b.n	9c2e <memcpy+0x8e>
    9d2e:	bf00      	nop

00009d30 <memset>:
    9d30:	2a03      	cmp	r2, #3
    9d32:	b2c9      	uxtb	r1, r1
    9d34:	b430      	push	{r4, r5}
    9d36:	d807      	bhi.n	9d48 <memset+0x18>
    9d38:	b122      	cbz	r2, 9d44 <memset+0x14>
    9d3a:	2300      	movs	r3, #0
    9d3c:	54c1      	strb	r1, [r0, r3]
    9d3e:	3301      	adds	r3, #1
    9d40:	4293      	cmp	r3, r2
    9d42:	d1fb      	bne.n	9d3c <memset+0xc>
    9d44:	bc30      	pop	{r4, r5}
    9d46:	4770      	bx	lr
    9d48:	eb00 0c02 	add.w	ip, r0, r2
    9d4c:	4603      	mov	r3, r0
    9d4e:	e001      	b.n	9d54 <memset+0x24>
    9d50:	f803 1c01 	strb.w	r1, [r3, #-1]
    9d54:	f003 0403 	and.w	r4, r3, #3
    9d58:	461a      	mov	r2, r3
    9d5a:	3301      	adds	r3, #1
    9d5c:	2c00      	cmp	r4, #0
    9d5e:	d1f7      	bne.n	9d50 <memset+0x20>
    9d60:	f04f 3301 	mov.w	r3, #16843009	; 0x1010101
    9d64:	ebc2 040c 	rsb	r4, r2, ip
    9d68:	fb03 f301 	mul.w	r3, r3, r1
    9d6c:	e01f      	b.n	9dae <memset+0x7e>
    9d6e:	f842 3c40 	str.w	r3, [r2, #-64]
    9d72:	f842 3c3c 	str.w	r3, [r2, #-60]
    9d76:	f842 3c38 	str.w	r3, [r2, #-56]
    9d7a:	f842 3c34 	str.w	r3, [r2, #-52]
    9d7e:	f842 3c30 	str.w	r3, [r2, #-48]
    9d82:	f842 3c2c 	str.w	r3, [r2, #-44]
    9d86:	f842 3c28 	str.w	r3, [r2, #-40]
    9d8a:	f842 3c24 	str.w	r3, [r2, #-36]
    9d8e:	f842 3c20 	str.w	r3, [r2, #-32]
    9d92:	f842 3c1c 	str.w	r3, [r2, #-28]
    9d96:	f842 3c18 	str.w	r3, [r2, #-24]
    9d9a:	f842 3c14 	str.w	r3, [r2, #-20]
    9d9e:	f842 3c10 	str.w	r3, [r2, #-16]
    9da2:	f842 3c0c 	str.w	r3, [r2, #-12]
    9da6:	f842 3c08 	str.w	r3, [r2, #-8]
    9daa:	f842 3c04 	str.w	r3, [r2, #-4]
    9dae:	4615      	mov	r5, r2
    9db0:	3240      	adds	r2, #64	; 0x40
    9db2:	2c3f      	cmp	r4, #63	; 0x3f
    9db4:	f1a4 0440 	sub.w	r4, r4, #64	; 0x40
    9db8:	dcd9      	bgt.n	9d6e <memset+0x3e>
    9dba:	462a      	mov	r2, r5
    9dbc:	ebc5 040c 	rsb	r4, r5, ip
    9dc0:	e007      	b.n	9dd2 <memset+0xa2>
    9dc2:	f842 3c10 	str.w	r3, [r2, #-16]
    9dc6:	f842 3c0c 	str.w	r3, [r2, #-12]
    9dca:	f842 3c08 	str.w	r3, [r2, #-8]
    9dce:	f842 3c04 	str.w	r3, [r2, #-4]
    9dd2:	4615      	mov	r5, r2
    9dd4:	3210      	adds	r2, #16
    9dd6:	2c0f      	cmp	r4, #15
    9dd8:	f1a4 0410 	sub.w	r4, r4, #16
    9ddc:	dcf1      	bgt.n	9dc2 <memset+0x92>
    9dde:	462a      	mov	r2, r5
    9de0:	ebc5 050c 	rsb	r5, r5, ip
    9de4:	e001      	b.n	9dea <memset+0xba>
    9de6:	f842 3c04 	str.w	r3, [r2, #-4]
    9dea:	4614      	mov	r4, r2
    9dec:	3204      	adds	r2, #4
    9dee:	2d03      	cmp	r5, #3
    9df0:	f1a5 0504 	sub.w	r5, r5, #4
    9df4:	dcf7      	bgt.n	9de6 <memset+0xb6>
    9df6:	e001      	b.n	9dfc <memset+0xcc>
    9df8:	f804 1b01 	strb.w	r1, [r4], #1
    9dfc:	4564      	cmp	r4, ip
    9dfe:	d3fb      	bcc.n	9df8 <memset+0xc8>
    9e00:	e7a0      	b.n	9d44 <memset+0x14>
    9e02:	bf00      	nop
    9e04:	00000073 	.word	0x00000073
    9e08:	00000064 	.word	0x00000064
    9e0c:	00000061 	.word	0x00000061
    9e10:	00000068 	.word	0x00000068
    9e14:	0000006b 	.word	0x0000006b
    9e18:	00000063 	.word	0x00000063
    9e1c:	00000070 	.word	0x00000070
    9e20:	00000076 	.word	0x00000076
    9e24:	00000079 	.word	0x00000079

00009e28 <C.94.4678>:
    9e28:	22ca87aa 37058bbe 1ec7b18e 74ad20f3     ..."...7..... .t
    9e38:	623b1d6e 989ba78b e041f759 382a5482     n.;b....Y.A..T*8
    9e48:	5df20255 6c2955bf 385e543a b70a7672     U..].U)l:T^8rv..
    9e58:	4ade1736 6f2c2696 bf989e5d 29dc9292     6..J.&,o]......)
    9e68:	bd1df4f8 7c149a28 1331dae9 c0b8f0b5     ....(..|..1.....
    9e78:	ceb1600a 9d817e1d 7c1d437a 5f0eea90     .`...~..zC.|..._

00009e88 <g_nvm>:
    9e88:	60080000 600c0000                       ...`...`

00009e90 <g_nvm32>:
    9e90:	60080000 600c0000                       ...`...`

00009e98 <g_config_reg_lut>:
    9e98:	40013000 40013004 40013008 4001300c     .0.@.0.@.0.@.0.@
    9ea8:	40013010 40013014 40013018 4001301c     .0.@.0.@.0.@.0.@
    9eb8:	40013020 40013024 40013028 4001302c      0.@$0.@(0.@,0.@
    9ec8:	40013030 40013034 40013038 4001303c     00.@40.@80.@<0.@
    9ed8:	40013040 40013044 40013048 4001304c     @0.@D0.@H0.@L0.@
    9ee8:	40013050 40013054 40013058 4001305c     P0.@T0.@X0.@\0.@
    9ef8:	40013060 40013064 40013068 4001306c     `0.@d0.@h0.@l0.@
    9f08:	40013070 40013074 40013078 4001307c     p0.@t0.@x0.@|0.@

00009f18 <g_gpio_irqn_lut>:
    9f18:	35343332 39383736 3d3c3b3a 41403f3e     23456789:;<=>?@A
    9f28:	45444342 49484746 4d4c4b4a 51504f4e     BCDEFGHIJKLMNOPQ

00009f38 <C.19.3551>:
    9f38:	01000100 03030202 70616548 646e6120     ........Heap and
    9f48:	61747320 63206b63 696c6c6f 6e6f6973      stack collision
    9f58:	0000000a 2074754f 6820666f 20706165     ....Out of heap 
    9f68:	6f6d656d 000a7972                       memory..

00009f70 <_global_impure_ptr>:
    9f70:	20000034 00000043                       4.. C...

00009f78 <_init>:
    9f78:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    9f7a:	bf00      	nop
    9f7c:	bcf8      	pop	{r3, r4, r5, r6, r7}
    9f7e:	bc08      	pop	{r3}
    9f80:	469e      	mov	lr, r3
    9f82:	4770      	bx	lr

00009f84 <_fini>:
    9f84:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    9f86:	bf00      	nop
    9f88:	bcf8      	pop	{r3, r4, r5, r6, r7}
    9f8a:	bc08      	pop	{r3}
    9f8c:	469e      	mov	lr, r3
    9f8e:	4770      	bx	lr

00009f90 <__frame_dummy_init_array_entry>:
    9f90:	0a75 0000                                   u...

00009f94 <__do_global_dtors_aux_fini_array_entry>:
    9f94:	0a61 0000 0000 0000 0000 0000               a...........
