pin,slack
MSS_ADLIB_INST/IP_INTERFACE_51:A,
MSS_ADLIB_INST/IP_INTERFACE_51:B,
MSS_ADLIB_INST/IP_INTERFACE_51:C,
MSS_ADLIB_INST/IP_INTERFACE_51:IPA,
MSS_ADLIB_INST/IP_INTERFACE_51:IPB,
MDDR_DDR_AXI_S_WSTRB_ibuf[6]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WSTRB_ibuf[6]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WID_ibuf[3]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WID_ibuf[3]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[19]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[19]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HRDATA_obuf[3]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[3]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[49]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[49]/U0/U_IOPAD:Y,
FIC_2_APB_M_PRDATA_ibuf[16]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[16]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HRDATA_obuf[27]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[27]/U0/U_IOOUTFF:Y,
FIC_2_APB_M_PRDATA_ibuf[22]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[22]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HRDATA_obuf[9]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[9]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[42]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[42]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARLEN_ibuf[2]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARLEN_ibuf[2]/U0/U_IOPAD:Y,
FIC_2_APB_M_PWDATA_obuf[26]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[26]/U0/U_IOENFF:Y,
FIC_2_APB_M_PWDATA_obuf[29]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[29]/U0/U_IOENFF:Y,
FIC_0_AHB_S_HRDATA_obuf[2]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[2]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_207:A,
MSS_ADLIB_INST/IP_INTERFACE_207:B,
MSS_ADLIB_INST/IP_INTERFACE_207:C,
MSS_ADLIB_INST/IP_INTERFACE_207:IPA,
MSS_ADLIB_INST/IP_INTERFACE_207:IPB,
MDDR_DDR_AXI_S_ARADDR_ibuf[14]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[14]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[51]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[51]/U0/U_IOINFF:Y,
MDDR_ADDR_7_PAD/U_IOPAD:D,
MDDR_ADDR_7_PAD/U_IOPAD:E,
MDDR_ADDR_7_PAD/U_IOPAD:PAD,
ip_interface_inst_2:A,
ip_interface_inst_2:B,
ip_interface_inst_2:C,
MDDR_DDR_AXI_S_RDATA_obuf[14]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[14]/U0/U_IOENFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[30]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[30]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HRDATA_obuf[19]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[19]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_122:A,
MSS_ADLIB_INST/IP_INTERFACE_122:B,
MSS_ADLIB_INST/IP_INTERFACE_122:C,
MSS_ADLIB_INST/IP_INTERFACE_122:IPA,
MSS_ADLIB_INST/IP_INTERFACE_122:IPB,
FIC_2_APB_M_PWDATA_obuf[4]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[4]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_348:A,
MSS_ADLIB_INST/IP_INTERFACE_348:B,
MSS_ADLIB_INST/IP_INTERFACE_348:C,
MSS_ADLIB_INST/IP_INTERFACE_348:IPA,
FIC_0_AHB_S_HWDATA_ibuf[15]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[15]/U0/U_IOINFF:Y,
SPI_0_SS0_PAD/U_IOINFF:A,
SPI_0_SS0_PAD/U_IOINFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[5]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[5]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_180:A,
MSS_ADLIB_INST/IP_INTERFACE_180:B,
MSS_ADLIB_INST/IP_INTERFACE_180:C,
MSS_ADLIB_INST/IP_INTERFACE_180:IPA,
MDDR_DDR_AXI_S_AWLEN_ibuf[1]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWLEN_ibuf[1]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HADDR_ibuf[15]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[15]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_AWREADY_obuf/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_AWREADY_obuf/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_361:A,
MSS_ADLIB_INST/IP_INTERFACE_361:B,
MSS_ADLIB_INST/IP_INTERFACE_361:C,
MSS_ADLIB_INST/IP_INTERFACE_361:IPB,
MDDR_APB_S_PRDATA_obuf[12]/U0/U_IOENFF:A,
MDDR_APB_S_PRDATA_obuf[12]/U0/U_IOENFF:Y,
FIC_0_AHB_S_HRDATA_obuf[10]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[10]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_345:A,
MSS_ADLIB_INST/IP_INTERFACE_345:B,
MSS_ADLIB_INST/IP_INTERFACE_345:C,
MSS_ADLIB_INST/IP_INTERFACE_345:IPA,
MSS_ADLIB_INST/IP_INTERFACE_345:IPB,
MDDR_DDR_AXI_S_ARADDR_ibuf[12]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[12]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[3]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[3]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[3]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HRDATA_obuf[18]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[18]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[24]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[24]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[43]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[43]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[43]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_84:A,
MSS_ADLIB_INST/IP_INTERFACE_84:B,
MSS_ADLIB_INST/IP_INTERFACE_84:C,
MSS_ADLIB_INST/IP_INTERFACE_84:IPA,
MDDR_DDR_AXI_S_WID_ibuf[2]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WID_ibuf[2]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARID_ibuf[2]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARID_ibuf[2]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HRDATA_obuf[13]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[13]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[13]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_209:A,
MSS_ADLIB_INST/IP_INTERFACE_209:B,
MSS_ADLIB_INST/IP_INTERFACE_209:C,
MSS_ADLIB_INST/IP_INTERFACE_209:IPA,
MSS_ADLIB_INST/IP_INTERFACE_209:IPB,
MSS_ADLIB_INST/IP_INTERFACE_197:A,
MSS_ADLIB_INST/IP_INTERFACE_197:B,
MSS_ADLIB_INST/IP_INTERFACE_197:C,
MSS_ADLIB_INST/IP_INTERFACE_197:IPA,
MSS_ADLIB_INST/IP_INTERFACE_197:IPB,
FIC_2_APB_M_PADDR_obuf[9]/U0/U_IOPAD:D,
FIC_2_APB_M_PADDR_obuf[9]/U0/U_IOPAD:E,
FIC_2_APB_M_PADDR_obuf[9]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PADDR_obuf[15]/U0/U_IOENFF:A,
FIC_2_APB_M_PADDR_obuf[15]/U0/U_IOENFF:Y,
MDDR_DQS_TMATCH_0_IN_PAD/U_IOINFF:A,
MDDR_DQS_TMATCH_0_IN_PAD/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[10]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[10]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[17]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[17]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[17]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_308:A,
MSS_ADLIB_INST/IP_INTERFACE_308:B,
MSS_ADLIB_INST/IP_INTERFACE_308:C,
MSS_ADLIB_INST/IP_INTERFACE_308:IPA,
MSS_ADLIB_INST/IP_INTERFACE_308:IPB,
MDDR_DDR_AXI_S_AWREADY_obuf/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_AWREADY_obuf/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_AWREADY_obuf/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RDATA_obuf[23]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[23]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[40]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[40]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[7]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[7]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[52]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[52]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[52]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[12]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[12]/U0/U_IOINFF:Y,
FIC_2_APB_M_PADDR_obuf[5]/U0/U_IOENFF:A,
FIC_2_APB_M_PADDR_obuf[5]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_257:A,
MSS_ADLIB_INST/IP_INTERFACE_257:B,
MSS_ADLIB_INST/IP_INTERFACE_257:C,
MSS_ADLIB_INST/IP_INTERFACE_257:IPA,
MSS_ADLIB_INST/IP_INTERFACE_257:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[56]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[56]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[37]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[37]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[37]/U0/U_IOPAD:PAD,
MDDR_DQ_2_PAD/U_IOINFF:A,
MDDR_DQ_2_PAD/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[41]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[41]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[51]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[51]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RID_obuf[2]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RID_obuf[2]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RID_obuf[2]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RDATA_obuf[25]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[25]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[25]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_2:A,
MSS_ADLIB_INST/IP_INTERFACE_2:B,
MSS_ADLIB_INST/IP_INTERFACE_2:C,
MSS_ADLIB_INST/IP_INTERFACE_2:IPA,
MSS_ADLIB_INST/IP_INTERFACE_2:IPB,
MDDR_DDR_AXI_S_AWADDR_ibuf[11]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[11]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_312:A,
MSS_ADLIB_INST/IP_INTERFACE_312:B,
MSS_ADLIB_INST/IP_INTERFACE_312:C,
MSS_ADLIB_INST/IP_INTERFACE_312:IPA,
FIC_2_APB_M_PRDATA_ibuf[24]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[24]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_305:A,
MSS_ADLIB_INST/IP_INTERFACE_305:B,
MSS_ADLIB_INST/IP_INTERFACE_305:C,
MSS_ADLIB_INST/IP_INTERFACE_305:IPA,
MSS_ADLIB_INST/IP_INTERFACE_305:IPB,
MSS_ADLIB_INST/IP_INTERFACE_226:A,
MSS_ADLIB_INST/IP_INTERFACE_226:B,
MSS_ADLIB_INST/IP_INTERFACE_226:C,
MSS_ADLIB_INST/IP_INTERFACE_226:IPB,
MDDR_DQ_0_PAD/U_IOPAD:D,
MDDR_DQ_0_PAD/U_IOPAD:E,
MDDR_DQ_0_PAD/U_IOPAD:PAD,
MDDR_DQ_0_PAD/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_80:A,
MSS_ADLIB_INST/IP_INTERFACE_80:B,
MSS_ADLIB_INST/IP_INTERFACE_80:C,
MSS_ADLIB_INST/IP_INTERFACE_80:IPA,
MSS_ADLIB_INST/IP_INTERFACE_80:IPB,
MDDR_APB_S_PRDATA_obuf[11]/U0/U_IOENFF:A,
MDDR_APB_S_PRDATA_obuf[11]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_BID_obuf[0]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_BID_obuf[0]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_BID_obuf[0]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HRDATA_obuf[24]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[24]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[24]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[11]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[11]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_93:A,
MSS_ADLIB_INST/IP_INTERFACE_93:B,
MSS_ADLIB_INST/IP_INTERFACE_93:C,
MSS_ADLIB_INST/IP_INTERFACE_93:IPA,
MSS_ADLIB_INST/IP_INTERFACE_93:IPB,
GPIO_1_M2F_obuf/U0/U_IOPAD:D,
GPIO_1_M2F_obuf/U0/U_IOPAD:E,
GPIO_1_M2F_obuf/U0/U_IOPAD:PAD,
FIC_2_APB_M_PWDATA_obuf[1]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[1]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_26:A,
MSS_ADLIB_INST/IP_INTERFACE_26:B,
MSS_ADLIB_INST/IP_INTERFACE_26:C,
MSS_ADLIB_INST/IP_INTERFACE_26:IPA,
MSS_ADLIB_INST/IP_INTERFACE_26:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[60]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[60]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HADDR_ibuf[27]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[27]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_235:A,
MSS_ADLIB_INST/IP_INTERFACE_235:B,
MSS_ADLIB_INST/IP_INTERFACE_235:C,
MSS_ADLIB_INST/IP_INTERFACE_235:IPA,
MSS_ADLIB_INST/IP_INTERFACE_235:IPB,
MSS_ADLIB_INST/IP_INTERFACE_178:A,
MSS_ADLIB_INST/IP_INTERFACE_178:B,
MSS_ADLIB_INST/IP_INTERFACE_178:C,
MSS_ADLIB_INST/IP_INTERFACE_178:IPB,
GPIO_1_M2F_obuf/U0/U_IOOUTFF:A,
GPIO_1_M2F_obuf/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_140:A,
MSS_ADLIB_INST/IP_INTERFACE_140:B,
MSS_ADLIB_INST/IP_INTERFACE_140:C,
MSS_ADLIB_INST/IP_INTERFACE_140:IPA,
MSS_ADLIB_INST/IP_INTERFACE_140:IPB,
MSS_ADLIB_INST/IP_INTERFACE_259:A,
MSS_ADLIB_INST/IP_INTERFACE_259:B,
MSS_ADLIB_INST/IP_INTERFACE_259:C,
MSS_ADLIB_INST/IP_INTERFACE_259:IPA,
MSS_ADLIB_INST/IP_INTERFACE_259:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[62]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[62]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[62]/U0/U_IOPAD:PAD,
MDDR_APB_S_PRDATA_obuf[0]/U0/U_IOENFF:A,
MDDR_APB_S_PRDATA_obuf[0]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[61]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[61]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_358:A,
MSS_ADLIB_INST/IP_INTERFACE_358:B,
MSS_ADLIB_INST/IP_INTERFACE_358:C,
MSS_ADLIB_INST/IP_INTERFACE_358:IPB,
MSS_ADLIB_INST/IP_INTERFACE_381:A,
MSS_ADLIB_INST/IP_INTERFACE_381:B,
MSS_ADLIB_INST/IP_INTERFACE_381:C,
MSS_ADLIB_INST/IP_INTERFACE_381:IPA,
MSS_ADLIB_INST/IP_INTERFACE_381:IPB,
MDDR_RESET_N_PAD/U_IOPAD:D,
MDDR_RESET_N_PAD/U_IOPAD:E,
MDDR_RESET_N_PAD/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[58]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[58]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[45]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[45]/U0/U_IOINFF:Y,
FIC_2_APB_M_PRDATA_ibuf[12]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[12]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_165:A,
MSS_ADLIB_INST/IP_INTERFACE_165:B,
MSS_ADLIB_INST/IP_INTERFACE_165:C,
MSS_ADLIB_INST/IP_INTERFACE_165:IPA,
MSS_ADLIB_INST/IP_INTERFACE_165:IPB,
MDDR_APB_S_PRDATA_obuf[8]/U0/U_IOPAD:D,
MDDR_APB_S_PRDATA_obuf[8]/U0/U_IOPAD:E,
MDDR_APB_S_PRDATA_obuf[8]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PWDATA_obuf[16]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[16]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[19]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[19]/U0/U_IOPAD:Y,
FIC_2_APB_M_PWDATA_obuf[19]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[19]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_347:A,
MSS_ADLIB_INST/IP_INTERFACE_347:B,
MSS_ADLIB_INST/IP_INTERFACE_347:C,
MSS_ADLIB_INST/IP_INTERFACE_347:IPB,
MDDR_APB_S_PRESET_N_ibuf/U0/U_IOPAD:PAD,
MDDR_APB_S_PRESET_N_ibuf/U0/U_IOPAD:Y,
FIC_2_APB_M_PWDATA_obuf[28]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[28]/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HRDATA_obuf[15]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[15]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[15]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_179:A,
MSS_ADLIB_INST/IP_INTERFACE_179:B,
MSS_ADLIB_INST/IP_INTERFACE_179:C,
MSS_ADLIB_INST/IP_INTERFACE_179:IPB,
MSS_ADLIB_INST/IP_INTERFACE_355:A,
MSS_ADLIB_INST/IP_INTERFACE_355:B,
MSS_ADLIB_INST/IP_INTERFACE_355:C,
MSS_ADLIB_INST/IP_INTERFACE_355:IPA,
FIC_0_AHB_S_HRDATA_obuf[17]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[17]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[30]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[30]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_BID_obuf[0]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_BID_obuf[0]/U0/U_IOOUTFF:Y,
MDDR_CLK_PAD/U_IOPADN:EIN_P,
MDDR_CLK_PAD/U_IOPADN:OIN_P,
MDDR_CLK_PAD/U_IOPADN:PAD_P,
MSS_ADLIB_INST/IP_INTERFACE_85:A,
MSS_ADLIB_INST/IP_INTERFACE_85:B,
MSS_ADLIB_INST/IP_INTERFACE_85:C,
MSS_ADLIB_INST/IP_INTERFACE_85:IPA,
MSS_ADLIB_INST/IP_INTERFACE_212:A,
MSS_ADLIB_INST/IP_INTERFACE_212:B,
MSS_ADLIB_INST/IP_INTERFACE_212:C,
MSS_ADLIB_INST/IP_INTERFACE_212:IPA,
MSS_ADLIB_INST/IP_INTERFACE_212:IPB,
MSS_ADLIB_INST/IP_INTERFACE_100:A,
MSS_ADLIB_INST/IP_INTERFACE_100:B,
MSS_ADLIB_INST/IP_INTERFACE_100:C,
MSS_ADLIB_INST/IP_INTERFACE_100:IPA,
MSS_ADLIB_INST/IP_INTERFACE_100:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[31]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[31]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[25]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[25]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_AWLOCK_ibuf[0]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWLOCK_ibuf[0]/U0/U_IOPAD:Y,
FIC_2_APB_M_PWDATA_obuf[9]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[9]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[26]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[26]/U0/U_IOPAD:Y,
FIC_2_APB_M_PADDR_obuf[10]/U0/U_IOPAD:D,
FIC_2_APB_M_PADDR_obuf[10]/U0/U_IOPAD:E,
FIC_2_APB_M_PADDR_obuf[10]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RDATA_obuf[44]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[44]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[44]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WSTRB_ibuf[7]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WSTRB_ibuf[7]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[28]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[28]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WSTRB_ibuf[0]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WSTRB_ibuf[0]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[8]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[8]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_BID_obuf[1]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_BID_obuf[1]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_BID_obuf[1]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARLOCK_ibuf[0]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARLOCK_ibuf[0]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_37:A,
MSS_ADLIB_INST/IP_INTERFACE_37:B,
MSS_ADLIB_INST/IP_INTERFACE_37:C,
MSS_ADLIB_INST/IP_INTERFACE_37:IPA,
MDDR_DDR_AXI_S_RDATA_obuf[60]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[60]/U0/U_IOENFF:Y,
FIC_2_APB_M_PWDATA_obuf[23]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[23]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[23]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_307:A,
MSS_ADLIB_INST/IP_INTERFACE_307:B,
MSS_ADLIB_INST/IP_INTERFACE_307:C,
MSS_ADLIB_INST/IP_INTERFACE_307:IPA,
MSS_ADLIB_INST/IP_INTERFACE_307:IPB,
FIC_2_APB_M_PWDATA_obuf[16]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[16]/U0/U_IOOUTFF:Y,
MDDR_APB_S_PWDATA_ibuf[2]/U0/U_IOPAD:PAD,
MDDR_APB_S_PWDATA_ibuf[2]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[1]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[1]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[16]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[16]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[5]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[5]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HRDATA_obuf[4]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[4]/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HADDR_ibuf[28]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[28]/U0/U_IOPAD:Y,
FIC_2_APB_M_PWDATA_obuf[8]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[8]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_323:A,
MSS_ADLIB_INST/IP_INTERFACE_323:B,
MSS_ADLIB_INST/IP_INTERFACE_323:C,
MSS_ADLIB_INST/IP_INTERFACE_323:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[24]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[24]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[9]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[9]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HRDATA_obuf[26]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[26]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[26]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[21]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[21]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_28:A,
MSS_ADLIB_INST/IP_INTERFACE_28:B,
MSS_ADLIB_INST/IP_INTERFACE_28:C,
MSS_ADLIB_INST/IP_INTERFACE_28:IPA,
MSS_ADLIB_INST/IP_INTERFACE_28:IPB,
FIC_2_APB_M_PADDR_obuf[5]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PADDR_obuf[5]/U0/U_IOOUTFF:Y,
MDDR_APB_S_PRDATA_obuf[10]/U0/U_IOENFF:A,
MDDR_APB_S_PRDATA_obuf[10]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_341:A,
MSS_ADLIB_INST/IP_INTERFACE_341:B,
MSS_ADLIB_INST/IP_INTERFACE_341:C,
MSS_ADLIB_INST/IP_INTERFACE_341:IPA,
MSS_ADLIB_INST/IP_INTERFACE_341:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[11]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[11]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_99:A,
MSS_ADLIB_INST/IP_INTERFACE_99:B,
MSS_ADLIB_INST/IP_INTERFACE_99:C,
MSS_ADLIB_INST/IP_INTERFACE_99:IPA,
MSS_ADLIB_INST/IP_INTERFACE_99:IPB,
MSS_ADLIB_INST/IP_INTERFACE_237:A,
MSS_ADLIB_INST/IP_INTERFACE_237:B,
MSS_ADLIB_INST/IP_INTERFACE_237:C,
MSS_ADLIB_INST/IP_INTERFACE_237:IPA,
MSS_ADLIB_INST/IP_INTERFACE_237:IPB,
MSS_ADLIB_INST/IP_INTERFACE_150:A,
MSS_ADLIB_INST/IP_INTERFACE_150:B,
MSS_ADLIB_INST/IP_INTERFACE_150:C,
MSS_ADLIB_INST/IP_INTERFACE_150:IPA,
MSS_ADLIB_INST/IP_INTERFACE_150:IPB,
FIC_2_APB_M_PWDATA_obuf[21]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[21]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_77:A,
MSS_ADLIB_INST/IP_INTERFACE_77:B,
MSS_ADLIB_INST/IP_INTERFACE_77:C,
MSS_ADLIB_INST/IP_INTERFACE_77:IPA,
MSS_ADLIB_INST/IP_INTERFACE_77:IPB,
MSS_ADLIB_INST/IP_INTERFACE_185:A,
MSS_ADLIB_INST/IP_INTERFACE_185:B,
MSS_ADLIB_INST/IP_INTERFACE_185:C,
MSS_ADLIB_INST/IP_INTERFACE_185:IPA,
MSS_ADLIB_INST/IP_INTERFACE_185:IPB,
FIC_2_APB_M_PADDR_obuf[9]/U0/U_IOENFF:A,
FIC_2_APB_M_PADDR_obuf[9]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_163:A,
MSS_ADLIB_INST/IP_INTERFACE_163:B,
MSS_ADLIB_INST/IP_INTERFACE_163:C,
MSS_ADLIB_INST/IP_INTERFACE_163:IPA,
MSS_ADLIB_INST/IP_INTERFACE_163:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[49]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[49]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_4:A,
MSS_ADLIB_INST/IP_INTERFACE_4:B,
MSS_ADLIB_INST/IP_INTERFACE_4:C,
MSS_ADLIB_INST/IP_INTERFACE_4:IPA,
MSS_ADLIB_INST/IP_INTERFACE_4:IPB,
FIC_2_APB_M_PREADY_ibuf/U0/U_IOINFF:A,
FIC_2_APB_M_PREADY_ibuf/U0/U_IOINFF:Y,
FIC_2_APB_M_PRDATA_ibuf[18]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[18]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_295:A,
MSS_ADLIB_INST/IP_INTERFACE_295:B,
MSS_ADLIB_INST/IP_INTERFACE_295:C,
MSS_ADLIB_INST/IP_INTERFACE_295:IPA,
MSS_ADLIB_INST/IP_INTERFACE_295:IPB,
MSS_ADLIB_INST/IP_INTERFACE_224:A,
MSS_ADLIB_INST/IP_INTERFACE_224:B,
MSS_ADLIB_INST/IP_INTERFACE_224:C,
MSS_ADLIB_INST/IP_INTERFACE_224:IPA,
MSS_ADLIB_INST/IP_INTERFACE_224:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[5]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[5]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_357:A,
MSS_ADLIB_INST/IP_INTERFACE_357:B,
MSS_ADLIB_INST/IP_INTERFACE_357:C,
MSS_ADLIB_INST/IP_INTERFACE_357:IPA,
MSS_ADLIB_INST/IP_INTERFACE_357:IPB,
FIC_0_AHB_S_HWDATA_ibuf[30]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[30]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_319:A,
MSS_ADLIB_INST/IP_INTERFACE_319:B,
MSS_ADLIB_INST/IP_INTERFACE_319:C,
MSS_ADLIB_INST/IP_INTERFACE_319:IPA,
MSS_ADLIB_INST/IP_INTERFACE_319:IPB,
MDDR_DDR_AXI_S_RRESP_obuf[1]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RRESP_obuf[1]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RRESP_obuf[1]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RDATA_obuf[29]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[29]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[29]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARBURST_ibuf[0]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARBURST_ibuf[0]/U0/U_IOINFF:Y,
FIC_2_APB_M_PWDATA_obuf[6]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[6]/U0/U_IOENFF:Y,
MDDR_DQ_9_PAD/U_IOPAD:D,
MDDR_DQ_9_PAD/U_IOPAD:E,
MDDR_DQ_9_PAD/U_IOPAD:PAD,
MDDR_DQ_9_PAD/U_IOPAD:Y,
MDDR_APB_S_PWDATA_ibuf[10]/U0/U_IOPAD:PAD,
MDDR_APB_S_PWDATA_ibuf[10]/U0/U_IOPAD:Y,
FIC_2_APB_M_PRDATA_ibuf[4]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[4]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[63]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[63]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_301:A,
MSS_ADLIB_INST/IP_INTERFACE_301:B,
MSS_ADLIB_INST/IP_INTERFACE_301:C,
MSS_ADLIB_INST/IP_INTERFACE_301:IPA,
MSS_ADLIB_INST/IP_INTERFACE_301:IPB,
MDDR_DDR_AXI_S_ARADDR_ibuf[24]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[24]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[12]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[12]/U0/U_IOINFF:Y,
MDDR_APB_S_PRDATA_obuf[13]/U0/U_IOOUTFF:A,
MDDR_APB_S_PRDATA_obuf[13]/U0/U_IOOUTFF:Y,
FIC_2_APB_M_PWDATA_obuf[20]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[20]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[20]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PADDR_obuf[9]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PADDR_obuf[9]/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[4]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[4]/U0/U_IOPAD:Y,
GPIO_12_F2M_ibuf/U0/U_IOINFF:A,
GPIO_12_F2M_ibuf/U0/U_IOINFF:Y,
FIC_2_APB_M_PRDATA_ibuf[20]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[20]/U0/U_IOINFF:Y,
FIC_2_APB_M_PADDR_obuf[16]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PADDR_obuf[16]/U0/U_IOOUTFF:Y,
FIC_2_APB_M_PWDATA_obuf[5]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[5]/U0/U_IOOUTFF:Y,
FIC_2_APB_M_PWDATA_obuf[15]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[15]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_46:A,
MSS_ADLIB_INST/IP_INTERFACE_46:B,
MSS_ADLIB_INST/IP_INTERFACE_46:C,
MSS_ADLIB_INST/IP_INTERFACE_46:IPB,
MDDR_DDR_AXI_S_ARADDR_ibuf[28]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[28]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_239:A,
MSS_ADLIB_INST/IP_INTERFACE_239:B,
MSS_ADLIB_INST/IP_INTERFACE_239:C,
MSS_ADLIB_INST/IP_INTERFACE_239:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[60]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[60]/U0/U_IOOUTFF:Y,
FIC_2_APB_M_PRDATA_ibuf[1]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[1]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[61]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[61]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_338:A,
MSS_ADLIB_INST/IP_INTERFACE_338:B,
MSS_ADLIB_INST/IP_INTERFACE_338:C,
MSS_ADLIB_INST/IP_INTERFACE_338:IPA,
MSS_ADLIB_INST/IP_INTERFACE_338:IPB,
FIC_0_AHB_S_HRDATA_obuf[29]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[29]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[10]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[10]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_11:A,
MSS_ADLIB_INST/IP_INTERFACE_11:B,
MSS_ADLIB_INST/IP_INTERFACE_11:C,
MSS_ADLIB_INST/IP_INTERFACE_11:IPB,
FIC_0_AHB_S_HRDATA_obuf[21]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[21]/U0/U_IOOUTFF:Y,
MMUART_0_RXD_PAD/U_IOINFF:A,
MMUART_0_RXD_PAD/U_IOINFF:Y,
FIC_2_APB_M_PSEL_obuf/U0/U_IOPAD:D,
FIC_2_APB_M_PSEL_obuf/U0/U_IOPAD:E,
FIC_2_APB_M_PSEL_obuf/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_24:A,
MSS_ADLIB_INST/IP_INTERFACE_24:B,
MSS_ADLIB_INST/IP_INTERFACE_24:C,
MSS_ADLIB_INST/IP_INTERFACE_24:IPA,
MDDR_DDR_AXI_S_WDATA_ibuf[56]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[56]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HWDATA_ibuf[9]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[9]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[1]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[1]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_335:A,
MSS_ADLIB_INST/IP_INTERFACE_335:B,
MSS_ADLIB_INST/IP_INTERFACE_335:C,
MSS_ADLIB_INST/IP_INTERFACE_335:IPB,
MDDR_DDR_AXI_S_ARADDR_ibuf[16]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[16]/U0/U_IOINFF:Y,
FIC_2_APB_M_PADDR_obuf[14]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PADDR_obuf[14]/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[29]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[29]/U0/U_IOINFF:Y,
MDDR_DQ_15_PAD/U_IOPAD:D,
MDDR_DQ_15_PAD/U_IOPAD:E,
MDDR_DQ_15_PAD/U_IOPAD:PAD,
MDDR_DQ_15_PAD/U_IOPAD:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[27]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[27]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_83:A,
MSS_ADLIB_INST/IP_INTERFACE_83:B,
MSS_ADLIB_INST/IP_INTERFACE_83:C,
MSS_ADLIB_INST/IP_INTERFACE_83:IPB,
MDDR_DQS_0_PAD/U_IOPADN:EIN_P,
MDDR_DQS_0_PAD/U_IOPADN:N2POUT_P,
MDDR_DQS_0_PAD/U_IOPADN:OIN_P,
MDDR_DQS_0_PAD/U_IOPADN:PAD_P,
MDDR_DDR_AXI_S_RLAST_obuf/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RLAST_obuf/U0/U_IOOUTFF:Y,
MDDR_APB_S_PRDATA_obuf[5]/U0/U_IOPAD:D,
MDDR_APB_S_PRDATA_obuf[5]/U0/U_IOPAD:E,
MDDR_APB_S_PRDATA_obuf[5]/U0/U_IOPAD:PAD,
GPIO_3_M2F_obuf/U0/U_IOPAD:D,
GPIO_3_M2F_obuf/U0/U_IOPAD:E,
GPIO_3_M2F_obuf/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_145:A,
MSS_ADLIB_INST/IP_INTERFACE_145:B,
MSS_ADLIB_INST/IP_INTERFACE_145:C,
MSS_ADLIB_INST/IP_INTERFACE_145:IPA,
MDDR_DDR_AXI_S_RDATA_obuf[11]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[11]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[11]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HRDATA_obuf[6]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[6]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[6]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_351:A,
MSS_ADLIB_INST/IP_INTERFACE_351:B,
MSS_ADLIB_INST/IP_INTERFACE_351:C,
MSS_ADLIB_INST/IP_INTERFACE_351:IPA,
MSS_ADLIB_INST/IP_INTERFACE_183:A,
MSS_ADLIB_INST/IP_INTERFACE_183:B,
MSS_ADLIB_INST/IP_INTERFACE_183:C,
MSS_ADLIB_INST/IP_INTERFACE_183:IPA,
MSS_ADLIB_INST/IP_INTERFACE_183:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[31]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[31]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[31]/U0/U_IOPAD:PAD,
MDDR_APB_S_PADDR_ibuf[2]/U0/U_IOPAD:PAD,
MDDR_APB_S_PADDR_ibuf[2]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_324:A,
MSS_ADLIB_INST/IP_INTERFACE_324:B,
MSS_ADLIB_INST/IP_INTERFACE_324:C,
MSS_ADLIB_INST/IP_INTERFACE_324:IPA,
SPI_0_CLK_PAD/U_IOPAD:D,
SPI_0_CLK_PAD/U_IOPAD:E,
SPI_0_CLK_PAD/U_IOPAD:PAD,
SPI_0_CLK_PAD/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_20:A,
MSS_ADLIB_INST/IP_INTERFACE_20:B,
MSS_ADLIB_INST/IP_INTERFACE_20:C,
MSS_ADLIB_INST/IP_INTERFACE_20:IPA,
MSS_ADLIB_INST/IP_INTERFACE_20:IPB,
FIC_2_APB_M_PADDR_obuf[4]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PADDR_obuf[4]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[59]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[59]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[29]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[29]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_297:A,
MSS_ADLIB_INST/IP_INTERFACE_297:B,
MSS_ADLIB_INST/IP_INTERFACE_297:C,
MSS_ADLIB_INST/IP_INTERFACE_297:IPA,
MSS_ADLIB_INST/IP_INTERFACE_297:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[2]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[2]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[2]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_162:A,
MSS_ADLIB_INST/IP_INTERFACE_162:B,
MSS_ADLIB_INST/IP_INTERFACE_162:C,
MSS_ADLIB_INST/IP_INTERFACE_162:IPA,
MSS_ADLIB_INST/IP_INTERFACE_162:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[17]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[17]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_105:A,
MSS_ADLIB_INST/IP_INTERFACE_105:B,
MSS_ADLIB_INST/IP_INTERFACE_105:C,
MSS_ADLIB_INST/IP_INTERFACE_105:IPA,
MSS_ADLIB_INST/IP_INTERFACE_105:IPB,
MDDR_DDR_AXI_S_AWADDR_ibuf[14]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[14]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[37]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[37]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HWDATA_ibuf[17]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[17]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[4]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[4]/U0/U_IOPAD:Y,
FIC_2_APB_M_PWDATA_obuf[11]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[11]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_48:A,
MSS_ADLIB_INST/IP_INTERFACE_48:B,
MSS_ADLIB_INST/IP_INTERFACE_48:C,
MSS_ADLIB_INST/IP_INTERFACE_48:IPA,
MSS_ADLIB_INST/IP_INTERFACE_218:A,
MSS_ADLIB_INST/IP_INTERFACE_218:B,
MSS_ADLIB_INST/IP_INTERFACE_218:C,
MSS_ADLIB_INST/IP_INTERFACE_218:IPA,
MSS_ADLIB_INST/IP_INTERFACE_218:IPB,
FIC_2_APB_M_PWDATA_obuf[15]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[15]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[15]/U0/U_IOPAD:PAD,
MDDR_APB_S_PWRITE_ibuf/U0/U_IOPAD:PAD,
MDDR_APB_S_PWRITE_ibuf/U0/U_IOPAD:Y,
MDDR_APB_S_PRDATA_obuf[6]/U0/U_IOOUTFF:A,
MDDR_APB_S_PRDATA_obuf[6]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[3]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[3]/U0/U_IOINFF:Y,
GPIO_8_M2F_obuf/U0/U_IOENFF:A,
GPIO_8_M2F_obuf/U0/U_IOENFF:Y,
FIC_0_AHB_S_HADDR_ibuf[0]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[0]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[9]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[9]/U0/U_IOPAD:Y,
MCCC_CLK_BASE_PLL_LOCK_ibuf/U0/U_IOINFF:A,
MCCC_CLK_BASE_PLL_LOCK_ibuf/U0/U_IOINFF:Y,
MDDR_APB_S_PRDATA_obuf[9]/U0/U_IOENFF:A,
MDDR_APB_S_PRDATA_obuf[9]/U0/U_IOENFF:Y,
GPIO_12_F2M_ibuf/U0/U_IOPAD:PAD,
GPIO_12_F2M_ibuf/U0/U_IOPAD:Y,
FIC_2_APB_M_PRDATA_ibuf[13]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[13]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_130:A,
MSS_ADLIB_INST/IP_INTERFACE_130:B,
MSS_ADLIB_INST/IP_INTERFACE_130:C,
MSS_ADLIB_INST/IP_INTERFACE_130:IPB,
MDDR_DDR_AXI_S_RID_obuf[3]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RID_obuf[3]/U0/U_IOENFF:Y,
FIC_2_APB_M_PADDR_obuf[7]/U0/U_IOPAD:D,
FIC_2_APB_M_PADDR_obuf[7]/U0/U_IOPAD:E,
FIC_2_APB_M_PADDR_obuf[7]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[16]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[16]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_61:A,
MSS_ADLIB_INST/IP_INTERFACE_61:B,
MSS_ADLIB_INST/IP_INTERFACE_61:C,
MSS_ADLIB_INST/IP_INTERFACE_61:IPA,
MSS_ADLIB_INST/IP_INTERFACE_337:A,
MSS_ADLIB_INST/IP_INTERFACE_337:B,
MSS_ADLIB_INST/IP_INTERFACE_337:C,
MSS_ADLIB_INST/IP_INTERFACE_337:IPA,
MSS_ADLIB_INST/IP_INTERFACE_337:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[15]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[15]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_299:A,
MSS_ADLIB_INST/IP_INTERFACE_299:B,
MSS_ADLIB_INST/IP_INTERFACE_299:C,
MSS_ADLIB_INST/IP_INTERFACE_299:IPB,
MSS_ADLIB_INST/IP_INTERFACE_25:A,
MSS_ADLIB_INST/IP_INTERFACE_25:B,
MSS_ADLIB_INST/IP_INTERFACE_25:C,
MSS_ADLIB_INST/IP_INTERFACE_25:IPA,
MDDR_DDR_AXI_S_RID_obuf[0]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RID_obuf[0]/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HTRANS_ibuf[1]/U0/U_IOINFF:A,
FIC_0_AHB_S_HTRANS_ibuf[1]/U0/U_IOINFF:Y,
FIC_2_APB_M_PRDATA_ibuf[10]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[10]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[21]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[21]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[15]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[15]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[24]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[24]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_143:A,
MSS_ADLIB_INST/IP_INTERFACE_143:B,
MSS_ADLIB_INST/IP_INTERFACE_143:C,
MSS_ADLIB_INST/IP_INTERFACE_143:IPB,
MSS_ADLIB_INST/IP_INTERFACE_266:A,
MSS_ADLIB_INST/IP_INTERFACE_266:B,
MSS_ADLIB_INST/IP_INTERFACE_266:C,
MSS_ADLIB_INST/IP_INTERFACE_266:IPA,
MSS_ADLIB_INST/IP_INTERFACE_266:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[40]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[40]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RRESP_obuf[0]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RRESP_obuf[0]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RRESP_obuf[0]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_155:A,
MSS_ADLIB_INST/IP_INTERFACE_155:B,
MSS_ADLIB_INST/IP_INTERFACE_155:C,
MSS_ADLIB_INST/IP_INTERFACE_155:IPB,
FIC_2_APB_M_PWDATA_obuf[14]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[14]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[14]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RDATA_obuf[6]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[6]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[7]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[7]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[20]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[20]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_89:A,
MSS_ADLIB_INST/IP_INTERFACE_89:B,
MSS_ADLIB_INST/IP_INTERFACE_89:C,
MSS_ADLIB_INST/IP_INTERFACE_89:IPA,
MSS_ADLIB_INST/IP_INTERFACE_89:IPB,
FIC_0_AHB_S_HRESP_obuf/U0/U_IOPAD:D,
FIC_0_AHB_S_HRESP_obuf/U0/U_IOPAD:E,
FIC_0_AHB_S_HRESP_obuf/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[19]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[19]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HADDR_ibuf[16]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[16]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[9]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[9]/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HWRITE_ibuf/U0/U_IOINFF:A,
FIC_0_AHB_S_HWRITE_ibuf/U0/U_IOINFF:Y,
FIC_0_AHB_S_HRDATA_obuf[30]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[30]/U0/U_IOENFF:Y,
FIC_2_APB_M_PADDR_obuf[6]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PADDR_obuf[6]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_182:A,
MSS_ADLIB_INST/IP_INTERFACE_182:B,
MSS_ADLIB_INST/IP_INTERFACE_182:C,
MSS_ADLIB_INST/IP_INTERFACE_182:IPA,
MSS_ADLIB_INST/IP_INTERFACE_182:IPB,
GPIO_0_M2F_obuf/U0/U_IOOUTFF:A,
GPIO_0_M2F_obuf/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HADDR_ibuf[9]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[9]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[22]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[22]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_103:A,
MSS_ADLIB_INST/IP_INTERFACE_103:B,
MSS_ADLIB_INST/IP_INTERFACE_103:C,
MSS_ADLIB_INST/IP_INTERFACE_103:IPA,
MSS_ADLIB_INST/IP_INTERFACE_103:IPB,
MDDR_DDR_AXI_S_RLAST_obuf/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RLAST_obuf/U0/U_IOENFF:Y,
MDDR_APB_S_PENABLE_ibuf/U0/U_IOPAD:PAD,
MDDR_APB_S_PENABLE_ibuf/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[22]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[22]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_44:A,
MSS_ADLIB_INST/IP_INTERFACE_44:B,
MSS_ADLIB_INST/IP_INTERFACE_44:C,
MSS_ADLIB_INST/IP_INTERFACE_44:IPA,
MSS_ADLIB_INST/IP_INTERFACE_44:IPB,
FIC_2_APB_M_PRDATA_ibuf[2]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[2]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_111:A,
MSS_ADLIB_INST/IP_INTERFACE_111:B,
MSS_ADLIB_INST/IP_INTERFACE_111:C,
MSS_ADLIB_INST/IP_INTERFACE_111:IPA,
MSS_ADLIB_INST/IP_INTERFACE_111:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[50]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[50]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[20]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[20]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[3]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[3]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[33]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[33]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[51]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[51]/U0/U_IOOUTFF:Y,
MDDR_DQ_8_PAD/U_IOPAD:D,
MDDR_DQ_8_PAD/U_IOPAD:E,
MDDR_DQ_8_PAD/U_IOPAD:PAD,
MDDR_DQ_8_PAD/U_IOPAD:Y,
FIC_0_AHB_S_HRDATA_obuf[31]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[31]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[31]/U0/U_IOPAD:PAD,
MDDR_CLK_PAD/U_IOP:YIN,
MDDR_DDR_AXI_S_RDATA_obuf[40]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[40]/U0/U_IOENFF:Y,
MDDR_APB_S_PADDR_ibuf[4]/U0/U_IOINFF:A,
MDDR_APB_S_PADDR_ibuf[4]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_331:A,
MSS_ADLIB_INST/IP_INTERFACE_331:B,
MSS_ADLIB_INST/IP_INTERFACE_331:C,
MSS_ADLIB_INST/IP_INTERFACE_331:IPA,
MSS_ADLIB_INST/IP_INTERFACE_331:IPB,
MDDR_DDR_AXI_S_AWADDR_ibuf[22]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[22]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HRESP_obuf/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRESP_obuf/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_BVALID_obuf/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_BVALID_obuf/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_BVALID_obuf/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWBURST_ibuf[0]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWBURST_ibuf[0]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HWDATA_ibuf[24]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[24]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[21]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[21]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[47]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[47]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_40:A,
MSS_ADLIB_INST/IP_INTERFACE_40:B,
MSS_ADLIB_INST/IP_INTERFACE_40:C,
MSS_ADLIB_INST/IP_INTERFACE_40:IPA,
MSS_ADLIB_INST/IP_INTERFACE_40:IPB,
MSS_ADLIB_INST/IP_INTERFACE_177:A,
MSS_ADLIB_INST/IP_INTERFACE_177:B,
MSS_ADLIB_INST/IP_INTERFACE_177:C,
MSS_ADLIB_INST/IP_INTERFACE_177:IPA,
MSS_ADLIB_INST/IP_INTERFACE_177:IPB,
FIC_0_AHB_S_HADDR_ibuf[20]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[20]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[27]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[27]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[27]/U0/U_IOPAD:PAD,
MDDR_APB_S_PREADY_obuf/U0/U_IOPAD:D,
MDDR_APB_S_PREADY_obuf/U0/U_IOPAD:E,
MDDR_APB_S_PREADY_obuf/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RDATA_obuf[48]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[48]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[48]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[12]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[12]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[48]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[48]/U0/U_IOPAD:Y,
flash_freeze_inst/INST_FLASH_FREEZE_IP:FF_TO_START,
FIC_0_AHB_S_HRDATA_obuf[1]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[1]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[19]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[19]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_190:A,
MSS_ADLIB_INST/IP_INTERFACE_190:B,
MSS_ADLIB_INST/IP_INTERFACE_190:C,
MSS_ADLIB_INST/IP_INTERFACE_190:IPB,
MDDR_DDR_AXI_S_ARADDR_ibuf[31]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[31]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[11]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[11]/U0/U_IOPAD:Y,
FIC_2_APB_M_PRDATA_ibuf[12]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[12]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HRDATA_obuf[0]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[0]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[0]/U0/U_IOPAD:PAD,
MDDR_DQ_6_PAD/U_IOINFF:A,
MDDR_DQ_6_PAD/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_286:A,
MSS_ADLIB_INST/IP_INTERFACE_286:B,
MSS_ADLIB_INST/IP_INTERFACE_286:C,
MSS_ADLIB_INST/IP_INTERFACE_286:IPB,
MDDR_DDR_AXI_S_AWLOCK_ibuf[0]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWLOCK_ibuf[0]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[19]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[19]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_153:A,
MSS_ADLIB_INST/IP_INTERFACE_153:B,
MSS_ADLIB_INST/IP_INTERFACE_153:C,
MSS_ADLIB_INST/IP_INTERFACE_153:IPA,
MSS_ADLIB_INST/IP_INTERFACE_153:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[42]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[42]/U0/U_IOPAD:Y,
MDDR_APB_S_PRDATA_obuf[8]/U0/U_IOOUTFF:A,
MDDR_APB_S_PRDATA_obuf[8]/U0/U_IOOUTFF:Y,
FIC_2_APB_M_PADDR_obuf[2]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PADDR_obuf[2]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[27]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[27]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HRDATA_obuf[23]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[23]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_363:A,
MSS_ADLIB_INST/IP_INTERFACE_363:B,
MSS_ADLIB_INST/IP_INTERFACE_363:C,
MSS_ADLIB_INST/IP_INTERFACE_363:IPB,
MSS_ADLIB_INST/IP_INTERFACE_142:A,
MSS_ADLIB_INST/IP_INTERFACE_142:B,
MSS_ADLIB_INST/IP_INTERFACE_142:C,
MSS_ADLIB_INST/IP_INTERFACE_142:IPB,
MDDR_DDR_AXI_S_ARBURST_ibuf[1]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARBURST_ibuf[1]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RVALID_obuf/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RVALID_obuf/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RVALID_obuf/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[8]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[8]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[61]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[61]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_BRESP_obuf[0]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_BRESP_obuf[0]/U0/U_IOOUTFF:Y,
MDDR_APB_S_PRDATA_obuf[10]/U0/U_IOPAD:D,
MDDR_APB_S_PRDATA_obuf[10]/U0/U_IOPAD:E,
MDDR_APB_S_PRDATA_obuf[10]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_23:A,
MSS_ADLIB_INST/IP_INTERFACE_23:B,
MSS_ADLIB_INST/IP_INTERFACE_23:C,
MSS_ADLIB_INST/IP_INTERFACE_23:IPB,
MDDR_DDR_AXI_S_WID_ibuf[2]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WID_ibuf[2]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[1]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[1]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_45:A,
MSS_ADLIB_INST/IP_INTERFACE_45:B,
MSS_ADLIB_INST/IP_INTERFACE_45:C,
MSS_ADLIB_INST/IP_INTERFACE_45:IPA,
MSS_ADLIB_INST/IP_INTERFACE_45:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[43]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[43]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[31]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[31]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[35]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[35]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_102:A,
MSS_ADLIB_INST/IP_INTERFACE_102:B,
MSS_ADLIB_INST/IP_INTERFACE_102:C,
MSS_ADLIB_INST/IP_INTERFACE_102:IPA,
MSS_ADLIB_INST/IP_INTERFACE_102:IPB,
FIC_2_APB_M_PRDATA_ibuf[29]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[29]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_135:A,
MSS_ADLIB_INST/IP_INTERFACE_135:B,
MSS_ADLIB_INST/IP_INTERFACE_135:C,
MSS_ADLIB_INST/IP_INTERFACE_135:IPA,
MSS_ADLIB_INST/IP_INTERFACE_135:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[44]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[44]/U0/U_IOINFF:Y,
MDDR_APB_S_PRDATA_obuf[4]/U0/U_IOOUTFF:A,
MDDR_APB_S_PRDATA_obuf[4]/U0/U_IOOUTFF:Y,
MDDR_APB_S_PRDATA_obuf[0]/U0/U_IOOUTFF:A,
MDDR_APB_S_PRDATA_obuf[0]/U0/U_IOOUTFF:Y,
FIC_2_APB_M_PADDR_obuf[8]/U0/U_IOENFF:A,
FIC_2_APB_M_PADDR_obuf[8]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_264:A,
MSS_ADLIB_INST/IP_INTERFACE_264:B,
MSS_ADLIB_INST/IP_INTERFACE_264:C,
MSS_ADLIB_INST/IP_INTERFACE_264:IPA,
MDDR_DDR_AXI_S_WDATA_ibuf[13]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[13]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[10]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[10]/U0/U_IOOUTFF:Y,
FIC_2_APB_M_PWDATA_obuf[29]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[29]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[4]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[4]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[4]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[16]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[16]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HWDATA_ibuf[19]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[19]/U0/U_IOINFF:Y,
FIC_2_APB_M_PWDATA_obuf[5]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[5]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[5]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RRESP_obuf[0]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RRESP_obuf[0]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[11]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[11]/U0/U_IOOUTFF:Y,
MDDR_APB_S_PRDATA_obuf[13]/U0/U_IOPAD:D,
MDDR_APB_S_PRDATA_obuf[13]/U0/U_IOPAD:E,
MDDR_APB_S_PRDATA_obuf[13]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[20]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[20]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[33]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[33]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[25]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[25]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HADDR_ibuf[25]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[25]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_210:A,
MSS_ADLIB_INST/IP_INTERFACE_210:B,
MSS_ADLIB_INST/IP_INTERFACE_210:C,
MSS_ADLIB_INST/IP_INTERFACE_210:IPA,
MSS_ADLIB_INST/IP_INTERFACE_210:IPB,
MDDR_APB_S_PSEL_ibuf/U0/U_IOINFF:A,
MDDR_APB_S_PSEL_ibuf/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_246:A,
MSS_ADLIB_INST/IP_INTERFACE_246:B,
MSS_ADLIB_INST/IP_INTERFACE_246:C,
MSS_ADLIB_INST/IP_INTERFACE_246:IPA,
FIC_2_APB_M_PWDATA_obuf[6]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[6]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[6]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PWDATA_obuf[23]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[23]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[34]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[34]/U0/U_IOENFF:Y,
FIC_2_APB_M_PCLK_obuf/U0/U_IOOUTFF:A,
FIC_2_APB_M_PCLK_obuf/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_211:A,
MSS_ADLIB_INST/IP_INTERFACE_211:B,
MSS_ADLIB_INST/IP_INTERFACE_211:C,
MSS_ADLIB_INST/IP_INTERFACE_211:IPB,
MDDR_DQ_5_PAD/U_IOPAD:D,
MDDR_DQ_5_PAD/U_IOPAD:E,
MDDR_DQ_5_PAD/U_IOPAD:PAD,
MDDR_DQ_5_PAD/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[23]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[23]/U0/U_IOOUTFF:Y,
MDDR_APB_S_PRDATA_obuf[6]/U0/U_IOENFF:A,
MDDR_APB_S_PRDATA_obuf[6]/U0/U_IOENFF:Y,
ip_interface_inst_3:A,
ip_interface_inst_3:B,
ip_interface_inst_3:C,
MDDR_APB_S_PWDATA_ibuf[4]/U0/U_IOPAD:PAD,
MDDR_APB_S_PWDATA_ibuf[4]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_383:A,
MSS_ADLIB_INST/IP_INTERFACE_383:B,
MSS_ADLIB_INST/IP_INTERFACE_383:C,
MSS_ADLIB_INST/IP_INTERFACE_383:IPB,
MDDR_APB_S_PADDR_ibuf[5]/U0/U_IOINFF:A,
MDDR_APB_S_PADDR_ibuf[5]/U0/U_IOINFF:Y,
FIC_2_APB_M_PRDATA_ibuf[2]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[2]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[8]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[8]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[27]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[27]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_206:A,
MSS_ADLIB_INST/IP_INTERFACE_206:B,
MSS_ADLIB_INST/IP_INTERFACE_206:C,
MSS_ADLIB_INST/IP_INTERFACE_206:IPA,
MSS_ADLIB_INST/IP_INTERFACE_206:IPB,
MDDR_BA_1_PAD/U_IOPAD:D,
MDDR_BA_1_PAD/U_IOPAD:E,
MDDR_BA_1_PAD/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_152:A,
MSS_ADLIB_INST/IP_INTERFACE_152:B,
MSS_ADLIB_INST/IP_INTERFACE_152:C,
MSS_ADLIB_INST/IP_INTERFACE_152:IPA,
MSS_ADLIB_INST/IP_INTERFACE_152:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[15]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[15]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HADDR_ibuf[22]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[22]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_BRESP_obuf[0]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_BRESP_obuf[0]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_126:A,
MSS_ADLIB_INST/IP_INTERFACE_126:B,
MSS_ADLIB_INST/IP_INTERFACE_126:C,
MSS_ADLIB_INST/IP_INTERFACE_126:IPA,
MSS_ADLIB_INST/IP_INTERFACE_126:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[50]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[50]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[50]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[44]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[44]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[35]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[35]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[1]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[1]/U0/U_IOENFF:Y,
MDDR_APB_S_PWDATA_ibuf[9]/U0/U_IOPAD:PAD,
MDDR_APB_S_PWDATA_ibuf[9]/U0/U_IOPAD:Y,
MDDR_DQS_1_PAD/U_IOPADP:EIN_P,
MDDR_DQS_1_PAD/U_IOPADP:IOUT_P,
MDDR_DQS_1_PAD/U_IOPADP:N2PIN_P,
MDDR_DQS_1_PAD/U_IOPADP:OIN_P,
MDDR_DQS_1_PAD/U_IOPADP:PAD_P,
FIC_0_AHB_S_HRDATA_obuf[16]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[16]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_97:A,
MSS_ADLIB_INST/IP_INTERFACE_97:B,
MSS_ADLIB_INST/IP_INTERFACE_97:C,
MSS_ADLIB_INST/IP_INTERFACE_97:IPA,
FIC_2_APB_M_PADDR_obuf[13]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PADDR_obuf[13]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_364:A,
MSS_ADLIB_INST/IP_INTERFACE_364:B,
MSS_ADLIB_INST/IP_INTERFACE_364:C,
MSS_ADLIB_INST/IP_INTERFACE_364:IPA,
MSS_ADLIB_INST/IP_INTERFACE_364:IPB,
MDDR_DDR_AXI_S_ARID_ibuf[1]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARID_ibuf[1]/U0/U_IOPAD:Y,
FIC_2_APB_M_PWDATA_obuf[0]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[0]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[0]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_284:A,
MSS_ADLIB_INST/IP_INTERFACE_284:B,
MSS_ADLIB_INST/IP_INTERFACE_284:C,
MSS_ADLIB_INST/IP_INTERFACE_284:IPA,
MSS_ADLIB_INST/IP_INTERFACE_284:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[50]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[50]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_133:A,
MSS_ADLIB_INST/IP_INTERFACE_133:B,
MSS_ADLIB_INST/IP_INTERFACE_133:C,
MSS_ADLIB_INST/IP_INTERFACE_133:IPA,
MDDR_DDR_AXI_S_RDATA_obuf[45]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[45]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[45]/U0/U_IOPAD:PAD,
MDDR_APB_S_PWDATA_ibuf[8]/U0/U_IOINFF:A,
MDDR_APB_S_PWDATA_ibuf[8]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_29:A,
MSS_ADLIB_INST/IP_INTERFACE_29:B,
MSS_ADLIB_INST/IP_INTERFACE_29:C,
MSS_ADLIB_INST/IP_INTERFACE_29:IPA,
MSS_ADLIB_INST/IP_INTERFACE_29:IPB,
MDDR_DDR_AXI_S_ARADDR_ibuf[23]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[23]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_275:A,
MSS_ADLIB_INST/IP_INTERFACE_275:B,
MSS_ADLIB_INST/IP_INTERFACE_275:C,
MSS_ADLIB_INST/IP_INTERFACE_275:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[10]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[10]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HRDATA_obuf[21]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[21]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[29]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[29]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_AWBURST_ibuf[0]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWBURST_ibuf[0]/U0/U_IOINFF:Y,
FIC_2_APB_M_PWDATA_obuf[11]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[11]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_326:A,
MSS_ADLIB_INST/IP_INTERFACE_326:B,
MSS_ADLIB_INST/IP_INTERFACE_326:C,
MSS_ADLIB_INST/IP_INTERFACE_326:IPA,
MSS_ADLIB_INST/IP_INTERFACE_326:IPB,
MSS_ADLIB_INST/IP_INTERFACE_195:A,
MSS_ADLIB_INST/IP_INTERFACE_195:B,
MSS_ADLIB_INST/IP_INTERFACE_195:C,
MSS_ADLIB_INST/IP_INTERFACE_195:IPA,
MSS_ADLIB_INST/IP_INTERFACE_195:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[60]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[60]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[60]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PWDATA_obuf[28]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[28]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[28]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RDATA_obuf[0]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[0]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[0]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_256:A,
MSS_ADLIB_INST/IP_INTERFACE_256:B,
MSS_ADLIB_INST/IP_INTERFACE_256:C,
MSS_ADLIB_INST/IP_INTERFACE_256:IPA,
MSS_ADLIB_INST/IP_INTERFACE_256:IPB,
FIC_0_AHB_S_HADDR_ibuf[21]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[21]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_BREADY_ibuf/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_BREADY_ibuf/U0/U_IOPAD:Y,
FIC_2_APB_M_PRDATA_ibuf[19]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[19]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_43:A,
MSS_ADLIB_INST/IP_INTERFACE_43:B,
MSS_ADLIB_INST/IP_INTERFACE_43:C,
MSS_ADLIB_INST/IP_INTERFACE_43:IPA,
MSS_ADLIB_INST/IP_INTERFACE_43:IPB,
MSS_ADLIB_INST/IP_INTERFACE_343:A,
MSS_ADLIB_INST/IP_INTERFACE_343:B,
MSS_ADLIB_INST/IP_INTERFACE_343:C,
MSS_ADLIB_INST/IP_INTERFACE_343:IPA,
MSS_ADLIB_INST/IP_INTERFACE_343:IPB,
MSS_ADLIB_INST/IP_INTERFACE_114:A,
MSS_ADLIB_INST/IP_INTERFACE_114:B,
MSS_ADLIB_INST/IP_INTERFACE_114:C,
MSS_ADLIB_INST/IP_INTERFACE_114:IPA,
MSS_ADLIB_INST/IP_INTERFACE_114:IPB,
FIC_0_AHB_S_HWDATA_ibuf[12]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[12]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[26]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[26]/U0/U_IOINFF:Y,
FIC_2_APB_M_PRDATA_ibuf[25]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[25]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[4]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[4]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[60]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[60]/U0/U_IOPAD:Y,
MDDR_APB_S_PRDATA_obuf[3]/U0/U_IOPAD:D,
MDDR_APB_S_PRDATA_obuf[3]/U0/U_IOPAD:E,
MDDR_APB_S_PRDATA_obuf[3]/U0/U_IOPAD:PAD,
GPIO_9_M2F_obuf/U0/U_IOPAD:D,
GPIO_9_M2F_obuf/U0/U_IOPAD:E,
GPIO_9_M2F_obuf/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_213:A,
MSS_ADLIB_INST/IP_INTERFACE_213:B,
MSS_ADLIB_INST/IP_INTERFACE_213:C,
MSS_ADLIB_INST/IP_INTERFACE_213:IPA,
MSS_ADLIB_INST/IP_INTERFACE_213:IPB,
FIC_0_AHB_S_HWDATA_ibuf[26]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[26]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[15]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[15]/U0/U_IOINFF:Y,
MDDR_DM_RDQS_1_PAD/U_IOINFF:A,
MDDR_DM_RDQS_1_PAD/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[10]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[10]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_303:A,
MSS_ADLIB_INST/IP_INTERFACE_303:B,
MSS_ADLIB_INST/IP_INTERFACE_303:C,
MSS_ADLIB_INST/IP_INTERFACE_303:IPA,
MSS_ADLIB_INST/IP_INTERFACE_303:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[21]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[21]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[21]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[29]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[29]/U0/U_IOPAD:Y,
MDDR_CLK_PAD/U_ION:YIN,
FIC_0_AHB_S_HRDATA_obuf[5]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[5]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[13]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[13]/U0/U_IOINFF:Y,
MDDR_APB_S_PADDR_ibuf[10]/U0/U_IOINFF:A,
MDDR_APB_S_PADDR_ibuf[10]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[17]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[17]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_244:A,
MSS_ADLIB_INST/IP_INTERFACE_244:B,
MSS_ADLIB_INST/IP_INTERFACE_244:C,
MSS_ADLIB_INST/IP_INTERFACE_244:IPA,
FIC_2_APB_M_PRDATA_ibuf[9]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[9]/U0/U_IOINFF:Y,
MDDR_APB_S_PRDATA_obuf[0]/U0/U_IOPAD:D,
MDDR_APB_S_PRDATA_obuf[0]/U0/U_IOPAD:E,
MDDR_APB_S_PRDATA_obuf[0]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RDATA_obuf[3]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[3]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[5]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[5]/U0/U_IOINFF:Y,
MDDR_ADDR_1_PAD/U_IOPAD:D,
MDDR_ADDR_1_PAD/U_IOPAD:E,
MDDR_ADDR_1_PAD/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[24]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[24]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[30]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[30]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_WREADY_obuf/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_WREADY_obuf/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_WREADY_obuf/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[2]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[2]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[3]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[3]/U0/U_IOPAD:Y,
FIC_2_APB_M_PRDATA_ibuf[14]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[14]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[2]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[2]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_AWID_ibuf[1]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWID_ibuf[1]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_52:A,
MSS_ADLIB_INST/IP_INTERFACE_52:B,
MSS_ADLIB_INST/IP_INTERFACE_52:C,
MSS_ADLIB_INST/IP_INTERFACE_52:IPA,
MSS_ADLIB_INST/IP_INTERFACE_52:IPB,
MDDR_CAS_N_PAD/U_IOPAD:D,
MDDR_CAS_N_PAD/U_IOPAD:E,
MDDR_CAS_N_PAD/U_IOPAD:PAD,
MDDR_APB_S_PWDATA_ibuf[6]/U0/U_IOPAD:PAD,
MDDR_APB_S_PWDATA_ibuf[6]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_277:A,
MSS_ADLIB_INST/IP_INTERFACE_277:B,
MSS_ADLIB_INST/IP_INTERFACE_277:C,
MSS_ADLIB_INST/IP_INTERFACE_277:IPA,
MSS_ADLIB_INST/IP_INTERFACE_277:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[27]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[27]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[31]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[31]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_132:A,
MSS_ADLIB_INST/IP_INTERFACE_132:B,
MSS_ADLIB_INST/IP_INTERFACE_132:C,
MSS_ADLIB_INST/IP_INTERFACE_132:IPA,
MDDR_DDR_AXI_S_AWADDR_ibuf[10]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[10]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_204:A,
MSS_ADLIB_INST/IP_INTERFACE_204:B,
MSS_ADLIB_INST/IP_INTERFACE_204:C,
MSS_ADLIB_INST/IP_INTERFACE_204:IPA,
MSS_ADLIB_INST/IP_INTERFACE_193:A,
MSS_ADLIB_INST/IP_INTERFACE_193:B,
MSS_ADLIB_INST/IP_INTERFACE_193:C,
MSS_ADLIB_INST/IP_INTERFACE_193:IPA,
MSS_ADLIB_INST/IP_INTERFACE_193:IPB,
MDDR_DDR_AXI_S_BRESP_obuf[1]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_BRESP_obuf[1]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_BRESP_obuf[1]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[26]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[26]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[3]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[3]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RID_obuf[0]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RID_obuf[0]/U0/U_IOENFF:Y,
FIC_2_APB_M_PWDATA_obuf[31]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[31]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[56]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[56]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[56]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WLAST_ibuf/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WLAST_ibuf/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[31]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[31]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[22]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[22]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_353:A,
MSS_ADLIB_INST/IP_INTERFACE_353:B,
MSS_ADLIB_INST/IP_INTERFACE_353:C,
MSS_ADLIB_INST/IP_INTERFACE_353:IPA,
FIC_2_APB_M_PRDATA_ibuf[5]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[5]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[25]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[25]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[13]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[13]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[5]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[5]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARVALID_ibuf/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARVALID_ibuf/U0/U_IOINFF:Y,
FIC_2_APB_M_PRDATA_ibuf[8]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[8]/U0/U_IOINFF:Y,
MDDR_DQ_12_PAD/U_IOINFF:A,
MDDR_DQ_12_PAD/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_49:A,
MSS_ADLIB_INST/IP_INTERFACE_49:B,
MSS_ADLIB_INST/IP_INTERFACE_49:C,
MSS_ADLIB_INST/IP_INTERFACE_49:IPA,
MSS_ADLIB_INST/IP_INTERFACE_279:A,
MSS_ADLIB_INST/IP_INTERFACE_279:B,
MSS_ADLIB_INST/IP_INTERFACE_279:C,
MSS_ADLIB_INST/IP_INTERFACE_279:IPA,
MSS_ADLIB_INST/IP_INTERFACE_279:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[14]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[14]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HREADY_ibuf/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HREADY_ibuf/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[56]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[56]/U0/U_IOINFF:Y,
FIC_2_APB_M_PRDATA_ibuf[30]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[30]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_378:A,
MSS_ADLIB_INST/IP_INTERFACE_378:B,
MSS_ADLIB_INST/IP_INTERFACE_378:C,
MSS_ADLIB_INST/IP_INTERFACE_378:IPA,
MSS_ADLIB_INST/IP_INTERFACE_378:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[41]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[41]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RID_obuf[0]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RID_obuf[0]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RID_obuf[0]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_344:A,
MSS_ADLIB_INST/IP_INTERFACE_344:B,
MSS_ADLIB_INST/IP_INTERFACE_344:C,
MSS_ADLIB_INST/IP_INTERFACE_344:IPA,
MSS_ADLIB_INST/IP_INTERFACE_344:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[49]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[49]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[49]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARID_ibuf[0]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARID_ibuf[0]/U0/U_IOINFF:Y,
MDDR_APB_S_PWDATA_ibuf[2]/U0/U_IOINFF:A,
MDDR_APB_S_PWDATA_ibuf[2]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HREADYOUT_obuf/U0/U_IOPAD:D,
FIC_0_AHB_S_HREADYOUT_obuf/U0/U_IOPAD:E,
FIC_0_AHB_S_HREADYOUT_obuf/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[32]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[32]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HADDR_ibuf[2]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[2]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HADDR_ibuf[17]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[17]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_236:A,
MSS_ADLIB_INST/IP_INTERFACE_236:B,
MSS_ADLIB_INST/IP_INTERFACE_236:C,
MSS_ADLIB_INST/IP_INTERFACE_236:IPA,
MSS_ADLIB_INST/IP_INTERFACE_236:IPB,
MDDR_DDR_AXI_S_BVALID_obuf/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_BVALID_obuf/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[9]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[9]/U0/U_IOENFF:Y,
MDDR_CKE_PAD/U_IOPAD:D,
MDDR_CKE_PAD/U_IOPAD:E,
MDDR_CKE_PAD/U_IOPAD:PAD,
GPIO_3_M2F_obuf/U0/U_IOOUTFF:A,
GPIO_3_M2F_obuf/U0/U_IOOUTFF:Y,
MDDR_DQ_15_PAD/U_IOINFF:A,
MDDR_DQ_15_PAD/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[12]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[12]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[12]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_375:A,
MSS_ADLIB_INST/IP_INTERFACE_375:B,
MSS_ADLIB_INST/IP_INTERFACE_375:C,
MSS_ADLIB_INST/IP_INTERFACE_375:IPA,
MSS_ADLIB_INST/IP_INTERFACE_254:A,
MSS_ADLIB_INST/IP_INTERFACE_254:B,
MSS_ADLIB_INST/IP_INTERFACE_254:C,
MSS_ADLIB_INST/IP_INTERFACE_254:IPA,
MSS_ADLIB_INST/IP_INTERFACE_254:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[11]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[11]/U0/U_IOPAD:Y,
FIC_2_APB_M_PWDATA_obuf[13]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[13]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[13]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HRDATA_obuf[10]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[10]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[10]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_87:A,
MSS_ADLIB_INST/IP_INTERFACE_87:B,
MSS_ADLIB_INST/IP_INTERFACE_87:C,
MSS_ADLIB_INST/IP_INTERFACE_87:IPA,
MSS_ADLIB_INST/IP_INTERFACE_87:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[32]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[32]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[32]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[20]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[20]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[31]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[31]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HRDATA_obuf[25]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[25]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_322:A,
MSS_ADLIB_INST/IP_INTERFACE_322:B,
MSS_ADLIB_INST/IP_INTERFACE_322:C,
MSS_ADLIB_INST/IP_INTERFACE_322:IPB,
FIC_0_AHB_S_HRDATA_obuf[28]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[28]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[28]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_304:A,
MSS_ADLIB_INST/IP_INTERFACE_304:B,
MSS_ADLIB_INST/IP_INTERFACE_304:C,
MSS_ADLIB_INST/IP_INTERFACE_304:IPA,
MSS_ADLIB_INST/IP_INTERFACE_304:IPB,
MDDR_DDR_AXI_S_ARLEN_ibuf[2]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARLEN_ibuf[2]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARVALID_ibuf/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARVALID_ibuf/U0/U_IOPAD:Y,
FIC_0_AHB_S_HSEL_ibuf/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HSEL_ibuf/U0/U_IOPAD:Y,
FIC_0_AHB_S_HADDR_ibuf[28]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[28]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[8]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[8]/U0/U_IOINFF:Y,
FIC_2_APB_M_PWDATA_obuf[7]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[7]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[7]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RDATA_obuf[48]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[48]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[6]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[6]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[1]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[1]/U0/U_IOPAD:Y,
FIC_2_APB_M_PRDATA_ibuf[7]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[7]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[29]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[29]/U0/U_IOPAD:Y,
FIC_2_APB_M_PWDATA_obuf[17]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[17]/U0/U_IOOUTFF:Y,
FIC_2_APB_M_PRDATA_ibuf[25]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[25]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HADDR_ibuf[29]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[29]/U0/U_IOPAD:Y,
MDDR_ADDR_11_PAD/U_IOPAD:D,
MDDR_ADDR_11_PAD/U_IOPAD:E,
MDDR_ADDR_11_PAD/U_IOPAD:PAD,
FIC_0_AHB_S_HSEL_ibuf/U0/U_IOINFF:A,
FIC_0_AHB_S_HSEL_ibuf/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_192:A,
MSS_ADLIB_INST/IP_INTERFACE_192:B,
MSS_ADLIB_INST/IP_INTERFACE_192:C,
MSS_ADLIB_INST/IP_INTERFACE_192:IPA,
MDDR_DDR_AXI_S_WVALID_ibuf/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WVALID_ibuf/U0/U_IOINFF:Y,
MSS_RESET_N_M2F_obuf/U0/U_IOENFF:A,
MSS_RESET_N_M2F_obuf/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RID_obuf[1]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RID_obuf[1]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RID_obuf[1]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[18]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[18]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[29]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[29]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[20]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[20]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_AWBURST_ibuf[1]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWBURST_ibuf[1]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HRDATA_obuf[12]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[12]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[12]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[12]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HRDATA_obuf[6]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[6]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_170:A,
MSS_ADLIB_INST/IP_INTERFACE_170:B,
MSS_ADLIB_INST/IP_INTERFACE_170:C,
MSS_ADLIB_INST/IP_INTERFACE_170:IPA,
MSS_ADLIB_INST/IP_INTERFACE_170:IPB,
FIC_0_AHB_S_HWDATA_ibuf[7]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[7]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[52]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[52]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[27]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[27]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_354:A,
MSS_ADLIB_INST/IP_INTERFACE_354:B,
MSS_ADLIB_INST/IP_INTERFACE_354:C,
MSS_ADLIB_INST/IP_INTERFACE_354:IPA,
FIC_2_APB_M_PWDATA_obuf[10]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[10]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[10]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_222:A,
MSS_ADLIB_INST/IP_INTERFACE_222:B,
MSS_ADLIB_INST/IP_INTERFACE_222:C,
MSS_ADLIB_INST/IP_INTERFACE_222:IPA,
MSS_ADLIB_INST/IP_INTERFACE_222:IPB,
FIC_0_AHB_S_HWRITE_ibuf/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWRITE_ibuf/U0/U_IOPAD:Y,
FIC_0_AHB_S_HRDATA_obuf[22]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[22]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_377:A,
MSS_ADLIB_INST/IP_INTERFACE_377:B,
MSS_ADLIB_INST/IP_INTERFACE_377:C,
MSS_ADLIB_INST/IP_INTERFACE_377:IPA,
MSS_ADLIB_INST/IP_INTERFACE_377:IPB,
FIC_2_APB_M_PWDATA_obuf[23]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[23]/U0/U_IOENFF:Y,
FIC_0_AHB_S_HRDATA_obuf[11]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[11]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[56]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[56]/U0/U_IOENFF:Y,
MDDR_APB_S_PRDATA_obuf[4]/U0/U_IOENFF:A,
MDDR_APB_S_PRDATA_obuf[4]/U0/U_IOENFF:Y,
GPIO_4_M2F_obuf/U0/U_IOPAD:D,
GPIO_4_M2F_obuf/U0/U_IOPAD:E,
GPIO_4_M2F_obuf/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_BRESP_obuf[0]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_BRESP_obuf[0]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_BRESP_obuf[0]/U0/U_IOPAD:PAD,
MDDR_APB_S_PWDATA_ibuf[15]/U0/U_IOINFF:A,
MDDR_APB_S_PWDATA_ibuf[15]/U0/U_IOINFF:Y,
MDDR_APB_S_PRDATA_obuf[15]/U0/U_IOPAD:D,
MDDR_APB_S_PRDATA_obuf[15]/U0/U_IOPAD:E,
MDDR_APB_S_PRDATA_obuf[15]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_333:A,
MSS_ADLIB_INST/IP_INTERFACE_333:B,
MSS_ADLIB_INST/IP_INTERFACE_333:C,
MSS_ADLIB_INST/IP_INTERFACE_333:IPA,
MSS_ADLIB_INST/IP_INTERFACE_333:IPB,
MSS_ADLIB_INST/IP_INTERFACE_118:A,
MSS_ADLIB_INST/IP_INTERFACE_118:B,
MSS_ADLIB_INST/IP_INTERFACE_118:C,
MSS_ADLIB_INST/IP_INTERFACE_118:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[48]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[48]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[2]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[2]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[38]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[38]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_166:A,
MSS_ADLIB_INST/IP_INTERFACE_166:B,
MSS_ADLIB_INST/IP_INTERFACE_166:C,
MSS_ADLIB_INST/IP_INTERFACE_166:IPB,
FIC_2_APB_M_PADDR_obuf[11]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PADDR_obuf[11]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_296:A,
MSS_ADLIB_INST/IP_INTERFACE_296:B,
MSS_ADLIB_INST/IP_INTERFACE_296:C,
MSS_ADLIB_INST/IP_INTERFACE_296:IPA,
MSS_ADLIB_INST/IP_INTERFACE_296:IPB,
FIC_2_APB_M_PADDR_obuf[16]/U0/U_IOPAD:D,
FIC_2_APB_M_PADDR_obuf[16]/U0/U_IOPAD:E,
FIC_2_APB_M_PADDR_obuf[16]/U0/U_IOPAD:PAD,
MDDR_APB_S_PRDATA_obuf[2]/U0/U_IOPAD:D,
MDDR_APB_S_PRDATA_obuf[2]/U0/U_IOPAD:E,
MDDR_APB_S_PRDATA_obuf[2]/U0/U_IOPAD:PAD,
GPIO_11_F2M_ibuf/U0/U_IOPAD:PAD,
GPIO_11_F2M_ibuf/U0/U_IOPAD:Y,
FIC_2_APB_M_PWDATA_obuf[7]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[7]/U0/U_IOOUTFF:Y,
MDDR_APB_S_PCLK_ibuf/U0/U_IOINFF:A,
MDDR_APB_S_PCLK_ibuf/U0/U_IOINFF:Y,
FIC_2_APB_M_PWDATA_obuf[3]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[3]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[35]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[35]/U0/U_IOINFF:Y,
MDDR_APB_S_PRDATA_obuf[11]/U0/U_IOOUTFF:A,
MDDR_APB_S_PRDATA_obuf[11]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_119:A,
MSS_ADLIB_INST/IP_INTERFACE_119:B,
MSS_ADLIB_INST/IP_INTERFACE_119:C,
MSS_ADLIB_INST/IP_INTERFACE_119:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[4]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[4]/U0/U_IOPAD:Y,
MDDR_APB_S_PRDATA_obuf[9]/U0/U_IOOUTFF:A,
MDDR_APB_S_PRDATA_obuf[9]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[23]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[23]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HWDATA_ibuf[16]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[16]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[23]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[23]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_234:A,
MSS_ADLIB_INST/IP_INTERFACE_234:B,
MSS_ADLIB_INST/IP_INTERFACE_234:C,
MSS_ADLIB_INST/IP_INTERFACE_234:IPA,
MSS_ADLIB_INST/IP_INTERFACE_234:IPB,
FIC_2_APB_M_PWDATA_obuf[26]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[26]/U0/U_IOOUTFF:Y,
FIC_2_APB_M_PWDATA_obuf[10]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[10]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_31:A,
MSS_ADLIB_INST/IP_INTERFACE_31:B,
MSS_ADLIB_INST/IP_INTERFACE_31:C,
MSS_ADLIB_INST/IP_INTERFACE_31:IPA,
MSS_ADLIB_INST/IP_INTERFACE_31:IPB,
FIC_0_AHB_S_HSIZE_ibuf[1]/U0/U_IOINFF:A,
FIC_0_AHB_S_HSIZE_ibuf[1]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[2]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[2]/U0/U_IOINFF:Y,
GPIO_0_M2F_obuf/U0/U_IOPAD:D,
GPIO_0_M2F_obuf/U0/U_IOPAD:E,
GPIO_0_M2F_obuf/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_366:A,
MSS_ADLIB_INST/IP_INTERFACE_366:B,
MSS_ADLIB_INST/IP_INTERFACE_366:C,
MSS_ADLIB_INST/IP_INTERFACE_366:IPA,
MSS_ADLIB_INST/IP_INTERFACE_366:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[24]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[24]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[4]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[4]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[0]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[0]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[15]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[15]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HRDATA_obuf[14]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[14]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[14]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[15]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[15]/U0/U_IOINFF:Y,
MDDR_CS_N_PAD/U_IOPAD:D,
MDDR_CS_N_PAD/U_IOPAD:E,
MDDR_CS_N_PAD/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_329:A,
MSS_ADLIB_INST/IP_INTERFACE_329:B,
MSS_ADLIB_INST/IP_INTERFACE_329:C,
MSS_ADLIB_INST/IP_INTERFACE_329:IPA,
MSS_ADLIB_INST/IP_INTERFACE_329:IPB,
FIC_0_AHB_S_HRESP_obuf/U0/U_IOENFF:A,
FIC_0_AHB_S_HRESP_obuf/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[7]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[7]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[20]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[20]/U0/U_IOPAD:Y,
MDDR_APB_S_PWDATA_ibuf[4]/U0/U_IOINFF:A,
MDDR_APB_S_PWDATA_ibuf[4]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HRDATA_obuf[21]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[21]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[21]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RDATA_obuf[5]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[5]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[5]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[23]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[23]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_186:A,
MSS_ADLIB_INST/IP_INTERFACE_186:B,
MSS_ADLIB_INST/IP_INTERFACE_186:C,
MSS_ADLIB_INST/IP_INTERFACE_186:IPA,
MSS_ADLIB_INST/IP_INTERFACE_186:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[25]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[25]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_AWID_ibuf[3]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWID_ibuf[3]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HRDATA_obuf[3]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[3]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_5:A,
MSS_ADLIB_INST/IP_INTERFACE_5:B,
MSS_ADLIB_INST/IP_INTERFACE_5:C,
MSS_ADLIB_INST/IP_INTERFACE_5:IPA,
MSS_ADLIB_INST/IP_INTERFACE_5:IPB,
FIC_0_AHB_S_HADDR_ibuf[4]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[4]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_71:A,
MSS_ADLIB_INST/IP_INTERFACE_71:B,
MSS_ADLIB_INST/IP_INTERFACE_71:C,
MSS_ADLIB_INST/IP_INTERFACE_71:IPB,
MDDR_APB_S_PADDR_ibuf[3]/U0/U_IOINFF:A,
MDDR_APB_S_PADDR_ibuf[3]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[5]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[5]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[13]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[13]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HRDATA_obuf[5]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[5]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[5]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[16]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[16]/U0/U_IOPAD:Y,
MSS_RESET_N_M2F_obuf/U0/U_IOPAD:D,
MSS_RESET_N_M2F_obuf/U0/U_IOPAD:E,
MSS_RESET_N_M2F_obuf/U0/U_IOPAD:PAD,
GPIO_4_M2F_obuf/U0/U_IOOUTFF:A,
GPIO_4_M2F_obuf/U0/U_IOOUTFF:Y,
FIC_2_APB_M_PENABLE_obuf/U0/U_IOOUTFF:A,
FIC_2_APB_M_PENABLE_obuf/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[39]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[39]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[47]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[47]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[47]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[36]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[36]/U0/U_IOPAD:Y,
MDDR_APB_S_PWDATA_ibuf[7]/U0/U_IOPAD:PAD,
MDDR_APB_S_PWDATA_ibuf[7]/U0/U_IOPAD:Y,
FIC_2_APB_M_PWDATA_obuf[13]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[13]/U0/U_IOENFF:Y,
SPI_0_DO_PAD/U_IOPAD:D,
SPI_0_DO_PAD/U_IOPAD:E,
SPI_0_DO_PAD/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[24]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[24]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HRDATA_obuf[29]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[29]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[29]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_334:A,
MSS_ADLIB_INST/IP_INTERFACE_334:B,
MSS_ADLIB_INST/IP_INTERFACE_334:C,
MSS_ADLIB_INST/IP_INTERFACE_334:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[57]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[57]/U0/U_IOINFF:Y,
GPIO_9_M2F_obuf/U0/U_IOENFF:A,
GPIO_9_M2F_obuf/U0/U_IOENFF:Y,
FIC_2_APB_M_PADDR_obuf[3]/U0/U_IOENFF:A,
FIC_2_APB_M_PADDR_obuf[3]/U0/U_IOENFF:Y,
MDDR_DQ_1_PAD/U_IOPAD:D,
MDDR_DQ_1_PAD/U_IOPAD:E,
MDDR_DQ_1_PAD/U_IOPAD:PAD,
MDDR_DQ_1_PAD/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[11]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[11]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[15]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[15]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_56:A,
MSS_ADLIB_INST/IP_INTERFACE_56:B,
MSS_ADLIB_INST/IP_INTERFACE_56:C,
MSS_ADLIB_INST/IP_INTERFACE_56:IPA,
MSS_ADLIB_INST/IP_INTERFACE_56:IPB,
FIC_2_APB_M_PWDATA_obuf[25]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[25]/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[18]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[18]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_27:A,
MSS_ADLIB_INST/IP_INTERFACE_27:B,
MSS_ADLIB_INST/IP_INTERFACE_27:C,
MSS_ADLIB_INST/IP_INTERFACE_27:IPA,
MSS_ADLIB_INST/IP_INTERFACE_27:IPB,
MDDR_APB_S_PRDATA_obuf[15]/U0/U_IOENFF:A,
MDDR_APB_S_PRDATA_obuf[15]/U0/U_IOENFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[9]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[9]/U0/U_IOPAD:Y,
MDDR_DDR_CORE_RESET_N_ibuf/U0/U_IOPAD:PAD,
MDDR_DDR_CORE_RESET_N_ibuf/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WSTRB_ibuf[2]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WSTRB_ibuf[2]/U0/U_IOINFF:Y,
FIC_2_APB_M_PWDATA_obuf[14]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[14]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[0]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[0]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_BID_obuf[1]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_BID_obuf[1]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_BID_obuf[3]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_BID_obuf[3]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_175:A,
MSS_ADLIB_INST/IP_INTERFACE_175:B,
MSS_ADLIB_INST/IP_INTERFACE_175:C,
MSS_ADLIB_INST/IP_INTERFACE_175:IPA,
MSS_ADLIB_INST/IP_INTERFACE_175:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[6]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[6]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[6]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HRDATA_obuf[7]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[7]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_294:A,
MSS_ADLIB_INST/IP_INTERFACE_294:B,
MSS_ADLIB_INST/IP_INTERFACE_294:C,
MSS_ADLIB_INST/IP_INTERFACE_294:IPA,
MSS_ADLIB_INST/IP_INTERFACE_294:IPB,
FIC_0_AHB_S_HADDR_ibuf[20]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[20]/U0/U_IOINFF:Y,
MDDR_APB_S_PWDATA_ibuf[1]/U0/U_IOINFF:A,
MDDR_APB_S_PWDATA_ibuf[1]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HRDATA_obuf[16]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[16]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[16]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RDATA_obuf[49]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[49]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[59]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[59]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[25]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[25]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HRDATA_obuf[15]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[15]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_146:A,
MSS_ADLIB_INST/IP_INTERFACE_146:B,
MSS_ADLIB_INST/IP_INTERFACE_146:C,
MSS_ADLIB_INST/IP_INTERFACE_146:IPA,
MSS_ADLIB_INST/IP_INTERFACE_146:IPB,
MDDR_ADDR_9_PAD/U_IOPAD:D,
MDDR_ADDR_9_PAD/U_IOPAD:E,
MDDR_ADDR_9_PAD/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[23]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[23]/U0/U_IOINFF:Y,
FIC_2_APB_M_PRDATA_ibuf[28]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[28]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_228:A,
MSS_ADLIB_INST/IP_INTERFACE_228:B,
MSS_ADLIB_INST/IP_INTERFACE_228:C,
MSS_ADLIB_INST/IP_INTERFACE_228:IPA,
MDDR_DDR_AXI_S_RDATA_obuf[26]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[26]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[18]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[18]/U0/U_IOINFF:Y,
MDDR_BA_0_PAD/U_IOPAD:D,
MDDR_BA_0_PAD/U_IOPAD:E,
MDDR_BA_0_PAD/U_IOPAD:PAD,
FIC_0_AHB_S_HRDATA_obuf[23]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[23]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[49]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[49]/U0/U_IOENFF:Y,
FIC_0_AHB_S_HSIZE_ibuf[0]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HSIZE_ibuf[0]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_62:A,
MSS_ADLIB_INST/IP_INTERFACE_62:B,
MSS_ADLIB_INST/IP_INTERFACE_62:C,
MSS_ADLIB_INST/IP_INTERFACE_62:IPA,
MSS_ADLIB_INST/IP_INTERFACE_62:IPB,
MDDR_DDR_AXI_S_AWADDR_ibuf[17]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[17]/U0/U_IOINFF:Y,
MDDR_APB_S_PRDATA_obuf[14]/U0/U_IOPAD:D,
MDDR_APB_S_PRDATA_obuf[14]/U0/U_IOPAD:E,
MDDR_APB_S_PRDATA_obuf[14]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_106:A,
MSS_ADLIB_INST/IP_INTERFACE_106:B,
MSS_ADLIB_INST/IP_INTERFACE_106:C,
MSS_ADLIB_INST/IP_INTERFACE_106:IPB,
FIC_0_AHB_S_HRDATA_obuf[25]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[25]/U0/U_IOOUTFF:Y,
MDDR_APB_S_PADDR_ibuf[9]/U0/U_IOINFF:A,
MDDR_APB_S_PADDR_ibuf[9]/U0/U_IOINFF:Y,
FIC_2_APB_M_PWDATA_obuf[4]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[4]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[4]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[20]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[20]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[8]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[8]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_58:A,
MSS_ADLIB_INST/IP_INTERFACE_58:B,
MSS_ADLIB_INST/IP_INTERFACE_58:C,
MSS_ADLIB_INST/IP_INTERFACE_58:IPB,
FIC_2_APB_M_PRDATA_ibuf[13]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[13]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_WSTRB_ibuf[3]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WSTRB_ibuf[3]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[53]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[53]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[53]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_346:A,
MSS_ADLIB_INST/IP_INTERFACE_346:B,
MSS_ADLIB_INST/IP_INTERFACE_346:C,
MSS_ADLIB_INST/IP_INTERFACE_346:IPB,
FIC_2_APB_M_PWDATA_obuf[12]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[12]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_362:A,
MSS_ADLIB_INST/IP_INTERFACE_362:B,
MSS_ADLIB_INST/IP_INTERFACE_362:C,
MSS_ADLIB_INST/IP_INTERFACE_362:IPB,
FIC_0_AHB_S_HWDATA_ibuf[27]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[27]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[58]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[58]/U0/U_IOENFF:Y,
FIC_2_APB_M_PWDATA_obuf[1]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[1]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[1]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[10]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[10]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[39]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[39]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_173:A,
MSS_ADLIB_INST/IP_INTERFACE_173:B,
MSS_ADLIB_INST/IP_INTERFACE_173:C,
MSS_ADLIB_INST/IP_INTERFACE_173:IPA,
MSS_ADLIB_INST/IP_INTERFACE_173:IPB,
MDDR_DDR_AXI_S_AWADDR_ibuf[5]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[5]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HRDATA_obuf[12]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[12]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[18]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[18]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[18]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[18]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_306:A,
MSS_ADLIB_INST/IP_INTERFACE_306:B,
MSS_ADLIB_INST/IP_INTERFACE_306:C,
MSS_ADLIB_INST/IP_INTERFACE_306:IPA,
MSS_ADLIB_INST/IP_INTERFACE_306:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[45]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[45]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_AWLEN_ibuf[2]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWLEN_ibuf[2]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARREADY_obuf/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_ARREADY_obuf/U0/U_IOENFF:Y,
MDDR_APB_S_PRDATA_obuf[3]/U0/U_IOENFF:A,
MDDR_APB_S_PRDATA_obuf[3]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_ARSIZE_ibuf[1]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARSIZE_ibuf[1]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HADDR_ibuf[7]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[7]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_121:A,
MSS_ADLIB_INST/IP_INTERFACE_121:B,
MSS_ADLIB_INST/IP_INTERFACE_121:C,
MSS_ADLIB_INST/IP_INTERFACE_121:IPA,
MDDR_DDR_AXI_S_AWADDR_ibuf[22]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[22]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[0]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[0]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[63]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[63]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[63]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[31]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[31]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_156:A,
MSS_ADLIB_INST/IP_INTERFACE_156:B,
MSS_ADLIB_INST/IP_INTERFACE_156:C,
MSS_ADLIB_INST/IP_INTERFACE_156:IPA,
MDDR_DDR_AXI_S_ARADDR_ibuf[21]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[21]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HADDR_ibuf[30]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[30]/U0/U_IOINFF:Y,
MDDR_DM_RDQS_0_PAD/U_IOPAD:D,
MDDR_DM_RDQS_0_PAD/U_IOPAD:E,
MDDR_DM_RDQS_0_PAD/U_IOPAD:PAD,
MDDR_DM_RDQS_0_PAD/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_47:A,
MSS_ADLIB_INST/IP_INTERFACE_47:B,
MSS_ADLIB_INST/IP_INTERFACE_47:C,
MSS_ADLIB_INST/IP_INTERFACE_47:IPB,
FIC_2_APB_M_PADDR_obuf[12]/U0/U_IOENFF:A,
FIC_2_APB_M_PADDR_obuf[12]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[30]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[30]/U0/U_IOINFF:Y,
MDDR_APB_S_PRDATA_obuf[7]/U0/U_IOOUTFF:A,
MDDR_APB_S_PRDATA_obuf[7]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_262:A,
MSS_ADLIB_INST/IP_INTERFACE_262:B,
MSS_ADLIB_INST/IP_INTERFACE_262:C,
MSS_ADLIB_INST/IP_INTERFACE_262:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[58]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[58]/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[2]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[2]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_54:A,
MSS_ADLIB_INST/IP_INTERFACE_54:B,
MSS_ADLIB_INST/IP_INTERFACE_54:C,
MSS_ADLIB_INST/IP_INTERFACE_54:IPA,
MSS_ADLIB_INST/IP_INTERFACE_54:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[22]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[22]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[22]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PADDR_obuf[13]/U0/U_IOENFF:A,
FIC_2_APB_M_PADDR_obuf[13]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RMW_ibuf/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RMW_ibuf/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[21]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[21]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[21]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[21]/U0/U_IOINFF:Y,
MDDR_APB_S_PADDR_ibuf[6]/U0/U_IOPAD:PAD,
MDDR_APB_S_PADDR_ibuf[6]/U0/U_IOPAD:Y,
FIC_2_APB_M_PRDATA_ibuf[18]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[18]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HRDATA_obuf[20]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[20]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_382:A,
MSS_ADLIB_INST/IP_INTERFACE_382:B,
MSS_ADLIB_INST/IP_INTERFACE_382:C,
MSS_ADLIB_INST/IP_INTERFACE_382:IPB,
FIC_0_AHB_S_HRDATA_obuf[28]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[28]/U0/U_IOOUTFF:Y,
MDDR_DQ_11_PAD/U_IOPAD:D,
MDDR_DQ_11_PAD/U_IOPAD:E,
MDDR_DQ_11_PAD/U_IOPAD:PAD,
MDDR_DQ_11_PAD/U_IOPAD:Y,
FIC_0_AHB_S_HWDATA_ibuf[8]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[8]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_356:A,
MSS_ADLIB_INST/IP_INTERFACE_356:B,
MSS_ADLIB_INST/IP_INTERFACE_356:C,
MSS_ADLIB_INST/IP_INTERFACE_356:IPA,
GPIO_2_M2F_obuf/U0/U_IOOUTFF:A,
GPIO_2_M2F_obuf/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HRDATA_obuf[4]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[4]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[4]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WID_ibuf[0]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WID_ibuf[0]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[54]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[54]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[54]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_50:A,
MSS_ADLIB_INST/IP_INTERFACE_50:B,
MSS_ADLIB_INST/IP_INTERFACE_50:C,
MSS_ADLIB_INST/IP_INTERFACE_50:IPA,
MSS_ADLIB_INST/IP_INTERFACE_50:IPB,
MDDR_DDR_AXI_S_ARLEN_ibuf[3]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARLEN_ibuf[3]/U0/U_IOINFF:Y,
GPIO_2_M2F_obuf/U0/U_IOENFF:A,
GPIO_2_M2F_obuf/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[35]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[35]/U0/U_IOOUTFF:Y,
FIC_2_APB_M_PADDR_obuf[6]/U0/U_IOPAD:D,
FIC_2_APB_M_PADDR_obuf[6]/U0/U_IOPAD:E,
FIC_2_APB_M_PADDR_obuf[6]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[15]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[15]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HADDR_ibuf[2]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[2]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[30]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[30]/U0/U_IOENFF:Y,
FIC_2_APB_M_PADDR_obuf[12]/U0/U_IOPAD:D,
FIC_2_APB_M_PADDR_obuf[12]/U0/U_IOPAD:E,
FIC_2_APB_M_PADDR_obuf[12]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWSIZE_ibuf[1]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWSIZE_ibuf[1]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_117:A,
MSS_ADLIB_INST/IP_INTERFACE_117:B,
MSS_ADLIB_INST/IP_INTERFACE_117:C,
MSS_ADLIB_INST/IP_INTERFACE_117:IPA,
MSS_ADLIB_INST/IP_INTERFACE_117:IPB,
MDDR_DQ_8_PAD/U_IOINFF:A,
MDDR_DQ_8_PAD/U_IOINFF:Y,
MDDR_DDR_AXI_S_RLAST_obuf/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RLAST_obuf/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RLAST_obuf/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[26]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[26]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[41]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[41]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[41]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RDATA_obuf[37]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[37]/U0/U_IOENFF:Y,
MDDR_APB_S_PADDR_ibuf[8]/U0/U_IOPAD:PAD,
MDDR_APB_S_PADDR_ibuf[8]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_172:A,
MSS_ADLIB_INST/IP_INTERFACE_172:B,
MSS_ADLIB_INST/IP_INTERFACE_172:C,
MSS_ADLIB_INST/IP_INTERFACE_172:IPA,
MSS_ADLIB_INST/IP_INTERFACE_172:IPB,
FIC_0_AHB_S_HRDATA_obuf[1]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[1]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[1]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HRDATA_obuf[1]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[1]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_RRESP_obuf[1]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RRESP_obuf[1]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_AWID_ibuf[1]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWID_ibuf[1]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_310:A,
MSS_ADLIB_INST/IP_INTERFACE_310:B,
MSS_ADLIB_INST/IP_INTERFACE_310:C,
MSS_ADLIB_INST/IP_INTERFACE_310:IPB,
MDDR_APB_S_PWDATA_ibuf[7]/U0/U_IOINFF:A,
MDDR_APB_S_PWDATA_ibuf[7]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[14]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[14]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RID_obuf[1]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RID_obuf[1]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_369:A,
MSS_ADLIB_INST/IP_INTERFACE_369:B,
MSS_ADLIB_INST/IP_INTERFACE_369:C,
MSS_ADLIB_INST/IP_INTERFACE_369:IPA,
MDDR_DQS_0_PAD/U_IOINFF:A,
MDDR_DQS_0_PAD/U_IOINFF:Y,
MDDR_DDR_AXI_S_RID_obuf[3]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RID_obuf[3]/U0/U_IOOUTFF:Y,
SPI_0_CLK_PAD/U_IOINFF:A,
SPI_0_CLK_PAD/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_1:A,
MSS_ADLIB_INST/IP_INTERFACE_1:B,
MSS_ADLIB_INST/IP_INTERFACE_1:C,
MSS_ADLIB_INST/IP_INTERFACE_1:IPA,
MDDR_DDR_AXI_S_WDATA_ibuf[47]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[47]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HADDR_ibuf[12]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[12]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[4]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[4]/U0/U_IOENFF:Y,
FIC_2_APB_M_PWDATA_obuf[22]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[22]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[22]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PWDATA_obuf[18]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[18]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[18]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_342:A,
MSS_ADLIB_INST/IP_INTERFACE_342:B,
MSS_ADLIB_INST/IP_INTERFACE_342:C,
MSS_ADLIB_INST/IP_INTERFACE_342:IPA,
MSS_ADLIB_INST/IP_INTERFACE_342:IPB,
MSS_ADLIB_INST/IP_INTERFACE_220:A,
MSS_ADLIB_INST/IP_INTERFACE_220:B,
MSS_ADLIB_INST/IP_INTERFACE_220:C,
MSS_ADLIB_INST/IP_INTERFACE_220:IPA,
MSS_ADLIB_INST/IP_INTERFACE_220:IPB,
MDDR_DDR_AXI_S_BID_obuf[2]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_BID_obuf[2]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_55:A,
MSS_ADLIB_INST/IP_INTERFACE_55:B,
MSS_ADLIB_INST/IP_INTERFACE_55:C,
MSS_ADLIB_INST/IP_INTERFACE_55:IPA,
MSS_ADLIB_INST/IP_INTERFACE_55:IPB,
FIC_2_APB_M_PWRITE_obuf/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWRITE_obuf/U0/U_IOOUTFF:Y,
FIC_2_APB_M_PRDATA_ibuf[8]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[8]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_221:A,
MSS_ADLIB_INST/IP_INTERFACE_221:B,
MSS_ADLIB_INST/IP_INTERFACE_221:C,
MSS_ADLIB_INST/IP_INTERFACE_221:IPA,
MSS_ADLIB_INST/IP_INTERFACE_221:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[18]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[18]/U0/U_IOOUTFF:Y,
FIC_2_APB_M_PWDATA_obuf[2]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[2]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[2]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WID_ibuf[1]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WID_ibuf[1]/U0/U_IOPAD:Y,
FIC_2_APB_M_PRDATA_ibuf[15]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[15]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[4]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[4]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HRDATA_obuf[2]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[2]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[30]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[30]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HWDATA_ibuf[25]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[25]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_276:A,
MSS_ADLIB_INST/IP_INTERFACE_276:B,
MSS_ADLIB_INST/IP_INTERFACE_276:C,
MSS_ADLIB_INST/IP_INTERFACE_276:IPA,
MSS_ADLIB_INST/IP_INTERFACE_136:A,
MSS_ADLIB_INST/IP_INTERFACE_136:B,
MSS_ADLIB_INST/IP_INTERFACE_136:C,
MSS_ADLIB_INST/IP_INTERFACE_136:IPA,
MSS_ADLIB_INST/IP_INTERFACE_136:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[33]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[33]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_16:A,
MSS_ADLIB_INST/IP_INTERFACE_16:B,
MSS_ADLIB_INST/IP_INTERFACE_16:C,
MSS_ADLIB_INST/IP_INTERFACE_16:IPA,
MSS_ADLIB_INST/IP_INTERFACE_16:IPB,
MDDR_APB_S_PRDATA_obuf[4]/U0/U_IOPAD:D,
MDDR_APB_S_PRDATA_obuf[4]/U0/U_IOPAD:E,
MDDR_APB_S_PRDATA_obuf[4]/U0/U_IOPAD:PAD,
ip_interface_inst:A,
ip_interface_inst:B,
ip_interface_inst:C,
FIC_2_APB_M_PWDATA_obuf[20]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[20]/U0/U_IOENFF:Y,
MDDR_APB_S_PRDATA_obuf[7]/U0/U_IOENFF:A,
MDDR_APB_S_PRDATA_obuf[7]/U0/U_IOENFF:Y,
MDDR_ODT_PAD/U_IOPAD:D,
MDDR_ODT_PAD/U_IOPAD:E,
MDDR_ODT_PAD/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[28]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[28]/U0/U_IOINFF:Y,
FIC_2_APB_M_PWDATA_obuf[26]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[26]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[26]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[14]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[14]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HTRANS_ibuf[1]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HTRANS_ibuf[1]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_302:A,
MSS_ADLIB_INST/IP_INTERFACE_302:B,
MSS_ADLIB_INST/IP_INTERFACE_302:C,
MSS_ADLIB_INST/IP_INTERFACE_302:IPA,
MSS_ADLIB_INST/IP_INTERFACE_302:IPB,
MDDR_APB_S_PSLVERR_obuf/U0/U_IOENFF:A,
MDDR_APB_S_PSLVERR_obuf/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[34]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[34]/U0/U_IOINFF:Y,
MDDR_ADDR_3_PAD/U_IOPAD:D,
MDDR_ADDR_3_PAD/U_IOPAD:E,
MDDR_ADDR_3_PAD/U_IOPAD:PAD,
FIC_2_APB_M_PWDATA_obuf[31]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[31]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[31]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RDATA_obuf[10]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[10]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[10]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[6]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[6]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HADDR_ibuf[11]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[11]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HMASTLOCK_ibuf/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HMASTLOCK_ibuf/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[30]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[30]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[30]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[5]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[5]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[44]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[44]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[19]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[19]/U0/U_IOENFF:Y,
MDDR_APB_S_PRDATA_obuf[9]/U0/U_IOPAD:D,
MDDR_APB_S_PRDATA_obuf[9]/U0/U_IOPAD:E,
MDDR_APB_S_PRDATA_obuf[9]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HRDATA_obuf[13]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[13]/U0/U_IOENFF:Y,
MDDR_APB_S_PWDATA_ibuf[12]/U0/U_IOPAD:PAD,
MDDR_APB_S_PWDATA_ibuf[12]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[10]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[10]/U0/U_IOPAD:Y,
GPIO_4_M2F_obuf/U0/U_IOENFF:A,
GPIO_4_M2F_obuf/U0/U_IOENFF:Y,
MDDR_DQ_2_PAD/U_IOPAD:D,
MDDR_DQ_2_PAD/U_IOPAD:E,
MDDR_DQ_2_PAD/U_IOPAD:PAD,
MDDR_DQ_2_PAD/U_IOPAD:Y,
MDDR_ADDR_4_PAD/U_IOPAD:D,
MDDR_ADDR_4_PAD/U_IOPAD:E,
MDDR_ADDR_4_PAD/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_336:A,
MSS_ADLIB_INST/IP_INTERFACE_336:B,
MSS_ADLIB_INST/IP_INTERFACE_336:C,
MSS_ADLIB_INST/IP_INTERFACE_336:IPA,
FIC_0_AHB_S_HADDR_ibuf[30]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[30]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_242:A,
MSS_ADLIB_INST/IP_INTERFACE_242:B,
MSS_ADLIB_INST/IP_INTERFACE_242:C,
MSS_ADLIB_INST/IP_INTERFACE_242:IPA,
MDDR_DDR_AXI_S_WDATA_ibuf[30]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[30]/U0/U_IOPAD:Y,
MDDR_DQ_14_PAD/U_IOINFF:A,
MDDR_DQ_14_PAD/U_IOINFF:Y,
MDDR_DQ_7_PAD/U_IOPAD:D,
MDDR_DQ_7_PAD/U_IOPAD:E,
MDDR_DQ_7_PAD/U_IOPAD:PAD,
MDDR_DQ_7_PAD/U_IOPAD:Y,
FIC_0_AHB_S_HADDR_ibuf[1]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[1]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[62]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[62]/U0/U_IOENFF:Y,
FIC_0_AHB_S_HRDATA_obuf[14]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[14]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[5]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[5]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_6:A,
MSS_ADLIB_INST/IP_INTERFACE_6:B,
MSS_ADLIB_INST/IP_INTERFACE_6:C,
MSS_ADLIB_INST/IP_INTERFACE_6:IPA,
MSS_ADLIB_INST/IP_INTERFACE_6:IPB,
FIC_0_AHB_S_HWDATA_ibuf[17]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[17]/U0/U_IOINFF:Y,
FIC_2_APB_M_PWDATA_obuf[25]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[25]/U0/U_IOENFF:Y,
FIC_0_AHB_S_HADDR_ibuf[8]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[8]/U0/U_IOPAD:Y,
MDDR_APB_S_PRDATA_obuf[11]/U0/U_IOPAD:D,
MDDR_APB_S_PRDATA_obuf[11]/U0/U_IOPAD:E,
MDDR_APB_S_PRDATA_obuf[11]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_352:A,
MSS_ADLIB_INST/IP_INTERFACE_352:B,
MSS_ADLIB_INST/IP_INTERFACE_352:C,
MSS_ADLIB_INST/IP_INTERFACE_352:IPA,
MSS_ADLIB_INST/IP_INTERFACE_268:A,
MSS_ADLIB_INST/IP_INTERFACE_268:B,
MSS_ADLIB_INST/IP_INTERFACE_268:C,
MSS_ADLIB_INST/IP_INTERFACE_268:IPA,
MSS_ADLIB_INST/IP_INTERFACE_268:IPB,
MDDR_DDR_AXI_S_AWADDR_ibuf[30]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[30]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_202:A,
MSS_ADLIB_INST/IP_INTERFACE_202:B,
MSS_ADLIB_INST/IP_INTERFACE_202:C,
MSS_ADLIB_INST/IP_INTERFACE_202:IPB,
FIC_2_APB_M_PRESET_N_obuf/U0/U_IOENFF:A,
FIC_2_APB_M_PRESET_N_obuf/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_91:A,
MSS_ADLIB_INST/IP_INTERFACE_91:B,
MSS_ADLIB_INST/IP_INTERFACE_91:C,
MSS_ADLIB_INST/IP_INTERFACE_91:IPA,
MSS_ADLIB_INST/IP_INTERFACE_91:IPB,
MSS_ADLIB_INST/IP_INTERFACE_124:A,
MSS_ADLIB_INST/IP_INTERFACE_124:B,
MSS_ADLIB_INST/IP_INTERFACE_124:C,
MSS_ADLIB_INST/IP_INTERFACE_124:IPA,
MSS_ADLIB_INST/IP_INTERFACE_124:IPB,
MSS_ADLIB_INST/IP_INTERFACE_18:A,
MSS_ADLIB_INST/IP_INTERFACE_18:B,
MSS_ADLIB_INST/IP_INTERFACE_18:C,
MSS_ADLIB_INST/IP_INTERFACE_18:IPA,
MSS_ADLIB_INST/IP_INTERFACE_18:IPB,
FIC_0_AHB_S_HADDR_ibuf[24]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[24]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[26]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[26]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_66:A,
MSS_ADLIB_INST/IP_INTERFACE_66:B,
MSS_ADLIB_INST/IP_INTERFACE_66:C,
MSS_ADLIB_INST/IP_INTERFACE_66:IPA,
MSS_ADLIB_INST/IP_INTERFACE_66:IPB,
MSS_ADLIB_INST/IP_INTERFACE_223:A,
MSS_ADLIB_INST/IP_INTERFACE_223:B,
MSS_ADLIB_INST/IP_INTERFACE_223:C,
MSS_ADLIB_INST/IP_INTERFACE_223:IPA,
MSS_ADLIB_INST/IP_INTERFACE_223:IPB,
MDDR_DDR_AXI_S_BID_obuf[1]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_BID_obuf[1]/U0/U_IOENFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[10]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[10]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_373:A,
MSS_ADLIB_INST/IP_INTERFACE_373:B,
MSS_ADLIB_INST/IP_INTERFACE_373:C,
MSS_ADLIB_INST/IP_INTERFACE_373:IPA,
MSS_ADLIB_INST/IP_INTERFACE_215:A,
MSS_ADLIB_INST/IP_INTERFACE_215:B,
MSS_ADLIB_INST/IP_INTERFACE_215:C,
MSS_ADLIB_INST/IP_INTERFACE_215:IPB,
FIC_2_APB_M_PWDATA_obuf[21]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[21]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[34]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[34]/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HADDR_ibuf[9]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[9]/U0/U_IOINFF:Y,
MDDR_DDR_CORE_RESET_N_ibuf/U0/U_IOINFF:A,
MDDR_DDR_CORE_RESET_N_ibuf/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_196:A,
MSS_ADLIB_INST/IP_INTERFACE_196:B,
MSS_ADLIB_INST/IP_INTERFACE_196:C,
MSS_ADLIB_INST/IP_INTERFACE_196:IPA,
MSS_ADLIB_INST/IP_INTERFACE_196:IPB,
FIC_2_APB_M_PWDATA_obuf[2]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[2]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[59]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[59]/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HADDR_ibuf[7]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[7]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[1]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[1]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_53:A,
MSS_ADLIB_INST/IP_INTERFACE_53:B,
MSS_ADLIB_INST/IP_INTERFACE_53:C,
MSS_ADLIB_INST/IP_INTERFACE_53:IPA,
MSS_ADLIB_INST/IP_INTERFACE_53:IPB,
FIC_2_APB_M_PRDATA_ibuf[3]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[3]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_AWLEN_ibuf[0]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWLEN_ibuf[0]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[6]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[6]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_349:A,
MSS_ADLIB_INST/IP_INTERFACE_349:B,
MSS_ADLIB_INST/IP_INTERFACE_349:C,
MSS_ADLIB_INST/IP_INTERFACE_349:IPA,
MSS_ADLIB_INST/IP_INTERFACE_349:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[20]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[20]/U0/U_IOOUTFF:Y,
FIC_2_APB_M_PWDATA_obuf[10]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[10]/U0/U_IOENFF:Y,
MDDR_DQS_TMATCH_0_OUT_PAD/U_IOPAD:D,
MDDR_DQS_TMATCH_0_OUT_PAD/U_IOPAD:E,
MDDR_DQS_TMATCH_0_OUT_PAD/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RDATA_obuf[21]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[21]/U0/U_IOOUTFF:Y,
FIC_2_APB_M_PADDR_obuf[10]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PADDR_obuf[10]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[18]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[18]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_252:A,
MSS_ADLIB_INST/IP_INTERFACE_252:B,
MSS_ADLIB_INST/IP_INTERFACE_252:C,
MSS_ADLIB_INST/IP_INTERFACE_252:IPA,
MDDR_APB_S_PRDATA_obuf[6]/U0/U_IOPAD:D,
MDDR_APB_S_PRDATA_obuf[6]/U0/U_IOPAD:E,
MDDR_APB_S_PRDATA_obuf[6]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_274:A,
MSS_ADLIB_INST/IP_INTERFACE_274:B,
MSS_ADLIB_INST/IP_INTERFACE_274:C,
MSS_ADLIB_INST/IP_INTERFACE_274:IPB,
MDDR_DDR_AXI_S_AWLEN_ibuf[3]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWLEN_ibuf[3]/U0/U_IOPAD:Y,
FIC_2_APB_M_PADDR_obuf[2]/U0/U_IOPAD:D,
FIC_2_APB_M_PADDR_obuf[2]/U0/U_IOPAD:E,
FIC_2_APB_M_PADDR_obuf[2]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[28]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[28]/U0/U_IOINFF:Y,
MDDR_CLK_PAD/U_IOPADP:EIN_P,
MDDR_CLK_PAD/U_IOPADP:OIN_P,
MDDR_CLK_PAD/U_IOPADP:PAD_P,
MDDR_DDR_AXI_S_WREADY_obuf/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_WREADY_obuf/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_288:A,
MSS_ADLIB_INST/IP_INTERFACE_288:B,
MSS_ADLIB_INST/IP_INTERFACE_288:C,
MSS_ADLIB_INST/IP_INTERFACE_288:IPA,
MSS_ADLIB_INST/IP_INTERFACE_161:A,
MSS_ADLIB_INST/IP_INTERFACE_161:B,
MSS_ADLIB_INST/IP_INTERFACE_161:C,
MSS_ADLIB_INST/IP_INTERFACE_161:IPA,
MSS_ADLIB_INST/IP_INTERFACE_161:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[5]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[5]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_309:A,
MSS_ADLIB_INST/IP_INTERFACE_309:B,
MSS_ADLIB_INST/IP_INTERFACE_309:C,
MSS_ADLIB_INST/IP_INTERFACE_309:IPA,
MSS_ADLIB_INST/IP_INTERFACE_309:IPB,
MDDR_DDR_AXI_S_AWADDR_ibuf[27]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[27]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[16]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[16]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[16]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_BVALID_obuf/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_BVALID_obuf/U0/U_IOOUTFF:Y,
FIC_2_APB_M_PADDR_obuf[6]/U0/U_IOENFF:A,
FIC_2_APB_M_PADDR_obuf[6]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_14:A,
MSS_ADLIB_INST/IP_INTERFACE_14:B,
MSS_ADLIB_INST/IP_INTERFACE_14:C,
MSS_ADLIB_INST/IP_INTERFACE_14:IPB,
FIC_2_APB_M_PRDATA_ibuf[30]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[30]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[2]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[2]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_ARSIZE_ibuf[0]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARSIZE_ibuf[0]/U0/U_IOINFF:Y,
MDDR_APB_S_PADDR_ibuf[2]/U0/U_IOINFF:A,
MDDR_APB_S_PADDR_ibuf[2]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[43]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[43]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[36]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[36]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[36]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HRDATA_obuf[31]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[31]/U0/U_IOENFF:Y,
FIC_0_AHB_S_HRDATA_obuf[24]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[24]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_ARLEN_ibuf[1]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARLEN_ibuf[1]/U0/U_IOPAD:Y,
MDDR_APB_S_PWDATA_ibuf[15]/U0/U_IOPAD:PAD,
MDDR_APB_S_PWDATA_ibuf[15]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_68:A,
MSS_ADLIB_INST/IP_INTERFACE_68:B,
MSS_ADLIB_INST/IP_INTERFACE_68:C,
MSS_ADLIB_INST/IP_INTERFACE_68:IPA,
MSS_ADLIB_INST/IP_INTERFACE_68:IPB,
MDDR_APB_S_PWDATA_ibuf[5]/U0/U_IOINFF:A,
MDDR_APB_S_PWDATA_ibuf[5]/U0/U_IOINFF:Y,
FIC_2_APB_M_PADDR_obuf[11]/U0/U_IOPAD:D,
FIC_2_APB_M_PADDR_obuf[11]/U0/U_IOPAD:E,
FIC_2_APB_M_PADDR_obuf[11]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[21]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[21]/U0/U_IOINFF:Y,
MDDR_WE_N_PAD/U_IOPAD:D,
MDDR_WE_N_PAD/U_IOPAD:E,
MDDR_WE_N_PAD/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[2]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[2]/U0/U_IOPAD:Y,
MMUART_0_TXD_PAD/U_IOPAD:D,
MMUART_0_TXD_PAD/U_IOPAD:E,
MMUART_0_TXD_PAD/U_IOPAD:PAD,
FIC_2_APB_M_PWDATA_obuf[15]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[15]/U0/U_IOENFF:Y,
FIC_0_AHB_S_HADDR_ibuf[18]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[18]/U0/U_IOINFF:Y,
GPIO_10_M2F_obuf/U0/U_IOPAD:D,
GPIO_10_M2F_obuf/U0/U_IOPAD:E,
GPIO_10_M2F_obuf/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARREADY_obuf/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_ARREADY_obuf/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_217:A,
MSS_ADLIB_INST/IP_INTERFACE_217:B,
MSS_ADLIB_INST/IP_INTERFACE_217:C,
MSS_ADLIB_INST/IP_INTERFACE_217:IPA,
FIC_2_APB_M_PADDR_obuf[2]/U0/U_IOENFF:A,
FIC_2_APB_M_PADDR_obuf[2]/U0/U_IOENFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[23]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[23]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[29]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[29]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_10:A,
MSS_ADLIB_INST/IP_INTERFACE_10:B,
MSS_ADLIB_INST/IP_INTERFACE_10:C,
MSS_ADLIB_INST/IP_INTERFACE_10:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[9]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[9]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[9]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[19]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[19]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[55]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[55]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[6]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[6]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_332:A,
MSS_ADLIB_INST/IP_INTERFACE_332:B,
MSS_ADLIB_INST/IP_INTERFACE_332:C,
MSS_ADLIB_INST/IP_INTERFACE_332:IPA,
MSS_ADLIB_INST/IP_INTERFACE_332:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[58]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[58]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[58]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[58]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[58]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[19]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[19]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_374:A,
MSS_ADLIB_INST/IP_INTERFACE_374:B,
MSS_ADLIB_INST/IP_INTERFACE_374:C,
MSS_ADLIB_INST/IP_INTERFACE_374:IPA,
MDDR_DDR_AXI_S_WDATA_ibuf[45]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[45]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_59:A,
MSS_ADLIB_INST/IP_INTERFACE_59:B,
MSS_ADLIB_INST/IP_INTERFACE_59:C,
MSS_ADLIB_INST/IP_INTERFACE_59:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[52]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[52]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[46]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[46]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HADDR_ibuf[31]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[31]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HADDR_ibuf[29]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[29]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_181:A,
MSS_ADLIB_INST/IP_INTERFACE_181:B,
MSS_ADLIB_INST/IP_INTERFACE_181:C,
MSS_ADLIB_INST/IP_INTERFACE_181:IPA,
FIC_2_APB_M_PADDR_obuf[7]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PADDR_obuf[7]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_219:A,
MSS_ADLIB_INST/IP_INTERFACE_219:B,
MSS_ADLIB_INST/IP_INTERFACE_219:C,
MSS_ADLIB_INST/IP_INTERFACE_219:IPA,
MSS_ADLIB_INST/IP_INTERFACE_219:IPB,
MDDR_ADDR_15_PAD/U_IOPAD:D,
MDDR_ADDR_15_PAD/U_IOPAD:E,
MDDR_ADDR_15_PAD/U_IOPAD:PAD,
FIC_2_APB_M_PWDATA_obuf[27]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[27]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[27]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWSIZE_ibuf[0]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWSIZE_ibuf[0]/U0/U_IOINFF:Y,
FIC_2_APB_M_PWDATA_obuf[29]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[29]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[29]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[28]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[28]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_318:A,
MSS_ADLIB_INST/IP_INTERFACE_318:B,
MSS_ADLIB_INST/IP_INTERFACE_318:C,
MSS_ADLIB_INST/IP_INTERFACE_318:IPA,
MSS_ADLIB_INST/IP_INTERFACE_318:IPB,
MDDR_APB_S_PADDR_ibuf[10]/U0/U_IOPAD:PAD,
MDDR_APB_S_PADDR_ibuf[10]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HADDR_ibuf[4]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[4]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_AWLEN_ibuf[3]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWLEN_ibuf[3]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[22]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[22]/U0/U_IOPAD:Y,
MDDR_ADDR_8_PAD/U_IOPAD:D,
MDDR_ADDR_8_PAD/U_IOPAD:E,
MDDR_ADDR_8_PAD/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_64:A,
MSS_ADLIB_INST/IP_INTERFACE_64:B,
MSS_ADLIB_INST/IP_INTERFACE_64:C,
MSS_ADLIB_INST/IP_INTERFACE_64:IPA,
MSS_ADLIB_INST/IP_INTERFACE_64:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[31]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[31]/U0/U_IOINFF:Y,
MDDR_APB_S_PRDATA_obuf[13]/U0/U_IOENFF:A,
MDDR_APB_S_PRDATA_obuf[13]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_15:A,
MSS_ADLIB_INST/IP_INTERFACE_15:B,
MSS_ADLIB_INST/IP_INTERFACE_15:C,
MSS_ADLIB_INST/IP_INTERFACE_15:IPA,
MSS_ADLIB_INST/IP_INTERFACE_15:IPB,
FIC_2_APB_M_PRESET_N_obuf/U0/U_IOOUTFF:A,
FIC_2_APB_M_PRESET_N_obuf/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[2]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[2]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HADDR_ibuf[3]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[3]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_315:A,
MSS_ADLIB_INST/IP_INTERFACE_315:B,
MSS_ADLIB_INST/IP_INTERFACE_315:C,
MSS_ADLIB_INST/IP_INTERFACE_315:IPA,
MSS_ADLIB_INST/IP_INTERFACE_315:IPB,
FIC_0_AHB_S_HRDATA_obuf[7]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[7]/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HRDATA_obuf[17]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[17]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_208:A,
MSS_ADLIB_INST/IP_INTERFACE_208:B,
MSS_ADLIB_INST/IP_INTERFACE_208:C,
MSS_ADLIB_INST/IP_INTERFACE_208:IPA,
MSS_ADLIB_INST/IP_INTERFACE_208:IPB,
MSS_ADLIB_INST/IP_INTERFACE_81:A,
MSS_ADLIB_INST/IP_INTERFACE_81:B,
MSS_ADLIB_INST/IP_INTERFACE_81:C,
MSS_ADLIB_INST/IP_INTERFACE_81:IPA,
MSS_ADLIB_INST/IP_INTERFACE_81:IPB,
FIC_2_APB_M_PENABLE_obuf/U0/U_IOENFF:A,
FIC_2_APB_M_PENABLE_obuf/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_232:A,
MSS_ADLIB_INST/IP_INTERFACE_232:B,
MSS_ADLIB_INST/IP_INTERFACE_232:C,
MSS_ADLIB_INST/IP_INTERFACE_232:IPA,
MSS_ADLIB_INST/IP_INTERFACE_232:IPB,
MSS_ADLIB_INST/IP_INTERFACE_260:A,
MSS_ADLIB_INST/IP_INTERFACE_260:B,
MSS_ADLIB_INST/IP_INTERFACE_260:C,
MSS_ADLIB_INST/IP_INTERFACE_260:IPA,
MSS_ADLIB_INST/IP_INTERFACE_260:IPB,
MDDR_DQ_10_PAD/U_IOINFF:A,
MDDR_DQ_10_PAD/U_IOINFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[62]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[62]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_BID_obuf[3]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_BID_obuf[3]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_BID_obuf[3]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_BID_obuf[2]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_BID_obuf[2]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_261:A,
MSS_ADLIB_INST/IP_INTERFACE_261:B,
MSS_ADLIB_INST/IP_INTERFACE_261:C,
MSS_ADLIB_INST/IP_INTERFACE_261:IPA,
MSS_ADLIB_INST/IP_INTERFACE_261:IPB,
FIC_0_AHB_S_HADDR_ibuf[22]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[22]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_60:A,
MSS_ADLIB_INST/IP_INTERFACE_60:B,
MSS_ADLIB_INST/IP_INTERFACE_60:C,
MSS_ADLIB_INST/IP_INTERFACE_60:IPA,
FIC_2_APB_M_PWDATA_obuf[27]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[27]/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[23]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[23]/U0/U_IOPAD:Y,
MDDR_DQ_4_PAD/U_IOINFF:A,
MDDR_DQ_4_PAD/U_IOINFF:Y,
FIC_0_AHB_S_HRDATA_obuf[27]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[27]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[27]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[31]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[31]/U0/U_IOINFF:Y,
MDDR_ADDR_13_PAD/U_IOPAD:D,
MDDR_ADDR_13_PAD/U_IOPAD:E,
MDDR_ADDR_13_PAD/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARLOCK_ibuf[1]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARLOCK_ibuf[1]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[4]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[4]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[53]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[53]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[15]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[15]/U0/U_IOOUTFF:Y,
MDDR_APB_S_PRESET_N_ibuf/U0/U_IOINFF:A,
MDDR_APB_S_PRESET_N_ibuf/U0/U_IOINFF:Y,
FIC_2_APB_M_PRDATA_ibuf[21]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[21]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_WSTRB_ibuf[1]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WSTRB_ibuf[1]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_128:A,
MSS_ADLIB_INST/IP_INTERFACE_128:B,
MSS_ADLIB_INST/IP_INTERFACE_128:C,
MSS_ADLIB_INST/IP_INTERFACE_128:IPA,
MSS_ADLIB_INST/IP_INTERFACE_128:IPB,
FIC_2_APB_M_PADDR_obuf[11]/U0/U_IOENFF:A,
FIC_2_APB_M_PADDR_obuf[11]/U0/U_IOENFF:Y,
FIC_0_AHB_S_HRDATA_obuf[8]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[8]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_141:A,
MSS_ADLIB_INST/IP_INTERFACE_141:B,
MSS_ADLIB_INST/IP_INTERFACE_141:C,
MSS_ADLIB_INST/IP_INTERFACE_141:IPA,
MSS_ADLIB_INST/IP_INTERFACE_141:IPB,
MDDR_APB_S_PWDATA_ibuf[3]/U0/U_IOINFF:A,
MDDR_APB_S_PWDATA_ibuf[3]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARLEN_ibuf[1]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARLEN_ibuf[1]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HRDATA_obuf[22]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[22]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[22]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RDATA_obuf[42]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[42]/U0/U_IOENFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[5]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[5]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_258:A,
MSS_ADLIB_INST/IP_INTERFACE_258:B,
MSS_ADLIB_INST/IP_INTERFACE_258:C,
MSS_ADLIB_INST/IP_INTERFACE_258:IPA,
MSS_ADLIB_INST/IP_INTERFACE_258:IPB,
MSS_ADLIB_INST/IP_INTERFACE_110:A,
MSS_ADLIB_INST/IP_INTERFACE_110:B,
MSS_ADLIB_INST/IP_INTERFACE_110:C,
MSS_ADLIB_INST/IP_INTERFACE_110:IPA,
MSS_ADLIB_INST/IP_INTERFACE_110:IPB,
MDDR_APB_S_PSLVERR_obuf/U0/U_IOOUTFF:A,
MDDR_APB_S_PSLVERR_obuf/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_129:A,
MSS_ADLIB_INST/IP_INTERFACE_129:B,
MSS_ADLIB_INST/IP_INTERFACE_129:C,
MSS_ADLIB_INST/IP_INTERFACE_129:IPA,
MSS_ADLIB_INST/IP_INTERFACE_129:IPB,
MDDR_DDR_AXI_S_AWADDR_ibuf[11]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[11]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[46]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[46]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[25]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[25]/U0/U_IOPAD:Y,
MDDR_APB_S_PWDATA_ibuf[1]/U0/U_IOPAD:PAD,
MDDR_APB_S_PWDATA_ibuf[1]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_65:A,
MSS_ADLIB_INST/IP_INTERFACE_65:B,
MSS_ADLIB_INST/IP_INTERFACE_65:C,
MSS_ADLIB_INST/IP_INTERFACE_65:IPA,
MSS_ADLIB_INST/IP_INTERFACE_65:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[9]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[9]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[54]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[54]/U0/U_IOPAD:Y,
MCCC_CLK_BASE_ibuf/U0/U_IOPAD:PAD,
MCCC_CLK_BASE_ibuf/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_317:A,
MSS_ADLIB_INST/IP_INTERFACE_317:B,
MSS_ADLIB_INST/IP_INTERFACE_317:C,
MSS_ADLIB_INST/IP_INTERFACE_317:IPA,
MSS_ADLIB_INST/IP_INTERFACE_317:IPB,
MSS_ADLIB_INST/IP_INTERFACE_101:A,
MSS_ADLIB_INST/IP_INTERFACE_101:B,
MSS_ADLIB_INST/IP_INTERFACE_101:C,
MSS_ADLIB_INST/IP_INTERFACE_101:IPA,
MSS_ADLIB_INST/IP_INTERFACE_101:IPB,
MDDR_DQ_7_PAD/U_IOINFF:A,
MDDR_DQ_7_PAD/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_339:A,
MSS_ADLIB_INST/IP_INTERFACE_339:B,
MSS_ADLIB_INST/IP_INTERFACE_339:C,
MSS_ADLIB_INST/IP_INTERFACE_339:IPA,
MSS_ADLIB_INST/IP_INTERFACE_339:IPB,
MSS_ADLIB_INST/IP_INTERFACE_32:A,
MSS_ADLIB_INST/IP_INTERFACE_32:B,
MSS_ADLIB_INST/IP_INTERFACE_32:C,
MSS_ADLIB_INST/IP_INTERFACE_32:IPA,
MSS_ADLIB_INST/IP_INTERFACE_32:IPB,
FIC_0_AHB_S_HRDATA_obuf[18]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[18]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[18]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_280:A,
MSS_ADLIB_INST/IP_INTERFACE_280:B,
MSS_ADLIB_INST/IP_INTERFACE_280:C,
MSS_ADLIB_INST/IP_INTERFACE_280:IPA,
MSS_ADLIB_INST/IP_INTERFACE_280:IPB,
MDDR_DQ_10_PAD/U_IOPAD:D,
MDDR_DQ_10_PAD/U_IOPAD:E,
MDDR_DQ_10_PAD/U_IOPAD:PAD,
MDDR_DQ_10_PAD/U_IOPAD:Y,
FIC_2_APB_M_PRDATA_ibuf[26]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[26]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[38]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[38]/U0/U_IOINFF:Y,
FIC_2_APB_M_PRDATA_ibuf[27]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[27]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[55]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[55]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[55]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[21]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[21]/U0/U_IOPAD:Y,
SPI_0_SS0_PAD/U_IOPAD:D,
SPI_0_SS0_PAD/U_IOPAD:E,
SPI_0_SS0_PAD/U_IOPAD:PAD,
SPI_0_SS0_PAD/U_IOPAD:Y,
FIC_2_APB_M_PWDATA_obuf[27]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[27]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_164:A,
MSS_ADLIB_INST/IP_INTERFACE_164:B,
MSS_ADLIB_INST/IP_INTERFACE_164:C,
MSS_ADLIB_INST/IP_INTERFACE_164:IPA,
MSS_ADLIB_INST/IP_INTERFACE_164:IPB,
MDDR_DQ_13_PAD/U_IOINFF:A,
MDDR_DQ_13_PAD/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[54]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[54]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[23]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[23]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[55]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[55]/U0/U_IOENFF:Y,
MDDR_APB_S_PADDR_ibuf[6]/U0/U_IOINFF:A,
MDDR_APB_S_PADDR_ibuf[6]/U0/U_IOINFF:Y,
FIC_2_APB_M_PADDR_obuf[12]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PADDR_obuf[12]/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HRDATA_obuf[3]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[3]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[3]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_292:A,
MSS_ADLIB_INST/IP_INTERFACE_292:B,
MSS_ADLIB_INST/IP_INTERFACE_292:C,
MSS_ADLIB_INST/IP_INTERFACE_292:IPA,
MSS_ADLIB_INST/IP_INTERFACE_292:IPB,
MDDR_DQ_13_PAD/U_IOPAD:D,
MDDR_DQ_13_PAD/U_IOPAD:E,
MDDR_DQ_13_PAD/U_IOPAD:PAD,
MDDR_DQ_13_PAD/U_IOPAD:Y,
FIC_2_APB_M_PWDATA_obuf[20]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[20]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_263:A,
MSS_ADLIB_INST/IP_INTERFACE_263:B,
MSS_ADLIB_INST/IP_INTERFACE_263:C,
MSS_ADLIB_INST/IP_INTERFACE_263:IPB,
FIC_2_APB_M_PRDATA_ibuf[9]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[9]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HWDATA_ibuf[26]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[26]/U0/U_IOPAD:Y,
FIC_2_APB_M_PADDR_obuf[14]/U0/U_IOENFF:A,
FIC_2_APB_M_PADDR_obuf[14]/U0/U_IOENFF:Y,
MDDR_APB_S_PRDATA_obuf[14]/U0/U_IOENFF:A,
MDDR_APB_S_PRDATA_obuf[14]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[20]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[20]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[20]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[1]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[1]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[0]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[0]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[2]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[2]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[25]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[25]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_ARBURST_ibuf[0]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARBURST_ibuf[0]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_72:A,
MSS_ADLIB_INST/IP_INTERFACE_72:B,
MSS_ADLIB_INST/IP_INTERFACE_72:C,
MSS_ADLIB_INST/IP_INTERFACE_72:IPA,
MDDR_DQS_1_PAD/U_IOPADN:EIN_P,
MDDR_DQS_1_PAD/U_IOPADN:N2POUT_P,
MDDR_DQS_1_PAD/U_IOPADN:OIN_P,
MDDR_DQS_1_PAD/U_IOPADN:PAD_P,
MDDR_APB_S_PRDATA_obuf[1]/U0/U_IOOUTFF:A,
MDDR_APB_S_PRDATA_obuf[1]/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HRDATA_obuf[31]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[31]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_151:A,
MSS_ADLIB_INST/IP_INTERFACE_151:B,
MSS_ADLIB_INST/IP_INTERFACE_151:C,
MSS_ADLIB_INST/IP_INTERFACE_151:IPA,
MSS_ADLIB_INST/IP_INTERFACE_151:IPB,
MDDR_DDR_AXI_S_RREADY_ibuf/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RREADY_ibuf/U0/U_IOPAD:Y,
FIC_2_APB_M_PSEL_obuf/U0/U_IOOUTFF:A,
FIC_2_APB_M_PSEL_obuf/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HADDR_ibuf[10]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[10]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RREADY_ibuf/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_RREADY_ibuf/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[54]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[54]/U0/U_IOENFF:Y,
FIC_0_AHB_S_HRDATA_obuf[14]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[14]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_311:A,
MSS_ADLIB_INST/IP_INTERFACE_311:B,
MSS_ADLIB_INST/IP_INTERFACE_311:C,
MSS_ADLIB_INST/IP_INTERFACE_311:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[42]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[42]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[42]/U0/U_IOPAD:PAD,
MDDR_DQ_3_PAD/U_IOINFF:A,
MDDR_DQ_3_PAD/U_IOINFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[20]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[20]/U0/U_IOPAD:Y,
MDDR_APB_S_PRDATA_obuf[7]/U0/U_IOPAD:D,
MDDR_APB_S_PRDATA_obuf[7]/U0/U_IOPAD:E,
MDDR_APB_S_PRDATA_obuf[7]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[41]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[41]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WSTRB_ibuf[1]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WSTRB_ibuf[1]/U0/U_IOINFF:Y,
FIC_2_APB_M_PRDATA_ibuf[11]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[11]/U0/U_IOINFF:Y,
FIC_2_APB_M_PADDR_obuf[14]/U0/U_IOPAD:D,
FIC_2_APB_M_PADDR_obuf[14]/U0/U_IOPAD:E,
FIC_2_APB_M_PADDR_obuf[14]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PWDATA_obuf[21]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[21]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[21]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_240:A,
MSS_ADLIB_INST/IP_INTERFACE_240:B,
MSS_ADLIB_INST/IP_INTERFACE_240:C,
MSS_ADLIB_INST/IP_INTERFACE_240:IPA,
FIC_0_AHB_S_HWDATA_ibuf[13]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[13]/U0/U_IOINFF:Y,
FIC_2_APB_M_PRDATA_ibuf[31]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[31]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WSTRB_ibuf[3]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WSTRB_ibuf[3]/U0/U_IOINFF:Y,
FIC_2_APB_M_PWDATA_obuf[4]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[4]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_241:A,
MSS_ADLIB_INST/IP_INTERFACE_241:B,
MSS_ADLIB_INST/IP_INTERFACE_241:C,
MSS_ADLIB_INST/IP_INTERFACE_241:IPA,
FIC_0_AHB_S_HRDATA_obuf[26]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[26]/U0/U_IOOUTFF:Y,
MDDR_APB_S_PWDATA_ibuf[14]/U0/U_IOINFF:A,
MDDR_APB_S_PWDATA_ibuf[14]/U0/U_IOINFF:Y,
MDDR_APB_S_PADDR_ibuf[7]/U0/U_IOINFF:A,
MDDR_APB_S_PADDR_ibuf[7]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_AWSIZE_ibuf[0]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWSIZE_ibuf[0]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[14]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[14]/U0/U_IOPAD:Y,
FIC_2_APB_M_PRDATA_ibuf[3]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[3]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[3]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[3]/U0/U_IOENFF:Y,
MDDR_APB_S_PRDATA_obuf[12]/U0/U_IOPAD:D,
MDDR_APB_S_PRDATA_obuf[12]/U0/U_IOPAD:E,
MDDR_APB_S_PRDATA_obuf[12]/U0/U_IOPAD:PAD,
MDDR_APB_S_PADDR_ibuf[3]/U0/U_IOPAD:PAD,
MDDR_APB_S_PADDR_ibuf[3]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_238:A,
MSS_ADLIB_INST/IP_INTERFACE_238:B,
MSS_ADLIB_INST/IP_INTERFACE_238:C,
MSS_ADLIB_INST/IP_INTERFACE_238:IPB,
MSS_ADLIB_INST/IP_INTERFACE_184:A,
MSS_ADLIB_INST/IP_INTERFACE_184:B,
MSS_ADLIB_INST/IP_INTERFACE_184:C,
MSS_ADLIB_INST/IP_INTERFACE_184:IPA,
MSS_ADLIB_INST/IP_INTERFACE_184:IPB,
MDDR_DQ_1_PAD/U_IOINFF:A,
MDDR_DQ_1_PAD/U_IOINFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[19]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[19]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WID_ibuf[0]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WID_ibuf[0]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[47]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[47]/U0/U_IOINFF:Y,
MDDR_APB_S_PADDR_ibuf[4]/U0/U_IOPAD:PAD,
MDDR_APB_S_PADDR_ibuf[4]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[16]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[16]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HADDR_ibuf[26]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[26]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_200:A,
MSS_ADLIB_INST/IP_INTERFACE_200:B,
MSS_ADLIB_INST/IP_INTERFACE_200:C,
MSS_ADLIB_INST/IP_INTERFACE_200:IPA,
MSS_ADLIB_INST/IP_INTERFACE_200:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[39]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[39]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[1]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[1]/U0/U_IOPAD:Y,
FIC_2_APB_M_PWDATA_obuf[31]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[31]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_283:A,
MSS_ADLIB_INST/IP_INTERFACE_283:B,
MSS_ADLIB_INST/IP_INTERFACE_283:C,
MSS_ADLIB_INST/IP_INTERFACE_283:IPA,
MSS_ADLIB_INST/IP_INTERFACE_201:A,
MSS_ADLIB_INST/IP_INTERFACE_201:B,
MSS_ADLIB_INST/IP_INTERFACE_201:C,
MSS_ADLIB_INST/IP_INTERFACE_201:IPA,
MSS_ADLIB_INST/IP_INTERFACE_201:IPB,
MSS_ADLIB_INST/IP_INTERFACE_63:A,
MSS_ADLIB_INST/IP_INTERFACE_63:B,
MSS_ADLIB_INST/IP_INTERFACE_63:C,
MSS_ADLIB_INST/IP_INTERFACE_63:IPA,
MSS_ADLIB_INST/IP_INTERFACE_63:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[14]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[14]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_WID_ibuf[3]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WID_ibuf[3]/U0/U_IOINFF:Y,
FIC_2_APB_M_PWDATA_obuf[24]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[24]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_21:A,
MSS_ADLIB_INST/IP_INTERFACE_21:B,
MSS_ADLIB_INST/IP_INTERFACE_21:C,
MSS_ADLIB_INST/IP_INTERFACE_21:IPA,
MSS_ADLIB_INST/IP_INTERFACE_21:IPB,
FIC_2_APB_M_PRDATA_ibuf[29]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[29]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HWDATA_ibuf[18]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[18]/U0/U_IOINFF:Y,
MDDR_DQ_12_PAD/U_IOPAD:D,
MDDR_DQ_12_PAD/U_IOPAD:E,
MDDR_DQ_12_PAD/U_IOPAD:PAD,
MDDR_DQ_12_PAD/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_176:A,
MSS_ADLIB_INST/IP_INTERFACE_176:B,
MSS_ADLIB_INST/IP_INTERFACE_176:C,
MSS_ADLIB_INST/IP_INTERFACE_176:IPA,
MSS_ADLIB_INST/IP_INTERFACE_176:IPB,
FIC_2_APB_M_PWDATA_obuf[17]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[17]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_19:A,
MSS_ADLIB_INST/IP_INTERFACE_19:B,
MSS_ADLIB_INST/IP_INTERFACE_19:C,
MSS_ADLIB_INST/IP_INTERFACE_19:IPA,
MSS_ADLIB_INST/IP_INTERFACE_19:IPB,
MSS_ADLIB_INST/IP_INTERFACE_115:A,
MSS_ADLIB_INST/IP_INTERFACE_115:B,
MSS_ADLIB_INST/IP_INTERFACE_115:C,
MSS_ADLIB_INST/IP_INTERFACE_115:IPA,
MSS_ADLIB_INST/IP_INTERFACE_115:IPB,
MDDR_DDR_AXI_S_RID_obuf[2]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RID_obuf[2]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[13]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[13]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HRDATA_obuf[7]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[7]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[7]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HRDATA_obuf[11]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[11]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[11]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RMW_ibuf/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_RMW_ibuf/U0/U_IOINFF:Y,
FIC_2_APB_M_PWDATA_obuf[30]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[30]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[13]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[13]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[13]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[6]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[6]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[28]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[28]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[59]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[59]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[59]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWLEN_ibuf[2]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWLEN_ibuf[2]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HRDATA_obuf[19]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[19]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[33]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[33]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[33]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARID_ibuf[3]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARID_ibuf[3]/U0/U_IOINFF:Y,
FIC_2_APB_M_PRDATA_ibuf[24]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[24]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HRDATA_obuf[11]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[11]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[3]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[3]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[21]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[21]/U0/U_IOINFF:Y,
ip_interface_inst_1:A,
ip_interface_inst_1:B,
ip_interface_inst_1:C,
MSS_ADLIB_INST/IP_INTERFACE_376:A,
MSS_ADLIB_INST/IP_INTERFACE_376:B,
MSS_ADLIB_INST/IP_INTERFACE_376:C,
MSS_ADLIB_INST/IP_INTERFACE_376:IPA,
MSS_ADLIB_INST/IP_INTERFACE_144:A,
MSS_ADLIB_INST/IP_INTERFACE_144:B,
MSS_ADLIB_INST/IP_INTERFACE_144:C,
MSS_ADLIB_INST/IP_INTERFACE_144:IPA,
FIC_2_APB_M_PSEL_obuf/U0/U_IOENFF:A,
FIC_2_APB_M_PSEL_obuf/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_131:A,
MSS_ADLIB_INST/IP_INTERFACE_131:B,
MSS_ADLIB_INST/IP_INTERFACE_131:C,
MSS_ADLIB_INST/IP_INTERFACE_131:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[26]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[26]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[26]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[30]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[30]/U0/U_IOPAD:Y,
MDDR_DM_RDQS_1_PAD/U_IOPAD:D,
MDDR_DM_RDQS_1_PAD/U_IOPAD:E,
MDDR_DM_RDQS_1_PAD/U_IOPAD:PAD,
MDDR_DM_RDQS_1_PAD/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_243:A,
MSS_ADLIB_INST/IP_INTERFACE_243:B,
MSS_ADLIB_INST/IP_INTERFACE_243:C,
MSS_ADLIB_INST/IP_INTERFACE_243:IPA,
MDDR_DDR_AXI_S_RDATA_obuf[39]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[39]/U0/U_IOENFF:Y,
FIC_0_AHB_S_HRDATA_obuf[19]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[19]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[19]/U0/U_IOPAD:PAD,
MDDR_APB_S_PWDATA_ibuf[10]/U0/U_IOINFF:A,
MDDR_APB_S_PWDATA_ibuf[10]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[12]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[12]/U0/U_IOENFF:Y,
FIC_2_APB_M_PWDATA_obuf[22]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[22]/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HRDATA_obuf[0]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[0]/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HMASTLOCK_ibuf/U0/U_IOINFF:A,
FIC_0_AHB_S_HMASTLOCK_ibuf/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[48]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[48]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_298:A,
MSS_ADLIB_INST/IP_INTERFACE_298:B,
MSS_ADLIB_INST/IP_INTERFACE_298:C,
MSS_ADLIB_INST/IP_INTERFACE_298:IPB,
MSS_ADLIB_INST/IP_INTERFACE_104:A,
MSS_ADLIB_INST/IP_INTERFACE_104:B,
MSS_ADLIB_INST/IP_INTERFACE_104:C,
MSS_ADLIB_INST/IP_INTERFACE_104:IPA,
MSS_ADLIB_INST/IP_INTERFACE_104:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[9]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[9]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[16]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[16]/U0/U_IOENFF:Y,
FIC_0_AHB_S_HADDR_ibuf[27]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[27]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_0:A,
MSS_ADLIB_INST/IP_INTERFACE_0:B,
MSS_ADLIB_INST/IP_INTERFACE_0:C,
MSS_ADLIB_INST/IP_INTERFACE_0:IPA,
MDDR_DQS_0_PAD/U_IOPADP:EIN_P,
MDDR_DQS_0_PAD/U_IOPADP:IOUT_P,
MDDR_DQS_0_PAD/U_IOPADP:N2PIN_P,
MDDR_DQS_0_PAD/U_IOPADP:OIN_P,
MDDR_DQS_0_PAD/U_IOPADP:PAD_P,
MDDR_DDR_AXI_S_AWLOCK_ibuf[1]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWLOCK_ibuf[1]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[17]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[17]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_203:A,
MSS_ADLIB_INST/IP_INTERFACE_203:B,
MSS_ADLIB_INST/IP_INTERFACE_203:C,
MSS_ADLIB_INST/IP_INTERFACE_203:IPB,
MDDR_APB_S_PWDATA_ibuf[13]/U0/U_IOPAD:PAD,
MDDR_APB_S_PWDATA_ibuf[13]/U0/U_IOPAD:Y,
FIC_2_APB_M_PRDATA_ibuf[20]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[20]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_69:A,
MSS_ADLIB_INST/IP_INTERFACE_69:B,
MSS_ADLIB_INST/IP_INTERFACE_69:C,
MSS_ADLIB_INST/IP_INTERFACE_69:IPA,
MSS_ADLIB_INST/IP_INTERFACE_69:IPB,
MSS_ADLIB_INST/IP_INTERFACE_113:A,
MSS_ADLIB_INST/IP_INTERFACE_113:B,
MSS_ADLIB_INST/IP_INTERFACE_113:C,
MSS_ADLIB_INST/IP_INTERFACE_113:IPA,
MSS_ADLIB_INST/IP_INTERFACE_113:IPB,
FIC_2_APB_M_PWDATA_obuf[12]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[12]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[12]/U0/U_IOPAD:PAD,
GPIO_2_M2F_obuf/U0/U_IOPAD:D,
GPIO_2_M2F_obuf/U0/U_IOPAD:E,
GPIO_2_M2F_obuf/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HRDATA_obuf[23]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[23]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[23]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RDATA_obuf[43]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[43]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_BID_obuf[3]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_BID_obuf[3]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[51]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[51]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_AWSIZE_ibuf[1]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWSIZE_ibuf[1]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_AWID_ibuf[2]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWID_ibuf[2]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_168:A,
MSS_ADLIB_INST/IP_INTERFACE_168:B,
MSS_ADLIB_INST/IP_INTERFACE_168:C,
MSS_ADLIB_INST/IP_INTERFACE_168:IPA,
MSS_ADLIB_INST/IP_INTERFACE_57:A,
MSS_ADLIB_INST/IP_INTERFACE_57:B,
MSS_ADLIB_INST/IP_INTERFACE_57:C,
MSS_ADLIB_INST/IP_INTERFACE_57:IPA,
MSS_ADLIB_INST/IP_INTERFACE_57:IPB,
MDDR_ADDR_0_PAD/U_IOPAD:D,
MDDR_ADDR_0_PAD/U_IOPAD:E,
MDDR_ADDR_0_PAD/U_IOPAD:PAD,
FIC_2_APB_M_PSLVERR_ibuf/U0/U_IOINFF:A,
FIC_2_APB_M_PSLVERR_ibuf/U0/U_IOINFF:Y,
FIC_0_AHB_S_HADDR_ibuf[6]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[6]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[14]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[14]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[14]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[23]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[23]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_3:A,
MSS_ADLIB_INST/IP_INTERFACE_3:B,
MSS_ADLIB_INST/IP_INTERFACE_3:C,
MSS_ADLIB_INST/IP_INTERFACE_3:IPA,
MSS_ADLIB_INST/IP_INTERFACE_3:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[46]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[46]/U0/U_IOPAD:Y,
FIC_2_APB_M_PWDATA_obuf[16]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[16]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[16]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RDATA_obuf[47]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[47]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_41:A,
MSS_ADLIB_INST/IP_INTERFACE_41:B,
MSS_ADLIB_INST/IP_INTERFACE_41:C,
MSS_ADLIB_INST/IP_INTERFACE_41:IPA,
MSS_ADLIB_INST/IP_INTERFACE_41:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[34]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[34]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[34]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[1]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[1]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HADDR_ibuf[1]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[1]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_169:A,
MSS_ADLIB_INST/IP_INTERFACE_169:B,
MSS_ADLIB_INST/IP_INTERFACE_169:C,
MSS_ADLIB_INST/IP_INTERFACE_169:IPA,
MSS_ADLIB_INST/IP_INTERFACE_154:A,
MSS_ADLIB_INST/IP_INTERFACE_154:B,
MSS_ADLIB_INST/IP_INTERFACE_154:C,
MSS_ADLIB_INST/IP_INTERFACE_154:IPB,
MDDR_DQ_4_PAD/U_IOPAD:D,
MDDR_DQ_4_PAD/U_IOPAD:E,
MDDR_DQ_4_PAD/U_IOPAD:PAD,
MDDR_DQ_4_PAD/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[26]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[26]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARID_ibuf[2]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARID_ibuf[2]/U0/U_IOPAD:Y,
MDDR_APB_S_PRDATA_obuf[3]/U0/U_IOOUTFF:A,
MDDR_APB_S_PRDATA_obuf[3]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[52]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[52]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_127:A,
MSS_ADLIB_INST/IP_INTERFACE_127:B,
MSS_ADLIB_INST/IP_INTERFACE_127:C,
MSS_ADLIB_INST/IP_INTERFACE_127:IPA,
MSS_ADLIB_INST/IP_INTERFACE_127:IPB,
FIC_0_AHB_S_HADDR_ibuf[23]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[23]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_253:A,
MSS_ADLIB_INST/IP_INTERFACE_253:B,
MSS_ADLIB_INST/IP_INTERFACE_253:C,
MSS_ADLIB_INST/IP_INTERFACE_253:IPA,
MSS_ADLIB_INST/IP_INTERFACE_253:IPB,
FIC_2_APB_M_PADDR_obuf[4]/U0/U_IOENFF:A,
FIC_2_APB_M_PADDR_obuf[4]/U0/U_IOENFF:Y,
FIC_2_APB_M_PRDATA_ibuf[14]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[14]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_36:A,
MSS_ADLIB_INST/IP_INTERFACE_36:B,
MSS_ADLIB_INST/IP_INTERFACE_36:C,
MSS_ADLIB_INST/IP_INTERFACE_36:IPA,
MSS_ADLIB_INST/IP_INTERFACE_191:A,
MSS_ADLIB_INST/IP_INTERFACE_191:B,
MSS_ADLIB_INST/IP_INTERFACE_191:C,
MSS_ADLIB_INST/IP_INTERFACE_191:IPB,
MDDR_DDR_AXI_S_WLAST_ibuf/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WLAST_ibuf/U0/U_IOINFF:Y,
MDDR_APB_S_PRDATA_obuf[5]/U0/U_IOOUTFF:A,
MDDR_APB_S_PRDATA_obuf[5]/U0/U_IOOUTFF:Y,
GPIO_11_F2M_ibuf/U0/U_IOINFF:A,
GPIO_11_F2M_ibuf/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_230:A,
MSS_ADLIB_INST/IP_INTERFACE_230:B,
MSS_ADLIB_INST/IP_INTERFACE_230:C,
MSS_ADLIB_INST/IP_INTERFACE_230:IPA,
MSS_ADLIB_INST/IP_INTERFACE_230:IPB,
FIC_0_AHB_S_HRDATA_obuf[9]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[9]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[9]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[0]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[0]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_7:A,
MSS_ADLIB_INST/IP_INTERFACE_7:B,
MSS_ADLIB_INST/IP_INTERFACE_7:C,
MSS_ADLIB_INST/IP_INTERFACE_7:IPA,
MSS_ADLIB_INST/IP_INTERFACE_7:IPB,
MSS_ADLIB_INST/IP_INTERFACE_320:A,
MSS_ADLIB_INST/IP_INTERFACE_320:B,
MSS_ADLIB_INST/IP_INTERFACE_320:C,
MSS_ADLIB_INST/IP_INTERFACE_320:IPA,
MSS_ADLIB_INST/IP_INTERFACE_320:IPB,
MDDR_DDR_AXI_S_ARSIZE_ibuf[0]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARSIZE_ibuf[0]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_231:A,
MSS_ADLIB_INST/IP_INTERFACE_231:B,
MSS_ADLIB_INST/IP_INTERFACE_231:C,
MSS_ADLIB_INST/IP_INTERFACE_231:IPA,
MSS_ADLIB_INST/IP_INTERFACE_231:IPB,
FIC_0_AHB_S_HRDATA_obuf[25]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[25]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[25]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RDATA_obuf[33]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[33]/U0/U_IOOUTFF:Y,
FIC_2_APB_M_PADDR_obuf[15]/U0/U_IOPAD:D,
FIC_2_APB_M_PADDR_obuf[15]/U0/U_IOPAD:E,
FIC_2_APB_M_PADDR_obuf[15]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HRDATA_obuf[22]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[22]/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[7]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[7]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_188:A,
MSS_ADLIB_INST/IP_INTERFACE_188:B,
MSS_ADLIB_INST/IP_INTERFACE_188:C,
MSS_ADLIB_INST/IP_INTERFACE_188:IPA,
MSS_ADLIB_INST/IP_INTERFACE_188:IPB,
MDDR_APB_S_PRDATA_obuf[8]/U0/U_IOENFF:A,
MDDR_APB_S_PRDATA_obuf[8]/U0/U_IOENFF:Y,
FIC_0_AHB_S_HADDR_ibuf[24]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[24]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_112:A,
MSS_ADLIB_INST/IP_INTERFACE_112:B,
MSS_ADLIB_INST/IP_INTERFACE_112:C,
MSS_ADLIB_INST/IP_INTERFACE_112:IPA,
MSS_ADLIB_INST/IP_INTERFACE_112:IPB,
MDDR_DDR_AXI_S_AWADDR_ibuf[4]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[4]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[0]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[0]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[17]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[17]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[37]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[37]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_76:A,
MSS_ADLIB_INST/IP_INTERFACE_76:B,
MSS_ADLIB_INST/IP_INTERFACE_76:C,
MSS_ADLIB_INST/IP_INTERFACE_76:IPA,
MSS_ADLIB_INST/IP_INTERFACE_76:IPB,
MSS_ADLIB_INST/IP_INTERFACE_372:A,
MSS_ADLIB_INST/IP_INTERFACE_372:B,
MSS_ADLIB_INST/IP_INTERFACE_372:C,
MSS_ADLIB_INST/IP_INTERFACE_372:IPA,
MSS_ADLIB_INST/IP_INTERFACE_189:A,
MSS_ADLIB_INST/IP_INTERFACE_189:B,
MSS_ADLIB_INST/IP_INTERFACE_189:C,
MSS_ADLIB_INST/IP_INTERFACE_189:IPA,
MSS_ADLIB_INST/IP_INTERFACE_189:IPB,
FIC_2_APB_M_PRDATA_ibuf[6]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[6]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_AWLEN_ibuf[1]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWLEN_ibuf[1]/U0/U_IOINFF:Y,
MCCC_CLK_BASE_PLL_LOCK_ibuf/U0/U_IOPAD:PAD,
MCCC_CLK_BASE_PLL_LOCK_ibuf/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WSTRB_ibuf[7]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WSTRB_ibuf[7]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[22]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[22]/U0/U_IOENFF:Y,
MDDR_APB_S_PREADY_obuf/U0/U_IOOUTFF:A,
MDDR_APB_S_PREADY_obuf/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_AWID_ibuf[2]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWID_ibuf[2]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_38:A,
MSS_ADLIB_INST/IP_INTERFACE_38:B,
MSS_ADLIB_INST/IP_INTERFACE_38:C,
MSS_ADLIB_INST/IP_INTERFACE_38:IPA,
MSS_ADLIB_INST/IP_INTERFACE_38:IPB,
MDDR_DDR_AXI_S_AWADDR_ibuf[8]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[8]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[31]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[31]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HWDATA_ibuf[6]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[6]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HRDATA_obuf[13]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[13]/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HADDR_ibuf[14]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[14]/U0/U_IOPAD:Y,
MMUART_0_RXD_PAD/U_IOPAD:PAD,
MMUART_0_RXD_PAD/U_IOPAD:Y,
MDDR_DDR_AXI_S_WID_ibuf[1]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WID_ibuf[1]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[57]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[57]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[57]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WSTRB_ibuf[4]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WSTRB_ibuf[4]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[6]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[6]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[26]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[26]/U0/U_IOENFF:Y,
MDDR_DQ_5_PAD/U_IOINFF:A,
MDDR_DQ_5_PAD/U_IOINFF:Y,
GPIO_10_M2F_obuf/U0/U_IOENFF:A,
GPIO_10_M2F_obuf/U0/U_IOENFF:Y,
GPIO_0_M2F_obuf/U0/U_IOENFF:A,
GPIO_0_M2F_obuf/U0/U_IOENFF:Y,
MDDR_DQ_6_PAD/U_IOPAD:D,
MDDR_DQ_6_PAD/U_IOPAD:E,
MDDR_DQ_6_PAD/U_IOPAD:PAD,
MDDR_DQ_6_PAD/U_IOPAD:Y,
MDDR_DDR_AXI_S_RRESP_obuf[0]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RRESP_obuf[0]/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[22]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[22]/U0/U_IOINFF:Y,
SPI_0_DI_PAD/U_IOPAD:PAD,
SPI_0_DI_PAD/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_216:A,
MSS_ADLIB_INST/IP_INTERFACE_216:B,
MSS_ADLIB_INST/IP_INTERFACE_216:C,
MSS_ADLIB_INST/IP_INTERFACE_216:IPA,
MDDR_DDR_AXI_S_ARADDR_ibuf[3]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[3]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HADDR_ibuf[8]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[8]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[55]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[55]/U0/U_IOINFF:Y,
FIC_2_APB_M_PWDATA_obuf[30]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[30]/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HADDR_ibuf[25]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[25]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_148:A,
MSS_ADLIB_INST/IP_INTERFACE_148:B,
MSS_ADLIB_INST/IP_INTERFACE_148:C,
MSS_ADLIB_INST/IP_INTERFACE_148:IPA,
MSS_ADLIB_INST/IP_INTERFACE_148:IPB,
MSS_ADLIB_INST/IP_INTERFACE_134:A,
MSS_ADLIB_INST/IP_INTERFACE_134:B,
MSS_ADLIB_INST/IP_INTERFACE_134:C,
MSS_ADLIB_INST/IP_INTERFACE_134:IPA,
MSS_ADLIB_INST/IP_INTERFACE_134:IPB,
FIC_2_APB_M_PWDATA_obuf[18]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[18]/U0/U_IOOUTFF:Y,
MDDR_APB_S_PWRITE_ibuf/U0/U_IOINFF:A,
MDDR_APB_S_PWRITE_ibuf/U0/U_IOINFF:Y,
FIC_2_APB_M_PCLK_obuf/U0/U_IOENFF:A,
FIC_2_APB_M_PCLK_obuf/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_272:A,
MSS_ADLIB_INST/IP_INTERFACE_272:B,
MSS_ADLIB_INST/IP_INTERFACE_272:C,
MSS_ADLIB_INST/IP_INTERFACE_272:IPA,
MSS_ADLIB_INST/IP_INTERFACE_272:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[63]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[63]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_290:A,
MSS_ADLIB_INST/IP_INTERFACE_290:B,
MSS_ADLIB_INST/IP_INTERFACE_290:C,
MSS_ADLIB_INST/IP_INTERFACE_290:IPA,
MSS_ADLIB_INST/IP_INTERFACE_290:IPB,
MDDR_APB_S_PCLK_ibuf/U0/U_IOPAD:PAD,
MDDR_APB_S_PCLK_ibuf/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_233:A,
MSS_ADLIB_INST/IP_INTERFACE_233:B,
MSS_ADLIB_INST/IP_INTERFACE_233:C,
MSS_ADLIB_INST/IP_INTERFACE_233:IPA,
MSS_ADLIB_INST/IP_INTERFACE_233:IPB,
MDDR_DDR_AXI_S_ARID_ibuf[1]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARID_ibuf[1]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[11]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[11]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_291:A,
MSS_ADLIB_INST/IP_INTERFACE_291:B,
MSS_ADLIB_INST/IP_INTERFACE_291:C,
MSS_ADLIB_INST/IP_INTERFACE_291:IPA,
MSS_ADLIB_INST/IP_INTERFACE_291:IPB,
FIC_0_AHB_S_HWDATA_ibuf[20]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[20]/U0/U_IOINFF:Y,
MDDR_APB_S_PADDR_ibuf[7]/U0/U_IOPAD:PAD,
MDDR_APB_S_PADDR_ibuf[7]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_78:A,
MSS_ADLIB_INST/IP_INTERFACE_78:B,
MSS_ADLIB_INST/IP_INTERFACE_78:C,
MSS_ADLIB_INST/IP_INTERFACE_78:IPA,
MSS_ADLIB_INST/IP_INTERFACE_78:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[42]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[42]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_BID_obuf[2]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_BID_obuf[2]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_BID_obuf[2]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RDATA_obuf[63]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[63]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[9]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[9]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_92:A,
MSS_ADLIB_INST/IP_INTERFACE_92:B,
MSS_ADLIB_INST/IP_INTERFACE_92:C,
MSS_ADLIB_INST/IP_INTERFACE_92:IPA,
MSS_ADLIB_INST/IP_INTERFACE_92:IPB,
MDDR_DDR_AXI_S_ARREADY_obuf/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_ARREADY_obuf/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_ARREADY_obuf/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_149:A,
MSS_ADLIB_INST/IP_INTERFACE_149:B,
MSS_ADLIB_INST/IP_INTERFACE_149:C,
MSS_ADLIB_INST/IP_INTERFACE_149:IPA,
MSS_ADLIB_INST/IP_INTERFACE_149:IPB,
FIC_2_APB_M_PENABLE_obuf/U0/U_IOPAD:D,
FIC_2_APB_M_PENABLE_obuf/U0/U_IOPAD:E,
FIC_2_APB_M_PENABLE_obuf/U0/U_IOPAD:PAD,
FIC_2_APB_M_PWDATA_obuf[1]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[1]/U0/U_IOOUTFF:Y,
MDDR_APB_S_PSEL_ibuf/U0/U_IOPAD:PAD,
MDDR_APB_S_PSEL_ibuf/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_108:A,
MSS_ADLIB_INST/IP_INTERFACE_108:B,
MSS_ADLIB_INST/IP_INTERFACE_108:C,
MSS_ADLIB_INST/IP_INTERFACE_108:IPA,
MDDR_APB_S_PWDATA_ibuf[8]/U0/U_IOPAD:PAD,
MDDR_APB_S_PWDATA_ibuf[8]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[18]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[18]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_225:A,
MSS_ADLIB_INST/IP_INTERFACE_225:B,
MSS_ADLIB_INST/IP_INTERFACE_225:C,
MSS_ADLIB_INST/IP_INTERFACE_225:IPA,
MSS_ADLIB_INST/IP_INTERFACE_225:IPB,
GPIO_10_M2F_obuf/U0/U_IOOUTFF:A,
GPIO_10_M2F_obuf/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HRDATA_obuf[30]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[30]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[30]/U0/U_IOPAD:PAD,
MDDR_DM_RDQS_0_PAD/U_IOINFF:A,
MDDR_DM_RDQS_0_PAD/U_IOINFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[6]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[6]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_34:A,
MSS_ADLIB_INST/IP_INTERFACE_34:B,
MSS_ADLIB_INST/IP_INTERFACE_34:C,
MSS_ADLIB_INST/IP_INTERFACE_34:IPB,
MDDR_DDR_AXI_S_AWADDR_ibuf[28]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[28]/U0/U_IOPAD:Y,
FIC_2_APB_M_PRDATA_ibuf[31]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[31]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HRDATA_obuf[26]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[26]/U0/U_IOENFF:Y,
FIC_2_APB_M_PWDATA_obuf[3]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[3]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_ARSIZE_ibuf[1]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARSIZE_ibuf[1]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_109:A,
MSS_ADLIB_INST/IP_INTERFACE_109:B,
MSS_ADLIB_INST/IP_INTERFACE_109:C,
MSS_ADLIB_INST/IP_INTERFACE_109:IPA,
FIC_2_APB_M_PWDATA_obuf[8]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[8]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[8]/U0/U_IOPAD:PAD,
MDDR_ADDR_10_PAD/U_IOPAD:D,
MDDR_ADDR_10_PAD/U_IOPAD:E,
MDDR_ADDR_10_PAD/U_IOPAD:PAD,
MDDR_APB_S_PADDR_ibuf[5]/U0/U_IOPAD:PAD,
MDDR_APB_S_PADDR_ibuf[5]/U0/U_IOPAD:Y,
FIC_2_APB_M_PADDR_obuf[3]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PADDR_obuf[3]/U0/U_IOOUTFF:Y,
MDDR_APB_S_PRDATA_obuf[2]/U0/U_IOENFF:A,
MDDR_APB_S_PRDATA_obuf[2]/U0/U_IOENFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[15]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[15]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WSTRB_ibuf[6]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WSTRB_ibuf[6]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HREADY_ibuf/U0/U_IOINFF:A,
FIC_0_AHB_S_HREADY_ibuf/U0/U_IOINFF:Y,
FIC_0_AHB_S_HRDATA_obuf[8]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[8]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[8]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[11]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[11]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[7]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[7]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[29]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[29]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_30:A,
MSS_ADLIB_INST/IP_INTERFACE_30:B,
MSS_ADLIB_INST/IP_INTERFACE_30:C,
MSS_ADLIB_INST/IP_INTERFACE_30:IPA,
MSS_ADLIB_INST/IP_INTERFACE_30:IPB,
MDDR_DDR_AXI_S_WREADY_obuf/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_WREADY_obuf/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_379:A,
MSS_ADLIB_INST/IP_INTERFACE_379:B,
MSS_ADLIB_INST/IP_INTERFACE_379:C,
MSS_ADLIB_INST/IP_INTERFACE_379:IPA,
MSS_ADLIB_INST/IP_INTERFACE_379:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[59]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[59]/U0/U_IOINFF:Y,
FIC_2_APB_M_PWDATA_obuf[0]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[0]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_313:A,
MSS_ADLIB_INST/IP_INTERFACE_313:B,
MSS_ADLIB_INST/IP_INTERFACE_313:C,
MSS_ADLIB_INST/IP_INTERFACE_313:IPA,
MSS_ADLIB_INST/IP_INTERFACE_313:IPB,
FIC_2_APB_M_PWDATA_obuf[17]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[17]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[17]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[16]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[16]/U0/U_IOPAD:Y,
FIC_2_APB_M_PWDATA_obuf[9]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[9]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[8]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[8]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[28]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[28]/U0/U_IOOUTFF:Y,
FIC_2_APB_M_PWDATA_obuf[24]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[24]/U0/U_IOENFF:Y,
FIC_2_APB_M_PWDATA_obuf[19]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[19]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[19]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_158:A,
MSS_ADLIB_INST/IP_INTERFACE_158:B,
MSS_ADLIB_INST/IP_INTERFACE_158:C,
MSS_ADLIB_INST/IP_INTERFACE_158:IPA,
MSS_ADLIB_INST/IP_INTERFACE_158:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[8]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[8]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[32]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[32]/U0/U_IOOUTFF:Y,
FIC_2_APB_M_PRDATA_ibuf[21]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[21]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_74:A,
MSS_ADLIB_INST/IP_INTERFACE_74:B,
MSS_ADLIB_INST/IP_INTERFACE_74:C,
MSS_ADLIB_INST/IP_INTERFACE_74:IPA,
MSS_ADLIB_INST/IP_INTERFACE_74:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[27]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[27]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[27]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[27]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[23]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[23]/U0/U_IOINFF:Y,
MDDR_APB_S_PRDATA_obuf[10]/U0/U_IOOUTFF:A,
MDDR_APB_S_PRDATA_obuf[10]/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HRDATA_obuf[6]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[6]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_194:A,
MSS_ADLIB_INST/IP_INTERFACE_194:B,
MSS_ADLIB_INST/IP_INTERFACE_194:C,
MSS_ADLIB_INST/IP_INTERFACE_194:IPA,
MSS_ADLIB_INST/IP_INTERFACE_194:IPB,
FIC_2_APB_M_PADDR_obuf[7]/U0/U_IOENFF:A,
FIC_2_APB_M_PADDR_obuf[7]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_159:A,
MSS_ADLIB_INST/IP_INTERFACE_159:B,
MSS_ADLIB_INST/IP_INTERFACE_159:C,
MSS_ADLIB_INST/IP_INTERFACE_159:IPA,
MSS_ADLIB_INST/IP_INTERFACE_159:IPB,
FIC_2_APB_M_PWDATA_obuf[7]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[7]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_17:A,
MSS_ADLIB_INST/IP_INTERFACE_17:B,
MSS_ADLIB_INST/IP_INTERFACE_17:C,
MSS_ADLIB_INST/IP_INTERFACE_17:IPA,
MSS_ADLIB_INST/IP_INTERFACE_17:IPB,
MSS_ADLIB_INST/IP_INTERFACE_293:A,
MSS_ADLIB_INST/IP_INTERFACE_293:B,
MSS_ADLIB_INST/IP_INTERFACE_293:C,
MSS_ADLIB_INST/IP_INTERFACE_293:IPA,
MSS_ADLIB_INST/IP_INTERFACE_293:IPB,
GPIO_3_M2F_obuf/U0/U_IOENFF:A,
GPIO_3_M2F_obuf/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_214:A,
MSS_ADLIB_INST/IP_INTERFACE_214:B,
MSS_ADLIB_INST/IP_INTERFACE_214:C,
MSS_ADLIB_INST/IP_INTERFACE_214:IPB,
FIC_0_AHB_S_HADDR_ibuf[19]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[19]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_70:A,
MSS_ADLIB_INST/IP_INTERFACE_70:B,
MSS_ADLIB_INST/IP_INTERFACE_70:C,
MSS_ADLIB_INST/IP_INTERFACE_70:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[23]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[23]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[23]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_227:A,
MSS_ADLIB_INST/IP_INTERFACE_227:B,
MSS_ADLIB_INST/IP_INTERFACE_227:C,
MSS_ADLIB_INST/IP_INTERFACE_227:IPB,
FIC_0_AHB_S_HWDATA_ibuf[0]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[0]/U0/U_IOPAD:Y,
FIC_2_APB_M_PWDATA_obuf[0]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[0]/U0/U_IOOUTFF:Y,
FIC_2_APB_M_PWDATA_obuf[5]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[5]/U0/U_IOENFF:Y,
FIC_0_AHB_S_HADDR_ibuf[3]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[3]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_35:A,
MSS_ADLIB_INST/IP_INTERFACE_35:B,
MSS_ADLIB_INST/IP_INTERFACE_35:C,
MSS_ADLIB_INST/IP_INTERFACE_35:IPB,
MDDR_RAS_N_PAD/U_IOPAD:D,
MDDR_RAS_N_PAD/U_IOPAD:E,
MDDR_RAS_N_PAD/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WVALID_ibuf/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WVALID_ibuf/U0/U_IOPAD:Y,
MDDR_APB_S_PADDR_ibuf[9]/U0/U_IOPAD:PAD,
MDDR_APB_S_PADDR_ibuf[9]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[18]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[18]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[18]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[18]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[18]/U0/U_IOPAD:Y,
FIC_2_APB_M_PCLK_obuf/U0/U_IOPAD:D,
FIC_2_APB_M_PCLK_obuf/U0/U_IOPAD:E,
FIC_2_APB_M_PCLK_obuf/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RDATA_obuf[38]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[38]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[38]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[38]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[38]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HRDATA_obuf[28]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[28]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[4]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[4]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[0]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[0]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[7]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[7]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[7]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PWRITE_obuf/U0/U_IOENFF:A,
FIC_2_APB_M_PWRITE_obuf/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[40]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[40]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[40]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[12]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[12]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_ARBURST_ibuf[1]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARBURST_ibuf[1]/U0/U_IOINFF:Y,
FIC_2_APB_M_PADDR_obuf[8]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PADDR_obuf[8]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_ARID_ibuf[3]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARID_ibuf[3]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HADDR_ibuf[12]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[12]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_167:A,
MSS_ADLIB_INST/IP_INTERFACE_167:B,
MSS_ADLIB_INST/IP_INTERFACE_167:C,
MSS_ADLIB_INST/IP_INTERFACE_167:IPB,
FIC_0_AHB_S_HWDATA_ibuf[29]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[29]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[14]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[14]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[32]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[32]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[7]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[7]/U0/U_IOINFF:Y,
MDDR_APB_S_PREADY_obuf/U0/U_IOENFF:A,
MDDR_APB_S_PREADY_obuf/U0/U_IOENFF:Y,
MDDR_DQS_1_PAD/U_IOINFF:A,
MDDR_DQS_1_PAD/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[27]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[27]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_229:A,
MSS_ADLIB_INST/IP_INTERFACE_229:B,
MSS_ADLIB_INST/IP_INTERFACE_229:C,
MSS_ADLIB_INST/IP_INTERFACE_229:IPA,
MDDR_DDR_AXI_S_RID_obuf[3]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RID_obuf[3]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RID_obuf[3]/U0/U_IOPAD:PAD,
MDDR_APB_S_PWDATA_ibuf[11]/U0/U_IOINFF:A,
MDDR_APB_S_PWDATA_ibuf[11]/U0/U_IOINFF:Y,
M3_RESET_N_ibuf/U0/U_IOINFF:A,
M3_RESET_N_ibuf/U0/U_IOINFF:Y,
FIC_2_APB_M_PWDATA_obuf[28]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[28]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_328:A,
MSS_ADLIB_INST/IP_INTERFACE_328:B,
MSS_ADLIB_INST/IP_INTERFACE_328:C,
MSS_ADLIB_INST/IP_INTERFACE_328:IPA,
MSS_ADLIB_INST/IP_INTERFACE_328:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[40]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[40]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HRDATA_obuf[20]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[20]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_75:A,
MSS_ADLIB_INST/IP_INTERFACE_75:B,
MSS_ADLIB_INST/IP_INTERFACE_75:C,
MSS_ADLIB_INST/IP_INTERFACE_75:IPA,
MSS_ADLIB_INST/IP_INTERFACE_75:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[53]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[53]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_ARLOCK_ibuf[1]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARLOCK_ibuf[1]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_278:A,
MSS_ADLIB_INST/IP_INTERFACE_278:B,
MSS_ADLIB_INST/IP_INTERFACE_278:C,
MSS_ADLIB_INST/IP_INTERFACE_278:IPB,
MDDR_APB_S_PWDATA_ibuf[5]/U0/U_IOPAD:PAD,
MDDR_APB_S_PWDATA_ibuf[5]/U0/U_IOPAD:Y,
FIC_2_APB_M_PWDATA_obuf[3]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[3]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[3]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PADDR_obuf[16]/U0/U_IOENFF:A,
FIC_2_APB_M_PADDR_obuf[16]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[51]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[51]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[51]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_325:A,
MSS_ADLIB_INST/IP_INTERFACE_325:B,
MSS_ADLIB_INST/IP_INTERFACE_325:C,
MSS_ADLIB_INST/IP_INTERFACE_325:IPA,
MSS_ADLIB_INST/IP_INTERFACE_325:IPB,
MDDR_DDR_AXI_S_ARID_ibuf[0]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARID_ibuf[0]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[62]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[62]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_314:A,
MSS_ADLIB_INST/IP_INTERFACE_314:B,
MSS_ADLIB_INST/IP_INTERFACE_314:C,
MSS_ADLIB_INST/IP_INTERFACE_314:IPA,
MSS_ADLIB_INST/IP_INTERFACE_314:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[28]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[28]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_82:A,
MSS_ADLIB_INST/IP_INTERFACE_82:B,
MSS_ADLIB_INST/IP_INTERFACE_82:C,
MSS_ADLIB_INST/IP_INTERFACE_82:IPB,
MDDR_DDR_AXI_S_WSTRB_ibuf[2]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WSTRB_ibuf[2]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_BID_obuf[0]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_BID_obuf[0]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_67:A,
MSS_ADLIB_INST/IP_INTERFACE_67:B,
MSS_ADLIB_INST/IP_INTERFACE_67:C,
MSS_ADLIB_INST/IP_INTERFACE_67:IPA,
MSS_ADLIB_INST/IP_INTERFACE_67:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[57]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[57]/U0/U_IOOUTFF:Y,
FIC_2_APB_M_PRDATA_ibuf[16]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[16]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HRDATA_obuf[0]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[0]/U0/U_IOENFF:Y,
FIC_2_APB_M_PWDATA_obuf[14]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[14]/U0/U_IOENFF:Y,
FIC_2_APB_M_PRDATA_ibuf[17]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[17]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[17]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[17]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_BREADY_ibuf/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_BREADY_ibuf/U0/U_IOINFF:Y,
FIC_2_APB_M_PRDATA_ibuf[28]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[28]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_AWLEN_ibuf[0]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWLEN_ibuf[0]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[36]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[36]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_138:A,
MSS_ADLIB_INST/IP_INTERFACE_138:B,
MSS_ADLIB_INST/IP_INTERFACE_138:C,
MSS_ADLIB_INST/IP_INTERFACE_138:IPA,
MSS_ADLIB_INST/IP_INTERFACE_138:IPB,
MDDR_DDR_AXI_S_WSTRB_ibuf[0]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WSTRB_ibuf[0]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[12]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[12]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[57]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[57]/U0/U_IOPAD:Y,
MDDR_APB_S_PRDATA_obuf[1]/U0/U_IOENFF:A,
MDDR_APB_S_PRDATA_obuf[1]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[24]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[24]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[24]/U0/U_IOPAD:PAD,
MDDR_APB_S_PWDATA_ibuf[14]/U0/U_IOPAD:PAD,
MDDR_APB_S_PWDATA_ibuf[14]/U0/U_IOPAD:Y,
FIC_2_APB_M_PREADY_ibuf/U0/U_IOPAD:PAD,
FIC_2_APB_M_PREADY_ibuf/U0/U_IOPAD:Y,
FIC_0_AHB_S_HWDATA_ibuf[1]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[1]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[50]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[50]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[21]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[21]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[61]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[61]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[61]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[4]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[4]/U0/U_IOINFF:Y,
MDDR_APB_S_PWDATA_ibuf[9]/U0/U_IOINFF:A,
MDDR_APB_S_PWDATA_ibuf[9]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_187:A,
MSS_ADLIB_INST/IP_INTERFACE_187:B,
MSS_ADLIB_INST/IP_INTERFACE_187:C,
MSS_ADLIB_INST/IP_INTERFACE_187:IPA,
MSS_ADLIB_INST/IP_INTERFACE_187:IPB,
MSS_ADLIB_INST/IP_INTERFACE_139:A,
MSS_ADLIB_INST/IP_INTERFACE_139:B,
MSS_ADLIB_INST/IP_INTERFACE_139:C,
MSS_ADLIB_INST/IP_INTERFACE_139:IPA,
MSS_ADLIB_INST/IP_INTERFACE_139:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[6]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[6]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_WSTRB_ibuf[5]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WSTRB_ibuf[5]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[10]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[10]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_AWREADY_obuf/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_AWREADY_obuf/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_AWID_ibuf[3]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWID_ibuf[3]/U0/U_IOPAD:Y,
MDDR_DQ_0_PAD/U_IOINFF:A,
MDDR_DQ_0_PAD/U_IOINFF:Y,
FIC_0_AHB_S_HRDATA_obuf[9]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[9]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_120:A,
MSS_ADLIB_INST/IP_INTERFACE_120:B,
MSS_ADLIB_INST/IP_INTERFACE_120:C,
MSS_ADLIB_INST/IP_INTERFACE_120:IPA,
MSS_ADLIB_INST/IP_INTERFACE_171:A,
MSS_ADLIB_INST/IP_INTERFACE_171:B,
MSS_ADLIB_INST/IP_INTERFACE_171:C,
MSS_ADLIB_INST/IP_INTERFACE_171:IPA,
MSS_ADLIB_INST/IP_INTERFACE_171:IPB,
MSS_ADLIB_INST/IP_INTERFACE_33:A,
MSS_ADLIB_INST/IP_INTERFACE_33:B,
MSS_ADLIB_INST/IP_INTERFACE_33:C,
MSS_ADLIB_INST/IP_INTERFACE_33:IPA,
MSS_ADLIB_INST/IP_INTERFACE_33:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[43]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[43]/U0/U_IOENFF:Y,
MDDR_DQ_3_PAD/U_IOPAD:D,
MDDR_DQ_3_PAD/U_IOPAD:E,
MDDR_DQ_3_PAD/U_IOPAD:PAD,
MDDR_DQ_3_PAD/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[14]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[14]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_380:A,
MSS_ADLIB_INST/IP_INTERFACE_380:B,
MSS_ADLIB_INST/IP_INTERFACE_380:C,
MSS_ADLIB_INST/IP_INTERFACE_380:IPA,
MSS_ADLIB_INST/IP_INTERFACE_380:IPB,
MDDR_APB_S_PADDR_ibuf[8]/U0/U_IOINFF:A,
MDDR_APB_S_PADDR_ibuf[8]/U0/U_IOINFF:Y,
FIC_2_APB_M_PWDATA_obuf[11]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[11]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[11]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RVALID_obuf/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RVALID_obuf/U0/U_IOENFF:Y,
MDDR_APB_S_PRDATA_obuf[1]/U0/U_IOPAD:D,
MDDR_APB_S_PRDATA_obuf[1]/U0/U_IOPAD:E,
MDDR_APB_S_PRDATA_obuf[1]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_9:A,
MSS_ADLIB_INST/IP_INTERFACE_9:B,
MSS_ADLIB_INST/IP_INTERFACE_9:C,
MSS_ADLIB_INST/IP_INTERFACE_9:IPA,
MSS_ADLIB_INST/IP_INTERFACE_9:IPB,
MSS_ADLIB_INST/IP_INTERFACE_327:A,
MSS_ADLIB_INST/IP_INTERFACE_327:B,
MSS_ADLIB_INST/IP_INTERFACE_327:C,
MSS_ADLIB_INST/IP_INTERFACE_327:IPA,
MSS_ADLIB_INST/IP_INTERFACE_327:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[34]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[34]/U0/U_IOPAD:Y,
MDDR_APB_S_PRDATA_obuf[2]/U0/U_IOOUTFF:A,
MDDR_APB_S_PRDATA_obuf[2]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/INST_MSS_120_IP:CAN_RXBUS_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:CAN_RXBUS_MGPIO3A_H2F_B,
MSS_ADLIB_INST/INST_MSS_120_IP:CAN_RXBUS_USBA_DATA1_MGPIO3A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:CAN_TXBUS_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:CAN_TXBUS_MGPIO2A_H2F_B,
MSS_ADLIB_INST/INST_MSS_120_IP:CAN_TXBUS_USBA_DATA0_MGPIO2A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:CAN_TX_EBL_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:CAN_TX_EBL_MGPIO4A_H2F_B,
MSS_ADLIB_INST/INST_MSS_120_IP:CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE,
MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB,
MSS_ADLIB_INST/INST_MSS_120_IP:CLK_MDDR_APB,
MSS_ADLIB_INST/INST_MSS_120_IP:COLF,
MSS_ADLIB_INST/INST_MSS_120_IP:CONFIG_PRESET_N,
MSS_ADLIB_INST/INST_MSS_120_IP:CRSF,
MSS_ADLIB_INST/INST_MSS_120_IP:DM_IN[0],
MSS_ADLIB_INST/INST_MSS_120_IP:DM_IN[1],
MSS_ADLIB_INST/INST_MSS_120_IP:DM_IN[2],
MSS_ADLIB_INST/INST_MSS_120_IP:DM_IN[3],
MSS_ADLIB_INST/INST_MSS_120_IP:DM_IN[4],
MSS_ADLIB_INST/INST_MSS_120_IP:DM_OE[0],
MSS_ADLIB_INST/INST_MSS_120_IP:DM_OE[1],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_ADDR[0],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_ADDR[10],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_ADDR[11],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_ADDR[12],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_ADDR[13],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_ADDR[14],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_ADDR[15],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_ADDR[1],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_ADDR[2],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_ADDR[3],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_ADDR[4],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_ADDR[5],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_ADDR[6],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_ADDR[7],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_ADDR[8],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_ADDR[9],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_BA[0],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_BA[1],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_BA[2],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_CASN,
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_CKE,
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_CLK,
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_CSN,
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DM_RDQS_OUT[0],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DM_RDQS_OUT[1],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQS_IN[0],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQS_IN[1],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQS_IN[2],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQS_IN[3],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQS_IN[4],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQS_OE[0],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQS_OE[1],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQS_OUT[0],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQS_OUT[1],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[0],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[10],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[11],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[12],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[13],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[14],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[15],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[16],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[17],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[18],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[19],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[1],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[20],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[21],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[22],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[23],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[24],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[25],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[26],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[27],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[28],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[29],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[2],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[30],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[31],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[32],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[33],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[34],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[35],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[3],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[4],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[5],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[6],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[7],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[8],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_IN[9],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OE[0],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OE[10],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OE[11],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OE[12],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OE[13],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OE[14],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OE[15],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OE[1],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OE[2],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OE[3],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OE[4],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OE[5],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OE[6],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OE[7],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OE[8],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OE[9],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OUT[0],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OUT[10],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OUT[11],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OUT[12],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OUT[13],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OUT[14],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OUT[15],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OUT[1],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OUT[2],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OUT[3],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OUT[4],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OUT[5],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OUT[6],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OUT[7],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OUT[8],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_DQ_OUT[9],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_FIFO_WE_IN[0],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_FIFO_WE_IN[1],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_FIFO_WE_IN[2],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_FIFO_WE_OUT[0],
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_ODT,
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_RASN,
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_RSTN,
MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_WEN,
MSS_ADLIB_INST/INST_MSS_120_IP:F2HCALIB,
MSS_ADLIB_INST/INST_MSS_120_IP:F2H_INTERRUPT[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F2H_INTERRUPT[10],
MSS_ADLIB_INST/INST_MSS_120_IP:F2H_INTERRUPT[11],
MSS_ADLIB_INST/INST_MSS_120_IP:F2H_INTERRUPT[12],
MSS_ADLIB_INST/INST_MSS_120_IP:F2H_INTERRUPT[13],
MSS_ADLIB_INST/INST_MSS_120_IP:F2H_INTERRUPT[14],
MSS_ADLIB_INST/INST_MSS_120_IP:F2H_INTERRUPT[15],
MSS_ADLIB_INST/INST_MSS_120_IP:F2H_INTERRUPT[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F2H_INTERRUPT[2],
MSS_ADLIB_INST/INST_MSS_120_IP:F2H_INTERRUPT[3],
MSS_ADLIB_INST/INST_MSS_120_IP:F2H_INTERRUPT[4],
MSS_ADLIB_INST/INST_MSS_120_IP:F2H_INTERRUPT[5],
MSS_ADLIB_INST/INST_MSS_120_IP:F2H_INTERRUPT[6],
MSS_ADLIB_INST/INST_MSS_120_IP:F2H_INTERRUPT[7],
MSS_ADLIB_INST/INST_MSS_120_IP:F2H_INTERRUPT[8],
MSS_ADLIB_INST/INST_MSS_120_IP:F2H_INTERRUPT[9],
MSS_ADLIB_INST/INST_MSS_120_IP:F2_DMAREADY[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F2_DMAREADY[1],
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_AVALID,
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_HOSTDISCON,
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_IDDIG,
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_LINESTATE[0],
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_LINESTATE[1],
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_M3_RESET_N,
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_PLL_LOCK,
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_RXACTIVE,
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_RXERROR,
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_RXVALID,
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_RXVALIDH,
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_SESSEND,
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_TXREADY,
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_VBUSVALID,
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_VSTATUS[0],
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_VSTATUS[1],
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_VSTATUS[2],
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_VSTATUS[3],
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_VSTATUS[4],
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_VSTATUS[5],
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_VSTATUS[6],
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_VSTATUS[7],
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_XDATAIN[0],
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_XDATAIN[1],
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_XDATAIN[2],
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_XDATAIN[3],
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_XDATAIN[4],
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_XDATAIN[5],
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_XDATAIN[6],
MSS_ADLIB_INST/INST_MSS_120_IP:FAB_XDATAIN[7],
MSS_ADLIB_INST/INST_MSS_120_IP:FPGA_MDDR_ARESET_N,
MSS_ADLIB_INST/INST_MSS_120_IP:FPGA_RESET_N,
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[10],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[11],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[12],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[13],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[14],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[15],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[16],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[17],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[18],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[19],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[20],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[21],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[22],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[23],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[24],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[25],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[26],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[27],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[28],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[29],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[2],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[30],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[31],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[3],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[4],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[5],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[6],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[7],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[8],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARADDR_HADDR1[9],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARBURST_HTRANS1[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARBURST_HTRANS1[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARID_HSEL1[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARID_HSEL1[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARID_HSEL1[2],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARID_HSEL1[3],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARLEN_HBURST1[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARLEN_HBURST1[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARLEN_HBURST1[2],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARLEN_HBURST1[3],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARLOCK_HMASTLOCK1[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARLOCK_HMASTLOCK1[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARREADY_HREADYOUT1,
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARSIZE_HSIZE1[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARSIZE_HSIZE1[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_ARVALID_HWRITE1,
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[10],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[11],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[12],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[13],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[14],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[15],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[16],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[17],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[18],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[19],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[20],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[21],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[22],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[23],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[24],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[25],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[26],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[27],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[28],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[29],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[2],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[30],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[31],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[3],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[4],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[5],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[6],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[7],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[8],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWADDR_HADDR0[9],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWBURST_HTRANS0[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWBURST_HTRANS0[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWID_HSEL0[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWID_HSEL0[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWID_HSEL0[2],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWID_HSEL0[3],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWLEN_HBURST0[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWLEN_HBURST0[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWLEN_HBURST0[2],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWLEN_HBURST0[3],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWLOCK_HMASTLOCK0[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWLOCK_HMASTLOCK0[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWREADY_HREADYOUT0,
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWSIZE_HSIZE0[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWSIZE_HSIZE0[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_AWVALID_HWRITE0,
MSS_ADLIB_INST/INST_MSS_120_IP:F_BID[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_BID[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_BID[2],
MSS_ADLIB_INST/INST_MSS_120_IP:F_BID[3],
MSS_ADLIB_INST/INST_MSS_120_IP:F_BREADY,
MSS_ADLIB_INST/INST_MSS_120_IP:F_BRESP_HRESP0[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_BRESP_HRESP0[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_BVALID,
MSS_ADLIB_INST/INST_MSS_120_IP:F_DMAREADY[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_DMAREADY[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[10],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[11],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[12],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[13],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[14],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[15],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[16],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[17],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[18],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[19],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[20],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[21],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[22],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[23],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[24],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[25],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[26],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[27],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[28],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[29],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[2],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[30],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[31],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[3],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[4],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[5],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[6],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[7],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[8],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[9],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ENABLE,
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_MASTLOCK,
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[10],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[11],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[12],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[13],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[14],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[15],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[16],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[17],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[18],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[19],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[20],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[21],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[22],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[23],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[24],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[25],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[26],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[27],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[28],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[29],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[2],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[30],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[31],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[3],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[4],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[5],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[6],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[7],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[8],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RDATA[9],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_READY,
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_READYOUT,
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_RESP,
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_SEL,
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_SIZE[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_SIZE[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_TRANS1,
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[10],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[11],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[12],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[13],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[14],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[15],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[16],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[17],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[18],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[19],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[20],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[21],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[22],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[23],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[24],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[25],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[26],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[27],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[28],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[29],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[2],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[30],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[31],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[3],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[4],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[5],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[6],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[7],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[8],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WDATA[9],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_WRITE,
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[10],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[11],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[12],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[13],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[14],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[15],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[16],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[17],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[18],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[19],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[20],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[21],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[22],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[23],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[24],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[25],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[26],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[27],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[28],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[29],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[2],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[30],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[31],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[3],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[4],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[5],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[6],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[7],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[8],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ADDR[9],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_ENABLE,
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_MASTLOCK,
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_READY,
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_SEL,
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_SIZE[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_SIZE[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_TRANS1,
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[10],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[11],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[12],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[13],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[14],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[15],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[16],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[17],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[18],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[19],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[20],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[21],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[22],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[23],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[24],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[25],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[26],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[27],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[28],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[29],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[2],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[30],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[31],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[3],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[4],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[5],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[6],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[7],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[8],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WDATA[9],
MSS_ADLIB_INST/INST_MSS_120_IP:F_FM1_WRITE,
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[10],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[11],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[12],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[13],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[14],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[15],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[16],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[17],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[18],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[19],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[20],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[21],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[22],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[23],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[24],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[25],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[26],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[27],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[28],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[29],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[2],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[30],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[31],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[3],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[4],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[5],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[6],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[7],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[8],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RDATA[9],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_READY,
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM0_RESP,
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[10],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[11],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[12],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[13],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[14],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[15],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[16],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[17],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[18],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[19],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[20],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[21],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[22],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[23],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[24],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[25],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[26],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[27],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[28],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[29],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[2],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[30],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[31],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[3],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[4],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[5],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[6],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[7],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[8],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RDATA[9],
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_READY,
MSS_ADLIB_INST/INST_MSS_120_IP:F_HM1_RESP,
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[10],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[11],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[12],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[13],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[14],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[15],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[16],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[17],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[18],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[19],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[20],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[21],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[22],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[23],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[24],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[25],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[26],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[27],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[28],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[29],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[2],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[30],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[31],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[32],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[33],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[34],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[35],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[36],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[37],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[38],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[39],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[3],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[40],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[41],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[42],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[43],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[44],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[45],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[46],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[47],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[48],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[49],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[4],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[50],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[51],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[52],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[53],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[54],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[55],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[56],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[57],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[58],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[59],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[5],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[60],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[61],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[62],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[63],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[6],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[7],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[8],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[9],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RID[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RID[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RID[2],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RID[3],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RLAST,
MSS_ADLIB_INST/INST_MSS_120_IP:F_RMW_AXI,
MSS_ADLIB_INST/INST_MSS_120_IP:F_RREADY,
MSS_ADLIB_INST/INST_MSS_120_IP:F_RRESP_HRESP1[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RRESP_HRESP1[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_RVALID,
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[10],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[11],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[12],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[13],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[14],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[15],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[16],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[17],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[18],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[19],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[20],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[21],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[22],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[23],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[24],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[25],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[26],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[27],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[28],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[29],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[2],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[30],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[31],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[32],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[33],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[34],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[35],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[36],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[37],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[38],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[39],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[3],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[40],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[41],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[42],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[43],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[44],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[45],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[46],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[47],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[48],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[49],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[4],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[50],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[51],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[52],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[53],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[54],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[55],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[56],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[57],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[58],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[59],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[5],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[60],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[61],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[62],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[63],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[6],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[7],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[8],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[9],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WID_HREADY01[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WID_HREADY01[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WID_HREADY01[2],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WID_HREADY01[3],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WLAST,
MSS_ADLIB_INST/INST_MSS_120_IP:F_WREADY,
MSS_ADLIB_INST/INST_MSS_120_IP:F_WSTRB[0],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WSTRB[1],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WSTRB[2],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WSTRB[3],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WSTRB[4],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WSTRB[5],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WSTRB[6],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WSTRB[7],
MSS_ADLIB_INST/INST_MSS_120_IP:F_WVALID,
MSS_ADLIB_INST/INST_MSS_120_IP:GTX_CLKPF,
MSS_ADLIB_INST/INST_MSS_120_IP:I2C0_BCLK,
MSS_ADLIB_INST/INST_MSS_120_IP:I2C0_SCL_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:I2C0_SCL_USBC_DATA1_MGPIO31B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:I2C0_SDA_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:I2C0_SDA_USBC_DATA0_MGPIO30B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:I2C1_BCLK,
MSS_ADLIB_INST/INST_MSS_120_IP:I2C1_SCL_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:I2C1_SCL_MGPIO1A_H2F_B,
MSS_ADLIB_INST/INST_MSS_120_IP:I2C1_SCL_USBA_DATA4_MGPIO1A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:I2C1_SDA_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:I2C1_SDA_MGPIO0A_H2F_B,
MSS_ADLIB_INST/INST_MSS_120_IP:I2C1_SDA_USBA_DATA3_MGPIO0A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PADDR[10],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PADDR[2],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PADDR[3],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PADDR[4],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PADDR[5],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PADDR[6],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PADDR[7],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PADDR[8],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PADDR[9],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PENABLE,
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PRDATA[0],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PRDATA[10],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PRDATA[11],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PRDATA[12],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PRDATA[13],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PRDATA[14],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PRDATA[15],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PRDATA[1],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PRDATA[2],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PRDATA[3],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PRDATA[4],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PRDATA[5],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PRDATA[6],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PRDATA[7],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PRDATA[8],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PRDATA[9],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PREADY,
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PSEL,
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PSLVERR,
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PWDATA[0],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PWDATA[10],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PWDATA[11],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PWDATA[12],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PWDATA[13],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PWDATA[14],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PWDATA[15],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PWDATA[1],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PWDATA[2],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PWDATA[3],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PWDATA[4],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PWDATA[5],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PWDATA[6],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PWDATA[7],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PWDATA[8],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PWDATA[9],
MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PWRITE,
MSS_ADLIB_INST/INST_MSS_120_IP:MDIF,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO0A_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO0B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO10A_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO10B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO11A_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO11B_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO12A_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO13A_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO14A_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO15A_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO16A_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO17B_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO18B_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO19B_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO1A_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO1B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO20B_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO21B_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO22B_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO24B_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO25A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO25B_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO26A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO26B_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO27A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO27B_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO28A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO28B_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO29A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO29B_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO2A_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO2B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO30A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO30B_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO31A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO31B_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO3A_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO3B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO4A_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO4B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO5A_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO5B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO6A_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO6B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO7A_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO7B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO8A_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO8B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO9A_F2H_GPIN,
MSS_ADLIB_INST/INST_MSS_120_IP:MGPIO9B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_CTS_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_CTS_USBC_DATA7_MGPIO19B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_DCD_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_DCD_MGPIO22B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_DSR_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_DSR_MGPIO20B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_DTR_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_DTR_USBC_DATA6_MGPIO18B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_RI_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_RI_MGPIO21B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_RTS_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_RTS_USBC_DATA5_MGPIO17B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_RXD_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_RXD_USBC_STP_MGPIO28B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_SCK_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_SCK_USBC_NXT_MGPIO29B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_TXD_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_TXD_USBC_DIR_MGPIO27B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_TXD_USBC_DIR_MGPIO27B_OE,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_TXD_USBC_DIR_MGPIO27B_OUT,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART1_CTS_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART1_CTS_MGPIO13B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART1_DCD_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART1_DCD_MGPIO16B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART1_DSR_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART1_DSR_MGPIO14B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART1_DTR_MGPIO12B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART1_RI_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART1_RI_MGPIO15B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART1_RTS_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART1_RTS_MGPIO11B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART1_RXD_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART1_RXD_USBC_DATA3_MGPIO26B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART1_SCK_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART1_SCK_USBC_DATA4_MGPIO25B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART1_TXD_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:MMUART1_TXD_USBC_DATA2_MGPIO24B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PADDR[10],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PADDR[11],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PADDR[12],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PADDR[13],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PADDR[14],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PADDR[15],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PADDR[16],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PADDR[2],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PADDR[3],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PADDR[4],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PADDR[5],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PADDR[6],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PADDR[7],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PADDR[8],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PADDR[9],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PENABLE,
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[0],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[10],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[11],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[12],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[13],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[14],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[15],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[16],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[17],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[18],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[19],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[1],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[20],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[21],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[22],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[23],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[24],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[25],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[26],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[27],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[28],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[29],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[2],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[30],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[31],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[3],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[4],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[5],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[6],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[7],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[8],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PRDATA[9],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PREADY,
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PSEL,
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PSLVERR,
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[0],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[10],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[11],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[12],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[13],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[14],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[15],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[16],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[17],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[18],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[19],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[1],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[20],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[21],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[22],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[23],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[24],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[25],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[26],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[27],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[28],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[29],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[2],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[30],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[31],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[3],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[4],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[5],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[6],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[7],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[8],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWDATA[9],
MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PWRITE,
MSS_ADLIB_INST/INST_MSS_120_IP:PRESET_N,
MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[0],
MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[1],
MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[2],
MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[3],
MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[4],
MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[5],
MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[6],
MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[7],
MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[8],
MSS_ADLIB_INST/INST_MSS_120_IP:RCGF[9],
MSS_ADLIB_INST/INST_MSS_120_IP:RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:RGMII_MDC_RMII_MDC_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:RGMII_RXD3_USBB_DATA4_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:RGMII_RX_CLK_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:RGMII_TXD0_RMII_TXD0_USBB_DIR_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:RGMII_TXD1_RMII_TXD1_USBB_STP_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:RGMII_TXD2_USBB_DATA5_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:RGMII_TXD3_USBB_DATA6_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:RGMII_TX_CLK_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:RXDF[0],
MSS_ADLIB_INST/INST_MSS_120_IP:RXDF[1],
MSS_ADLIB_INST/INST_MSS_120_IP:RXDF[2],
MSS_ADLIB_INST/INST_MSS_120_IP:RXDF[3],
MSS_ADLIB_INST/INST_MSS_120_IP:RXDF[4],
MSS_ADLIB_INST/INST_MSS_120_IP:RXDF[5],
MSS_ADLIB_INST/INST_MSS_120_IP:RXDF[6],
MSS_ADLIB_INST/INST_MSS_120_IP:RXDF[7],
MSS_ADLIB_INST/INST_MSS_120_IP:RX_CLKPF,
MSS_ADLIB_INST/INST_MSS_120_IP:RX_DVF,
MSS_ADLIB_INST/INST_MSS_120_IP:RX_ERRF,
MSS_ADLIB_INST/INST_MSS_120_IP:RX_EV,
MSS_ADLIB_INST/INST_MSS_120_IP:SLEEPHOLDREQ,
MSS_ADLIB_INST/INST_MSS_120_IP:SMBALERT_NI0,
MSS_ADLIB_INST/INST_MSS_120_IP:SMBALERT_NI1,
MSS_ADLIB_INST/INST_MSS_120_IP:SMBSUS_NI0,
MSS_ADLIB_INST/INST_MSS_120_IP:SMBSUS_NI1,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_CLK_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SCK_USBA_XCLK_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SCK_USBA_XCLK_OE,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SCK_USBA_XCLK_OUT,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SDI_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SDI_USBA_DIR_MGPIO5A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SDO_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SDO_USBA_STP_MGPIO6A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SDO_USBA_STP_MGPIO6A_OE,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SDO_USBA_STP_MGPIO6A_OUT,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SS0_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SS0_USBA_NXT_MGPIO7A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SS0_USBA_NXT_MGPIO7A_OE,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SS0_USBA_NXT_MGPIO7A_OUT,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SS1_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SS1_MGPIO8A_H2F_B,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SS1_USBA_DATA5_MGPIO8A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SS2_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SS2_MGPIO9A_H2F_B,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SS2_USBA_DATA6_MGPIO9A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SS3_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SS3_MGPIO10A_H2F_B,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SS3_USBA_DATA7_MGPIO10A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SS4_MGPIO19A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SS5_MGPIO20A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SS6_MGPIO21A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI0_SS7_MGPIO22A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI1_CLK_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI1_SCK_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI1_SDI_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI1_SDI_MGPIO11A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI1_SDO_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI1_SDO_MGPIO12A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI1_SS0_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI1_SS0_MGPIO13A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI1_SS1_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI1_SS1_MGPIO14A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI1_SS2_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI1_SS2_MGPIO15A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI1_SS3_F2H_SCP,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI1_SS3_MGPIO16A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI1_SS4_MGPIO17A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI1_SS5_MGPIO18A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI1_SS6_MGPIO23A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:SPI1_SS7_MGPIO24A_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:TX_CLKPF,
MSS_ADLIB_INST/INST_MSS_120_IP:USBC_XCLK_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:USBD_DATA0_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:USBD_DATA1_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:USBD_DATA2_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:USBD_DATA3_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:USBD_DATA4_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:USBD_DATA5_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:USBD_DATA6_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:USBD_DATA7_MGPIO23B_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:USBD_DIR_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:USBD_NXT_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:USBD_STP_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:USBD_XCLK_IN,
MSS_ADLIB_INST/INST_MSS_120_IP:USER_MSS_GPIO_RESET_N,
MSS_ADLIB_INST/INST_MSS_120_IP:USER_MSS_RESET_N,
MSS_ADLIB_INST/INST_MSS_120_IP:XCLK_FAB,
MDDR_DDR_AXI_S_RDATA_obuf[13]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[13]/U0/U_IOOUTFF:Y,
MDDR_ADDR_12_PAD/U_IOPAD:D,
MDDR_ADDR_12_PAD/U_IOPAD:E,
MDDR_ADDR_12_PAD/U_IOPAD:PAD,
FIC_0_AHB_S_HRDATA_obuf[16]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[16]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_BRESP_obuf[1]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_BRESP_obuf[1]/U0/U_IOOUTFF:Y,
FIC_2_APB_M_PRDATA_ibuf[5]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[5]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[50]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[50]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_AWID_ibuf[0]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWID_ibuf[0]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[15]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[15]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[15]/U0/U_IOPAD:PAD,
MDDR_ADDR_14_PAD/U_IOPAD:D,
MDDR_ADDR_14_PAD/U_IOPAD:E,
MDDR_ADDR_14_PAD/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RVALID_obuf/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RVALID_obuf/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_WSTRB_ibuf[5]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WSTRB_ibuf[5]/U0/U_IOPAD:Y,
FIC_2_APB_M_PWDATA_obuf[18]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[18]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[46]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[46]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[46]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RDATA_obuf[57]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[57]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[35]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[35]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[35]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_RDATA_obuf[17]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[17]/U0/U_IOOUTFF:Y,
FIC_2_APB_M_PRDATA_ibuf[6]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[6]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[61]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[61]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[29]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[29]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[32]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[32]/U0/U_IOENFF:Y,
MCCC_CLK_BASE_ibuf/U0/U_IOINFF:A,
MCCC_CLK_BASE_ibuf/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_96:A,
MSS_ADLIB_INST/IP_INTERFACE_96:B,
MSS_ADLIB_INST/IP_INTERFACE_96:C,
MSS_ADLIB_INST/IP_INTERFACE_96:IPA,
MSS_ADLIB_INST/IP_INTERFACE_73:A,
MSS_ADLIB_INST/IP_INTERFACE_73:B,
MSS_ADLIB_INST/IP_INTERFACE_73:C,
MSS_ADLIB_INST/IP_INTERFACE_73:IPA,
MDDR_DDR_AXI_S_AWADDR_ibuf[10]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[10]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[46]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[46]/U0/U_IOOUTFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_147:A,
MSS_ADLIB_INST/IP_INTERFACE_147:B,
MSS_ADLIB_INST/IP_INTERFACE_147:C,
MSS_ADLIB_INST/IP_INTERFACE_147:IPA,
MSS_ADLIB_INST/IP_INTERFACE_147:IPB,
FIC_2_APB_M_PWDATA_obuf[25]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[25]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[25]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[19]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[19]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HWDATA_ibuf[3]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[3]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RID_obuf[2]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RID_obuf[2]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[7]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[7]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[36]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[36]/U0/U_IOENFF:Y,
FIC_2_APB_M_PADDR_obuf[5]/U0/U_IOPAD:D,
FIC_2_APB_M_PADDR_obuf[5]/U0/U_IOPAD:E,
FIC_2_APB_M_PADDR_obuf[5]/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_265:A,
MSS_ADLIB_INST/IP_INTERFACE_265:B,
MSS_ADLIB_INST/IP_INTERFACE_265:C,
MSS_ADLIB_INST/IP_INTERFACE_265:IPA,
MSS_ADLIB_INST/IP_INTERFACE_265:IPB,
MDDR_DDR_AXI_S_AWVALID_ibuf/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWVALID_ibuf/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_198:A,
MSS_ADLIB_INST/IP_INTERFACE_198:B,
MSS_ADLIB_INST/IP_INTERFACE_198:C,
MSS_ADLIB_INST/IP_INTERFACE_198:IPA,
MSS_ADLIB_INST/IP_INTERFACE_198:IPB,
FIC_2_APB_M_PRDATA_ibuf[23]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[23]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[8]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[8]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RRESP_obuf[1]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RRESP_obuf[1]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[0]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[0]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[62]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[62]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HRDATA_obuf[2]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[2]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[2]/U0/U_IOPAD:PAD,
MDDR_APB_S_PWDATA_ibuf[0]/U0/U_IOINFF:A,
MDDR_APB_S_PWDATA_ibuf[0]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_AWVALID_ibuf/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWVALID_ibuf/U0/U_IOINFF:Y,
FIC_0_AHB_S_HADDR_ibuf[26]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[26]/U0/U_IOPAD:Y,
MDDR_APB_S_PSLVERR_obuf/U0/U_IOPAD:D,
MDDR_APB_S_PSLVERR_obuf/U0/U_IOPAD:E,
MDDR_APB_S_PSLVERR_obuf/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[13]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[13]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_321:A,
MSS_ADLIB_INST/IP_INTERFACE_321:B,
MSS_ADLIB_INST/IP_INTERFACE_321:C,
MSS_ADLIB_INST/IP_INTERFACE_321:IPA,
MSS_ADLIB_INST/IP_INTERFACE_321:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[45]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[45]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_340:A,
MSS_ADLIB_INST/IP_INTERFACE_340:B,
MSS_ADLIB_INST/IP_INTERFACE_340:C,
MSS_ADLIB_INST/IP_INTERFACE_340:IPA,
MSS_ADLIB_INST/IP_INTERFACE_340:IPB,
FIC_2_APB_M_PWDATA_obuf[22]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[22]/U0/U_IOENFF:Y,
FIC_0_AHB_S_HRDATA_obuf[17]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[17]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[17]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[16]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[16]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_199:A,
MSS_ADLIB_INST/IP_INTERFACE_199:B,
MSS_ADLIB_INST/IP_INTERFACE_199:C,
MSS_ADLIB_INST/IP_INTERFACE_199:IPA,
MSS_ADLIB_INST/IP_INTERFACE_199:IPB,
MDDR_DDR_AXI_S_AWADDR_ibuf[6]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[6]/U0/U_IOPAD:Y,
FIC_2_APB_M_PWDATA_obuf[8]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[8]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_107:A,
MSS_ADLIB_INST/IP_INTERFACE_107:B,
MSS_ADLIB_INST/IP_INTERFACE_107:C,
MSS_ADLIB_INST/IP_INTERFACE_107:IPB,
MDDR_DDR_AXI_S_AWADDR_ibuf[24]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[24]/U0/U_IOPAD:Y,
FIC_2_APB_M_PADDR_obuf[8]/U0/U_IOPAD:D,
FIC_2_APB_M_PADDR_obuf[8]/U0/U_IOPAD:E,
FIC_2_APB_M_PADDR_obuf[8]/U0/U_IOPAD:PAD,
MDDR_APB_S_PRDATA_obuf[5]/U0/U_IOENFF:A,
MDDR_APB_S_PRDATA_obuf[5]/U0/U_IOENFF:Y,
FIC_2_APB_M_PRDATA_ibuf[0]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[0]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[52]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[52]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[53]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[53]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[3]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[3]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HSIZE_ibuf[1]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HSIZE_ibuf[1]/U0/U_IOPAD:Y,
MDDR_ADDR_6_PAD/U_IOPAD:D,
MDDR_ADDR_6_PAD/U_IOPAD:E,
MDDR_ADDR_6_PAD/U_IOPAD:PAD,
MDDR_DQS_0_PAD/U_ION:YIN,
MDDR_DDR_AXI_S_AWBURST_ibuf[1]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWBURST_ibuf[1]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_39:A,
MSS_ADLIB_INST/IP_INTERFACE_39:B,
MSS_ADLIB_INST/IP_INTERFACE_39:C,
MSS_ADLIB_INST/IP_INTERFACE_39:IPA,
MSS_ADLIB_INST/IP_INTERFACE_39:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[54]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[54]/U0/U_IOINFF:Y,
FIC_2_APB_M_PWDATA_obuf[24]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[24]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[24]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HRDATA_obuf[29]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[29]/U0/U_IOENFF:Y,
FIC_0_AHB_S_HRDATA_obuf[12]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[12]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[12]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PWDATA_obuf[19]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[19]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[44]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[44]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_BRESP_obuf[1]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_BRESP_obuf[1]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_300:A,
MSS_ADLIB_INST/IP_INTERFACE_300:B,
MSS_ADLIB_INST/IP_INTERFACE_300:C,
MSS_ADLIB_INST/IP_INTERFACE_300:IPA,
MSS_ADLIB_INST/IP_INTERFACE_270:A,
MSS_ADLIB_INST/IP_INTERFACE_270:B,
MSS_ADLIB_INST/IP_INTERFACE_270:C,
MSS_ADLIB_INST/IP_INTERFACE_270:IPA,
MSS_ADLIB_INST/IP_INTERFACE_270:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[8]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[8]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[8]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PWDATA_obuf[6]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[6]/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[25]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[25]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_98:A,
MSS_ADLIB_INST/IP_INTERFACE_98:B,
MSS_ADLIB_INST/IP_INTERFACE_98:C,
MSS_ADLIB_INST/IP_INTERFACE_98:IPA,
MSS_ADLIB_INST/IP_INTERFACE_98:IPB,
MSS_ADLIB_INST/IP_INTERFACE_271:A,
MSS_ADLIB_INST/IP_INTERFACE_271:B,
MSS_ADLIB_INST/IP_INTERFACE_271:C,
MSS_ADLIB_INST/IP_INTERFACE_271:IPA,
MSS_ADLIB_INST/IP_INTERFACE_271:IPB,
MDDR_DDR_AXI_S_ARADDR_ibuf[7]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[7]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HRDATA_obuf[18]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[18]/U0/U_IOENFF:Y,
MDDR_APB_S_PWDATA_ibuf[13]/U0/U_IOINFF:A,
MDDR_APB_S_PWDATA_ibuf[13]/U0/U_IOINFF:Y,
GPIO_9_M2F_obuf/U0/U_IOOUTFF:A,
GPIO_9_M2F_obuf/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[36]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[36]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[25]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[25]/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HRDATA_obuf[24]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[24]/U0/U_IOOUTFF:Y,
FIC_2_APB_M_PWDATA_obuf[13]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PWDATA_obuf[13]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[1]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[1]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[1]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARLEN_ibuf[0]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARLEN_ibuf[0]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[17]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[17]/U0/U_IOPAD:Y,
SPI_0_DI_PAD/U_IOINFF:A,
SPI_0_DI_PAD/U_IOINFF:Y,
FIC_2_APB_M_PADDR_obuf[10]/U0/U_IOENFF:A,
FIC_2_APB_M_PADDR_obuf[10]/U0/U_IOENFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[22]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[22]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_285:A,
MSS_ADLIB_INST/IP_INTERFACE_285:B,
MSS_ADLIB_INST/IP_INTERFACE_285:C,
MSS_ADLIB_INST/IP_INTERFACE_285:IPA,
MSS_ADLIB_INST/IP_INTERFACE_285:IPB,
MDDR_DDR_AXI_S_AWADDR_ibuf[2]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[2]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_22:A,
MSS_ADLIB_INST/IP_INTERFACE_22:B,
MSS_ADLIB_INST/IP_INTERFACE_22:C,
MSS_ADLIB_INST/IP_INTERFACE_22:IPB,
MSS_ADLIB_INST/IP_INTERFACE_157:A,
MSS_ADLIB_INST/IP_INTERFACE_157:B,
MSS_ADLIB_INST/IP_INTERFACE_157:C,
MSS_ADLIB_INST/IP_INTERFACE_157:IPA,
MSS_ADLIB_INST/IP_INTERFACE_267:A,
MSS_ADLIB_INST/IP_INTERFACE_267:B,
MSS_ADLIB_INST/IP_INTERFACE_267:C,
MSS_ADLIB_INST/IP_INTERFACE_267:IPA,
MSS_ADLIB_INST/IP_INTERFACE_267:IPB,
FIC_2_APB_M_PWDATA_obuf[30]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[30]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[30]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[53]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[53]/U0/U_IOPAD:Y,
MDDR_APB_S_PENABLE_ibuf/U0/U_IOINFF:A,
MDDR_APB_S_PENABLE_ibuf/U0/U_IOINFF:Y,
FIC_2_APB_M_PRDATA_ibuf[10]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[10]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HRDATA_obuf[10]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[10]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_79:A,
MSS_ADLIB_INST/IP_INTERFACE_79:B,
MSS_ADLIB_INST/IP_INTERFACE_79:C,
MSS_ADLIB_INST/IP_INTERFACE_79:IPA,
MSS_ADLIB_INST/IP_INTERFACE_79:IPB,
FIC_2_APB_M_PRDATA_ibuf[27]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[27]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[11]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[11]/U0/U_IOINFF:Y,
FIC_2_APB_M_PADDR_obuf[4]/U0/U_IOPAD:D,
FIC_2_APB_M_PADDR_obuf[4]/U0/U_IOPAD:E,
FIC_2_APB_M_PADDR_obuf[4]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PWRITE_obuf/U0/U_IOPAD:D,
FIC_2_APB_M_PWRITE_obuf/U0/U_IOPAD:E,
FIC_2_APB_M_PWRITE_obuf/U0/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_125:A,
MSS_ADLIB_INST/IP_INTERFACE_125:B,
MSS_ADLIB_INST/IP_INTERFACE_125:C,
MSS_ADLIB_INST/IP_INTERFACE_125:IPA,
MSS_ADLIB_INST/IP_INTERFACE_125:IPB,
FIC_2_APB_M_PADDR_obuf[15]/U0/U_IOOUTFF:A,
FIC_2_APB_M_PADDR_obuf[15]/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[11]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[11]/U0/U_IOPAD:Y,
MDDR_APB_S_PRDATA_obuf[15]/U0/U_IOOUTFF:A,
MDDR_APB_S_PRDATA_obuf[15]/U0/U_IOOUTFF:Y,
MDDR_APB_S_PRDATA_obuf[14]/U0/U_IOOUTFF:A,
MDDR_APB_S_PRDATA_obuf[14]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_RID_obuf[1]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RID_obuf[1]/U0/U_IOENFF:Y,
FIC_2_APB_M_PSLVERR_ibuf/U0/U_IOPAD:PAD,
FIC_2_APB_M_PSLVERR_ibuf/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_350:A,
MSS_ADLIB_INST/IP_INTERFACE_350:B,
MSS_ADLIB_INST/IP_INTERFACE_350:C,
MSS_ADLIB_INST/IP_INTERFACE_350:IPA,
MSS_ADLIB_INST/IP_INTERFACE_350:IPB,
FIC_2_APB_M_PRDATA_ibuf[22]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[22]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[19]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[19]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[19]/U0/U_IOPAD:PAD,
MDDR_DQ_11_PAD/U_IOINFF:A,
MDDR_DQ_11_PAD/U_IOINFF:Y,
FIC_0_AHB_S_HWDATA_ibuf[0]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[0]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[37]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_WDATA_ibuf[37]/U0/U_IOINFF:Y,
MDDR_ADDR_2_PAD/U_IOPAD:D,
MDDR_ADDR_2_PAD/U_IOPAD:E,
MDDR_ADDR_2_PAD/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[16]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HWDATA_ibuf[16]/U0/U_IOPAD:Y,
MDDR_DQS_TMATCH_0_IN_PAD/U_IOPAD:PAD,
MDDR_DQS_TMATCH_0_IN_PAD/U_IOPAD:Y,
MDDR_DDR_AXI_S_RDATA_obuf[39]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[39]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[39]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PWDATA_obuf[9]/U0/U_IOPAD:D,
FIC_2_APB_M_PWDATA_obuf[9]/U0/U_IOPAD:E,
FIC_2_APB_M_PWDATA_obuf[9]/U0/U_IOPAD:PAD,
MSS_RESET_N_M2F_obuf/U0/U_IOOUTFF:A,
MSS_RESET_N_M2F_obuf/U0/U_IOOUTFF:Y,
MDDR_DQ_9_PAD/U_IOINFF:A,
MDDR_DQ_9_PAD/U_IOINFF:Y,
FIC_0_AHB_S_HADDR_ibuf[17]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[17]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_8:A,
MSS_ADLIB_INST/IP_INTERFACE_8:B,
MSS_ADLIB_INST/IP_INTERFACE_8:C,
MSS_ADLIB_INST/IP_INTERFACE_8:IPA,
MSS_ADLIB_INST/IP_INTERFACE_8:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[12]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[12]/U0/U_IOOUTFF:Y,
FIC_2_APB_M_PADDR_obuf[3]/U0/U_IOPAD:D,
FIC_2_APB_M_PADDR_obuf[3]/U0/U_IOPAD:E,
FIC_2_APB_M_PADDR_obuf[3]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARLEN_ibuf[3]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARLEN_ibuf[3]/U0/U_IOPAD:Y,
GPIO_1_M2F_obuf/U0/U_IOENFF:A,
GPIO_1_M2F_obuf/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_269:A,
MSS_ADLIB_INST/IP_INTERFACE_269:B,
MSS_ADLIB_INST/IP_INTERFACE_269:C,
MSS_ADLIB_INST/IP_INTERFACE_269:IPA,
MSS_ADLIB_INST/IP_INTERFACE_269:IPB,
MDDR_DQS_1_PAD/U_ION:YIN,
MDDR_DDR_AXI_S_WSTRB_ibuf[4]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WSTRB_ibuf[4]/U0/U_IOPAD:Y,
FIC_2_APB_M_PADDR_obuf[13]/U0/U_IOPAD:D,
FIC_2_APB_M_PADDR_obuf[13]/U0/U_IOPAD:E,
FIC_2_APB_M_PADDR_obuf[13]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[63]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[63]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_ARLOCK_ibuf[0]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARLOCK_ibuf[0]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_94:A,
MSS_ADLIB_INST/IP_INTERFACE_94:B,
MSS_ADLIB_INST/IP_INTERFACE_94:C,
MSS_ADLIB_INST/IP_INTERFACE_94:IPB,
MDDR_BA_2_PAD/U_IOPAD:D,
MDDR_BA_2_PAD/U_IOPAD:E,
MDDR_BA_2_PAD/U_IOPAD:PAD,
MSS_ADLIB_INST/IP_INTERFACE_368:A,
MSS_ADLIB_INST/IP_INTERFACE_368:B,
MSS_ADLIB_INST/IP_INTERFACE_368:C,
MSS_ADLIB_INST/IP_INTERFACE_368:IPA,
MSS_ADLIB_INST/IP_INTERFACE_116:A,
MSS_ADLIB_INST/IP_INTERFACE_116:B,
MSS_ADLIB_INST/IP_INTERFACE_116:C,
MSS_ADLIB_INST/IP_INTERFACE_116:IPA,
MSS_ADLIB_INST/IP_INTERFACE_116:IPB,
FIC_2_APB_M_PWDATA_obuf[2]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[2]/U0/U_IOENFF:Y,
FIC_2_APB_M_PWDATA_obuf[12]/U0/U_IOENFF:A,
FIC_2_APB_M_PWDATA_obuf[12]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[55]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[55]/U0/U_IOPAD:Y,
FIC_2_APB_M_PRDATA_ibuf[26]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[26]/U0/U_IOINFF:Y,
GPIO_8_M2F_obuf/U0/U_IOOUTFF:A,
GPIO_8_M2F_obuf/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_AWLOCK_ibuf[1]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWLOCK_ibuf[1]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_365:A,
MSS_ADLIB_INST/IP_INTERFACE_365:B,
MSS_ADLIB_INST/IP_INTERFACE_365:C,
MSS_ADLIB_INST/IP_INTERFACE_365:IPA,
MSS_ADLIB_INST/IP_INTERFACE_365:IPB,
MSS_ADLIB_INST/IP_INTERFACE_245:A,
MSS_ADLIB_INST/IP_INTERFACE_245:B,
MSS_ADLIB_INST/IP_INTERFACE_245:C,
MSS_ADLIB_INST/IP_INTERFACE_245:IPA,
MSS_ADLIB_INST/IP_INTERFACE_174:A,
MSS_ADLIB_INST/IP_INTERFACE_174:B,
MSS_ADLIB_INST/IP_INTERFACE_174:C,
MSS_ADLIB_INST/IP_INTERFACE_174:IPA,
MSS_ADLIB_INST/IP_INTERFACE_174:IPB,
MDDR_DDR_AXI_S_ARADDR_ibuf[18]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[18]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HSIZE_ibuf[0]/U0/U_IOINFF:A,
FIC_0_AHB_S_HSIZE_ibuf[0]/U0/U_IOINFF:Y,
MDDR_DQ_14_PAD/U_IOPAD:D,
MDDR_DQ_14_PAD/U_IOPAD:E,
MDDR_DQ_14_PAD/U_IOPAD:PAD,
MDDR_DQ_14_PAD/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_86:A,
MSS_ADLIB_INST/IP_INTERFACE_86:B,
MSS_ADLIB_INST/IP_INTERFACE_86:C,
MSS_ADLIB_INST/IP_INTERFACE_86:IPA,
MSS_ADLIB_INST/IP_INTERFACE_86:IPB,
FIC_0_AHB_S_HRDATA_obuf[8]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[8]/U0/U_IOENFF:Y,
FIC_0_AHB_S_HRDATA_obuf[27]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[27]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_273:A,
MSS_ADLIB_INST/IP_INTERFACE_273:B,
MSS_ADLIB_INST/IP_INTERFACE_273:C,
MSS_ADLIB_INST/IP_INTERFACE_273:IPA,
MSS_ADLIB_INST/IP_INTERFACE_273:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[13]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[13]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_287:A,
MSS_ADLIB_INST/IP_INTERFACE_287:B,
MSS_ADLIB_INST/IP_INTERFACE_287:C,
MSS_ADLIB_INST/IP_INTERFACE_287:IPB,
FIC_0_AHB_S_HADDR_ibuf[13]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[13]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_90:A,
MSS_ADLIB_INST/IP_INTERFACE_90:B,
MSS_ADLIB_INST/IP_INTERFACE_90:C,
MSS_ADLIB_INST/IP_INTERFACE_90:IPA,
MSS_ADLIB_INST/IP_INTERFACE_90:IPB,
MDDR_APB_S_PWDATA_ibuf[6]/U0/U_IOINFF:A,
MDDR_APB_S_PWDATA_ibuf[6]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HADDR_ibuf[5]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[5]/U0/U_IOPAD:Y,
MDDR_APB_S_PWDATA_ibuf[12]/U0/U_IOINFF:A,
MDDR_APB_S_PWDATA_ibuf[12]/U0/U_IOINFF:Y,
FIC_2_APB_M_PRDATA_ibuf[1]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[1]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HRDATA_obuf[4]/U0/U_IOENFF:A,
FIC_0_AHB_S_HRDATA_obuf[4]/U0/U_IOENFF:Y,
FIC_2_APB_M_PRESET_N_obuf/U0/U_IOPAD:D,
FIC_2_APB_M_PRESET_N_obuf/U0/U_IOPAD:E,
FIC_2_APB_M_PRESET_N_obuf/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[0]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[0]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_316:A,
MSS_ADLIB_INST/IP_INTERFACE_316:B,
MSS_ADLIB_INST/IP_INTERFACE_316:C,
MSS_ADLIB_INST/IP_INTERFACE_316:IPA,
MSS_ADLIB_INST/IP_INTERFACE_316:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[28]/U0/U_IOPAD:D,
MDDR_DDR_AXI_S_RDATA_obuf[28]/U0/U_IOPAD:E,
MDDR_DDR_AXI_S_RDATA_obuf[28]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[13]/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HADDR_ibuf[13]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_205:A,
MSS_ADLIB_INST/IP_INTERFACE_205:B,
MSS_ADLIB_INST/IP_INTERFACE_205:C,
MSS_ADLIB_INST/IP_INTERFACE_205:IPA,
MSS_ADLIB_INST/IP_INTERFACE_123:A,
MSS_ADLIB_INST/IP_INTERFACE_123:B,
MSS_ADLIB_INST/IP_INTERFACE_123:C,
MSS_ADLIB_INST/IP_INTERFACE_123:IPA,
MSS_ADLIB_INST/IP_INTERFACE_123:IPB,
MDDR_DDR_AXI_S_WDATA_ibuf[28]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[28]/U0/U_IOPAD:Y,
MDDR_APB_S_PRDATA_obuf[12]/U0/U_IOOUTFF:A,
MDDR_APB_S_PRDATA_obuf[12]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[7]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[7]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HREADYOUT_obuf/U0/U_IOENFF:A,
FIC_0_AHB_S_HREADYOUT_obuf/U0/U_IOENFF:Y,
MDDR_ADDR_5_PAD/U_IOPAD:D,
MDDR_ADDR_5_PAD/U_IOPAD:E,
MDDR_ADDR_5_PAD/U_IOPAD:PAD,
GPIO_8_M2F_obuf/U0/U_IOPAD:D,
GPIO_8_M2F_obuf/U0/U_IOPAD:E,
GPIO_8_M2F_obuf/U0/U_IOPAD:PAD,
FIC_0_AHB_S_HREADYOUT_obuf/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HREADYOUT_obuf/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HRDATA_obuf[30]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[30]/U0/U_IOOUTFF:Y,
MDDR_DDR_AXI_S_AWID_ibuf[0]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWID_ibuf[0]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_ARLEN_ibuf[0]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARLEN_ibuf[0]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[13]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_ARADDR_ibuf[13]/U0/U_IOPAD:Y,
M3_RESET_N_ibuf/U0/U_IOPAD:PAD,
M3_RESET_N_ibuf/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_WDATA_ibuf[22]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_WDATA_ibuf[22]/U0/U_IOPAD:Y,
FIC_0_AHB_S_HRDATA_obuf[20]/U0/U_IOPAD:D,
FIC_0_AHB_S_HRDATA_obuf[20]/U0/U_IOPAD:E,
FIC_0_AHB_S_HRDATA_obuf[20]/U0/U_IOPAD:PAD,
MDDR_APB_S_PWDATA_ibuf[3]/U0/U_IOPAD:PAD,
MDDR_APB_S_PWDATA_ibuf[3]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_289:A,
MSS_ADLIB_INST/IP_INTERFACE_289:B,
MSS_ADLIB_INST/IP_INTERFACE_289:C,
MSS_ADLIB_INST/IP_INTERFACE_289:IPA,
MSS_ADLIB_INST/IP_INTERFACE_289:IPB,
FIC_2_APB_M_PRDATA_ibuf[17]/U0/U_IOINFF:A,
FIC_2_APB_M_PRDATA_ibuf[17]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_137:A,
MSS_ADLIB_INST/IP_INTERFACE_137:B,
MSS_ADLIB_INST/IP_INTERFACE_137:C,
MSS_ADLIB_INST/IP_INTERFACE_137:IPA,
MSS_ADLIB_INST/IP_INTERFACE_137:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[38]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[38]/U0/U_IOENFF:Y,
MDDR_DDR_AXI_S_AWADDR_ibuf[0]/U0/U_IOPAD:PAD,
MDDR_DDR_AXI_S_AWADDR_ibuf[0]/U0/U_IOPAD:Y,
MDDR_DDR_AXI_S_ARADDR_ibuf[19]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_ARADDR_ibuf[19]/U0/U_IOINFF:Y,
FIC_0_AHB_S_HRDATA_obuf[15]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[15]/U0/U_IOOUTFF:Y,
MDDR_APB_S_PWDATA_ibuf[11]/U0/U_IOPAD:PAD,
MDDR_APB_S_PWDATA_ibuf[11]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_42:A,
MSS_ADLIB_INST/IP_INTERFACE_42:B,
MSS_ADLIB_INST/IP_INTERFACE_42:C,
MSS_ADLIB_INST/IP_INTERFACE_42:IPA,
MSS_ADLIB_INST/IP_INTERFACE_42:IPB,
MSS_ADLIB_INST/IP_INTERFACE_160:A,
MSS_ADLIB_INST/IP_INTERFACE_160:B,
MSS_ADLIB_INST/IP_INTERFACE_160:C,
MSS_ADLIB_INST/IP_INTERFACE_160:IPA,
MSS_ADLIB_INST/IP_INTERFACE_160:IPB,
MDDR_DDR_AXI_S_AWADDR_ibuf[9]/U0/U_IOINFF:A,
MDDR_DDR_AXI_S_AWADDR_ibuf[9]/U0/U_IOINFF:Y,
FIC_2_APB_M_PRDATA_ibuf[7]/U0/U_IOPAD:PAD,
FIC_2_APB_M_PRDATA_ibuf[7]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_95:A,
MSS_ADLIB_INST/IP_INTERFACE_95:B,
MSS_ADLIB_INST/IP_INTERFACE_95:C,
MSS_ADLIB_INST/IP_INTERFACE_95:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[41]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[41]/U0/U_IOENFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_367:A,
MSS_ADLIB_INST/IP_INTERFACE_367:B,
MSS_ADLIB_INST/IP_INTERFACE_367:C,
MSS_ADLIB_INST/IP_INTERFACE_367:IPA,
MSS_ADLIB_INST/IP_INTERFACE_367:IPB,
MDDR_DDR_AXI_S_RDATA_obuf[24]/U0/U_IOOUTFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[24]/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HRDATA_obuf[5]/U0/U_IOOUTFF:A,
FIC_0_AHB_S_HRDATA_obuf[5]/U0/U_IOOUTFF:Y,
FIC_0_AHB_S_HADDR_ibuf[14]/U0/U_IOINFF:A,
FIC_0_AHB_S_HADDR_ibuf[14]/U0/U_IOINFF:Y,
MSS_ADLIB_INST/IP_INTERFACE_88:A,
MSS_ADLIB_INST/IP_INTERFACE_88:B,
MSS_ADLIB_INST/IP_INTERFACE_88:C,
MSS_ADLIB_INST/IP_INTERFACE_88:IPA,
MSS_ADLIB_INST/IP_INTERFACE_88:IPB,
MDDR_APB_S_PWDATA_ibuf[0]/U0/U_IOPAD:PAD,
MDDR_APB_S_PWDATA_ibuf[0]/U0/U_IOPAD:Y,
MSS_ADLIB_INST/IP_INTERFACE_330:A,
MSS_ADLIB_INST/IP_INTERFACE_330:B,
MSS_ADLIB_INST/IP_INTERFACE_330:C,
MSS_ADLIB_INST/IP_INTERFACE_330:IPA,
MSS_ADLIB_INST/IP_INTERFACE_330:IPB,
MSS_ADLIB_INST/IP_INTERFACE_255:A,
MSS_ADLIB_INST/IP_INTERFACE_255:B,
MSS_ADLIB_INST/IP_INTERFACE_255:C,
MSS_ADLIB_INST/IP_INTERFACE_255:IPA,
MSS_ADLIB_INST/IP_INTERFACE_255:IPB,
MSS_ADLIB_INST/IP_INTERFACE_247:A,
MSS_ADLIB_INST/IP_INTERFACE_247:B,
MSS_ADLIB_INST/IP_INTERFACE_247:C,
MSS_ADLIB_INST/IP_INTERFACE_247:IPA,
FIC_0_AHB_S_HWDATA_ibuf[31]/U0/U_IOINFF:A,
FIC_0_AHB_S_HWDATA_ibuf[31]/U0/U_IOINFF:Y,
MDDR_DDR_AXI_S_RDATA_obuf[15]/U0/U_IOENFF:A,
MDDR_DDR_AXI_S_RDATA_obuf[15]/U0/U_IOENFF:Y,
MDDR_DQS_TMATCH_0_IN,
MMUART_0_RXD,
SPI_0_DI,
MDDR_ADDR<0>,
MDDR_ADDR<1>,
MDDR_ADDR<2>,
MDDR_ADDR<3>,
MDDR_ADDR<4>,
MDDR_ADDR<5>,
MDDR_ADDR<6>,
MDDR_ADDR<7>,
MDDR_ADDR<8>,
MDDR_ADDR<9>,
MDDR_ADDR<10>,
MDDR_ADDR<11>,
MDDR_ADDR<12>,
MDDR_ADDR<13>,
MDDR_ADDR<14>,
MDDR_ADDR<15>,
MDDR_BA<0>,
MDDR_BA<1>,
MDDR_BA<2>,
MDDR_CAS_N,
MDDR_CKE,
MDDR_CLK,
MDDR_CLK_N,
MDDR_CS_N,
MDDR_DQS_TMATCH_0_OUT,
MDDR_ODT,
MDDR_RAS_N,
MDDR_RESET_N,
MDDR_WE_N,
MMUART_0_TXD,
SPI_0_DO,
MDDR_DM_RDQS<0>,
MDDR_DM_RDQS<1>,
MDDR_DQ<0>,
MDDR_DQ<1>,
MDDR_DQ<2>,
MDDR_DQ<3>,
MDDR_DQ<4>,
MDDR_DQ<5>,
MDDR_DQ<6>,
MDDR_DQ<7>,
MDDR_DQ<8>,
MDDR_DQ<9>,
MDDR_DQ<10>,
MDDR_DQ<11>,
MDDR_DQ<12>,
MDDR_DQ<13>,
MDDR_DQ<14>,
MDDR_DQ<15>,
MDDR_DQS<0>,
MDDR_DQS<1>,
MDDR_DQS_N<0>,
MDDR_DQS_N<1>,
SPI_0_CLK,
SPI_0_SS0,
FIC_0_AHB_S_HADDR<0>,
FIC_0_AHB_S_HADDR<1>,
FIC_0_AHB_S_HADDR<2>,
FIC_0_AHB_S_HADDR<3>,
FIC_0_AHB_S_HADDR<4>,
FIC_0_AHB_S_HADDR<5>,
FIC_0_AHB_S_HADDR<6>,
FIC_0_AHB_S_HADDR<7>,
FIC_0_AHB_S_HADDR<8>,
FIC_0_AHB_S_HADDR<9>,
FIC_0_AHB_S_HADDR<10>,
FIC_0_AHB_S_HADDR<11>,
FIC_0_AHB_S_HADDR<12>,
FIC_0_AHB_S_HADDR<13>,
FIC_0_AHB_S_HADDR<14>,
FIC_0_AHB_S_HADDR<15>,
FIC_0_AHB_S_HADDR<16>,
FIC_0_AHB_S_HADDR<17>,
FIC_0_AHB_S_HADDR<18>,
FIC_0_AHB_S_HADDR<19>,
FIC_0_AHB_S_HADDR<20>,
FIC_0_AHB_S_HADDR<21>,
FIC_0_AHB_S_HADDR<22>,
FIC_0_AHB_S_HADDR<23>,
FIC_0_AHB_S_HADDR<24>,
FIC_0_AHB_S_HADDR<25>,
FIC_0_AHB_S_HADDR<26>,
FIC_0_AHB_S_HADDR<27>,
FIC_0_AHB_S_HADDR<28>,
FIC_0_AHB_S_HADDR<29>,
FIC_0_AHB_S_HADDR<30>,
FIC_0_AHB_S_HADDR<31>,
FIC_0_AHB_S_HMASTLOCK,
FIC_0_AHB_S_HREADY,
FIC_0_AHB_S_HSEL,
FIC_0_AHB_S_HSIZE<0>,
FIC_0_AHB_S_HSIZE<1>,
FIC_0_AHB_S_HTRANS<1>,
FIC_0_AHB_S_HWDATA<0>,
FIC_0_AHB_S_HWDATA<1>,
FIC_0_AHB_S_HWDATA<2>,
FIC_0_AHB_S_HWDATA<3>,
FIC_0_AHB_S_HWDATA<4>,
FIC_0_AHB_S_HWDATA<5>,
FIC_0_AHB_S_HWDATA<6>,
FIC_0_AHB_S_HWDATA<7>,
FIC_0_AHB_S_HWDATA<8>,
FIC_0_AHB_S_HWDATA<9>,
FIC_0_AHB_S_HWDATA<10>,
FIC_0_AHB_S_HWDATA<11>,
FIC_0_AHB_S_HWDATA<12>,
FIC_0_AHB_S_HWDATA<13>,
FIC_0_AHB_S_HWDATA<14>,
FIC_0_AHB_S_HWDATA<15>,
FIC_0_AHB_S_HWDATA<16>,
FIC_0_AHB_S_HWDATA<17>,
FIC_0_AHB_S_HWDATA<18>,
FIC_0_AHB_S_HWDATA<19>,
FIC_0_AHB_S_HWDATA<20>,
FIC_0_AHB_S_HWDATA<21>,
FIC_0_AHB_S_HWDATA<22>,
FIC_0_AHB_S_HWDATA<23>,
FIC_0_AHB_S_HWDATA<24>,
FIC_0_AHB_S_HWDATA<25>,
FIC_0_AHB_S_HWDATA<26>,
FIC_0_AHB_S_HWDATA<27>,
FIC_0_AHB_S_HWDATA<28>,
FIC_0_AHB_S_HWDATA<29>,
FIC_0_AHB_S_HWDATA<30>,
FIC_0_AHB_S_HWDATA<31>,
FIC_0_AHB_S_HWRITE,
FIC_2_APB_M_PRDATA<0>,
FIC_2_APB_M_PRDATA<1>,
FIC_2_APB_M_PRDATA<2>,
FIC_2_APB_M_PRDATA<3>,
FIC_2_APB_M_PRDATA<4>,
FIC_2_APB_M_PRDATA<5>,
FIC_2_APB_M_PRDATA<6>,
FIC_2_APB_M_PRDATA<7>,
FIC_2_APB_M_PRDATA<8>,
FIC_2_APB_M_PRDATA<9>,
FIC_2_APB_M_PRDATA<10>,
FIC_2_APB_M_PRDATA<11>,
FIC_2_APB_M_PRDATA<12>,
FIC_2_APB_M_PRDATA<13>,
FIC_2_APB_M_PRDATA<14>,
FIC_2_APB_M_PRDATA<15>,
FIC_2_APB_M_PRDATA<16>,
FIC_2_APB_M_PRDATA<17>,
FIC_2_APB_M_PRDATA<18>,
FIC_2_APB_M_PRDATA<19>,
FIC_2_APB_M_PRDATA<20>,
FIC_2_APB_M_PRDATA<21>,
FIC_2_APB_M_PRDATA<22>,
FIC_2_APB_M_PRDATA<23>,
FIC_2_APB_M_PRDATA<24>,
FIC_2_APB_M_PRDATA<25>,
FIC_2_APB_M_PRDATA<26>,
FIC_2_APB_M_PRDATA<27>,
FIC_2_APB_M_PRDATA<28>,
FIC_2_APB_M_PRDATA<29>,
FIC_2_APB_M_PRDATA<30>,
FIC_2_APB_M_PRDATA<31>,
FIC_2_APB_M_PREADY,
FIC_2_APB_M_PSLVERR,
GPIO_11_F2M,
GPIO_12_F2M,
M3_RESET_N,
MCCC_CLK_BASE,
MCCC_CLK_BASE_PLL_LOCK,
MDDR_APB_S_PADDR<2>,
MDDR_APB_S_PADDR<3>,
MDDR_APB_S_PADDR<4>,
MDDR_APB_S_PADDR<5>,
MDDR_APB_S_PADDR<6>,
MDDR_APB_S_PADDR<7>,
MDDR_APB_S_PADDR<8>,
MDDR_APB_S_PADDR<9>,
MDDR_APB_S_PADDR<10>,
MDDR_APB_S_PCLK,
MDDR_APB_S_PENABLE,
MDDR_APB_S_PRESET_N,
MDDR_APB_S_PSEL,
MDDR_APB_S_PWDATA<0>,
MDDR_APB_S_PWDATA<1>,
MDDR_APB_S_PWDATA<2>,
MDDR_APB_S_PWDATA<3>,
MDDR_APB_S_PWDATA<4>,
MDDR_APB_S_PWDATA<5>,
MDDR_APB_S_PWDATA<6>,
MDDR_APB_S_PWDATA<7>,
MDDR_APB_S_PWDATA<8>,
MDDR_APB_S_PWDATA<9>,
MDDR_APB_S_PWDATA<10>,
MDDR_APB_S_PWDATA<11>,
MDDR_APB_S_PWDATA<12>,
MDDR_APB_S_PWDATA<13>,
MDDR_APB_S_PWDATA<14>,
MDDR_APB_S_PWDATA<15>,
MDDR_APB_S_PWRITE,
MDDR_DDR_AXI_S_ARADDR<0>,
MDDR_DDR_AXI_S_ARADDR<1>,
MDDR_DDR_AXI_S_ARADDR<2>,
MDDR_DDR_AXI_S_ARADDR<3>,
MDDR_DDR_AXI_S_ARADDR<4>,
MDDR_DDR_AXI_S_ARADDR<5>,
MDDR_DDR_AXI_S_ARADDR<6>,
MDDR_DDR_AXI_S_ARADDR<7>,
MDDR_DDR_AXI_S_ARADDR<8>,
MDDR_DDR_AXI_S_ARADDR<9>,
MDDR_DDR_AXI_S_ARADDR<10>,
MDDR_DDR_AXI_S_ARADDR<11>,
MDDR_DDR_AXI_S_ARADDR<12>,
MDDR_DDR_AXI_S_ARADDR<13>,
MDDR_DDR_AXI_S_ARADDR<14>,
MDDR_DDR_AXI_S_ARADDR<15>,
MDDR_DDR_AXI_S_ARADDR<16>,
MDDR_DDR_AXI_S_ARADDR<17>,
MDDR_DDR_AXI_S_ARADDR<18>,
MDDR_DDR_AXI_S_ARADDR<19>,
MDDR_DDR_AXI_S_ARADDR<20>,
MDDR_DDR_AXI_S_ARADDR<21>,
MDDR_DDR_AXI_S_ARADDR<22>,
MDDR_DDR_AXI_S_ARADDR<23>,
MDDR_DDR_AXI_S_ARADDR<24>,
MDDR_DDR_AXI_S_ARADDR<25>,
MDDR_DDR_AXI_S_ARADDR<26>,
MDDR_DDR_AXI_S_ARADDR<27>,
MDDR_DDR_AXI_S_ARADDR<28>,
MDDR_DDR_AXI_S_ARADDR<29>,
MDDR_DDR_AXI_S_ARADDR<30>,
MDDR_DDR_AXI_S_ARADDR<31>,
MDDR_DDR_AXI_S_ARBURST<0>,
MDDR_DDR_AXI_S_ARBURST<1>,
MDDR_DDR_AXI_S_ARID<0>,
MDDR_DDR_AXI_S_ARID<1>,
MDDR_DDR_AXI_S_ARID<2>,
MDDR_DDR_AXI_S_ARID<3>,
MDDR_DDR_AXI_S_ARLEN<0>,
MDDR_DDR_AXI_S_ARLEN<1>,
MDDR_DDR_AXI_S_ARLEN<2>,
MDDR_DDR_AXI_S_ARLEN<3>,
MDDR_DDR_AXI_S_ARLOCK<0>,
MDDR_DDR_AXI_S_ARLOCK<1>,
MDDR_DDR_AXI_S_ARSIZE<0>,
MDDR_DDR_AXI_S_ARSIZE<1>,
MDDR_DDR_AXI_S_ARVALID,
MDDR_DDR_AXI_S_AWADDR<0>,
MDDR_DDR_AXI_S_AWADDR<1>,
MDDR_DDR_AXI_S_AWADDR<2>,
MDDR_DDR_AXI_S_AWADDR<3>,
MDDR_DDR_AXI_S_AWADDR<4>,
MDDR_DDR_AXI_S_AWADDR<5>,
MDDR_DDR_AXI_S_AWADDR<6>,
MDDR_DDR_AXI_S_AWADDR<7>,
MDDR_DDR_AXI_S_AWADDR<8>,
MDDR_DDR_AXI_S_AWADDR<9>,
MDDR_DDR_AXI_S_AWADDR<10>,
MDDR_DDR_AXI_S_AWADDR<11>,
MDDR_DDR_AXI_S_AWADDR<12>,
MDDR_DDR_AXI_S_AWADDR<13>,
MDDR_DDR_AXI_S_AWADDR<14>,
MDDR_DDR_AXI_S_AWADDR<15>,
MDDR_DDR_AXI_S_AWADDR<16>,
MDDR_DDR_AXI_S_AWADDR<17>,
MDDR_DDR_AXI_S_AWADDR<18>,
MDDR_DDR_AXI_S_AWADDR<19>,
MDDR_DDR_AXI_S_AWADDR<20>,
MDDR_DDR_AXI_S_AWADDR<21>,
MDDR_DDR_AXI_S_AWADDR<22>,
MDDR_DDR_AXI_S_AWADDR<23>,
MDDR_DDR_AXI_S_AWADDR<24>,
MDDR_DDR_AXI_S_AWADDR<25>,
MDDR_DDR_AXI_S_AWADDR<26>,
MDDR_DDR_AXI_S_AWADDR<27>,
MDDR_DDR_AXI_S_AWADDR<28>,
MDDR_DDR_AXI_S_AWADDR<29>,
MDDR_DDR_AXI_S_AWADDR<30>,
MDDR_DDR_AXI_S_AWADDR<31>,
MDDR_DDR_AXI_S_AWBURST<0>,
MDDR_DDR_AXI_S_AWBURST<1>,
MDDR_DDR_AXI_S_AWID<0>,
MDDR_DDR_AXI_S_AWID<1>,
MDDR_DDR_AXI_S_AWID<2>,
MDDR_DDR_AXI_S_AWID<3>,
MDDR_DDR_AXI_S_AWLEN<0>,
MDDR_DDR_AXI_S_AWLEN<1>,
MDDR_DDR_AXI_S_AWLEN<2>,
MDDR_DDR_AXI_S_AWLEN<3>,
MDDR_DDR_AXI_S_AWLOCK<0>,
MDDR_DDR_AXI_S_AWLOCK<1>,
MDDR_DDR_AXI_S_AWSIZE<0>,
MDDR_DDR_AXI_S_AWSIZE<1>,
MDDR_DDR_AXI_S_AWVALID,
MDDR_DDR_AXI_S_BREADY,
MDDR_DDR_AXI_S_RMW,
MDDR_DDR_AXI_S_RREADY,
MDDR_DDR_AXI_S_WDATA<0>,
MDDR_DDR_AXI_S_WDATA<1>,
MDDR_DDR_AXI_S_WDATA<2>,
MDDR_DDR_AXI_S_WDATA<3>,
MDDR_DDR_AXI_S_WDATA<4>,
MDDR_DDR_AXI_S_WDATA<5>,
MDDR_DDR_AXI_S_WDATA<6>,
MDDR_DDR_AXI_S_WDATA<7>,
MDDR_DDR_AXI_S_WDATA<8>,
MDDR_DDR_AXI_S_WDATA<9>,
MDDR_DDR_AXI_S_WDATA<10>,
MDDR_DDR_AXI_S_WDATA<11>,
MDDR_DDR_AXI_S_WDATA<12>,
MDDR_DDR_AXI_S_WDATA<13>,
MDDR_DDR_AXI_S_WDATA<14>,
MDDR_DDR_AXI_S_WDATA<15>,
MDDR_DDR_AXI_S_WDATA<16>,
MDDR_DDR_AXI_S_WDATA<17>,
MDDR_DDR_AXI_S_WDATA<18>,
MDDR_DDR_AXI_S_WDATA<19>,
MDDR_DDR_AXI_S_WDATA<20>,
MDDR_DDR_AXI_S_WDATA<21>,
MDDR_DDR_AXI_S_WDATA<22>,
MDDR_DDR_AXI_S_WDATA<23>,
MDDR_DDR_AXI_S_WDATA<24>,
MDDR_DDR_AXI_S_WDATA<25>,
MDDR_DDR_AXI_S_WDATA<26>,
MDDR_DDR_AXI_S_WDATA<27>,
MDDR_DDR_AXI_S_WDATA<28>,
MDDR_DDR_AXI_S_WDATA<29>,
MDDR_DDR_AXI_S_WDATA<30>,
MDDR_DDR_AXI_S_WDATA<31>,
MDDR_DDR_AXI_S_WDATA<32>,
MDDR_DDR_AXI_S_WDATA<33>,
MDDR_DDR_AXI_S_WDATA<34>,
MDDR_DDR_AXI_S_WDATA<35>,
MDDR_DDR_AXI_S_WDATA<36>,
MDDR_DDR_AXI_S_WDATA<37>,
MDDR_DDR_AXI_S_WDATA<38>,
MDDR_DDR_AXI_S_WDATA<39>,
MDDR_DDR_AXI_S_WDATA<40>,
MDDR_DDR_AXI_S_WDATA<41>,
MDDR_DDR_AXI_S_WDATA<42>,
MDDR_DDR_AXI_S_WDATA<43>,
MDDR_DDR_AXI_S_WDATA<44>,
MDDR_DDR_AXI_S_WDATA<45>,
MDDR_DDR_AXI_S_WDATA<46>,
MDDR_DDR_AXI_S_WDATA<47>,
MDDR_DDR_AXI_S_WDATA<48>,
MDDR_DDR_AXI_S_WDATA<49>,
MDDR_DDR_AXI_S_WDATA<50>,
MDDR_DDR_AXI_S_WDATA<51>,
MDDR_DDR_AXI_S_WDATA<52>,
MDDR_DDR_AXI_S_WDATA<53>,
MDDR_DDR_AXI_S_WDATA<54>,
MDDR_DDR_AXI_S_WDATA<55>,
MDDR_DDR_AXI_S_WDATA<56>,
MDDR_DDR_AXI_S_WDATA<57>,
MDDR_DDR_AXI_S_WDATA<58>,
MDDR_DDR_AXI_S_WDATA<59>,
MDDR_DDR_AXI_S_WDATA<60>,
MDDR_DDR_AXI_S_WDATA<61>,
MDDR_DDR_AXI_S_WDATA<62>,
MDDR_DDR_AXI_S_WDATA<63>,
MDDR_DDR_AXI_S_WID<0>,
MDDR_DDR_AXI_S_WID<1>,
MDDR_DDR_AXI_S_WID<2>,
MDDR_DDR_AXI_S_WID<3>,
MDDR_DDR_AXI_S_WLAST,
MDDR_DDR_AXI_S_WSTRB<0>,
MDDR_DDR_AXI_S_WSTRB<1>,
MDDR_DDR_AXI_S_WSTRB<2>,
MDDR_DDR_AXI_S_WSTRB<3>,
MDDR_DDR_AXI_S_WSTRB<4>,
MDDR_DDR_AXI_S_WSTRB<5>,
MDDR_DDR_AXI_S_WSTRB<6>,
MDDR_DDR_AXI_S_WSTRB<7>,
MDDR_DDR_AXI_S_WVALID,
MDDR_DDR_CORE_RESET_N,
FIC_0_AHB_S_HRDATA<0>,
FIC_0_AHB_S_HRDATA<1>,
FIC_0_AHB_S_HRDATA<2>,
FIC_0_AHB_S_HRDATA<3>,
FIC_0_AHB_S_HRDATA<4>,
FIC_0_AHB_S_HRDATA<5>,
FIC_0_AHB_S_HRDATA<6>,
FIC_0_AHB_S_HRDATA<7>,
FIC_0_AHB_S_HRDATA<8>,
FIC_0_AHB_S_HRDATA<9>,
FIC_0_AHB_S_HRDATA<10>,
FIC_0_AHB_S_HRDATA<11>,
FIC_0_AHB_S_HRDATA<12>,
FIC_0_AHB_S_HRDATA<13>,
FIC_0_AHB_S_HRDATA<14>,
FIC_0_AHB_S_HRDATA<15>,
FIC_0_AHB_S_HRDATA<16>,
FIC_0_AHB_S_HRDATA<17>,
FIC_0_AHB_S_HRDATA<18>,
FIC_0_AHB_S_HRDATA<19>,
FIC_0_AHB_S_HRDATA<20>,
FIC_0_AHB_S_HRDATA<21>,
FIC_0_AHB_S_HRDATA<22>,
FIC_0_AHB_S_HRDATA<23>,
FIC_0_AHB_S_HRDATA<24>,
FIC_0_AHB_S_HRDATA<25>,
FIC_0_AHB_S_HRDATA<26>,
FIC_0_AHB_S_HRDATA<27>,
FIC_0_AHB_S_HRDATA<28>,
FIC_0_AHB_S_HRDATA<29>,
FIC_0_AHB_S_HRDATA<30>,
FIC_0_AHB_S_HRDATA<31>,
FIC_0_AHB_S_HREADYOUT,
FIC_0_AHB_S_HRESP,
FIC_2_APB_M_PADDR<2>,
FIC_2_APB_M_PADDR<3>,
FIC_2_APB_M_PADDR<4>,
FIC_2_APB_M_PADDR<5>,
FIC_2_APB_M_PADDR<6>,
FIC_2_APB_M_PADDR<7>,
FIC_2_APB_M_PADDR<8>,
FIC_2_APB_M_PADDR<9>,
FIC_2_APB_M_PADDR<10>,
FIC_2_APB_M_PADDR<11>,
FIC_2_APB_M_PADDR<12>,
FIC_2_APB_M_PADDR<13>,
FIC_2_APB_M_PADDR<14>,
FIC_2_APB_M_PADDR<15>,
FIC_2_APB_M_PADDR<16>,
FIC_2_APB_M_PCLK,
FIC_2_APB_M_PENABLE,
FIC_2_APB_M_PRESET_N,
FIC_2_APB_M_PSEL,
FIC_2_APB_M_PWDATA<0>,
FIC_2_APB_M_PWDATA<1>,
FIC_2_APB_M_PWDATA<2>,
FIC_2_APB_M_PWDATA<3>,
FIC_2_APB_M_PWDATA<4>,
FIC_2_APB_M_PWDATA<5>,
FIC_2_APB_M_PWDATA<6>,
FIC_2_APB_M_PWDATA<7>,
FIC_2_APB_M_PWDATA<8>,
FIC_2_APB_M_PWDATA<9>,
FIC_2_APB_M_PWDATA<10>,
FIC_2_APB_M_PWDATA<11>,
FIC_2_APB_M_PWDATA<12>,
FIC_2_APB_M_PWDATA<13>,
FIC_2_APB_M_PWDATA<14>,
FIC_2_APB_M_PWDATA<15>,
FIC_2_APB_M_PWDATA<16>,
FIC_2_APB_M_PWDATA<17>,
FIC_2_APB_M_PWDATA<18>,
FIC_2_APB_M_PWDATA<19>,
FIC_2_APB_M_PWDATA<20>,
FIC_2_APB_M_PWDATA<21>,
FIC_2_APB_M_PWDATA<22>,
FIC_2_APB_M_PWDATA<23>,
FIC_2_APB_M_PWDATA<24>,
FIC_2_APB_M_PWDATA<25>,
FIC_2_APB_M_PWDATA<26>,
FIC_2_APB_M_PWDATA<27>,
FIC_2_APB_M_PWDATA<28>,
FIC_2_APB_M_PWDATA<29>,
FIC_2_APB_M_PWDATA<30>,
FIC_2_APB_M_PWDATA<31>,
FIC_2_APB_M_PWRITE,
GPIO_0_M2F,
GPIO_10_M2F,
GPIO_1_M2F,
GPIO_2_M2F,
GPIO_3_M2F,
GPIO_4_M2F,
GPIO_8_M2F,
GPIO_9_M2F,
MDDR_APB_S_PRDATA<0>,
MDDR_APB_S_PRDATA<1>,
MDDR_APB_S_PRDATA<2>,
MDDR_APB_S_PRDATA<3>,
MDDR_APB_S_PRDATA<4>,
MDDR_APB_S_PRDATA<5>,
MDDR_APB_S_PRDATA<6>,
MDDR_APB_S_PRDATA<7>,
MDDR_APB_S_PRDATA<8>,
MDDR_APB_S_PRDATA<9>,
MDDR_APB_S_PRDATA<10>,
MDDR_APB_S_PRDATA<11>,
MDDR_APB_S_PRDATA<12>,
MDDR_APB_S_PRDATA<13>,
MDDR_APB_S_PRDATA<14>,
MDDR_APB_S_PRDATA<15>,
MDDR_APB_S_PREADY,
MDDR_APB_S_PSLVERR,
MDDR_DDR_AXI_S_ARREADY,
MDDR_DDR_AXI_S_AWREADY,
MDDR_DDR_AXI_S_BID<0>,
MDDR_DDR_AXI_S_BID<1>,
MDDR_DDR_AXI_S_BID<2>,
MDDR_DDR_AXI_S_BID<3>,
MDDR_DDR_AXI_S_BRESP<0>,
MDDR_DDR_AXI_S_BRESP<1>,
MDDR_DDR_AXI_S_BVALID,
MDDR_DDR_AXI_S_RDATA<0>,
MDDR_DDR_AXI_S_RDATA<1>,
MDDR_DDR_AXI_S_RDATA<2>,
MDDR_DDR_AXI_S_RDATA<3>,
MDDR_DDR_AXI_S_RDATA<4>,
MDDR_DDR_AXI_S_RDATA<5>,
MDDR_DDR_AXI_S_RDATA<6>,
MDDR_DDR_AXI_S_RDATA<7>,
MDDR_DDR_AXI_S_RDATA<8>,
MDDR_DDR_AXI_S_RDATA<9>,
MDDR_DDR_AXI_S_RDATA<10>,
MDDR_DDR_AXI_S_RDATA<11>,
MDDR_DDR_AXI_S_RDATA<12>,
MDDR_DDR_AXI_S_RDATA<13>,
MDDR_DDR_AXI_S_RDATA<14>,
MDDR_DDR_AXI_S_RDATA<15>,
MDDR_DDR_AXI_S_RDATA<16>,
MDDR_DDR_AXI_S_RDATA<17>,
MDDR_DDR_AXI_S_RDATA<18>,
MDDR_DDR_AXI_S_RDATA<19>,
MDDR_DDR_AXI_S_RDATA<20>,
MDDR_DDR_AXI_S_RDATA<21>,
MDDR_DDR_AXI_S_RDATA<22>,
MDDR_DDR_AXI_S_RDATA<23>,
MDDR_DDR_AXI_S_RDATA<24>,
MDDR_DDR_AXI_S_RDATA<25>,
MDDR_DDR_AXI_S_RDATA<26>,
MDDR_DDR_AXI_S_RDATA<27>,
MDDR_DDR_AXI_S_RDATA<28>,
MDDR_DDR_AXI_S_RDATA<29>,
MDDR_DDR_AXI_S_RDATA<30>,
MDDR_DDR_AXI_S_RDATA<31>,
MDDR_DDR_AXI_S_RDATA<32>,
MDDR_DDR_AXI_S_RDATA<33>,
MDDR_DDR_AXI_S_RDATA<34>,
MDDR_DDR_AXI_S_RDATA<35>,
MDDR_DDR_AXI_S_RDATA<36>,
MDDR_DDR_AXI_S_RDATA<37>,
MDDR_DDR_AXI_S_RDATA<38>,
MDDR_DDR_AXI_S_RDATA<39>,
MDDR_DDR_AXI_S_RDATA<40>,
MDDR_DDR_AXI_S_RDATA<41>,
MDDR_DDR_AXI_S_RDATA<42>,
MDDR_DDR_AXI_S_RDATA<43>,
MDDR_DDR_AXI_S_RDATA<44>,
MDDR_DDR_AXI_S_RDATA<45>,
MDDR_DDR_AXI_S_RDATA<46>,
MDDR_DDR_AXI_S_RDATA<47>,
MDDR_DDR_AXI_S_RDATA<48>,
MDDR_DDR_AXI_S_RDATA<49>,
MDDR_DDR_AXI_S_RDATA<50>,
MDDR_DDR_AXI_S_RDATA<51>,
MDDR_DDR_AXI_S_RDATA<52>,
MDDR_DDR_AXI_S_RDATA<53>,
MDDR_DDR_AXI_S_RDATA<54>,
MDDR_DDR_AXI_S_RDATA<55>,
MDDR_DDR_AXI_S_RDATA<56>,
MDDR_DDR_AXI_S_RDATA<57>,
MDDR_DDR_AXI_S_RDATA<58>,
MDDR_DDR_AXI_S_RDATA<59>,
MDDR_DDR_AXI_S_RDATA<60>,
MDDR_DDR_AXI_S_RDATA<61>,
MDDR_DDR_AXI_S_RDATA<62>,
MDDR_DDR_AXI_S_RDATA<63>,
MDDR_DDR_AXI_S_RID<0>,
MDDR_DDR_AXI_S_RID<1>,
MDDR_DDR_AXI_S_RID<2>,
MDDR_DDR_AXI_S_RID<3>,
MDDR_DDR_AXI_S_RLAST,
MDDR_DDR_AXI_S_RRESP<0>,
MDDR_DDR_AXI_S_RRESP<1>,
MDDR_DDR_AXI_S_RVALID,
MDDR_DDR_AXI_S_WREADY,
MSS_RESET_N_M2F,
FIC_0_AHB_S_HTRANS<0>,
