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<doc>
<title>Compile Report</title>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.4 (Version 11.4.0.112)</text>
<text>Date: Wed Sep 03 12:05:00 2014
</text>
<section><name>Device Selection</name></section>
<table>
<header>
</header>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Device</cell>
 <cell>M2S150T</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>1152 FC</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Temp</cell>
 <cell>0:25:85</cell>
</row>
<row>
 <cell>Voltage</cell>
 <cell>1.26:1.20:1.14</cell>
</row>
<row>
 <cell>Core Voltage</cell>
 <cell>1.2V</cell>
</row>
<row>
 <cell>Ramp Rate</cell>
 <cell>100ms Minimum</cell>
</row>
<row>
 <cell>System Controller Suspend Mode</cell>
 <cell>No</cell>
</row>
<row>
 <cell>PLL Supply Voltage</cell>
 <cell>2.5V</cell>
</row>
<row>
 <cell>Default I/O technology</cell>
 <cell>LVCMOS 2.5V</cell>
</row>
<row>
 <cell>Restrict Probe Pins</cell>
 <cell>Yes</cell>
</row>
</table>
<section><name>Source Files</name></section>
<table>
<header>
</header>
<row>
 <cell>Topcell</cell>
 <cell>CodeShadowing_Fabric_MSS</cell>
</row>
<row>
 <cell>Format</cell>
 <cell>EDIF</cell>
</row>
<row>
 <cell>Source</cell>
 <cell>E:\Libero_11.4_updates\SF2\HWBootEngine_method\system_builder_approch\CodeShadowing_Fabric\synthesis\CodeShadowing_Fabric_MSS.edn</cell>
</row>
</table>
<section><name>Options</name></section>
<table>
<header>
</header>
<row>
 <cell>Merge User SDC file(s) with Existing Timing Constraints</cell>
 <cell>true</cell>
</row>
<row>
 <cell>Abort Compile if errors are found in PDC file(s)</cell>
 <cell>true</cell>
</row>
<row>
 <cell>Limit the number of high fanout nets to display to</cell>
 <cell>10</cell>
</row>
</table>
<section><name>Resource Usage</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Used</cell>
 <cell>Total</cell>
 <cell>Percentage</cell>
</header>
<row>
 <cell>4LUT</cell>
 <cell>0</cell>
 <cell>146124</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>DFF</cell>
 <cell>0</cell>
 <cell>146124</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>I/O Register</cell>
 <cell>0</cell>
 <cell>1716</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>User I/O</cell>
 <cell>569</cell>
 <cell>572</cell>
 <cell>99.48</cell>
</row>
<row>
 <cell>-- Single-ended I/O</cell>
 <cell>563</cell>
 <cell>572</cell>
 <cell>98.43</cell>
</row>
<row>
 <cell>-- Differential I/O Pairs</cell>
 <cell>3</cell>
 <cell>286</cell>
 <cell>1.05</cell>
</row>
<row>
 <cell>RAM64x18</cell>
 <cell>0</cell>
 <cell>240</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>RAM1K18</cell>
 <cell>0</cell>
 <cell>236</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>MACC</cell>
 <cell>0</cell>
 <cell>240</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>Chip Global</cell>
 <cell>0</cell>
 <cell>16</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>CCC</cell>
 <cell>0</cell>
 <cell>8</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>RCOSC_25_50MHZ</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>RCOSC_1MHZ</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>XTLOSC</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>SERDESIF Blocks</cell>
 <cell>0</cell>
 <cell>4</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>-- SERDESIF Lanes</cell>
 <cell>0</cell>
 <cell>16</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>FDDR</cell>
 <cell>0</cell>
 <cell>1</cell>
 <cell>0.00</cell>
</row>
<row>
 <cell>MSS</cell>
 <cell>1</cell>
 <cell>1</cell>
 <cell>100.00</cell>
</row>
</table>
<section><name>Detailed Logic Resource Usage</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>4LUT</cell>
 <cell>DFF</cell>
</header>
<row>
 <cell>Fabric Logic</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>RAM64x18 Interface Logic</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>RAM1K18 Interface Logic</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>MACC Interface Logic</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Total Used</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
</table>
<section><name>MSS Resource Usage</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Used</cell>
 <cell>Total</cell>
</header>
<row>
 <cell>Cortex-M3*</cell>
 <cell>1</cell>
 <cell>1</cell>
</row>
<row>
 <cell>eNVM (512KB)*</cell>
 <cell>1</cell>
 <cell>1</cell>
</row>
<row>
 <cell>eSRAM*</cell>
 <cell>2</cell>
 <cell>2</cell>
</row>
<row>
 <cell>TIMER*</cell>
 <cell>2</cell>
 <cell>2</cell>
</row>
<row>
 <cell>CAN</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>SPI</cell>
 <cell>1</cell>
 <cell>2</cell>
</row>
<row>
 <cell>I2C</cell>
 <cell>0</cell>
 <cell>2</cell>
</row>
<row>
 <cell>UART</cell>
 <cell>1</cell>
 <cell>2</cell>
</row>
<row>
 <cell>USB</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>MAC</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>MDDR</cell>
 <cell>1</cell>
 <cell>1</cell>
</row>
<row>
 <cell>HPDMA</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
<row>
 <cell>PDMA</cell>
 <cell>0</cell>
 <cell>1</cell>
</row>
</table>
<text>* These resources are always marked as used when you are using the MSS</text>
<text></text>
<section><name>I/O Function</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>w/o register</cell>
 <cell>w/ register</cell>
 <cell>w/ DDR register</cell>
</header>
<row>
 <cell>Input I/O</cell>
 <cell>319</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Output I/O</cell>
 <cell>224</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Bidirectional I/O</cell>
 <cell>20</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Differential Input I/O Pairs</cell>
 <cell>0</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Differential Output I/O Pairs</cell>
 <cell>1</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
<row>
 <cell>Differential Bidirectional I/O Pairs</cell>
 <cell>2</cell>
 <cell>0</cell>
 <cell>0</cell>
</row>
</table>
<section><name>I/O Technology</name></section>
<table>
<header>
 <cell>I/O Standard</cell>
 <cell>Vddi</cell>
 <cell>Vref</cell>
 <cell>Input</cell>
 <cell>Output</cell>
 <cell>Bidirectional</cell>
</header>
<row>
 <cell>LVCMOS25</cell>
 <cell> 2.50v</cell>
 <cell> N/A</cell>
 <cell> 318</cell>
 <cell> 197</cell>
 <cell> 2</cell>
</row>
<row>
 <cell>SSTL15I (Input/Bidirectional)</cell>
 <cell> 1.50v</cell>
 <cell> 0.75v</cell>
 <cell> 1</cell>
 <cell> 0</cell>
 <cell> 22</cell>
</row>
<row>
 <cell>SSTL15I (Output)</cell>
 <cell> 1.50v</cell>
 <cell> N/A</cell>
 <cell> 0</cell>
 <cell> 29</cell>
 <cell> 0</cell>
</row>
</table>
<section><name>I/O Placement</name></section>
<table>
<header>
 <cell>Type</cell>
 <cell>Count</cell>
 <cell>Percentage</cell>
</header>
<row>
 <cell>Locked</cell>
 <cell> 58</cell>
 <cell>10.19%</cell>
</row>
<row>
 <cell>Placed</cell>
 <cell> 0</cell>
 <cell>0.00%</cell>
</row>
<row>
 <cell>UnPlaced</cell>
 <cell> 511</cell>
 <cell>89.81%</cell>
</row>
</table>
<section><name>Nets assigned to chip global resources</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
</table>
<section><name>Nets assigned to row global resources</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
</table>
<section><name>High fanout nets</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>4</cell>
 <cell>INT_NET</cell>
 <cell>Net   : ff_to_start_net</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: flash_freeze_inst/INST_FLASH_FREEZE_IP</cell>
</row>
<row>
 <cell>1</cell>
 <cell>INT_NET</cell>
 <cell>Net   : FIC_0_AHB_S_HADDR_c[0]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: FIC_0_AHB_S_HADDR_ibuf[0]</cell>
</row>
<row>
 <cell>1</cell>
 <cell>INT_NET</cell>
 <cell>Net   : FIC_0_AHB_S_HADDR_c[1]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: FIC_0_AHB_S_HADDR_ibuf[1]</cell>
</row>
<row>
 <cell>1</cell>
 <cell>INT_NET</cell>
 <cell>Net   : FIC_0_AHB_S_HADDR_c[2]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: FIC_0_AHB_S_HADDR_ibuf[2]</cell>
</row>
<row>
 <cell>1</cell>
 <cell>INT_NET</cell>
 <cell>Net   : FIC_0_AHB_S_HADDR_c[3]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: FIC_0_AHB_S_HADDR_ibuf[3]</cell>
</row>
<row>
 <cell>1</cell>
 <cell>INT_NET</cell>
 <cell>Net   : FIC_0_AHB_S_HADDR_c[4]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: FIC_0_AHB_S_HADDR_ibuf[4]</cell>
</row>
<row>
 <cell>1</cell>
 <cell>INT_NET</cell>
 <cell>Net   : FIC_0_AHB_S_HADDR_c[5]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: FIC_0_AHB_S_HADDR_ibuf[5]</cell>
</row>
<row>
 <cell>1</cell>
 <cell>INT_NET</cell>
 <cell>Net   : FIC_0_AHB_S_HADDR_c[6]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: FIC_0_AHB_S_HADDR_ibuf[6]</cell>
</row>
<row>
 <cell>1</cell>
 <cell>INT_NET</cell>
 <cell>Net   : FIC_0_AHB_S_HADDR_c[7]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: FIC_0_AHB_S_HADDR_ibuf[7]</cell>
</row>
<row>
 <cell>1</cell>
 <cell>INT_NET</cell>
 <cell>Net   : FIC_0_AHB_S_HADDR_c[8]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: FIC_0_AHB_S_HADDR_ibuf[8]</cell>
</row>
</table>
<section><name>High fanout nets (through buffer trees)</name></section>
<table>
<header>
 <cell>Fanout</cell>
 <cell>Type</cell>
 <cell>Name</cell>
</header>
<row>
 <cell>4</cell>
 <cell>INT_NET</cell>
 <cell>Net   : ff_to_start_net</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: flash_freeze_inst/INST_FLASH_FREEZE_IP</cell>
</row>
<row>
 <cell>1</cell>
 <cell>INT_NET</cell>
 <cell>Net   : FIC_0_AHB_S_HADDR_c[0]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: FIC_0_AHB_S_HADDR_ibuf[0]</cell>
</row>
<row>
 <cell>1</cell>
 <cell>INT_NET</cell>
 <cell>Net   : FIC_0_AHB_S_HADDR_c[1]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: FIC_0_AHB_S_HADDR_ibuf[1]</cell>
</row>
<row>
 <cell>1</cell>
 <cell>INT_NET</cell>
 <cell>Net   : FIC_0_AHB_S_HADDR_c[2]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: FIC_0_AHB_S_HADDR_ibuf[2]</cell>
</row>
<row>
 <cell>1</cell>
 <cell>INT_NET</cell>
 <cell>Net   : FIC_0_AHB_S_HADDR_c[3]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: FIC_0_AHB_S_HADDR_ibuf[3]</cell>
</row>
<row>
 <cell>1</cell>
 <cell>INT_NET</cell>
 <cell>Net   : FIC_0_AHB_S_HADDR_c[4]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: FIC_0_AHB_S_HADDR_ibuf[4]</cell>
</row>
<row>
 <cell>1</cell>
 <cell>INT_NET</cell>
 <cell>Net   : FIC_0_AHB_S_HADDR_c[5]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: FIC_0_AHB_S_HADDR_ibuf[5]</cell>
</row>
<row>
 <cell>1</cell>
 <cell>INT_NET</cell>
 <cell>Net   : FIC_0_AHB_S_HADDR_c[6]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: FIC_0_AHB_S_HADDR_ibuf[6]</cell>
</row>
<row>
 <cell>1</cell>
 <cell>INT_NET</cell>
 <cell>Net   : FIC_0_AHB_S_HADDR_c[7]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: FIC_0_AHB_S_HADDR_ibuf[7]</cell>
</row>
<row>
 <cell>1</cell>
 <cell>INT_NET</cell>
 <cell>Net   : FIC_0_AHB_S_HADDR_c[8]</cell>
</row>
<row>
 <cell></cell>
 <cell></cell>
 <cell>Driver: FIC_0_AHB_S_HADDR_ibuf[8]</cell>
</row>
</table>
</doc>
