<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>COREAXI</name><vendor>Actel</vendor><library>DirectCore</library><version>3.0.112</version><fileSets><fileSet fileSetId="STIMULUS_FILESET"><file fileid="0"><name>rtl\vlog\test\user\axi_slave.v</name><fileType>verilogSource</fileType></file><file fileid="1"><name>rtl\vlog\test\user\axi_master.v</name><fileType>verilogSource</fileType></file><file fileid="2"><name>coreparameters.v</name><fileType>verilogSource</fileType><vendorExtensions><IncludeInRunDo/><isIncludeFile/></vendorExtensions></file></fileSet><fileSet fileSetId="HDL_FILESET"><file fileid="3"><name>rtl\vlog\core\axi_feedthrough.v</name><fileType>verilogSource</fileType></file><file fileid="4"><name>rtl\vlog\core\axi_interconnect_ntom.v</name><fileType>verilogSource</fileType></file><file fileid="5"><name>rtl\vlog\core\axi_master_stage.v</name><fileType>verilogSource</fileType></file><file fileid="6"><name>rtl\vlog\core\axi_matrix_m.v</name><fileType>verilogSource</fileType></file><file fileid="7"><name>rtl\vlog\core\axi_matrix_s.v</name><fileType>verilogSource</fileType></file><file fileid="8"><name>rtl\vlog\core\axi_ra_arbiter.v</name><fileType>verilogSource</fileType></file><file fileid="9"><name>rtl\vlog\core\axi_ra_channel.v</name><fileType>verilogSource</fileType></file><file fileid="10"><name>rtl\vlog\core\axi_rd_channel.v</name><fileType>verilogSource</fileType></file><file fileid="11"><name>rtl\vlog\core\axi_rdmatrix_4Mto1S.v</name><fileType>verilogSource</fileType></file><file fileid="12"><name>rtl\vlog\core\axi_rdmatrix_16Sto1M.v</name><fileType>verilogSource</fileType></file><file fileid="13"><name>rtl\vlog\core\axi_slave_stage.v</name><fileType>verilogSource</fileType></file><file fileid="14"><name>rtl\vlog\core\axi_wa_arbiter.v</name><fileType>verilogSource</fileType></file><file fileid="15"><name>rtl\vlog\core\axi_wa_channel.v</name><fileType>verilogSource</fileType></file><file fileid="16"><name>rtl\vlog\core\axi_wd_channel.v</name><fileType>verilogSource</fileType></file><file fileid="17"><name>rtl\vlog\core\axi_wresp_channel.v</name><fileType>verilogSource</fileType></file><file fileid="18"><name>rtl\vlog\core\axi_wrmatrix_4Mto1S.v</name><fileType>verilogSource</fileType></file><file fileid="19"><name>rtl\vlog\core\axi_rdmatrix_4Mto1S_hgs_high.v</name><fileType>verilogSource</fileType></file><file fileid="20"><name>rtl\vlog\core\axi_rdmatrix_4Mto1S_hgs_low.v</name><fileType>verilogSource</fileType></file><file fileid="21"><name>rtl\vlog\core\axi_wrmatrix_4Mto1S_hgs_high.v</name><fileType>verilogSource</fileType></file><file fileid="22"><name>rtl\vlog\core\axi_wrmatrix_4Mto1S_hgs_low.v</name><fileType>verilogSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>STIMULUS_FILESET</fileSetRef><name>SIMULATION</name></view><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel></Component>