<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>CoreConfigP</name><vendor>Actel</vendor><library>DirectCore</library><version>7.0.105</version><fileSets><fileSet fileSetId="HDL_FILESET"><file fileid="0"><name>rtl\vlog\core\coreconfigp.v</name><fileType>verilogSource</fileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>HDL_FILESET</fileSetRef><name>HDL</name></view></views></hwModel></Component>