//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Tue Mar 15 18:42:56 2016
// Version: v11.7 11.7.0.119
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

// CodeShadowing_Fabric
module CodeShadowing_Fabric(
    // Inputs
    DEVRST_N,
    DP_SW1,
    GPIO_11_F2M,
    GPIO_12_F2M,
    MDDR_DQS_TMATCH_0_IN,
    MMUART_0_RXD,
    SPI_0_DI,
    // Outputs
    GPIO_0_M2F,
    GPIO_10_M2F,
    GPIO_1_M2F,
    GPIO_2_M2F,
    GPIO_3_M2F,
    GPIO_4_M2F,
    GPIO_8_M2F,
    GPIO_9_M2F,
    MDDR_ADDR,
    MDDR_BA,
    MDDR_CAS_N,
    MDDR_CKE,
    MDDR_CLK,
    MDDR_CLK_N,
    MDDR_CS_N,
    MDDR_DQS_TMATCH_0_OUT,
    MDDR_ODT,
    MDDR_RAS_N,
    MDDR_RESET_N,
    MDDR_WE_N,
    MMUART_0_TXD,
    SPI_0_DO,
    // Inouts
    MDDR_DM_RDQS,
    MDDR_DQ,
    MDDR_DQS,
    MDDR_DQS_N,
    SPI_0_CLK,
    SPI_0_SS0
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input         DEVRST_N;
input         DP_SW1;
input         GPIO_11_F2M;
input         GPIO_12_F2M;
input         MDDR_DQS_TMATCH_0_IN;
input         MMUART_0_RXD;
input         SPI_0_DI;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output        GPIO_0_M2F;
output        GPIO_10_M2F;
output        GPIO_1_M2F;
output        GPIO_2_M2F;
output        GPIO_3_M2F;
output        GPIO_4_M2F;
output        GPIO_8_M2F;
output        GPIO_9_M2F;
output [15:0] MDDR_ADDR;
output [2:0]  MDDR_BA;
output        MDDR_CAS_N;
output        MDDR_CKE;
output        MDDR_CLK;
output        MDDR_CLK_N;
output        MDDR_CS_N;
output        MDDR_DQS_TMATCH_0_OUT;
output        MDDR_ODT;
output        MDDR_RAS_N;
output        MDDR_RESET_N;
output        MDDR_WE_N;
output        MMUART_0_TXD;
output        SPI_0_DO;
//--------------------------------------------------------------------
// Inout
//--------------------------------------------------------------------
inout  [1:0]  MDDR_DM_RDQS;
inout  [15:0] MDDR_DQ;
inout  [1:0]  MDDR_DQS;
inout  [1:0]  MDDR_DQS_N;
inout         SPI_0_CLK;
inout         SPI_0_SS0;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire          CodeShadowing_Fabric_MSS_0_FIC_2_APB_M_PCLK;
wire   [31:0] CoreAHBLite_0_AHBmslave4_HADDR;
wire   [2:0]  CoreAHBLite_0_AHBmslave4_HBURST;
wire          CoreAHBLite_0_AHBmslave4_HMASTLOCK;
wire   [3:0]  CoreAHBLite_0_AHBmslave4_HPROT;
wire   [31:0] CoreAHBLite_0_AHBmslave4_HRDATA;
wire          CoreAHBLite_0_AHBmslave4_HREADY;
wire          CoreAHBLite_0_AHBmslave4_HREADYOUT;
wire          CoreAHBLite_0_AHBmslave4_HSELx;
wire   [1:0]  CoreAHBLite_0_AHBmslave4_HTRANS;
wire   [31:0] CoreAHBLite_0_AHBmslave4_HWDATA;
wire          CoreAHBLite_0_AHBmslave4_HWRITE;
wire          CORECONFIGP_0_APB_S_PCLK;
wire          CORECONFIGP_0_APB_S_PRESET_N;
wire          CORECONFIGP_0_MDDR_APBmslave_PENABLE;
wire          CORECONFIGP_0_MDDR_APBmslave_PREADY;
wire          CORECONFIGP_0_MDDR_APBmslave_PSELx;
wire          CORECONFIGP_0_MDDR_APBmslave_PSLVERR;
wire          CORECONFIGP_0_MDDR_APBmslave_PWRITE;
wire          DEVRST_N;
wire          DP_SW1;
wire          FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC;
wire          FABOSC_0_RCOSC_25_50MHZ_O2F;
wire          FIC_0_CLK;
wire          FIC_2_APB_M_PRESET_N;
wire          GPIO_0_M2F_0;
wire          GPIO_1_M2F_0;
wire          GPIO_2_M2F_0;
wire          GPIO_3_M2F_1;
wire          GPIO_4_M2F_1;
wire          GPIO_8_M2F_1;
wire          GPIO_9_M2F_1;
wire          GPIO_10_M2F_1;
wire          GPIO_11_F2M;
wire          GPIO_12_F2M;
wire   [31:0] HW_Boot_Engine_0_AHB_IF_HADDR;
wire   [2:0]  HW_Boot_Engine_0_AHB_IF_HBURST;
wire   [3:0]  HW_Boot_Engine_0_AHB_IF_HPROT;
wire   [31:0] HW_Boot_Engine_0_AHB_IF_HRDATA;
wire          HW_Boot_Engine_0_AHB_IF_HREADY;
wire   [1:0]  HW_Boot_Engine_0_AHB_IF_HRESP;
wire   [2:0]  HW_Boot_Engine_0_AHB_IF_HSIZE;
wire   [1:0]  HW_Boot_Engine_0_AHB_IF_HTRANS;
wire   [31:0] HW_Boot_Engine_0_AHB_IF_HWDATA;
wire          HW_Boot_Engine_0_AHB_IF_HWRITE;
wire          HW_Boot_Engine_0_APB_IF_PENABLE;
wire          HW_Boot_Engine_0_APB_IF_PREADY;
wire          HW_Boot_Engine_0_APB_IF_PSELx;
wire          HW_Boot_Engine_0_APB_IF_PSLVERR;
wire          HW_Boot_Engine_0_APB_IF_PWRITE;
wire   [31:0] HW_Boot_Engine_0_AXI_IF_ARADDR;
wire   [1:0]  HW_Boot_Engine_0_AXI_IF_ARBURST;
wire   [3:0]  HW_Boot_Engine_0_AXI_IF_ARID;
wire   [3:0]  HW_Boot_Engine_0_AXI_IF_ARLEN;
wire   [1:0]  HW_Boot_Engine_0_AXI_IF_ARLOCK;
wire          HW_Boot_Engine_0_AXI_IF_ARREADY;
wire   [1:0]  HW_Boot_Engine_0_AXI_IF_ARSIZE;
wire          HW_Boot_Engine_0_AXI_IF_ARVALID;
wire   [31:0] HW_Boot_Engine_0_AXI_IF_AWADDR;
wire   [1:0]  HW_Boot_Engine_0_AXI_IF_AWBURST;
wire   [3:0]  HW_Boot_Engine_0_AXI_IF_AWID;
wire   [3:0]  HW_Boot_Engine_0_AXI_IF_AWLEN;
wire   [1:0]  HW_Boot_Engine_0_AXI_IF_AWLOCK;
wire          HW_Boot_Engine_0_AXI_IF_AWREADY;
wire          HW_Boot_Engine_0_AXI_IF_AWVALID;
wire   [3:0]  HW_Boot_Engine_0_AXI_IF_BID;
wire          HW_Boot_Engine_0_AXI_IF_BREADY;
wire   [1:0]  HW_Boot_Engine_0_AXI_IF_BRESP;
wire          HW_Boot_Engine_0_AXI_IF_BVALID;
wire   [63:0] HW_Boot_Engine_0_AXI_IF_RDATA;
wire   [3:0]  HW_Boot_Engine_0_AXI_IF_RID;
wire          HW_Boot_Engine_0_AXI_IF_RLAST;
wire          HW_Boot_Engine_0_AXI_IF_RREADY;
wire   [1:0]  HW_Boot_Engine_0_AXI_IF_RRESP;
wire          HW_Boot_Engine_0_AXI_IF_RVALID;
wire   [63:0] HW_Boot_Engine_0_AXI_IF_WDATA;
wire   [3:0]  HW_Boot_Engine_0_AXI_IF_WID;
wire          HW_Boot_Engine_0_AXI_IF_WLAST;
wire          HW_Boot_Engine_0_AXI_IF_WREADY;
wire   [7:0]  HW_Boot_Engine_0_AXI_IF_WSTRB;
wire          HW_Boot_Engine_0_AXI_IF_WVALID;
wire          M3_RESETn;
wire   [15:0] MDDR_ADDR_net_0;
wire   [2:0]  MDDR_BA_net_0;
wire          MDDR_CAS_N_net_0;
wire          MDDR_CKE_net_0;
wire          MDDR_CLK_net_0;
wire          MDDR_CLK_N_net_0;
wire          MDDR_CS_N_net_0;
wire   [1:0]  MDDR_DM_RDQS;
wire   [15:0] MDDR_DQ;
wire   [1:0]  MDDR_DQS;
wire   [1:0]  MDDR_DQS_N;
wire          MDDR_DQS_TMATCH_0_IN;
wire          MDDR_DQS_TMATCH_0_OUT_net_0;
wire          MDDR_ODT_net_0;
wire          MDDR_RAS_N_net_0;
wire          MDDR_RESET_N_net_0;
wire          MDDR_WE_N_net_0;
wire          MMUART_0_RXD;
wire          MMUART_0_TXD_net_0;
wire          MSS_DDR_FIC_SUBSYSTEM_LOCK;
wire          MSS_HPMS_READY;
wire          MSS_RESET_N_M2F;
wire          POWER_ON_RESET_N;
wire          SPI_0_CLK;
wire          SPI_0_DI;
wire          SPI_0_DO_net_0;
wire          SPI_0_SS0;
wire          SPI_0_DO_net_1;
wire          MMUART_0_TXD_net_1;
wire          MDDR_DQS_TMATCH_0_OUT_net_1;
wire          MDDR_CAS_N_net_1;
wire          MDDR_CLK_net_1;
wire          MDDR_CLK_N_net_1;
wire          MDDR_CKE_net_1;
wire          MDDR_CS_N_net_1;
wire          MDDR_ODT_net_1;
wire          MDDR_RAS_N_net_1;
wire          MDDR_RESET_N_net_1;
wire          MDDR_WE_N_net_1;
wire          GPIO_0_M2F_0_net_0;
wire          GPIO_1_M2F_0_net_0;
wire          GPIO_2_M2F_0_net_0;
wire          GPIO_3_M2F_1_net_0;
wire          GPIO_4_M2F_1_net_0;
wire          GPIO_8_M2F_1_net_0;
wire          GPIO_9_M2F_1_net_0;
wire          GPIO_10_M2F_1_net_0;
wire   [15:0] MDDR_ADDR_net_1;
wire   [2:0]  MDDR_BA_net_1;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire          VCC_net;
wire          GND_net;
wire   [7:2]  PADDR_const_net_0;
wire   [7:0]  PWDATA_const_net_0;
wire   [31:0] FDDR_PRDATA_const_net_0;
wire   [31:0] SDIF0_PRDATA_const_net_0;
wire   [31:0] SDIF1_PRDATA_const_net_0;
wire   [31:0] SDIF2_PRDATA_const_net_0;
wire   [31:0] SDIF3_PRDATA_const_net_0;
wire   [31:0] SDIF0_PRDATA_const_net_1;
wire   [31:0] SDIF1_PRDATA_const_net_1;
wire   [31:0] SDIF2_PRDATA_const_net_1;
wire   [31:0] SDIF3_PRDATA_const_net_1;
wire   [31:0] FIC_2_APB_M_PRDATA_const_net_0;
wire   [31:0] HADDR_M1_const_net_0;
wire   [1:0]  HTRANS_M1_const_net_0;
wire   [2:0]  HSIZE_M1_const_net_0;
wire   [2:0]  HBURST_M1_const_net_0;
wire   [3:0]  HPROT_M1_const_net_0;
wire   [31:0] HWDATA_M1_const_net_0;
wire   [31:0] HADDR_M2_const_net_0;
wire   [1:0]  HTRANS_M2_const_net_0;
wire   [2:0]  HSIZE_M2_const_net_0;
wire   [2:0]  HBURST_M2_const_net_0;
wire   [3:0]  HPROT_M2_const_net_0;
wire   [31:0] HWDATA_M2_const_net_0;
wire   [31:0] HADDR_M3_const_net_0;
wire   [1:0]  HTRANS_M3_const_net_0;
wire   [2:0]  HSIZE_M3_const_net_0;
wire   [2:0]  HBURST_M3_const_net_0;
wire   [3:0]  HPROT_M3_const_net_0;
wire   [31:0] HWDATA_M3_const_net_0;
wire   [31:0] HRDATA_S0_const_net_0;
wire   [1:0]  HRESP_S0_const_net_0;
wire   [31:0] HRDATA_S1_const_net_0;
wire   [1:0]  HRESP_S1_const_net_0;
wire   [31:0] HRDATA_S2_const_net_0;
wire   [1:0]  HRESP_S2_const_net_0;
wire   [31:0] HRDATA_S3_const_net_0;
wire   [1:0]  HRESP_S3_const_net_0;
wire   [31:0] HRDATA_S5_const_net_0;
wire   [1:0]  HRESP_S5_const_net_0;
wire   [31:0] HRDATA_S6_const_net_0;
wire   [1:0]  HRESP_S6_const_net_0;
wire   [31:0] HRDATA_S7_const_net_0;
wire   [1:0]  HRESP_S7_const_net_0;
wire   [31:0] HRDATA_S8_const_net_0;
wire   [1:0]  HRESP_S8_const_net_0;
wire   [31:0] HRDATA_S9_const_net_0;
wire   [1:0]  HRESP_S9_const_net_0;
wire   [31:0] HRDATA_S10_const_net_0;
wire   [1:0]  HRESP_S10_const_net_0;
wire   [31:0] HRDATA_S11_const_net_0;
wire   [1:0]  HRESP_S11_const_net_0;
wire   [31:0] HRDATA_S12_const_net_0;
wire   [1:0]  HRESP_S12_const_net_0;
wire   [31:0] HRDATA_S13_const_net_0;
wire   [1:0]  HRESP_S13_const_net_0;
wire   [31:0] HRDATA_S14_const_net_0;
wire   [1:0]  HRESP_S14_const_net_0;
wire   [31:0] HRDATA_S15_const_net_0;
wire   [1:0]  HRESP_S15_const_net_0;
wire   [31:0] HRDATA_S16_const_net_0;
wire   [1:0]  HRESP_S16_const_net_0;
//--------------------------------------------------------------------
// Bus Interface Nets Declarations - Unequal Pin Widths
//--------------------------------------------------------------------
wire          CoreAHBLite_0_AHBmslave4_HRESP;
wire   [1:1]  CoreAHBLite_0_AHBmslave4_HRESP_0_1to1;
wire   [0:0]  CoreAHBLite_0_AHBmslave4_HRESP_0_0to0;
wire   [1:0]  CoreAHBLite_0_AHBmslave4_HRESP_0;
wire   [2:0]  CoreAHBLite_0_AHBmslave4_HSIZE;
wire   [1:0]  CoreAHBLite_0_AHBmslave4_HSIZE_0_1to0;
wire   [1:0]  CoreAHBLite_0_AHBmslave4_HSIZE_0;
wire   [10:2] CORECONFIGP_0_MDDR_APBmslave_PADDR_0_10to2;
wire   [10:2] CORECONFIGP_0_MDDR_APBmslave_PADDR_0;
wire   [15:2] CORECONFIGP_0_MDDR_APBmslave_PADDR;
wire   [15:0] CORECONFIGP_0_MDDR_APBmslave_PRDATA;
wire   [31:16]CORECONFIGP_0_MDDR_APBmslave_PRDATA_0_31to16;
wire   [15:0] CORECONFIGP_0_MDDR_APBmslave_PRDATA_0_15to0;
wire   [31:0] CORECONFIGP_0_MDDR_APBmslave_PRDATA_0;
wire   [15:0] CORECONFIGP_0_MDDR_APBmslave_PWDATA_0_15to0;
wire   [15:0] CORECONFIGP_0_MDDR_APBmslave_PWDATA_0;
wire   [31:0] CORECONFIGP_0_MDDR_APBmslave_PWDATA;
wire   [16:16]HW_Boot_Engine_0_APB_IF_PADDR_0_16to16;
wire   [15:2] HW_Boot_Engine_0_APB_IF_PADDR_0_15to2;
wire   [16:2] HW_Boot_Engine_0_APB_IF_PADDR_0;
wire   [15:2] HW_Boot_Engine_0_APB_IF_PADDR;
wire   [31:0] HW_Boot_Engine_0_APB_IF_PRDATA;
wire   [15:0] HW_Boot_Engine_0_APB_IF_PRDATA_0_15to0;
wire   [15:0] HW_Boot_Engine_0_APB_IF_PRDATA_0;
wire   [31:16]HW_Boot_Engine_0_APB_IF_PWDATA_0_31to16;
wire   [15:0] HW_Boot_Engine_0_APB_IF_PWDATA_0_15to0;
wire   [31:0] HW_Boot_Engine_0_APB_IF_PWDATA_0;
wire   [15:0] HW_Boot_Engine_0_APB_IF_PWDATA;
wire   [2:0]  HW_Boot_Engine_0_AXI_IF_AWSIZE;
wire   [1:0]  HW_Boot_Engine_0_AXI_IF_AWSIZE_0_1to0;
wire   [1:0]  HW_Boot_Engine_0_AXI_IF_AWSIZE_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign VCC_net                        = 1'b1;
assign GND_net                        = 1'b0;
assign PADDR_const_net_0              = 6'h00;
assign PWDATA_const_net_0             = 8'h00;
assign FDDR_PRDATA_const_net_0        = 32'h00000000;
assign SDIF0_PRDATA_const_net_0       = 32'h00000000;
assign SDIF1_PRDATA_const_net_0       = 32'h00000000;
assign SDIF2_PRDATA_const_net_0       = 32'h00000000;
assign SDIF3_PRDATA_const_net_0       = 32'h00000000;
assign SDIF0_PRDATA_const_net_1       = 32'h00000000;
assign SDIF1_PRDATA_const_net_1       = 32'h00000000;
assign SDIF2_PRDATA_const_net_1       = 32'h00000000;
assign SDIF3_PRDATA_const_net_1       = 32'h00000000;
assign FIC_2_APB_M_PRDATA_const_net_0 = 32'h00000000;
assign HADDR_M1_const_net_0           = 32'h00000000;
assign HTRANS_M1_const_net_0          = 2'h0;
assign HSIZE_M1_const_net_0           = 3'h0;
assign HBURST_M1_const_net_0          = 3'h0;
assign HPROT_M1_const_net_0           = 4'h0;
assign HWDATA_M1_const_net_0          = 32'h00000000;
assign HADDR_M2_const_net_0           = 32'h00000000;
assign HTRANS_M2_const_net_0          = 2'h0;
assign HSIZE_M2_const_net_0           = 3'h0;
assign HBURST_M2_const_net_0          = 3'h0;
assign HPROT_M2_const_net_0           = 4'h0;
assign HWDATA_M2_const_net_0          = 32'h00000000;
assign HADDR_M3_const_net_0           = 32'h00000000;
assign HTRANS_M3_const_net_0          = 2'h0;
assign HSIZE_M3_const_net_0           = 3'h0;
assign HBURST_M3_const_net_0          = 3'h0;
assign HPROT_M3_const_net_0           = 4'h0;
assign HWDATA_M3_const_net_0          = 32'h00000000;
assign HRDATA_S0_const_net_0          = 32'h00000000;
assign HRESP_S0_const_net_0           = 2'h0;
assign HRDATA_S1_const_net_0          = 32'h00000000;
assign HRESP_S1_const_net_0           = 2'h0;
assign HRDATA_S2_const_net_0          = 32'h00000000;
assign HRESP_S2_const_net_0           = 2'h0;
assign HRDATA_S3_const_net_0          = 32'h00000000;
assign HRESP_S3_const_net_0           = 2'h0;
assign HRDATA_S5_const_net_0          = 32'h00000000;
assign HRESP_S5_const_net_0           = 2'h0;
assign HRDATA_S6_const_net_0          = 32'h00000000;
assign HRESP_S6_const_net_0           = 2'h0;
assign HRDATA_S7_const_net_0          = 32'h00000000;
assign HRESP_S7_const_net_0           = 2'h0;
assign HRDATA_S8_const_net_0          = 32'h00000000;
assign HRESP_S8_const_net_0           = 2'h0;
assign HRDATA_S9_const_net_0          = 32'h00000000;
assign HRESP_S9_const_net_0           = 2'h0;
assign HRDATA_S10_const_net_0         = 32'h00000000;
assign HRESP_S10_const_net_0          = 2'h0;
assign HRDATA_S11_const_net_0         = 32'h00000000;
assign HRESP_S11_const_net_0          = 2'h0;
assign HRDATA_S12_const_net_0         = 32'h00000000;
assign HRESP_S12_const_net_0          = 2'h0;
assign HRDATA_S13_const_net_0         = 32'h00000000;
assign HRESP_S13_const_net_0          = 2'h0;
assign HRDATA_S14_const_net_0         = 32'h00000000;
assign HRESP_S14_const_net_0          = 2'h0;
assign HRDATA_S15_const_net_0         = 32'h00000000;
assign HRESP_S15_const_net_0          = 2'h0;
assign HRDATA_S16_const_net_0         = 32'h00000000;
assign HRESP_S16_const_net_0          = 2'h0;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign SPI_0_DO_net_1              = SPI_0_DO_net_0;
assign SPI_0_DO                    = SPI_0_DO_net_1;
assign MMUART_0_TXD_net_1          = MMUART_0_TXD_net_0;
assign MMUART_0_TXD                = MMUART_0_TXD_net_1;
assign MDDR_DQS_TMATCH_0_OUT_net_1 = MDDR_DQS_TMATCH_0_OUT_net_0;
assign MDDR_DQS_TMATCH_0_OUT       = MDDR_DQS_TMATCH_0_OUT_net_1;
assign MDDR_CAS_N_net_1            = MDDR_CAS_N_net_0;
assign MDDR_CAS_N                  = MDDR_CAS_N_net_1;
assign MDDR_CLK_net_1              = MDDR_CLK_net_0;
assign MDDR_CLK                    = MDDR_CLK_net_1;
assign MDDR_CLK_N_net_1            = MDDR_CLK_N_net_0;
assign MDDR_CLK_N                  = MDDR_CLK_N_net_1;
assign MDDR_CKE_net_1              = MDDR_CKE_net_0;
assign MDDR_CKE                    = MDDR_CKE_net_1;
assign MDDR_CS_N_net_1             = MDDR_CS_N_net_0;
assign MDDR_CS_N                   = MDDR_CS_N_net_1;
assign MDDR_ODT_net_1              = MDDR_ODT_net_0;
assign MDDR_ODT                    = MDDR_ODT_net_1;
assign MDDR_RAS_N_net_1            = MDDR_RAS_N_net_0;
assign MDDR_RAS_N                  = MDDR_RAS_N_net_1;
assign MDDR_RESET_N_net_1          = MDDR_RESET_N_net_0;
assign MDDR_RESET_N                = MDDR_RESET_N_net_1;
assign MDDR_WE_N_net_1             = MDDR_WE_N_net_0;
assign MDDR_WE_N                   = MDDR_WE_N_net_1;
assign GPIO_0_M2F_0_net_0          = GPIO_0_M2F_0;
assign GPIO_0_M2F                  = GPIO_0_M2F_0_net_0;
assign GPIO_1_M2F_0_net_0          = GPIO_1_M2F_0;
assign GPIO_1_M2F                  = GPIO_1_M2F_0_net_0;
assign GPIO_2_M2F_0_net_0          = GPIO_2_M2F_0;
assign GPIO_2_M2F                  = GPIO_2_M2F_0_net_0;
assign GPIO_3_M2F_1_net_0          = GPIO_3_M2F_1;
assign GPIO_3_M2F                  = GPIO_3_M2F_1_net_0;
assign GPIO_4_M2F_1_net_0          = GPIO_4_M2F_1;
assign GPIO_4_M2F                  = GPIO_4_M2F_1_net_0;
assign GPIO_8_M2F_1_net_0          = GPIO_8_M2F_1;
assign GPIO_8_M2F                  = GPIO_8_M2F_1_net_0;
assign GPIO_9_M2F_1_net_0          = GPIO_9_M2F_1;
assign GPIO_9_M2F                  = GPIO_9_M2F_1_net_0;
assign GPIO_10_M2F_1_net_0         = GPIO_10_M2F_1;
assign GPIO_10_M2F                 = GPIO_10_M2F_1_net_0;
assign MDDR_ADDR_net_1             = MDDR_ADDR_net_0;
assign MDDR_ADDR[15:0]             = MDDR_ADDR_net_1;
assign MDDR_BA_net_1               = MDDR_BA_net_0;
assign MDDR_BA[2:0]                = MDDR_BA_net_1;
//--------------------------------------------------------------------
// Bus Interface Nets Assignments - Unequal Pin Widths
//--------------------------------------------------------------------
assign CoreAHBLite_0_AHBmslave4_HRESP_0_1to1 = 1'b0;
assign CoreAHBLite_0_AHBmslave4_HRESP_0_0to0 = CoreAHBLite_0_AHBmslave4_HRESP;
assign CoreAHBLite_0_AHBmslave4_HRESP_0 = { CoreAHBLite_0_AHBmslave4_HRESP_0_1to1, CoreAHBLite_0_AHBmslave4_HRESP_0_0to0 };

assign CoreAHBLite_0_AHBmslave4_HSIZE_0_1to0 = CoreAHBLite_0_AHBmslave4_HSIZE[1:0];
assign CoreAHBLite_0_AHBmslave4_HSIZE_0 = { CoreAHBLite_0_AHBmslave4_HSIZE_0_1to0 };

assign CORECONFIGP_0_MDDR_APBmslave_PADDR_0_10to2 = CORECONFIGP_0_MDDR_APBmslave_PADDR[10:2];
assign CORECONFIGP_0_MDDR_APBmslave_PADDR_0 = { CORECONFIGP_0_MDDR_APBmslave_PADDR_0_10to2 };

assign CORECONFIGP_0_MDDR_APBmslave_PRDATA_0_31to16 = 16'h0;
assign CORECONFIGP_0_MDDR_APBmslave_PRDATA_0_15to0 = CORECONFIGP_0_MDDR_APBmslave_PRDATA[15:0];
assign CORECONFIGP_0_MDDR_APBmslave_PRDATA_0 = { CORECONFIGP_0_MDDR_APBmslave_PRDATA_0_31to16, CORECONFIGP_0_MDDR_APBmslave_PRDATA_0_15to0 };

assign CORECONFIGP_0_MDDR_APBmslave_PWDATA_0_15to0 = CORECONFIGP_0_MDDR_APBmslave_PWDATA[15:0];
assign CORECONFIGP_0_MDDR_APBmslave_PWDATA_0 = { CORECONFIGP_0_MDDR_APBmslave_PWDATA_0_15to0 };

assign HW_Boot_Engine_0_APB_IF_PADDR_0_16to16 = 1'b0;
assign HW_Boot_Engine_0_APB_IF_PADDR_0_15to2 = HW_Boot_Engine_0_APB_IF_PADDR[15:2];
assign HW_Boot_Engine_0_APB_IF_PADDR_0 = { HW_Boot_Engine_0_APB_IF_PADDR_0_16to16, HW_Boot_Engine_0_APB_IF_PADDR_0_15to2 };

assign HW_Boot_Engine_0_APB_IF_PRDATA_0_15to0 = HW_Boot_Engine_0_APB_IF_PRDATA[15:0];
assign HW_Boot_Engine_0_APB_IF_PRDATA_0 = { HW_Boot_Engine_0_APB_IF_PRDATA_0_15to0 };

assign HW_Boot_Engine_0_APB_IF_PWDATA_0_31to16 = 16'h0;
assign HW_Boot_Engine_0_APB_IF_PWDATA_0_15to0 = HW_Boot_Engine_0_APB_IF_PWDATA[15:0];
assign HW_Boot_Engine_0_APB_IF_PWDATA_0 = { HW_Boot_Engine_0_APB_IF_PWDATA_0_31to16, HW_Boot_Engine_0_APB_IF_PWDATA_0_15to0 };

assign HW_Boot_Engine_0_AXI_IF_AWSIZE_0_1to0 = HW_Boot_Engine_0_AXI_IF_AWSIZE[1:0];
assign HW_Boot_Engine_0_AXI_IF_AWSIZE_0 = { HW_Boot_Engine_0_AXI_IF_AWSIZE_0_1to0 };

//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------CodeShadowing_Fabric_CCC_0_FCCC   -   Actel:SgCore:FCCC:2.0.200
CodeShadowing_Fabric_CCC_0_FCCC CCC_0(
        // Inputs
        .RCOSC_25_50MHZ ( FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC ),
        // Outputs
        .GL0            ( FIC_0_CLK ),
        .LOCK           ( MSS_DDR_FIC_SUBSYSTEM_LOCK ) 
        );

//--------CodeShadowing_Fabric_MSS
CodeShadowing_Fabric_MSS CodeShadowing_Fabric_MSS_0(
        // Inputs
        .SPI_0_DI               ( SPI_0_DI ),
        .MCCC_CLK_BASE          ( FIC_0_CLK ),
        .MMUART_0_RXD           ( MMUART_0_RXD ),
        .MCCC_CLK_BASE_PLL_LOCK ( MSS_DDR_FIC_SUBSYSTEM_LOCK ),
        .GPIO_11_F2M            ( GPIO_11_F2M ),
        .GPIO_12_F2M            ( GPIO_12_F2M ),
        .M3_RESET_N             ( M3_RESETn ),
        .MDDR_APB_S_PRESET_N    ( CORECONFIGP_0_APB_S_PRESET_N ),
        .MDDR_APB_S_PCLK        ( CORECONFIGP_0_APB_S_PCLK ),
        .FIC_2_APB_M_PREADY     ( VCC_net ), // tied to 1'b1 from definition
        .FIC_2_APB_M_PSLVERR    ( GND_net ), // tied to 1'b0 from definition
        .MDDR_APB_S_PWRITE      ( CORECONFIGP_0_MDDR_APBmslave_PWRITE ),
        .MDDR_APB_S_PENABLE     ( CORECONFIGP_0_MDDR_APBmslave_PENABLE ),
        .MDDR_APB_S_PSEL        ( CORECONFIGP_0_MDDR_APBmslave_PSELx ),
        .FIC_0_AHB_S_HREADY     ( CoreAHBLite_0_AHBmslave4_HREADY ),
        .FIC_0_AHB_S_HWRITE     ( CoreAHBLite_0_AHBmslave4_HWRITE ),
        .FIC_0_AHB_S_HMASTLOCK  ( CoreAHBLite_0_AHBmslave4_HMASTLOCK ),
        .FIC_0_AHB_S_HSEL       ( CoreAHBLite_0_AHBmslave4_HSELx ),
        .MDDR_DQS_TMATCH_0_IN   ( MDDR_DQS_TMATCH_0_IN ),
        .MDDR_DDR_CORE_RESET_N  ( VCC_net ),
        .MDDR_DDR_AXI_S_RMW     ( GND_net ),
        .MDDR_DDR_AXI_S_AWVALID ( HW_Boot_Engine_0_AXI_IF_AWVALID ),
        .MDDR_DDR_AXI_S_WLAST   ( HW_Boot_Engine_0_AXI_IF_WLAST ),
        .MDDR_DDR_AXI_S_WVALID  ( HW_Boot_Engine_0_AXI_IF_WVALID ),
        .MDDR_DDR_AXI_S_BREADY  ( HW_Boot_Engine_0_AXI_IF_BREADY ),
        .MDDR_DDR_AXI_S_ARVALID ( HW_Boot_Engine_0_AXI_IF_ARVALID ),
        .MDDR_DDR_AXI_S_RREADY  ( HW_Boot_Engine_0_AXI_IF_RREADY ),
        .FIC_2_APB_M_PRDATA     ( FIC_2_APB_M_PRDATA_const_net_0 ), // tied to 32'h00000000 from definition
        .MDDR_APB_S_PWDATA      ( CORECONFIGP_0_MDDR_APBmslave_PWDATA_0 ),
        .MDDR_APB_S_PADDR       ( CORECONFIGP_0_MDDR_APBmslave_PADDR_0 ),
        .FIC_0_AHB_S_HADDR      ( CoreAHBLite_0_AHBmslave4_HADDR ),
        .FIC_0_AHB_S_HWDATA     ( CoreAHBLite_0_AHBmslave4_HWDATA ),
        .FIC_0_AHB_S_HSIZE      ( CoreAHBLite_0_AHBmslave4_HSIZE_0 ),
        .FIC_0_AHB_S_HTRANS     ( CoreAHBLite_0_AHBmslave4_HTRANS ),
        .MDDR_DDR_AXI_S_AWID    ( HW_Boot_Engine_0_AXI_IF_AWID ),
        .MDDR_DDR_AXI_S_AWADDR  ( HW_Boot_Engine_0_AXI_IF_AWADDR ),
        .MDDR_DDR_AXI_S_AWLEN   ( HW_Boot_Engine_0_AXI_IF_AWLEN ),
        .MDDR_DDR_AXI_S_AWSIZE  ( HW_Boot_Engine_0_AXI_IF_AWSIZE_0 ),
        .MDDR_DDR_AXI_S_AWBURST ( HW_Boot_Engine_0_AXI_IF_AWBURST ),
        .MDDR_DDR_AXI_S_AWLOCK  ( HW_Boot_Engine_0_AXI_IF_AWLOCK ),
        .MDDR_DDR_AXI_S_WID     ( HW_Boot_Engine_0_AXI_IF_WID ),
        .MDDR_DDR_AXI_S_WDATA   ( HW_Boot_Engine_0_AXI_IF_WDATA ),
        .MDDR_DDR_AXI_S_WSTRB   ( HW_Boot_Engine_0_AXI_IF_WSTRB ),
        .MDDR_DDR_AXI_S_ARID    ( HW_Boot_Engine_0_AXI_IF_ARID ),
        .MDDR_DDR_AXI_S_ARADDR  ( HW_Boot_Engine_0_AXI_IF_ARADDR ),
        .MDDR_DDR_AXI_S_ARLEN   ( HW_Boot_Engine_0_AXI_IF_ARLEN ),
        .MDDR_DDR_AXI_S_ARSIZE  ( HW_Boot_Engine_0_AXI_IF_ARSIZE ),
        .MDDR_DDR_AXI_S_ARBURST ( HW_Boot_Engine_0_AXI_IF_ARBURST ),
        .MDDR_DDR_AXI_S_ARLOCK  ( HW_Boot_Engine_0_AXI_IF_ARLOCK ),
        // Outputs
        .SPI_0_DO               ( SPI_0_DO_net_0 ),
        .MMUART_0_TXD           ( MMUART_0_TXD_net_0 ),
        .MSS_RESET_N_M2F        ( MSS_RESET_N_M2F ),
        .FIC_2_APB_M_PRESET_N   ( FIC_2_APB_M_PRESET_N ),
        .FIC_2_APB_M_PCLK       ( CodeShadowing_Fabric_MSS_0_FIC_2_APB_M_PCLK ),
        .FIC_2_APB_M_PWRITE     (  ),
        .FIC_2_APB_M_PENABLE    (  ),
        .FIC_2_APB_M_PSEL       (  ),
        .MDDR_APB_S_PREADY      ( CORECONFIGP_0_MDDR_APBmslave_PREADY ),
        .MDDR_APB_S_PSLVERR     ( CORECONFIGP_0_MDDR_APBmslave_PSLVERR ),
        .FIC_0_AHB_S_HRESP      ( CoreAHBLite_0_AHBmslave4_HRESP ),
        .FIC_0_AHB_S_HREADYOUT  ( CoreAHBLite_0_AHBmslave4_HREADYOUT ),
        .GPIO_0_M2F             ( GPIO_0_M2F_0 ),
        .GPIO_1_M2F             ( GPIO_1_M2F_0 ),
        .GPIO_2_M2F             ( GPIO_2_M2F_0 ),
        .GPIO_3_M2F             ( GPIO_3_M2F_1 ),
        .GPIO_4_M2F             ( GPIO_4_M2F_1 ),
        .GPIO_8_M2F             ( GPIO_8_M2F_1 ),
        .GPIO_9_M2F             ( GPIO_9_M2F_1 ),
        .GPIO_10_M2F            ( GPIO_10_M2F_1 ),
        .MDDR_DQS_TMATCH_0_OUT  ( MDDR_DQS_TMATCH_0_OUT_net_0 ),
        .MDDR_CAS_N             ( MDDR_CAS_N_net_0 ),
        .MDDR_CLK               ( MDDR_CLK_net_0 ),
        .MDDR_CLK_N             ( MDDR_CLK_N_net_0 ),
        .MDDR_CKE               ( MDDR_CKE_net_0 ),
        .MDDR_CS_N              ( MDDR_CS_N_net_0 ),
        .MDDR_ODT               ( MDDR_ODT_net_0 ),
        .MDDR_RAS_N             ( MDDR_RAS_N_net_0 ),
        .MDDR_RESET_N           ( MDDR_RESET_N_net_0 ),
        .MDDR_WE_N              ( MDDR_WE_N_net_0 ),
        .MDDR_DDR_AXI_S_AWREADY ( HW_Boot_Engine_0_AXI_IF_AWREADY ),
        .MDDR_DDR_AXI_S_WREADY  ( HW_Boot_Engine_0_AXI_IF_WREADY ),
        .MDDR_DDR_AXI_S_BVALID  ( HW_Boot_Engine_0_AXI_IF_BVALID ),
        .MDDR_DDR_AXI_S_ARREADY ( HW_Boot_Engine_0_AXI_IF_ARREADY ),
        .MDDR_DDR_AXI_S_RLAST   ( HW_Boot_Engine_0_AXI_IF_RLAST ),
        .MDDR_DDR_AXI_S_RVALID  ( HW_Boot_Engine_0_AXI_IF_RVALID ),
        .FIC_2_APB_M_PADDR      (  ),
        .FIC_2_APB_M_PWDATA     (  ),
        .MDDR_APB_S_PRDATA      ( CORECONFIGP_0_MDDR_APBmslave_PRDATA ),
        .FIC_0_AHB_S_HRDATA     ( CoreAHBLite_0_AHBmslave4_HRDATA ),
        .MDDR_ADDR              ( MDDR_ADDR_net_0 ),
        .MDDR_BA                ( MDDR_BA_net_0 ),
        .MDDR_DDR_AXI_S_BID     ( HW_Boot_Engine_0_AXI_IF_BID ),
        .MDDR_DDR_AXI_S_BRESP   ( HW_Boot_Engine_0_AXI_IF_BRESP ),
        .MDDR_DDR_AXI_S_RID     ( HW_Boot_Engine_0_AXI_IF_RID ),
        .MDDR_DDR_AXI_S_RRESP   ( HW_Boot_Engine_0_AXI_IF_RRESP ),
        .MDDR_DDR_AXI_S_RDATA   ( HW_Boot_Engine_0_AXI_IF_RDATA ),
        // Inouts
        .SPI_0_CLK              ( SPI_0_CLK ),
        .SPI_0_SS0              ( SPI_0_SS0 ),
        .MDDR_DM_RDQS           ( MDDR_DM_RDQS ),
        .MDDR_DQ                ( MDDR_DQ ),
        .MDDR_DQS               ( MDDR_DQS ),
        .MDDR_DQS_N             ( MDDR_DQS_N ) 
        );

//--------CoreAHBLite   -   Actel:DirectCore:CoreAHBLite:5.2.100
CoreAHBLite #( 
        .FAMILY             ( 19 ),
        .HADDR_SHG_CFG      ( 1 ),
        .M0_AHBSLOT0ENABLE  ( 0 ),
        .M0_AHBSLOT1ENABLE  ( 0 ),
        .M0_AHBSLOT2ENABLE  ( 0 ),
        .M0_AHBSLOT3ENABLE  ( 0 ),
        .M0_AHBSLOT4ENABLE  ( 1 ),
        .M0_AHBSLOT5ENABLE  ( 0 ),
        .M0_AHBSLOT6ENABLE  ( 0 ),
        .M0_AHBSLOT7ENABLE  ( 0 ),
        .M0_AHBSLOT8ENABLE  ( 0 ),
        .M0_AHBSLOT9ENABLE  ( 0 ),
        .M0_AHBSLOT10ENABLE ( 0 ),
        .M0_AHBSLOT11ENABLE ( 0 ),
        .M0_AHBSLOT12ENABLE ( 0 ),
        .M0_AHBSLOT13ENABLE ( 0 ),
        .M0_AHBSLOT14ENABLE ( 0 ),
        .M0_AHBSLOT15ENABLE ( 0 ),
        .M0_AHBSLOT16ENABLE ( 0 ),
        .M1_AHBSLOT0ENABLE  ( 0 ),
        .M1_AHBSLOT1ENABLE  ( 0 ),
        .M1_AHBSLOT2ENABLE  ( 0 ),
        .M1_AHBSLOT3ENABLE  ( 0 ),
        .M1_AHBSLOT4ENABLE  ( 0 ),
        .M1_AHBSLOT5ENABLE  ( 0 ),
        .M1_AHBSLOT6ENABLE  ( 0 ),
        .M1_AHBSLOT7ENABLE  ( 0 ),
        .M1_AHBSLOT8ENABLE  ( 0 ),
        .M1_AHBSLOT9ENABLE  ( 0 ),
        .M1_AHBSLOT10ENABLE ( 0 ),
        .M1_AHBSLOT11ENABLE ( 0 ),
        .M1_AHBSLOT12ENABLE ( 0 ),
        .M1_AHBSLOT13ENABLE ( 0 ),
        .M1_AHBSLOT14ENABLE ( 0 ),
        .M1_AHBSLOT15ENABLE ( 0 ),
        .M1_AHBSLOT16ENABLE ( 0 ),
        .M2_AHBSLOT0ENABLE  ( 0 ),
        .M2_AHBSLOT1ENABLE  ( 0 ),
        .M2_AHBSLOT2ENABLE  ( 0 ),
        .M2_AHBSLOT3ENABLE  ( 0 ),
        .M2_AHBSLOT4ENABLE  ( 0 ),
        .M2_AHBSLOT5ENABLE  ( 0 ),
        .M2_AHBSLOT6ENABLE  ( 0 ),
        .M2_AHBSLOT7ENABLE  ( 0 ),
        .M2_AHBSLOT8ENABLE  ( 0 ),
        .M2_AHBSLOT9ENABLE  ( 0 ),
        .M2_AHBSLOT10ENABLE ( 0 ),
        .M2_AHBSLOT11ENABLE ( 0 ),
        .M2_AHBSLOT12ENABLE ( 0 ),
        .M2_AHBSLOT13ENABLE ( 0 ),
        .M2_AHBSLOT14ENABLE ( 0 ),
        .M2_AHBSLOT15ENABLE ( 0 ),
        .M2_AHBSLOT16ENABLE ( 0 ),
        .M3_AHBSLOT0ENABLE  ( 0 ),
        .M3_AHBSLOT1ENABLE  ( 0 ),
        .M3_AHBSLOT2ENABLE  ( 0 ),
        .M3_AHBSLOT3ENABLE  ( 0 ),
        .M3_AHBSLOT4ENABLE  ( 0 ),
        .M3_AHBSLOT5ENABLE  ( 0 ),
        .M3_AHBSLOT6ENABLE  ( 0 ),
        .M3_AHBSLOT7ENABLE  ( 0 ),
        .M3_AHBSLOT8ENABLE  ( 0 ),
        .M3_AHBSLOT9ENABLE  ( 0 ),
        .M3_AHBSLOT10ENABLE ( 0 ),
        .M3_AHBSLOT11ENABLE ( 0 ),
        .M3_AHBSLOT12ENABLE ( 0 ),
        .M3_AHBSLOT13ENABLE ( 0 ),
        .M3_AHBSLOT14ENABLE ( 0 ),
        .M3_AHBSLOT15ENABLE ( 0 ),
        .M3_AHBSLOT16ENABLE ( 0 ),
        .MEMSPACE           ( 1 ),
        .SC_0               ( 0 ),
        .SC_1               ( 0 ),
        .SC_2               ( 0 ),
        .SC_3               ( 0 ),
        .SC_4               ( 0 ),
        .SC_5               ( 0 ),
        .SC_6               ( 0 ),
        .SC_7               ( 0 ),
        .SC_8               ( 0 ),
        .SC_9               ( 0 ),
        .SC_10              ( 0 ),
        .SC_11              ( 0 ),
        .SC_12              ( 0 ),
        .SC_13              ( 0 ),
        .SC_14              ( 0 ),
        .SC_15              ( 0 ) )
CoreAHBLite_0(
        // Inputs
        .HCLK          ( FIC_0_CLK ),
        .HRESETN       ( MSS_HPMS_READY ),
        .REMAP_M0      ( GND_net ),
        .HMASTLOCK_M0  ( GND_net ), // tied to 1'b0 from definition
        .HWRITE_M0     ( HW_Boot_Engine_0_AHB_IF_HWRITE ),
        .HMASTLOCK_M1  ( GND_net ), // tied to 1'b0 from definition
        .HWRITE_M1     ( GND_net ), // tied to 1'b0 from definition
        .HMASTLOCK_M2  ( GND_net ), // tied to 1'b0 from definition
        .HWRITE_M2     ( GND_net ), // tied to 1'b0 from definition
        .HMASTLOCK_M3  ( GND_net ), // tied to 1'b0 from definition
        .HWRITE_M3     ( GND_net ), // tied to 1'b0 from definition
        .HREADYOUT_S0  ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S1  ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S2  ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S3  ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S4  ( CoreAHBLite_0_AHBmslave4_HREADYOUT ),
        .HREADYOUT_S5  ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S6  ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S7  ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S8  ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S9  ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S10 ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S11 ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S12 ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S13 ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S14 ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S15 ( VCC_net ), // tied to 1'b1 from definition
        .HREADYOUT_S16 ( VCC_net ), // tied to 1'b1 from definition
        .HADDR_M0      ( HW_Boot_Engine_0_AHB_IF_HADDR ),
        .HSIZE_M0      ( HW_Boot_Engine_0_AHB_IF_HSIZE ),
        .HTRANS_M0     ( HW_Boot_Engine_0_AHB_IF_HTRANS ),
        .HWDATA_M0     ( HW_Boot_Engine_0_AHB_IF_HWDATA ),
        .HBURST_M0     ( HW_Boot_Engine_0_AHB_IF_HBURST ),
        .HPROT_M0      ( HW_Boot_Engine_0_AHB_IF_HPROT ),
        .HADDR_M1      ( HADDR_M1_const_net_0 ), // tied to 32'h00000000 from definition
        .HSIZE_M1      ( HSIZE_M1_const_net_0 ), // tied to 3'h0 from definition
        .HTRANS_M1     ( HTRANS_M1_const_net_0 ), // tied to 2'h0 from definition
        .HWDATA_M1     ( HWDATA_M1_const_net_0 ), // tied to 32'h00000000 from definition
        .HBURST_M1     ( HBURST_M1_const_net_0 ), // tied to 3'h0 from definition
        .HPROT_M1      ( HPROT_M1_const_net_0 ), // tied to 4'h0 from definition
        .HADDR_M2      ( HADDR_M2_const_net_0 ), // tied to 32'h00000000 from definition
        .HSIZE_M2      ( HSIZE_M2_const_net_0 ), // tied to 3'h0 from definition
        .HTRANS_M2     ( HTRANS_M2_const_net_0 ), // tied to 2'h0 from definition
        .HWDATA_M2     ( HWDATA_M2_const_net_0 ), // tied to 32'h00000000 from definition
        .HBURST_M2     ( HBURST_M2_const_net_0 ), // tied to 3'h0 from definition
        .HPROT_M2      ( HPROT_M2_const_net_0 ), // tied to 4'h0 from definition
        .HADDR_M3      ( HADDR_M3_const_net_0 ), // tied to 32'h00000000 from definition
        .HSIZE_M3      ( HSIZE_M3_const_net_0 ), // tied to 3'h0 from definition
        .HTRANS_M3     ( HTRANS_M3_const_net_0 ), // tied to 2'h0 from definition
        .HWDATA_M3     ( HWDATA_M3_const_net_0 ), // tied to 32'h00000000 from definition
        .HBURST_M3     ( HBURST_M3_const_net_0 ), // tied to 3'h0 from definition
        .HPROT_M3      ( HPROT_M3_const_net_0 ), // tied to 4'h0 from definition
        .HRDATA_S0     ( HRDATA_S0_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S0      ( HRESP_S0_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S1     ( HRDATA_S1_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S1      ( HRESP_S1_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S2     ( HRDATA_S2_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S2      ( HRESP_S2_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S3     ( HRDATA_S3_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S3      ( HRESP_S3_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S4     ( CoreAHBLite_0_AHBmslave4_HRDATA ),
        .HRESP_S4      ( CoreAHBLite_0_AHBmslave4_HRESP_0 ),
        .HRDATA_S5     ( HRDATA_S5_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S5      ( HRESP_S5_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S6     ( HRDATA_S6_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S6      ( HRESP_S6_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S7     ( HRDATA_S7_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S7      ( HRESP_S7_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S8     ( HRDATA_S8_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S8      ( HRESP_S8_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S9     ( HRDATA_S9_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S9      ( HRESP_S9_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S10    ( HRDATA_S10_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S10     ( HRESP_S10_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S11    ( HRDATA_S11_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S11     ( HRESP_S11_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S12    ( HRDATA_S12_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S12     ( HRESP_S12_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S13    ( HRDATA_S13_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S13     ( HRESP_S13_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S14    ( HRDATA_S14_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S14     ( HRESP_S14_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S15    ( HRDATA_S15_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S15     ( HRESP_S15_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S16    ( HRDATA_S16_const_net_0 ), // tied to 32'h00000000 from definition
        .HRESP_S16     ( HRESP_S16_const_net_0 ), // tied to 2'h0 from definition
        // Outputs
        .HREADY_M0     ( HW_Boot_Engine_0_AHB_IF_HREADY ),
        .HREADY_M1     (  ),
        .HREADY_M2     (  ),
        .HREADY_M3     (  ),
        .HSEL_S0       (  ),
        .HWRITE_S0     (  ),
        .HREADY_S0     (  ),
        .HMASTLOCK_S0  (  ),
        .HSEL_S1       (  ),
        .HWRITE_S1     (  ),
        .HREADY_S1     (  ),
        .HMASTLOCK_S1  (  ),
        .HSEL_S2       (  ),
        .HWRITE_S2     (  ),
        .HREADY_S2     (  ),
        .HMASTLOCK_S2  (  ),
        .HSEL_S3       (  ),
        .HWRITE_S3     (  ),
        .HREADY_S3     (  ),
        .HMASTLOCK_S3  (  ),
        .HSEL_S4       ( CoreAHBLite_0_AHBmslave4_HSELx ),
        .HWRITE_S4     ( CoreAHBLite_0_AHBmslave4_HWRITE ),
        .HREADY_S4     ( CoreAHBLite_0_AHBmslave4_HREADY ),
        .HMASTLOCK_S4  ( CoreAHBLite_0_AHBmslave4_HMASTLOCK ),
        .HSEL_S5       (  ),
        .HWRITE_S5     (  ),
        .HREADY_S5     (  ),
        .HMASTLOCK_S5  (  ),
        .HSEL_S6       (  ),
        .HWRITE_S6     (  ),
        .HREADY_S6     (  ),
        .HMASTLOCK_S6  (  ),
        .HSEL_S7       (  ),
        .HWRITE_S7     (  ),
        .HREADY_S7     (  ),
        .HMASTLOCK_S7  (  ),
        .HSEL_S8       (  ),
        .HWRITE_S8     (  ),
        .HREADY_S8     (  ),
        .HMASTLOCK_S8  (  ),
        .HSEL_S9       (  ),
        .HWRITE_S9     (  ),
        .HREADY_S9     (  ),
        .HMASTLOCK_S9  (  ),
        .HSEL_S10      (  ),
        .HWRITE_S10    (  ),
        .HREADY_S10    (  ),
        .HMASTLOCK_S10 (  ),
        .HSEL_S11      (  ),
        .HWRITE_S11    (  ),
        .HREADY_S11    (  ),
        .HMASTLOCK_S11 (  ),
        .HSEL_S12      (  ),
        .HWRITE_S12    (  ),
        .HREADY_S12    (  ),
        .HMASTLOCK_S12 (  ),
        .HSEL_S13      (  ),
        .HWRITE_S13    (  ),
        .HREADY_S13    (  ),
        .HMASTLOCK_S13 (  ),
        .HSEL_S14      (  ),
        .HWRITE_S14    (  ),
        .HREADY_S14    (  ),
        .HMASTLOCK_S14 (  ),
        .HSEL_S15      (  ),
        .HWRITE_S15    (  ),
        .HREADY_S15    (  ),
        .HMASTLOCK_S15 (  ),
        .HSEL_S16      (  ),
        .HWRITE_S16    (  ),
        .HREADY_S16    (  ),
        .HMASTLOCK_S16 (  ),
        .HRESP_M0      ( HW_Boot_Engine_0_AHB_IF_HRESP ),
        .HRDATA_M0     ( HW_Boot_Engine_0_AHB_IF_HRDATA ),
        .HRESP_M1      (  ),
        .HRDATA_M1     (  ),
        .HRESP_M2      (  ),
        .HRDATA_M2     (  ),
        .HRESP_M3      (  ),
        .HRDATA_M3     (  ),
        .HADDR_S0      (  ),
        .HSIZE_S0      (  ),
        .HTRANS_S0     (  ),
        .HWDATA_S0     (  ),
        .HBURST_S0     (  ),
        .HPROT_S0      (  ),
        .HADDR_S1      (  ),
        .HSIZE_S1      (  ),
        .HTRANS_S1     (  ),
        .HWDATA_S1     (  ),
        .HBURST_S1     (  ),
        .HPROT_S1      (  ),
        .HADDR_S2      (  ),
        .HSIZE_S2      (  ),
        .HTRANS_S2     (  ),
        .HWDATA_S2     (  ),
        .HBURST_S2     (  ),
        .HPROT_S2      (  ),
        .HADDR_S3      (  ),
        .HSIZE_S3      (  ),
        .HTRANS_S3     (  ),
        .HWDATA_S3     (  ),
        .HBURST_S3     (  ),
        .HPROT_S3      (  ),
        .HADDR_S4      ( CoreAHBLite_0_AHBmslave4_HADDR ),
        .HSIZE_S4      ( CoreAHBLite_0_AHBmslave4_HSIZE ),
        .HTRANS_S4     ( CoreAHBLite_0_AHBmslave4_HTRANS ),
        .HWDATA_S4     ( CoreAHBLite_0_AHBmslave4_HWDATA ),
        .HBURST_S4     ( CoreAHBLite_0_AHBmslave4_HBURST ),
        .HPROT_S4      ( CoreAHBLite_0_AHBmslave4_HPROT ),
        .HADDR_S5      (  ),
        .HSIZE_S5      (  ),
        .HTRANS_S5     (  ),
        .HWDATA_S5     (  ),
        .HBURST_S5     (  ),
        .HPROT_S5      (  ),
        .HADDR_S6      (  ),
        .HSIZE_S6      (  ),
        .HTRANS_S6     (  ),
        .HWDATA_S6     (  ),
        .HBURST_S6     (  ),
        .HPROT_S6      (  ),
        .HADDR_S7      (  ),
        .HSIZE_S7      (  ),
        .HTRANS_S7     (  ),
        .HWDATA_S7     (  ),
        .HBURST_S7     (  ),
        .HPROT_S7      (  ),
        .HADDR_S8      (  ),
        .HSIZE_S8      (  ),
        .HTRANS_S8     (  ),
        .HWDATA_S8     (  ),
        .HBURST_S8     (  ),
        .HPROT_S8      (  ),
        .HADDR_S9      (  ),
        .HSIZE_S9      (  ),
        .HTRANS_S9     (  ),
        .HWDATA_S9     (  ),
        .HBURST_S9     (  ),
        .HPROT_S9      (  ),
        .HADDR_S10     (  ),
        .HSIZE_S10     (  ),
        .HTRANS_S10    (  ),
        .HWDATA_S10    (  ),
        .HBURST_S10    (  ),
        .HPROT_S10     (  ),
        .HADDR_S11     (  ),
        .HSIZE_S11     (  ),
        .HTRANS_S11    (  ),
        .HWDATA_S11    (  ),
        .HBURST_S11    (  ),
        .HPROT_S11     (  ),
        .HADDR_S12     (  ),
        .HSIZE_S12     (  ),
        .HTRANS_S12    (  ),
        .HWDATA_S12    (  ),
        .HBURST_S12    (  ),
        .HPROT_S12     (  ),
        .HADDR_S13     (  ),
        .HSIZE_S13     (  ),
        .HTRANS_S13    (  ),
        .HWDATA_S13    (  ),
        .HBURST_S13    (  ),
        .HPROT_S13     (  ),
        .HADDR_S14     (  ),
        .HSIZE_S14     (  ),
        .HTRANS_S14    (  ),
        .HWDATA_S14    (  ),
        .HBURST_S14    (  ),
        .HPROT_S14     (  ),
        .HADDR_S15     (  ),
        .HSIZE_S15     (  ),
        .HTRANS_S15    (  ),
        .HWDATA_S15    (  ),
        .HBURST_S15    (  ),
        .HPROT_S15     (  ),
        .HADDR_S16     (  ),
        .HSIZE_S16     (  ),
        .HTRANS_S16    (  ),
        .HWDATA_S16    (  ),
        .HBURST_S16    (  ),
        .HPROT_S16     (  ) 
        );

//--------CoreConfigP   -   Actel:DirectCore:CoreConfigP:7.0.105
CoreConfigP #( 
        .DEVICE_090         ( 0 ),
        .ENABLE_SOFT_RESETS ( 0 ),
        .FDDR_IN_USE        ( 0 ),
        .MDDR_IN_USE        ( 1 ),
        .SDIF0_IN_USE       ( 0 ),
        .SDIF0_PCIE         ( 0 ),
        .SDIF1_IN_USE       ( 0 ),
        .SDIF1_PCIE         ( 0 ),
        .SDIF2_IN_USE       ( 0 ),
        .SDIF2_PCIE         ( 0 ),
        .SDIF3_IN_USE       ( 0 ),
        .SDIF3_PCIE         ( 0 ) )
CORECONFIGP_0(
        // Inputs
        .FIC_2_APB_M_PRESET_N           ( MSS_HPMS_READY ),
        .FIC_2_APB_M_PCLK               ( CodeShadowing_Fabric_MSS_0_FIC_2_APB_M_PCLK ),
        .SDIF_RELEASED                  ( GND_net ), // tied to 1'b0 from definition
        .INIT_DONE                      ( VCC_net ),
        .FIC_2_APB_M_PSEL               ( HW_Boot_Engine_0_APB_IF_PSELx ),
        .FIC_2_APB_M_PENABLE            ( HW_Boot_Engine_0_APB_IF_PENABLE ),
        .FIC_2_APB_M_PWRITE             ( HW_Boot_Engine_0_APB_IF_PWRITE ),
        .MDDR_PREADY                    ( CORECONFIGP_0_MDDR_APBmslave_PREADY ),
        .MDDR_PSLVERR                   ( CORECONFIGP_0_MDDR_APBmslave_PSLVERR ),
        .FDDR_PREADY                    ( VCC_net ), // tied to 1'b1 from definition
        .FDDR_PSLVERR                   ( GND_net ), // tied to 1'b0 from definition
        .SDIF0_PREADY                   ( VCC_net ), // tied to 1'b1 from definition
        .SDIF0_PSLVERR                  ( GND_net ), // tied to 1'b0 from definition
        .SDIF1_PREADY                   ( VCC_net ), // tied to 1'b1 from definition
        .SDIF1_PSLVERR                  ( GND_net ), // tied to 1'b0 from definition
        .SDIF2_PREADY                   ( VCC_net ), // tied to 1'b1 from definition
        .SDIF2_PSLVERR                  ( GND_net ), // tied to 1'b0 from definition
        .SDIF3_PREADY                   ( VCC_net ), // tied to 1'b1 from definition
        .SDIF3_PSLVERR                  ( GND_net ), // tied to 1'b0 from definition
        .FIC_2_APB_M_PADDR              ( HW_Boot_Engine_0_APB_IF_PADDR_0 ),
        .FIC_2_APB_M_PWDATA             ( HW_Boot_Engine_0_APB_IF_PWDATA_0 ),
        .MDDR_PRDATA                    ( CORECONFIGP_0_MDDR_APBmslave_PRDATA_0 ),
        .FDDR_PRDATA                    ( FDDR_PRDATA_const_net_0 ), // tied to 32'h00000000 from definition
        .SDIF0_PRDATA                   ( SDIF0_PRDATA_const_net_0 ), // tied to 32'h00000000 from definition
        .SDIF1_PRDATA                   ( SDIF1_PRDATA_const_net_0 ), // tied to 32'h00000000 from definition
        .SDIF2_PRDATA                   ( SDIF2_PRDATA_const_net_0 ), // tied to 32'h00000000 from definition
        .SDIF3_PRDATA                   ( SDIF3_PRDATA_const_net_0 ), // tied to 32'h00000000 from definition
        // Outputs
        .APB_S_PCLK                     ( CORECONFIGP_0_APB_S_PCLK ),
        .APB_S_PRESET_N                 ( CORECONFIGP_0_APB_S_PRESET_N ),
        .CONFIG1_DONE                   (  ),
        .CONFIG2_DONE                   (  ),
        .FIC_2_APB_M_PREADY             ( HW_Boot_Engine_0_APB_IF_PREADY ),
        .FIC_2_APB_M_PSLVERR            ( HW_Boot_Engine_0_APB_IF_PSLVERR ),
        .MDDR_PSEL                      ( CORECONFIGP_0_MDDR_APBmslave_PSELx ),
        .MDDR_PENABLE                   ( CORECONFIGP_0_MDDR_APBmslave_PENABLE ),
        .MDDR_PWRITE                    ( CORECONFIGP_0_MDDR_APBmslave_PWRITE ),
        .FDDR_PSEL                      (  ),
        .FDDR_PENABLE                   (  ),
        .FDDR_PWRITE                    (  ),
        .SDIF0_PSEL                     (  ),
        .SDIF0_PENABLE                  (  ),
        .SDIF0_PWRITE                   (  ),
        .SDIF1_PSEL                     (  ),
        .SDIF1_PENABLE                  (  ),
        .SDIF1_PWRITE                   (  ),
        .SDIF2_PSEL                     (  ),
        .SDIF2_PENABLE                  (  ),
        .SDIF2_PWRITE                   (  ),
        .SDIF3_PSEL                     (  ),
        .SDIF3_PENABLE                  (  ),
        .SDIF3_PWRITE                   (  ),
        .SOFT_EXT_RESET_OUT             (  ),
        .SOFT_RESET_F2M                 (  ),
        .SOFT_M3_RESET                  (  ),
        .SOFT_MDDR_DDR_AXI_S_CORE_RESET (  ),
        .SOFT_FDDR_CORE_RESET           (  ),
        .SOFT_SDIF0_PHY_RESET           (  ),
        .SOFT_SDIF0_CORE_RESET          (  ),
        .SOFT_SDIF0_0_CORE_RESET        (  ),
        .SOFT_SDIF0_1_CORE_RESET        (  ),
        .SOFT_SDIF1_PHY_RESET           (  ),
        .SOFT_SDIF1_CORE_RESET          (  ),
        .SOFT_SDIF2_PHY_RESET           (  ),
        .SOFT_SDIF2_CORE_RESET          (  ),
        .SOFT_SDIF3_PHY_RESET           (  ),
        .SOFT_SDIF3_CORE_RESET          (  ),
        .R_SDIF0_PSEL                   (  ),
        .R_SDIF0_PWRITE                 (  ),
        .R_SDIF1_PSEL                   (  ),
        .R_SDIF1_PWRITE                 (  ),
        .R_SDIF2_PSEL                   (  ),
        .R_SDIF2_PWRITE                 (  ),
        .R_SDIF3_PSEL                   (  ),
        .R_SDIF3_PWRITE                 (  ),
        .FIC_2_APB_M_PRDATA             ( HW_Boot_Engine_0_APB_IF_PRDATA ),
        .MDDR_PADDR                     ( CORECONFIGP_0_MDDR_APBmslave_PADDR ),
        .MDDR_PWDATA                    ( CORECONFIGP_0_MDDR_APBmslave_PWDATA ),
        .FDDR_PADDR                     (  ),
        .FDDR_PWDATA                    (  ),
        .SDIF0_PADDR                    (  ),
        .SDIF0_PWDATA                   (  ),
        .SDIF1_PADDR                    (  ),
        .SDIF1_PWDATA                   (  ),
        .SDIF2_PADDR                    (  ),
        .SDIF2_PWDATA                   (  ),
        .SDIF3_PADDR                    (  ),
        .SDIF3_PWDATA                   (  ),
        .R_SDIF0_PRDATA                 (  ),
        .R_SDIF1_PRDATA                 (  ),
        .R_SDIF2_PRDATA                 (  ),
        .R_SDIF3_PRDATA                 (  ) 
        );

//--------CoreResetP   -   Actel:DirectCore:CoreResetP:7.0.104
CoreResetP #( 
        .DDR_WAIT            ( 200 ),
        .DEVICE_090          ( 0 ),
        .DEVICE_VOLTAGE      ( 2 ),
        .ENABLE_SOFT_RESETS  ( 0 ),
        .EXT_RESET_CFG       ( 0 ),
        .FDDR_IN_USE         ( 0 ),
        .MDDR_IN_USE         ( 0 ),
        .SDIF0_IN_USE        ( 0 ),
        .SDIF0_PCIE          ( 0 ),
        .SDIF0_PCIE_HOTRESET ( 1 ),
        .SDIF0_PCIE_L2P2     ( 1 ),
        .SDIF1_IN_USE        ( 0 ),
        .SDIF1_PCIE          ( 0 ),
        .SDIF1_PCIE_HOTRESET ( 1 ),
        .SDIF1_PCIE_L2P2     ( 1 ),
        .SDIF2_IN_USE        ( 0 ),
        .SDIF2_PCIE          ( 0 ),
        .SDIF2_PCIE_HOTRESET ( 1 ),
        .SDIF2_PCIE_L2P2     ( 1 ),
        .SDIF3_IN_USE        ( 0 ),
        .SDIF3_PCIE          ( 0 ),
        .SDIF3_PCIE_HOTRESET ( 1 ),
        .SDIF3_PCIE_L2P2     ( 1 ) )
CORERESETP_0(
        // Inputs
        .RESET_N_M2F                    ( MSS_RESET_N_M2F ),
        .FIC_2_APB_M_PRESET_N           ( FIC_2_APB_M_PRESET_N ),
        .POWER_ON_RESET_N               ( POWER_ON_RESET_N ),
        .FAB_RESET_N                    ( VCC_net ),
        .RCOSC_25_50MHZ                 ( FABOSC_0_RCOSC_25_50MHZ_O2F ),
        .CLK_BASE                       ( FIC_0_CLK ),
        .CLK_LTSSM                      ( GND_net ), // tied to 1'b0 from definition
        .FPLL_LOCK                      ( VCC_net ), // tied to 1'b1 from definition
        .SDIF0_SPLL_LOCK                ( VCC_net ), // tied to 1'b1 from definition
        .SDIF1_SPLL_LOCK                ( VCC_net ), // tied to 1'b1 from definition
        .SDIF2_SPLL_LOCK                ( VCC_net ), // tied to 1'b1 from definition
        .SDIF3_SPLL_LOCK                ( VCC_net ), // tied to 1'b1 from definition
        .CONFIG1_DONE                   ( VCC_net ),
        .CONFIG2_DONE                   ( VCC_net ),
        .SDIF0_PERST_N                  ( VCC_net ), // tied to 1'b1 from definition
        .SDIF1_PERST_N                  ( VCC_net ), // tied to 1'b1 from definition
        .SDIF2_PERST_N                  ( VCC_net ), // tied to 1'b1 from definition
        .SDIF3_PERST_N                  ( VCC_net ), // tied to 1'b1 from definition
        .SDIF0_PSEL                     ( GND_net ), // tied to 1'b0 from definition
        .SDIF0_PWRITE                   ( VCC_net ), // tied to 1'b1 from definition
        .SDIF1_PSEL                     ( GND_net ), // tied to 1'b0 from definition
        .SDIF1_PWRITE                   ( VCC_net ), // tied to 1'b1 from definition
        .SDIF2_PSEL                     ( GND_net ), // tied to 1'b0 from definition
        .SDIF2_PWRITE                   ( VCC_net ), // tied to 1'b1 from definition
        .SDIF3_PSEL                     ( GND_net ), // tied to 1'b0 from definition
        .SDIF3_PWRITE                   ( VCC_net ), // tied to 1'b1 from definition
        .SOFT_EXT_RESET_OUT             ( GND_net ), // tied to 1'b0 from definition
        .SOFT_RESET_F2M                 ( GND_net ), // tied to 1'b0 from definition
        .SOFT_M3_RESET                  ( GND_net ), // tied to 1'b0 from definition
        .SOFT_MDDR_DDR_AXI_S_CORE_RESET ( GND_net ), // tied to 1'b0 from definition
        .SOFT_FDDR_CORE_RESET           ( GND_net ), // tied to 1'b0 from definition
        .SOFT_SDIF0_PHY_RESET           ( GND_net ), // tied to 1'b0 from definition
        .SOFT_SDIF0_CORE_RESET          ( GND_net ), // tied to 1'b0 from definition
        .SOFT_SDIF0_0_CORE_RESET        ( GND_net ), // tied to 1'b0 from definition
        .SOFT_SDIF0_1_CORE_RESET        ( GND_net ), // tied to 1'b0 from definition
        .SOFT_SDIF1_PHY_RESET           ( GND_net ), // tied to 1'b0 from definition
        .SOFT_SDIF1_CORE_RESET          ( GND_net ), // tied to 1'b0 from definition
        .SOFT_SDIF2_PHY_RESET           ( GND_net ), // tied to 1'b0 from definition
        .SOFT_SDIF2_CORE_RESET          ( GND_net ), // tied to 1'b0 from definition
        .SOFT_SDIF3_PHY_RESET           ( GND_net ), // tied to 1'b0 from definition
        .SOFT_SDIF3_CORE_RESET          ( GND_net ), // tied to 1'b0 from definition
        .SDIF0_PRDATA                   ( SDIF0_PRDATA_const_net_1 ), // tied to 32'h00000000 from definition
        .SDIF1_PRDATA                   ( SDIF1_PRDATA_const_net_1 ), // tied to 32'h00000000 from definition
        .SDIF2_PRDATA                   ( SDIF2_PRDATA_const_net_1 ), // tied to 32'h00000000 from definition
        .SDIF3_PRDATA                   ( SDIF3_PRDATA_const_net_1 ), // tied to 32'h00000000 from definition
        // Outputs
        .MSS_HPMS_READY                 ( MSS_HPMS_READY ),
        .DDR_READY                      (  ),
        .SDIF_READY                     (  ),
        .RESET_N_F2M                    (  ),
        .M3_RESET_N                     (  ),
        .EXT_RESET_OUT                  (  ),
        .MDDR_DDR_AXI_S_CORE_RESET_N    (  ),
        .FDDR_CORE_RESET_N              (  ),
        .SDIF0_CORE_RESET_N             (  ),
        .SDIF0_0_CORE_RESET_N           (  ),
        .SDIF0_1_CORE_RESET_N           (  ),
        .SDIF0_PHY_RESET_N              (  ),
        .SDIF1_CORE_RESET_N             (  ),
        .SDIF1_PHY_RESET_N              (  ),
        .SDIF2_CORE_RESET_N             (  ),
        .SDIF2_PHY_RESET_N              (  ),
        .SDIF3_CORE_RESET_N             (  ),
        .SDIF3_PHY_RESET_N              (  ),
        .SDIF_RELEASED                  (  ),
        .INIT_DONE                      (  ) 
        );

//--------CodeShadowing_Fabric_FABOSC_0_OSC   -   Actel:SgCore:OSC:2.0.101
CodeShadowing_Fabric_FABOSC_0_OSC FABOSC_0(
        // Inputs
        .XTL                ( GND_net ), // tied to 1'b0 from definition
        // Outputs
        .RCOSC_25_50MHZ_CCC ( FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC ),
        .RCOSC_25_50MHZ_O2F ( FABOSC_0_RCOSC_25_50MHZ_O2F ),
        .RCOSC_1MHZ_CCC     (  ),
        .RCOSC_1MHZ_O2F     (  ),
        .XTLOSC_CCC         (  ),
        .XTLOSC_O2F         (  ) 
        );

//--------HW_Boot_Engine
HW_Boot_Engine HW_Boot_Engine_0(
        // Inputs
        .RESETn            ( MSS_HPMS_READY ),
        .APB_CLK           ( CORECONFIGP_0_APB_S_PCLK ),
        .CLK               ( FIC_0_CLK ),
        .START_CODE_SHADOW ( DP_SW1 ),
        .AWREADY           ( HW_Boot_Engine_0_AXI_IF_AWREADY ),
        .WREADY            ( HW_Boot_Engine_0_AXI_IF_WREADY ),
        .BVALID            ( HW_Boot_Engine_0_AXI_IF_BVALID ),
        .ARREADY           ( HW_Boot_Engine_0_AXI_IF_ARREADY ),
        .RLAST             ( HW_Boot_Engine_0_AXI_IF_RLAST ),
        .RVALID            ( HW_Boot_Engine_0_AXI_IF_RVALID ),
        .PREADY            ( HW_Boot_Engine_0_APB_IF_PREADY ),
        .PSLVERR           ( HW_Boot_Engine_0_APB_IF_PSLVERR ),
        .HREADY            ( HW_Boot_Engine_0_AHB_IF_HREADY ),
        .BID               ( HW_Boot_Engine_0_AXI_IF_BID ),
        .BRESP             ( HW_Boot_Engine_0_AXI_IF_BRESP ),
        .RID               ( HW_Boot_Engine_0_AXI_IF_RID ),
        .RDATA             ( HW_Boot_Engine_0_AXI_IF_RDATA ),
        .RRESP             ( HW_Boot_Engine_0_AXI_IF_RRESP ),
        .PRDATA            ( HW_Boot_Engine_0_APB_IF_PRDATA_0 ),
        .HRDATA            ( HW_Boot_Engine_0_AHB_IF_HRDATA ),
        .HRESP             ( HW_Boot_Engine_0_AHB_IF_HRESP ),
        // Outputs
        .AWVALID           ( HW_Boot_Engine_0_AXI_IF_AWVALID ),
        .WLAST             ( HW_Boot_Engine_0_AXI_IF_WLAST ),
        .WVALID            ( HW_Boot_Engine_0_AXI_IF_WVALID ),
        .BREADY            ( HW_Boot_Engine_0_AXI_IF_BREADY ),
        .ARVALID           ( HW_Boot_Engine_0_AXI_IF_ARVALID ),
        .RREADY            ( HW_Boot_Engine_0_AXI_IF_RREADY ),
        .PENABLE           ( HW_Boot_Engine_0_APB_IF_PENABLE ),
        .PWRITE            ( HW_Boot_Engine_0_APB_IF_PWRITE ),
        .PSEL              ( HW_Boot_Engine_0_APB_IF_PSELx ),
        .M3_RESETn         ( M3_RESETn ),
        .HWRITE            ( HW_Boot_Engine_0_AHB_IF_HWRITE ),
        .AWID              ( HW_Boot_Engine_0_AXI_IF_AWID ),
        .AWADDR            ( HW_Boot_Engine_0_AXI_IF_AWADDR ),
        .AWLEN             ( HW_Boot_Engine_0_AXI_IF_AWLEN ),
        .AWSIZE            ( HW_Boot_Engine_0_AXI_IF_AWSIZE ),
        .AWBURST           ( HW_Boot_Engine_0_AXI_IF_AWBURST ),
        .AWLOCK            ( HW_Boot_Engine_0_AXI_IF_AWLOCK ),
        .WID               ( HW_Boot_Engine_0_AXI_IF_WID ),
        .WDATA             ( HW_Boot_Engine_0_AXI_IF_WDATA ),
        .WSTRB             ( HW_Boot_Engine_0_AXI_IF_WSTRB ),
        .ARID              ( HW_Boot_Engine_0_AXI_IF_ARID ),
        .ARADDR            ( HW_Boot_Engine_0_AXI_IF_ARADDR ),
        .ARLEN             ( HW_Boot_Engine_0_AXI_IF_ARLEN ),
        .ARSIZE            ( HW_Boot_Engine_0_AXI_IF_ARSIZE ),
        .ARBURST           ( HW_Boot_Engine_0_AXI_IF_ARBURST ),
        .ARLOCK            ( HW_Boot_Engine_0_AXI_IF_ARLOCK ),
        .PADDR             ( HW_Boot_Engine_0_APB_IF_PADDR ),
        .PWDATA            ( HW_Boot_Engine_0_APB_IF_PWDATA ),
        .HADDR             ( HW_Boot_Engine_0_AHB_IF_HADDR ),
        .HTRANS            ( HW_Boot_Engine_0_AHB_IF_HTRANS ),
        .HSIZE             ( HW_Boot_Engine_0_AHB_IF_HSIZE ),
        .HBURST            ( HW_Boot_Engine_0_AHB_IF_HBURST ),
        .HPROT             ( HW_Boot_Engine_0_AHB_IF_HPROT ),
        .HWDATA            ( HW_Boot_Engine_0_AHB_IF_HWDATA ) 
        );

//--------SYSRESET
SYSRESET SYSRESET_POR(
        // Inputs
        .DEVRST_N         ( DEVRST_N ),
        // Outputs
        .POWER_ON_RESET_N ( POWER_ON_RESET_N ) 
        );


endmodule
