`

    #Build: Synplify Pro L-2016.09M-2, Build 065R, Nov 16 2016
    #install: C:\Microsemi\Libero_SoC_v11.8\SynplifyPro
    #OS: Windows 7 6.1
    #Hostname: SJSOC0507

    # Fri Mar 24 19:57:04 2017

    #Implementation: synthesis

    Synopsys HDL Compiler, version comp2016q3p1, Build 117R, built Nov 17 2016
    @N: :  | Running in 64-bit mode
    Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

    Synopsys Verilog Compiler, version comp2016q3p1, Build 127R, built Nov 24 2016
    @N: :  | Running in 64-bit mode
    Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

    @I::"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\smartfusion2.v" (library work)
    @I::"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
    @I::"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"C:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"C:\AC407_11_8\m2s_ac407_using_nrbg_services_liberov11p7_df\Libero\M2S090_design\NRBG_M2S090TS\hdl\Count28.v" (library work)
    @I::"C:\AC407_11_8\m2s_ac407_using_nrbg_services_liberov11p7_df\Libero\M2S090_design\NRBG_M2S090TS\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v" (library work)
    @I::"C:\AC407_11_8\m2s_ac407_using_nrbg_services_liberov11p7_df\Libero\M2S090_design\NRBG_M2S090TS\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v" (library work)
    @I::"C:\AC407_11_8\m2s_ac407_using_nrbg_services_liberov11p7_df\Libero\M2S090_design\NRBG_M2S090TS\component\work\my_mss_sb\CCC_0\my_mss_sb_CCC_0_FCCC.v" (library work)
    @I::"C:\AC407_11_8\m2s_ac407_using_nrbg_services_liberov11p7_df\Libero\M2S090_design\NRBG_M2S090TS\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" (library work)
    @I::"C:\AC407_11_8\m2s_ac407_using_nrbg_services_liberov11p7_df\Libero\M2S090_design\NRBG_M2S090TS\component\work\my_mss_sb\FABOSC_0\my_mss_sb_FABOSC_0_OSC.v" (library work)
    @I::"C:\AC407_11_8\m2s_ac407_using_nrbg_services_liberov11p7_df\Libero\M2S090_design\NRBG_M2S090TS\component\work\my_mss_sb_MSS\my_mss_sb_MSS_syn.v" (library work)
    @I::"C:\AC407_11_8\m2s_ac407_using_nrbg_services_liberov11p7_df\Libero\M2S090_design\NRBG_M2S090TS\component\work\my_mss_sb_MSS\my_mss_sb_MSS.v" (library work)
    @I::"C:\AC407_11_8\m2s_ac407_using_nrbg_services_liberov11p7_df\Libero\M2S090_design\NRBG_M2S090TS\component\work\my_mss_sb\my_mss_sb.v" (library work)
    @I::"C:\AC407_11_8\m2s_ac407_using_nrbg_services_liberov11p7_df\Libero\M2S090_design\NRBG_M2S090TS\component\work\my_mss\my_mss.v" (library work)
    @I::"C:\AC407_11_8\m2s_ac407_using_nrbg_services_liberov11p7_df\Libero\M2S090_design\NRBG_M2S090TS\component\work\Top\Top.v" (library work)
    Verilog syntax check successful!
    Options changed - recompiling
    Selecting top level module Top
    @N:CG364 : Count28.v(3) | Synthesizing module counter28 in library work.

    @N:CG364 : smartfusion2.v(376) | Synthesizing module VCC in library work.

    @N:CG364 : smartfusion2.v(372) | Synthesizing module GND in library work.

    @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT in library work.

    @N:CG364 : smartfusion2.v(727) | Synthesizing module CCC in library work.

    @N:CG364 : my_mss_sb_CCC_0_FCCC.v(5) | Synthesizing module my_mss_sb_CCC_0_FCCC in library work.

    @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP in library work.

    	FAMILY=32'b00000000000000000000000000010011
    	EXT_RESET_CFG=32'b00000000000000000000000000000000
    	DEVICE_VOLTAGE=32'b00000000000000000000000000000010
    	MDDR_IN_USE=32'b00000000000000000000000000000000
    	FDDR_IN_USE=32'b00000000000000000000000000000000
    	SDIF0_IN_USE=32'b00000000000000000000000000000000
    	SDIF1_IN_USE=32'b00000000000000000000000000000000
    	SDIF2_IN_USE=32'b00000000000000000000000000000000
    	SDIF3_IN_USE=32'b00000000000000000000000000000000
    	SDIF0_PCIE=32'b00000000000000000000000000000000
    	SDIF1_PCIE=32'b00000000000000000000000000000000
    	SDIF2_PCIE=32'b00000000000000000000000000000000
    	SDIF3_PCIE=32'b00000000000000000000000000000000
    	SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001
    	SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001
    	SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001
    	SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001
    	SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001
    	SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001
    	SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001
    	SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001
    	ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000
    	DEVICE_090=32'b00000000000000000000000000000001
    	DDR_WAIT=32'b00000000000000000000000011001000
    	RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010
    	SDIF_INTERVAL=32'b00000000000000000001100101100100
    	DDR_INTERVAL=32'b00000000000000000010011100010000
    	COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101
    	COUNT_WIDTH_DDR=32'b00000000000000000000000000001110
    	S0=32'b00000000000000000000000000000000
    	S1=32'b00000000000000000000000000000001
    	S2=32'b00000000000000000000000000000010
    	S3=32'b00000000000000000000000000000011
    	S4=32'b00000000000000000000000000000100
    	S5=32'b00000000000000000000000000000101
    	S6=32'b00000000000000000000000000000110
       Generated name = CoreResetP_Z1

    @W:CL169 : coreresetp.v(1613) | Pruning unused register count_ddr[13:0]. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.v(1581) | Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.v(1549) | Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.v(1517) | Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.v(1485) | Pruning unused register count_sdif0[12:0]. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_q1. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif0_enable_rcosc. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.v(1455) | Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.v(1455) | Pruning unused register count_ddr_enable_q1. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.v(1455) | Pruning unused register count_ddr_enable_rcosc. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.v(1365) | Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.v(1300) | Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.v(1235) | Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.v(1170) | Pruning unused register count_sdif0_enable. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.v(1089) | Pruning unused register count_ddr_enable. Make sure that there are no unused intermediate registers.
    @W:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing.
    @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
    @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
    @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
    @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
    @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
    @W:CL169 : coreresetp.v(1089) | Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.v(1433) | Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.v(1433) | Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers.
    @W:CL169 : coreresetp.v(783) | Pruning unused register sm2_areset_n_clk_base. Make sure that there are no unused intermediate registers.
    @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB in library work.

    @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ in library work.

    @N:CG364 : my_mss_sb_FABOSC_0_OSC.v(5) | Synthesizing module my_mss_sb_FABOSC_0_OSC in library work.

    @N:CG364 : my_mss_sb_MSS_syn.v(5) | Synthesizing module MSS_075 in library work.

    @N:CG364 : my_mss_sb_MSS.v(9) | Synthesizing module my_mss_sb_MSS in library work.

    @N:CG364 : smartfusion2.v(718) | Synthesizing module SYSRESET in library work.

    @N:CG364 : my_mss_sb.v(9) | Synthesizing module my_mss_sb in library work.

    @N:CG364 : my_mss.v(9) | Synthesizing module my_mss in library work.

    @N:CG364 : Top.v(9) | Synthesizing module Top in library work.

    @W:CL157 : my_mss_sb_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
    @W:CL157 : my_mss_sb_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
    @W:CL157 : my_mss_sb_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
    @W:CL157 : my_mss_sb_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
    @N:CL159 : my_mss_sb_FABOSC_0_OSC.v(14) | Input XTL is unused.
    @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
    @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
    @W:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
    @W:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
    @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state.
    Extracted state machine for register sdif3_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state.
    Extracted state machine for register sdif2_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state.
    Extracted state machine for register sdif1_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state.
    Extracted state machine for register sdif0_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state.
    Extracted state machine for register sm0_state
    State machine has 7 reachable states with original encodings of:
       000
       001
       010
       011
       100
       101
       110
    @N:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused.
    @N:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused.
    @N:CL159 : coreresetp.v(59) | Input SDIF0_SPLL_LOCK is unused.
    @N:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused.
    @N:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused.
    @N:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused.
    @N:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused.
    @N:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused.
    @N:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused.
    @N:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused.
    @N:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused.
    @N:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused.
    @N:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused.
    @N:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused.
    @N:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused.
    @N:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused.
    @N:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused.
    @N:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused.
    @N:CL159 : coreresetp.v(107) | Input SOFT_EXT_RESET_OUT is unused.
    @N:CL159 : coreresetp.v(108) | Input SOFT_RESET_F2M is unused.
    @N:CL159 : coreresetp.v(109) | Input SOFT_M3_RESET is unused.
    @N:CL159 : coreresetp.v(110) | Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused.
    @N:CL159 : coreresetp.v(111) | Input SOFT_FDDR_CORE_RESET is unused.
    @N:CL159 : coreresetp.v(112) | Input SOFT_SDIF0_PHY_RESET is unused.
    @N:CL159 : coreresetp.v(113) | Input SOFT_SDIF0_CORE_RESET is unused.
    @N:CL159 : coreresetp.v(114) | Input SOFT_SDIF1_PHY_RESET is unused.
    @N:CL159 : coreresetp.v(115) | Input SOFT_SDIF1_CORE_RESET is unused.
    @N:CL159 : coreresetp.v(116) | Input SOFT_SDIF2_PHY_RESET is unused.
    @N:CL159 : coreresetp.v(117) | Input SOFT_SDIF2_CORE_RESET is unused.
    @N:CL159 : coreresetp.v(118) | Input SOFT_SDIF3_PHY_RESET is unused.
    @N:CL159 : coreresetp.v(119) | Input SOFT_SDIF3_CORE_RESET is unused.
    @N:CL159 : coreresetp.v(123) | Input SOFT_SDIF0_0_CORE_RESET is unused.
    @N:CL159 : coreresetp.v(124) | Input SOFT_SDIF0_1_CORE_RESET is unused.

    At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Fri Mar 24 19:57:04 2017

    ###########################################################]
    Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016
    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Fri Mar 24 19:57:04 2017

    ###########################################################]
    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Fri Mar 24 19:57:04 2017

    ###########################################################]
    Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016
    @N: :  | Running in 64-bit mode
    File C:\Microsemi\Libero_SoC_v11.7\Synplify\bin64\syn_nfilter.exe changed - recompiling
    File D:\cases\11_7APPNOTE UPDATE\AC407\m2s_ac407_using_nrbg_services_liberov11p7_df\m2s_ac407_using_nrbg_services_liberov11p6_df\M2S090_design\NRBG_M2S090TS\synthesis\synwork\Top_comp.srs changed - recompiling

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 70MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Fri Mar 24 19:57:06 2017

    ###########################################################]
    Pre-mapping Report

    # Fri Mar 24 19:57:06 2017

    Synopsys Generic Technology Pre-mapping, Version map201609actrcp1, Build 005R, Built Jan 25 2017 01:01:33
    Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
    Product Version L-2016.09M-2

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @A:MF827 :  | No constraint file specified.
    Linked File: Top_scck.rpt
    Printing clock  summary report in "C:\AC407_11_8\m2s_ac407_using_nrbg_services_liberov11p7_df\Libero\M2S090_design\NRBG_M2S090TS\synthesis\Top_scck.rpt" file
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 106MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 106MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 106MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 107MB)

    @W:BN132 : coreresetp.v(1089) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int because it is equivalent to instance my_mss_0.my_mss_sb_0.CORERESETP_0.FDDR_CORE_RESET_N_int. To keep the instance, apply constraint syn_preserve=1 on the instance.
    @N:MO111 : my_mss_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.my_mss_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.my_mss_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
    @N:MO111 : my_mss_sb_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.my_mss_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.my_mss_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
    @N:MO111 : my_mss_sb_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.my_mss_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.my_mss_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
    @N:MO111 : my_mss_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.my_mss_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.my_mss_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
    @W:MO129 : coreresetp.v(676) | Sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.v(695) | Sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.v(714) | Sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.v(733) | Sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.v(769) | Sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.v(676) | Sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.v(695) | Sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.v(714) | Sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.v(733) | Sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.v(769) | Sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.sm1_areset_n_clk_base is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.v(676) | Sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.v(695) | Sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.v(714) | Sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.v(733) | Sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation.
    @W:MO129 : coreresetp.v(1388) | Sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation.
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_READY_int (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_RELEASED_int (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_PHY_RESET_N_int (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.v(1170) | Removing sequential instance sdif0_state[3:0] (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_clk_base (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_q1 (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 (in view: work.CoreResetP_Z1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
    syn_allowed_resources : blockrams=109  set on top level netlist Top

    Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB)

    Clock Summary
    *****************

    Start                                                        Requested     Requested     Clock        Clock                   Clock
    Clock                                                        Frequency     Period        Type         Group                   Load
    -----------------------------------------------------------------------------------------------------------------------------------
    System                                                       100.0 MHz     10.000        system       system_clkgroup         0
    my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock                  100.0 MHz     10.000        inferred     Inferred_clkgroup_0     64
    my_mss_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_1     15
    ===================================================================================================================================

    @W:MT530 : count28.v(16) | Found inferred clock my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock which controls 64 sequential elements including counter28_0.cntout[27:0]. This clock has no specified timing constraint which may adversely impact design performance.
    @W:MT530 : coreresetp.v(912) | Found inferred clock my_mss_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 15 sequential elements including my_mss_0.my_mss_sb_0.CORERESETP_0.sdif3_areset_n_rcosc_q1. This clock has no specified timing constraint which may adversely impact design performance.

    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file C:\AC407_11_8\m2s_ac407_using_nrbg_services_liberov11p7_df\Libero\M2S090_design\NRBG_M2S090TS\synthesis\Top.sap.

    Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 137MB)

    Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z1(verilog))
    original code -> new code
       000 -> 0000001
       001 -> 0000010
       010 -> 0000100
       011 -> 0001000
       100 -> 0010000
       101 -> 0100000
       110 -> 1000000
    None
    None

    Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 137MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 137MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Fri Mar 24 19:57:06 2017

    ###########################################################]
    Map & Optimize Report

    # Fri Mar 24 19:57:06 2017

    Synopsys Generic Technology Mapper, Version map201609actrcp1, Build 005R, Built Jan 25 2017 01:01:33
    Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
    Product Version L-2016.09M-2

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 136MB)

    @N:MO111 : my_mss_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.my_mss_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.my_mss_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
    @N:MO111 : my_mss_sb_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.my_mss_sb_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.my_mss_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
    @N:MO111 : my_mss_sb_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.my_mss_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.my_mss_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
    @N:MO111 : my_mss_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.my_mss_sb_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.my_mss_sb_FABOSC_0_OSC(verilog)) has its enable tied to GND.
    @W:BN132 : coreresetp.v(963) | Removing sequential instance my_mss_sb_0.CORERESETP_0.sdif3_spll_lock_q1 because it is equivalent to instance my_mss_sb_0.CORERESETP_0.CONFIG2_DONE_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
    @W:BN132 : coreresetp.v(946) | Removing sequential instance my_mss_sb_0.CORERESETP_0.CONFIG2_DONE_q1 because it is equivalent to instance my_mss_sb_0.CORERESETP_0.CONFIG1_DONE_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
    @W:BN132 : coreresetp.v(946) | Removing sequential instance my_mss_sb_0.CORERESETP_0.CONFIG2_DONE_clk_base because it is equivalent to instance my_mss_sb_0.CORERESETP_0.sdif3_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance.
    @W:BN132 : coreresetp.v(929) | Removing sequential instance my_mss_sb_0.CORERESETP_0.CONFIG1_DONE_clk_base because it is equivalent to instance my_mss_sb_0.CORERESETP_0.sdif3_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance.
    @W:BN132 : coreresetp.v(884) | Removing sequential instance my_mss_sb_0.CORERESETP_0.sdif1_areset_n_rcosc_q1 because it is equivalent to instance my_mss_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
    @W:BN132 : coreresetp.v(912) | Removing sequential instance my_mss_sb_0.CORERESETP_0.sdif3_areset_n_rcosc_q1 because it is equivalent to instance my_mss_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
    @W:BN132 : coreresetp.v(898) | Removing sequential instance my_mss_sb_0.CORERESETP_0.sdif2_areset_n_rcosc_q1 because it is equivalent to instance my_mss_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
    @W:BN132 : coreresetp.v(856) | Removing sequential instance my_mss_sb_0.CORERESETP_0.sm0_areset_n_rcosc_q1 because it is equivalent to instance my_mss_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
    @W:BN132 : coreresetp.v(898) | Removing sequential instance my_mss_sb_0.CORERESETP_0.sdif2_areset_n_rcosc because it is equivalent to instance my_mss_sb_0.CORERESETP_0.sm0_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance.
    @W:BN132 : coreresetp.v(912) | Removing sequential instance my_mss_sb_0.CORERESETP_0.sdif3_areset_n_rcosc because it is equivalent to instance my_mss_sb_0.CORERESETP_0.sm0_areset_n_rcosc. To keep the instance, apply constraint syn_preserve=1 on the instance.

    Available hyper_sources - for debug and ip models
    	None Found

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)

    @N:MO231 : count28.v(16) | Found counter in view:work.Top(verilog) instance counter28_0.cntout[27:0]
    Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z1(verilog))
    original code -> new code
       000 -> 0000001
       001 -> 0000010
       010 -> 0000100
       011 -> 0001000
       100 -> 0010000
       101 -> 0100000
       110 -> 1000000

    Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)

    @N:BN362 : coreresetp.v(1089) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.INIT_DONE_int (in view: work.Top(verilog)) because it does not drive other instances.
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.sm0_state[6] (in view: work.Top(verilog)) because it does not drive other instances.

    Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)

    Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)

    @W:BN114 : my_mss_sb.v(243) | Removing instance my_mss_0.my_mss_sb_0.SYSRESET_POR (in view: work.Top(verilog)) of black box view:ACG4.SYSRESET(PRIM) because it does not drive other instances.
    @N:BN362 : coreresetp.v(1613) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.ddr_settled (in view: work.Top(verilog)) because it does not drive other instances.
    @A:BN291 : coreresetp.v(1613) | Boundary register my_mss_0.my_mss_sb_0.CORERESETP_0.ddr_settled (in view: work.Top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @N:BN362 : coreresetp.v(526) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.FIC_2_APB_M_PRESET_N_q1 (in view: work.Top(verilog)) because it does not drive other instances.
    @N:BN362 : coreresetp.v(511) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.RESET_N_M2F_q1 (in view: work.Top(verilog)) because it does not drive other instances.
    @N:BN362 : coreresetp.v(496) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.POWER_ON_RESET_N_q1 (in view: work.Top(verilog)) because it does not drive other instances.
    @N:BN362 : coreresetp.v(1646) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.ddr_settled_q1 (in view: work.Top(verilog)) because it does not drive other instances.
    @A:BN291 : coreresetp.v(1646) | Boundary register my_mss_0.my_mss_sb_0.CORERESETP_0.ddr_settled_q1 (in view: work.Top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @N:BN362 : coreresetp.v(963) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.sdif3_spll_lock_q2 (in view: work.Top(verilog)) because it does not drive other instances.
    @N:BN362 : coreresetp.v(929) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.CONFIG1_DONE_q1 (in view: work.Top(verilog)) because it does not drive other instances.
    @N:BN362 : coreresetp.v(870) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1 (in view: work.Top(verilog)) because it does not drive other instances.
    @N:BN362 : coreresetp.v(565) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.MSS_HPMS_READY_int (in view: work.Top(verilog)) because it does not drive other instances.
    @N:BN362 : coreresetp.v(856) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.sm0_areset_n_rcosc (in view: work.Top(verilog)) because it does not drive other instances.
    @N:BN362 : coreresetp.v(755) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.sm0_areset_n_q1 (in view: work.Top(verilog)) because it does not drive other instances.
    @N:BN362 : coreresetp.v(755) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.sm0_areset_n_clk_base (in view: work.Top(verilog)) because it does not drive other instances.
    @N:BN362 : coreresetp.v(526) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.FIC_2_APB_M_PRESET_N_clk_base (in view: work.Top(verilog)) because it does not drive other instances.
    @N:BN362 : coreresetp.v(511) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.RESET_N_M2F_clk_base (in view: work.Top(verilog)) because it does not drive other instances.
    @N:BN362 : coreresetp.v(496) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.POWER_ON_RESET_N_clk_base (in view: work.Top(verilog)) because it does not drive other instances.
    @N:BN362 : coreresetp.v(1646) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.ddr_settled_clk_base (in view: work.Top(verilog)) because it does not drive other instances.
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.sm0_state[5] (in view: work.Top(verilog)) because it does not drive other instances.
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.sm0_state[4] (in view: work.Top(verilog)) because it does not drive other instances.
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.sm0_state[3] (in view: work.Top(verilog)) because it does not drive other instances.
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.sm0_state[2] (in view: work.Top(verilog)) because it does not drive other instances.
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.sm0_state[1] (in view: work.Top(verilog)) because it does not drive other instances.
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.sm0_state[0] (in view: work.Top(verilog)) because it does not drive other instances.
    @N:BN362 : coreresetp.v(545) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.mss_ready_state (in view: work.Top(verilog)) because it does not drive other instances.
    @N:BN362 : coreresetp.v(545) | Removing sequential instance my_mss_0.my_mss_sb_0.CORERESETP_0.mss_ready_select (in view: work.Top(verilog)) because it does not drive other instances.

    Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)

    Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:00s		     6.84ns		  30 /        28

    Added 0 Buffers
    Added 0 Cells via replication
    	Added 0 Sequential Cells via replication
    	Added 0 Combinational Cells via replication

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)

    Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)

    @S |Clock Optimization Summary

    #### START OF CLOCK OPTIMIZATION REPORT #####[

    Clock optimization not enabled
    0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    1 gated/generated clock tree(s) driving 29 clock pin(s) of sequential element(s)
    0 instances converted, 29 sequential instances remain driven by gated/generated clocks

    =========================================================================================== Gated/Generated Clocks ============================================================================================
    Clock Tree ID     Driving Element                         Drive Element Type     Fanout     Sample Instance                                         Explanation
    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    ClockId0001        my_mss_0.my_mss_sb_0.CCC_0.CCC_INST     CCC                    29         my_mss_0.my_mss_sb_0.my_mss_sb_MSS_0.MSS_ADLIB_INST     No gated clock conversion method for cell cell:work.MSS_075
    ===============================================================================================================================================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######]

    Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 136MB)

    Writing Analyst data base C:\AC407_11_8\m2s_ac407_using_nrbg_services_liberov11p7_df\Libero\M2S090_design\NRBG_M2S090TS\synthesis\synwork\Top_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 136MB)

    Writing EDIF Netlist and constraint files
    @N:FX1056 :  | Writing EDF file: C:\AC407_11_8\m2s_ac407_using_nrbg_services_liberov11p7_df\Libero\M2S090_design\NRBG_M2S090TS\synthesis\Top.edn
    @N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF
    L-2016.09M-2

    Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)

    Start final timing analysis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)

    @W:MT246 : my_mss_sb_ccc_0_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT420 :  | Found inferred clock my_mss_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:my_mss_0.my_mss_sb_0.FABOSC_0.RCOSC_25_50MHZ_CCC"
    @W:MT420 :  | Found inferred clock my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:my_mss_0.my_mss_sb_0.CCC_0.GL0_net"

    ##### START OF TIMING REPORT #####[
    # Timing Report written on Fri Mar 24 19:57:07 2017
    #

    Top view:               Top
    Requested Frequency:    100.0 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: 7.468

                                                                 Requested     Estimated     Requested     Estimated               Clock        Clock
    Starting Clock                                               Frequency     Frequency     Period        Period        Slack     Type         Group
    ---------------------------------------------------------------------------------------------------------------------------------------------------------------
    my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock                  100.0 MHz     394.9 MHz     10.000        2.532         7.468     inferred     Inferred_clkgroup_0
    my_mss_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     100.0 MHz     NA            10.000        NA            NA        inferred     Inferred_clkgroup_1
    System                                                       100.0 MHz     775.3 MHz     10.000        1.290         8.710     system       system_clkgroup
    ===============================================================================================================================================================
    @N:MT582 :  | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack

    Clock Relationships
    *******************

    Clocks                                                                                    |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                                     Ending                                       |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    System                                       my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock  |  10.000      8.710  |  No paths    -      |  No paths    -      |  No paths    -
    my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock  my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock  |  10.000      7.468  |  No paths    -      |  No paths    -      |  No paths    -
    ================================================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                               Starting                                                                          Arrival
    Instance                   Reference                                       Type     Pin     Net              Time        Slack
                               Clock
    ------------------------------------------------------------------------------------------------------------------------------
    counter28_0.cntout[24]     my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       cntout_c[24]     0.094       7.468
    counter28_0.cntout[25]     my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       cntout_c[25]     0.094       7.468
    counter28_0.cntout[26]     my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       cntout_c[26]     0.094       7.468
    counter28_0.cntout[27]     my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       cntout_c[27]     0.094       7.468
    counter28_0.cntout[0]      my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       cntout[0]        0.094       7.519
    counter28_0.cntout[1]      my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       cntout[1]        0.094       7.611
    counter28_0.cntout[2]      my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       cntout[2]        0.094       7.625
    counter28_0.cntout[3]      my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       cntout[3]        0.094       7.639
    counter28_0.cntout[4]      my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       cntout[4]        0.094       7.653
    counter28_0.cntout[5]      my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       cntout[5]        0.094       7.668
    ==============================================================================================================================

    Ending Points with Worst Slack
    ******************************

                               Starting                                                                          Required
    Instance                   Reference                                       Type     Pin     Net              Time         Slack
                               Clock
    -------------------------------------------------------------------------------------------------------------------------------
    counter28_0.cntout[24]     my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       cntout_s[24]     9.778        7.468
    counter28_0.cntout[25]     my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       cntout_s[25]     9.778        7.468
    counter28_0.cntout[26]     my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       cntout_s[26]     9.778        7.468
    counter28_0.cntout[27]     my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       cntout_s[27]     9.778        7.468
    counter28_0.cntout[23]     my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       cntout_s[23]     9.778        7.576
    counter28_0.cntout[22]     my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       cntout_s[22]     9.778        7.590
    counter28_0.cntout[21]     my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       cntout_s[21]     9.778        7.604
    counter28_0.cntout[20]     my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       cntout_s[20]     9.778        7.618
    counter28_0.cntout[19]     my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       cntout_s[19]     9.778        7.632
    counter28_0.cntout[18]     my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       cntout_s[18]     9.778        7.647
    ===============================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.778

        - Propagation time:                      2.310
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     7.468

        Number of logic level(s):                1
        Starting point:                          counter28_0.cntout[24] / Q
        Ending point:                            counter28_0.cntout[24] / D
        The start point is clocked by            my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK
        The end   point is clocked by            my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK

    Instance / Net                          Pin      Pin               Arrival     No. of
    Name                           Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------
    counter28_0.cntout[24]         SLE      Q        Out     0.094     0.094       -
    cntout_c[24]                   Net      -        -       0.977     -           2
    counter28_0.cntout_cry[24]     ARI1     B        In      -         1.071       -
    counter28_0.cntout_cry[24]     ARI1     S        Out     0.268     1.339       -
    cntout_s[24]                   Net      -        -       0.971     -           1
    counter28_0.cntout[24]         SLE      D        In      -         2.310       -
    =========================================================================================
    Total path delay (propagation time + setup) of 2.532 is 0.584(23.1%) logic and 1.948(76.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                            Starting                                                  Arrival
    Instance                                Reference     Type     Pin      Net                       Time        Slack
                                            Clock
    -------------------------------------------------------------------------------------------------------------------
    my_mss_0.my_mss_sb_0.CCC_0.CCC_INST     System        CCC      LOCK     my_mss_0_FAB_CCC_LOCK     0.000       8.710
    ===================================================================================================================

    Ending Points with Worst Slack
    ******************************

                              Starting                                                 Required
    Instance                  Reference     Type     Pin     Net                       Time         Slack
                              Clock
    -----------------------------------------------------------------------------------------------------
    counter28_0.cntout[0]     System        SLE      SLn     my_mss_0_FAB_CCC_LOCK     9.707        8.710
    counter28_0.cntout[1]     System        SLE      SLn     my_mss_0_FAB_CCC_LOCK     9.707        8.710
    counter28_0.cntout[2]     System        SLE      SLn     my_mss_0_FAB_CCC_LOCK     9.707        8.710
    counter28_0.cntout[3]     System        SLE      SLn     my_mss_0_FAB_CCC_LOCK     9.707        8.710
    counter28_0.cntout[4]     System        SLE      SLn     my_mss_0_FAB_CCC_LOCK     9.707        8.710
    counter28_0.cntout[5]     System        SLE      SLn     my_mss_0_FAB_CCC_LOCK     9.707        8.710
    counter28_0.cntout[6]     System        SLE      SLn     my_mss_0_FAB_CCC_LOCK     9.707        8.710
    counter28_0.cntout[7]     System        SLE      SLn     my_mss_0_FAB_CCC_LOCK     9.707        8.710
    counter28_0.cntout[8]     System        SLE      SLn     my_mss_0_FAB_CCC_LOCK     9.707        8.710
    counter28_0.cntout[9]     System        SLE      SLn     my_mss_0_FAB_CCC_LOCK     9.707        8.710
    =====================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            0.293
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.707

        - Propagation time:                      0.996
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 8.710

        Number of logic level(s):                0
        Starting point:                          my_mss_0.my_mss_sb_0.CCC_0.CCC_INST / LOCK
        Ending point:                            counter28_0.cntout[0] / SLn
        The start point is clocked by            System [rising]
        The end   point is clocked by            my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK

    Instance / Net                                   Pin      Pin               Arrival     No. of
    Name                                    Type     Name     Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------------
    my_mss_0.my_mss_sb_0.CCC_0.CCC_INST     CCC      LOCK     Out     0.000     0.000       -
    my_mss_0_FAB_CCC_LOCK                   Net      -        -       0.996     -           29
    counter28_0.cntout[0]                   SLE      SLn      In      -         0.996       -
    ==================================================================================================
    Total path delay (propagation time + setup) of 1.290 is 0.293(22.8%) logic and 0.996(77.2%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied
    None

    Finished final timing analysis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)

    Finished timing report (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)

    ---------------------------------------
    Resource Usage Report for Top

    Mapping to part: m2s090tsfbga484-1
    Cell usage:
    CCC             1 use
    CLKINT          1 use
    MSS_075         1 use
    RCOSC_25_50MHZ  1 use
    CFG1           1 use

    Carry cells:
    ARI1            28 uses - used for arithmetic functions

    Sequential Cells:
    SLE            28 uses

    DSP Blocks:    0 of 84 (0%)

    I/O ports: 7
    I/O primitives: 6
    INBUF          1 use
    OUTBUF         5 uses

    Global Clock Buffers: 1 of 8 (12%)

    Total LUTs:    29

    Extra resources required for RAM and MACC interface logic during P&R:

    RAM64x18 Interface Logic : SLEs = 0; LUTs = 0;
    RAM1K18  Interface Logic : SLEs = 0; LUTs = 0;
    MACC     Interface Logic : SLEs = 0; LUTs = 0;

    Total number of SLEs after P&R:  28 + 0 + 0 + 0 = 28;
    Total number of LUTs after P&R:  29 + 0 + 0 + 0 = 29;

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 28MB peak: 136MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Fri Mar 24 19:57:07 2017

    ###########################################################]

`