Project Settings
Project Name | Top_syn | Implementation Name | synthesis
Top Module | Top | Retiming | 0
Resource Sharing | 1 | Fanout Guide | 10000
Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0
Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
(compiler) | Complete | 58 | 39 | 0 | - | 00m:00s | - | 3/24/2017 7:57:04 PM
(premap) | Complete | 31 | 18 | 0 | 0m:00s | 0m:00s | 137MB | 3/24/2017 7:57:06 PM
(fpga_mapper) | Complete | 39 | 14 | 0 | 0m:00s | 0m:00s | 136MB | 3/24/2017 7:57:07 PM
Multi-srs Generator | Complete |  |  |  | 00m:01s |  |  | 3/24/2017 7:57:06 PM
Area Summary
Carry Cells | 28 | Sequential Cells | 28
DSP Blocks (MACC) (dsp_used) | 0 | I/O Cells | 6
Global Clock Buffers | 1 | LUTs (total_luts) | 29
Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
my_mss_sb_CCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | 394.9 MHz | 7.468
my_mss_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | 100.0 MHz | NA | NA
System | 100.0 MHz | 775.3 MHz | 8.710
Optimizations Summary
Combined Clock Conversion | 0 / 1 |  |