| Project Settings |
|---|
| Project Name | Disp_syn | Implementation Name | synthesis |
| Top Module | Disp | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 10000 |
| Disable I/O Insertion | 0 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
58 |
221 |
0 |
- |
0m:02s |
- |
2/22/2016
2:57:42 PM |
| (premap) | Complete |
50 |
14 |
0 |
0m:01s |
0m:01s |
148MB |
2/22/2016
2:57:45 PM |
| (fpga_mapper) | Complete |
62 |
54 |
0 |
0m:05s |
0m:05s |
148MB |
2/22/2016
2:57:51 PM |
| Multi-srs Generator |
Complete | | | | 0m:01s | | | 2/22/2016
2:57:44 PM |
| Area Summary |
|---|
| |
| Carry Cells | 14 |
Sequential Cells | 228 |
| DSP Blocks (MACC)
(dsp_used) | 0 |
I/O Cells | 56 |
| Global Clock Buffers | 7 |
Block Rams (RAM1K18)
(v_ram) | 64 |
| LUTs
(total_luts) | 299 |
| |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | 121.6 MHz | 1.776 |
| Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | 100.0 MHz | 428.6 MHz | 7.667 |
| Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock | 100.0 MHz | 154.7 MHz | 1.968 |
| Disp|SPI_1_CLK_F2M | 100.0 MHz | NA | NA |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 3 / 1 |
| |
|