#Build: Synplify Pro J-2015.03M-SP1-2, Build 266R, Dec 14 2015 #install: C:\Microsemi\Libero_SoC_v11.7\Synplify #OS: Windows 7 6.1 #Hostname: W764D-KILDAGIM #Implementation: synthesis Synopsys HDL Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Synopsys Verilog Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. @I::"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v" @I::"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\hypermods.v" @I::"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\umr_capim.v" @I::"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\scemi_objects.v" @I::"C:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\scemi_pipes.svh" @I::"E:\ftdi_disp\display_demo_src\libero\display\component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v" @I::"E:\ftdi_disp\display_demo_src\libero\display\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v" @I::"E:\ftdi_disp\display_demo_src\libero\display\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v" @I::"E:\ftdi_disp\display_demo_src\libero\display\component\work\Disp_sb\CCC_0\Disp_sb_CCC_0_FCCC.v" @I::"E:\ftdi_disp\display_demo_src\libero\display\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" @I::"E:\ftdi_disp\display_demo_src\libero\display\component\work\Disp_sb\FABOSC_0\Disp_sb_FABOSC_0_OSC.v" @I::"E:\ftdi_disp\display_demo_src\libero\display\component\work\Disp_sb_MSS\Disp_sb_MSS_syn.v" @I::"E:\ftdi_disp\display_demo_src\libero\display\component\work\Disp_sb_MSS\Disp_sb_MSS.v" @I::"E:\ftdi_disp\display_demo_src\libero\display\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v" @I::"E:\ftdi_disp\display_demo_src\libero\display\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v" @I::"E:\ftdi_disp\display_demo_src\libero\display\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v" @I::"E:\ftdi_disp\display_demo_src\libero\display\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v" @I::"E:\ftdi_disp\display_demo_src\libero\display\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v" @I::"E:\ftdi_disp\display_demo_src\libero\display\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v" @I::"E:\ftdi_disp\display_demo_src\libero\display\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v" @I::"E:\ftdi_disp\display_demo_src\libero\display\component\Actel\DirectCore\COREAHBLSRAM\2.0.113\rtl\vlog\core\AHBLSramIf.v" @I::"E:\ftdi_disp\display_demo_src\libero\display\component\work\Disp_sb\COREAHBLSRAM_0_0\rtl\vlog\core\lsram_2048to139264x8.v" @I::"E:\ftdi_disp\display_demo_src\libero\display\component\work\Disp_sb\COREAHBLSRAM_0_0\rtl\vlog\core\usram_128to9216x8.v" @I::"E:\ftdi_disp\display_demo_src\libero\display\component\work\Disp_sb\COREAHBLSRAM_0_0\rtl\vlog\core\SramCtrlIf.v" @I::"E:\ftdi_disp\display_demo_src\libero\display\component\work\Disp_sb\COREAHBLSRAM_0_0\rtl\vlog\core\CoreAHBLSRAM.v" @I::"E:\ftdi_disp\display_demo_src\libero\display\component\work\Disp_sb\Disp_sb.v" @I::"E:\ftdi_disp\display_demo_src\libero\display\component\work\Disp\Disp.v" Verilog syntax check successful! Selecting top level module Disp @N:CG364 : smartfusion2.v(376) | Synthesizing module VCC @N:CG364 : smartfusion2.v(372) | Synthesizing module GND @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT @N:CG364 : smartfusion2.v(727) | Synthesizing module CCC @N:CG364 : Disp_sb_CCC_0_FCCC.v(5) | Synthesizing module Disp_sb_CCC_0_FCCC @W:CG775 : coreahblite.v(23) | Found Component CoreAHBLite in library COREAHBLITE_LIB @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000001 MSB_ADDR=32'b00000000000000000000000000011011 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z1 @N:CG364 : coreahblite_defaultslavesm.v(20) | Synthesizing module COREAHBLITE_DEFAULTSLAVESM SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 HRESPEXTEND=1'b1 Generated name = COREAHBLITE_DEFAULTSLAVESM_0s_0_1 @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000001 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_2_1_0_1_0s_0_1_0 @N:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000000 MSB_ADDR=32'b00000000000000000000000000011011 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z2 @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_2_1_0_0_0s_0_1_0 @N:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. @N:CG364 : coreahblite_slavearbiter.v(20) | Synthesizing module COREAHBLITE_SLAVEARBITER SYNC_RESET=32'b00000000000000000000000000000000 M0EXTEND=4'b0000 M0DONE=4'b0001 M0LOCK=4'b0010 M0LOCKEXTEND=4'b0011 M1EXTEND=4'b0100 M1DONE=4'b0101 M1LOCK=4'b0110 M1LOCKEXTEND=4'b0111 M2EXTEND=4'b1000 M2DONE=4'b1001 M2LOCK=4'b1010 M2LOCKEXTEND=4'b1011 M3EXTEND=4'b1100 M3DONE=4'b1101 M3LOCK=4'b1110 M3LOCKEXTEND=4'b1111 MASTER_0=4'b0001 MASTER_1=4'b0010 MASTER_2=4'b0100 MASTER_3=4'b1000 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVEARBITER_Z3 @N:CG364 : coreahblite_slavestage.v(22) | Synthesizing module COREAHBLITE_SLAVESTAGE SYNC_RESET=32'b00000000000000000000000000000000 TRN_IDLE=1'b0 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVESTAGE_0s_0_0 @N:CG364 : coreahblite_matrix4x16.v(23) | Synthesizing module COREAHBLITE_MATRIX4X16 MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M0_AHBSLOTENABLE=17'b00000000000000001 M1_AHBSLOTENABLE=17'b00000000000000000 M2_AHBSLOTENABLE=17'b00000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = COREAHBLITE_MATRIX4X16_2_1_0_1_0_0_0_0s @N:CG364 : coreahblite.v(23) | Synthesizing module CoreAHBLite FAMILY=6'b010011 MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC_0=1'b0 SC_1=1'b0 SC_2=1'b0 SC_3=1'b0 SC_4=1'b0 SC_5=1'b0 SC_6=1'b0 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 M0_AHBSLOT0ENABLE=1'b1 M0_AHBSLOT1ENABLE=1'b0 M0_AHBSLOT2ENABLE=1'b0 M0_AHBSLOT3ENABLE=1'b0 M0_AHBSLOT4ENABLE=1'b0 M0_AHBSLOT5ENABLE=1'b0 M0_AHBSLOT6ENABLE=1'b0 M0_AHBSLOT7ENABLE=1'b0 M0_AHBSLOT8ENABLE=1'b0 M0_AHBSLOT9ENABLE=1'b0 M0_AHBSLOT10ENABLE=1'b0 M0_AHBSLOT11ENABLE=1'b0 M0_AHBSLOT12ENABLE=1'b0 M0_AHBSLOT13ENABLE=1'b0 M0_AHBSLOT14ENABLE=1'b0 M0_AHBSLOT15ENABLE=1'b0 M0_AHBSLOT16ENABLE=1'b0 M1_AHBSLOT0ENABLE=1'b0 M1_AHBSLOT1ENABLE=1'b0 M1_AHBSLOT2ENABLE=1'b0 M1_AHBSLOT3ENABLE=1'b0 M1_AHBSLOT4ENABLE=1'b0 M1_AHBSLOT5ENABLE=1'b0 M1_AHBSLOT6ENABLE=1'b0 M1_AHBSLOT7ENABLE=1'b0 M1_AHBSLOT8ENABLE=1'b0 M1_AHBSLOT9ENABLE=1'b0 M1_AHBSLOT10ENABLE=1'b0 M1_AHBSLOT11ENABLE=1'b0 M1_AHBSLOT12ENABLE=1'b0 M1_AHBSLOT13ENABLE=1'b0 M1_AHBSLOT14ENABLE=1'b0 M1_AHBSLOT15ENABLE=1'b0 M1_AHBSLOT16ENABLE=1'b0 M2_AHBSLOT0ENABLE=1'b0 M2_AHBSLOT1ENABLE=1'b0 M2_AHBSLOT2ENABLE=1'b0 M2_AHBSLOT3ENABLE=1'b0 M2_AHBSLOT4ENABLE=1'b0 M2_AHBSLOT5ENABLE=1'b0 M2_AHBSLOT6ENABLE=1'b0 M2_AHBSLOT7ENABLE=1'b0 M2_AHBSLOT8ENABLE=1'b0 M2_AHBSLOT9ENABLE=1'b0 M2_AHBSLOT10ENABLE=1'b0 M2_AHBSLOT11ENABLE=1'b0 M2_AHBSLOT12ENABLE=1'b0 M2_AHBSLOT13ENABLE=1'b0 M2_AHBSLOT14ENABLE=1'b0 M2_AHBSLOT15ENABLE=1'b0 M2_AHBSLOT16ENABLE=1'b0 M3_AHBSLOT0ENABLE=1'b0 M3_AHBSLOT1ENABLE=1'b0 M3_AHBSLOT2ENABLE=1'b0 M3_AHBSLOT3ENABLE=1'b0 M3_AHBSLOT4ENABLE=1'b0 M3_AHBSLOT5ENABLE=1'b0 M3_AHBSLOT6ENABLE=1'b0 M3_AHBSLOT7ENABLE=1'b0 M3_AHBSLOT8ENABLE=1'b0 M3_AHBSLOT9ENABLE=1'b0 M3_AHBSLOT10ENABLE=1'b0 M3_AHBSLOT11ENABLE=1'b0 M3_AHBSLOT12ENABLE=1'b0 M3_AHBSLOT13ENABLE=1'b0 M3_AHBSLOT14ENABLE=1'b0 M3_AHBSLOT15ENABLE=1'b0 M3_AHBSLOT16ENABLE=1'b0 SYNC_RESET=32'b00000000000000000000000000000000 M0_AHBSLOTENABLE=17'b00000000000000001 M1_AHBSLOTENABLE=17'b00000000000000000 M2_AHBSLOTENABLE=17'b00000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SC=16'b0000000000000000 Generated name = CoreAHBLite_Z4 @W:CG775 : CoreAHBLSRAM.v(29) | Found Component Disp_sb_COREAHBLSRAM_0_0_COREAHBLSRAM in library COREAHBLSRAM_LIB @N:CG364 : AHBLSramIf.v(29) | Synthesizing module AHBLSramIf @W:CL169 : AHBLSramIf.v(161) | Pruning register HWDATA_d[31:0] @W:CL169 : AHBLSramIf.v(161) | Pruning register HTRANS_d[1:0] @W:CL169 : AHBLSramIf.v(161) | Pruning register HSEL_d @W:CL169 : AHBLSramIf.v(161) | Pruning register HREADYIN_d @N:CG364 : SramCtrlIf.v(29) | Synthesizing module Disp_sb_COREAHBLSRAM_0_0_SramCtrlIf SEL_SRAM_TYPE=32'b00000000000000000000000000000000 LSRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000001000000000000000 USRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000000000001000000000 AHB_DWIDTH=32'b00000000000000000000000000100000 S_IDLE=2'b00 S_WR=2'b01 S_RD=2'b10 Generated name = Disp_sb_COREAHBLSRAM_0_0_SramCtrlIf_0s_32768s_512s_32s_0_1_2 @N:CG364 : smartfusion2.v(382) | Synthesizing module RAM1K18 @N:CG364 : lsram_2048to139264x8.v(28) | Synthesizing module Disp_sb_COREAHBLSRAM_0_0_lsram_2048to139264x8 DEPTH=32'b00000000000000001000000000000000 AHB_DWIDTH=32'b00000000000000000000000000001000 Generated name = Disp_sb_COREAHBLSRAM_0_0_lsram_2048to139264x8_32768s_8s @W:CL265 : lsram_2048to139264x8.v(229) | Pruning bit 15 of ckRdAddr[15:9] -- not in use ... @W:CL265 : lsram_2048to139264x8.v(229) | Pruning bit 9 of ckRdAddr[15:9] -- not in use ... @W:CL279 : lsram_2048to139264x8.v(229) | Pruning register bits 13 to 10 of ckRdAddr[14:10] @N:CG179 : SramCtrlIf.v(381) | Removing redundant assignment @W:CG133 : SramCtrlIf.v(95) | No assignment to ahbsram_wdata_upd_r @W:CG133 : SramCtrlIf.v(96) | No assignment to u_ahbsram_wdata_upd_r @W:CG360 : SramCtrlIf.v(103) | No assignment to wire u_BUSY_all_0 @W:CG360 : SramCtrlIf.v(104) | No assignment to wire u_BUSY_all_1 @W:CG360 : SramCtrlIf.v(105) | No assignment to wire u_BUSY_all_2 @W:CG360 : SramCtrlIf.v(106) | No assignment to wire u_BUSY_all_3 @W:CG360 : SramCtrlIf.v(113) | No assignment to wire u_ahbsram_wdata_upd @N:CG364 : CoreAHBLSRAM.v(29) | Synthesizing module Disp_sb_COREAHBLSRAM_0_0_COREAHBLSRAM FAMILY=32'b00000000000000000000000000010011 AHB_DWIDTH=32'b00000000000000000000000000100000 AHB_AWIDTH=32'b00000000000000000000000000100000 LSRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000001000000000000000 USRAM_NUM_LOCATIONS_DWIDTH32=32'b00000000000000000000001000000000 SEL_SRAM_TYPE=32'b00000000000000000000000000000000 Generated name = Disp_sb_COREAHBLSRAM_0_0_COREAHBLSRAM_19s_32s_32s_32768s_512s_0s @N:CG364 : coreconfigp.v(22) | Synthesizing module CoreConfigP FAMILY=32'b00000000000000000000000000010011 MDDR_IN_USE=32'b00000000000000000000000000000001 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000001 VERSION_MAJOR=32'b00000000000000000000000000000111 VERSION_MINOR=32'b00000000000000000000000000000000 VERSION_MAJOR_VECTOR=16'b0000000000000111 VERSION_MINOR_VECTOR=16'b0000000000000000 S0=2'b00 S1=2'b01 S2=2'b10 Generated name = CoreConfigP_Z5 @W:CL207 : coreconfigp.v(461) | All reachable assignments to SDIF1_PENABLE assign 0, register removed by optimization. @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000001 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000001 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z6 @W:CL169 : coreresetp.v(1581) | Pruning register count_sdif3[12:0] @W:CL169 : coreresetp.v(1549) | Pruning register count_sdif2[12:0] @W:CL169 : coreresetp.v(1517) | Pruning register count_sdif1[12:0] @W:CL169 : coreresetp.v(1485) | Pruning register count_sdif0[12:0] @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif0_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif0_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_rcosc @W:CL169 : coreresetp.v(1365) | Pruning register count_sdif3_enable @W:CL169 : coreresetp.v(1300) | Pruning register count_sdif2_enable @W:CL169 : coreresetp.v(1235) | Pruning register count_sdif1_enable @W:CL169 : coreresetp.v(1170) | Pruning register count_sdif0_enable @N:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0 @W:CL169 : coreresetp.v(1089) | Pruning register release_ext_reset @W:CL169 : coreresetp.v(1433) | Pruning register EXT_RESET_OUT_int @W:CL169 : coreresetp.v(1433) | Pruning register sm2_state[2:0] @W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_q1 @W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_clk_base @N:CG364 : smartfusion2.v(286) | Synthesizing module BIBUF @N:CG364 : smartfusion2.v(274) | Synthesizing module OUTBUF @N:CG364 : smartfusion2.v(326) | Synthesizing module OUTBUF_DIFF @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF @N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF @N:CG364 : Disp_sb_MSS_syn.v(5) | Synthesizing module MSS_075 @N:CG364 : Disp_sb_MSS.v(9) | Synthesizing module Disp_sb_MSS @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ @N:CG364 : Disp_sb_FABOSC_0_OSC.v(5) | Synthesizing module Disp_sb_FABOSC_0_OSC @N:CG364 : smartfusion2.v(718) | Synthesizing module SYSRESET @N:CG364 : Disp_sb.v(9) | Synthesizing module Disp_sb @N:CG364 : Disp.v(9) | Synthesizing module Disp @W:CL157 : Disp_sb_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : Disp_sb_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible. @W:CL157 : Disp_sb_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : Disp_sb_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits -- simulation mismatch possible. @W:CL159 : Disp_sb_FABOSC_0_OSC.v(14) | Input XTL is unused @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @W:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused @W:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused @W:CL159 : coreresetp.v(59) | Input SDIF0_SPLL_LOCK is unused @W:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused @W:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused @W:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused @W:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused @W:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused @W:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused @W:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused @W:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused @W:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused @W:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused @W:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused @W:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused @W:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused @W:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused @W:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused @N:CL201 : coreconfigp.v(447) | Trying to extract state machine for register state Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL159 : coreconfigp.v(71) | Input SDIF1_PREADY is unused @W:CL159 : coreconfigp.v(72) | Input SDIF1_PSLVERR is unused @W:CL246 : CoreAHBLSRAM.v(68) | Input port bits 31 to 20 of HADDR[31:0] are unused @W:CL247 : lsram_2048to139264x8.v(61) | Input port bit 15 of writeAddr[15:0] is unused @W:CL247 : lsram_2048to139264x8.v(62) | Input port bit 15 of readAddr[15:0] is unused @W:CL246 : lsram_2048to139264x8.v(62) | Input port bits 13 to 0 of readAddr[15:0] are unused @W:CL159 : lsram_2048to139264x8.v(60) | Input ren is unused @N:CL201 : SramCtrlIf.v(127) | Trying to extract state machine for register sramcurr_state Extracted state machine for register sramcurr_state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL246 : SramCtrlIf.v(72) | Input port bits 19 to 18 of ahbsram_addr[19:0] are unused @N:CL201 : AHBLSramIf.v(185) | Trying to extract state machine for register ahbcurr_state Extracted state machine for register ahbcurr_state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL159 : AHBLSramIf.v(97) | Input BUSY is unused @W:CL247 : coreahblite.v(120) | Input port bit 0 of HTRANS_M0[1:0] is unused @W:CL247 : coreahblite.v(131) | Input port bit 0 of HTRANS_M1[1:0] is unused @W:CL247 : coreahblite.v(142) | Input port bit 0 of HTRANS_M2[1:0] is unused @W:CL247 : coreahblite.v(153) | Input port bit 0 of HTRANS_M3[1:0] is unused @W:CL247 : coreahblite.v(163) | Input port bit 1 of HRESP_S0[1:0] is unused @W:CL247 : coreahblite.v(176) | Input port bit 1 of HRESP_S1[1:0] is unused @W:CL247 : coreahblite.v(189) | Input port bit 1 of HRESP_S2[1:0] is unused @W:CL247 : coreahblite.v(202) | Input port bit 1 of HRESP_S3[1:0] is unused @W:CL247 : coreahblite.v(215) | Input port bit 1 of HRESP_S4[1:0] is unused @W:CL247 : coreahblite.v(228) | Input port bit 1 of HRESP_S5[1:0] is unused @W:CL247 : coreahblite.v(241) | Input port bit 1 of HRESP_S6[1:0] is unused @W:CL247 : coreahblite.v(254) | Input port bit 1 of HRESP_S7[1:0] is unused @W:CL247 : coreahblite.v(267) | Input port bit 1 of HRESP_S8[1:0] is unused @W:CL247 : coreahblite.v(280) | Input port bit 1 of HRESP_S9[1:0] is unused @W:CL247 : coreahblite.v(293) | Input port bit 1 of HRESP_S10[1:0] is unused @W:CL247 : coreahblite.v(306) | Input port bit 1 of HRESP_S11[1:0] is unused @W:CL247 : coreahblite.v(319) | Input port bit 1 of HRESP_S12[1:0] is unused @W:CL247 : coreahblite.v(332) | Input port bit 1 of HRESP_S13[1:0] is unused @W:CL247 : coreahblite.v(345) | Input port bit 1 of HRESP_S14[1:0] is unused @W:CL247 : coreahblite.v(358) | Input port bit 1 of HRESP_S15[1:0] is unused @W:CL247 : coreahblite.v(371) | Input port bit 1 of HRESP_S16[1:0] is unused @W:CL159 : coreahblite.v(123) | Input HBURST_M0 is unused @W:CL159 : coreahblite.v(124) | Input HPROT_M0 is unused @W:CL159 : coreahblite.v(134) | Input HBURST_M1 is unused @W:CL159 : coreahblite.v(135) | Input HPROT_M1 is unused @W:CL159 : coreahblite.v(145) | Input HBURST_M2 is unused @W:CL159 : coreahblite.v(146) | Input HPROT_M2 is unused @W:CL159 : coreahblite.v(156) | Input HBURST_M3 is unused @W:CL159 : coreahblite.v(157) | Input HPROT_M3 is unused @W:CL159 : coreahblite_matrix4x16.v(51) | Input HWDATA_M1 is unused @W:CL159 : coreahblite_matrix4x16.v(60) | Input HWDATA_M2 is unused @W:CL159 : coreahblite_matrix4x16.v(69) | Input HWDATA_M3 is unused @W:CL159 : coreahblite_matrix4x16.v(84) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_matrix4x16.v(85) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_matrix4x16.v(86) | Input HRESP_S1 is unused @W:CL159 : coreahblite_matrix4x16.v(95) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_matrix4x16.v(96) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_matrix4x16.v(97) | Input HRESP_S2 is unused @W:CL159 : coreahblite_matrix4x16.v(106) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_matrix4x16.v(107) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_matrix4x16.v(108) | Input HRESP_S3 is unused @W:CL159 : coreahblite_matrix4x16.v(117) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_matrix4x16.v(118) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_matrix4x16.v(119) | Input HRESP_S4 is unused @W:CL159 : coreahblite_matrix4x16.v(128) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(129) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(130) | Input HRESP_S5 is unused @W:CL159 : coreahblite_matrix4x16.v(139) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(140) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(141) | Input HRESP_S6 is unused @W:CL159 : coreahblite_matrix4x16.v(150) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(151) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(152) | Input HRESP_S7 is unused @W:CL159 : coreahblite_matrix4x16.v(161) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(162) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(163) | Input HRESP_S8 is unused @W:CL159 : coreahblite_matrix4x16.v(172) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(173) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(174) | Input HRESP_S9 is unused @W:CL159 : coreahblite_matrix4x16.v(183) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(184) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(185) | Input HRESP_S10 is unused @W:CL159 : coreahblite_matrix4x16.v(194) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(195) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(196) | Input HRESP_S11 is unused @W:CL159 : coreahblite_matrix4x16.v(205) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(206) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(207) | Input HRESP_S12 is unused @W:CL159 : coreahblite_matrix4x16.v(216) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(217) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(218) | Input HRESP_S13 is unused @W:CL159 : coreahblite_matrix4x16.v(227) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(228) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(229) | Input HRESP_S14 is unused @W:CL159 : coreahblite_matrix4x16.v(238) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_matrix4x16.v(239) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_matrix4x16.v(240) | Input HRESP_S15 is unused @W:CL159 : coreahblite_matrix4x16.v(249) | Input HRDATA_S16 is unused @W:CL159 : coreahblite_matrix4x16.v(250) | Input HREADYOUT_S16 is unused @W:CL159 : coreahblite_matrix4x16.v(251) | Input HRESP_S16 is unused @N:CL201 : coreahblite_slavearbiter.v(449) | Trying to extract state machine for register arbRegSMCurrentState Extracted state machine for register arbRegSMCurrentState State machine has 16 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 @W:CL159 : coreahblite_masterstage.v(42) | Input SDATAREADY is unused @W:CL159 : coreahblite_masterstage.v(43) | Input SHRESP is unused @W:CL159 : coreahblite_masterstage.v(52) | Input HRDATA_S0 is unused @W:CL159 : coreahblite_masterstage.v(53) | Input HREADYOUT_S0 is unused @W:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S16 is unused @W:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S16 is unused @W:CL246 : coreahblite_masterstage.v(42) | Input port bits 16 to 1 of SDATAREADY[16:0] are unused @W:CL246 : coreahblite_masterstage.v(43) | Input port bits 16 to 1 of SHRESP[16:0] are unused @W:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused @W:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused @W:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S2 is unused @W:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S2 is unused @W:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S3 is unused @W:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S3 is unused @W:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused @W:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused @W:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S5 is unused @W:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S5 is unused @W:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused @W:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused @W:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused @W:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused @W:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused @W:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused @W:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused @W:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused @W:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused @W:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused @W:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused @W:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused @W:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused @W:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S12 is unused @W:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S13 is unused @W:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S13 is unused @W:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S14 is unused @W:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S14 is unused @W:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S15 is unused @W:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S15 is unused @W:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S16 is unused @W:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S16 is unused At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 98MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Feb 22 14:57:41 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 77MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Feb 22 14:57:42 2016 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Feb 22 14:57:42 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode File C:\Microsemi\Libero_v11.5\Synopsys\synplify_I201403MSP1\bin64\syn_nfilter.exe changed - recompiling File G:\ftdi_disp\display\synthesis\synwork\Disp_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 82MB peak: 83MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Feb 22 14:57:44 2016 ###########################################################] Pre-mapping Report Synopsys Generic Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) Linked File: Disp_scck.rpt Printing clock summary report in "E:\ftdi_disp\display_demo_src\libero\display\synthesis\Disp_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 116MB peak: 119MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 116MB peak: 119MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 119MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 120MB) @W:BN132 : coreahblite_matrix4x16.v(3626) | Removing user instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_16, because it is equivalent to instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_15 @W:BN132 : coreahblite_matrix4x16.v(3580) | Removing user instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_15, because it is equivalent to instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_14 @W:BN132 : coreahblite_matrix4x16.v(3534) | Removing user instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_14, because it is equivalent to instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_13 @W:BN132 : coreahblite_matrix4x16.v(3488) | Removing user instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_13, because it is equivalent to instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_12 @W:BN132 : coreahblite_matrix4x16.v(3442) | Removing user instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_12, because it is equivalent to instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_11 @W:BN132 : coreahblite_matrix4x16.v(3396) | Removing user instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_11, because it is equivalent to instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3304) | Removing user instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_9, because it is equivalent to instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3258) | Removing user instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_8, because it is equivalent to instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3212) | Removing user instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_7, because it is equivalent to instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10 @W:BN132 : coreahblite_matrix4x16.v(3166) | Removing user instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_6, because it is equivalent to instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10 @N:BN362 : coreconfigp.v(461) | Removing sequential instance FDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF0_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF2_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF3_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_RELEASED_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_2(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_2(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_2(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_1(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_1(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_1(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_0(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_0(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_0(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2703) | Removing instance masterstage_1 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_2(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2767) | Removing instance masterstage_2 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_1(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2831) | Removing instance masterstage_3 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_0(verilog) because there are no references to its outputs @N:BN115 : coreahblite_matrix4x16.v(2936) | Removing instance slavestage_1 of view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_0(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1170) | Removing sequential instance sdif0_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2708) | Removing sequential instance block16 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Disp_sb_COREAHBLSRAM_0_0_lsram_2048to139264x8_32768s_8s_0(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2708) | Removing sequential instance block16 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Disp_sb_COREAHBLSRAM_0_0_lsram_2048to139264x8_32768s_8s_1(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2708) | Removing sequential instance block16 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Disp_sb_COREAHBLSRAM_0_0_lsram_2048to139264x8_32768s_8s_2(verilog) because there are no references to its outputs @N:BN362 : lsram_2048to139264x8.v(2708) | Removing sequential instance block16 of view:ACG4.RAM1K18(PRIM) in hierarchy view:COREAHBLSRAM_LIB.Disp_sb_COREAHBLSRAM_0_0_lsram_2048to139264x8_32768s_8s_3(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[3:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_0(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z6(verilog) because there are no references to its outputs @N:BN115 : coreahblite_slavestage.v(87) | Removing instance slave_arbiter of view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3_1(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance arbRegSMCurrentState[15:0] of view:PrimLib.statemachine(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3_1(verilog) because there are no references to its outputs syn_allowed_resources : blockrams=109 set on top level netlist Disp Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 147MB peak: 148MB) @S |Clock Summary ***************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ----------------------------------------------------------------------------------------------------------------------- Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_1 Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_3 Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 Disp|SPI_1_CLK_F2M 100.0 MHz 10.000 inferred Inferred_clkgroup_2 ======================================================================================================================= @W:MT530 : coreconfigp.v(546) | Found inferred clock Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock which controls 110 sequential elements including Disp_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[31:0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coreahblite_defaultslavesm.v(64) | Found inferred clock Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock which controls 207 sequential elements including Disp_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.default_slave_sm.defSlaveSMCurrentState. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : disp_sb_mss.v(1158) | Found inferred clock Disp|SPI_1_CLK_F2M which controls 0 sequential elements including Disp_sb_0.Disp_sb_MSS_0.MSS_ADLIB_INST. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coreresetp.v(1613) | Found inferred clock Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 31 sequential elements including Disp_sb_0.CORERESETP_0.count_ddr[13:0]. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file E:\ftdi_disp\display_demo_src\libero\display\synthesis\Disp.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 78MB peak: 148MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Mon Feb 22 14:57:45 2016 ###########################################################] Map & Optimize Report Synopsys Generic Technology Mapper, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 140MB) @W:MO111 : disp_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module Disp_sb_FABOSC_0_OSC) @W:MO111 : disp_sb_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module Disp_sb_FABOSC_0_OSC) @W:MO111 : disp_sb_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module Disp_sb_FABOSC_0_OSC) @W:MO111 : disp_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module Disp_sb_FABOSC_0_OSC) @W:MO171 : coreresetp.v(676) | Sequential instance Disp_sb_0.CORERESETP_0.SDIF0_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(695) | Sequential instance Disp_sb_0.CORERESETP_0.SDIF1_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance Disp_sb_0.CORERESETP_0.SDIF2_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance Disp_sb_0.CORERESETP_0.SDIF3_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(676) | Sequential instance Disp_sb_0.CORERESETP_0.SDIF0_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(695) | Sequential instance Disp_sb_0.CORERESETP_0.SDIF1_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance Disp_sb_0.CORERESETP_0.SDIF2_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance Disp_sb_0.CORERESETP_0.SDIF3_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(676) | Sequential instance Disp_sb_0.CORERESETP_0.SDIF0_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(695) | Sequential instance Disp_sb_0.CORERESETP_0.SDIF1_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance Disp_sb_0.CORERESETP_0.SDIF2_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance Disp_sb_0.CORERESETP_0.SDIF3_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreconfigp.v(583) | Sequential instance Disp_sb_0.CORECONFIGP_0.SDIF_RELEASED_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(769) | Sequential instance Disp_sb_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(769) | Sequential instance Disp_sb_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(1388) | Sequential instance Disp_sb_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation @W:BN132 : lsram_2048to139264x8.v(229) | Removing sequential instance Disp_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1.byte_3.ckRdAddr[14], because it is equivalent to instance Disp_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1.byte_2.ckRdAddr[14] @W:BN132 : lsram_2048to139264x8.v(229) | Removing sequential instance Disp_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1.byte_2.ckRdAddr[14], because it is equivalent to instance Disp_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1.byte_1.ckRdAddr[14] @W:BN132 : lsram_2048to139264x8.v(229) | Removing sequential instance Disp_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1.byte_1.ckRdAddr[14], because it is equivalent to instance Disp_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1.byte_0.ckRdAddr[14] @W:BN132 : coreresetp.v(898) | Removing sequential instance Disp_sb_0.CORERESETP_0.sdif2_areset_n_rcosc_q1, because it is equivalent to instance Disp_sb_0.CORERESETP_0.sm0_areset_n_rcosc_q1 @W:BN132 : coreresetp.v(912) | Removing sequential instance Disp_sb_0.CORERESETP_0.sdif3_areset_n_rcosc_q1, because it is equivalent to instance Disp_sb_0.CORERESETP_0.sm0_areset_n_rcosc_q1 @W:BN132 : coreresetp.v(884) | Removing sequential instance Disp_sb_0.CORERESETP_0.sdif1_areset_n_rcosc_q1, because it is equivalent to instance Disp_sb_0.CORERESETP_0.sm0_areset_n_rcosc_q1 @W:BN132 : coreresetp.v(870) | Removing sequential instance Disp_sb_0.CORERESETP_0.sdif0_areset_n_rcosc_q1, because it is equivalent to instance Disp_sb_0.CORERESETP_0.sm0_areset_n_rcosc_q1 @W:BN132 : coreresetp.v(884) | Removing sequential instance Disp_sb_0.CORERESETP_0.sdif1_areset_n_rcosc, because it is equivalent to instance Disp_sb_0.CORERESETP_0.sdif0_areset_n_rcosc @W:BN132 : coreresetp.v(912) | Removing sequential instance Disp_sb_0.CORERESETP_0.sdif3_areset_n_rcosc, because it is equivalent to instance Disp_sb_0.CORERESETP_0.sdif0_areset_n_rcosc @W:BN132 : coreresetp.v(898) | Removing sequential instance Disp_sb_0.CORERESETP_0.sdif2_areset_n_rcosc, because it is equivalent to instance Disp_sb_0.CORERESETP_0.sdif0_areset_n_rcosc Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[20] of view:PrimLib.dffr(prim) in hierarchy view:work.Disp_sb(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[21] of view:PrimLib.dffr(prim) in hierarchy view:work.Disp_sb(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[22] of view:PrimLib.dffr(prim) in hierarchy view:work.Disp_sb(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[23] of view:PrimLib.dffr(prim) in hierarchy view:work.Disp_sb(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28] of view:PrimLib.dffr(prim) in hierarchy view:work.Disp_sb(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[29] of view:PrimLib.dffr(prim) in hierarchy view:work.Disp_sb(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[30] of view:PrimLib.dffr(prim) in hierarchy view:work.Disp_sb(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[31] of view:PrimLib.dffr(prim) in hierarchy view:work.Disp_sb(verilog) because there are no references to its outputs @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] is always 0, optimizing ... @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[16] is always 0, optimizing ... @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_0.masterDataInProg[3] of view:PrimLib.dffr(prim) in hierarchy view:work.Disp_sb(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_0.masterDataInProg[2] of view:PrimLib.dffr(prim) in hierarchy view:work.Disp_sb(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_0.masterDataInProg[1] of view:PrimLib.dffr(prim) in hierarchy view:work.Disp_sb(verilog) because there are no references to its outputs Encoding state machine arbRegSMCurrentState[15:0] (view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3_0(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[12] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[8] is always 0, optimizing ... @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[4] is always 0, optimizing ... Encoding state machine ahbcurr_state[2:0] (view:COREAHBLSRAM_LIB.AHBLSramIf(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:BN362 : ahblsramif.v(161) | Removing sequential instance HADDR_d[17] of view:PrimLib.dffr(prim) in hierarchy view:COREAHBLSRAM_LIB.AHBLSramIf(verilog) because there are no references to its outputs @N:BN362 : ahblsramif.v(161) | Removing sequential instance HADDR_d[18] of view:PrimLib.dffr(prim) in hierarchy view:COREAHBLSRAM_LIB.AHBLSramIf(verilog) because there are no references to its outputs @N:BN362 : ahblsramif.v(161) | Removing sequential instance HADDR_d[19] of view:PrimLib.dffr(prim) in hierarchy view:COREAHBLSRAM_LIB.AHBLSramIf(verilog) because there are no references to its outputs Encoding state machine sramcurr_state[2:0] (view:COREAHBLSRAM_LIB.Disp_sb_COREAHBLSRAM_0_0_SramCtrlIf_0s_32768s_512s_32s_0_1_2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine state[2:0] (view:work.CoreConfigP_Z5(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[16] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[17] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[18] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[19] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[20] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[21] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[22] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[23] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[24] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[25] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[26] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[27] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[28] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[29] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[30] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[31] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @N:BN362 : coreconfigp.v(255) | Removing sequential instance paddr[11] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs @W:MO160 : coreconfigp.v(255) | Register bit paddr[16] is always 0, optimizing ... @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[31] is always 0, optimizing ... @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[30] is always 0, optimizing ... @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[29] is always 0, optimizing ... @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[28] is always 0, optimizing ... @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[27] is always 0, optimizing ... @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[26] is always 0, optimizing ... @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[25] is always 0, optimizing ... @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[24] is always 0, optimizing ... @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[23] is always 0, optimizing ... @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[22] is always 0, optimizing ... @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[21] is always 0, optimizing ... @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[20] is always 0, optimizing ... @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[19] is always 0, optimizing ... @N:BN362 : coreconfigp.v(255) | Removing sequential instance paddr[14] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs Encoding state machine sm0_state[6:0] (view:work.CoreResetP_Z6(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 @N: : coreresetp.v(1613) | Found counter in view:work.CoreResetP_Z6(verilog) inst count_ddr[13:0] Auto Dissolve of Disp_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf (inst of view:COREAHBLSRAM_LIB.Disp_sb_COREAHBLSRAM_0_0_SramCtrlIf_0s_32768s_512s_32s_0_1_2(verilog)) @N:BN362 : coreresetp.v(1089) | Removing sequential instance Disp_sb_0.CORERESETP_0.DDR_READY_int in hierarchy view:work.Disp(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance Disp_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[19] in hierarchy view:work.Disp(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance Disp_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[18] in hierarchy view:work.Disp(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance Disp_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[17] in hierarchy view:work.Disp(verilog) because there are no references to its outputs @N:BN362 : ahblsramif.v(161) | Removing sequential instance Disp_sb_0.COREAHBLSRAM_0_0.U_AHBLSramIf.HSIZE_d[2] in hierarchy view:work.Disp(verilog) because there are no references to its outputs @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance Disp_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[24] in hierarchy view:work.Disp(verilog) because there are no references to its outputs Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 143MB) @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[14] in hierarchy view:work.Disp(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[15] in hierarchy view:work.Disp(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[2] in hierarchy view:work.Disp(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[3] in hierarchy view:work.Disp(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[6] in hierarchy view:work.Disp(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[7] in hierarchy view:work.Disp(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[10] in hierarchy view:work.Disp(verilog) because there are no references to its outputs @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[11] in hierarchy view:work.Disp(verilog) because there are no references to its outputs Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 143MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 143MB) @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[5] in hierarchy view:work.Disp(verilog) because there are no references to its outputs Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 140MB peak: 143MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 141MB peak: 143MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 140MB peak: 143MB) Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 141MB peak: 143MB) Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 145MB peak: 148MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:02s 1.03ns 326 / 228 2 0h:00m:02s 1.03ns 324 / 228 @N:FP130 : | Promoting Net un1_Disp_sb_0_2 on CLKINT I_211 @N:FP130 : | Promoting Net Disp_sb_0.CORECONFIGP_0_APB_S_PRESET_N on CLKINT I_212 @N:FP130 : | Promoting Net Disp_sb_0.CORECONFIGP_0_APB_S_PCLK on CLKINT I_213 @N:FP130 : | Promoting Net Disp_sb_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT I_214 @N:FP130 : | Promoting Net Disp_sb_0.CORERESETP_0.sm0_areset_n_rcosc on CLKINT I_215 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 145MB peak: 148MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 146MB peak: 148MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 3 non-gated/non-generated clock tree(s) driving 284 clock pin(s) of sequential element(s) 1 gated/generated clock tree(s) driving 75 clock pin(s) of sequential element(s) 0 instances converted, 75 sequential instances remain driven by gated/generated clocks ====================================================== Non-Gated/Non-Generated Clocks ======================================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------------------------------------------------------------- ClockId0002 SPI_1_CLK_F2M port 1 Disp_sb_0.Disp_sb_MSS_0.MSS_ADLIB_INST ClockId0003 Disp_sb_0.CCC_0.GL0_INST CLKINT 263 Disp_sb_0.Disp_sb_MSS_0.MSS_ADLIB_INST ClockId0004 Disp_sb_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB_CLKINT CLKINT 20 Disp_sb_0.CORERESETP_0.count_ddr[13] ============================================================================================================================================= ====================================================================================== Gated/Generated Clocks ======================================================================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 Disp_sb_0.Disp_sb_MSS_0.MSS_ADLIB_INST MSS_075 75 Disp_sb_0.Disp_sb_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_075 ===================================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 116MB peak: 148MB) Writing Analyst data base E:\ftdi_disp\display_demo_src\libero\display\synthesis\synwork\Disp_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 143MB peak: 148MB) Writing EDIF Netlist and constraint files @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF J-2015.03M-SP1-2 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 144MB peak: 148MB) Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 144MB peak: 148MB) @W:MT246 : disp_sb_ccc_0_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock Disp|SPI_1_CLK_F2M with period 10.00ns. Please declare a user-defined clock on object "p:SPI_1_CLK_F2M" @W:MT420 : | Found inferred clock Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:Disp_sb_0.FABOSC_0.RCOSC_25_50MHZ_CCC" @W:MT420 : | Found inferred clock Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:Disp_sb_0.Disp_sb_MSS_0.FIC_2_APB_M_PCLK" @W:MT420 : | Found inferred clock Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:Disp_sb_0.CCC_0.GL0_net" @S |##### START OF TIMING REPORT #####[ # Timing Report written on Mon Feb 22 14:57:51 2016 # Top view: Disp Requested Frequency: 100.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 1.776 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------------------------- Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 121.6 MHz 10.000 8.224 1.776 inferred Inferred_clkgroup_1 Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock 100.0 MHz 428.6 MHz 10.000 2.333 7.667 inferred Inferred_clkgroup_3 Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 154.7 MHz 10.000 6.464 1.968 inferred Inferred_clkgroup_0 Disp|SPI_1_CLK_F2M 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_2 ============================================================================================================================================================= @N:MT582 : | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock | 10.000 3.536 | No paths - | 5.000 2.990 | 5.000 1.969 Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock | Diff grp - | No paths - | No paths - | No paths - Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock | Diff grp - | No paths - | No paths - | No paths - Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock | 10.000 1.776 | No paths - | No paths - | No paths - Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | Diff grp - | No paths - | No paths - | No paths - Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock | Diff grp - | No paths - | No paths - | No paths - Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | 10.000 7.667 | No paths - | No paths - | No paths - ====================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Disp_sb_0.Disp_sb_MSS_0.MSS_ADLIB_INST Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_SIZE[0] Disp_sb_MSS_TMP_0_FIC_0_AHB_MASTER_HSIZE[0] 3.190 1.776 Disp_sb_0.Disp_sb_MSS_0.MSS_ADLIB_INST Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_SIZE[1] Disp_sb_MSS_TMP_0_FIC_0_AHB_MASTER_HSIZE[1] 3.198 1.855 Disp_sb_0.Disp_sb_MSS_0.MSS_ADLIB_INST Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_ADDR[25] Disp_sb_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[25] 3.051 1.862 Disp_sb_0.Disp_sb_MSS_0.MSS_ADLIB_INST Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_ADDR[26] Disp_sb_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[26] 3.053 1.941 Disp_sb_0.Disp_sb_MSS_0.MSS_ADLIB_INST Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_TRANS1 Disp_sb_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS[1] 3.108 1.999 Disp_sb_0.Disp_sb_MSS_0.MSS_ADLIB_INST Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_ADDR[24] Disp_sb_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[24] 3.023 2.052 Disp_sb_0.Disp_sb_MSS_0.MSS_ADLIB_INST Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_ADDR[27] Disp_sb_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[27] 3.030 2.122 Disp_sb_0.Disp_sb_MSS_0.MSS_ADLIB_INST Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_WRITE Disp_sb_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE 3.135 3.203 Disp_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[2] Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[2] 0.076 3.732 Disp_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[5] Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[5] 0.094 3.819 =================================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Disp_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_3.block0 Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock RAM1K18 A_WEN[0] wen_a7[0] 9.590 1.776 Disp_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_2.block0 Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock RAM1K18 A_WEN[0] wen_a7[0] 9.590 1.776 Disp_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_3.block1 Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock RAM1K18 A_WEN[0] wen_a7[0] 9.590 1.776 Disp_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_2.block1 Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock RAM1K18 A_WEN[0] wen_a7[0] 9.590 1.776 Disp_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_3.block2 Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock RAM1K18 A_WEN[0] wen_a7[0] 9.590 1.776 Disp_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_2.block2 Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock RAM1K18 A_WEN[0] wen_a7[0] 9.590 1.776 Disp_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_3.block3 Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock RAM1K18 A_WEN[0] wen_a7[0] 9.590 1.776 Disp_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_2.block3 Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock RAM1K18 A_WEN[0] wen_a7[0] 9.590 1.776 Disp_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_3.block4 Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock RAM1K18 A_WEN[0] wen_a7[0] 9.590 1.776 Disp_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_2.block4 Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock RAM1K18 A_WEN[0] wen_a7[0] 9.590 1.776 ========================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.410 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.590 - Propagation time: 7.814 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 1.776 Number of logic level(s): 4 Starting point: Disp_sb_0.Disp_sb_MSS_0.MSS_ADLIB_INST / F_HM0_SIZE[0] Ending point: Disp_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_2.block0 / A_WEN[0] The start point is clocked by Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE The end point is clocked by Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin A_CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Disp_sb_0.Disp_sb_MSS_0.MSS_ADLIB_INST MSS_075 F_HM0_SIZE[0] Out 3.190 3.190 - Disp_sb_MSS_TMP_0_FIC_0_AHB_MASTER_HSIZE[0] Net - - 0.977 - 2 Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNI2SRR1[13] CFG4 C In - 4.167 - Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_RNI2SRR1[13] CFG4 Y Out 0.182 4.349 - arbRegSMCurrentState_ns_i_a2_d_1_1_0[0] Net - - 0.548 - 2 Disp_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.sram_wen_mem_ss3_0_o2_a0_0 CFG3 C In - 4.897 - Disp_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.sram_wen_mem_ss3_0_o2_a0_0 CFG3 Y Out 0.194 5.090 - sram_wen_mem_ss3_0_o2_a0_0 Net - - 0.548 - 2 Disp_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.sram_wen_mem_ss3_0_o2_0 CFG4 D In - 5.638 - Disp_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.sram_wen_mem_ss3_0_o2_0 CFG4 Y Out 0.284 5.922 - sram_wen_mem_ss3 Net - - 0.622 - 4 Disp_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_2.wen_a7_xx_RNIFC9I[0] CFG4 D In - 6.544 - Disp_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_2.wen_a7_xx_RNIFC9I[0] CFG4 Y Out 0.284 6.828 - wen_a7[0] Net - - 0.987 - 8 Disp_sb_0.COREAHBLSRAM_0_0.U_SramCtrlIf.genblk1\.byte_2.block0 RAM1K18 A_WEN[0] In - 7.814 - ========================================================================================================================================================================== Total path delay (propagation time + setup) of 8.224 is 4.544(55.2%) logic and 3.681(44.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------ Disp_sb_0.CORERESETP_0.count_ddr[0] Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_ddr[0] 0.094 7.667 Disp_sb_0.CORERESETP_0.count_ddr[1] Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_ddr[1] 0.094 7.732 Disp_sb_0.CORERESETP_0.count_ddr[2] Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_ddr[2] 0.094 7.746 Disp_sb_0.CORERESETP_0.count_ddr[3] Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_ddr[3] 0.094 7.760 Disp_sb_0.CORERESETP_0.count_ddr[4] Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_ddr[4] 0.094 7.774 Disp_sb_0.CORERESETP_0.count_ddr[5] Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_ddr[5] 0.094 7.789 Disp_sb_0.CORERESETP_0.count_ddr[6] Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_ddr[6] 0.094 7.803 Disp_sb_0.CORERESETP_0.count_ddr[7] Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_ddr[7] 0.094 7.817 Disp_sb_0.CORERESETP_0.count_ddr[8] Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_ddr[8] 0.094 7.831 Disp_sb_0.CORERESETP_0.count_ddr[9] Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE Q count_ddr[9] 0.094 7.845 ====================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------- Disp_sb_0.CORERESETP_0.count_ddr[13] Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_ddr_s[13] 9.778 7.667 Disp_sb_0.CORERESETP_0.count_ddr[12] Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_ddr_s[12] 9.778 7.681 Disp_sb_0.CORERESETP_0.count_ddr[11] Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_ddr_s[11] 9.778 7.695 Disp_sb_0.CORERESETP_0.count_ddr[10] Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_ddr_s[10] 9.778 7.709 Disp_sb_0.CORERESETP_0.count_ddr[9] Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_ddr_s[9] 9.778 7.723 Disp_sb_0.CORERESETP_0.count_ddr[8] Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_ddr_s[8] 9.778 7.738 Disp_sb_0.CORERESETP_0.count_ddr[7] Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_ddr_s[7] 9.778 7.752 Disp_sb_0.CORERESETP_0.count_ddr[6] Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_ddr_s[6] 9.778 7.766 Disp_sb_0.CORERESETP_0.count_ddr[5] Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_ddr_s[5] 9.778 7.780 Disp_sb_0.CORERESETP_0.count_ddr[4] Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock SLE D count_ddr_s[4] 9.778 7.795 =========================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 2.111 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 7.667 Number of logic level(s): 14 Starting point: Disp_sb_0.CORERESETP_0.count_ddr[0] / Q Ending point: Disp_sb_0.CORERESETP_0.count_ddr[13] / D The start point is clocked by Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock [rising] on pin CLK The end point is clocked by Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------- Disp_sb_0.CORERESETP_0.count_ddr[0] SLE Q Out 0.094 0.094 - count_ddr[0] Net - - 0.637 - 3 Disp_sb_0.CORERESETP_0.count_ddr_s_210 ARI1 B In - 0.732 - Disp_sb_0.CORERESETP_0.count_ddr_s_210 ARI1 FCO Out 0.174 0.906 - count_ddr_s_210_FCO Net - - 0.000 - 1 Disp_sb_0.CORERESETP_0.count_ddr_cry[1] ARI1 FCI In - 0.906 - Disp_sb_0.CORERESETP_0.count_ddr_cry[1] ARI1 FCO Out 0.014 0.920 - count_ddr_cry[1] Net - - 0.000 - 1 Disp_sb_0.CORERESETP_0.count_ddr_cry[2] ARI1 FCI In - 0.920 - Disp_sb_0.CORERESETP_0.count_ddr_cry[2] ARI1 FCO Out 0.014 0.935 - count_ddr_cry[2] Net - - 0.000 - 1 Disp_sb_0.CORERESETP_0.count_ddr_cry[3] ARI1 FCI In - 0.935 - Disp_sb_0.CORERESETP_0.count_ddr_cry[3] ARI1 FCO Out 0.014 0.949 - count_ddr_cry[3] Net - - 0.000 - 1 Disp_sb_0.CORERESETP_0.count_ddr_cry[4] ARI1 FCI In - 0.949 - Disp_sb_0.CORERESETP_0.count_ddr_cry[4] ARI1 FCO Out 0.014 0.963 - count_ddr_cry[4] Net - - 0.000 - 1 Disp_sb_0.CORERESETP_0.count_ddr_cry[5] ARI1 FCI In - 0.963 - Disp_sb_0.CORERESETP_0.count_ddr_cry[5] ARI1 FCO Out 0.014 0.977 - count_ddr_cry[5] Net - - 0.000 - 1 Disp_sb_0.CORERESETP_0.count_ddr_cry[6] ARI1 FCI In - 0.977 - Disp_sb_0.CORERESETP_0.count_ddr_cry[6] ARI1 FCO Out 0.014 0.991 - count_ddr_cry[6] Net - - 0.000 - 1 Disp_sb_0.CORERESETP_0.count_ddr_cry[7] ARI1 FCI In - 0.991 - Disp_sb_0.CORERESETP_0.count_ddr_cry[7] ARI1 FCO Out 0.014 1.006 - count_ddr_cry[7] Net - - 0.000 - 1 Disp_sb_0.CORERESETP_0.count_ddr_cry[8] ARI1 FCI In - 1.006 - Disp_sb_0.CORERESETP_0.count_ddr_cry[8] ARI1 FCO Out 0.014 1.020 - count_ddr_cry[8] Net - - 0.000 - 1 Disp_sb_0.CORERESETP_0.count_ddr_cry[9] ARI1 FCI In - 1.020 - Disp_sb_0.CORERESETP_0.count_ddr_cry[9] ARI1 FCO Out 0.014 1.034 - count_ddr_cry[9] Net - - 0.000 - 1 Disp_sb_0.CORERESETP_0.count_ddr_cry[10] ARI1 FCI In - 1.034 - Disp_sb_0.CORERESETP_0.count_ddr_cry[10] ARI1 FCO Out 0.014 1.048 - count_ddr_cry[10] Net - - 0.000 - 1 Disp_sb_0.CORERESETP_0.count_ddr_cry[11] ARI1 FCI In - 1.048 - Disp_sb_0.CORERESETP_0.count_ddr_cry[11] ARI1 FCO Out 0.014 1.062 - count_ddr_cry[11] Net - - 0.000 - 1 Disp_sb_0.CORERESETP_0.count_ddr_cry[12] ARI1 FCI In - 1.062 - Disp_sb_0.CORERESETP_0.count_ddr_cry[12] ARI1 FCO Out 0.014 1.077 - count_ddr_cry[12] Net - - 0.000 - 1 Disp_sb_0.CORERESETP_0.count_ddr_s[13] ARI1 FCI In - 1.077 - Disp_sb_0.CORERESETP_0.count_ddr_s[13] ARI1 S Out 0.063 1.140 - count_ddr_s[13] Net - - 0.971 - 1 Disp_sb_0.CORERESETP_0.count_ddr[13] SLE D In - 2.111 - ======================================================================================================= Total path delay (propagation time + setup) of 2.333 is 0.724(31.1%) logic and 1.609(68.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Disp_sb_0.CORECONFIGP_0.psel Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q psel 0.094 1.968 Disp_sb_0.CORECONFIGP_0.state[1] Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q state[1] 0.076 2.990 Disp_sb_0.Disp_sb_MSS_0.MSS_ADLIB_INST Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_075 MDDR_FABRIC_PRDATA[15] CORECONFIGP_0_MDDR_APBmslave_PRDATA[15] 4.956 3.536 Disp_sb_0.Disp_sb_MSS_0.MSS_ADLIB_INST Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_075 MDDR_FABRIC_PRDATA[9] CORECONFIGP_0_MDDR_APBmslave_PRDATA[9] 4.949 3.543 Disp_sb_0.Disp_sb_MSS_0.MSS_ADLIB_INST Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_075 MDDR_FABRIC_PRDATA[4] CORECONFIGP_0_MDDR_APBmslave_PRDATA[4] 4.943 3.549 Disp_sb_0.Disp_sb_MSS_0.MSS_ADLIB_INST Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_075 MDDR_FABRIC_PRDATA[14] CORECONFIGP_0_MDDR_APBmslave_PRDATA[14] 4.935 3.557 Disp_sb_0.Disp_sb_MSS_0.MSS_ADLIB_INST Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_075 MDDR_FABRIC_PRDATA[10] CORECONFIGP_0_MDDR_APBmslave_PRDATA[10] 4.892 3.600 Disp_sb_0.CORECONFIGP_0.paddr[13] Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE Q paddr[13] 0.094 3.644 Disp_sb_0.Disp_sb_MSS_0.MSS_ADLIB_INST Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_075 MDDR_FABRIC_PRDATA[11] CORECONFIGP_0_MDDR_APBmslave_PRDATA[11] 4.837 3.655 Disp_sb_0.Disp_sb_MSS_0.MSS_ADLIB_INST Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock MSS_075 MDDR_FABRIC_PRDATA[13] CORECONFIGP_0_MDDR_APBmslave_PRDATA[13] 4.808 3.684 =============================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------- Disp_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[16] Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE D prdata[16] 4.778 1.968 Disp_sb_0.CORECONFIGP_0.soft_reset_reg[0] Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE EN soft_reset_reg6 4.707 2.115 Disp_sb_0.CORECONFIGP_0.soft_reset_reg[1] Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE EN soft_reset_reg6 4.707 2.115 Disp_sb_0.CORECONFIGP_0.soft_reset_reg[2] Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE EN soft_reset_reg6 4.707 2.115 Disp_sb_0.CORECONFIGP_0.soft_reset_reg[3] Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE EN soft_reset_reg6 4.707 2.115 Disp_sb_0.CORECONFIGP_0.soft_reset_reg[4] Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE EN soft_reset_reg6 4.707 2.115 Disp_sb_0.CORECONFIGP_0.soft_reset_reg[5] Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE EN soft_reset_reg6 4.707 2.115 Disp_sb_0.CORECONFIGP_0.soft_reset_reg[6] Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE EN soft_reset_reg6 4.707 2.115 Disp_sb_0.CORECONFIGP_0.soft_reset_reg[7] Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE EN soft_reset_reg6 4.707 2.115 Disp_sb_0.CORECONFIGP_0.soft_reset_reg[8] Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock SLE EN soft_reset_reg6 4.707 2.115 ========================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.778 - Propagation time: 2.809 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 1.968 Number of logic level(s): 3 Starting point: Disp_sb_0.CORECONFIGP_0.psel / Q Ending point: Disp_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[16] / D The start point is clocked by Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock [falling] on pin CLK The end point is clocked by Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------- Disp_sb_0.CORECONFIGP_0.psel SLE Q Out 0.094 0.094 - psel Net - - 0.676 - 4 Disp_sb_0.CORECONFIGP_0.un1_R_SDIF3_PSEL_1 CFG3 B In - 0.770 - Disp_sb_0.CORECONFIGP_0.un1_R_SDIF3_PSEL_1 CFG3 Y Out 0.129 0.900 - un1_R_SDIF3_PSEL_1 Net - - 0.812 - 17 Disp_sb_0.CORECONFIGP_0.int_prdata_5_sqmuxa CFG4 D In - 1.711 - Disp_sb_0.CORECONFIGP_0.int_prdata_5_sqmuxa CFG4 Y Out 0.236 1.947 - int_prdata_5_sqmuxa Net - - 0.548 - 2 Disp_sb_0.CORECONFIGP_0.prdata_0_iv[16] CFG4 C In - 2.495 - Disp_sb_0.CORECONFIGP_0.prdata_0_iv[16] CFG4 Y Out 0.177 2.672 - prdata[16] Net - - 0.138 - 1 Disp_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[16] SLE D In - 2.809 - ============================================================================================================= Total path delay (propagation time + setup) of 3.032 is 0.858(28.3%) logic and 2.174(71.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Finished final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 144MB peak: 148MB) Finished timing report (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 144MB peak: 148MB) --------------------------------------- Resource Usage Report for Disp Mapping to part: m2s090tfbga484-1 Cell usage: CCC 1 use CLKINT 7 uses MSS_075 1 use RCOSC_25_50MHZ 1 use RCOSC_25_50MHZ_FAB 1 use SYSRESET 1 use CFG1 4 uses CFG2 86 uses CFG3 78 uses CFG4 117 uses Carry primitives used for arithmetic functions: ARI1 14 uses Sequential Cells: SLE 228 uses DSP Blocks: 0 I/O ports: 58 I/O primitives: 56 BIBUF 16 uses INBUF 6 uses OUTBUF 31 uses OUTBUF_DIFF 1 use TRIBUFF 2 uses Global Clock Buffers: 7 RAM/ROM usage summary Block Rams (RAM1K18) : 64 Total LUTs: 299 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 2304; LUTs = 2304; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 228 + 0 + 2304 + 0 = 2532; Total number of LUTs after P&R: 299 + 0 + 2304 + 0 = 2603; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 52MB peak: 148MB) Process took 0h:00m:05s realtime, 0h:00m:05s cputime # Mon Feb 22 14:57:51 2016 ###########################################################]