@W: BN132 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3626:2:3626:14|Removing user instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_16,  because it is equivalent to instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_15
@W: BN132 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3580:2:3580:14|Removing user instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_15,  because it is equivalent to instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_14
@W: BN132 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3534:2:3534:14|Removing user instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_14,  because it is equivalent to instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_13
@W: BN132 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3488:2:3488:14|Removing user instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_13,  because it is equivalent to instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_12
@W: BN132 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3442:2:3442:14|Removing user instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_12,  because it is equivalent to instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_11
@W: BN132 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3396:2:3396:14|Removing user instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_11,  because it is equivalent to instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3304:2:3304:13|Removing user instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_9,  because it is equivalent to instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3258:2:3258:13|Removing user instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_8,  because it is equivalent to instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3212:2:3212:13|Removing user instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_7,  because it is equivalent to instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: BN132 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":3166:2:3166:13|Removing user instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_6,  because it is equivalent to instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_10
@W: MT530 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":546:4:546:9|Found inferred clock Disp_sb_MSS|FIC_2_APB_M_PCLK_inferred_clock which controls 110 sequential elements including Disp_sb_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[31:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v":64:4:64:9|Found inferred clock Disp_sb_CCC_0_FCCC|GL0_net_inferred_clock which controls 207 sequential elements including Disp_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.default_slave_sm.defSlaveSMCurrentState. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"e:\ftdi_disp\display_demo_src\libero\display\component\work\disp_sb_mss\disp_sb_mss.v":1158:0:1158:13|Found inferred clock Disp|SPI_1_CLK_F2M which controls 0 sequential elements including Disp_sb_0.Disp_sb_MSS_0.MSS_ADLIB_INST. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Found inferred clock Disp_sb_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 31 sequential elements including Disp_sb_0.CORERESETP_0.count_ddr[13:0]. This clock has no specified timing constraint which may adversely impact design performance. 
