@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[20] of view:PrimLib.dffr(prim) in hierarchy view:work.Disp_sb(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[21] of view:PrimLib.dffr(prim) in hierarchy view:work.Disp_sb(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[22] of view:PrimLib.dffr(prim) in hierarchy view:work.Disp_sb(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[23] of view:PrimLib.dffr(prim) in hierarchy view:work.Disp_sb(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28] of view:PrimLib.dffr(prim) in hierarchy view:work.Disp_sb(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[29] of view:PrimLib.dffr(prim) in hierarchy view:work.Disp_sb(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[30] of view:PrimLib.dffr(prim) in hierarchy view:work.Disp_sb(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[31] of view:PrimLib.dffr(prim) in hierarchy view:work.Disp_sb(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":79:4:79:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_0.masterDataInProg[3] of view:PrimLib.dffr(prim) in hierarchy view:work.Disp_sb(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":79:4:79:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_0.masterDataInProg[2] of view:PrimLib.dffr(prim) in hierarchy view:work.Disp_sb(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":79:4:79:9|Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_0.masterDataInProg[1] of view:PrimLib.dffr(prim) in hierarchy view:work.Disp_sb(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblsram\2.0.113\rtl\vlog\core\ahblsramif.v":161:3:161:8|Removing sequential instance HADDR_d[17] of view:PrimLib.dffr(prim) in hierarchy view:COREAHBLSRAM_LIB.AHBLSramIf(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblsram\2.0.113\rtl\vlog\core\ahblsramif.v":161:3:161:8|Removing sequential instance HADDR_d[18] of view:PrimLib.dffr(prim) in hierarchy view:COREAHBLSRAM_LIB.AHBLSramIf(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblsram\2.0.113\rtl\vlog\core\ahblsramif.v":161:3:161:8|Removing sequential instance HADDR_d[19] of view:PrimLib.dffr(prim) in hierarchy view:COREAHBLSRAM_LIB.AHBLSramIf(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[16] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[17] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[18] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[19] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[20] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[21] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[22] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[23] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[24] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[25] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[26] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[27] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[28] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[29] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[30] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance pwdata[31] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance paddr[11] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":255:4:255:9|Removing sequential instance paddr[14] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z5(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance Disp_sb_0.CORERESETP_0.DDR_READY_int in hierarchy view:work.Disp(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance Disp_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[19] in hierarchy view:work.Disp(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance Disp_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[18] in hierarchy view:work.Disp(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance Disp_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[17] in hierarchy view:work.Disp(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblsram\2.0.113\rtl\vlog\core\ahblsramif.v":161:3:161:8|Removing sequential instance Disp_sb_0.COREAHBLSRAM_0_0.U_AHBLSramIf.HSIZE_d[2] in hierarchy view:work.Disp(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance Disp_sb_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[24] in hierarchy view:work.Disp(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[14] in hierarchy view:work.Disp(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[15] in hierarchy view:work.Disp(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[2] in hierarchy view:work.Disp(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[3] in hierarchy view:work.Disp(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[6] in hierarchy view:work.Disp(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[7] in hierarchy view:work.Disp(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[10] in hierarchy view:work.Disp(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[11] in hierarchy view:work.Disp(verilog) because there are no references to its outputs 
@N: BN362 :"e:\ftdi_disp\display_demo_src\libero\display\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance Disp_sb_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState[5] in hierarchy view:work.Disp(verilog) because there are no references to its outputs 
@N: FP130 |Promoting Net un1_Disp_sb_0_2 on CLKINT  I_211 
@N: FP130 |Promoting Net Disp_sb_0.CORECONFIGP_0_APB_S_PRESET_N on CLKINT  I_212 
@N: FP130 |Promoting Net Disp_sb_0.CORECONFIGP_0_APB_S_PCLK on CLKINT  I_213 
@N: FP130 |Promoting Net Disp_sb_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT  I_214 
@N: FP130 |Promoting Net Disp_sb_0.CORERESETP_0.sm0_areset_n_rcosc on CLKINT  I_215 
@N: BW103 |Synopsys Constraint File time units using default value of 1ns 
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
@N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
@N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack
