<?xml version="1.0" encoding="UTF-8" standalone="no" ?><TCML xmlns="tcml"><Scenario Id="Primary"><false_path Id="3"><from><type>EXCEPT_SRC</type><toolcontext>TCL</toolcontext><orig_string>[get_pins {Disp_sb_0/CORERESETP_0/ddr_settled:CLK }]</orig_string><macro><type>PIN</type><pattern>Disp_sb_0/CORERESETP_0/ddr_settled:CLK</pattern></macro></from><to><type>EXCEPT_DST</type><toolcontext>TCL</toolcontext><orig_string>[get_pins {Disp_sb_0/CORERESETP_0/ddr_settled_q1:D }]</orig_string><macro><type>PIN</type><pattern>Disp_sb_0/CORERESETP_0/ddr_settled_q1:D</pattern></macro></to><comment/><origin><file>Tcl</file><line>0</line></origin></false_path><false_path Id="4"><from><type>EXCEPT_SRC</type><toolcontext>TCL</toolcontext><orig_string>[get_pins {Disp_sb_0/CORERESETP_0/release_sdif0_core:CLK }]</orig_string><macro><type>PIN</type><pattern>Disp_sb_0/CORERESETP_0/release_sdif0_core:CLK</pattern></macro></from><to><type>EXCEPT_DST</type><toolcontext>TCL</toolcontext><orig_string>[get_pins {Disp_sb_0/CORERESETP_0/release_sdif0_core_q1:D }]</orig_string><macro><type>PIN</type><pattern>Disp_sb_0/CORERESETP_0/release_sdif0_core_q1:D</pattern></macro></to><comment/><origin><file>Tcl</file><line>0</line></origin></false_path><false_path Id="5"><from><type>EXCEPT_SRC</type><toolcontext>TCL</toolcontext><orig_string>[get_pins {Disp_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK }]</orig_string><macro><type>PIN</type><pattern>Disp_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</pattern></macro></from><to><type>EXCEPT_DST</type><toolcontext>TCL</toolcontext><orig_string>[get_pins {Disp_sb_0/CORERESETP_0/sm0_areset_n_rcosc_q1:ALn }]</orig_string><macro><type>PIN</type><pattern>Disp_sb_0/CORERESETP_0/sm0_areset_n_rcosc_q1:ALn</pattern></macro></to><comment/><origin><file>Tcl</file><line>0</line></origin></false_path><false_path Id="6"><from><type>EXCEPT_SRC</type><toolcontext>TCL</toolcontext><orig_string>[get_pins {Disp_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK }]</orig_string><macro><type>PIN</type><pattern>Disp_sb_0/CORERESETP_0/MSS_HPMS_READY_int:CLK</pattern></macro></from><to><type>EXCEPT_DST</type><toolcontext>TCL</toolcontext><orig_string>[get_pins {Disp_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:ALn }]</orig_string><macro><type>PIN</type><pattern>Disp_sb_0/CORERESETP_0/sdif0_areset_n_rcosc:ALn</pattern></macro></to><comment/><origin><file>Tcl</file><line>0</line></origin></false_path><false_path Id="7"><from><type>EXCEPT_SRC</type><toolcontext>TCL</toolcontext><orig_string>[get_pins {Disp_sb_0/CORERESETP_0/count_ddr_enable:CLK }]</orig_string><macro><type>PIN</type><pattern>Disp_sb_0/CORERESETP_0/count_ddr_enable:CLK</pattern></macro></from><to><type>EXCEPT_DST</type><toolcontext>TCL</toolcontext><orig_string>[get_pins {Disp_sb_0/CORERESETP_0/count_ddr_enable_q1:D }]</orig_string><macro><type>PIN</type><pattern>Disp_sb_0/CORERESETP_0/count_ddr_enable_q1:D</pattern></macro></to><comment/><origin><file>Tcl</file><line>0</line></origin></false_path></Scenario></TCML>