Detailed Resource Usage
Module Name,Fabric 4LUT,Fabric DFF,Interface 4LUT,Interface DFF,Single-Ended I/O,Differential I/O Pairs,LSRAM 18K,PLLs and CCCs,Chip Globals,MSS,Multi-Mode UART,SPI,I2C,MDDR Controller,RCOSC_50MHZ
Disp_sb_0/Disp_sb_MSS_0/Primitives,32,0,0,0,48,1,0,0,2,1,1,2,2,1,0
Disp_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/genblk1_byte_0/Primitives,0,0,576,576,0,0,16,0,0,0,0,0,0,0,0
Disp_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/genblk1_byte_1/Primitives,0,0,576,576,0,0,16,0,0,0,0,0,0,0,0
Disp_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/genblk1_byte_3/Primitives,0,0,576,576,0,0,16,0,0,0,0,0,0,0,0
Disp_sb_0/CORERESETP_0/Primitives,31,50,0,0,0,0,0,0,3,0,0,0,0,0,0
Disp_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/Primitives,18,37,0,0,0,0,0,0,0,0,0,0,0,0,0
Disp_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/genblk1_byte_2/Primitives,0,0,576,576,0,0,16,0,0,0,0,0,0,0,0
Disp_sb_0/FABOSC_0/Primitives,0,0,0,0,0,0,0,0,1,0,0,0,0,0,1
Disp_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/Primitives,48,38,0,0,0,0,0,0,0,0,0,0,0,0,0
Disp_sb_0/CORECONFIGP_0/Primitives,53,74,0,0,0,0,0,0,0,0,0,0,0,0,0
Disp_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/slave_arbiter/Primitives,23,3,0,0,0,0,0,0,0,0,0,0,0,0,0
Primitives/Primitives,1,0,0,0,7,0,0,0,0,0,0,0,0,0,0
Disp_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/genblk1.byte_3/Primitives,12,0,0,0,0,0,0,0,0,0,0,0,0,0,0
Disp_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/genblk1.byte_2/Primitives,12,0,0,0,0,0,0,0,0,0,0,0,0,0,0
Disp_sb_0/CoreAHBLite_0/matrix4x16/slavestage_0/Primitives,34,1,0,0,0,0,0,0,0,0,0,0,0,0,0
Disp_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/genblk1.byte_1/Primitives,12,0,0,0,0,0,0,0,0,0,0,0,0,0,0
Disp_sb_0/COREAHBLSRAM_0_0/U_SramCtrlIf/genblk1.byte_0/Primitives,12,1,0,0,0,0,0,0,0,0,0,0,0,0,0
Disp_sb_0/COREAHBLSRAM_0_0/U_AHBLSramIf/Primitives,7,23,0,0,0,0,0,0,0,0,0,0,0,0,0
Disp_sb_0/CCC_0/Primitives,0,0,0,0,0,0,0,1,1,0,0,0,0,0,0
Disp_sb_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/Primitives,4,1,0,0,0,0,0,0,0,0,0,0,0,0,0
