| Project Settings |
|---|
| Project Name | DeviceCertificate_top_syn | Implementation Name | synthesis |
| Top Module | DeviceCertificate_top | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 10000 |
| Disable I/O Insertion | 0 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
33 |
64 |
0 |
- |
0m:00s |
- |
3/11/2016
5:14:34 PM |
| (premap) | Complete |
27 |
3 |
0 |
0m:00s |
0m:00s |
135MB |
3/11/2016
5:14:36 PM |
| (fpga_mapper) | Complete |
37 |
32 |
0 |
0m:01s |
0m:01s |
135MB |
3/11/2016
5:14:37 PM |
| Multi-srs Generator |
Complete | | | | 0m:00s | | | 3/11/2016
5:14:35 PM |
| Area Summary |
|---|
| |
| Sequential Cells | 0 |
DSP Blocks (MACC)
(dsp_used) | 0 |
| I/O Cells | 2 |
Global Clock Buffers | 1 |
| LUTs
(total_luts) | 0 |
| |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| DeviceCertificate_CCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | NA | NA |
| DeviceCertificate_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | 100.0 MHz | NA | NA |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 1 / 0 |
| |
|