<?xml version="1.0" encoding="UTF-8" standalone="no" ?><Component xmlns="http://actel.com/sweng/afi"><name>OSC</name><vendor>Actel</vendor><library>SgCore</library><version>1.0.103</version><fileSets><fileSet fileSetId="SYNPLIFY_SYNTHESIS_FILESET"><file fileid="0"><name>osc_comps.v</name><userFileType>Verilog</userFileType></file></fileSet><fileSet fileSetId="PRECISION_SYNTHESIS_FILESET"><file fileid="1"><name>osc_comps_pre.v</name><userFileType>Verilog</userFileType></file></fileSet></fileSets><hwModel><views><view><fileSetRef>SYNPLIFY_SYNTHESIS_FILESET</fileSetRef><fileSetRef>PRECISION_SYNTHESIS_FILESET</fileSetRef><name>SYNTHESIS</name></view></views></hwModel></Component>