#Build: Synplify Pro J-2015.03M-SP1-2, Build 266R, Dec 14 2015 #install: D:\Microsemi\Libero_SoC_v11.7\Synplify #OS: Windows 7 6.1 #Hostname: W764-AITHAS #Implementation: synthesis Synopsys HDL Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Synopsys Verilog Compiler, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. @I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v" @I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\hypermods.v" @I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\umr_capim.v" @I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\scemi_objects.v" @I::"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\scemi_pipes.svh" @I::"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v" @I::"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v" @I::"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\work\ECC_App\CCC_0\ECC_App_CCC_0_FCCC.v" @I::"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" @I::"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\work\ECC_App\FABOSC_0\ECC_App_FABOSC_0_OSC.v" @I::"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\work\ECC_App_MSS\ECC_App_MSS_syn.v" @I::"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\work\ECC_App_MSS\ECC_App_MSS.v" @I::"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\work\ECC_App\ECC_App.v" @I::"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\work\ECC_App_top\ECC_App_top.v" Verilog syntax check successful! Options changed - recompiling Selecting top level module ECC_App_top @N:CG364 : smartfusion2.v(376) | Synthesizing module VCC @N:CG364 : smartfusion2.v(372) | Synthesizing module GND @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT @N:CG364 : smartfusion2.v(727) | Synthesizing module CCC @N:CG364 : ECC_App_CCC_0_FCCC.v(5) | Synthesizing module ECC_App_CCC_0_FCCC @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000 DEVICE_090=32'b00000000000000000000000000000001 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z1 @W:CL169 : coreresetp.v(1613) | Pruning register count_ddr[13:0] @W:CL169 : coreresetp.v(1581) | Pruning register count_sdif3[12:0] @W:CL169 : coreresetp.v(1549) | Pruning register count_sdif2[12:0] @W:CL169 : coreresetp.v(1517) | Pruning register count_sdif1[12:0] @W:CL169 : coreresetp.v(1485) | Pruning register count_sdif0[12:0] @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif0_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif0_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_rcosc @W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_q1 @W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_rcosc @W:CL169 : coreresetp.v(1365) | Pruning register count_sdif3_enable @W:CL169 : coreresetp.v(1300) | Pruning register count_sdif2_enable @W:CL169 : coreresetp.v(1235) | Pruning register count_sdif1_enable @W:CL169 : coreresetp.v(1170) | Pruning register count_sdif0_enable @W:CL169 : coreresetp.v(1089) | Pruning register count_ddr_enable @N:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q1. @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1. @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0 @W:CL169 : coreresetp.v(1089) | Pruning register release_ext_reset @W:CL169 : coreresetp.v(1433) | Pruning register EXT_RESET_OUT_int @W:CL169 : coreresetp.v(1433) | Pruning register sm2_state[2:0] @W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_q1 @W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_clk_base @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF @N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF @N:CG364 : ECC_App_MSS_syn.v(5) | Synthesizing module MSS_075 @N:CG364 : ECC_App_MSS.v(9) | Synthesizing module ECC_App_MSS @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ @N:CG364 : ECC_App_FABOSC_0_OSC.v(5) | Synthesizing module ECC_App_FABOSC_0_OSC @N:CG364 : smartfusion2.v(718) | Synthesizing module SYSRESET @N:CG364 : ECC_App.v(9) | Synthesizing module ECC_App @N:CG364 : ECC_App_top.v(9) | Synthesizing module ECC_App_top @W:CL157 : ECC_App_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : ECC_App_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible. @W:CL157 : ECC_App_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits -- simulation mismatch possible. @W:CL157 : ECC_App_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits -- simulation mismatch possible. @W:CL159 : ECC_App_FABOSC_0_OSC.v(14) | Input XTL is unused @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2. @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2. @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @W:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused @W:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused @W:CL159 : coreresetp.v(59) | Input SDIF0_SPLL_LOCK is unused @W:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused @W:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused @W:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused @W:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused @W:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused @W:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused @W:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused @W:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused @W:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused @W:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused @W:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused @W:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused @W:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused @W:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused @W:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused @W:CL159 : coreresetp.v(107) | Input SOFT_EXT_RESET_OUT is unused @W:CL159 : coreresetp.v(108) | Input SOFT_RESET_F2M is unused @W:CL159 : coreresetp.v(109) | Input SOFT_M3_RESET is unused @W:CL159 : coreresetp.v(110) | Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused @W:CL159 : coreresetp.v(111) | Input SOFT_FDDR_CORE_RESET is unused @W:CL159 : coreresetp.v(112) | Input SOFT_SDIF0_PHY_RESET is unused @W:CL159 : coreresetp.v(113) | Input SOFT_SDIF0_CORE_RESET is unused @W:CL159 : coreresetp.v(114) | Input SOFT_SDIF1_PHY_RESET is unused @W:CL159 : coreresetp.v(115) | Input SOFT_SDIF1_CORE_RESET is unused @W:CL159 : coreresetp.v(116) | Input SOFT_SDIF2_PHY_RESET is unused @W:CL159 : coreresetp.v(117) | Input SOFT_SDIF2_CORE_RESET is unused @W:CL159 : coreresetp.v(118) | Input SOFT_SDIF3_PHY_RESET is unused @W:CL159 : coreresetp.v(119) | Input SOFT_SDIF3_CORE_RESET is unused @W:CL159 : coreresetp.v(123) | Input SOFT_SDIF0_0_CORE_RESET is unused @W:CL159 : coreresetp.v(124) | Input SOFT_SDIF0_1_CORE_RESET is unused At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Feb 18 15:29:10 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Feb 18 15:29:10 2016 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Feb 18 15:29:10 2016 ###########################################################] Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec 1 2015 @N: : | Running in 64-bit mode File C:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3\bin64\syn_nfilter.exe changed - recompiling File D:\Libero11.6\website\PUBLISH\SF2_ECC_Demo_DF\ECC_App\synthesis\synwork\ECC_App_top_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Feb 18 15:29:12 2016 ###########################################################] Pre-mapping Report Synopsys Generic Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) Linked File: ECC_App_top_scck.rpt Printing clock summary report in "D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\synthesis\ECC_App_top_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 105MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 103MB peak: 105MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 104MB peak: 105MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 104MB peak: 107MB) @W:BN132 : coreresetp.v(1089) | Removing sequential instance ECC_App_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int, because it is equivalent to instance ECC_App_0.CORERESETP_0.FDDR_CORE_RESET_N_int @N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_RELEASED_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1170) | Removing sequential instance sdif0_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z1(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z1(verilog) because there are no references to its outputs syn_allowed_resources : blockrams=109 set on top level netlist ECC_App_top Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB) @S |Clock Summary ***************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ----------------------------------------------------------------------------------------------------------------------- ECC_App_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 ECC_App_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_1 ======================================================================================================================= @W:MT530 : coreresetp.v(565) | Found inferred clock ECC_App_CCC_0_FCCC|GL0_net_inferred_clock which controls 54 sequential elements including ECC_App_0.CORERESETP_0.MSS_HPMS_READY_int. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coreresetp.v(912) | Found inferred clock ECC_App_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 15 sequential elements including ECC_App_0.CORERESETP_0.sdif3_areset_n_rcosc_q1. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\synthesis\ECC_App_top.sap. Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 135MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Feb 18 15:29:12 2016 ###########################################################] Map & Optimize Report Synopsys Generic Technology Mapper, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42 Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. Product Version J-2015.03M-SP1-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 135MB) @W:MO111 : ecc_app_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module ECC_App_FABOSC_0_OSC) @W:MO111 : ecc_app_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module ECC_App_FABOSC_0_OSC) @W:MO111 : ecc_app_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module ECC_App_FABOSC_0_OSC) @W:MO111 : ecc_app_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module ECC_App_FABOSC_0_OSC) @W:MO171 : coreresetp.v(676) | Sequential instance ECC_App_0.CORERESETP_0.SDIF0_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(695) | Sequential instance ECC_App_0.CORERESETP_0.SDIF1_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance ECC_App_0.CORERESETP_0.SDIF2_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance ECC_App_0.CORERESETP_0.SDIF3_PERST_N_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(676) | Sequential instance ECC_App_0.CORERESETP_0.SDIF0_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(695) | Sequential instance ECC_App_0.CORERESETP_0.SDIF1_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance ECC_App_0.CORERESETP_0.SDIF2_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance ECC_App_0.CORERESETP_0.SDIF3_PERST_N_q2 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(676) | Sequential instance ECC_App_0.CORERESETP_0.SDIF0_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(695) | Sequential instance ECC_App_0.CORERESETP_0.SDIF1_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(714) | Sequential instance ECC_App_0.CORERESETP_0.SDIF2_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(733) | Sequential instance ECC_App_0.CORERESETP_0.SDIF3_PERST_N_q3 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(769) | Sequential instance ECC_App_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(769) | Sequential instance ECC_App_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation @W:MO171 : coreresetp.v(1388) | Sequential instance ECC_App_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation @W:BN132 : coreresetp.v(963) | Removing sequential instance ECC_App_0.CORERESETP_0.sdif3_spll_lock_q1, because it is equivalent to instance ECC_App_0.CORERESETP_0.CONFIG2_DONE_q1 @W:BN132 : coreresetp.v(946) | Removing sequential instance ECC_App_0.CORERESETP_0.CONFIG2_DONE_q1, because it is equivalent to instance ECC_App_0.CORERESETP_0.CONFIG1_DONE_q1 @W:BN132 : coreresetp.v(946) | Removing sequential instance ECC_App_0.CORERESETP_0.CONFIG2_DONE_clk_base, because it is equivalent to instance ECC_App_0.CORERESETP_0.sdif3_spll_lock_q2 @W:BN132 : coreresetp.v(929) | Removing sequential instance ECC_App_0.CORERESETP_0.CONFIG1_DONE_clk_base, because it is equivalent to instance ECC_App_0.CORERESETP_0.sdif3_spll_lock_q2 @W:BN132 : coreresetp.v(884) | Removing sequential instance ECC_App_0.CORERESETP_0.sdif1_areset_n_rcosc_q1, because it is equivalent to instance ECC_App_0.CORERESETP_0.sdif0_areset_n_rcosc_q1 @W:BN132 : coreresetp.v(912) | Removing sequential instance ECC_App_0.CORERESETP_0.sdif3_areset_n_rcosc_q1, because it is equivalent to instance ECC_App_0.CORERESETP_0.sdif0_areset_n_rcosc_q1 @W:BN132 : coreresetp.v(898) | Removing sequential instance ECC_App_0.CORERESETP_0.sdif2_areset_n_rcosc_q1, because it is equivalent to instance ECC_App_0.CORERESETP_0.sdif0_areset_n_rcosc_q1 @W:BN132 : coreresetp.v(856) | Removing sequential instance ECC_App_0.CORERESETP_0.sm0_areset_n_rcosc_q1, because it is equivalent to instance ECC_App_0.CORERESETP_0.sdif0_areset_n_rcosc_q1 @W:BN132 : coreresetp.v(898) | Removing sequential instance ECC_App_0.CORERESETP_0.sdif2_areset_n_rcosc, because it is equivalent to instance ECC_App_0.CORERESETP_0.sm0_areset_n_rcosc @W:BN132 : coreresetp.v(912) | Removing sequential instance ECC_App_0.CORERESETP_0.sdif3_areset_n_rcosc, because it is equivalent to instance ECC_App_0.CORERESETP_0.sm0_areset_n_rcosc Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB) Encoding state machine sm0_state[6:0] (view:work.CoreResetP_Z1(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 @N:BN362 : coreresetp.v(1089) | Removing sequential instance ECC_App_0.CORERESETP_0.INIT_DONE_int in hierarchy view:work.ECC_App_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance ECC_App_0.CORERESETP_0.sm0_state[6] in hierarchy view:work.ECC_App_top(verilog) because there are no references to its outputs Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB) @N:BN114 : ecc_app.v(243) | Removing instance ECC_App_0.SYSRESET_POR of black_box view:ACG4.SYSRESET(PRIM) because there are no references to its outputs @N:BN362 : coreresetp.v(1613) | Removing sequential instance ECC_App_0.CORERESETP_0.ddr_settled in hierarchy view:work.ECC_App_top(verilog) because there are no references to its outputs @A:BN291 : coreresetp.v(1613) | Boundary register ECC_App_0.CORERESETP_0.ddr_settled packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N:BN362 : coreresetp.v(526) | Removing sequential instance ECC_App_0.CORERESETP_0.FIC_2_APB_M_PRESET_N_q1 in hierarchy view:work.ECC_App_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(511) | Removing sequential instance ECC_App_0.CORERESETP_0.RESET_N_M2F_q1 in hierarchy view:work.ECC_App_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(496) | Removing sequential instance ECC_App_0.CORERESETP_0.POWER_ON_RESET_N_q1 in hierarchy view:work.ECC_App_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1646) | Removing sequential instance ECC_App_0.CORERESETP_0.ddr_settled_q1 in hierarchy view:work.ECC_App_top(verilog) because there are no references to its outputs @A:BN291 : coreresetp.v(1646) | Boundary register ECC_App_0.CORERESETP_0.ddr_settled_q1 packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell. @N:BN362 : coreresetp.v(963) | Removing sequential instance ECC_App_0.CORERESETP_0.sdif3_spll_lock_q2 in hierarchy view:work.ECC_App_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(929) | Removing sequential instance ECC_App_0.CORERESETP_0.CONFIG1_DONE_q1 in hierarchy view:work.ECC_App_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(870) | Removing sequential instance ECC_App_0.CORERESETP_0.sdif0_areset_n_rcosc_q1 in hierarchy view:work.ECC_App_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(565) | Removing sequential instance ECC_App_0.CORERESETP_0.MSS_HPMS_READY_int in hierarchy view:work.ECC_App_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(856) | Removing sequential instance ECC_App_0.CORERESETP_0.sm0_areset_n_rcosc in hierarchy view:work.ECC_App_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(755) | Removing sequential instance ECC_App_0.CORERESETP_0.sm0_areset_n_q1 in hierarchy view:work.ECC_App_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(755) | Removing sequential instance ECC_App_0.CORERESETP_0.sm0_areset_n_clk_base in hierarchy view:work.ECC_App_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(526) | Removing sequential instance ECC_App_0.CORERESETP_0.FIC_2_APB_M_PRESET_N_clk_base in hierarchy view:work.ECC_App_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(511) | Removing sequential instance ECC_App_0.CORERESETP_0.RESET_N_M2F_clk_base in hierarchy view:work.ECC_App_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(496) | Removing sequential instance ECC_App_0.CORERESETP_0.POWER_ON_RESET_N_clk_base in hierarchy view:work.ECC_App_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1646) | Removing sequential instance ECC_App_0.CORERESETP_0.ddr_settled_clk_base in hierarchy view:work.ECC_App_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance ECC_App_0.CORERESETP_0.sm0_state[5] in hierarchy view:work.ECC_App_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance ECC_App_0.CORERESETP_0.sm0_state[4] in hierarchy view:work.ECC_App_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance ECC_App_0.CORERESETP_0.sm0_state[3] in hierarchy view:work.ECC_App_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance ECC_App_0.CORERESETP_0.sm0_state[2] in hierarchy view:work.ECC_App_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance ECC_App_0.CORERESETP_0.sm0_state[1] in hierarchy view:work.ECC_App_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(1089) | Removing sequential instance ECC_App_0.CORERESETP_0.sm0_state[0] in hierarchy view:work.ECC_App_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(545) | Removing sequential instance ECC_App_0.CORERESETP_0.mss_ready_state in hierarchy view:work.ECC_App_top(verilog) because there are no references to its outputs @N:BN362 : coreresetp.v(545) | Removing sequential instance ECC_App_0.CORERESETP_0.mss_ready_select in hierarchy view:work.ECC_App_top(verilog) because there are no references to its outputs Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB) Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s 100000.00ns 1 / 0 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 1 non-gated/non-generated clock tree(s) driving 1 clock pin(s) of sequential element(s) 0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 0 instances converted, 0 sequential instances remain driven by gated/generated clocks =========================================== Non-Gated/Non-Generated Clocks ============================================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ----------------------------------------------------------------------------------------------------------------------- ClockId0001 ECC_App_0.CCC_0.GL0_INST CLKINT 1 ECC_App_0.ECC_App_MSS_0.MSS_ADLIB_INST ======================================================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 135MB) Writing Analyst data base D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\synthesis\synwork\ECC_App_top_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 135MB) Writing EDIF Netlist and constraint files @N:BW103 : | Synopsys Constraint File time units using default value of 1ns @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF J-2015.03M-SP1-2 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 135MB) Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB) @W:MT246 : ecc_app_ccc_0_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock ECC_App_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:ECC_App_0.FABOSC_0.RCOSC_25_50MHZ_CCC" @W:MT420 : | Found inferred clock ECC_App_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:ECC_App_0.CCC_0.GL0_net" @S |##### START OF TIMING REPORT #####[ # Timing Report written on Thu Feb 18 15:29:13 2016 # Top view: ECC_App_top Requested Frequency: 100.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: NA Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------------------------- ECC_App_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_0 ECC_App_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_1 ============================================================================================================================================================= @N:MT582 : | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack -------------------------------------------------------------------------------------------------------- ======================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ##### END OF TIMING REPORT #####] Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB) Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB) --------------------------------------- Resource Usage Report for ECC_App_top Mapping to part: m2s090tsfbga484-1 Cell usage: CCC 1 use CLKINT 1 use MSS_075 1 use RCOSC_25_50MHZ 1 use Sequential Cells: SLE 0 uses DSP Blocks: 0 I/O ports: 3 I/O primitives: 2 INBUF 1 use TRIBUFF 1 use Global Clock Buffers: 1 Total LUTs: 0 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 0; LUTs = 0; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 0 + 0 + 0 + 0 = 0; Total number of LUTs after P&R: 0 + 0 + 0 + 0 = 0; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 50MB peak: 135MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Feb 18 15:29:13 2016 ###########################################################]