@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v":376:7:376:9|Synthesizing module VCC
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v":372:7:372:9|Synthesizing module GND
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v":362:7:362:12|Synthesizing module CLKINT
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v":727:7:727:9|Synthesizing module CCC
@N: CG364 :"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\work\ECC_App\CCC_0\ECC_App_CCC_0_FCCC.v":5:7:5:24|Synthesizing module ECC_App_CCC_0_FCCC
@N: CG364 :"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":23:7:23:16|Synthesizing module CoreResetP
@N: CL177 :"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sharing sequential element M3_RESET_N_int.
@N: CL177 :"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q1.
@N: CL177 :"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q1.
@N: CL177 :"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif0_spll_lock_q1.
@N: CL177 :"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q1.
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v":268:7:268:11|Synthesizing module INBUF
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v":280:7:280:13|Synthesizing module TRIBUFF
@N: CG364 :"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\work\ECC_App_MSS\ECC_App_MSS_syn.v":5:7:5:13|Synthesizing module MSS_075
@N: CG364 :"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\work\ECC_App_MSS\ECC_App_MSS.v":9:7:9:17|Synthesizing module ECC_App_MSS
@N: CG364 :"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\Actel\SgCore\OSC\2.0.101\osc_comps.v":51:7:51:24|Synthesizing module RCOSC_25_50MHZ_FAB
@N: CG364 :"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\Actel\SgCore\OSC\2.0.101\osc_comps.v":11:7:11:20|Synthesizing module RCOSC_25_50MHZ
@N: CG364 :"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\work\ECC_App\FABOSC_0\ECC_App_FABOSC_0_OSC.v":5:7:5:26|Synthesizing module ECC_App_FABOSC_0_OSC
@N: CG364 :"D:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v":718:7:718:14|Synthesizing module SYSRESET
@N: CG364 :"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\work\ECC_App\ECC_App.v":9:7:9:13|Synthesizing module ECC_App
@N: CG364 :"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\work\ECC_App_top\ECC_App_top.v":9:7:9:17|Synthesizing module ECC_App_top
@N: CL177 :"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif0_spll_lock_q2.
@N: CL177 :"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q2.
@N: CL177 :"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q2.
@N: CL177 :"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q2.
@N: CL201 :"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Trying to extract state machine for register sdif3_state
@N: CL201 :"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Trying to extract state machine for register sdif2_state
@N: CL201 :"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Trying to extract state machine for register sdif1_state
@N: CL201 :"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Trying to extract state machine for register sdif0_state
@N: CL201 :"D:\11.7_Upload\SF2_Sec_ECC_Services\SF2_ECC_Demo_DF\ECC_App\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Trying to extract state machine for register sm0_state
@N|Running in 64-bit mode

