# Microsemi Physical design constraints file

# Version: v11.7 11.7.0.119

# Design Name: ECC_App_top 

# Input Netlist Format: EDIF 

# Family: SmartFusion2 , Die: M2S090TS , Package: 484 FBGA , Speed grade: -1 

# Date generated: Thu Feb 18 15:29:54 2016 


#
# I/O constraints
#

set_io MMUART_1_RXD -DIRECTION INPUT -pinname G18 -fixed no
set_io MMUART_1_TXD -DIRECTION OUTPUT -pinname H19 -fixed no

#
# Core cell constraints
#

set_location ECC_App_0/FABOSC_0/I_RCOSC_25_50MHZ -fixed no 24 254
set_location ECC_App_0/CCC_0/GL0_INST -fixed no 513 132
set_location ECC_App_0/CCC_0/GL0_INST/U0_RGB1 -fixed no 770 264
set_location ECC_App_0/ECC_App_MSS_0/MSS_ADLIB_INST -fixed no 924 266
set_location ECC_App_0/CCC_0/CCC_INST -fixed no 18 254
