Project Settings
Project Name top_syn Device Name synthesis: Microchip SmartFusion2 : M2S090TS
Implementation Name synthesis Top Module top
Retiming 0 Resource Sharing 1
Fanout Guide 10000 Disable I/O Insertion 0
Disable Sequential Optimizations 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 59 39 0 - 00m:05s - 6/3/2021
4:19:19 PM
(premap)Complete 34 19 0 0m:01s 0m:01s 169MB 6/3/2021
4:19:22 PM
(fpga_mapper)Complete 59 12 0 0m:03s 0m:04s 169MB 6/3/2021
4:19:27 PM
Multi-srs Generator Complete6/3/2021
4:19:20 PM

Area Summary
Sequential Cells 0 DSP Blocks (dsp_used) 0
I/O Cells 2 Global Clock Buffers 1
LUTs (total_luts) 0

Timing Summary
Clock NameReq FreqEst FreqSlack
PUF_Top_0/CCC_0/GL0100.0 MHzNANA
PUF_Top_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT50.0 MHzNANA

Optimizations Summary
Combined Clock Conversion 0 / 1