@W: BN132 :"c:\users\i63442\desktop\v12.6 updates\smart fusion2\new folder\ac0434_sf2_sram_puf_df\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":963:4:963:9|Removing sequential instance PUF_Top_0.CORERESETP_0.sdif3_spll_lock_q1 because it is equivalent to instance PUF_Top_0.CORERESETP_0.CONFIG2_DONE_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\i63442\desktop\v12.6 updates\smart fusion2\new folder\ac0434_sf2_sram_puf_df\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":946:4:946:9|Removing sequential instance PUF_Top_0.CORERESETP_0.CONFIG2_DONE_q1 because it is equivalent to instance PUF_Top_0.CORERESETP_0.CONFIG1_DONE_q1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\i63442\desktop\v12.6 updates\smart fusion2\new folder\ac0434_sf2_sram_puf_df\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":946:4:946:9|Removing sequential instance PUF_Top_0.CORERESETP_0.CONFIG2_DONE_clk_base because it is equivalent to instance PUF_Top_0.CORERESETP_0.sdif3_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\users\i63442\desktop\v12.6 updates\smart fusion2\new folder\ac0434_sf2_sram_puf_df\libero_project\component\actel\directcore\coreresetp\7.1.100\rtl\vlog\core\coreresetp.v":929:4:929:9|Removing sequential instance PUF_Top_0.CORERESETP_0.CONFIG1_DONE_clk_base because it is equivalent to instance PUF_Top_0.CORERESETP_0.sdif3_spll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN114 :"c:\users\i63442\desktop\v12.6 updates\smart fusion2\new folder\ac0434_sf2_sram_puf_df\libero_project\component\work\puf_top\puf_top.v":243:9:243:20|Removing instance PUF_Top_0.SYSRESET_POR (in view: work.top(verilog)) of black box view:ACG4.SYSRESET(PRIM) because it does not drive other instances.
@W: MT246 :"c:\users\i63442\desktop\v12.6 updates\smart fusion2\new folder\ac0434_sf2_sram_puf_df\libero_project\component\work\puf_top\ccc_0\puf_top_ccc_0_fccc.v":20:36:20:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT447 :"c:/users/i63442/desktop/v12.6 updates/smart fusion2/new folder/ac0434_sf2_sram_puf_df/libero_project/designer/top/synthesis.fdc":9:0:9:0|Timing constraint (through [get_nets { PUF_Top_0.CORERESETP_0.ddr_settled PUF_Top_0.CORERESETP_0.count_ddr_enable PUF_Top_0.CORERESETP_0.release_sdif*_core PUF_Top_0.CORERESETP_0.count_sdif*_enable }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design 
@W: MT447 :"c:/users/i63442/desktop/v12.6 updates/smart fusion2/new folder/ac0434_sf2_sram_puf_df/libero_project/designer/top/synthesis.fdc":10:0:10:0|Timing constraint (from [get_cells { PUF_Top_0.CORERESETP_0.MSS_HPMS_READY_int }] to [get_cells { PUF_Top_0.CORERESETP_0.sm0_areset_n_rcosc PUF_Top_0.CORERESETP_0.sm0_areset_n_rcosc_q1 }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"c:/users/i63442/desktop/v12.6 updates/smart fusion2/new folder/ac0434_sf2_sram_puf_df/libero_project/designer/top/synthesis.fdc":11:0:11:0|Timing constraint (from [get_cells { PUF_Top_0.CORERESETP_0.MSS_HPMS_READY_int PUF_Top_0.CORERESETP_0.SDIF*_PERST_N_re }] to [get_cells { PUF_Top_0.CORERESETP_0.sdif*_areset_n_rcosc* }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"c:/users/i63442/desktop/v12.6 updates/smart fusion2/new folder/ac0434_sf2_sram_puf_df/libero_project/designer/top/synthesis.fdc":12:0:12:0|Timing constraint (through [get_nets { PUF_Top_0.CORERESETP_0.CONFIG1_DONE PUF_Top_0.CORERESETP_0.CONFIG2_DONE PUF_Top_0.CORERESETP_0.SDIF*_PERST_N PUF_Top_0.CORERESETP_0.SDIF*_PSEL PUF_Top_0.CORERESETP_0.SDIF*_PWRITE PUF_Top_0.CORERESETP_0.SDIF*_PRDATA[*] PUF_Top_0.CORERESETP_0.SOFT_EXT_RESET_OUT PUF_Top_0.CORERESETP_0.SOFT_RESET_F2M PUF_Top_0.CORERESETP_0.SOFT_M3_RESET PUF_Top_0.CORERESETP_0.SOFT_MDDR_DDR_AXI_S_CORE_RESET PUF_Top_0.CORERESETP_0.SOFT_FDDR_CORE_RESET PUF_Top_0.CORERESETP_0.SOFT_SDIF*_PHY_RESET PUF_Top_0.CORERESETP_0.SOFT_SDIF*_CORE_RESET PUF_Top_0.CORERESETP_0.SOFT_SDIF0_0_CORE_RESET PUF_Top_0.CORERESETP_0.SOFT_SDIF0_1_CORE_RESET }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design 
@W: MT447 :"c:/users/i63442/desktop/v12.6 updates/smart fusion2/new folder/ac0434_sf2_sram_puf_df/libero_project/designer/top/synthesis.fdc":13:0:13:0|Timing constraint (through [get_pins { PUF_Top_0.PUF_Top_MSS_0.MSS_ADLIB_INST.CONFIG_PRESET_N }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design 
@W: MT447 :"c:/users/i63442/desktop/v12.6 updates/smart fusion2/new folder/ac0434_sf2_sram_puf_df/libero_project/designer/top/synthesis.fdc":14:0:14:0|Timing constraint (through [get_pins { PUF_Top_0.SYSRESET_POR.POWER_ON_RESET_N }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design 
