# Timing Multi Corner Report Max Delay Analysis

SmartTime Version 2021.1.0.17

Microsemi Corporation - Microsemi Libero Software Release v2021.1 (Version 2021.1.0.17)

Date: Thu Jun 3 16:21:19 2021

Design | top
Family | SmartFusion2
Die | M2S090TS
Package | 484 FBGA
Temperature Range | 0 - 85 C
Voltage Range | 1.14 - 1.26 V
Speed Grade | -1
Design State | Post-Layout
Data source | Production
Multi Corner Report Operating Conditions | BEST, TYPICAL, WORST
Scenario for Timing Analysis | timing_analysis

## Summary

Clock Domain | Required Period (ns) | Required Frequency (MHz) | Worst Slack (ns) | Operating Conditions
--- | --- | --- | --- | ---
PUF_Top_0/CCC_0/GL0 | 10.000 | 100.000 |  |
PUF_Top_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT | 20.000 | 50.000 |  |

| Worst Slack (ns) | Operating Conditions
--- | --- | ---
Input to Output |  |

## Clock Domain PUF_Top_0/CCC_0/GL0

Info: The maximum frequency of this clock domain is limited by the period of pin PUF_Top_0/PUF_Top_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE

### SET Register to Register

No Path

### SET External Setup

No Path

### SET Clock to Output

| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Clock to Out (ns) | Operating Conditions
--- | --- | --- | --- | --- | --- | --- | --- | ---
Path 1 | PUF_Top_0/PUF_Top_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE | MMUART_1_TXD | 6.004 |  | 12.253 |  | 12.253 | WORST

#### Expanded Path 1

Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge
--- | --- | --- | --- | --- | --- | --- | --- | ---
From: PUF_Top_0/PUF_Top_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE |  |  |  |  |  |  |  |
To: MMUART_1_TXD |  |  |  |  |  |  |  |
data required time |  |  |  |  |  | N/C |  |
data arrival time |  |  |  | - |  | 12.253 |  |
slack |  |  |  |  |  | N/C |  |
Data arrival time calculation |  |  |  |  |  |  |  |
PUF_Top_0/CCC_0/GL0 |  |  |  |  | 0.000 | 0.000 |  |
PUF_Top_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source |  |  | + | 0.000 | 0.000 |  | r
| Clock generation |  |  | + | 3.859 | 3.859 |  |
PUF_Top_0/CCC_0/GL0_INST:An | net | PUF_Top_0/CCC_0/GL0_net |  | + | 0.461 | 4.320 |  | r
PUF_Top_0/CCC_0/GL0_INST:YEn | cell |  | ADLIB:GBM | + | 0.178 | 4.498 | 1 | f
PUF_Top_0/CCC_0/GL0_INST/U0_RGB1:An | net | PUF_Top_0/CCC_0/GL0_INST/U0_YWn_GEast |  | + | 0.603 | 5.101 |  | f
PUF_Top_0/CCC_0/GL0_INST/U0_RGB1:YR | cell |  | ADLIB:RGB | + | 0.316 | 5.417 | 1 | r
PUF_Top_0/PUF_Top_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:B | net | PUF_Top_0/CCC_0/GL0_INST/U0_RGB1_YR |  | + | 0.407 | 5.824 |  | r
PUF_Top_0/PUF_Top_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_268:IPB | cell |  | ADLIB:IP_INTERFACE | + | 0.209 | 6.033 | 1 | r
PUF_Top_0/PUF_Top_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:CLK_BASE | net | PUF_Top_0/PUF_Top_MSS_0/MSS_ADLIB_INST/CLK_BASE_net |  | + | 0.216 | 6.249 |  | r
PUF_Top_0/PUF_Top_MSS_0/MSS_ADLIB_INST/INST_MSS_075_IP:MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT | cell |  | ADLIB:MSS_075_IP | + | 2.019 | 8.268 | 1 | f
PUF_Top_0/PUF_Top_MSS_0/MMUART_1_TXD_PAD/U_IOPAD:D | net | PUF_Top_0/PUF_Top_MSS_0/MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT |  | + | 1.319 | 9.587 |  | f
PUF_Top_0/PUF_Top_MSS_0/MMUART_1_TXD_PAD/U_IOPAD:PAD | cell |  | ADLIB:IOPAD_TRI | + | 2.666 | 12.253 | 0 | f
MMUART_1_TXD | net | MMUART_1_TXD |  | + | 0.000 | 12.253 |  | f
data arrival time |  |  |  |  |  | 12.253 |  |
Data required time calculation |  |  |  |  |  |  |  |
PUF_Top_0/CCC_0/GL0 |  |  |  |  | N/C | N/C |  |
PUF_Top_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 | Clock source |  |  | + | 0.000 | N/C |  | r
| Clock generation |  |  | + | 3.859 | N/C |  |
MMUART_1_TXD |  |  |  |  |  | N/C |  | f
Operating Conditions | WORST

### SET Register to Asynchronous

No Path

### SET External Recovery

No Path

### SET Asynchronous to Register

No Path

## Clock Domain PUF_Top_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT

### SET Register to Register

No Path

### SET External Setup

No Path

### SET Clock to Output

No Path

### SET Register to Asynchronous

No Path

### SET External Recovery

No Path

### SET Asynchronous to Register

No Path

## Path Set Pin to Pin

### SET Input to Output

No Path

## Path Set User Sets