@W: BN132 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int,  because it is equivalent to instance I2C_Multi_Master_Slave_0.CORERESETP_0.FDDR_CORE_RESET_N_int
@W: MT530 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\corei2c\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":7015:0:7015:5|Found inferred clock I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock which controls 248 sequential elements including I2C_Multi_Master_Slave_0.COREI2C_0_0.CI2CIlI\[0\]\.ui2c.CI2ClO0I[4:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":912:4:912:9|Found inferred clock I2C_Multi_Master_Slave_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 15 sequential elements including I2C_Multi_Master_Slave_0.CORERESETP_0.sdif3_areset_n_rcosc_q1. This clock has no specified timing constraint which may adversely impact design performance. 
