@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG364 :"F:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v":286:7:286:11|Synthesizing module BIBUF
@N: CG364 :"F:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v":376:7:376:9|Synthesizing module VCC
@N: CG364 :"F:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v":372:7:372:9|Synthesizing module GND
@N: CG364 :"F:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v":362:7:362:12|Synthesizing module CLKINT
@N: CG364 :"F:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v":727:7:727:9|Synthesizing module CCC
@N: CG364 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\work\I2C_Multi_Master_Slave\CCC_0\I2C_Multi_Master_Slave_CCC_0_FCCC.v":5:7:5:39|Synthesizing module I2C_Multi_Master_Slave_CCC_0_FCCC
@N: CG364 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_muxptob3.v":30:7:30:23|Synthesizing module COREAPB3_MUXPTOB3
@N: CG364 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":31:7:31:14|Synthesizing module CoreAPB3
@N: CG364 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2c.v":7:0:7:6|Synthesizing module COREI2C
@N: CG364 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":7:0:7:10|Synthesizing module COREI2CREAL
@N: CG364 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":23:7:23:16|Synthesizing module CoreResetP
@N: CL177 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sharing sequential element M3_RESET_N_int.
@N: CL177 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q1.
@N: CL177 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q1.
@N: CL177 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif0_spll_lock_q1.
@N: CL177 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q1.
@N: CG364 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\SgCore\OSC\2.0.101\osc_comps.v":51:7:51:24|Synthesizing module RCOSC_25_50MHZ_FAB
@N: CG364 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\SgCore\OSC\2.0.101\osc_comps.v":11:7:11:20|Synthesizing module RCOSC_25_50MHZ
@N: CG364 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\work\I2C_Multi_Master_Slave\FABOSC_0\I2C_Multi_Master_Slave_FABOSC_0_OSC.v":5:7:5:41|Synthesizing module I2C_Multi_Master_Slave_FABOSC_0_OSC
@N: CG364 :"F:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v":268:7:268:11|Synthesizing module INBUF
@N: CG364 :"F:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v":280:7:280:13|Synthesizing module TRIBUFF
@N: CG364 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\work\I2C_Multi_Master_Slave_MSS\I2C_Multi_Master_Slave_MSS_syn.v":5:7:5:13|Synthesizing module MSS_075
@N: CG364 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\work\I2C_Multi_Master_Slave_MSS\I2C_Multi_Master_Slave_MSS.v":9:7:9:32|Synthesizing module I2C_Multi_Master_Slave_MSS
@N: CG364 :"F:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v":718:7:718:14|Synthesizing module SYSRESET
@N: CG364 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\work\I2C_Multi_Master_Slave\I2C_Multi_Master_Slave.v":9:7:9:28|Synthesizing module I2C_Multi_Master_Slave
@N: CG364 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\work\I2C_Multi_Master_Slave_top\I2C_Multi_Master_Slave_top.v":9:7:9:32|Synthesizing module I2C_Multi_Master_Slave_top
@N: CL177 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif0_spll_lock_q2.
@N: CL177 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif1_spll_lock_q2.
@N: CL177 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element sdif2_spll_lock_q2.
@N: CL177 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Sharing sequential element fpll_lock_q2.
@N: CL201 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Trying to extract state machine for register sdif3_state
@N: CL201 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Trying to extract state machine for register sdif2_state
@N: CL201 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Trying to extract state machine for register sdif1_state
@N: CL201 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Trying to extract state machine for register sdif0_state
@N: CL201 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Trying to extract state machine for register sm0_state
@N: CL201 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":8331:0:8331:5|Trying to extract state machine for register CI2Cl0lI
@N: CL201 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":7755:0:7755:5|Trying to extract state machine for register CI2COO0I
@N: CL201 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":5560:0:5560:5|Trying to extract state machine for register CI2CI1lI
@N|Running in 64-bit mode

