#--  Synopsys, Inc.
#--  Version J-2015.03M-SP1-2
#--  Project file F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\synthesis\run_options.txt
#--  Written on Fri Feb 19 14:35:32 2016


#project files
add_file -verilog "F:/M2S_I2C_DF/Libero_Project/I2C_Multi_Master_Slave/component/Actel/DirectCore/COREI2C/7.0.102/rtl/vlog/core_obfuscated/corei2creal.v"
add_file -verilog "F:/M2S_I2C_DF/Libero_Project/I2C_Multi_Master_Slave/component/Actel/DirectCore/COREI2C/7.0.102/rtl/vlog/core_obfuscated/corei2c.v"
add_file -verilog "F:/M2S_I2C_DF/Libero_Project/I2C_Multi_Master_Slave/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp_pcie_hotreset.v"
add_file -verilog "F:/M2S_I2C_DF/Libero_Project/I2C_Multi_Master_Slave/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp.v"
add_file -verilog "F:/M2S_I2C_DF/Libero_Project/I2C_Multi_Master_Slave/component/work/I2C_Multi_Master_Slave/CCC_0/I2C_Multi_Master_Slave_CCC_0_FCCC.v"
add_file -verilog "F:/M2S_I2C_DF/Libero_Project/I2C_Multi_Master_Slave/component/Actel/SgCore/OSC/2.0.101/osc_comps.v"
add_file -verilog "F:/M2S_I2C_DF/Libero_Project/I2C_Multi_Master_Slave/component/work/I2C_Multi_Master_Slave/FABOSC_0/I2C_Multi_Master_Slave_FABOSC_0_OSC.v"
add_file -verilog "F:/M2S_I2C_DF/Libero_Project/I2C_Multi_Master_Slave/component/work/I2C_Multi_Master_Slave_MSS/I2C_Multi_Master_Slave_MSS_syn.v"
add_file -verilog "F:/M2S_I2C_DF/Libero_Project/I2C_Multi_Master_Slave/component/work/I2C_Multi_Master_Slave_MSS/I2C_Multi_Master_Slave_MSS.v"
add_file -verilog -lib COREAPB3_LIB "F:/M2S_I2C_DF/Libero_Project/I2C_Multi_Master_Slave/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3_muxptob3.v"
add_file -verilog -lib COREAPB3_LIB "F:/M2S_I2C_DF/Libero_Project/I2C_Multi_Master_Slave/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3_iaddr_reg.v"
add_file -verilog -lib COREAPB3_LIB "F:/M2S_I2C_DF/Libero_Project/I2C_Multi_Master_Slave/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3.v"
add_file -verilog "F:/M2S_I2C_DF/Libero_Project/I2C_Multi_Master_Slave/component/work/I2C_Multi_Master_Slave/I2C_Multi_Master_Slave.v"
add_file -verilog "F:/M2S_I2C_DF/Libero_Project/I2C_Multi_Master_Slave/component/work/I2C_Multi_Master_Slave_top/I2C_Multi_Master_Slave_top.v"



#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std v2001

#device options
set_option -technology SmartFusion2
set_option -part M2S090TS
set_option -package FBGA484
set_option -speed_grade STD
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "I2C_Multi_Master_Slave_top"

# mapper_options
set_option -frequency 100.000
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -srs_instrumentation 1

# actel_options
set_option -rw_check_on_ram 0

# Microsemi G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 12
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -disable_io_insertion 0
set_option -opcond COMTC
set_option -retiming 0
set_option -report_path 0
set_option -update_models_cp 0
set_option -preserve_registers 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./I2C_Multi_Master_Slave_top.edn"
impl -active "synthesis"
