@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 
@N: FA239 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\corei2c\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":2566:0:2566:3|ROM CI2COlll\.CI2COl0I_2[4:0] mapped in logic.
@N: FA239 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\corei2c\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":2566:0:2566:3|ROM CI2COlll\.CI2COl0I_2[4:0] mapped in logic.
@N: MO106 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\corei2c\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":2566:0:2566:3|Found ROM, 'CI2COlll\.CI2COl0I_2[4:0]', 29 words by 5 bits 
@N: FA239 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\corei2c\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":2566:0:2566:3|ROM CI2COlll\.CI2COl0I_2[4:0] mapped in logic.
@N: FA239 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\corei2c\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":2566:0:2566:3|ROM CI2COlll\.CI2COl0I_2[4:0] mapped in logic.
@N: MO106 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\corei2c\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":2566:0:2566:3|Found ROM, 'CI2COlll\.CI2COl0I_2[4:0]', 29 words by 5 bits 
@N: BN362 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.INIT_DONE_int in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs 
@N: BN362 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm0_state[6] in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs 
@N: BN362 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.ddr_settled in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs 
@N: BN362 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1646:4:1646:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.ddr_settled_q1 in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs 
@N: BN362 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif3_spll_lock_q2 in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs 
@N: BN362 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":929:4:929:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.CONFIG1_DONE_q1 in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs 
@N: BN362 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":870:4:870:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif0_areset_n_rcosc_q1 in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs 
@N: BN362 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":856:4:856:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm0_areset_n_rcosc in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs 
@N: BN362 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":755:4:755:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm0_areset_n_q1 in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs 
@N: BN362 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":755:4:755:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm0_areset_n_clk_base in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs 
@N: BN362 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1646:4:1646:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.ddr_settled_clk_base in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs 
@N: BN362 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm0_state[5] in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs 
@N: BN362 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm0_state[4] in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs 
@N: BN362 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm0_state[3] in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs 
@N: BN362 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm0_state[2] in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs 
@N: BN362 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm0_state[1] in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs 
@N: BN362 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm0_state[0] in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs 
@N: BN362 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\corei2c\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":5560:0:5560:5|Removing sequential instance I2C_Multi_Master_Slave_0.COREI2C_1_0.CI2CIlI\[0\]\.ui2c.CI2CI1lI[7] in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs 
@N: BN362 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\corei2c\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":5560:0:5560:5|Removing sequential instance I2C_Multi_Master_Slave_0.COREI2C_0_0.CI2CIlI\[0\]\.ui2c.CI2CI1lI[7] in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs 
@N: FP130 |Promoting Net un1_I2C_Multi_Master_Slave_0_8 on CLKINT  I_98 
@N: BW103 |Synopsys Constraint File time units using default value of 1ns 
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
@N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
@N: MT582 |Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack
