@W: CG775 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":31:7:31:14|Found Component CoreAPB3 in library COREAPB3_LIB
@W: CG360 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":244:12:244:20|No assignment to wire IA_PRDATA
@W: CG133 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":1038:0:1038:7|No assignment to CI2CIl0I
@W: CG133 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":1041:0:1041:7|No assignment to CI2Cll0I
@W: CG133 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":1047:0:1047:7|No assignment to CI2CI00I
@W: CG133 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":1053:0:1053:7|No assignment to CI2CO10I
@W: CG133 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":1056:0:1056:7|No assignment to CI2CI10I
@W: CG133 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":1059:0:1059:7|No assignment to CI2Cl10I
@W: CG133 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":1106:0:1106:7|No assignment to CI2Cl11I
@W: CG133 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":1108:0:1108:7|No assignment to CI2COOOl
@W: CG133 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":1111:0:1111:7|No assignment to CI2CIOOl
@W: CG133 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":1113:0:1113:7|No assignment to CI2ClOOl
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":8759:0:8759:5|Pruning register CI2ClllI[3:0] 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":8643:0:8643:5|Pruning register CI2ClIlI[6:0] 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":8512:0:8512:5|Pruning register CI2ClOlI[7:0] 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":3385:0:3385:5|Pruning register CI2CIl1I 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":3385:0:3385:5|Pruning register CI2CO01I 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":3385:0:3385:5|Pruning register CI2Cll1I 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":7015:0:7015:5|Pruning register CI2CI01I 
@W: CL190 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":7015:0:7015:5|Optimizing register bit CI2Cl01I to a constant 1
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":7015:0:7015:5|Pruning register CI2Cl01I 
@W: CG133 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2c.v":407:0:407:5|No assignment to CI2CI1
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2c.v":537:0:537:5|Pruning register CI2CI0 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2c.v":537:0:537:5|Pruning register CI2Cl0 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2c.v":453:0:453:5|Pruning register CI2CO0[12:0] 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Pruning register count_ddr[13:0] 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1581:4:1581:9|Pruning register count_sdif3[12:0] 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1549:4:1549:9|Pruning register count_sdif2[12:0] 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1517:4:1517:9|Pruning register count_sdif1[12:0] 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1485:4:1485:9|Pruning register count_sdif0[12:0] 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif0_enable_q1 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif1_enable_q1 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif2_enable_q1 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif3_enable_q1 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif0_enable_rcosc 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif1_enable_rcosc 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif2_enable_rcosc 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_sdif3_enable_rcosc 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_ddr_enable_q1 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1455:4:1455:9|Pruning register count_ddr_enable_rcosc 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Pruning register count_sdif3_enable 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Pruning register count_sdif2_enable 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Pruning register count_sdif1_enable 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Pruning register count_sdif0_enable 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning register count_ddr_enable 
@W: CL190 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Optimizing register bit EXT_RESET_OUT_int to a constant 0
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Pruning register release_ext_reset 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning register EXT_RESET_OUT_int 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":1433:4:1433:9|Pruning register sm2_state[2:0] 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning register sm2_areset_n_q1 
@W: CL169 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":783:4:783:9|Pruning register sm2_areset_n_clk_base 
@W: CL157 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\work\I2C_Multi_Master_Slave\FABOSC_0\I2C_Multi_Master_Slave_FABOSC_0_OSC.v":17:7:17:20|*Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible.
@W: CL157 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\work\I2C_Multi_Master_Slave\FABOSC_0\I2C_Multi_Master_Slave_FABOSC_0_OSC.v":18:7:18:20|*Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible.
@W: CL157 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\work\I2C_Multi_Master_Slave\FABOSC_0\I2C_Multi_Master_Slave_FABOSC_0_OSC.v":19:7:19:16|*Output XTLOSC_CCC has undriven bits -- simulation mismatch possible.
@W: CL157 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\work\I2C_Multi_Master_Slave\FABOSC_0\I2C_Multi_Master_Slave_FABOSC_0_OSC.v":20:7:20:16|*Output XTLOSC_O2F has undriven bits -- simulation mismatch possible.
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\work\I2C_Multi_Master_Slave\FABOSC_0\I2C_Multi_Master_Slave_FABOSC_0_OSC.v":14:7:14:9|Input XTL is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":29:20:29:28|Input CLK_LTSSM is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":56:20:56:28|Input FPLL_LOCK is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":59:20:59:34|Input SDIF0_SPLL_LOCK is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":68:20:68:34|Input SDIF1_SPLL_LOCK is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":72:20:72:34|Input SDIF2_SPLL_LOCK is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":76:20:76:34|Input SDIF3_SPLL_LOCK is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":90:20:90:29|Input SDIF0_PSEL is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":91:20:91:31|Input SDIF0_PWRITE is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":92:20:92:31|Input SDIF0_PRDATA is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":93:20:93:29|Input SDIF1_PSEL is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":94:20:94:31|Input SDIF1_PWRITE is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":95:20:95:31|Input SDIF1_PRDATA is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":96:20:96:29|Input SDIF2_PSEL is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":97:20:97:31|Input SDIF2_PWRITE is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":98:20:98:31|Input SDIF2_PRDATA is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":99:20:99:29|Input SDIF3_PSEL is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":100:20:100:31|Input SDIF3_PWRITE is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":101:20:101:31|Input SDIF3_PRDATA is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":107:20:107:37|Input SOFT_EXT_RESET_OUT is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":108:20:108:33|Input SOFT_RESET_F2M is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":109:20:109:32|Input SOFT_M3_RESET is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":110:20:110:49|Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":111:20:111:39|Input SOFT_FDDR_CORE_RESET is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":112:20:112:39|Input SOFT_SDIF0_PHY_RESET is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":113:20:113:40|Input SOFT_SDIF0_CORE_RESET is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":114:20:114:39|Input SOFT_SDIF1_PHY_RESET is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":115:20:115:40|Input SOFT_SDIF1_CORE_RESET is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":116:20:116:39|Input SOFT_SDIF2_PHY_RESET is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":117:20:117:40|Input SOFT_SDIF2_CORE_RESET is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":118:20:118:39|Input SOFT_SDIF3_PHY_RESET is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":119:20:119:40|Input SOFT_SDIF3_CORE_RESET is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":123:20:123:42|Input SOFT_SDIF0_0_CORE_RESET is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v":124:20:124:42|Input SOFT_SDIF0_1_CORE_RESET is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":88:0:88:10|Input pulse_215us is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":104:0:104:10|Input seradr1apb0 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":149:0:149:10|Input SMBALERT_NI is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v":155:0:155:8|Input SMBSUS_NI is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2c.v":97:0:97:3|Input BCLK is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":72:36:72:40|Input IADDR is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":73:13:73:19|Input PRESETN is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":74:13:74:16|Input PCLK is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":106:18:106:25|Input PRDATAS2 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":107:18:107:25|Input PRDATAS3 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":108:18:108:25|Input PRDATAS4 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":109:18:109:25|Input PRDATAS5 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":110:18:110:25|Input PRDATAS6 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":111:18:111:25|Input PRDATAS7 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":112:18:112:25|Input PRDATAS8 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":113:18:113:25|Input PRDATAS9 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":114:18:114:26|Input PRDATAS10 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":115:18:115:26|Input PRDATAS11 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":116:18:116:26|Input PRDATAS12 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":117:18:117:26|Input PRDATAS13 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":118:18:118:26|Input PRDATAS14 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":119:18:119:26|Input PRDATAS15 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":123:13:123:20|Input PREADYS2 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":124:13:124:20|Input PREADYS3 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":125:13:125:20|Input PREADYS4 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":126:13:126:20|Input PREADYS5 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":127:13:127:20|Input PREADYS6 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":128:13:128:20|Input PREADYS7 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":129:13:129:20|Input PREADYS8 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":130:13:130:20|Input PREADYS9 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":131:13:131:21|Input PREADYS10 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":132:13:132:21|Input PREADYS11 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":133:13:133:21|Input PREADYS12 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":134:13:134:21|Input PREADYS13 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":135:13:135:21|Input PREADYS14 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":136:13:136:21|Input PREADYS15 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":140:13:140:21|Input PSLVERRS2 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":141:13:141:21|Input PSLVERRS3 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":142:13:142:21|Input PSLVERRS4 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":143:13:143:21|Input PSLVERRS5 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":144:13:144:21|Input PSLVERRS6 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":145:13:145:21|Input PSLVERRS7 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":146:13:146:21|Input PSLVERRS8 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":147:13:147:21|Input PSLVERRS9 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":148:13:148:22|Input PSLVERRS10 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":149:13:149:22|Input PSLVERRS11 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":150:13:150:22|Input PSLVERRS12 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":151:13:151:22|Input PSLVERRS13 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":152:13:152:22|Input PSLVERRS14 is unused
@W: CL159 :"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":153:13:153:22|Input PSLVERRS15 is unused

