`

    #Build: Synplify Pro J-2015.03M-SP1-2, Build 266R, Dec 14 2015
    #install: F:\Microsemi\Libero_SoC_v11.7\Synplify
    #OS: Windows 7 6.1
    #Hostname: W764-HARISAKOL

    #Implementation: synthesis

    Synopsys HDL Compiler, version comp201503sp1p1, Build 240R, built Dec  1 2015
    @N: :  | Running in 64-bit mode
    Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

    Synopsys Verilog Compiler, version comp201503sp1p1, Build 240R, built Dec  1 2015
    @N: :  | Running in 64-bit mode
    Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

    @I::"F:\Microsemi\Libero_SoC_v11.7\Synplify\lib\generic\smartfusion2.v"
    @I::"F:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\hypermods.v"
    @I::"F:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\umr_capim.v"
    @I::"F:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\scemi_objects.v"
    @I::"F:\Microsemi\Libero_SoC_v11.7\Synplify\lib\vlog\scemi_pipes.svh"
    @I::"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2creal.v"
    @I::"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\COREI2C\7.0.102\rtl\vlog\core_obfuscated\corei2c.v"
    @I::"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v"
    @I::"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v"
    @I::"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\work\I2C_Multi_Master_Slave\CCC_0\I2C_Multi_Master_Slave_CCC_0_FCCC.v"
    @I::"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\SgCore\OSC\2.0.101\osc_comps.v"
    @I::"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\work\I2C_Multi_Master_Slave\FABOSC_0\I2C_Multi_Master_Slave_FABOSC_0_OSC.v"
    @I::"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\work\I2C_Multi_Master_Slave_MSS\I2C_Multi_Master_Slave_MSS_syn.v"
    @I::"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\work\I2C_Multi_Master_Slave_MSS\I2C_Multi_Master_Slave_MSS.v"
    @I::"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_muxptob3.v"
    @I::"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_iaddr_reg.v"
    @I::"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v"
    @I::"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\work\I2C_Multi_Master_Slave\I2C_Multi_Master_Slave.v"
    @I::"F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\work\I2C_Multi_Master_Slave_top\I2C_Multi_Master_Slave_top.v"
    Verilog syntax check successful!
    File F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\work\I2C_Multi_Master_Slave\CCC_0\I2C_Multi_Master_Slave_CCC_0_FCCC.v changed - recompiling
    File F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\work\I2C_Multi_Master_Slave\FABOSC_0\I2C_Multi_Master_Slave_FABOSC_0_OSC.v changed - recompiling
    File F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\work\I2C_Multi_Master_Slave_MSS\I2C_Multi_Master_Slave_MSS_syn.v changed - recompiling
    File F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\work\I2C_Multi_Master_Slave_MSS\I2C_Multi_Master_Slave_MSS.v changed - recompiling
    File F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\work\I2C_Multi_Master_Slave\I2C_Multi_Master_Slave.v changed - recompiling
    File F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\component\work\I2C_Multi_Master_Slave_top\I2C_Multi_Master_Slave_top.v changed - recompiling
    Selecting top level module I2C_Multi_Master_Slave_top
    @N:CG364 : smartfusion2.v(286) | Synthesizing module BIBUF

    @N:CG364 : smartfusion2.v(376) | Synthesizing module VCC

    @N:CG364 : smartfusion2.v(372) | Synthesizing module GND

    @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT

    @N:CG364 : smartfusion2.v(727) | Synthesizing module CCC

    @N:CG364 : I2C_Multi_Master_Slave_CCC_0_FCCC.v(5) | Synthesizing module I2C_Multi_Master_Slave_CCC_0_FCCC

    @W:CG775 : coreapb3.v(31) | Found Component CoreAPB3 in library COREAPB3_LIB
    @N:CG364 : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3

    @N:CG364 : coreapb3.v(31) | Synthesizing module CoreAPB3

    	APB_DWIDTH=6'b100000
    	IADDR_OPTION=32'b00000000000000000000000000000000
    	APBSLOT0ENABLE=1'b1
    	APBSLOT1ENABLE=1'b1
    	APBSLOT2ENABLE=1'b0
    	APBSLOT3ENABLE=1'b0
    	APBSLOT4ENABLE=1'b0
    	APBSLOT5ENABLE=1'b0
    	APBSLOT6ENABLE=1'b0
    	APBSLOT7ENABLE=1'b0
    	APBSLOT8ENABLE=1'b0
    	APBSLOT9ENABLE=1'b0
    	APBSLOT10ENABLE=1'b0
    	APBSLOT11ENABLE=1'b0
    	APBSLOT12ENABLE=1'b0
    	APBSLOT13ENABLE=1'b0
    	APBSLOT14ENABLE=1'b0
    	APBSLOT15ENABLE=1'b0
    	SC_0=1'b0
    	SC_1=1'b0
    	SC_2=1'b0
    	SC_3=1'b0
    	SC_4=1'b0
    	SC_5=1'b0
    	SC_6=1'b0
    	SC_7=1'b0
    	SC_8=1'b0
    	SC_9=1'b0
    	SC_10=1'b0
    	SC_11=1'b0
    	SC_12=1'b0
    	SC_13=1'b0
    	SC_14=1'b0
    	SC_15=1'b0
    	MADDR_BITS=6'b010000
    	UPR_NIBBLE_POSN=4'b0011
    	FAMILY=32'b00000000000000000000000000010011
    	SYNC_RESET=32'b00000000000000000000000000000000
    	IADDR_NOTINUSE=32'b00000000000000000000000000000000
    	IADDR_EXTERNAL=32'b00000000000000000000000000000001
    	IADDR_SLOT0=32'b00000000000000000000000000000010
    	IADDR_SLOT1=32'b00000000000000000000000000000011
    	IADDR_SLOT2=32'b00000000000000000000000000000100
    	IADDR_SLOT3=32'b00000000000000000000000000000101
    	IADDR_SLOT4=32'b00000000000000000000000000000110
    	IADDR_SLOT5=32'b00000000000000000000000000000111
    	IADDR_SLOT6=32'b00000000000000000000000000001000
    	IADDR_SLOT7=32'b00000000000000000000000000001001
    	IADDR_SLOT8=32'b00000000000000000000000000001010
    	IADDR_SLOT9=32'b00000000000000000000000000001011
    	IADDR_SLOT10=32'b00000000000000000000000000001100
    	IADDR_SLOT11=32'b00000000000000000000000000001101
    	IADDR_SLOT12=32'b00000000000000000000000000001110
    	IADDR_SLOT13=32'b00000000000000000000000000001111
    	IADDR_SLOT14=32'b00000000000000000000000000010000
    	IADDR_SLOT15=32'b00000000000000000000000000010001
    	SL0=16'b0000000000000001
    	SL1=16'b0000000000000010
    	SL2=16'b0000000000000000
    	SL3=16'b0000000000000000
    	SL4=16'b0000000000000000
    	SL5=16'b0000000000000000
    	SL6=16'b0000000000000000
    	SL7=16'b0000000000000000
    	SL8=16'b0000000000000000
    	SL9=16'b0000000000000000
    	SL10=16'b0000000000000000
    	SL11=16'b0000000000000000
    	SL12=16'b0000000000000000
    	SL13=16'b0000000000000000
    	SL14=16'b0000000000000000
    	SL15=16'b0000000000000000
    	SC=16'b0000000000000000
    	SC_qual=16'b0000000000000000
       Generated name = CoreAPB3_Z1

    @W:CG360 : coreapb3.v(244) | No assignment to wire IA_PRDATA

    @N:CG364 : corei2c.v(7) | Synthesizing module COREI2C

    	FAMILY=32'b00000000000000000000000000010001
    	OPERATING_MODE=32'b00000000000000000000000000000000
    	BAUD_RATE_FIXED=32'b00000000000000000000000000000000
    	BAUD_RATE_VALUE=32'b00000000000000000000000000000000
    	BCLK_ENABLED=32'b00000000000000000000000000000000
    	GLITCHREG_NUM=32'b00000000000000000000000000000011
    	SMB_EN=32'b00000000000000000000000000000000
    	IPMI_EN=32'b00000000000000000000000000000000
    	FREQUENCY=32'b00000000000000000000000000011110
    	FIXED_SLAVE0_ADDR_EN=32'b00000000000000000000000000000000
    	FIXED_SLAVE0_ADDR_VALUE=32'b00000000000000000000000000000000
    	ADD_SLAVE1_ADDRESS_EN=32'b00000000000000000000000000000000
    	FIXED_SLAVE1_ADDR_EN=32'b00000000000000000000000000000000
    	FIXED_SLAVE1_ADDR_VALUE=32'b00000000000000000000000000000000
    	I2C_NUM=32'b00000000000000000000000000000001
    	CI2CII=5'b01100
    	CI2ClI=8'b00000000
    	CI2COl=5'b11100
    	CI2CIl=8'b00000000
       Generated name = COREI2C_Z2

    @N:CG364 : corei2creal.v(7) | Synthesizing module COREI2CREAL

    	FAMILY=32'b00000000000000000000000000010001
    	OPERATING_MODE=32'b00000000000000000000000000000000
    	BAUD_RATE_FIXED=32'b00000000000000000000000000000000
    	BAUD_RATE_VALUE=32'b00000000000000000000000000000000
    	BCLK_ENABLED=32'b00000000000000000000000000000000
    	GLITCHREG_NUM=32'b00000000000000000000000000000011
    	SMB_EN=32'b00000000000000000000000000000000
    	IPMI_EN=32'b00000000000000000000000000000000
    	FREQUENCY=32'b00000000000000000000000000011110
    	FIXED_SLAVE0_ADDR_EN=32'b00000000000000000000000000000000
    	FIXED_SLAVE0_ADDR_VALUE=32'b00000000000000000000000000000000
    	ADD_SLAVE1_ADDRESS_EN=32'b00000000000000000000000000000000
    	FIXED_SLAVE1_ADDR_EN=32'b00000000000000000000000000000000
    	FIXED_SLAVE1_ADDR_VALUE=32'b00000000000000000000000000000000
    	CI2CI0l=32'b00000000000000000000000000000100
    	CI2Cl0l=4'b0101
    	CI2CO1l=1'b0
    	CI2CI1l=1'b0
    	CI2Cl1l=5'b00000
    	CI2COO0=8'b00000000
    	CI2CIO0=5'b00100
    	CI2ClO0=8'b11111000
    	CI2COI0=5'b01000
    	CI2CII0=8'b00000000
    	CI2ClI0=5'b10000
    	CI2COl0=8'b01x1x000
    	CI2CII=5'b01100
    	CI2ClI=8'b00000000
    	CI2COl=5'b11100
    	CI2CIl=8'b00000000
    	CI2CIl0=5'b00000
    	CI2Cll0=5'b00001
    	CI2CO00=5'b11101
    	CI2CI00=5'b00010
    	CI2Cl00=5'b00011
    	CI2CO10=5'b00100
    	CI2CI10=5'b00101
    	CI2Cl10=5'b00110
    	CI2COO1=5'b00111
    	CI2CIO1=5'b01000
    	CI2ClO1=5'b01001
    	CI2COI1=5'b01010
    	CI2CII1=5'b01011
    	CI2ClI1=5'b01100
    	CI2COl1=5'b01101
    	CI2CIl1=5'b01110
    	CI2Cll1=5'b01111
    	CI2CO01=5'b10000
    	CI2CI01=5'b10001
    	CI2Cl01=5'b10010
    	CI2CO11=5'b10011
    	CI2CI11=5'b10100
    	CI2Cl11=5'b10101
    	CI2COOOI=5'b10110
    	CI2CIOOI=5'b10111
    	CI2ClOOI=5'b11000
    	CI2COIOI=5'b11001
    	CI2CIIOI=5'b11010
    	CI2ClIOI=5'b11011
    	CI2COlOI=5'b11100
    	CI2CIlOI=3'b000
    	CI2CllOI=3'b001
    	CI2CO0OI=3'b010
    	CI2CI0OI=3'b011
    	CI2Cl0OI=3'b100
    	CI2CO1OI=3'b101
    	CI2CI1OI=3'b110
    	CI2Cl1OI=3'b000
    	CI2COOII=3'b001
    	CI2CIOII=3'b010
    	CI2ClOII=3'b011
    	CI2COIII=3'b100
    	CI2CIIII=3'b101
    	CI2ClIII=3'b110
    	CI2COlII=3'b111
    	CI2CIlII=3'b000
    	CI2CllII=3'b001
    	CI2CO0II=3'b010
    	CI2CI0II=3'b011
    	CI2Cl0II=3'b100
    	CI2CO1II=3'b101
    	CI2CI1II=3'b110
    	CI2Cl1II=32'b00000000000000000000000000001000
    	CI2COOlI=32'b00000000000000000000000000000111
       Generated name = COREI2CREAL_Z3

    @W:CG133 : corei2creal.v(1038) | No assignment to CI2CIl0I
    @W:CG133 : corei2creal.v(1041) | No assignment to CI2Cll0I
    @W:CG133 : corei2creal.v(1047) | No assignment to CI2CI00I
    @W:CG133 : corei2creal.v(1053) | No assignment to CI2CO10I
    @W:CG133 : corei2creal.v(1056) | No assignment to CI2CI10I
    @W:CG133 : corei2creal.v(1059) | No assignment to CI2Cl10I
    @W:CG133 : corei2creal.v(1106) | No assignment to CI2Cl11I
    @W:CG133 : corei2creal.v(1108) | No assignment to CI2COOOl
    @W:CG133 : corei2creal.v(1111) | No assignment to CI2CIOOl
    @W:CG133 : corei2creal.v(1113) | No assignment to CI2ClOOl
    @W:CL169 : corei2creal.v(8759) | Pruning register CI2ClllI[3:0]

    @W:CL169 : corei2creal.v(8643) | Pruning register CI2ClIlI[6:0]

    @W:CL169 : corei2creal.v(8512) | Pruning register CI2ClOlI[7:0]

    @W:CL169 : corei2creal.v(3385) | Pruning register CI2CIl1I

    @W:CL169 : corei2creal.v(3385) | Pruning register CI2CO01I

    @W:CL169 : corei2creal.v(3385) | Pruning register CI2Cll1I

    @W:CL169 : corei2creal.v(7015) | Pruning register CI2CI01I

    @W:CL190 : corei2creal.v(7015) | Optimizing register bit CI2Cl01I to a constant 1
    @W:CL169 : corei2creal.v(7015) | Pruning register CI2Cl01I

    @W:CG133 : corei2c.v(407) | No assignment to CI2CI1
    @W:CL169 : corei2c.v(537) | Pruning register CI2CI0

    @W:CL169 : corei2c.v(537) | Pruning register CI2Cl0

    @W:CL169 : corei2c.v(453) | Pruning register CI2CO0[12:0]

    @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP

    	FAMILY=32'b00000000000000000000000000010011
    	EXT_RESET_CFG=32'b00000000000000000000000000000000
    	DEVICE_VOLTAGE=32'b00000000000000000000000000000010
    	MDDR_IN_USE=32'b00000000000000000000000000000000
    	FDDR_IN_USE=32'b00000000000000000000000000000000
    	SDIF0_IN_USE=32'b00000000000000000000000000000000
    	SDIF1_IN_USE=32'b00000000000000000000000000000000
    	SDIF2_IN_USE=32'b00000000000000000000000000000000
    	SDIF3_IN_USE=32'b00000000000000000000000000000000
    	SDIF0_PCIE=32'b00000000000000000000000000000000
    	SDIF1_PCIE=32'b00000000000000000000000000000000
    	SDIF2_PCIE=32'b00000000000000000000000000000000
    	SDIF3_PCIE=32'b00000000000000000000000000000000
    	SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001
    	SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001
    	SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001
    	SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001
    	SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001
    	SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001
    	SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001
    	SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001
    	ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000
    	DEVICE_090=32'b00000000000000000000000000000001
    	DDR_WAIT=32'b00000000000000000000000011001000
    	RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010
    	SDIF_INTERVAL=32'b00000000000000000001100101100100
    	DDR_INTERVAL=32'b00000000000000000010011100010000
    	COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101
    	COUNT_WIDTH_DDR=32'b00000000000000000000000000001110
    	S0=32'b00000000000000000000000000000000
    	S1=32'b00000000000000000000000000000001
    	S2=32'b00000000000000000000000000000010
    	S3=32'b00000000000000000000000000000011
    	S4=32'b00000000000000000000000000000100
    	S5=32'b00000000000000000000000000000101
    	S6=32'b00000000000000000000000000000110
       Generated name = CoreResetP_Z4

    @W:CL169 : coreresetp.v(1613) | Pruning register count_ddr[13:0]

    @W:CL169 : coreresetp.v(1581) | Pruning register count_sdif3[12:0]

    @W:CL169 : coreresetp.v(1549) | Pruning register count_sdif2[12:0]

    @W:CL169 : coreresetp.v(1517) | Pruning register count_sdif1[12:0]

    @W:CL169 : coreresetp.v(1485) | Pruning register count_sdif0[12:0]

    @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif0_enable_q1

    @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_q1

    @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_q1

    @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_q1

    @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif0_enable_rcosc

    @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_rcosc

    @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_rcosc

    @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_rcosc

    @W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_q1

    @W:CL169 : coreresetp.v(1455) | Pruning register count_ddr_enable_rcosc

    @W:CL169 : coreresetp.v(1365) | Pruning register count_sdif3_enable

    @W:CL169 : coreresetp.v(1300) | Pruning register count_sdif2_enable

    @W:CL169 : coreresetp.v(1235) | Pruning register count_sdif1_enable

    @W:CL169 : coreresetp.v(1170) | Pruning register count_sdif0_enable

    @W:CL169 : coreresetp.v(1089) | Pruning register count_ddr_enable

    @N:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int.
    @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1.
    @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1.
    @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q1.
    @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1.
    @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0
    @W:CL169 : coreresetp.v(1089) | Pruning register release_ext_reset

    @W:CL169 : coreresetp.v(1433) | Pruning register EXT_RESET_OUT_int

    @W:CL169 : coreresetp.v(1433) | Pruning register sm2_state[2:0]

    @W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_q1

    @W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_clk_base

    @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB

    @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ

    @N:CG364 : I2C_Multi_Master_Slave_FABOSC_0_OSC.v(5) | Synthesizing module I2C_Multi_Master_Slave_FABOSC_0_OSC

    @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF

    @N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF

    @N:CG364 : I2C_Multi_Master_Slave_MSS_syn.v(5) | Synthesizing module MSS_075

    @N:CG364 : I2C_Multi_Master_Slave_MSS.v(9) | Synthesizing module I2C_Multi_Master_Slave_MSS

    @N:CG364 : smartfusion2.v(718) | Synthesizing module SYSRESET

    @N:CG364 : I2C_Multi_Master_Slave.v(9) | Synthesizing module I2C_Multi_Master_Slave

    @N:CG364 : I2C_Multi_Master_Slave_top.v(9) | Synthesizing module I2C_Multi_Master_Slave_top

    @W:CL157 : I2C_Multi_Master_Slave_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible.
    @W:CL157 : I2C_Multi_Master_Slave_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible.
    @W:CL157 : I2C_Multi_Master_Slave_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits -- simulation mismatch possible.
    @W:CL157 : I2C_Multi_Master_Slave_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits -- simulation mismatch possible.
    @W:CL159 : I2C_Multi_Master_Slave_FABOSC_0_OSC.v(14) | Input XTL is unused
    @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q2.
    @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2.
    @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2.
    @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2.
    @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state
    Extracted state machine for register sdif3_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state
    Extracted state machine for register sdif2_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state
    Extracted state machine for register sdif1_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state
    Extracted state machine for register sdif0_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state
    Extracted state machine for register sm0_state
    State machine has 7 reachable states with original encodings of:
       000
       001
       010
       011
       100
       101
       110
    @W:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused
    @W:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused
    @W:CL159 : coreresetp.v(59) | Input SDIF0_SPLL_LOCK is unused
    @W:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused
    @W:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused
    @W:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused
    @W:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused
    @W:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused
    @W:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused
    @W:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused
    @W:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused
    @W:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused
    @W:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused
    @W:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused
    @W:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused
    @W:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused
    @W:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused
    @W:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused
    @W:CL159 : coreresetp.v(107) | Input SOFT_EXT_RESET_OUT is unused
    @W:CL159 : coreresetp.v(108) | Input SOFT_RESET_F2M is unused
    @W:CL159 : coreresetp.v(109) | Input SOFT_M3_RESET is unused
    @W:CL159 : coreresetp.v(110) | Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused
    @W:CL159 : coreresetp.v(111) | Input SOFT_FDDR_CORE_RESET is unused
    @W:CL159 : coreresetp.v(112) | Input SOFT_SDIF0_PHY_RESET is unused
    @W:CL159 : coreresetp.v(113) | Input SOFT_SDIF0_CORE_RESET is unused
    @W:CL159 : coreresetp.v(114) | Input SOFT_SDIF1_PHY_RESET is unused
    @W:CL159 : coreresetp.v(115) | Input SOFT_SDIF1_CORE_RESET is unused
    @W:CL159 : coreresetp.v(116) | Input SOFT_SDIF2_PHY_RESET is unused
    @W:CL159 : coreresetp.v(117) | Input SOFT_SDIF2_CORE_RESET is unused
    @W:CL159 : coreresetp.v(118) | Input SOFT_SDIF3_PHY_RESET is unused
    @W:CL159 : coreresetp.v(119) | Input SOFT_SDIF3_CORE_RESET is unused
    @W:CL159 : coreresetp.v(123) | Input SOFT_SDIF0_0_CORE_RESET is unused
    @W:CL159 : coreresetp.v(124) | Input SOFT_SDIF0_1_CORE_RESET is unused
    @N:CL201 : corei2creal.v(8331) | Trying to extract state machine for register CI2Cl0lI
    Extracted state machine for register CI2Cl0lI
    State machine has 7 reachable states with original encodings of:
       000
       001
       010
       011
       100
       101
       110
    @N:CL201 : corei2creal.v(7755) | Trying to extract state machine for register CI2COO0I
    Extracted state machine for register CI2COO0I
    State machine has 7 reachable states with original encodings of:
       000
       001
       010
       011
       100
       101
       110
    @N:CL201 : corei2creal.v(5560) | Trying to extract state machine for register CI2CI1lI
    Extracted state machine for register CI2CI1lI
    State machine has 8 reachable states with original encodings of:
       000
       001
       010
       011
       100
       101
       110
       111
    @W:CL159 : corei2creal.v(88) | Input pulse_215us is unused
    @W:CL159 : corei2creal.v(104) | Input seradr1apb0 is unused
    @W:CL159 : corei2creal.v(149) | Input SMBALERT_NI is unused
    @W:CL159 : corei2creal.v(155) | Input SMBSUS_NI is unused
    @W:CL159 : corei2c.v(97) | Input BCLK is unused
    @W:CL159 : coreapb3.v(72) | Input IADDR is unused
    @W:CL159 : coreapb3.v(73) | Input PRESETN is unused
    @W:CL159 : coreapb3.v(74) | Input PCLK is unused
    @W:CL159 : coreapb3.v(106) | Input PRDATAS2 is unused
    @W:CL159 : coreapb3.v(107) | Input PRDATAS3 is unused
    @W:CL159 : coreapb3.v(108) | Input PRDATAS4 is unused
    @W:CL159 : coreapb3.v(109) | Input PRDATAS5 is unused
    @W:CL159 : coreapb3.v(110) | Input PRDATAS6 is unused
    @W:CL159 : coreapb3.v(111) | Input PRDATAS7 is unused
    @W:CL159 : coreapb3.v(112) | Input PRDATAS8 is unused
    @W:CL159 : coreapb3.v(113) | Input PRDATAS9 is unused
    @W:CL159 : coreapb3.v(114) | Input PRDATAS10 is unused
    @W:CL159 : coreapb3.v(115) | Input PRDATAS11 is unused
    @W:CL159 : coreapb3.v(116) | Input PRDATAS12 is unused
    @W:CL159 : coreapb3.v(117) | Input PRDATAS13 is unused
    @W:CL159 : coreapb3.v(118) | Input PRDATAS14 is unused
    @W:CL159 : coreapb3.v(119) | Input PRDATAS15 is unused
    @W:CL159 : coreapb3.v(123) | Input PREADYS2 is unused
    @W:CL159 : coreapb3.v(124) | Input PREADYS3 is unused
    @W:CL159 : coreapb3.v(125) | Input PREADYS4 is unused
    @W:CL159 : coreapb3.v(126) | Input PREADYS5 is unused
    @W:CL159 : coreapb3.v(127) | Input PREADYS6 is unused
    @W:CL159 : coreapb3.v(128) | Input PREADYS7 is unused
    @W:CL159 : coreapb3.v(129) | Input PREADYS8 is unused
    @W:CL159 : coreapb3.v(130) | Input PREADYS9 is unused
    @W:CL159 : coreapb3.v(131) | Input PREADYS10 is unused
    @W:CL159 : coreapb3.v(132) | Input PREADYS11 is unused
    @W:CL159 : coreapb3.v(133) | Input PREADYS12 is unused
    @W:CL159 : coreapb3.v(134) | Input PREADYS13 is unused
    @W:CL159 : coreapb3.v(135) | Input PREADYS14 is unused
    @W:CL159 : coreapb3.v(136) | Input PREADYS15 is unused
    @W:CL159 : coreapb3.v(140) | Input PSLVERRS2 is unused
    @W:CL159 : coreapb3.v(141) | Input PSLVERRS3 is unused
    @W:CL159 : coreapb3.v(142) | Input PSLVERRS4 is unused
    @W:CL159 : coreapb3.v(143) | Input PSLVERRS5 is unused
    @W:CL159 : coreapb3.v(144) | Input PSLVERRS6 is unused
    @W:CL159 : coreapb3.v(145) | Input PSLVERRS7 is unused
    @W:CL159 : coreapb3.v(146) | Input PSLVERRS8 is unused
    @W:CL159 : coreapb3.v(147) | Input PSLVERRS9 is unused
    @W:CL159 : coreapb3.v(148) | Input PSLVERRS10 is unused
    @W:CL159 : coreapb3.v(149) | Input PSLVERRS11 is unused
    @W:CL159 : coreapb3.v(150) | Input PSLVERRS12 is unused
    @W:CL159 : coreapb3.v(151) | Input PSLVERRS13 is unused
    @W:CL159 : coreapb3.v(152) | Input PSLVERRS14 is unused
    @W:CL159 : coreapb3.v(153) | Input PSLVERRS15 is unused

    At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 81MB peak: 98MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Fri Feb 19 14:35:33 2016

    ###########################################################]
    Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec  1 2015
    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Fri Feb 19 14:35:33 2016

    ###########################################################]
    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Fri Feb 19 14:35:33 2016

    ###########################################################]
    Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec  1 2015
    @N: :  | Running in 64-bit mode
    File F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\synthesis\synwork\I2C_Multi_Master_Slave_top_comp.srs changed - recompiling

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Fri Feb 19 14:35:34 2016

    ###########################################################]
    Pre-mapping Report

    Synopsys Generic Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42
    Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
    Product Version J-2015.03M-SP1-2

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

    Linked File: I2C_Multi_Master_Slave_top_scck.rpt
    Printing clock  summary report in "F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\synthesis\I2C_Multi_Master_Slave_top_scck.rpt" file
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 108MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 108MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 108MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 110MB)

    @W:BN132 : coreresetp.v(1089) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int,  because it is equivalent to instance I2C_Multi_Master_Slave_0.CORERESETP_0.FDDR_CORE_RESET_N_int
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance DDR_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z4(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z4(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_RELEASED_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z4(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z4(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z4(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z4(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z4(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z4(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z4(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z4(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z4(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z4(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1170) | Removing sequential instance sdif0_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z4(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z4(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z4(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z4(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z4(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z4(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z4(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z4(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z4(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z4(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z4(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z4(verilog) because there are no references to its outputs
    syn_allowed_resources : blockrams=109  set on top level netlist I2C_Multi_Master_Slave_top

    Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 137MB)

    @S |Clock Summary
    *****************

    Start                                                                     Requested     Requested     Clock        Clock
    Clock                                                                     Frequency     Period        Type         Group
    --------------------------------------------------------------------------------------------------------------------------------------
    I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock                  100.0 MHz     10.000        inferred     Inferred_clkgroup_0
    I2C_Multi_Master_Slave_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_1
    ======================================================================================================================================

    @W:MT530 : corei2creal.v(7015) | Found inferred clock I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock which controls 248 sequential elements including I2C_Multi_Master_Slave_0.COREI2C_0_0.CI2CIlI\[0\]\.ui2c.CI2ClO0I[4:0]. This clock has no specified timing constraint which may adversely impact design performance.
    @W:MT530 : coreresetp.v(912) | Found inferred clock I2C_Multi_Master_Slave_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 15 sequential elements including I2C_Multi_Master_Slave_0.CORERESETP_0.sdif3_areset_n_rcosc_q1. This clock has no specified timing constraint which may adversely impact design performance.

    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\synthesis\I2C_Multi_Master_Slave_top.sap.
    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 137MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Fri Feb 19 14:35:35 2016

    ###########################################################]
    Map & Optimize Report

    Synopsys Generic Technology Mapper, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42
    Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
    Product Version J-2015.03M-SP1-2

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)

    @W:MO111 : i2c_multi_master_slave_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module I2C_Multi_Master_Slave_FABOSC_0_OSC)
    @W:MO111 : i2c_multi_master_slave_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module I2C_Multi_Master_Slave_FABOSC_0_OSC)
    @W:MO111 : i2c_multi_master_slave_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module I2C_Multi_Master_Slave_FABOSC_0_OSC)
    @W:MO111 : i2c_multi_master_slave_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module I2C_Multi_Master_Slave_FABOSC_0_OSC)
    @W:MO171 : coreresetp.v(676) | Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.SDIF0_PERST_N_q1 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(695) | Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.SDIF1_PERST_N_q1 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(714) | Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.SDIF2_PERST_N_q1 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(733) | Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.SDIF3_PERST_N_q1 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(676) | Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.SDIF0_PERST_N_q2 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(695) | Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.SDIF1_PERST_N_q2 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(714) | Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.SDIF2_PERST_N_q2 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(733) | Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.SDIF3_PERST_N_q2 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(676) | Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.SDIF0_PERST_N_q3 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(695) | Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.SDIF1_PERST_N_q3 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(714) | Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.SDIF2_PERST_N_q3 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(733) | Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.SDIF3_PERST_N_q3 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(769) | Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(769) | Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(1388) | Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation
    @W:BN132 : coreresetp.v(963) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif3_spll_lock_q1,  because it is equivalent to instance I2C_Multi_Master_Slave_0.CORERESETP_0.CONFIG2_DONE_q1
    @W:BN132 : coreresetp.v(946) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.CONFIG2_DONE_q1,  because it is equivalent to instance I2C_Multi_Master_Slave_0.CORERESETP_0.CONFIG1_DONE_q1
    @W:BN132 : coreresetp.v(946) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.CONFIG2_DONE_clk_base,  because it is equivalent to instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif3_spll_lock_q2
    @W:BN132 : coreresetp.v(929) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.CONFIG1_DONE_clk_base,  because it is equivalent to instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif3_spll_lock_q2
    @W:BN132 : coreresetp.v(884) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif1_areset_n_rcosc_q1,  because it is equivalent to instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif0_areset_n_rcosc_q1
    @W:BN132 : coreresetp.v(912) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif3_areset_n_rcosc_q1,  because it is equivalent to instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif0_areset_n_rcosc_q1
    @W:BN132 : coreresetp.v(898) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif2_areset_n_rcosc_q1,  because it is equivalent to instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif0_areset_n_rcosc_q1
    @W:BN132 : coreresetp.v(856) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm0_areset_n_rcosc_q1,  because it is equivalent to instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif0_areset_n_rcosc_q1
    @W:BN132 : coreresetp.v(898) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif2_areset_n_rcosc,  because it is equivalent to instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm0_areset_n_rcosc
    @W:BN132 : coreresetp.v(912) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif3_areset_n_rcosc,  because it is equivalent to instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm0_areset_n_rcosc

    Available hyper_sources - for debug and ip models
    	None Found

    @N:FA239 : corei2creal.v(2566) | ROM CI2COlll\.CI2COl0I_2[4:0] mapped in logic.
    @N:FA239 : corei2creal.v(2566) | ROM CI2COlll\.CI2COl0I_2[4:0] mapped in logic.
    @N:MO106 : corei2creal.v(2566) | Found ROM, 'CI2COlll\.CI2COl0I_2[4:0]', 29 words by 5 bits
    @N:FA239 : corei2creal.v(2566) | ROM CI2COlll\.CI2COl0I_2[4:0] mapped in logic.
    @N:FA239 : corei2creal.v(2566) | ROM CI2COlll\.CI2COl0I_2[4:0] mapped in logic.
    @N:MO106 : corei2creal.v(2566) | Found ROM, 'CI2COlll\.CI2COl0I_2[4:0]', 29 words by 5 bits

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB)

    Encoding state machine CI2Cl0lI[6:0] (view:work.COREI2CREAL_Z3(verilog))
    original code -> new code
       000 -> 0000001
       001 -> 0000010
       010 -> 0000100
       011 -> 0001000
       100 -> 0010000
       101 -> 0100000
       110 -> 1000000
    Encoding state machine CI2CI1lI[7:0] (view:work.COREI2CREAL_Z3(verilog))
    original code -> new code
       000 -> 00000001
       001 -> 00000010
       010 -> 00000100
       011 -> 00001000
       100 -> 00010000
       101 -> 00100000
       110 -> 01000000
       111 -> 10000000
    Encoding state machine CI2COO0I[6:0] (view:work.COREI2CREAL_Z3(verilog))
    original code -> new code
       000 -> 0000001
       001 -> 0000010
       010 -> 0000100
       011 -> 0001000
       100 -> 0010000
       101 -> 0100000
       110 -> 1000000
    Encoding state machine sm0_state[6:0] (view:work.CoreResetP_Z4(verilog))
    original code -> new code
       000 -> 0000001
       001 -> 0000010
       010 -> 0000100
       011 -> 0001000
       100 -> 0010000
       101 -> 0100000
       110 -> 1000000
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.INIT_DONE_int in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm0_state[6] in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs

    Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)

    Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 146MB)

    @N:BN362 : coreresetp.v(1613) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.ddr_settled in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs
    @A:BN291 : coreresetp.v(1613) | Boundary register I2C_Multi_Master_Slave_0.CORERESETP_0.ddr_settled packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
    @N:BN362 : coreresetp.v(1646) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.ddr_settled_q1 in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs
    @A:BN291 : coreresetp.v(1646) | Boundary register I2C_Multi_Master_Slave_0.CORERESETP_0.ddr_settled_q1 packed into a complex cell. To disable register packing, set syn_keep=1 on net between register and complex cell.
    @N:BN362 : coreresetp.v(963) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif3_spll_lock_q2 in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(929) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.CONFIG1_DONE_q1 in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(870) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif0_areset_n_rcosc_q1 in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(856) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm0_areset_n_rcosc in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(755) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm0_areset_n_q1 in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(755) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm0_areset_n_clk_base in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1646) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.ddr_settled_clk_base in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm0_state[5] in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm0_state[4] in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm0_state[3] in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm0_state[2] in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm0_state[1] in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm0_state[0] in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs
    @N:BN362 : corei2creal.v(5560) | Removing sequential instance I2C_Multi_Master_Slave_0.COREI2C_1_0.CI2CIlI\[0\]\.ui2c.CI2CI1lI[7] in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs
    @N:BN362 : corei2creal.v(5560) | Removing sequential instance I2C_Multi_Master_Slave_0.COREI2C_0_0.CI2CIlI\[0\]\.ui2c.CI2CI1lI[7] in hierarchy view:work.I2C_Multi_Master_Slave_top(verilog) because there are no references to its outputs

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 160MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 160MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 156MB peak: 160MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 155MB peak: 160MB)

    Finished preparing to map (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 155MB peak: 160MB)

    Finished technology mapping (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 163MB peak: 221MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:05s		    -0.92ns		 943 /       201
       2		0h:00m:05s		    -0.91ns		 871 /       201
       3		0h:00m:05s		    -0.56ns		 871 /       201

       4		0h:00m:07s		    -0.58ns		 871 /       201

       5		0h:00m:07s		    -0.58ns		 871 /       201
    @N:FP130 :  | Promoting Net un1_I2C_Multi_Master_Slave_0_8 on CLKINT  I_98

    Added 0 Buffers
    Added 0 Cells via replication
    	Added 0 Sequential Cells via replication
    	Added 0 Combinational Cells via replication

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 181MB peak: 221MB)

    Finished restoring hierarchy (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 181MB peak: 221MB)

    #### START OF CLOCK OPTIMIZATION REPORT #####[

    Clock optimization not enabled
    1 non-gated/non-generated clock tree(s) driving 202 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    ================================================================== Non-Gated/Non-Generated Clocks ==================================================================
    Clock Tree ID     Driving Element                             Drive Element Type     Fanout     Sample Instance
    --------------------------------------------------------------------------------------------------------------------------------------------------------------------
    ClockId0001        I2C_Multi_Master_Slave_0.CCC_0.GL0_INST     CLKINT                 202        I2C_Multi_Master_Slave_0.I2C_Multi_Master_Slave_MSS_0.MSS_ADLIB_INST
    ====================================================================================================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######]

    Start Writing Netlists (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 152MB peak: 221MB)

    Writing Analyst data base F:\M2S_I2C_DF\Libero_Project\I2C_Multi_Master_Slave\synthesis\synwork\I2C_Multi_Master_Slave_top_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 180MB peak: 221MB)

    Writing EDIF Netlist and constraint files
    @N:BW103 :  | Synopsys Constraint File time units using default value of 1ns
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF
    J-2015.03M-SP1-2

    Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 181MB peak: 221MB)

    Start final timing analysis (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 178MB peak: 221MB)

    @W:MT246 : i2c_multi_master_slave_ccc_0_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT420 :  | Found inferred clock I2C_Multi_Master_Slave_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:I2C_Multi_Master_Slave_0.FABOSC_0.RCOSC_25_50MHZ_CCC"

    @W:MT420 :  | Found inferred clock I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:I2C_Multi_Master_Slave_0.CCC_0.GL0_net"

    @S |##### START OF TIMING REPORT #####[
    # Timing Report written on Fri Feb 19 14:35:44 2016
    #

    Top view:               I2C_Multi_Master_Slave_top
    Requested Frequency:    100.0 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing.

    @N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock.

    Performance Summary
    *******************

    Worst slack in design: 0.501

                                                                              Requested     Estimated     Requested     Estimated               Clock        Clock
    Starting Clock                                                            Frequency     Frequency     Period        Period        Slack     Type         Group
    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock                  100.0 MHz     105.3 MHz     10.000        9.499         0.501     inferred     Inferred_clkgroup_0
    I2C_Multi_Master_Slave_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     100.0 MHz     NA            10.000        NA            NA        inferred     Inferred_clkgroup_1
    ============================================================================================================================================================================
    @N:MT582 :  | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack

    Clock Relationships
    *******************

    Clocks                                                                                                              |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                                                  Ending                                                    |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
    ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock  I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock  |  10.000      0.501  |  No paths    -      |  No paths    -      |  No paths    -
    ==========================================================================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                                             Starting                                                                                                                                                    Arrival
    Instance                                                                 Reference                                                    Type        Pin                Net                                                             Time        Slack
                                                                             Clock
    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    I2C_Multi_Master_Slave_0.I2C_Multi_Master_Slave_MSS_0.MSS_ADLIB_INST     I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_ADDR[3]      CoreAPB3_0_APBmslave0_PADDR[3]                                  3.570       0.501
    I2C_Multi_Master_Slave_0.I2C_Multi_Master_Slave_MSS_0.MSS_ADLIB_INST     I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_ADDR[2]      CoreAPB3_0_APBmslave0_PADDR[2]                                  3.545       0.512
    I2C_Multi_Master_Slave_0.I2C_Multi_Master_Slave_MSS_0.MSS_ADLIB_INST     I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_ADDR[8]      CoreAPB3_0_APBmslave0_PADDR[8]                                  3.679       0.541
    I2C_Multi_Master_Slave_0.I2C_Multi_Master_Slave_MSS_0.MSS_ADLIB_INST     I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_ADDR[15]     I2C_Multi_Master_Slave_MSS_TMP_0_FIC_0_APB_MASTER_PADDR[15]     3.594       0.544
    I2C_Multi_Master_Slave_0.I2C_Multi_Master_Slave_MSS_0.MSS_ADLIB_INST     I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_ADDR[4]      CoreAPB3_0_APBmslave0_PADDR[4]                                  3.748       0.567
    I2C_Multi_Master_Slave_0.I2C_Multi_Master_Slave_MSS_0.MSS_ADLIB_INST     I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_ADDR[12]     I2C_Multi_Master_Slave_MSS_TMP_0_FIC_0_APB_MASTER_PADDR[12]     3.583       0.626
    I2C_Multi_Master_Slave_0.I2C_Multi_Master_Slave_MSS_0.MSS_ADLIB_INST     I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_SEL          I2C_Multi_Master_Slave_MSS_TMP_0_FIC_0_APB_MASTER_PSELx         3.626       0.628
    I2C_Multi_Master_Slave_0.I2C_Multi_Master_Slave_MSS_0.MSS_ADLIB_INST     I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_ADDR[6]      CoreAPB3_0_APBmslave0_PADDR[6]                                  3.682       0.639
    I2C_Multi_Master_Slave_0.I2C_Multi_Master_Slave_MSS_0.MSS_ADLIB_INST     I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_ADDR[14]     I2C_Multi_Master_Slave_MSS_TMP_0_FIC_0_APB_MASTER_PADDR[14]     3.542       0.779
    I2C_Multi_Master_Slave_0.I2C_Multi_Master_Slave_MSS_0.MSS_ADLIB_INST     I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_ADDR[13]     I2C_Multi_Master_Slave_MSS_TMP_0_FIC_0_APB_MASTER_PADDR[13]     3.548       0.816
    ======================================================================================================================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                                             Starting                                                                                                                                                    Required
    Instance                                                                 Reference                                                    Type        Pin                Net                                                             Time         Slack
                                                                             Clock
    -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    I2C_Multi_Master_Slave_0.I2C_Multi_Master_Slave_MSS_0.MSS_ADLIB_INST     I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_RDATA[3]     I2C_Multi_Master_Slave_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]     8.877        0.501
    I2C_Multi_Master_Slave_0.I2C_Multi_Master_Slave_MSS_0.MSS_ADLIB_INST     I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_RDATA[5]     I2C_Multi_Master_Slave_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[5]     8.852        0.512
    I2C_Multi_Master_Slave_0.I2C_Multi_Master_Slave_MSS_0.MSS_ADLIB_INST     I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_RDATA[2]     I2C_Multi_Master_Slave_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[2]     8.474        0.541
    I2C_Multi_Master_Slave_0.I2C_Multi_Master_Slave_MSS_0.MSS_ADLIB_INST     I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_RDATA[6]     I2C_Multi_Master_Slave_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[6]     8.886        0.546
    I2C_Multi_Master_Slave_0.I2C_Multi_Master_Slave_MSS_0.MSS_ADLIB_INST     I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_RDATA[7]     I2C_Multi_Master_Slave_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[7]     8.824        0.561
    I2C_Multi_Master_Slave_0.I2C_Multi_Master_Slave_MSS_0.MSS_ADLIB_INST     I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_RDATA[4]     I2C_Multi_Master_Slave_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[4]     8.835        0.572
    I2C_Multi_Master_Slave_0.I2C_Multi_Master_Slave_MSS_0.MSS_ADLIB_INST     I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_RDATA[1]     I2C_Multi_Master_Slave_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[1]     8.805        0.630
    I2C_Multi_Master_Slave_0.I2C_Multi_Master_Slave_MSS_0.MSS_ADLIB_INST     I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock     MSS_075     F_HM0_RDATA[0]     I2C_Multi_Master_Slave_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[0]     8.865        0.690
    I2C_Multi_Master_Slave_0.COREI2C_1_0.CI2CIlI\[0\]\.ui2c.CI2CII0I[3]      I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock     SLE         D                  N_84_i_0                                                        9.745        1.024
    I2C_Multi_Master_Slave_0.COREI2C_0_0.CI2CIlI\[0\]\.ui2c.CI2ClIOl         I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock     SLE         D                  CI2ClIOl_10                                                     9.745        1.422
    =======================================================================================================================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            1.123
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         8.877

        - Propagation time:                      8.376
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     0.501

        Number of logic level(s):                4
        Starting point:                          I2C_Multi_Master_Slave_0.I2C_Multi_Master_Slave_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[3]
        Ending point:                            I2C_Multi_Master_Slave_0.I2C_Multi_Master_Slave_MSS_0.MSS_ADLIB_INST / F_HM0_RDATA[3]
        The start point is clocked by            I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE
        The end   point is clocked by            I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE

    Instance / Net                                                                               Pin                Pin               Arrival     No. of
    Name                                                                             Type        Name               Dir     Delay     Time        Fan Out(s)
    --------------------------------------------------------------------------------------------------------------------------------------------------------
    I2C_Multi_Master_Slave_0.I2C_Multi_Master_Slave_MSS_0.MSS_ADLIB_INST             MSS_075     F_HM0_ADDR[3]      Out     3.570     3.570       -
    CoreAPB3_0_APBmslave0_PADDR[3]                                                   Net         -                  -       1.144     -           24
    I2C_Multi_Master_Slave_0.COREI2C_0_0.CI2CIlI\[0\]\.ui2c.CI2ClI0I_RNIPCBT[3]      CFG4        D                  In      -         4.714       -
    I2C_Multi_Master_Slave_0.COREI2C_0_0.CI2CIlI\[0\]\.ui2c.CI2ClI0I_RNIPCBT[3]      CFG4        Y                  Out     0.326     5.040       -
    PRDATA_i_m2_1[3]                                                                 Net         -                  -       0.556     -           1
    I2C_Multi_Master_Slave_0.COREI2C_0_0.CI2CIlI\[0\]\.ui2c.CI2COl0I_RNI8UIT1[0]     CFG4        C                  In      -         5.596       -
    I2C_Multi_Master_Slave_0.COREI2C_0_0.CI2CIlI\[0\]\.ui2c.CI2COl0I_RNI8UIT1[0]     CFG4        Y                  Out     0.226     5.822       -
    N_1921                                                                           Net         -                  -       0.556     -           1
    I2C_Multi_Master_Slave_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1_1[3]                  CFG3        C                  In      -         6.377       -
    I2C_Multi_Master_Slave_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1_1[3]                  CFG3        Y                  Out     0.226     6.603       -
    PRDATA_1_1[3]                                                                    Net         -                  -       0.556     -           1
    I2C_Multi_Master_Slave_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1[3]                    CFG3        A                  In      -         7.159       -
    I2C_Multi_Master_Slave_0.CoreAPB3_0.u_mux_p_to_b3.PRDATA_1[3]                    CFG3        Y                  Out     0.100     7.259       -
    I2C_Multi_Master_Slave_MSS_TMP_0_FIC_0_APB_MASTER_PRDATA[3]                      Net         -                  -       1.117     -           1
    I2C_Multi_Master_Slave_0.I2C_Multi_Master_Slave_MSS_0.MSS_ADLIB_INST             MSS_075     F_HM0_RDATA[3]     In      -         8.376       -
    ========================================================================================================================================================
    Total path delay (propagation time + setup) of 9.499 is 5.571(58.6%) logic and 3.928(41.4%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Finished final timing analysis (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 178MB peak: 221MB)

    Finished timing report (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 178MB peak: 221MB)

    ---------------------------------------
    Resource Usage Report for I2C_Multi_Master_Slave_top

    Mapping to part: m2s090tsfbga484std
    Cell usage:
    CCC             1 use
    CLKINT          2 uses
    MSS_075         1 use
    RCOSC_25_50MHZ  1 use
    SYSRESET        1 use
    CFG1           8 uses
    CFG2           129 uses
    CFG3           234 uses
    CFG4           494 uses

    Sequential Cells:
    SLE            201 uses

    DSP Blocks:    0

    I/O ports: 11
    I/O primitives: 10
    BIBUF          8 uses
    INBUF          1 use
    TRIBUFF        1 use

    Global Clock Buffers: 2

    Total LUTs:    865

    Extra resources required for RAM and MACC interface logic during P&R:

    RAM64x18 Interface Logic : SLEs = 0; LUTs = 0;
    RAM1K18  Interface Logic : SLEs = 0; LUTs = 0;
    MACC     Interface Logic : SLEs = 0; LUTs = 0;

    Total number of SLEs after P&R:  201 + 0 + 0 + 0 = 201;
    Total number of LUTs after P&R:  865 + 0 + 0 + 0 = 865;

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 53MB peak: 221MB)

    Process took 0h:00m:08s realtime, 0h:00m:08s cputime
    # Fri Feb 19 14:35:44 2016

    ###########################################################]

`