@W: MO111 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\work\i2c_multi_master_slave\fabosc_0\i2c_multi_master_slave_fabosc_0_osc.v":20:7:20:16|Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module I2C_Multi_Master_Slave_FABOSC_0_OSC) 
@W: MO111 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\work\i2c_multi_master_slave\fabosc_0\i2c_multi_master_slave_fabosc_0_osc.v":19:7:19:16|Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module I2C_Multi_Master_Slave_FABOSC_0_OSC) 
@W: MO111 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\work\i2c_multi_master_slave\fabosc_0\i2c_multi_master_slave_fabosc_0_osc.v":18:7:18:20|Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module I2C_Multi_Master_Slave_FABOSC_0_OSC) 
@W: MO111 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\work\i2c_multi_master_slave\fabosc_0\i2c_multi_master_slave_fabosc_0_osc.v":17:7:17:20|Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module I2C_Multi_Master_Slave_FABOSC_0_OSC) 
@W: MO171 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":676:4:676:9|Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.SDIF0_PERST_N_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.SDIF1_PERST_N_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.SDIF2_PERST_N_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.SDIF3_PERST_N_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":676:4:676:9|Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.SDIF0_PERST_N_q2 reduced to a combinational gate by constant propagation 
@W: MO171 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.SDIF1_PERST_N_q2 reduced to a combinational gate by constant propagation 
@W: MO171 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.SDIF2_PERST_N_q2 reduced to a combinational gate by constant propagation 
@W: MO171 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.SDIF3_PERST_N_q2 reduced to a combinational gate by constant propagation 
@W: MO171 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":676:4:676:9|Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.SDIF0_PERST_N_q3 reduced to a combinational gate by constant propagation 
@W: MO171 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":695:4:695:9|Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.SDIF1_PERST_N_q3 reduced to a combinational gate by constant propagation 
@W: MO171 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":714:4:714:9|Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.SDIF2_PERST_N_q3 reduced to a combinational gate by constant propagation 
@W: MO171 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":733:4:733:9|Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.SDIF3_PERST_N_q3 reduced to a combinational gate by constant propagation 
@W: MO171 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation 
@W: MO171 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":769:4:769:9|Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation 
@W: MO171 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1388:4:1388:9|Sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation 
@W: BN132 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":963:4:963:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif3_spll_lock_q1,  because it is equivalent to instance I2C_Multi_Master_Slave_0.CORERESETP_0.CONFIG2_DONE_q1
@W: BN132 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":946:4:946:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.CONFIG2_DONE_q1,  because it is equivalent to instance I2C_Multi_Master_Slave_0.CORERESETP_0.CONFIG1_DONE_q1
@W: BN132 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":946:4:946:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.CONFIG2_DONE_clk_base,  because it is equivalent to instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif3_spll_lock_q2
@W: BN132 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":929:4:929:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.CONFIG1_DONE_clk_base,  because it is equivalent to instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif3_spll_lock_q2
@W: BN132 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":884:4:884:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif1_areset_n_rcosc_q1,  because it is equivalent to instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif0_areset_n_rcosc_q1
@W: BN132 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":912:4:912:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif3_areset_n_rcosc_q1,  because it is equivalent to instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif0_areset_n_rcosc_q1
@W: BN132 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":898:4:898:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif2_areset_n_rcosc_q1,  because it is equivalent to instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif0_areset_n_rcosc_q1
@W: BN132 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":856:4:856:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm0_areset_n_rcosc_q1,  because it is equivalent to instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif0_areset_n_rcosc_q1
@W: BN132 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":898:4:898:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif2_areset_n_rcosc,  because it is equivalent to instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm0_areset_n_rcosc
@W: BN132 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":912:4:912:9|Removing sequential instance I2C_Multi_Master_Slave_0.CORERESETP_0.sdif3_areset_n_rcosc,  because it is equivalent to instance I2C_Multi_Master_Slave_0.CORERESETP_0.sm0_areset_n_rcosc
@W: MT246 :"f:\m2s_i2c_df\libero_project\i2c_multi_master_slave\component\work\i2c_multi_master_slave\ccc_0\i2c_multi_master_slave_ccc_0_fccc.v":20:36:20:43|Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT420 |Found inferred clock I2C_Multi_Master_Slave_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:I2C_Multi_Master_Slave_0.FABOSC_0.RCOSC_25_50MHZ_CCC"
@W: MT420 |Found inferred clock I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:I2C_Multi_Master_Slave_0.CCC_0.GL0_net"
