Project Settings
Project Name | I2C_Multi_Master_Slave_top_syn | Implementation Name | synthesis
Top Module | I2C_Multi_Master_Slave_top | Retiming | 0
Resource Sharing | 1 | Fanout Guide | 10000
Disable I/O Insertion | 0 | FSM Compiler | 1
Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
(compiler) | Complete | 41 | 139 | 0 | - | 0m:01s | - | 2/19/2016 2:35:33 PM
(premap) | Complete | 27 | 3 | 0 | 0m:00s | 0m:00s | 137MB | 2/19/2016 2:35:35 PM
(fpga_mapper) | Complete | 36 | 32 | 0 | 0m:08s | 0m:08s | 221MB | 2/19/2016 2:35:44 PM
Multi-srs Generator | Complete |  |  |  | 0m:01s |  |  | 2/19/2016 2:35:34 PM
Area Summary
Sequential Cells | 201 | DSP Blocks (MACC) (dsp_used) | 0
I/O Cells | 10 | Global Clock Buffers | 2
LUTs (total_luts) | 865 |  |
Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
I2C_Multi_Master_Slave_CCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | 105.3 MHz | 0.501
I2C_Multi_Master_Slave_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | 100.0 MHz | NA | NA
Optimizations Summary
Combined Clock Conversion | 1 / 0 |  |