
Remapping_Appnote_MSS_CM3_app:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .vector_table 00000190  00000000  60000000  00008000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .boot_code    00000280  00000190  60000190  00008190  2**4
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  2 .text         00000f80  00000410  60000410  00008410  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  3 .data         00000020  20000000  60001390  00010000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  4 .bss          00000090  20000020  600013b0  00010020  2**2
                  ALLOC
  5 .heap         0000cf50  200000b0  600013b0  000100b0  2**0
                  ALLOC
  6 .stack        00003000  2000d000  600013b0  00015000  2**0
                  ALLOC
  7 .comment      000000d7  00000000  00000000  00010020  2**0
                  CONTENTS, READONLY
  8 .debug_aranges 00000268  00000000  00000000  000100f7  2**0
                  CONTENTS, READONLY, DEBUGGING
  9 .debug_pubnames 00000708  00000000  00000000  0001035f  2**0
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_info   00006448  00000000  00000000  00010a67  2**0
                  CONTENTS, READONLY, DEBUGGING
 11 .debug_abbrev 0000092d  00000000  00000000  00016eaf  2**0
                  CONTENTS, READONLY, DEBUGGING
 12 .debug_line   00001332  00000000  00000000  000177dc  2**0
                  CONTENTS, READONLY, DEBUGGING
 13 .debug_frame  0000065c  00000000  00000000  00018b10  2**2
                  CONTENTS, READONLY, DEBUGGING
 14 .debug_str    00002c47  00000000  00000000  0001916c  2**0
                  CONTENTS, READONLY, DEBUGGING
 15 .debug_loc    00000f5a  00000000  00000000  0001bdb3  2**0
                  CONTENTS, READONLY, DEBUGGING
 16 .ARM.attributes 00000025  00000000  00000000  0001cd0d  2**0
                  CONTENTS, READONLY
 17 .debug_ranges 00000de0  00000000  00000000  0001cd32  2**0
                  CONTENTS, READONLY, DEBUGGING

Disassembly of section .text:

00000410 <__do_global_dtors_aux>:
     410:	f240 0320 	movw	r3, #32
     414:	f2c2 0300 	movt	r3, #8192	; 0x2000
     418:	781a      	ldrb	r2, [r3, #0]
     41a:	b90a      	cbnz	r2, 420 <__do_global_dtors_aux+0x10>
     41c:	2001      	movs	r0, #1
     41e:	7018      	strb	r0, [r3, #0]
     420:	4770      	bx	lr
     422:	bf00      	nop

00000424 <frame_dummy>:
     424:	f240 0000 	movw	r0, #0
     428:	f2c2 0000 	movt	r0, #8192	; 0x2000
     42c:	b508      	push	{r3, lr}
     42e:	6803      	ldr	r3, [r0, #0]
     430:	b12b      	cbz	r3, 43e <frame_dummy+0x1a>
     432:	f240 0300 	movw	r3, #0
     436:	f2c0 0300 	movt	r3, #0
     43a:	b103      	cbz	r3, 43e <frame_dummy+0x1a>
     43c:	4798      	blx	r3
     43e:	bd08      	pop	{r3, pc}

00000440 <copy_image_to_ram>:
     440:	2803      	cmp	r0, #3
     442:	d81e      	bhi.n	482 <copy_image_to_ram+0x42>
     444:	e8df f000 	tbb	[pc, r0]
     448:	021e3950 	.word	0x021e3950
     44c:	f246 0104 	movw	r1, #24580	; 0x6004
     450:	f24a 0c04 	movw	ip, #40964	; 0xa004
     454:	f2c6 0101 	movt	r1, #24577	; 0x6001
     458:	f2c6 0c01 	movt	ip, #24577	; 0x6001
     45c:	f641 73fc 	movw	r3, #8188	; 0x1ffc
     460:	f851 0c04 	ldr.w	r0, [r1, #-4]
     464:	f6cb 73ff 	movt	r3, #49151	; 0xbfff
     468:	18ca      	adds	r2, r1, r3
     46a:	f242 0300 	movw	r3, #8192	; 0x2000
     46e:	6010      	str	r0, [r2, #0]
     470:	f6cb 73ff 	movt	r3, #49151	; 0xbfff
     474:	18ca      	adds	r2, r1, r3
     476:	f851 0b04 	ldr.w	r0, [r1], #4
     47a:	3104      	adds	r1, #4
     47c:	4561      	cmp	r1, ip
     47e:	6010      	str	r0, [r2, #0]
     480:	d1ec      	bne.n	45c <copy_image_to_ram+0x1c>
     482:	4770      	bx	lr
     484:	f242 0204 	movw	r2, #8196	; 0x2004
     488:	f246 0004 	movw	r0, #24580	; 0x6004
     48c:	f2c6 0201 	movt	r2, #24577	; 0x6001
     490:	f2c6 0001 	movt	r0, #24577	; 0x6001
     494:	f64d 73fc 	movw	r3, #57340	; 0xdffc
     498:	f852 1c04 	ldr.w	r1, [r2, #-4]
     49c:	f6cb 73fe 	movt	r3, #49150	; 0xbffe
     4a0:	18d3      	adds	r3, r2, r3
     4a2:	6019      	str	r1, [r3, #0]
     4a4:	f102 4c40 	add.w	ip, r2, #3221225472	; 0xc0000000
     4a8:	f852 1b04 	ldr.w	r1, [r2], #4
     4ac:	f5ac 3390 	sub.w	r3, ip, #73728	; 0x12000
     4b0:	3204      	adds	r2, #4
     4b2:	4282      	cmp	r2, r0
     4b4:	6019      	str	r1, [r3, #0]
     4b6:	d1ed      	bne.n	494 <copy_image_to_ram+0x54>
     4b8:	4770      	bx	lr
     4ba:	f248 0304 	movw	r3, #32772	; 0x8004
     4be:	f24c 0004 	movw	r0, #49156	; 0xc004
     4c2:	f2c6 0300 	movt	r3, #24576	; 0x6000
     4c6:	f2c6 0000 	movt	r0, #24576	; 0x6000
     4ca:	f853 1c04 	ldr.w	r1, [r3, #-4]
     4ce:	f103 4240 	add.w	r2, r3, #3221225472	; 0xc0000000
     4d2:	3a04      	subs	r2, #4
     4d4:	6011      	str	r1, [r2, #0]
     4d6:	f103 4240 	add.w	r2, r3, #3221225472	; 0xc0000000
     4da:	f853 1b04 	ldr.w	r1, [r3], #4
     4de:	3304      	adds	r3, #4
     4e0:	4283      	cmp	r3, r0
     4e2:	6011      	str	r1, [r2, #0]
     4e4:	d1f1      	bne.n	4ca <copy_image_to_ram+0x8a>
     4e6:	4770      	bx	lr
     4e8:	f244 0204 	movw	r2, #16388	; 0x4004
     4ec:	f248 0004 	movw	r0, #32772	; 0x8004
     4f0:	f2c6 0200 	movt	r2, #24576	; 0x6000
     4f4:	f2c6 0000 	movt	r0, #24576	; 0x6000
     4f8:	f64b 73fc 	movw	r3, #49148	; 0xbffc
     4fc:	f852 1c04 	ldr.w	r1, [r2, #-4]
     500:	f6cb 73ff 	movt	r3, #49151	; 0xbfff
     504:	18d3      	adds	r3, r2, r3
     506:	6019      	str	r1, [r3, #0]
     508:	f102 4c40 	add.w	ip, r2, #3221225472	; 0xc0000000
     50c:	f852 1b04 	ldr.w	r1, [r2], #4
     510:	f5ac 4380 	sub.w	r3, ip, #16384	; 0x4000
     514:	3204      	adds	r2, #4
     516:	4282      	cmp	r2, r0
     518:	6019      	str	r1, [r3, #0]
     51a:	d1ed      	bne.n	4f8 <copy_image_to_ram+0xb8>
     51c:	4770      	bx	lr
     51e:	bf00      	nop

00000520 <remap_user_code_eNVM_128KB>:
     520:	b508      	push	{r3, lr}
     522:	2300      	movs	r3, #0
     524:	681a      	ldr	r2, [r3, #0]
     526:	f382 8808 	msr	MSP, r2
     52a:	f248 0300 	movw	r3, #32768	; 0x8000
     52e:	f2c4 0303 	movt	r3, #16387	; 0x4003
     532:	68d8      	ldr	r0, [r3, #12]
     534:	f240 0201 	movw	r2, #1
     538:	f020 010f 	bic.w	r1, r0, #15
     53c:	60d9      	str	r1, [r3, #12]
     53e:	68d8      	ldr	r0, [r3, #12]
     540:	f2c0 0202 	movt	r2, #2
     544:	f040 0110 	orr.w	r1, r0, #16
     548:	2004      	movs	r0, #4
     54a:	60d9      	str	r1, [r3, #12]
     54c:	611a      	str	r2, [r3, #16]
     54e:	6803      	ldr	r3, [r0, #0]
     550:	4798      	blx	r3
     552:	e7fe      	b.n	552 <remap_user_code_eNVM_128KB+0x32>

00000554 <remap_user_code_eSRAM_0>:
     554:	f04f 5100 	mov.w	r1, #536870912	; 0x20000000
     558:	b508      	push	{r3, lr}
     55a:	680a      	ldr	r2, [r1, #0]
     55c:	f382 8808 	msr	MSP, r2
     560:	f248 0000 	movw	r0, #32768	; 0x8000
     564:	f2c4 0003 	movt	r0, #16387	; 0x4003
     568:	6803      	ldr	r3, [r0, #0]
     56a:	f240 0204 	movw	r2, #4
     56e:	f043 0101 	orr.w	r1, r3, #1
     572:	f2c2 0200 	movt	r2, #8192	; 0x2000
     576:	6001      	str	r1, [r0, #0]
     578:	6813      	ldr	r3, [r2, #0]
     57a:	4798      	blx	r3
     57c:	e7fe      	b.n	57c <remap_user_code_eSRAM_0+0x28>
     57e:	bf00      	nop

00000580 <remap_user_code_eSRAM_1>:
     580:	f248 0100 	movw	r1, #32768	; 0x8000
     584:	f2c2 0100 	movt	r1, #8192	; 0x2000
     588:	b508      	push	{r3, lr}
     58a:	680a      	ldr	r2, [r1, #0]
     58c:	f382 8808 	msr	MSP, r2
     590:	f248 0000 	movw	r0, #32768	; 0x8000
     594:	f2c4 0003 	movt	r0, #16387	; 0x4003
     598:	6803      	ldr	r3, [r0, #0]
     59a:	f248 0204 	movw	r2, #32772	; 0x8004
     59e:	f043 0103 	orr.w	r1, r3, #3
     5a2:	f2c2 0200 	movt	r2, #8192	; 0x2000
     5a6:	6001      	str	r1, [r0, #0]
     5a8:	6813      	ldr	r3, [r2, #0]
     5aa:	4798      	blx	r3
     5ac:	e7fe      	b.n	5ac <remap_user_code_eSRAM_1+0x2c>
     5ae:	bf00      	nop

000005b0 <main>:
     5b0:	b570      	push	{r4, r5, r6, lr}
     5b2:	f240 0424 	movw	r4, #36	; 0x24
     5b6:	f2c2 0400 	movt	r4, #8192	; 0x2000
     5ba:	b082      	sub	sp, #8
     5bc:	f44f 4161 	mov.w	r1, #57600	; 0xe100
     5c0:	2203      	movs	r2, #3
     5c2:	4620      	mov	r0, r4
     5c4:	f000 fbc6 	bl	d54 <MSS_UART_init>
     5c8:	f241 01e0 	movw	r1, #4320	; 0x10e0
     5cc:	4620      	mov	r0, r4
     5ce:	f2c0 0100 	movt	r1, #0
     5d2:	222f      	movs	r2, #47	; 0x2f
     5d4:	f000 f8bc 	bl	750 <MSS_UART_polled_tx>
     5d8:	ad01      	add	r5, sp, #4
     5da:	f240 0024 	movw	r0, #36	; 0x24
     5de:	f241 1110 	movw	r1, #4368	; 0x1110
     5e2:	f2c2 0000 	movt	r0, #8192	; 0x2000
     5e6:	f2c0 0100 	movt	r1, #0
     5ea:	221a      	movs	r2, #26
     5ec:	f000 f8b0 	bl	750 <MSS_UART_polled_tx>
     5f0:	f240 0024 	movw	r0, #36	; 0x24
     5f4:	f241 112c 	movw	r1, #4396	; 0x112c
     5f8:	f2c2 0000 	movt	r0, #8192	; 0x2000
     5fc:	f2c0 0100 	movt	r1, #0
     600:	221e      	movs	r2, #30
     602:	f000 f8a5 	bl	750 <MSS_UART_polled_tx>
     606:	f240 0024 	movw	r0, #36	; 0x24
     60a:	f241 114c 	movw	r1, #4428	; 0x114c
     60e:	f2c2 0000 	movt	r0, #8192	; 0x2000
     612:	f2c0 0100 	movt	r1, #0
     616:	221e      	movs	r2, #30
     618:	f000 f89a 	bl	750 <MSS_UART_polled_tx>
     61c:	f240 0024 	movw	r0, #36	; 0x24
     620:	f241 116c 	movw	r1, #4460	; 0x116c
     624:	f2c2 0000 	movt	r0, #8192	; 0x2000
     628:	f2c0 0100 	movt	r1, #0
     62c:	221e      	movs	r2, #30
     62e:	f000 f88f 	bl	750 <MSS_UART_polled_tx>
     632:	f240 0024 	movw	r0, #36	; 0x24
     636:	f241 118c 	movw	r1, #4492	; 0x118c
     63a:	f2c2 0000 	movt	r0, #8192	; 0x2000
     63e:	f2c0 0100 	movt	r1, #0
     642:	221e      	movs	r2, #30
     644:	f000 f884 	bl	750 <MSS_UART_polled_tx>
     648:	f240 0024 	movw	r0, #36	; 0x24
     64c:	f241 11ac 	movw	r1, #4524	; 0x11ac
     650:	221d      	movs	r2, #29
     652:	f2c2 0000 	movt	r0, #8192	; 0x2000
     656:	f2c0 0100 	movt	r1, #0
     65a:	f000 f879 	bl	750 <MSS_UART_polled_tx>
     65e:	6822      	ldr	r2, [r4, #0]
     660:	7d13      	ldrb	r3, [r2, #20]
     662:	f013 0f01 	tst.w	r3, #1
     666:	d0fb      	beq.n	660 <main+0xb0>
     668:	2300      	movs	r3, #0
     66a:	7811      	ldrb	r1, [r2, #0]
     66c:	6822      	ldr	r2, [r4, #0]
     66e:	54e9      	strb	r1, [r5, r3]
     670:	7d16      	ldrb	r6, [r2, #20]
     672:	3301      	adds	r3, #1
     674:	f016 0601 	ands.w	r6, r6, #1
     678:	d1f7      	bne.n	66a <main+0xba>
     67a:	2b00      	cmp	r3, #0
     67c:	d0f0      	beq.n	660 <main+0xb0>
     67e:	f89d 3004 	ldrb.w	r3, [sp, #4]
     682:	2b31      	cmp	r3, #49	; 0x31
     684:	d013      	beq.n	6ae <main+0xfe>
     686:	2b32      	cmp	r3, #50	; 0x32
     688:	d022      	beq.n	6d0 <main+0x120>
     68a:	2b33      	cmp	r3, #51	; 0x33
     68c:	d031      	beq.n	6f2 <main+0x142>
     68e:	2b34      	cmp	r3, #52	; 0x34
     690:	d040      	beq.n	714 <main+0x164>
     692:	2b35      	cmp	r3, #53	; 0x35
     694:	f240 0024 	movw	r0, #36	; 0x24
     698:	d04d      	beq.n	736 <main+0x186>
     69a:	f241 2144 	movw	r1, #4676	; 0x1244
     69e:	f2c2 0000 	movt	r0, #8192	; 0x2000
     6a2:	f2c0 0100 	movt	r1, #0
     6a6:	2213      	movs	r2, #19
     6a8:	f000 f852 	bl	750 <MSS_UART_polled_tx>
     6ac:	e795      	b.n	5da <main+0x2a>
     6ae:	f240 0024 	movw	r0, #36	; 0x24
     6b2:	f241 11cc 	movw	r1, #4556	; 0x11cc
     6b6:	f2c0 0100 	movt	r1, #0
     6ba:	2216      	movs	r2, #22
     6bc:	f2c2 0000 	movt	r0, #8192	; 0x2000
     6c0:	f000 f846 	bl	750 <MSS_UART_polled_tx>
     6c4:	4630      	mov	r0, r6
     6c6:	f7ff febb 	bl	440 <copy_image_to_ram>
     6ca:	f7ff ff43 	bl	554 <remap_user_code_eSRAM_0>
     6ce:	e784      	b.n	5da <main+0x2a>
     6d0:	f240 0024 	movw	r0, #36	; 0x24
     6d4:	f241 11e4 	movw	r1, #4580	; 0x11e4
     6d8:	f2c0 0100 	movt	r1, #0
     6dc:	2216      	movs	r2, #22
     6de:	f2c2 0000 	movt	r0, #8192	; 0x2000
     6e2:	f000 f835 	bl	750 <MSS_UART_polled_tx>
     6e6:	2001      	movs	r0, #1
     6e8:	f7ff feaa 	bl	440 <copy_image_to_ram>
     6ec:	f7ff ff48 	bl	580 <remap_user_code_eSRAM_1>
     6f0:	e773      	b.n	5da <main+0x2a>
     6f2:	f240 0024 	movw	r0, #36	; 0x24
     6f6:	f241 11fc 	movw	r1, #4604	; 0x11fc
     6fa:	f2c0 0100 	movt	r1, #0
     6fe:	2216      	movs	r2, #22
     700:	f2c2 0000 	movt	r0, #8192	; 0x2000
     704:	f000 f824 	bl	750 <MSS_UART_polled_tx>
     708:	2002      	movs	r0, #2
     70a:	f7ff fe99 	bl	440 <copy_image_to_ram>
     70e:	f7ff ff21 	bl	554 <remap_user_code_eSRAM_0>
     712:	e762      	b.n	5da <main+0x2a>
     714:	f240 0024 	movw	r0, #36	; 0x24
     718:	f241 2114 	movw	r1, #4628	; 0x1214
     71c:	f2c0 0100 	movt	r1, #0
     720:	2216      	movs	r2, #22
     722:	f2c2 0000 	movt	r0, #8192	; 0x2000
     726:	f000 f813 	bl	750 <MSS_UART_polled_tx>
     72a:	2003      	movs	r0, #3
     72c:	f7ff fe88 	bl	440 <copy_image_to_ram>
     730:	f7ff ff26 	bl	580 <remap_user_code_eSRAM_1>
     734:	e751      	b.n	5da <main+0x2a>
     736:	f241 212c 	movw	r1, #4652	; 0x122c
     73a:	f2c2 0000 	movt	r0, #8192	; 0x2000
     73e:	f2c0 0100 	movt	r1, #0
     742:	2216      	movs	r2, #22
     744:	f000 f804 	bl	750 <MSS_UART_polled_tx>
     748:	f7ff feea 	bl	520 <remap_user_code_eNVM_128KB>
     74c:	e745      	b.n	5da <main+0x2a>
     74e:	bf00      	nop

00000750 <MSS_UART_polled_tx>:

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(pbuff != ( (uint8_t *)0));
    ASSERT(tx_size > 0u);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
     750:	f240 0364 	movw	r3, #100	; 0x64
     754:	f2c2 0300 	movt	r3, #8192	; 0x2000
     758:	4298      	cmp	r0, r3
(
    mss_uart_instance_t * this_uart,
    const uint8_t * pbuff,
    uint32_t tx_size
)
{
     75a:	e92d 05f0 	stmdb	sp!, {r4, r5, r6, r7, r8, sl}

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(pbuff != ( (uint8_t *)0));
    ASSERT(tx_size > 0u);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
     75e:	d008      	beq.n	772 <MSS_UART_polled_tx+0x22>
     760:	f240 0c24 	movw	ip, #36	; 0x24
     764:	f2c2 0c00 	movt	ip, #8192	; 0x2000
     768:	4560      	cmp	r0, ip
     76a:	d002      	beq.n	772 <MSS_UART_polled_tx+0x22>
                /* Calculate the number of untransmitted bytes remaining. */
                tx_size -= size_sent;
            }
        } while(tx_size);
    }
}
     76c:	e8bd 05f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, sl}
     770:	4770      	bx	lr

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(pbuff != ( (uint8_t *)0));
    ASSERT(tx_size > 0u);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
     772:	1e0b      	subs	r3, r1, #0
     774:	bf18      	it	ne
     776:	2301      	movne	r3, #1
     778:	2a00      	cmp	r2, #0
     77a:	bf0c      	ite	eq
     77c:	2300      	moveq	r3, #0
     77e:	f003 0301 	andne.w	r3, r3, #1
     782:	2b00      	cmp	r3, #0
     784:	d0f2      	beq.n	76c <MSS_UART_polled_tx+0x1c>
     786:	f890 800d 	ldrb.w	r8, [r0, #13]
         /* Remain in this loop until the entire input buffer
          * has been transferred to the UART.
          */
        do {
            /* Read the Line Status Register and update the sticky record */
            status = this_uart->hw_reg->LSR;
     78a:	f8d0 a000 	ldr.w	sl, [r0]
     78e:	2500      	movs	r5, #0
     790:	f89a c014 	ldrb.w	ip, [sl, #20]
            this_uart->status |= status;
     794:	ea48 080c 	orr.w	r8, r8, ip

            /* Check if TX FIFO is empty. */
            if(status & MSS_UART_THRE)
     798:	f01c 0f20 	tst.w	ip, #32
          * has been transferred to the UART.
          */
        do {
            /* Read the Line Status Register and update the sticky record */
            status = this_uart->hw_reg->LSR;
            this_uart->status |= status;
     79c:	f880 800d 	strb.w	r8, [r0, #13]

            /* Check if TX FIFO is empty. */
            if(status & MSS_UART_THRE)
     7a0:	d023      	beq.n	7ea <MSS_UART_polled_tx+0x9a>
            {
                uint32_t fill_size = TX_FIFO_SIZE;

                /* Calculate the number of bytes to transmit. */
                if(tx_size < TX_FIFO_SIZE)
     7a2:	2a0f      	cmp	r2, #15
     7a4:	d924      	bls.n	7f0 <MSS_UART_polled_tx+0xa0>
     7a6:	2710      	movs	r7, #16

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     7a8:	5d4e      	ldrb	r6, [r1, r5]
            if(status & MSS_UART_THRE)
            {
                uint32_t fill_size = TX_FIFO_SIZE;

                /* Calculate the number of bytes to transmit. */
                if(tx_size < TX_FIFO_SIZE)
     7aa:	6804      	ldr	r4, [r0, #0]
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     7ac:	2301      	movs	r3, #1
     7ae:	f107 3cff 	add.w	ip, r7, #4294967295
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     7b2:	7026      	strb	r6, [r4, #0]
     7b4:	ea0c 0603 	and.w	r6, ip, r3
                    char_idx++;
     7b8:	eb05 0c03 	add.w	ip, r5, r3
     7bc:	194d      	adds	r5, r1, r5
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     7be:	42bb      	cmp	r3, r7
     7c0:	d211      	bcs.n	7e6 <MSS_UART_polled_tx+0x96>
     7c2:	b136      	cbz	r6, 7d2 <MSS_UART_polled_tx+0x82>
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     7c4:	5cee      	ldrb	r6, [r5, r3]
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     7c6:	2302      	movs	r3, #2
     7c8:	42bb      	cmp	r3, r7
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     7ca:	7026      	strb	r6, [r4, #0]
                    char_idx++;
     7cc:	f10c 0c01 	add.w	ip, ip, #1
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     7d0:	d209      	bcs.n	7e6 <MSS_UART_polled_tx+0x96>
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     7d2:	5cee      	ldrb	r6, [r5, r3]
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     7d4:	3301      	adds	r3, #1
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     7d6:	7026      	strb	r6, [r4, #0]
     7d8:	5cee      	ldrb	r6, [r5, r3]
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     7da:	3301      	adds	r3, #1
     7dc:	42bb      	cmp	r3, r7
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     7de:	7026      	strb	r6, [r4, #0]
                    char_idx++;
     7e0:	f10c 0c02 	add.w	ip, ip, #2
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     7e4:	d3f5      	bcc.n	7d2 <MSS_UART_polled_tx+0x82>
     7e6:	4665      	mov	r5, ip
                    this_uart->hw_reg->THR = pbuff[char_idx];
                    char_idx++;
                }

                /* Calculate the number of untransmitted bytes remaining. */
                tx_size -= size_sent;
     7e8:	1ad2      	subs	r2, r2, r3
            }
        } while(tx_size);
     7ea:	2a00      	cmp	r2, #0
     7ec:	d1d0      	bne.n	790 <MSS_UART_polled_tx+0x40>
     7ee:	e7bd      	b.n	76c <MSS_UART_polled_tx+0x1c>
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     7f0:	b10a      	cbz	r2, 7f6 <MSS_UART_polled_tx+0xa6>
     7f2:	4617      	mov	r7, r2
     7f4:	e7d8      	b.n	7a8 <MSS_UART_polled_tx+0x58>
     7f6:	4613      	mov	r3, r2
                    this_uart->hw_reg->THR = pbuff[char_idx];
                    char_idx++;
                }

                /* Calculate the number of untransmitted bytes remaining. */
                tx_size -= size_sent;
     7f8:	1ad2      	subs	r2, r2, r3
     7fa:	e7f6      	b.n	7ea <MSS_UART_polled_tx+0x9a>

000007fc <MSS_UART_isr>:
{
    uint8_t iirf;

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
     7fc:	f240 0364 	movw	r3, #100	; 0x64
     800:	f2c2 0300 	movt	r3, #8192	; 0x2000
     804:	4298      	cmp	r0, r3
static void
MSS_UART_isr
(
    mss_uart_instance_t * this_uart
)
{
     806:	b510      	push	{r4, lr}
     808:	4604      	mov	r4, r0
    uint8_t iirf;

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
     80a:	d006      	beq.n	81a <MSS_UART_isr+0x1e>
     80c:	f240 0024 	movw	r0, #36	; 0x24
     810:	f2c2 0000 	movt	r0, #8192	; 0x2000
     814:	4284      	cmp	r4, r0
     816:	d000      	beq.n	81a <MSS_UART_isr+0x1e>
     818:	bd10      	pop	{r4, pc}
    {
        iirf = this_uart->hw_reg->IIR & IIRF_MASK;
     81a:	6822      	ldr	r2, [r4, #0]
     81c:	7a11      	ldrb	r1, [r2, #8]

        switch (iirf)
     81e:	f001 0c0f 	and.w	ip, r1, #15
     822:	f1bc 0f0c 	cmp.w	ip, #12
     826:	d8f7      	bhi.n	818 <MSS_UART_isr+0x1c>
     828:	a101      	add	r1, pc, #4	; (adr r1, 830 <MSS_UART_isr+0x34>)
     82a:	f851 f02c 	ldr.w	pc, [r1, ip, lsl #2]
     82e:	bf00      	nop
     830:	00000881 	.word	0x00000881
     834:	00000819 	.word	0x00000819
     838:	00000879 	.word	0x00000879
     83c:	00000889 	.word	0x00000889
     840:	00000871 	.word	0x00000871
     844:	00000819 	.word	0x00000819
     848:	00000865 	.word	0x00000865
     84c:	00000819 	.word	0x00000819
     850:	00000819 	.word	0x00000819
     854:	00000819 	.word	0x00000819
     858:	00000819 	.word	0x00000819
     85c:	00000819 	.word	0x00000819
     860:	00000871 	.word	0x00000871
            break;

            case IIRF_RX_LINE_STATUS:  /* Line Status Interrupt */
            {
                ASSERT(NULL_HANDLER != this_uart->linests_handler);
                if(NULL_HANDLER != this_uart->linests_handler)
     864:	69e3      	ldr	r3, [r4, #28]
     866:	2b00      	cmp	r3, #0
     868:	d0d6      	beq.n	818 <MSS_UART_isr+0x1c>
                {
                   (*(this_uart->linests_handler))(this_uart);
     86a:	4620      	mov	r0, r4
     86c:	4798      	blx	r3
     86e:	bd10      	pop	{r4, pc}

            case IIRF_RX_DATA:      /* Received Data Available */
            case IIRF_DATA_TIMEOUT: /* Received Data Timed-out */
            {
                ASSERT(NULL_HANDLER != this_uart->rx_handler);
                if(NULL_HANDLER != this_uart->rx_handler)
     870:	6a23      	ldr	r3, [r4, #32]
     872:	2b00      	cmp	r3, #0
     874:	d1f9      	bne.n	86a <MSS_UART_isr+0x6e>
     876:	e7cf      	b.n	818 <MSS_UART_isr+0x1c>
            break;

            case IIRF_THRE: /* Transmitter Holding Register Empty */
            {
                ASSERT(NULL_HANDLER != this_uart->tx_handler);
                if(NULL_HANDLER != this_uart->tx_handler)
     878:	6a63      	ldr	r3, [r4, #36]	; 0x24
     87a:	2b00      	cmp	r3, #0
     87c:	d1f5      	bne.n	86a <MSS_UART_isr+0x6e>
     87e:	e7cb      	b.n	818 <MSS_UART_isr+0x1c>
        switch (iirf)
        {
            case IIRF_MODEM_STATUS:  /* Modem status interrupt */
            {
                ASSERT(NULL_HANDLER != this_uart->modemsts_handler);
                if(NULL_HANDLER != this_uart->modemsts_handler)
     880:	6aa3      	ldr	r3, [r4, #40]	; 0x28
     882:	2b00      	cmp	r3, #0
     884:	d1f1      	bne.n	86a <MSS_UART_isr+0x6e>
     886:	e7c7      	b.n	818 <MSS_UART_isr+0x1c>
            case IIRF_MMI:
            {
                /* Identify multimode interrupts and handle */

                /* Receiver time-out interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,ERTOI))
     888:	3228      	adds	r2, #40	; 0x28
{
    return (HW_REG_BIT(reg,bit));
}
static __INLINE uint8_t read_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    return (HW_REG_BIT(reg,bit));
     88a:	f022 407f 	bic.w	r0, r2, #4278190080	; 0xff000000
     88e:	f420 0370 	bic.w	r3, r0, #15728640	; 0xf00000
     892:	f002 4170 	and.w	r1, r2, #4026531840	; 0xf0000000
     896:	0158      	lsls	r0, r3, #5
     898:	f101 7c00 	add.w	ip, r1, #33554432	; 0x2000000
     89c:	f85c 3000 	ldr.w	r3, [ip, r0]
     8a0:	f013 0fff 	tst.w	r3, #255	; 0xff
     8a4:	d005      	beq.n	8b2 <MSS_UART_isr+0xb6>
                {
                    ASSERT(NULL_HANDLER != this_uart->rto_handler);
                    if(NULL_HANDLER != this_uart->rto_handler)
     8a6:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
     8a8:	b11b      	cbz	r3, 8b2 <MSS_UART_isr+0xb6>
                    {
                        (*(this_uart->rto_handler))(this_uart);
     8aa:	4620      	mov	r0, r4
     8ac:	4798      	blx	r3
     8ae:	6822      	ldr	r2, [r4, #0]
     8b0:	3228      	adds	r2, #40	; 0x28
     8b2:	f002 4070 	and.w	r0, r2, #4026531840	; 0xf0000000
     8b6:	f022 4c7f 	bic.w	ip, r2, #4278190080	; 0xff000000
     8ba:	f100 7300 	add.w	r3, r0, #33554432	; 0x2000000
     8be:	f42c 0170 	bic.w	r1, ip, #15728640	; 0xf00000
     8c2:	1d18      	adds	r0, r3, #4
     8c4:	0149      	lsls	r1, r1, #5
     8c6:	5843      	ldr	r3, [r0, r1]
                    }
                }
                /* NACK interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,ENACKI))
     8c8:	f013 0fff 	tst.w	r3, #255	; 0xff
     8cc:	d005      	beq.n	8da <MSS_UART_isr+0xde>
                {
                    ASSERT(NULL_HANDLER != this_uart->nack_handler);
                    if(NULL_HANDLER != this_uart->nack_handler)
     8ce:	6b23      	ldr	r3, [r4, #48]	; 0x30
     8d0:	b11b      	cbz	r3, 8da <MSS_UART_isr+0xde>
                    {
                        (*(this_uart->nack_handler))(this_uart);
     8d2:	4620      	mov	r0, r4
     8d4:	4798      	blx	r3
     8d6:	6822      	ldr	r2, [r4, #0]
     8d8:	3228      	adds	r2, #40	; 0x28
     8da:	f002 4370 	and.w	r3, r2, #4026531840	; 0xf0000000
     8de:	f022 4c7f 	bic.w	ip, r2, #4278190080	; 0xff000000
     8e2:	f103 7000 	add.w	r0, r3, #33554432	; 0x2000000
     8e6:	f42c 0170 	bic.w	r1, ip, #15728640	; 0xf00000
     8ea:	3008      	adds	r0, #8
     8ec:	0149      	lsls	r1, r1, #5
     8ee:	5843      	ldr	r3, [r0, r1]
                    }
                }

                /* PID parity error interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,EPID_PEI))
     8f0:	f013 0fff 	tst.w	r3, #255	; 0xff
     8f4:	d005      	beq.n	902 <MSS_UART_isr+0x106>
                {
                    ASSERT(NULL_HANDLER != this_uart->pid_pei_handler);
                    if(NULL_HANDLER != this_uart->pid_pei_handler)
     8f6:	6b63      	ldr	r3, [r4, #52]	; 0x34
     8f8:	b11b      	cbz	r3, 902 <MSS_UART_isr+0x106>
                    {
                        (*(this_uart->pid_pei_handler))(this_uart);
     8fa:	4620      	mov	r0, r4
     8fc:	4798      	blx	r3
     8fe:	6822      	ldr	r2, [r4, #0]
     900:	3228      	adds	r2, #40	; 0x28
     902:	f002 4370 	and.w	r3, r2, #4026531840	; 0xf0000000
     906:	f022 4c7f 	bic.w	ip, r2, #4278190080	; 0xff000000
     90a:	f42c 0070 	bic.w	r0, ip, #15728640	; 0xf00000
     90e:	f103 7300 	add.w	r3, r3, #33554432	; 0x2000000
     912:	330c      	adds	r3, #12
     914:	0141      	lsls	r1, r0, #5
     916:	5858      	ldr	r0, [r3, r1]
                    }
                }

                /* LIN break detection interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,ELINBI))
     918:	f010 0fff 	tst.w	r0, #255	; 0xff
     91c:	d005      	beq.n	92a <MSS_UART_isr+0x12e>
                {
                    ASSERT(NULL_HANDLER != this_uart->break_handler);
                    if(NULL_HANDLER != this_uart->break_handler)
     91e:	6ba3      	ldr	r3, [r4, #56]	; 0x38
     920:	b11b      	cbz	r3, 92a <MSS_UART_isr+0x12e>
                    {
                        (*(this_uart->break_handler))(this_uart);
     922:	4620      	mov	r0, r4
     924:	4798      	blx	r3
     926:	6822      	ldr	r2, [r4, #0]
     928:	3228      	adds	r2, #40	; 0x28
     92a:	f022 4c7f 	bic.w	ip, r2, #4278190080	; 0xff000000
     92e:	f002 4170 	and.w	r1, r2, #4026531840	; 0xf0000000
     932:	f101 7200 	add.w	r2, r1, #33554432	; 0x2000000
     936:	f42c 0370 	bic.w	r3, ip, #15728640	; 0xf00000
     93a:	3210      	adds	r2, #16
     93c:	0158      	lsls	r0, r3, #5
     93e:	5811      	ldr	r1, [r2, r0]
                    }
                }

                /* LIN Sync detection interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,ELINSI))
     940:	f011 0fff 	tst.w	r1, #255	; 0xff
     944:	f43f af68 	beq.w	818 <MSS_UART_isr+0x1c>
                {
                    ASSERT(NULL_HANDLER != this_uart->sync_handler);
                    if(NULL_HANDLER != this_uart->sync_handler)
     948:	6be3      	ldr	r3, [r4, #60]	; 0x3c
     94a:	2b00      	cmp	r3, #0
     94c:	f43f af64 	beq.w	818 <MSS_UART_isr+0x1c>
                    {
                        (*(this_uart->sync_handler))(this_uart);
     950:	4620      	mov	r0, r4
     952:	4798      	blx	r3
     954:	e760      	b.n	818 <MSS_UART_isr+0x1c>
     956:	bf00      	nop

00000958 <UART1_IRQHandler>:
#if defined(__GNUC__)
__attribute__((__interrupt__)) void UART1_IRQHandler(void)
#else
void UART1_IRQHandler(void)
#endif
{
     958:	4668      	mov	r0, sp
     95a:	f020 0107 	bic.w	r1, r0, #7
     95e:	468d      	mov	sp, r1
     960:	b501      	push	{r0, lr}
    MSS_UART_isr(&g_mss_uart1);
     962:	f240 0024 	movw	r0, #36	; 0x24
     966:	f2c2 0000 	movt	r0, #8192	; 0x2000
     96a:	f7ff ff47 	bl	7fc <MSS_UART_isr>
}
     96e:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
     972:	4685      	mov	sp, r0
     974:	4770      	bx	lr
     976:	bf00      	nop

00000978 <UART0_IRQHandler>:
#if defined(__GNUC__)
__attribute__((__interrupt__)) void UART0_IRQHandler(void)
#else
void UART0_IRQHandler(void)
#endif
{
     978:	4668      	mov	r0, sp
     97a:	f020 0107 	bic.w	r1, r0, #7
     97e:	468d      	mov	sp, r1
     980:	b501      	push	{r0, lr}
    MSS_UART_isr(&g_mss_uart0);
     982:	f240 0064 	movw	r0, #100	; 0x64
     986:	f2c2 0000 	movt	r0, #8192	; 0x2000
     98a:	f7ff ff37 	bl	7fc <MSS_UART_isr>
}
     98e:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
     992:	4685      	mov	sp, r0
     994:	4770      	bx	lr
     996:	bf00      	nop

00000998 <default_tx_handler>:

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(( (uint8_t *)0 ) != this_uart->tx_buffer);
    ASSERT(0u < this_uart->tx_buff_size);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
     998:	f240 0364 	movw	r3, #100	; 0x64
     99c:	f2c2 0300 	movt	r3, #8192	; 0x2000
     9a0:	4298      	cmp	r0, r3
static void
default_tx_handler
(
    mss_uart_instance_t * this_uart
)
{
     9a2:	b470      	push	{r4, r5, r6}

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(( (uint8_t *)0 ) != this_uart->tx_buffer);
    ASSERT(0u < this_uart->tx_buff_size);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
     9a4:	d007      	beq.n	9b6 <default_tx_handler+0x1e>
     9a6:	f240 0124 	movw	r1, #36	; 0x24
     9aa:	f2c2 0100 	movt	r1, #8192	; 0x2000
     9ae:	4288      	cmp	r0, r1
     9b0:	d001      	beq.n	9b6 <default_tx_handler+0x1e>
            this_uart->tx_buff_size = TX_COMPLETE;
            /* disables TX interrupt */
            clear_bit_reg8(&this_uart->hw_reg->IER,ETBEI);
        }
    }
}
     9b2:	bc70      	pop	{r4, r5, r6}
     9b4:	4770      	bx	lr
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(( (uint8_t *)0 ) != this_uart->tx_buffer);
    ASSERT(0u < this_uart->tx_buff_size);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
       (((uint8_t *)0 ) != this_uart->tx_buffer) &&
     9b6:	6904      	ldr	r4, [r0, #16]
     9b8:	2c00      	cmp	r4, #0
     9ba:	d0fa      	beq.n	9b2 <default_tx_handler+0x1a>
       (0u < this_uart->tx_buff_size))
     9bc:	6943      	ldr	r3, [r0, #20]
     9be:	2b00      	cmp	r3, #0
     9c0:	d0f7      	beq.n	9b2 <default_tx_handler+0x1a>
    {
        /* Read the Line Status Register and update the sticky record. */
        status = this_uart->hw_reg->LSR;
     9c2:	6801      	ldr	r1, [r0, #0]
        this_uart->status |= status;
     9c4:	f890 c00d 	ldrb.w	ip, [r0, #13]
    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
       (((uint8_t *)0 ) != this_uart->tx_buffer) &&
       (0u < this_uart->tx_buff_size))
    {
        /* Read the Line Status Register and update the sticky record. */
        status = this_uart->hw_reg->LSR;
     9c8:	7d0a      	ldrb	r2, [r1, #20]
        this_uart->status |= status;
     9ca:	ea42 0c0c 	orr.w	ip, r2, ip

        /*
         * This function should only be called as a result of a THRE interrupt.
         * Verify that this is true before proceeding to transmit data.
         */
        if(status & MSS_UART_THRE)
     9ce:	f012 0f20 	tst.w	r2, #32
       (((uint8_t *)0 ) != this_uart->tx_buffer) &&
       (0u < this_uart->tx_buff_size))
    {
        /* Read the Line Status Register and update the sticky record. */
        status = this_uart->hw_reg->LSR;
        this_uart->status |= status;
     9d2:	f880 c00d 	strb.w	ip, [r0, #13]

        /*
         * This function should only be called as a result of a THRE interrupt.
         * Verify that this is true before proceeding to transmit data.
         */
        if(status & MSS_UART_THRE)
     9d6:	6982      	ldr	r2, [r0, #24]
     9d8:	d029      	beq.n	a2e <default_tx_handler+0x96>
        {
            uint32_t i;
            uint32_t fill_size = TX_FIFO_SIZE;
            uint32_t tx_remain = this_uart->tx_buff_size - this_uart->tx_idx;
     9da:	1a9d      	subs	r5, r3, r2

            /* Calculate the number of bytes to transmit. */
            if(tx_remain < TX_FIFO_SIZE)
     9dc:	2d0f      	cmp	r5, #15
     9de:	d938      	bls.n	a52 <default_tx_handler+0xba>
     9e0:	2510      	movs	r5, #16
     9e2:	18a4      	adds	r4, r4, r2

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     9e4:	7826      	ldrb	r6, [r4, #0]
     9e6:	1e6b      	subs	r3, r5, #1
     9e8:	700e      	strb	r6, [r1, #0]
     9ea:	f003 0601 	and.w	r6, r3, #1
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     9ee:	2301      	movs	r3, #1
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
                ++this_uart->tx_idx;
     9f0:	3201      	adds	r2, #1
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     9f2:	429d      	cmp	r5, r3
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
                ++this_uart->tx_idx;
     9f4:	6182      	str	r2, [r0, #24]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     9f6:	d919      	bls.n	a2c <default_tx_handler+0x94>
     9f8:	b146      	cbz	r6, a0c <default_tx_handler+0x74>
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     9fa:	f894 c001 	ldrb.w	ip, [r4, #1]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     9fe:	2302      	movs	r3, #2
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
                ++this_uart->tx_idx;
     a00:	3201      	adds	r2, #1
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     a02:	429d      	cmp	r5, r3
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     a04:	f881 c000 	strb.w	ip, [r1]
                ++this_uart->tx_idx;
     a08:	6182      	str	r2, [r0, #24]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     a0a:	d90f      	bls.n	a2c <default_tx_handler+0x94>
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     a0c:	f814 c003 	ldrb.w	ip, [r4, r3]
                ++this_uart->tx_idx;
     a10:	3201      	adds	r2, #1

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     a12:	f881 c000 	strb.w	ip, [r1]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     a16:	3301      	adds	r3, #1
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
                ++this_uart->tx_idx;
     a18:	6182      	str	r2, [r0, #24]

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     a1a:	f814 c003 	ldrb.w	ip, [r4, r3]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     a1e:	3301      	adds	r3, #1
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
                ++this_uart->tx_idx;
     a20:	3201      	adds	r2, #1
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     a22:	429d      	cmp	r5, r3
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     a24:	f881 c000 	strb.w	ip, [r1]
                ++this_uart->tx_idx;
     a28:	6182      	str	r2, [r0, #24]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     a2a:	d8ef      	bhi.n	a0c <default_tx_handler+0x74>
     a2c:	6943      	ldr	r3, [r0, #20]
                ++this_uart->tx_idx;
            }
        }

        /* Flag Tx as complete if all data has been pushed into the Tx FIFO. */
        if(this_uart->tx_idx == this_uart->tx_buff_size)
     a2e:	429a      	cmp	r2, r3
     a30:	d1bf      	bne.n	9b2 <default_tx_handler+0x1a>
        {
            this_uart->tx_buff_size = TX_COMPLETE;
            /* disables TX interrupt */
            clear_bit_reg8(&this_uart->hw_reg->IER,ETBEI);
     a32:	6802      	ldr	r2, [r0, #0]
        }

        /* Flag Tx as complete if all data has been pushed into the Tx FIFO. */
        if(this_uart->tx_idx == this_uart->tx_buff_size)
        {
            this_uart->tx_buff_size = TX_COMPLETE;
     a34:	2100      	movs	r1, #0
            /* disables TX interrupt */
            clear_bit_reg8(&this_uart->hw_reg->IER,ETBEI);
     a36:	1d13      	adds	r3, r2, #4
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     a38:	f023 4c7f 	bic.w	ip, r3, #4278190080	; 0xff000000
     a3c:	f003 4270 	and.w	r2, r3, #4026531840	; 0xf0000000
     a40:	f102 7300 	add.w	r3, r2, #33554432	; 0x2000000
     a44:	f42c 0270 	bic.w	r2, ip, #15728640	; 0xf00000
     a48:	3304      	adds	r3, #4
     a4a:	0152      	lsls	r2, r2, #5
     a4c:	5099      	str	r1, [r3, r2]
        }

        /* Flag Tx as complete if all data has been pushed into the Tx FIFO. */
        if(this_uart->tx_idx == this_uart->tx_buff_size)
        {
            this_uart->tx_buff_size = TX_COMPLETE;
     a4e:	6141      	str	r1, [r0, #20]
     a50:	e7af      	b.n	9b2 <default_tx_handler+0x1a>
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     a52:	2d00      	cmp	r5, #0
     a54:	d1c5      	bne.n	9e2 <default_tx_handler+0x4a>
     a56:	e7ea      	b.n	a2e <default_tx_handler+0x96>

00000a58 <global_init>:
(
    mss_uart_instance_t * this_uart,
    uint32_t baud_rate,
    uint8_t line_config
)
{
     a58:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
     a5c:	f240 0364 	movw	r3, #100	; 0x64
(
    mss_uart_instance_t * this_uart,
    uint32_t baud_rate,
    uint8_t line_config
)
{
     a60:	b08f      	sub	sp, #60	; 0x3c
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
     a62:	f2c2 0300 	movt	r3, #8192	; 0x2000
(
    mss_uart_instance_t * this_uart,
    uint32_t baud_rate,
    uint8_t line_config
)
{
     a66:	920b      	str	r2, [sp, #44]	; 0x2c
    if(this_uart == &g_mss_uart0)
    {
        this_uart->hw_reg = UART0;
        this_uart->irqn = UART0_IRQn;
        /* reset UART0 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART0_SOFTRESET_MASK;
     a68:	f248 0200 	movw	r2, #32768	; 0x8000
{
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
     a6c:	4298      	cmp	r0, r3
    {
        this_uart->hw_reg = UART0;
        this_uart->irqn = UART0_IRQn;
        /* reset UART0 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART0_SOFTRESET_MASK;
     a6e:	f2c4 0203 	movt	r2, #16387	; 0x4003
(
    mss_uart_instance_t * this_uart,
    uint32_t baud_rate,
    uint8_t line_config
)
{
     a72:	4604      	mov	r4, r0
     a74:	910d      	str	r1, [sp, #52]	; 0x34
    if(this_uart == &g_mss_uart0)
    {
        this_uart->hw_reg = UART0;
        this_uart->irqn = UART0_IRQn;
        /* reset UART0 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART0_SOFTRESET_MASK;
     a76:	6c90      	ldr	r0, [r2, #72]	; 0x48

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
     a78:	f24e 1100 	movw	r1, #57600	; 0xe100
{
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
     a7c:	f000 8129 	beq.w	cd2 <global_init+0x27a>
    else
    {
        this_uart->hw_reg = UART1;
        this_uart->irqn = UART1_IRQn;
        /* Reset UART1 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART1_SOFTRESET_MASK;
     a80:	f440 7780 	orr.w	r7, r0, #256	; 0x100
     a84:	f2ce 0100 	movt	r1, #57344	; 0xe000
     a88:	f44f 6600 	mov.w	r6, #2048	; 0x800
     a8c:	6497      	str	r7, [r2, #72]	; 0x48
     a8e:	f8c1 6180 	str.w	r6, [r1, #384]	; 0x180
        /* Clear any previously pended UART1 interrupt */
        NVIC_ClearPendingIRQ(UART1_IRQn);
        /* Take UART1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART1_SOFTRESET_MASK;
     a92:	6c95      	ldr	r5, [r2, #72]	; 0x48
        /* Take UART0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
    }
    else
    {
        this_uart->hw_reg = UART1;
     a94:	f240 0100 	movw	r1, #0
        /* Reset UART1 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART1_SOFTRESET_MASK;
        /* Clear any previously pended UART1 interrupt */
        NVIC_ClearPendingIRQ(UART1_IRQn);
        /* Take UART1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART1_SOFTRESET_MASK;
     a98:	f425 7080 	bic.w	r0, r5, #256	; 0x100
        /* Take UART0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
    }
    else
    {
        this_uart->hw_reg = UART1;
     a9c:	f2c4 0101 	movt	r1, #16385	; 0x4001
        /* Reset UART1 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART1_SOFTRESET_MASK;
        /* Clear any previously pended UART1 interrupt */
        NVIC_ClearPendingIRQ(UART1_IRQn);
        /* Take UART1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART1_SOFTRESET_MASK;
     aa0:	6490      	str	r0, [r2, #72]	; 0x48
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
    }
    else
    {
        this_uart->hw_reg = UART1;
        this_uart->irqn = UART1_IRQn;
     aa2:	220b      	movs	r2, #11
     aa4:	7122      	strb	r2, [r4, #4]
        /* Take UART0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
    }
    else
    {
        this_uart->hw_reg = UART1;
     aa6:	6021      	str	r1, [r4, #0]
        /* Take UART1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART1_SOFTRESET_MASK;
    }

    /* disable interrupts */
    this_uart->hw_reg->IER = 0u;
     aa8:	2200      	movs	r2, #0

    /* FIFO configuration */
    this_uart->hw_reg->FCR = (uint8_t)MSS_UART_FIFO_SINGLE_BYTE;
     aaa:	460d      	mov	r5, r1
        /* Take UART1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART1_SOFTRESET_MASK;
    }

    /* disable interrupts */
    this_uart->hw_reg->IER = 0u;
     aac:	710a      	strb	r2, [r1, #4]
    /* enable RXRDYN and TXRDYN pins. The earlier FCR write to set the TX FIFO
     * trigger level inadvertently disabled the FCR_RXRDY_TXRDYN_EN bit. */
    set_bit_reg8(&this_uart->hw_reg->FCR,RXRDY_TXRDYN_EN);

    /* disable loopback : local * remote */
    clear_bit_reg8(&this_uart->hw_reg->MCR,LOOP);
     aae:	f101 0610 	add.w	r6, r1, #16

    /* disable interrupts */
    this_uart->hw_reg->IER = 0u;

    /* FIFO configuration */
    this_uart->hw_reg->FCR = (uint8_t)MSS_UART_FIFO_SINGLE_BYTE;
     ab2:	f805 2f08 	strb.w	r2, [r5, #8]!
    clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_TX);
    /* set default RX endian */
    clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_RX);

    /* default AFM : disabled */
    clear_bit_reg8(&this_uart->hw_reg->MM2,EAFM);
     ab6:	f101 0a38 	add.w	sl, r1, #56	; 0x38
     aba:	f02a 4b7f 	bic.w	fp, sl, #4278190080	; 0xff000000
    /* disable loopback : local * remote */
    clear_bit_reg8(&this_uart->hw_reg->MCR,LOOP);
    clear_bit_reg8(&this_uart->hw_reg->MCR,RLOOP);

    /* set default TX endian */
    clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_TX);
     abe:	f101 0934 	add.w	r9, r1, #52	; 0x34
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     ac2:	f025 477f 	bic.w	r7, r5, #4278190080	; 0xff000000
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     ac6:	f026 487f 	bic.w	r8, r6, #4278190080	; 0xff000000
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     aca:	f005 4570 	and.w	r5, r5, #4026531840	; 0xf0000000
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     ace:	f006 4670 	and.w	r6, r6, #4026531840	; 0xf0000000
     ad2:	f00a 4a70 	and.w	sl, sl, #4026531840	; 0xf0000000
     ad6:	f8cd a010 	str.w	sl, [sp, #16]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     ada:	9506      	str	r5, [sp, #24]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     adc:	f029 407f 	bic.w	r0, r9, #4278190080	; 0xff000000
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     ae0:	f106 7500 	add.w	r5, r6, #33554432	; 0x2000000
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     ae4:	9003      	str	r0, [sp, #12]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     ae6:	9501      	str	r5, [sp, #4]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     ae8:	f009 4970 	and.w	r9, r9, #4026531840	; 0xf0000000
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     aec:	9d04      	ldr	r5, [sp, #16]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     aee:	f8cd 901c 	str.w	r9, [sp, #28]
     af2:	f8dd 900c 	ldr.w	r9, [sp, #12]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     af6:	f105 7500 	add.w	r5, r5, #33554432	; 0x2000000
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     afa:	f429 0a70 	bic.w	sl, r9, #15728640	; 0xf00000
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     afe:	950a      	str	r5, [sp, #40]	; 0x28
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     b00:	f42b 0970 	bic.w	r9, fp, #15728640	; 0xf00000
     b04:	9d07      	ldr	r5, [sp, #28]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     b06:	f8dd b018 	ldr.w	fp, [sp, #24]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     b0a:	f8cd 9014 	str.w	r9, [sp, #20]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     b0e:	f10b 7900 	add.w	r9, fp, #33554432	; 0x2000000
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     b12:	f105 7b00 	add.w	fp, r5, #33554432	; 0x2000000
     b16:	9d04      	ldr	r5, [sp, #16]

    /* default AFM : disabled */
    clear_bit_reg8(&this_uart->hw_reg->MM2,EAFM);

    /* disable TX time gaurd */
    clear_bit_reg8(&this_uart->hw_reg->MM0,ETTG); 
     b18:	f101 0c30 	add.w	ip, r1, #48	; 0x30
     b1c:	f02c 407f 	bic.w	r0, ip, #4278190080	; 0xff000000
     b20:	f105 7500 	add.w	r5, r5, #33554432	; 0x2000000
     b24:	f00c 4c70 	and.w	ip, ip, #4026531840	; 0xf0000000
     b28:	f8cd a00c 	str.w	sl, [sp, #12]
     b2c:	9504      	str	r5, [sp, #16]
     b2e:	f10c 7500 	add.w	r5, ip, #33554432	; 0x2000000
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     b32:	f10c 7a00 	add.w	sl, ip, #33554432	; 0x2000000
     b36:	46ac      	mov	ip, r5
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     b38:	9d03      	ldr	r5, [sp, #12]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     b3a:	f8cd a024 	str.w	sl, [sp, #36]	; 0x24
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     b3e:	016d      	lsls	r5, r5, #5
     b40:	9503      	str	r5, [sp, #12]
     b42:	9d05      	ldr	r5, [sp, #20]
     b44:	f428 0870 	bic.w	r8, r8, #15728640	; 0xf00000
     b48:	016d      	lsls	r5, r5, #5
     b4a:	9505      	str	r5, [sp, #20]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     b4c:	9d06      	ldr	r5, [sp, #24]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     b4e:	46ca      	mov	sl, r9
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     b50:	f105 7500 	add.w	r5, r5, #33554432	; 0x2000000
     b54:	9506      	str	r5, [sp, #24]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     b56:	9d01      	ldr	r5, [sp, #4]
     b58:	ea4f 1848 	mov.w	r8, r8, lsl #5
     b5c:	3514      	adds	r5, #20
     b5e:	9501      	str	r5, [sp, #4]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     b60:	9d07      	ldr	r5, [sp, #28]
     b62:	f427 0770 	bic.w	r7, r7, #15728640	; 0xf00000
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     b66:	f105 7500 	add.w	r5, r5, #33554432	; 0x2000000
     b6a:	9507      	str	r5, [sp, #28]
     b6c:	9d04      	ldr	r5, [sp, #16]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     b6e:	017f      	lsls	r7, r7, #5
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     b70:	3504      	adds	r5, #4
     b72:	9504      	str	r5, [sp, #16]
     b74:	4665      	mov	r5, ip
     b76:	3514      	adds	r5, #20
     b78:	9508      	str	r5, [sp, #32]
     b7a:	9d09      	ldr	r5, [sp, #36]	; 0x24
     b7c:	f8cd 8030 	str.w	r8, [sp, #48]	; 0x30
     b80:	351c      	adds	r5, #28
     b82:	9509      	str	r5, [sp, #36]	; 0x24
     b84:	9d0a      	ldr	r5, [sp, #40]	; 0x28
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     b86:	f04f 0801 	mov.w	r8, #1
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     b8a:	350c      	adds	r5, #12
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     b8c:	f10a 0a08 	add.w	sl, sl, #8
     b90:	f109 0904 	add.w	r9, r9, #4
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     b94:	950a      	str	r5, [sp, #40]	; 0x28
     b96:	f106 7600 	add.w	r6, r6, #33554432	; 0x2000000
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     b9a:	f849 8007 	str.w	r8, [r9, r7]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     b9e:	9d0c      	ldr	r5, [sp, #48]	; 0x30
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     ba0:	f84a 8007 	str.w	r8, [sl, r7]
     ba4:	f8dd a018 	ldr.w	sl, [sp, #24]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     ba8:	3610      	adds	r6, #16
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     baa:	f84a 8007 	str.w	r8, [sl, r7]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     bae:	5172      	str	r2, [r6, r5]
     bb0:	f8dd a00c 	ldr.w	sl, [sp, #12]
     bb4:	9e01      	ldr	r6, [sp, #4]
     bb6:	f10b 0b04 	add.w	fp, fp, #4
     bba:	5172      	str	r2, [r6, r5]
     bbc:	f84b 200a 	str.w	r2, [fp, sl]
     bc0:	f8dd b01c 	ldr.w	fp, [sp, #28]
     bc4:	9d05      	ldr	r5, [sp, #20]
     bc6:	f84b 200a 	str.w	r2, [fp, sl]
     bca:	9e04      	ldr	r6, [sp, #16]
     bcc:	f8dd a020 	ldr.w	sl, [sp, #32]
     bd0:	f420 0070 	bic.w	r0, r0, #15728640	; 0xf00000
     bd4:	0140      	lsls	r0, r0, #5
     bd6:	f10c 0c18 	add.w	ip, ip, #24
     bda:	5172      	str	r2, [r6, r5]
     bdc:	f8dd b024 	ldr.w	fp, [sp, #36]	; 0x24
     be0:	f84a 2000 	str.w	r2, [sl, r0]
     be4:	f84c 2000 	str.w	r2, [ip, r0]
     be8:	f8dd c028 	ldr.w	ip, [sp, #40]	; 0x28
    uint32_t baudrate    
)
{
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    
    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
     bec:	429c      	cmp	r4, r3
     bee:	f84b 2000 	str.w	r2, [fp, r0]
     bf2:	f84c 2005 	str.w	r2, [ip, r5]

    /* disable single wire mode */
    clear_bit_reg8(&this_uart->hw_reg->MM2,ESWM);

    /* set filter to minimum value */
    this_uart->hw_reg->GFR = 0u;
     bf6:	f881 2044 	strb.w	r2, [r1, #68]	; 0x44
    /* set default TX time gaurd */
    this_uart->hw_reg->TTG = 0u;
     bfa:	f881 2048 	strb.w	r2, [r1, #72]	; 0x48
    /* set default RX timeout */
    this_uart->hw_reg->RTO = 0u;
     bfe:	f881 204c 	strb.w	r2, [r1, #76]	; 0x4c
    uint32_t baudrate    
)
{
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    
    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
     c02:	d079      	beq.n	cf8 <global_init+0x2a0>
     c04:	f240 0324 	movw	r3, #36	; 0x24
     c08:	f2c2 0300 	movt	r3, #8192	; 0x2000
     c0c:	429c      	cmp	r4, r3
     c0e:	d015      	beq.n	c3c <global_init+0x1e4>
     * where possible to provide the most accurate baud rat possible.
     */
    config_baud_divisors(this_uart, baud_rate);

    /* set the line control register (bit length, stop bits, parity) */
    this_uart->hw_reg->LCR = line_config;
     c10:	9d0b      	ldr	r5, [sp, #44]	; 0x2c

    /* Instance setup */
    this_uart->baudrate = baud_rate;
    this_uart->lineconfig = line_config;
    this_uart->tx_buff_size = TX_COMPLETE;
     c12:	2000      	movs	r0, #0
     * where possible to provide the most accurate baud rat possible.
     */
    config_baud_divisors(this_uart, baud_rate);

    /* set the line control register (bit length, stop bits, parity) */
    this_uart->hw_reg->LCR = line_config;
     c14:	730d      	strb	r5, [r1, #12]
    this_uart->pid_pei_handler  = NULL_HANDLER;
    this_uart->break_handler    = NULL_HANDLER;    
    this_uart->sync_handler     = NULL_HANDLER;   

    /* Initialize the sticky status */
    this_uart->status = 0u;
     c16:	7360      	strb	r0, [r4, #13]

    /* set the line control register (bit length, stop bits, parity) */
    this_uart->hw_reg->LCR = line_config;

    /* Instance setup */
    this_uart->baudrate = baud_rate;
     c18:	9e0d      	ldr	r6, [sp, #52]	; 0x34
    this_uart->lineconfig = line_config;
    this_uart->tx_buff_size = TX_COMPLETE;
     c1a:	6160      	str	r0, [r4, #20]

    /* set the line control register (bit length, stop bits, parity) */
    this_uart->hw_reg->LCR = line_config;

    /* Instance setup */
    this_uart->baudrate = baud_rate;
     c1c:	60a6      	str	r6, [r4, #8]
    this_uart->lineconfig = line_config;
     c1e:	7325      	strb	r5, [r4, #12]
    this_uart->tx_buff_size = TX_COMPLETE;
    this_uart->tx_buffer = (const uint8_t *)0;
     c20:	6120      	str	r0, [r4, #16]
    this_uart->tx_idx = 0u;
     c22:	61a0      	str	r0, [r4, #24]

    /* Default handlers for MSS UART interrupts */
    this_uart->rx_handler       = NULL_HANDLER;
     c24:	6220      	str	r0, [r4, #32]
    this_uart->tx_handler       = NULL_HANDLER;
     c26:	6260      	str	r0, [r4, #36]	; 0x24
    this_uart->linests_handler  = NULL_HANDLER;
     c28:	61e0      	str	r0, [r4, #28]
    this_uart->modemsts_handler = NULL_HANDLER;
     c2a:	62a0      	str	r0, [r4, #40]	; 0x28
    this_uart->rto_handler      = NULL_HANDLER;    
     c2c:	62e0      	str	r0, [r4, #44]	; 0x2c
    this_uart->nack_handler     = NULL_HANDLER;   
     c2e:	6320      	str	r0, [r4, #48]	; 0x30
    this_uart->pid_pei_handler  = NULL_HANDLER;
     c30:	6360      	str	r0, [r4, #52]	; 0x34
    this_uart->break_handler    = NULL_HANDLER;    
     c32:	63a0      	str	r0, [r4, #56]	; 0x38
    this_uart->sync_handler     = NULL_HANDLER;   
     c34:	63e0      	str	r0, [r4, #60]	; 0x3c

    /* Initialize the sticky status */
    this_uart->status = 0u;
}
     c36:	b00f      	add	sp, #60	; 0x3c
     c38:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
        uint32_t baud_value_by_64;
        uint32_t baud_value_by_128;
        uint32_t fractional_baud_value;
        uint32_t pclk_freq;

        this_uart->baudrate = baudrate;
     c3c:	9f0d      	ldr	r7, [sp, #52]	; 0x34
     c3e:	60a7      	str	r7, [r4, #8]

        /* Force the value of the CMSIS global variables holding the various system
          * clock frequencies to be updated. */
        SystemCoreClockUpdate();
     c40:	f000 f8b8 	bl	db4 <SystemCoreClockUpdate>
        {
            pclk_freq = g_FrequencyPCLK0;
        }
        else
        {
            pclk_freq = g_FrequencyPCLK1;
     c44:	f240 0118 	movw	r1, #24
     c48:	f2c2 0100 	movt	r1, #8192	; 0x2000
     c4c:	680a      	ldr	r2, [r1, #0]
        /*
         * Compute baud value based on requested baud rate and PCLK frequency.
         * The baud value is computed using the following equation:
         *      baud_value = PCLK_Frequency / (baud_rate * 16)
         */
        baud_value_by_128 = (8u * pclk_freq) / baudrate;
     c4e:	9e0d      	ldr	r6, [sp, #52]	; 0x34
     c50:	00d7      	lsls	r7, r2, #3
     c52:	fbb7 f2f6 	udiv	r2, r7, r6
        baud_value_by_64 = baud_value_by_128 / 2u;
        baud_value = baud_value_by_64 / 64u;
     c56:	09d3      	lsrs	r3, r2, #7
         * Compute baud value based on requested baud rate and PCLK frequency.
         * The baud value is computed using the following equation:
         *      baud_value = PCLK_Frequency / (baud_rate * 16)
         */
        baud_value_by_128 = (8u * pclk_freq) / baudrate;
        baud_value_by_64 = baud_value_by_128 / 2u;
     c58:	0857      	lsrs	r7, r2, #1
        fractional_baud_value += (baud_value_by_128 - (baud_value * 128u)) - (fractional_baud_value * 2u);
        
        /* Assert if integer baud value fits in 16-bit. */
        ASSERT(baud_value <= UINT16_MAX);
    
        if(baud_value <= (uint32_t)UINT16_MAX)
     c5a:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
     c5e:	bf28      	it	cs
     c60:	6821      	ldrcs	r1, [r4, #0]
     c62:	d2d5      	bcs.n	c10 <global_init+0x1b8>
        {
            if(baud_value > 1u)
     c64:	2b01      	cmp	r3, #1
            {
                /* 
                 * Use Frational baud rate divisors
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
     c66:	6821      	ldr	r1, [r4, #0]
        /* Assert if integer baud value fits in 16-bit. */
        ASSERT(baud_value <= UINT16_MAX);
    
        if(baud_value <= (uint32_t)UINT16_MAX)
        {
            if(baud_value > 1u)
     c68:	d950      	bls.n	d0c <global_init+0x2b4>
            {
                /* 
                 * Use Frational baud rate divisors
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
     c6a:	f101 000c 	add.w	r0, r1, #12
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     c6e:	f020 4c7f 	bic.w	ip, r0, #4278190080	; 0xff000000
     c72:	f000 4670 	and.w	r6, r0, #4026531840	; 0xf0000000
     c76:	f106 7000 	add.w	r0, r6, #33554432	; 0x2000000
     c7a:	f42c 0a70 	bic.w	sl, ip, #15728640	; 0xf00000
     c7e:	ea4f 1e4a 	mov.w	lr, sl, lsl #5
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8);
                /* lsb of baud value */
                this_uart->hw_reg->DLR = (uint8_t)baud_value;
     c82:	460d      	mov	r5, r1
     c84:	fa5f f883 	uxtb.w	r8, r3
         *      baud_value = PCLK_Frequency / (baud_rate * 16)
         */
        baud_value_by_128 = (8u * pclk_freq) / baudrate;
        baud_value_by_64 = baud_value_by_128 / 2u;
        baud_value = baud_value_by_64 / 64u;
        fractional_baud_value = baud_value_by_64 - (baud_value * 64u);
     c88:	eba7 1783 	sub.w	r7, r7, r3, lsl #6
     c8c:	301c      	adds	r0, #28
     c8e:	2601      	movs	r6, #1
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8);
     c90:	f3c2 3ac7 	ubfx	sl, r2, #15, #8
     c94:	f840 600e 	str.w	r6, [r0, lr]
         */
        baud_value_by_128 = (8u * pclk_freq) / baudrate;
        baud_value_by_64 = baud_value_by_128 / 2u;
        baud_value = baud_value_by_64 / 64u;
        fractional_baud_value = baud_value_by_64 - (baud_value * 64u);
        fractional_baud_value += (baud_value_by_128 - (baud_value * 128u)) - (fractional_baud_value * 2u);
     c98:	eba7 13c3 	sub.w	r3, r7, r3, lsl #7
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8);
     c9c:	f881 a004 	strb.w	sl, [r1, #4]
                /* lsb of baud value */
                this_uart->hw_reg->DLR = (uint8_t)baud_value;
     ca0:	f805 8b30 	strb.w	r8, [r5], #48
         */
        baud_value_by_128 = (8u * pclk_freq) / baudrate;
        baud_value_by_64 = baud_value_by_128 / 2u;
        baud_value = baud_value_by_64 / 64u;
        fractional_baud_value = baud_value_by_64 - (baud_value * 64u);
        fractional_baud_value += (baud_value_by_128 - (baud_value * 128u)) - (fractional_baud_value * 2u);
     ca4:	189a      	adds	r2, r3, r2
     ca6:	f025 437f 	bic.w	r3, r5, #4278190080	; 0xff000000
     caa:	f005 4570 	and.w	r5, r5, #4026531840	; 0xf0000000
     cae:	f423 0870 	bic.w	r8, r3, #15728640	; 0xf00000
                /* Enable Fractional baud rate */
                set_bit_reg8(&this_uart->hw_reg->MM0,EFBR);
        
                /* Load the fractional baud rate register */
                ASSERT(fractional_baud_value <= (uint32_t)UINT8_MAX);
                this_uart->hw_reg->DFR = (uint8_t)fractional_baud_value;
     cb2:	eba2 0747 	sub.w	r7, r2, r7, lsl #1
     cb6:	f105 7500 	add.w	r5, r5, #33554432	; 0x2000000
     cba:	351c      	adds	r5, #28
     cbc:	ea4f 1848 	mov.w	r8, r8, lsl #5
     cc0:	b2ff      	uxtb	r7, r7
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     cc2:	2300      	movs	r3, #0
     cc4:	f840 300e 	str.w	r3, [r0, lr]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     cc8:	f845 6008 	str.w	r6, [r5, r8]
     ccc:	f881 703c 	strb.w	r7, [r1, #60]	; 0x3c
     cd0:	e79e      	b.n	c10 <global_init+0x1b8>
    if(this_uart == &g_mss_uart0)
    {
        this_uart->hw_reg = UART0;
        this_uart->irqn = UART0_IRQn;
        /* reset UART0 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART0_SOFTRESET_MASK;
     cd2:	f040 0780 	orr.w	r7, r0, #128	; 0x80
     cd6:	f2ce 0100 	movt	r1, #57344	; 0xe000
     cda:	f44f 6680 	mov.w	r6, #1024	; 0x400
     cde:	6497      	str	r7, [r2, #72]	; 0x48
     ce0:	f8c1 6180 	str.w	r6, [r1, #384]	; 0x180
        /* Clear any previously pended UART0 interrupt */
        NVIC_ClearPendingIRQ(UART0_IRQn);
        /* Take UART0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
     ce4:	6c95      	ldr	r5, [r2, #72]	; 0x48
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
    {
        this_uart->hw_reg = UART0;
     ce6:	f04f 4180 	mov.w	r1, #1073741824	; 0x40000000
        /* reset UART0 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART0_SOFTRESET_MASK;
        /* Clear any previously pended UART0 interrupt */
        NVIC_ClearPendingIRQ(UART0_IRQn);
        /* Take UART0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
     cea:	f025 0080 	bic.w	r0, r5, #128	; 0x80
     cee:	6490      	str	r0, [r2, #72]	; 0x48
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
    {
        this_uart->hw_reg = UART0;
        this_uart->irqn = UART0_IRQn;
     cf0:	220a      	movs	r2, #10
     cf2:	7122      	strb	r2, [r4, #4]
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
    {
        this_uart->hw_reg = UART0;
     cf4:	6021      	str	r1, [r4, #0]
     cf6:	e6d7      	b.n	aa8 <global_init+0x50>
        uint32_t baud_value_by_64;
        uint32_t baud_value_by_128;
        uint32_t fractional_baud_value;
        uint32_t pclk_freq;

        this_uart->baudrate = baudrate;
     cf8:	9a0d      	ldr	r2, [sp, #52]	; 0x34
     cfa:	60a2      	str	r2, [r4, #8]

        /* Force the value of the CMSIS global variables holding the various system
          * clock frequencies to be updated. */
        SystemCoreClockUpdate();
     cfc:	f000 f85a 	bl	db4 <SystemCoreClockUpdate>
        if(this_uart == &g_mss_uart0)
        {
            pclk_freq = g_FrequencyPCLK0;
     d00:	f240 0114 	movw	r1, #20
     d04:	f2c2 0100 	movt	r1, #8192	; 0x2000
     d08:	680a      	ldr	r2, [r1, #0]
     d0a:	e7a0      	b.n	c4e <global_init+0x1f6>
            {
                /*
                 * Do NOT use Frational baud rate divisors.
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
     d0c:	f101 0c0c 	add.w	ip, r1, #12
     d10:	f02c 4e7f 	bic.w	lr, ip, #4278190080	; 0xff000000
     d14:	f00c 4270 	and.w	r2, ip, #4026531840	; 0xf0000000
     d18:	f42e 0570 	bic.w	r5, lr, #15728640	; 0xf00000
     d1c:	f102 7200 	add.w	r2, r2, #33554432	; 0x2000000
     d20:	ea4f 1e45 	mov.w	lr, r5, lsl #5
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8u);
                /* lsb of baud value */
                this_uart->hw_reg->DLR = (uint8_t)baud_value;
     d24:	4608      	mov	r0, r1
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8u);
     d26:	2500      	movs	r5, #0
                /* lsb of baud value */
                this_uart->hw_reg->DLR = (uint8_t)baud_value;
     d28:	b2db      	uxtb	r3, r3
     d2a:	321c      	adds	r2, #28
     d2c:	2601      	movs	r6, #1
     d2e:	f842 600e 	str.w	r6, [r2, lr]
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8u);
     d32:	710d      	strb	r5, [r1, #4]
                /* lsb of baud value */
                this_uart->hw_reg->DLR = (uint8_t)baud_value;
     d34:	f800 3b30 	strb.w	r3, [r0], #48
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     d38:	f020 4c7f 	bic.w	ip, r0, #4278190080	; 0xff000000
     d3c:	f000 4070 	and.w	r0, r0, #4026531840	; 0xf0000000
     d40:	f100 7600 	add.w	r6, r0, #33554432	; 0x2000000
     d44:	f42c 0370 	bic.w	r3, ip, #15728640	; 0xf00000
     d48:	361c      	adds	r6, #28
     d4a:	015b      	lsls	r3, r3, #5
     d4c:	f842 500e 	str.w	r5, [r2, lr]
     d50:	50f5      	str	r5, [r6, r3]
     d52:	e75d      	b.n	c10 <global_init+0x1b8>

00000d54 <MSS_UART_init>:
(
    mss_uart_instance_t* this_uart, 
    uint32_t baud_rate,
    uint8_t line_config
)
{
     d54:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
     d56:	4604      	mov	r4, r0
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    /* Perform generic initialization */
    global_init(this_uart, baud_rate, line_config);
     d58:	f7ff fe7e 	bl	a58 <global_init>

    /* Disable LIN mode */
    clear_bit_reg8(&this_uart->hw_reg->MM0, ELIN);
     d5c:	6822      	ldr	r2, [r4, #0]
     d5e:	f64f 73ff 	movw	r3, #65535	; 0xffff

    /* Disable IrDA mode */
    clear_bit_reg8(&this_uart->hw_reg->MM1, EIRD);
     d62:	f102 0034 	add.w	r0, r2, #52	; 0x34

    /* Perform generic initialization */
    global_init(this_uart, baud_rate, line_config);

    /* Disable LIN mode */
    clear_bit_reg8(&this_uart->hw_reg->MM0, ELIN);
     d66:	f102 0530 	add.w	r5, r2, #48	; 0x30
     d6a:	f2c0 030f 	movt	r3, #15
     d6e:	f005 4770 	and.w	r7, r5, #4026531840	; 0xf0000000

    /* Disable IrDA mode */
    clear_bit_reg8(&this_uart->hw_reg->MM1, EIRD);

    /* Disable SmartCard Mode */
    clear_bit_reg8(&this_uart->hw_reg->MM2, EERR);
     d72:	3238      	adds	r2, #56	; 0x38
     d74:	f000 4170 	and.w	r1, r0, #4026531840	; 0xf0000000

    /* set default tx handler for automated TX using interrupt in USART mode */
    this_uart->tx_handler = default_tx_handler;
     d78:	ea02 0603 	and.w	r6, r2, r3
     d7c:	f107 7c00 	add.w	ip, r7, #33554432	; 0x2000000
     d80:	401d      	ands	r5, r3
     d82:	ea00 0703 	and.w	r7, r0, r3
     d86:	f002 4270 	and.w	r2, r2, #4026531840	; 0xf0000000
     d8a:	f101 7100 	add.w	r1, r1, #33554432	; 0x2000000
     d8e:	f640 1099 	movw	r0, #2457	; 0x999
     d92:	017b      	lsls	r3, r7, #5
     d94:	f10c 0c0c 	add.w	ip, ip, #12
     d98:	f102 7700 	add.w	r7, r2, #33554432	; 0x2000000
     d9c:	016d      	lsls	r5, r5, #5
     d9e:	2200      	movs	r2, #0
     da0:	3108      	adds	r1, #8
     da2:	0176      	lsls	r6, r6, #5
     da4:	f2c0 0000 	movt	r0, #0
     da8:	f84c 2005 	str.w	r2, [ip, r5]
     dac:	6260      	str	r0, [r4, #36]	; 0x24
     dae:	50ca      	str	r2, [r1, r3]
     db0:	51ba      	str	r2, [r7, r6]
}
     db2:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

00000db4 <SystemCoreClockUpdate>:
#define FREQ_1MHZ    1000000u
#define FREQ_25MHZ   25000000u
#define FREQ_50MHZ   50000000u

void SystemCoreClockUpdate(void)
{
     db4:	e92d 01f0 	stmdb	sp!, {r4, r5, r6, r7, r8}
    uint32_t controller_pll_init;
    uint32_t clk_src;

    controller_pll_init = SYSREG->MSSDDR_FACC1_CR & CONTROLLER_PLL_INIT_MASK;
     db8:	f248 0300 	movw	r3, #32768	; 0x8000
     dbc:	f2c4 0303 	movt	r3, #16387	; 0x4003
     dc0:	f8d3 2098 	ldr.w	r2, [r3, #152]	; 0x98
#define FREQ_1MHZ    1000000u
#define FREQ_25MHZ   25000000u
#define FREQ_50MHZ   50000000u

void SystemCoreClockUpdate(void)
{
     dc4:	b083      	sub	sp, #12
    uint32_t controller_pll_init;
    uint32_t clk_src;

    controller_pll_init = SYSREG->MSSDDR_FACC1_CR & CONTROLLER_PLL_INIT_MASK;
    
    if(0u == controller_pll_init)
     dc6:	f012 6f80 	tst.w	r2, #67108864	; 0x4000000
     dca:	d118      	bne.n	dfe <SystemCoreClockUpdate+0x4a>
    {
        /* Normal operations. */
        uint32_t global_mux_sel;
        
        global_mux_sel = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK;
     dcc:	f8d3 0098 	ldr.w	r0, [r3, #152]	; 0x98
        if(0u == global_mux_sel)
     dd0:	f410 5f80 	tst.w	r0, #4096	; 0x1000
     dd4:	d04d      	beq.n	e72 <SystemCoreClockUpdate+0xbe>
                                                   RCOSC_25_50MHZ_CLK_SRC,
                                                   CLK_XTAL_CLK_SRC,
                                                   RCOSC_1_MHZ_CLK_SRC,
                                                   RCOSC_1_MHZ_CLK_SRC,
                                                   CCC2ASCI_CLK_SRC,
                                                   CCC2ASCI_CLK_SRC };
     dd6:	f241 2158 	movw	r1, #4696	; 0x1258
     dda:	f2c0 0100 	movt	r1, #0
     dde:	46ec      	mov	ip, sp
     de0:	c903      	ldmia	r1!, {r0, r1}
     de2:	e88c 0003 	stmia.w	ip, {r0, r1}
            
            uint32_t standby_sel;
            uint8_t clock_source;
            
            standby_sel = (SYSREG->MSSDDR_FACC2_CR >> FACC_STANDBY_SHIFT) & FACC_STANDBY_SEL_MASK;
     de6:	f8d3 209c 	ldr.w	r2, [r3, #156]	; 0x9c
            clock_source = standby_clock_lut[standby_sel];
            switch(clock_source)
     dea:	af02      	add	r7, sp, #8
     dec:	f3c2 1682 	ubfx	r6, r2, #6, #3
     df0:	19bd      	adds	r5, r7, r6
     df2:	f815 4c08 	ldrb.w	r4, [r5, #-8]
     df6:	2c01      	cmp	r4, #1
     df8:	f000 8081 	beq.w	efe <SystemCoreClockUpdate+0x14a>
     dfc:	d26a      	bcs.n	ed4 <SystemCoreClockUpdate+0x120>
static uint32_t get_rcosc_25_50mhz_frequency(void)
{
    uint32_t rcosc_div2;
    uint32_t rcosc_frequency;
    
    rcosc_div2 = SYSREG->MSSDDR_PLL_STATUS & RCOSC_DIV2_MASK;
     dfe:	f8d3 0150 	ldr.w	r0, [r3, #336]	; 0x150
    if(0u == rcosc_div2)
     e02:	f647 0840 	movw	r8, #30784	; 0x7840
     e06:	f24f 0380 	movw	r3, #61568	; 0xf080
     e0a:	f010 0f04 	tst.w	r0, #4
     e0e:	f2c0 187d 	movt	r8, #381	; 0x17d
     e12:	f2c0 23fa 	movt	r3, #762	; 0x2fa
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     e16:	f240 051c 	movw	r5, #28
    g_FrequencyPCLK0 = standby_clk;
     e1a:	f240 0414 	movw	r4, #20
    g_FrequencyPCLK1 = standby_clk;
     e1e:	f240 0018 	movw	r0, #24
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     e22:	f240 0708 	movw	r7, #8
     e26:	f646 6c70 	movw	ip, #28272	; 0x6e70
    g_FrequencyFIC0 = standby_clk;
     e2a:	f240 010c 	movw	r1, #12
    g_FrequencyFIC1 = standby_clk;
     e2e:	f240 0210 	movw	r2, #16
    g_FrequencyFIC64 = standby_clk;
     e32:	f240 0604 	movw	r6, #4
{
    uint32_t rcosc_div2;
    uint32_t rcosc_frequency;
    
    rcosc_div2 = SYSREG->MSSDDR_PLL_STATUS & RCOSC_DIV2_MASK;
    if(0u == rcosc_div2)
     e36:	bf08      	it	eq
     e38:	4643      	moveq	r3, r8
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     e3a:	f2c2 0500 	movt	r5, #8192	; 0x2000
    g_FrequencyPCLK0 = standby_clk;
     e3e:	f2c2 0400 	movt	r4, #8192	; 0x2000
    g_FrequencyPCLK1 = standby_clk;
     e42:	f2c2 0000 	movt	r0, #8192	; 0x2000
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     e46:	f2c2 0700 	movt	r7, #8192	; 0x2000
     e4a:	f2c0 1ca7 	movt	ip, #423	; 0x1a7
    g_FrequencyFIC0 = standby_clk;
     e4e:	f2c2 0100 	movt	r1, #8192	; 0x2000
    g_FrequencyFIC1 = standby_clk;
     e52:	f2c2 0200 	movt	r2, #8192	; 0x2000
    g_FrequencyFIC64 = standby_clk;
     e56:	f2c2 0600 	movt	r6, #8192	; 0x2000
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
    g_FrequencyPCLK0 = standby_clk;
    g_FrequencyPCLK1 = standby_clk;
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     e5a:	f8c7 c000 	str.w	ip, [r7]
    g_FrequencyFIC0 = standby_clk;
    g_FrequencyFIC1 = standby_clk;
    g_FrequencyFIC64 = standby_clk;
     e5e:	6033      	str	r3, [r6, #0]
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     e60:	602b      	str	r3, [r5, #0]
    g_FrequencyPCLK0 = standby_clk;
     e62:	6023      	str	r3, [r4, #0]
    g_FrequencyPCLK1 = standby_clk;
     e64:	6003      	str	r3, [r0, #0]
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
    g_FrequencyFIC0 = standby_clk;
     e66:	600b      	str	r3, [r1, #0]
    g_FrequencyFIC1 = standby_clk;
     e68:	6013      	str	r3, [r2, #0]
    {
        /* PLL initialization mode. Running from 25/50MHZ RC oscillator. */
        clk_src = get_rcosc_25_50mhz_frequency();
        set_clock_frequency_globals(clk_src);
    }
}
     e6a:	b003      	add	sp, #12
     e6c:	e8bd 01f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8}
     e70:	4770      	bx	lr
        
        global_mux_sel = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK;
        if(0u == global_mux_sel)
        {
            /* MSS clocked from MSS PLL. Use Libero flow defines. */
            SystemCoreClock = MSS_SYS_M3_CLK_FREQ;
     e72:	f240 041c 	movw	r4, #28
     e76:	f64b 13c0 	movw	r3, #47552	; 0xb9c0
            g_FrequencyPCLK0 = MSS_SYS_APB_0_CLK_FREQ;
     e7a:	f240 0014 	movw	r0, #20
            g_FrequencyPCLK1 = MSS_SYS_APB_1_CLK_FREQ;
     e7e:	f240 0118 	movw	r1, #24
            g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     e82:	f240 0c08 	movw	ip, #8
     e86:	f646 6870 	movw	r8, #28272	; 0x6e70
            g_FrequencyFIC0 = MSS_SYS_FIC_0_CLK_FREQ;
     e8a:	f240 020c 	movw	r2, #12
            g_FrequencyFIC1 = MSS_SYS_FIC_1_CLK_FREQ;
     e8e:	f240 0710 	movw	r7, #16
            g_FrequencyFIC64 = MSS_SYS_FIC64_CLK_FREQ;
     e92:	f240 0504 	movw	r5, #4
     e96:	f642 5640 	movw	r6, #11584	; 0x2d40
        
        global_mux_sel = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK;
        if(0u == global_mux_sel)
        {
            /* MSS clocked from MSS PLL. Use Libero flow defines. */
            SystemCoreClock = MSS_SYS_M3_CLK_FREQ;
     e9a:	f2c0 639d 	movt	r3, #1693	; 0x69d
     e9e:	f2c2 0400 	movt	r4, #8192	; 0x2000
            g_FrequencyPCLK0 = MSS_SYS_APB_0_CLK_FREQ;
     ea2:	f2c2 0000 	movt	r0, #8192	; 0x2000
            g_FrequencyPCLK1 = MSS_SYS_APB_1_CLK_FREQ;
     ea6:	f2c2 0100 	movt	r1, #8192	; 0x2000
            g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     eaa:	f2c2 0c00 	movt	ip, #8192	; 0x2000
     eae:	f2c0 18a7 	movt	r8, #423	; 0x1a7
            g_FrequencyFIC0 = MSS_SYS_FIC_0_CLK_FREQ;
     eb2:	f2c2 0200 	movt	r2, #8192	; 0x2000
            g_FrequencyFIC1 = MSS_SYS_FIC_1_CLK_FREQ;
     eb6:	f2c2 0700 	movt	r7, #8192	; 0x2000
            g_FrequencyFIC64 = MSS_SYS_FIC64_CLK_FREQ;
     eba:	f2c2 0500 	movt	r5, #8192	; 0x2000
     ebe:	f2c1 36d9 	movt	r6, #5081	; 0x13d9
        {
            /* MSS clocked from MSS PLL. Use Libero flow defines. */
            SystemCoreClock = MSS_SYS_M3_CLK_FREQ;
            g_FrequencyPCLK0 = MSS_SYS_APB_0_CLK_FREQ;
            g_FrequencyPCLK1 = MSS_SYS_APB_1_CLK_FREQ;
            g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     ec2:	f8cc 8000 	str.w	r8, [ip]
            g_FrequencyFIC0 = MSS_SYS_FIC_0_CLK_FREQ;
            g_FrequencyFIC1 = MSS_SYS_FIC_1_CLK_FREQ;
     ec6:	603b      	str	r3, [r7, #0]
            g_FrequencyFIC64 = MSS_SYS_FIC64_CLK_FREQ;
     ec8:	602e      	str	r6, [r5, #0]
        
        global_mux_sel = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK;
        if(0u == global_mux_sel)
        {
            /* MSS clocked from MSS PLL. Use Libero flow defines. */
            SystemCoreClock = MSS_SYS_M3_CLK_FREQ;
     eca:	6023      	str	r3, [r4, #0]
            g_FrequencyPCLK0 = MSS_SYS_APB_0_CLK_FREQ;
     ecc:	6003      	str	r3, [r0, #0]
            g_FrequencyPCLK1 = MSS_SYS_APB_1_CLK_FREQ;
     ece:	600b      	str	r3, [r1, #0]
            g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
            g_FrequencyFIC0 = MSS_SYS_FIC_0_CLK_FREQ;
     ed0:	6013      	str	r3, [r2, #0]
     ed2:	e7ca      	b.n	e6a <SystemCoreClockUpdate+0xb6>
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     ed4:	f244 2340 	movw	r3, #16960	; 0x4240
     ed8:	f240 051c 	movw	r5, #28
    g_FrequencyPCLK0 = standby_clk;
     edc:	f240 0414 	movw	r4, #20
    g_FrequencyPCLK1 = standby_clk;
     ee0:	f240 0018 	movw	r0, #24
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     ee4:	f240 0708 	movw	r7, #8
     ee8:	f646 6c70 	movw	ip, #28272	; 0x6e70
    g_FrequencyFIC0 = standby_clk;
     eec:	f240 010c 	movw	r1, #12
    g_FrequencyFIC1 = standby_clk;
     ef0:	f240 0210 	movw	r2, #16
    g_FrequencyFIC64 = standby_clk;
     ef4:	f240 0604 	movw	r6, #4
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     ef8:	f2c0 030f 	movt	r3, #15
     efc:	e79d      	b.n	e3a <SystemCoreClockUpdate+0x86>
    g_FrequencyPCLK0 = standby_clk;
     efe:	f240 051c 	movw	r5, #28
     f02:	f240 0414 	movw	r4, #20
    g_FrequencyPCLK1 = standby_clk;
     f06:	f240 0018 	movw	r0, #24
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     f0a:	f240 0708 	movw	r7, #8
     f0e:	f646 6c70 	movw	ip, #28272	; 0x6e70
    g_FrequencyFIC0 = standby_clk;
     f12:	f240 010c 	movw	r1, #12
    g_FrequencyFIC1 = standby_clk;
     f16:	f240 0210 	movw	r2, #16
    g_FrequencyFIC64 = standby_clk;
     f1a:	f240 0604 	movw	r6, #4
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     f1e:	f2c2 0500 	movt	r5, #8192	; 0x2000
    g_FrequencyPCLK0 = standby_clk;
     f22:	f2c2 0400 	movt	r4, #8192	; 0x2000
    g_FrequencyPCLK1 = standby_clk;
     f26:	f2c2 0000 	movt	r0, #8192	; 0x2000
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     f2a:	f2c2 0700 	movt	r7, #8192	; 0x2000
     f2e:	f2c0 1ca7 	movt	ip, #423	; 0x1a7
    g_FrequencyFIC0 = standby_clk;
     f32:	f2c2 0100 	movt	r1, #8192	; 0x2000
    g_FrequencyFIC1 = standby_clk;
     f36:	f2c2 0200 	movt	r2, #8192	; 0x2000
    g_FrequencyFIC64 = standby_clk;
     f3a:	f2c2 0600 	movt	r6, #8192	; 0x2000
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     f3e:	f44f 4300 	mov.w	r3, #32768	; 0x8000
     f42:	e78a      	b.n	e5a <SystemCoreClockUpdate+0xa6>

00000f44 <SystemInit>:
static uint32_t get_silicon_revision(void)
{
    uint32_t silicon_revision;
    uint32_t device_version;
    
    device_version = SYSREG->DEVICE_VERSION;
     f44:	f248 0300 	movw	r3, #32768	; 0x8000
     f48:	f2c4 0303 	movt	r3, #16387	; 0x4003
     f4c:	f8d3 114c 	ldr.w	r1, [r3, #332]	; 0x14c
    switch(device_version)
     f50:	f64f 0202 	movw	r2, #63490	; 0xf802
     f54:	4291      	cmp	r1, r2

/***************************************************************************//**
 * See system_m2sxxx.h for details.
 */
void SystemInit(void)
{
     f56:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
{
    uint32_t silicon_revision;
    uint32_t device_version;
    
    device_version = SYSREG->DEVICE_VERSION;
    switch(device_version)
     f5a:	d10b      	bne.n	f74 <SystemInit+0x30>
{
    /*--------------------------------------------------------------------------
     * Work around a couple of silicon issues:
     */
    /* DDR_CLK_EN <- 1 */
    SYSREG->MSSDDR_FACC1_CR |= (uint32_t)1 << DDR_CLK_EN_SHIFT;
     f5c:	f8d3 0098 	ldr.w	r0, [r3, #152]	; 0x98
     f60:	f440 7280 	orr.w	r2, r0, #256	; 0x100
     f64:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98
    
    /* CONTROLLER_PLL_INIT <- 0 */
    SYSREG->MSSDDR_FACC1_CR = SYSREG->MSSDDR_FACC1_CR & ~CONTROLLER_PLL_INIT_MASK;
     f68:	f8d3 1098 	ldr.w	r1, [r3, #152]	; 0x98
     f6c:	f021 6080 	bic.w	r0, r1, #67108864	; 0x4000000
     f70:	f8c3 0098 	str.w	r0, [r3, #152]	; 0x98
    /*--------------------------------------------------------------------------
     * Set STKALIGN to ensure exception stacking starts on 8 bytes address
     * boundary. This ensures compliance with the "Procedure Call Standards for
     * the ARM Architecture" (AAPCS).
     */
    SCB->CCR |= SCB_CCR_STKALIGN_Msk;
     f74:	f64e 5300 	movw	r3, #60672	; 0xed00
     f78:	f2ce 0300 	movt	r3, #57344	; 0xe000
     f7c:	6958      	ldr	r0, [r3, #20]
    
    /*--------------------------------------------------------------------------
     * MDDR configuration
     */
#if MSS_SYS_MDDR_CONFIG_BY_CORTEX
    if(0u == SYSREG->DDR_CR)
     f7e:	f248 0200 	movw	r2, #32768	; 0x8000
    /*--------------------------------------------------------------------------
     * Set STKALIGN to ensure exception stacking starts on 8 bytes address
     * boundary. This ensures compliance with the "Procedure Call Standards for
     * the ARM Architecture" (AAPCS).
     */
    SCB->CCR |= SCB_CCR_STKALIGN_Msk;
     f82:	f440 7100 	orr.w	r1, r0, #512	; 0x200
     f86:	6159      	str	r1, [r3, #20]
    
    /*--------------------------------------------------------------------------
     * MDDR configuration
     */
#if MSS_SYS_MDDR_CONFIG_BY_CORTEX
    if(0u == SYSREG->DDR_CR)
     f88:	f2c4 0203 	movt	r2, #16387	; 0x4003
     f8c:	6893      	ldr	r3, [r2, #8]
     f8e:	2b00      	cmp	r3, #0
     f90:	d164      	bne.n	105c <PROCESS_STACK_SIZE+0x5c>
         * to address 0x00000000. If MDDR is remapped to 0x00000000 then we are
         * probably executing this code from MDDR in a debugging session and
         * attempting to reconfigure the MDDR memory controller will cause the
         * Cortex-M3 to crash.
         */
        config_ddr_subsys(&g_m2s_mddr_subsys_config, &g_m2s_mddr_addr->core);
     f92:	f241 346c 	movw	r4, #4972	; 0x136c
     f96:	f2c0 0400 	movt	r4, #0
     f9a:	6826      	ldr	r6, [r4, #0]
     f9c:	f241 2460 	movw	r4, #4704	; 0x1260
     fa0:	f2c0 0400 	movt	r4, #0
    
    /*--------------------------------------------------------------------------
     * Configure DDR controller part of the MDDR subsystem.
     */
    p_cfg = &p_ddr_subsys_cfg->ddrc.DYN_SOFT_RESET_CR;
    p_regs = &p_ddr_subsys_regs->ddrc.DYN_SOFT_RESET_CR;
     fa4:	4632      	mov	r2, r6
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
    {
        p_regs[inc] = p_cfg[inc];
     fa6:	1c98      	adds	r0, r3, #2
     fa8:	1c81      	adds	r1, r0, #2
     faa:	5b1f      	ldrh	r7, [r3, r4]
     fac:	5b00      	ldrh	r0, [r0, r4]
     fae:	5b0d      	ldrh	r5, [r1, r4]
     fb0:	3306      	adds	r3, #6
     fb2:	4611      	mov	r1, r2
     fb4:	f841 7b04 	str.w	r7, [r1], #4
     fb8:	6050      	str	r0, [r2, #4]
     fba:	320c      	adds	r2, #12
    uint32_t nb_16bit_words
)
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
     fbc:	2b72      	cmp	r3, #114	; 0x72
    {
        p_regs[inc] = p_cfg[inc];
     fbe:	604d      	str	r5, [r1, #4]
    uint32_t nb_16bit_words
)
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
     fc0:	d1f1      	bne.n	fa6 <SystemInit+0x62>
    
    /*--------------------------------------------------------------------------
     * Configure DDR PHY.
     */
    p_cfg = &p_ddr_subsys_cfg->phy.LOOPBACK_TEST_CR;
    p_regs = &p_ddr_subsys_regs->phy.LOOPBACK_TEST_CR;
     fc2:	f241 2260 	movw	r2, #4704	; 0x1260
     fc6:	f2c0 0200 	movt	r2, #0
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
    {
        p_regs[inc] = p_cfg[inc];
     fca:	f8b2 5072 	ldrh.w	r5, [r2, #114]	; 0x72
    
    /*--------------------------------------------------------------------------
     * Configure DDR PHY.
     */
    p_cfg = &p_ddr_subsys_cfg->phy.LOOPBACK_TEST_CR;
    p_regs = &p_ddr_subsys_regs->phy.LOOPBACK_TEST_CR;
     fce:	f506 7307 	add.w	r3, r6, #540	; 0x21c
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
    {
        p_regs[inc] = p_cfg[inc];
     fd2:	601d      	str	r5, [r3, #0]
static void set_clock_frequency_globals(uint32_t fclk);

/***************************************************************************//**
 * See system_m2sxxx.h for details.
 */
void SystemInit(void)
     fd4:	f102 0c82 	add.w	ip, r2, #130	; 0x82
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
    {
        p_regs[inc] = p_cfg[inc];
     fd8:	1c93      	adds	r3, r2, #2
     fda:	f506 7108 	add.w	r1, r6, #544	; 0x220
     fde:	1c98      	adds	r0, r3, #2
     fe0:	f8b3 5072 	ldrh.w	r5, [r3, #114]	; 0x72
     fe4:	460f      	mov	r7, r1
     fe6:	f8b0 2072 	ldrh.w	r2, [r0, #114]	; 0x72
     fea:	f847 5b04 	str.w	r5, [r7], #4
     fee:	1c83      	adds	r3, r0, #2
     ff0:	604a      	str	r2, [r1, #4]
     ff2:	1d39      	adds	r1, r7, #4
    uint32_t nb_16bit_words
)
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
     ff4:	4563      	cmp	r3, ip
     ff6:	d1f2      	bne.n	fde <SystemInit+0x9a>
    p_ddr_subsys_regs->fic.HPD_SW_RW_EN_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_EN_CR;
    p_ddr_subsys_regs->fic.HPD_SW_RW_INVAL_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_INVAL_CR;
    p_ddr_subsys_regs->fic.SW_WR_ERCLR_CR = p_ddr_subsys_cfg->fic.SW_WR_ERCLR_CR;
    p_ddr_subsys_regs->fic.ERR_INT_ENABLE_CR = p_ddr_subsys_cfg->fic.ERR_INT_ENABLE_CR;
    p_ddr_subsys_regs->fic.NUM_AHB_MASTERS_CR = p_ddr_subsys_cfg->fic.NUM_AHB_MASTERS_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[0] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_1_CR;
     ff8:	f8b4 1104 	ldrh.w	r1, [r4, #260]	; 0x104
    copy_cfg16_to_regs(p_regs, p_cfg, NB_OF_DDR_PHY_REGS_TO_CONFIG);
    
    /*--------------------------------------------------------------------------
     * Configure DDR FIC.
     */
    p_ddr_subsys_regs->fic.NB_ADDR_CR = p_ddr_subsys_cfg->fic.NB_ADDR_CR;
     ffc:	f8b4 90f4 	ldrh.w	r9, [r4, #244]	; 0xf4
    p_ddr_subsys_regs->fic.NBRWB_SIZE_CR = p_ddr_subsys_cfg->fic.NBRWB_SIZE_CR;
    1000:	f8b4 a0f6 	ldrh.w	sl, [r4, #246]	; 0xf6
    p_ddr_subsys_regs->fic.WB_TIMEOUT_CR = p_ddr_subsys_cfg->fic.WB_TIMEOUT_CR;
    1004:	f8b4 80f8 	ldrh.w	r8, [r4, #248]	; 0xf8
    p_ddr_subsys_regs->fic.HPD_SW_RW_EN_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_EN_CR;
    1008:	f8b4 e0fa 	ldrh.w	lr, [r4, #250]	; 0xfa
    p_ddr_subsys_regs->fic.HPD_SW_RW_INVAL_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_INVAL_CR;
    100c:	f8b4 c0fc 	ldrh.w	ip, [r4, #252]	; 0xfc
    p_ddr_subsys_regs->fic.SW_WR_ERCLR_CR = p_ddr_subsys_cfg->fic.SW_WR_ERCLR_CR;
    1010:	f8b4 70fe 	ldrh.w	r7, [r4, #254]	; 0xfe
    p_ddr_subsys_regs->fic.ERR_INT_ENABLE_CR = p_ddr_subsys_cfg->fic.ERR_INT_ENABLE_CR;
    1014:	f8b4 5100 	ldrh.w	r5, [r4, #256]	; 0x100
    p_ddr_subsys_regs->fic.NUM_AHB_MASTERS_CR = p_ddr_subsys_cfg->fic.NUM_AHB_MASTERS_CR;
    1018:	f8b4 0102 	ldrh.w	r0, [r4, #258]	; 0x102
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[0] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_1_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[1] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_2_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUT_EN_CR = p_ddr_subsys_cfg->fic.LOCK_TIMEOUT_EN_CR;
    101c:	f8b4 3108 	ldrh.w	r3, [r4, #264]	; 0x108
    p_ddr_subsys_regs->fic.HPD_SW_RW_INVAL_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_INVAL_CR;
    p_ddr_subsys_regs->fic.SW_WR_ERCLR_CR = p_ddr_subsys_cfg->fic.SW_WR_ERCLR_CR;
    p_ddr_subsys_regs->fic.ERR_INT_ENABLE_CR = p_ddr_subsys_cfg->fic.ERR_INT_ENABLE_CR;
    p_ddr_subsys_regs->fic.NUM_AHB_MASTERS_CR = p_ddr_subsys_cfg->fic.NUM_AHB_MASTERS_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[0] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_1_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[1] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_2_CR;
    1020:	f8b4 2106 	ldrh.w	r2, [r4, #262]	; 0x106
    copy_cfg16_to_regs(p_regs, p_cfg, NB_OF_DDR_PHY_REGS_TO_CONFIG);
    
    /*--------------------------------------------------------------------------
     * Configure DDR FIC.
     */
    p_ddr_subsys_regs->fic.NB_ADDR_CR = p_ddr_subsys_cfg->fic.NB_ADDR_CR;
    1024:	f8c6 9400 	str.w	r9, [r6, #1024]	; 0x400
    p_ddr_subsys_regs->fic.NBRWB_SIZE_CR = p_ddr_subsys_cfg->fic.NBRWB_SIZE_CR;
    1028:	f8c6 a404 	str.w	sl, [r6, #1028]	; 0x404
    p_ddr_subsys_regs->fic.WB_TIMEOUT_CR = p_ddr_subsys_cfg->fic.WB_TIMEOUT_CR;
    102c:	f8c6 8408 	str.w	r8, [r6, #1032]	; 0x408
    p_ddr_subsys_regs->fic.HPD_SW_RW_EN_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_EN_CR;
    1030:	f8c6 e40c 	str.w	lr, [r6, #1036]	; 0x40c
    p_ddr_subsys_regs->fic.HPD_SW_RW_INVAL_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_INVAL_CR;
    1034:	f8c6 c410 	str.w	ip, [r6, #1040]	; 0x410
    p_ddr_subsys_regs->fic.SW_WR_ERCLR_CR = p_ddr_subsys_cfg->fic.SW_WR_ERCLR_CR;
    1038:	f8c6 7414 	str.w	r7, [r6, #1044]	; 0x414
    p_ddr_subsys_regs->fic.ERR_INT_ENABLE_CR = p_ddr_subsys_cfg->fic.ERR_INT_ENABLE_CR;
    103c:	f8c6 5418 	str.w	r5, [r6, #1048]	; 0x418
    p_ddr_subsys_regs->fic.NUM_AHB_MASTERS_CR = p_ddr_subsys_cfg->fic.NUM_AHB_MASTERS_CR;
    1040:	f8c6 041c 	str.w	r0, [r6, #1052]	; 0x41c
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[0] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_1_CR;
    1044:	f8c6 1440 	str.w	r1, [r6, #1088]	; 0x440
    p_ddr_subsys_regs->fic.LOCK_TIMEOUT_EN_CR = p_ddr_subsys_cfg->fic.LOCK_TIMEOUT_EN_CR;

    /*--------------------------------------------------------------------------
     * Enable DDR.
     */
    p_ddr_subsys_regs->ddrc.DYN_SOFT_RESET_CR = 0x01u;
    1048:	2101      	movs	r1, #1
    p_ddr_subsys_regs->fic.HPD_SW_RW_INVAL_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_INVAL_CR;
    p_ddr_subsys_regs->fic.SW_WR_ERCLR_CR = p_ddr_subsys_cfg->fic.SW_WR_ERCLR_CR;
    p_ddr_subsys_regs->fic.ERR_INT_ENABLE_CR = p_ddr_subsys_cfg->fic.ERR_INT_ENABLE_CR;
    p_ddr_subsys_regs->fic.NUM_AHB_MASTERS_CR = p_ddr_subsys_cfg->fic.NUM_AHB_MASTERS_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[0] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_1_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[1] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_2_CR;
    104a:	f8c6 2444 	str.w	r2, [r6, #1092]	; 0x444
    p_ddr_subsys_regs->fic.LOCK_TIMEOUT_EN_CR = p_ddr_subsys_cfg->fic.LOCK_TIMEOUT_EN_CR;
    104e:	f8c6 3448 	str.w	r3, [r6, #1096]	; 0x448

    /*--------------------------------------------------------------------------
     * Enable DDR.
     */
    p_ddr_subsys_regs->ddrc.DYN_SOFT_RESET_CR = 0x01u;
    1052:	6031      	str	r1, [r6, #0]
    
    while(0x0000u == p_ddr_subsys_regs->ddrc.DDRC_SR)
    1054:	f8d6 30e4 	ldr.w	r3, [r6, #228]	; 0xe4
    1058:	2b00      	cmp	r3, #0
    105a:	d0fb      	beq.n	1054 <PROCESS_STACK_SIZE+0x54>
#endif

    /*--------------------------------------------------------------------------
     * Call user defined configuration function.
     */
    mscc_post_hw_cfg_init();
    105c:	f7ff f998 	bl	390 <mscc_post_hw_cfg_init>
     * do this here because this signal is only deasserted by the System
     * Controller on a power-on reset. Other types of reset such as a watchdog
     * reset would result in the FPGA fabric being held in reset and getting
     * stuck waiting for the CoreSF2Config INIT_DONE to become asserted.
     */
    SYSREG->SOFT_RST_CR &= ~SYSREG_FPGA_SOFTRESET_MASK;
    1060:	f248 0200 	movw	r2, #32768	; 0x8000
    1064:	f2c4 0203 	movt	r2, #16387	; 0x4003
    1068:	6c93      	ldr	r3, [r2, #72]	; 0x48

    /*
     * Signal to CoreSF2Reset that peripheral configuration registers have been
     * written.
     */
    CORE_SF2_CFG->CONFIG_DONE |= (CONFIG_1_DONE | CONFIG_2_DONE);
    106a:	f242 0000 	movw	r0, #8192	; 0x2000
     * do this here because this signal is only deasserted by the System
     * Controller on a power-on reset. Other types of reset such as a watchdog
     * reset would result in the FPGA fabric being held in reset and getting
     * stuck waiting for the CoreSF2Config INIT_DONE to become asserted.
     */
    SYSREG->SOFT_RST_CR &= ~SYSREG_FPGA_SOFTRESET_MASK;
    106e:	f423 3180 	bic.w	r1, r3, #65536	; 0x10000
    1072:	6491      	str	r1, [r2, #72]	; 0x48

    /*
     * Signal to CoreSF2Reset that peripheral configuration registers have been
     * written.
     */
    CORE_SF2_CFG->CONFIG_DONE |= (CONFIG_1_DONE | CONFIG_2_DONE);
    1074:	f2c4 0002 	movt	r0, #16386	; 0x4002
    1078:	6803      	ldr	r3, [r0, #0]
     
    /* Wait for INIT_DONE from CoreSF2Reset. */
    do
    {
        init_done = CORE_SF2_CFG->INIT_DONE & INIT_DONE_MASK;
    107a:	4602      	mov	r2, r0

    /*
     * Signal to CoreSF2Reset that peripheral configuration registers have been
     * written.
     */
    CORE_SF2_CFG->CONFIG_DONE |= (CONFIG_1_DONE | CONFIG_2_DONE);
    107c:	f043 0103 	orr.w	r1, r3, #3
    1080:	6001      	str	r1, [r0, #0]
     
    /* Wait for INIT_DONE from CoreSF2Reset. */
    do
    {
        init_done = CORE_SF2_CFG->INIT_DONE & INIT_DONE_MASK;
    1082:	6850      	ldr	r0, [r2, #4]
    } while (0u == init_done);
    1084:	f010 0f01 	tst.w	r0, #1
    1088:	d0fb      	beq.n	1082 <PROCESS_STACK_SIZE+0x82>
#endif
}
    108a:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
    108e:	bf00      	nop

00001090 <__libc_init_array>:
    1090:	b570      	push	{r4, r5, r6, lr}
    1092:	f241 3688 	movw	r6, #5000	; 0x1388
    1096:	f241 3588 	movw	r5, #5000	; 0x1388
    109a:	f2c0 0600 	movt	r6, #0
    109e:	f2c0 0500 	movt	r5, #0
    10a2:	1b76      	subs	r6, r6, r5
    10a4:	10b6      	asrs	r6, r6, #2
    10a6:	d006      	beq.n	10b6 <__libc_init_array+0x26>
    10a8:	2400      	movs	r4, #0
    10aa:	f855 3024 	ldr.w	r3, [r5, r4, lsl #2]
    10ae:	3401      	adds	r4, #1
    10b0:	4798      	blx	r3
    10b2:	42a6      	cmp	r6, r4
    10b4:	d8f9      	bhi.n	10aa <__libc_init_array+0x1a>
    10b6:	f241 3588 	movw	r5, #5000	; 0x1388
    10ba:	f241 368c 	movw	r6, #5004	; 0x138c
    10be:	f2c0 0500 	movt	r5, #0
    10c2:	f2c0 0600 	movt	r6, #0
    10c6:	1b76      	subs	r6, r6, r5
    10c8:	f000 f952 	bl	1370 <_init>
    10cc:	10b6      	asrs	r6, r6, #2
    10ce:	d006      	beq.n	10de <__libc_init_array+0x4e>
    10d0:	2400      	movs	r4, #0
    10d2:	f855 3024 	ldr.w	r3, [r5, r4, lsl #2]
    10d6:	3401      	adds	r4, #1
    10d8:	4798      	blx	r3
    10da:	42a6      	cmp	r6, r4
    10dc:	d8f9      	bhi.n	10d2 <__libc_init_array+0x42>
    10de:	bd70      	pop	{r4, r5, r6, pc}
    10e0:	6c655723 	.word	0x6c655723
    10e4:	656d6f63 	.word	0x656d6f63
    10e8:	206f7420 	.word	0x206f7420
    10ec:	72616d53 	.word	0x72616d53
    10f0:	73754674 	.word	0x73754674
    10f4:	326e6f69 	.word	0x326e6f69
    10f8:	52202d20 	.word	0x52202d20
    10fc:	696e6e75 	.word	0x696e6e75
    1100:	4820676e 	.word	0x4820676e
    1104:	69467865 	.word	0x69467865
    1108:	2330656c 	.word	0x2330656c
    110c:	00000d0a 	.word	0x00000d0a
    1110:	656c6553 	.word	0x656c6553
    1114:	74207463 	.word	0x74207463
    1118:	62206568 	.word	0x62206568
    111c:	776f6c65 	.word	0x776f6c65
    1120:	74706f20 	.word	0x74706f20
    1124:	0a6e6f69 	.word	0x0a6e6f69
    1128:	0000000d 	.word	0x0000000d
    112c:	52202e31 	.word	0x52202e31
    1130:	48206e75 	.word	0x48206e75
    1134:	46207865 	.word	0x46207865
    1138:	31656c69 	.word	0x31656c69
    113c:	6f726620 	.word	0x6f726620
    1140:	5365206d 	.word	0x5365206d
    1144:	0a4d4152 	.word	0x0a4d4152
    1148:	0000000d 	.word	0x0000000d
    114c:	52202e32 	.word	0x52202e32
    1150:	48206e75 	.word	0x48206e75
    1154:	46207865 	.word	0x46207865
    1158:	32656c69 	.word	0x32656c69
    115c:	6f726620 	.word	0x6f726620
    1160:	5365206d 	.word	0x5365206d
    1164:	0a4d4152 	.word	0x0a4d4152
    1168:	0000000d 	.word	0x0000000d
    116c:	52202e33 	.word	0x52202e33
    1170:	48206e75 	.word	0x48206e75
    1174:	46207865 	.word	0x46207865
    1178:	33656c69 	.word	0x33656c69
    117c:	6f726620 	.word	0x6f726620
    1180:	5365206d 	.word	0x5365206d
    1184:	0a4d4152 	.word	0x0a4d4152
    1188:	0000000d 	.word	0x0000000d
    118c:	52202e34 	.word	0x52202e34
    1190:	48206e75 	.word	0x48206e75
    1194:	46207865 	.word	0x46207865
    1198:	34656c69 	.word	0x34656c69
    119c:	6f726620 	.word	0x6f726620
    11a0:	5365206d 	.word	0x5365206d
    11a4:	0a4d4152 	.word	0x0a4d4152
    11a8:	0000000d 	.word	0x0000000d
    11ac:	52202e35 	.word	0x52202e35
    11b0:	48206e75 	.word	0x48206e75
    11b4:	46207865 	.word	0x46207865
    11b8:	35656c69 	.word	0x35656c69
    11bc:	6f726620 	.word	0x6f726620
    11c0:	4e65206d 	.word	0x4e65206d
    11c4:	0d0a4d56 	.word	0x0d0a4d56
    11c8:	00000000 	.word	0x00000000
    11cc:	75520d0a 	.word	0x75520d0a
    11d0:	6e696e6e 	.word	0x6e696e6e
    11d4:	65482067 	.word	0x65482067
    11d8:	69462078 	.word	0x69462078
    11dc:	0a31656c 	.word	0x0a31656c
    11e0:	0000000d 	.word	0x0000000d
    11e4:	75520d0a 	.word	0x75520d0a
    11e8:	6e696e6e 	.word	0x6e696e6e
    11ec:	65482067 	.word	0x65482067
    11f0:	69462078 	.word	0x69462078
    11f4:	0a32656c 	.word	0x0a32656c
    11f8:	0000000d 	.word	0x0000000d
    11fc:	75520d0a 	.word	0x75520d0a
    1200:	6e696e6e 	.word	0x6e696e6e
    1204:	65482067 	.word	0x65482067
    1208:	69462078 	.word	0x69462078
    120c:	0a33656c 	.word	0x0a33656c
    1210:	0000000d 	.word	0x0000000d
    1214:	75520d0a 	.word	0x75520d0a
    1218:	6e696e6e 	.word	0x6e696e6e
    121c:	65482067 	.word	0x65482067
    1220:	69462078 	.word	0x69462078
    1224:	0a34656c 	.word	0x0a34656c
    1228:	0000000d 	.word	0x0000000d
    122c:	75520d0a 	.word	0x75520d0a
    1230:	6e696e6e 	.word	0x6e696e6e
    1234:	65482067 	.word	0x65482067
    1238:	69462078 	.word	0x69462078
    123c:	0a35656c 	.word	0x0a35656c
    1240:	0000000d 	.word	0x0000000d
    1244:	6f636e49 	.word	0x6f636e49
    1248:	63657272 	.word	0x63657272
    124c:	706f2074 	.word	0x706f2074
    1250:	6e6f6974 	.word	0x6e6f6974
    1254:	00000d0a 	.word	0x00000d0a

00001258 <C.17.3534>:
    1258:	01000100 03030202                       ........

00001260 <g_m2s_mddr_subsys_config>:
    1260:	00000000 030f27de 00000002 09990101     .....'..........
    1270:	33330000 8888ffff 00010888 00084242     ..33........BB..
    1280:	00000528 00000000 00860ce0 00640235     (...........5.d.
    1290:	0178010f 19370033 00000010 00003300     ..x.3.7......3..
    12a0:	04060000 02000000 00120040 40000002     ........@......@
    12b0:	000780f8 000780f8 04000200 00050000     ................
    12c0:	00400003 00000000 00000000 00010309     ..@.............
    12d0:	00000000 00800000 00000000 00000003     ................
	...
    12e8:	0000000b 00000000 00800000 01002004     ............. ..
    12f8:	00000008 00000000 00000000 00000001     ................
	...
    1310:	05014050 00005014 00000000 00000000     P@...P..........
	...
    1330:	05010050 00005010 00000000 00000000     P....P..........
    1340:	00430000 00030000 00010001 00000000     ..C.............
    1350:	00010000 00000000 00000000 00000000     ................
	...

0000136c <g_m2s_mddr_addr>:
    136c:	40020800                                ...@

00001370 <_init>:
    1370:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    1372:	bf00      	nop
    1374:	bcf8      	pop	{r3, r4, r5, r6, r7}
    1376:	bc08      	pop	{r3}
    1378:	469e      	mov	lr, r3
    137a:	4770      	bx	lr

0000137c <_fini>:
    137c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    137e:	bf00      	nop
    1380:	bcf8      	pop	{r3, r4, r5, r6, r7}
    1382:	bc08      	pop	{r3}
    1384:	469e      	mov	lr, r3
    1386:	4770      	bx	lr

00001388 <__frame_dummy_init_array_entry>:
    1388:	0425 0000                                   %...

0000138c <__do_global_dtors_aux_fini_array_entry>:
    138c:	0411 0000                                   ....
