
Remapping_Appnote_MSS_CM3_app:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .vector_table 00000190  20000000  20000000  00008000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .init         00000820  20000190  20000190  00008190  2**4
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .text         00001060  200009b0  200009b0  000089b0  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  3 .data         00000020  20001a10  20001a10  00009a10  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  4 .bss          00000090  20001a30  20001a30  00009a30  2**2
                  ALLOC
  5 .heap         0000b540  20001ac0  20001ac0  00009a30  2**0
                  ALLOC
  6 .stack        00003000  2000d000  2000d000  00009a30  2**0
                  ALLOC
  7 .comment      000000d7  00000000  00000000  00009a30  2**0
                  CONTENTS, READONLY
  8 .debug_aranges 00000320  00000000  00000000  00009b07  2**0
                  CONTENTS, READONLY, DEBUGGING
  9 .debug_pubnames 000007a3  00000000  00000000  00009e27  2**0
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_info   00006842  00000000  00000000  0000a5ca  2**0
                  CONTENTS, READONLY, DEBUGGING
 11 .debug_abbrev 00000886  00000000  00000000  00010e0c  2**0
                  CONTENTS, READONLY, DEBUGGING
 12 .debug_line   000015e3  00000000  00000000  00011692  2**0
                  CONTENTS, READONLY, DEBUGGING
 13 .debug_frame  00000afc  00000000  00000000  00012c78  2**2
                  CONTENTS, READONLY, DEBUGGING
 14 .debug_str    00002d71  00000000  00000000  00013774  2**0
                  CONTENTS, READONLY, DEBUGGING
 15 .debug_loc    000012ac  00000000  00000000  000164e5  2**0
                  CONTENTS, READONLY, DEBUGGING
 16 .debug_macinfo 000249f7  00000000  00000000  00017791  2**0
                  CONTENTS, READONLY, DEBUGGING
 17 .ARM.attributes 00000025  00000000  00000000  0003c188  2**0
                  CONTENTS, READONLY
 18 .debug_ranges 00000300  00000000  00000000  0003c1ad  2**0
                  CONTENTS, READONLY, DEBUGGING

Disassembly of section .init:

20000190 <Reset_Handler>:
20000190:	f04f 0b00 	mov.w	fp, #0
20000194:	f8df 021a 	ldr.w	r0, [pc, #538]	; 200003b2 <SF2_MDDR_MODE_CR>
20000198:	6800      	ldr	r0, [r0, #0]
2000019a:	f8df 1212 	ldr.w	r1, [pc, #530]	; 200003ae <SF2_EDAC_CR>
2000019e:	6809      	ldr	r1, [r1, #0]
200001a0:	f001 0103 	and.w	r1, r1, #3
200001a4:	f000 001c 	and.w	r0, r0, #28
200001a8:	2814      	cmp	r0, #20
200001aa:	d101      	bne.n	200001b0 <check_esram_edac>
200001ac:	f04b 0b02 	orr.w	fp, fp, #2

200001b0 <check_esram_edac>:
200001b0:	2900      	cmp	r1, #0
200001b2:	d001      	beq.n	200001b8 <check_stack_init>
200001b4:	f04b 0b01 	orr.w	fp, fp, #1

200001b8 <check_stack_init>:
200001b8:	f1bb 0f00 	cmp.w	fp, #0
200001bc:	d00d      	beq.n	200001da <system_init>

200001be <clear_stack>:
200001be:	487e      	ldr	r0, [pc, #504]	; (200003b8 <SF2_MDDR_MODE_CR+0x6>)
200001c0:	497e      	ldr	r1, [pc, #504]	; (200003bc <SF2_MDDR_MODE_CR+0xa>)
200001c2:	f8df 21ce 	ldr.w	r2, [pc, #462]	; 20000392 <RAM_INIT_PATTERN>
200001c6:	f8df 31ca 	ldr.w	r3, [pc, #458]	; 20000392 <RAM_INIT_PATTERN>
200001ca:	f8df 41c6 	ldr.w	r4, [pc, #454]	; 20000392 <RAM_INIT_PATTERN>
200001ce:	f8df 51c2 	ldr.w	r5, [pc, #450]	; 20000392 <RAM_INIT_PATTERN>

200001d2 <clear_stack_loop>:
200001d2:	4288      	cmp	r0, r1
200001d4:	bf18      	it	ne
200001d6:	c03c      	stmiane	r0!, {r2, r3, r4, r5}
200001d8:	d1fb      	bne.n	200001d2 <clear_stack_loop>

200001da <system_init>:
200001da:	4879      	ldr	r0, [pc, #484]	; (200003c0 <SF2_MDDR_MODE_CR+0xe>)
200001dc:	4780      	blx	r0
200001de:	f00b 0a02 	and.w	sl, fp, #2
200001e2:	f1ba 0f00 	cmp.w	sl, #0
200001e6:	d00c      	beq.n	20000202 <remap_memory>
200001e8:	f8df 01ba 	ldr.w	r0, [pc, #442]	; 200003a6 <SF2_DDRB_NB_SIZE>
200001ec:	f8df 11ba 	ldr.w	r1, [pc, #442]	; 200003aa <SF2_DDRB_CR>
200001f0:	6802      	ldr	r2, [r0, #0]
200001f2:	680b      	ldr	r3, [r1, #0]
200001f4:	b40f      	push	{r0, r1, r2, r3}
200001f6:	f04f 0200 	mov.w	r2, #0
200001fa:	f04f 03ff 	mov.w	r3, #255	; 0xff
200001fe:	6002      	str	r2, [r0, #0]
20000200:	600b      	str	r3, [r1, #0]

20000202 <remap_memory>:
20000202:	4870      	ldr	r0, [pc, #448]	; (200003c4 <SF2_MDDR_MODE_CR+0x12>)
20000204:	4a70      	ldr	r2, [pc, #448]	; (200003c8 <SF2_MDDR_MODE_CR+0x16>)
20000206:	4b71      	ldr	r3, [pc, #452]	; (200003cc <SF2_MDDR_MODE_CR+0x1a>)
20000208:	2802      	cmp	r0, #2
2000020a:	d108      	bne.n	2000021e <check_esram_remap>
2000020c:	f8df 118a 	ldr.w	r1, [pc, #394]	; 2000039a <SF2_ESRAM_CR>
20000210:	600a      	str	r2, [r1, #0]
20000212:	f8df 118e 	ldr.w	r1, [pc, #398]	; 200003a2 <SF2_ENVM_REMAP_CR>
20000216:	600a      	str	r2, [r1, #0]
20000218:	f8df 1182 	ldr.w	r1, [pc, #386]	; 2000039e <SF2_DDR_CR>
2000021c:	600b      	str	r3, [r1, #0]

2000021e <check_esram_remap>:
2000021e:	2801      	cmp	r0, #1
20000220:	d108      	bne.n	20000234 <check_mirrored_nvm>
20000222:	f8df 117a 	ldr.w	r1, [pc, #378]	; 2000039e <SF2_DDR_CR>
20000226:	600a      	str	r2, [r1, #0]
20000228:	f8df 1176 	ldr.w	r1, [pc, #374]	; 200003a2 <SF2_ENVM_REMAP_CR>
2000022c:	600a      	str	r2, [r1, #0]
2000022e:	f8df 116a 	ldr.w	r1, [pc, #362]	; 2000039a <SF2_ESRAM_CR>
20000232:	600b      	str	r3, [r1, #0]

20000234 <check_mirrored_nvm>:
20000234:	4866      	ldr	r0, [pc, #408]	; (200003d0 <SF2_MDDR_MODE_CR+0x1e>)
20000236:	2800      	cmp	r0, #0
20000238:	d109      	bne.n	2000024e <copy_data>
2000023a:	4866      	ldr	r0, [pc, #408]	; (200003d4 <SF2_MDDR_MODE_CR+0x22>)
2000023c:	4966      	ldr	r1, [pc, #408]	; (200003d8 <SF2_MDDR_MODE_CR+0x26>)
2000023e:	4a67      	ldr	r2, [pc, #412]	; (200003dc <SF2_MDDR_MODE_CR+0x2a>)
20000240:	f000 f83a 	bl	200002b8 <block_copy>

20000244 <copy_text>:
20000244:	4866      	ldr	r0, [pc, #408]	; (200003e0 <SF2_MDDR_MODE_CR+0x2e>)
20000246:	4967      	ldr	r1, [pc, #412]	; (200003e4 <SF2_MDDR_MODE_CR+0x32>)
20000248:	4a67      	ldr	r2, [pc, #412]	; (200003e8 <SF2_MDDR_MODE_CR+0x36>)
2000024a:	f000 f835 	bl	200002b8 <block_copy>

2000024e <copy_data>:
2000024e:	4867      	ldr	r0, [pc, #412]	; (200003ec <SF2_MDDR_MODE_CR+0x3a>)
20000250:	4967      	ldr	r1, [pc, #412]	; (200003f0 <SF2_MDDR_MODE_CR+0x3e>)
20000252:	4a68      	ldr	r2, [pc, #416]	; (200003f4 <SF2_MDDR_MODE_CR+0x42>)
20000254:	f000 f830 	bl	200002b8 <block_copy>

20000258 <clear_bss>:
20000258:	4867      	ldr	r0, [pc, #412]	; (200003f8 <SF2_MDDR_MODE_CR+0x46>)
2000025a:	4968      	ldr	r1, [pc, #416]	; (200003fc <SF2_MDDR_MODE_CR+0x4a>)
2000025c:	4a5a      	ldr	r2, [pc, #360]	; (200003c8 <SF2_MDDR_MODE_CR+0x16>)
2000025e:	4b5a      	ldr	r3, [pc, #360]	; (200003c8 <SF2_MDDR_MODE_CR+0x16>)
20000260:	4c59      	ldr	r4, [pc, #356]	; (200003c8 <SF2_MDDR_MODE_CR+0x16>)
20000262:	4d59      	ldr	r5, [pc, #356]	; (200003c8 <SF2_MDDR_MODE_CR+0x16>)

20000264 <clear_bss_loop>:
20000264:	4288      	cmp	r0, r1
20000266:	bf18      	it	ne
20000268:	c03c      	stmiane	r0!, {r2, r3, r4, r5}
2000026a:	d1fb      	bne.n	20000264 <clear_bss_loop>

2000026c <clear_heap>:
2000026c:	f1bb 0f00 	cmp.w	fp, #0
20000270:	d016      	beq.n	200002a0 <call_glob_ctor>
20000272:	4863      	ldr	r0, [pc, #396]	; (20000400 <SF2_MDDR_MODE_CR+0x4e>)
20000274:	4963      	ldr	r1, [pc, #396]	; (20000404 <SF2_MDDR_MODE_CR+0x52>)
20000276:	f8df 211e 	ldr.w	r2, [pc, #286]	; 20000396 <HEAP_INIT_PATTERN>
2000027a:	f8df 311a 	ldr.w	r3, [pc, #282]	; 20000396 <HEAP_INIT_PATTERN>
2000027e:	f8df 4116 	ldr.w	r4, [pc, #278]	; 20000396 <HEAP_INIT_PATTERN>
20000282:	f8df 5112 	ldr.w	r5, [pc, #274]	; 20000396 <HEAP_INIT_PATTERN>

20000286 <clear_heap_loop>:
20000286:	4288      	cmp	r0, r1
20000288:	bf18      	it	ne
2000028a:	c03c      	stmiane	r0!, {r2, r3, r4, r5}
2000028c:	d1fb      	bne.n	20000286 <clear_heap_loop>
2000028e:	f00b 0a02 	and.w	sl, fp, #2
20000292:	f1ba 0f00 	cmp.w	sl, #0
20000296:	d003      	beq.n	200002a0 <call_glob_ctor>
20000298:	bc0f      	pop	{r0, r1, r2, r3}
2000029a:	6002      	str	r2, [r0, #0]
2000029c:	600b      	str	r3, [r1, #0]
	...

200002a0 <call_glob_ctor>:
200002a0:	f8df 0164 	ldr.w	r0, [pc, #356]	; 20000408 <SF2_MDDR_MODE_CR+0x56>
200002a4:	f20f 0e03 	addw	lr, pc, #3
200002a8:	4700      	bx	r0

200002aa <branch_to_main>:
200002aa:	f04f 0000 	mov.w	r0, #0
200002ae:	f04f 0100 	mov.w	r1, #0
200002b2:	f8df f158 	ldr.w	pc, [pc, #344]	; 2000040c <SF2_MDDR_MODE_CR+0x5a>

200002b6 <ExitLoop>:
200002b6:	e7fe      	b.n	200002b6 <ExitLoop>

200002b8 <block_copy>:
200002b8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
200002ba:	4288      	cmp	r0, r1
200002bc:	d00c      	beq.n	200002d8 <block_copy_exit>
200002be:	1a52      	subs	r2, r2, r1
200002c0:	1112      	asrs	r2, r2, #4
200002c2:	f012 0f0f 	tst.w	r2, #15
200002c6:	d000      	beq.n	200002ca <block_copy_loop>
200002c8:	3201      	adds	r2, #1

200002ca <block_copy_loop>:
200002ca:	429a      	cmp	r2, r3
200002cc:	bf1c      	itt	ne
200002ce:	c8f0      	ldmiane	r0!, {r4, r5, r6, r7}
200002d0:	c1f0      	stmiane	r1!, {r4, r5, r6, r7}
200002d2:	f103 0301 	add.w	r3, r3, #1
200002d6:	d1f8      	bne.n	200002ca <block_copy_loop>

200002d8 <block_copy_exit>:
200002d8:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

200002da <NMI_Handler>:
200002da:	e7fe      	b.n	200002da <NMI_Handler>

200002dc <HardFault_Handler>:
200002dc:	e7fe      	b.n	200002dc <HardFault_Handler>

200002de <MemManage_Handler>:
200002de:	e7fe      	b.n	200002de <MemManage_Handler>

200002e0 <BusFault_Handler>:
200002e0:	e7fe      	b.n	200002e0 <BusFault_Handler>

200002e2 <UsageFault_Handler>:
200002e2:	e7fe      	b.n	200002e2 <UsageFault_Handler>

200002e4 <SVC_Handler>:
200002e4:	e7fe      	b.n	200002e4 <SVC_Handler>

200002e6 <DebugMon_Handler>:
200002e6:	e7fe      	b.n	200002e6 <DebugMon_Handler>

200002e8 <PendSV_Handler>:
200002e8:	e7fe      	b.n	200002e8 <PendSV_Handler>

200002ea <SysTick_Handler>:
200002ea:	e7fe      	b.n	200002ea <SysTick_Handler>

200002ec <WdogWakeup_IRQHandler>:
200002ec:	e7fe      	b.n	200002ec <WdogWakeup_IRQHandler>

200002ee <RTC_Wakeup_IRQHandler>:
200002ee:	e7fe      	b.n	200002ee <RTC_Wakeup_IRQHandler>

200002f0 <SPI0_IRQHandler>:
200002f0:	e7fe      	b.n	200002f0 <SPI0_IRQHandler>

200002f2 <SPI1_IRQHandler>:
200002f2:	e7fe      	b.n	200002f2 <SPI1_IRQHandler>

200002f4 <I2C0_IRQHandler>:
200002f4:	e7fe      	b.n	200002f4 <I2C0_IRQHandler>

200002f6 <I2C0_SMBAlert_IRQHandler>:
200002f6:	e7fe      	b.n	200002f6 <I2C0_SMBAlert_IRQHandler>

200002f8 <I2C0_SMBus_IRQHandler>:
200002f8:	e7fe      	b.n	200002f8 <I2C0_SMBus_IRQHandler>

200002fa <I2C1_IRQHandler>:
200002fa:	e7fe      	b.n	200002fa <I2C1_IRQHandler>

200002fc <I2C1_SMBAlert_IRQHandler>:
200002fc:	e7fe      	b.n	200002fc <I2C1_SMBAlert_IRQHandler>

200002fe <I2C1_SMBus_IRQHandler>:
200002fe:	e7fe      	b.n	200002fe <I2C1_SMBus_IRQHandler>
20000300:	e7fe      	b.n	20000300 <I2C1_SMBus_IRQHandler+0x2>
20000302:	e7fe      	b.n	20000302 <I2C1_SMBus_IRQHandler+0x4>

20000304 <EthernetMAC_IRQHandler>:
20000304:	e7fe      	b.n	20000304 <EthernetMAC_IRQHandler>

20000306 <DMA_IRQHandler>:
20000306:	e7fe      	b.n	20000306 <DMA_IRQHandler>

20000308 <Timer1_IRQHandler>:
20000308:	e7fe      	b.n	20000308 <Timer1_IRQHandler>

2000030a <Timer2_IRQHandler>:
2000030a:	e7fe      	b.n	2000030a <Timer2_IRQHandler>

2000030c <CAN_IRQHandler>:
2000030c:	e7fe      	b.n	2000030c <CAN_IRQHandler>

2000030e <ENVM0_IRQHandler>:
2000030e:	e7fe      	b.n	2000030e <ENVM0_IRQHandler>

20000310 <ENVM1_IRQHandler>:
20000310:	e7fe      	b.n	20000310 <ENVM1_IRQHandler>

20000312 <ComBlk_IRQHandler>:
20000312:	e7fe      	b.n	20000312 <ComBlk_IRQHandler>

20000314 <USB_IRQHandler>:
20000314:	e7fe      	b.n	20000314 <USB_IRQHandler>

20000316 <USB_DMA_IRQHandler>:
20000316:	e7fe      	b.n	20000316 <USB_DMA_IRQHandler>

20000318 <PLL_Lock_IRQHandler>:
20000318:	e7fe      	b.n	20000318 <PLL_Lock_IRQHandler>

2000031a <PLL_LockLost_IRQHandler>:
2000031a:	e7fe      	b.n	2000031a <PLL_LockLost_IRQHandler>

2000031c <CommSwitchError_IRQHandler>:
2000031c:	e7fe      	b.n	2000031c <CommSwitchError_IRQHandler>

2000031e <CacheError_IRQHandler>:
2000031e:	e7fe      	b.n	2000031e <CacheError_IRQHandler>

20000320 <DDR_IRQHandler>:
20000320:	e7fe      	b.n	20000320 <DDR_IRQHandler>

20000322 <HPDMA_Complete_IRQHandler>:
20000322:	e7fe      	b.n	20000322 <HPDMA_Complete_IRQHandler>

20000324 <HPDMA_Error_IRQHandler>:
20000324:	e7fe      	b.n	20000324 <HPDMA_Error_IRQHandler>

20000326 <ECC_Error_IRQHandler>:
20000326:	e7fe      	b.n	20000326 <ECC_Error_IRQHandler>

20000328 <MDDR_IOCalib_IRQHandler>:
20000328:	e7fe      	b.n	20000328 <MDDR_IOCalib_IRQHandler>

2000032a <FAB_PLL_Lock_IRQHandler>:
2000032a:	e7fe      	b.n	2000032a <FAB_PLL_Lock_IRQHandler>

2000032c <FAB_PLL_LockLost_IRQHandler>:
2000032c:	e7fe      	b.n	2000032c <FAB_PLL_LockLost_IRQHandler>

2000032e <FIC64_IRQHandler>:
2000032e:	e7fe      	b.n	2000032e <FIC64_IRQHandler>

20000330 <FabricIrq0_IRQHandler>:
20000330:	e7fe      	b.n	20000330 <FabricIrq0_IRQHandler>

20000332 <FabricIrq1_IRQHandler>:
20000332:	e7fe      	b.n	20000332 <FabricIrq1_IRQHandler>

20000334 <FabricIrq2_IRQHandler>:
20000334:	e7fe      	b.n	20000334 <FabricIrq2_IRQHandler>

20000336 <FabricIrq3_IRQHandler>:
20000336:	e7fe      	b.n	20000336 <FabricIrq3_IRQHandler>

20000338 <FabricIrq4_IRQHandler>:
20000338:	e7fe      	b.n	20000338 <FabricIrq4_IRQHandler>

2000033a <FabricIrq5_IRQHandler>:
2000033a:	e7fe      	b.n	2000033a <FabricIrq5_IRQHandler>

2000033c <FabricIrq6_IRQHandler>:
2000033c:	e7fe      	b.n	2000033c <FabricIrq6_IRQHandler>

2000033e <FabricIrq7_IRQHandler>:
2000033e:	e7fe      	b.n	2000033e <FabricIrq7_IRQHandler>

20000340 <FabricIrq8_IRQHandler>:
20000340:	e7fe      	b.n	20000340 <FabricIrq8_IRQHandler>

20000342 <FabricIrq9_IRQHandler>:
20000342:	e7fe      	b.n	20000342 <FabricIrq9_IRQHandler>

20000344 <FabricIrq10_IRQHandler>:
20000344:	e7fe      	b.n	20000344 <FabricIrq10_IRQHandler>

20000346 <FabricIrq11_IRQHandler>:
20000346:	e7fe      	b.n	20000346 <FabricIrq11_IRQHandler>

20000348 <FabricIrq12_IRQHandler>:
20000348:	e7fe      	b.n	20000348 <FabricIrq12_IRQHandler>

2000034a <FabricIrq13_IRQHandler>:
2000034a:	e7fe      	b.n	2000034a <FabricIrq13_IRQHandler>

2000034c <FabricIrq14_IRQHandler>:
2000034c:	e7fe      	b.n	2000034c <FabricIrq14_IRQHandler>

2000034e <FabricIrq15_IRQHandler>:
2000034e:	e7fe      	b.n	2000034e <FabricIrq15_IRQHandler>

20000350 <GPIO0_IRQHandler>:
20000350:	e7fe      	b.n	20000350 <GPIO0_IRQHandler>

20000352 <GPIO1_IRQHandler>:
20000352:	e7fe      	b.n	20000352 <GPIO1_IRQHandler>

20000354 <GPIO2_IRQHandler>:
20000354:	e7fe      	b.n	20000354 <GPIO2_IRQHandler>

20000356 <GPIO3_IRQHandler>:
20000356:	e7fe      	b.n	20000356 <GPIO3_IRQHandler>

20000358 <GPIO4_IRQHandler>:
20000358:	e7fe      	b.n	20000358 <GPIO4_IRQHandler>

2000035a <GPIO5_IRQHandler>:
2000035a:	e7fe      	b.n	2000035a <GPIO5_IRQHandler>

2000035c <GPIO6_IRQHandler>:
2000035c:	e7fe      	b.n	2000035c <GPIO6_IRQHandler>

2000035e <GPIO7_IRQHandler>:
2000035e:	e7fe      	b.n	2000035e <GPIO7_IRQHandler>

20000360 <GPIO8_IRQHandler>:
20000360:	e7fe      	b.n	20000360 <GPIO8_IRQHandler>

20000362 <GPIO9_IRQHandler>:
20000362:	e7fe      	b.n	20000362 <GPIO9_IRQHandler>

20000364 <GPIO10_IRQHandler>:
20000364:	e7fe      	b.n	20000364 <GPIO10_IRQHandler>

20000366 <GPIO11_IRQHandler>:
20000366:	e7fe      	b.n	20000366 <GPIO11_IRQHandler>

20000368 <GPIO12_IRQHandler>:
20000368:	e7fe      	b.n	20000368 <GPIO12_IRQHandler>

2000036a <GPIO13_IRQHandler>:
2000036a:	e7fe      	b.n	2000036a <GPIO13_IRQHandler>

2000036c <GPIO14_IRQHandler>:
2000036c:	e7fe      	b.n	2000036c <GPIO14_IRQHandler>

2000036e <GPIO15_IRQHandler>:
2000036e:	e7fe      	b.n	2000036e <GPIO15_IRQHandler>

20000370 <GPIO16_IRQHandler>:
20000370:	e7fe      	b.n	20000370 <GPIO16_IRQHandler>

20000372 <GPIO17_IRQHandler>:
20000372:	e7fe      	b.n	20000372 <GPIO17_IRQHandler>

20000374 <GPIO18_IRQHandler>:
20000374:	e7fe      	b.n	20000374 <GPIO18_IRQHandler>

20000376 <GPIO19_IRQHandler>:
20000376:	e7fe      	b.n	20000376 <GPIO19_IRQHandler>

20000378 <GPIO20_IRQHandler>:
20000378:	e7fe      	b.n	20000378 <GPIO20_IRQHandler>

2000037a <GPIO21_IRQHandler>:
2000037a:	e7fe      	b.n	2000037a <GPIO21_IRQHandler>

2000037c <GPIO22_IRQHandler>:
2000037c:	e7fe      	b.n	2000037c <GPIO22_IRQHandler>

2000037e <GPIO23_IRQHandler>:
2000037e:	e7fe      	b.n	2000037e <GPIO23_IRQHandler>

20000380 <GPIO24_IRQHandler>:
20000380:	e7fe      	b.n	20000380 <GPIO24_IRQHandler>

20000382 <GPIO25_IRQHandler>:
20000382:	e7fe      	b.n	20000382 <GPIO25_IRQHandler>

20000384 <GPIO26_IRQHandler>:
20000384:	e7fe      	b.n	20000384 <GPIO26_IRQHandler>

20000386 <GPIO27_IRQHandler>:
20000386:	e7fe      	b.n	20000386 <GPIO27_IRQHandler>

20000388 <GPIO28_IRQHandler>:
20000388:	e7fe      	b.n	20000388 <GPIO28_IRQHandler>

2000038a <GPIO29_IRQHandler>:
2000038a:	e7fe      	b.n	2000038a <GPIO29_IRQHandler>

2000038c <GPIO30_IRQHandler>:
2000038c:	e7fe      	b.n	2000038c <GPIO30_IRQHandler>

2000038e <GPIO31_IRQHandler>:
2000038e:	e7fe      	b.n	2000038e <GPIO31_IRQHandler>

20000390 <mscc_post_hw_cfg_init>:
20000390:	4770      	bx	lr

20000392 <RAM_INIT_PATTERN>:
20000392:	0000      	.short	0x0000
	...

20000396 <HEAP_INIT_PATTERN>:
20000396:	a2a2      	.short	0xa2a2
20000398:	a2a2      	.short	0xa2a2

2000039a <SF2_ESRAM_CR>:
2000039a:	8000      	.short	0x8000
2000039c:	4003      	.short	0x4003

2000039e <SF2_DDR_CR>:
2000039e:	8008      	.short	0x8008
200003a0:	4003      	.short	0x4003

200003a2 <SF2_ENVM_REMAP_CR>:
200003a2:	8010      	.short	0x8010
200003a4:	4003      	.short	0x4003

200003a6 <SF2_DDRB_NB_SIZE>:
200003a6:	8030      	.short	0x8030
200003a8:	4003      	.short	0x4003

200003aa <SF2_DDRB_CR>:
200003aa:	8034      	.short	0x8034
200003ac:	4003      	.short	0x4003

200003ae <SF2_EDAC_CR>:
200003ae:	8038      	.short	0x8038
200003b0:	4003      	.short	0x4003

200003b2 <SF2_MDDR_MODE_CR>:
200003b2:	0818      	.short	0x0818
200003b4:	00004002 	.word	0x00004002
200003b8:	2000d000 	.word	0x2000d000
200003bc:	20010000 	.word	0x20010000
200003c0:	20000411 	.word	0x20000411
200003c4:	00000001 	.word	0x00000001
200003c8:	00000000 	.word	0x00000000
200003cc:	00000001 	.word	0x00000001
200003d0:	00000000 	.word	0x00000000
200003d4:	20000000 	.word	0x20000000
200003d8:	20000000 	.word	0x20000000
200003dc:	20000190 	.word	0x20000190
200003e0:	200009b0 	.word	0x200009b0
200003e4:	200009b0 	.word	0x200009b0
200003e8:	20001a10 	.word	0x20001a10
200003ec:	20001a10 	.word	0x20001a10
200003f0:	20001a10 	.word	0x20001a10
200003f4:	20001a30 	.word	0x20001a30
200003f8:	20001a30 	.word	0x20001a30
200003fc:	20001ac0 	.word	0x20001ac0
20000400:	20001ac0 	.word	0x20001ac0
20000404:	2000d000 	.word	0x2000d000
20000408:	20001821 	.word	0x20001821
2000040c:	20000b85 	.word	0x20000b85

20000410 <SystemInit>:

/***************************************************************************//**
 * See system_m2sxxx.h for details.
 */
void SystemInit(void)
{
20000410:	b580      	push	{r7, lr}
20000412:	b082      	sub	sp, #8
20000414:	af00      	add	r7, sp, #0
     */
#if (MSS_SYS_FACC_INIT_BY_CORTEX == 1)
    complete_clock_config();
#endif

    silicon_workarounds();
20000416:	f000 fa0b 	bl	20000830 <silicon_workarounds>
    /*--------------------------------------------------------------------------
     * Set STKALIGN to ensure exception stacking starts on 8 bytes address
     * boundary. This ensures compliance with the "Procedure Call Standards for
     * the ARM Architecture" (AAPCS).
     */
    SCB->CCR |= SCB_CCR_STKALIGN_Msk;
2000041a:	f64e 5300 	movw	r3, #60672	; 0xed00
2000041e:	f2ce 0300 	movt	r3, #57344	; 0xe000
20000422:	f64e 5200 	movw	r2, #60672	; 0xed00
20000426:	f2ce 0200 	movt	r2, #57344	; 0xe000
2000042a:	6952      	ldr	r2, [r2, #20]
2000042c:	f442 7200 	orr.w	r2, r2, #512	; 0x200
20000430:	615a      	str	r2, [r3, #20]
    
    /*--------------------------------------------------------------------------
     * MDDR configuration
     */
#if MSS_SYS_MDDR_CONFIG_BY_CORTEX
    if(0u == SYSREG->DDR_CR)
20000432:	f248 0300 	movw	r3, #32768	; 0x8000
20000436:	f2c4 0303 	movt	r3, #16387	; 0x4003
2000043a:	689b      	ldr	r3, [r3, #8]
2000043c:	2b00      	cmp	r3, #0
2000043e:	d10b      	bne.n	20000458 <SystemInit+0x48>
         * to address 0x00000000. If MDDR is remapped to 0x00000000 then we are
         * probably executing this code from MDDR in a debugging session and
         * attempting to reconfigure the MDDR memory controller will cause the
         * Cortex-M3 to crash.
         */
        config_ddr_subsys(&g_m2s_mddr_subsys_config, &g_m2s_mddr_addr->core);
20000440:	f640 0394 	movw	r3, #2196	; 0x894
20000444:	f2c2 0300 	movt	r3, #8192	; 0x2000
20000448:	681b      	ldr	r3, [r3, #0]
2000044a:	f640 0098 	movw	r0, #2200	; 0x898
2000044e:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000452:	4619      	mov	r1, r3
20000454:	f000 f94c 	bl	200006f0 <config_ddr_subsys>
#endif

    /*--------------------------------------------------------------------------
     * Call user defined configuration function.
     */
    mscc_post_hw_cfg_init();
20000458:	f7ff ff9a 	bl	20000390 <mscc_post_hw_cfg_init>
     * do this here because this signal is only deasserted by the System
     * Controller on a power-on reset. Other types of reset such as a watchdog
     * reset would result in the FPGA fabric being held in reset and getting
     * stuck waiting for the CoreSF2Config INIT_DONE to become asserted.
     */
    SYSREG->SOFT_RST_CR &= ~SYSREG_FPGA_SOFTRESET_MASK;
2000045c:	f248 0300 	movw	r3, #32768	; 0x8000
20000460:	f2c4 0303 	movt	r3, #16387	; 0x4003
20000464:	f248 0200 	movw	r2, #32768	; 0x8000
20000468:	f2c4 0203 	movt	r2, #16387	; 0x4003
2000046c:	6c92      	ldr	r2, [r2, #72]	; 0x48
2000046e:	f422 3280 	bic.w	r2, r2, #65536	; 0x10000
20000472:	649a      	str	r2, [r3, #72]	; 0x48

    /*
     * Signal to CoreSF2Reset that peripheral configuration registers have been
     * written.
     */
    CORE_SF2_CFG->CONFIG_DONE |= (CONFIG_1_DONE | CONFIG_2_DONE);
20000474:	f242 0300 	movw	r3, #8192	; 0x2000
20000478:	f2c4 0302 	movt	r3, #16386	; 0x4002
2000047c:	f242 0200 	movw	r2, #8192	; 0x2000
20000480:	f2c4 0202 	movt	r2, #16386	; 0x4002
20000484:	6812      	ldr	r2, [r2, #0]
20000486:	f042 0203 	orr.w	r2, r2, #3
2000048a:	601a      	str	r2, [r3, #0]
     
    /* Wait for INIT_DONE from CoreSF2Reset. */
    do
    {
        init_done = CORE_SF2_CFG->INIT_DONE & INIT_DONE_MASK;
2000048c:	f242 0300 	movw	r3, #8192	; 0x2000
20000490:	f2c4 0302 	movt	r3, #16386	; 0x4002
20000494:	685b      	ldr	r3, [r3, #4]
20000496:	f003 0301 	and.w	r3, r3, #1
2000049a:	607b      	str	r3, [r7, #4]
    } while (0u == init_done);
2000049c:	687b      	ldr	r3, [r7, #4]
2000049e:	2b00      	cmp	r3, #0
200004a0:	d0f4      	beq.n	2000048c <SystemInit+0x7c>
#endif
}
200004a2:	f107 0708 	add.w	r7, r7, #8
200004a6:	46bd      	mov	sp, r7
200004a8:	bd80      	pop	{r7, pc}
200004aa:	bf00      	nop

200004ac <SystemCoreClockUpdate>:
#define FREQ_1MHZ    1000000u
#define FREQ_25MHZ   25000000u
#define FREQ_50MHZ   50000000u

void SystemCoreClockUpdate(void)
{
200004ac:	b580      	push	{r7, lr}
200004ae:	b088      	sub	sp, #32
200004b0:	af00      	add	r7, sp, #0
    uint32_t controller_pll_init;
    uint32_t clk_src;

    controller_pll_init = SYSREG->MSSDDR_FACC1_CR & CONTROLLER_PLL_INIT_MASK;
200004b2:	f248 0300 	movw	r3, #32768	; 0x8000
200004b6:	f2c4 0303 	movt	r3, #16387	; 0x4003
200004ba:	f8d3 3098 	ldr.w	r3, [r3, #152]	; 0x98
200004be:	f003 6380 	and.w	r3, r3, #67108864	; 0x4000000
200004c2:	60fb      	str	r3, [r7, #12]
    
    if(0u == controller_pll_init)
200004c4:	68fb      	ldr	r3, [r7, #12]
200004c6:	2b00      	cmp	r3, #0
200004c8:	f040 808b 	bne.w	200005e2 <SystemCoreClockUpdate+0x136>
    {
        /* Normal operations. */
        uint32_t global_mux_sel;
        
        global_mux_sel = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK;
200004cc:	f248 0300 	movw	r3, #32768	; 0x8000
200004d0:	f2c4 0303 	movt	r3, #16387	; 0x4003
200004d4:	f8d3 3098 	ldr.w	r3, [r3, #152]	; 0x98
200004d8:	f403 5380 	and.w	r3, r3, #4096	; 0x1000
200004dc:	617b      	str	r3, [r7, #20]
        if(0u == global_mux_sel)
200004de:	697b      	ldr	r3, [r7, #20]
200004e0:	2b00      	cmp	r3, #0
200004e2:	d13f      	bne.n	20000564 <SystemCoreClockUpdate+0xb8>
        {
            /* MSS clocked from MSS PLL. Use Libero flow defines. */
            SystemCoreClock = MSS_SYS_M3_CLK_FREQ;
200004e4:	f641 2314 	movw	r3, #6676	; 0x1a14
200004e8:	f2c2 0300 	movt	r3, #8192	; 0x2000
200004ec:	f64b 12c0 	movw	r2, #47552	; 0xb9c0
200004f0:	f2c0 629d 	movt	r2, #1693	; 0x69d
200004f4:	601a      	str	r2, [r3, #0]
            g_FrequencyPCLK0 = MSS_SYS_APB_0_CLK_FREQ;
200004f6:	f641 2318 	movw	r3, #6680	; 0x1a18
200004fa:	f2c2 0300 	movt	r3, #8192	; 0x2000
200004fe:	f64b 12c0 	movw	r2, #47552	; 0xb9c0
20000502:	f2c0 629d 	movt	r2, #1693	; 0x69d
20000506:	601a      	str	r2, [r3, #0]
            g_FrequencyPCLK1 = MSS_SYS_APB_1_CLK_FREQ;
20000508:	f641 231c 	movw	r3, #6684	; 0x1a1c
2000050c:	f2c2 0300 	movt	r3, #8192	; 0x2000
20000510:	f64b 12c0 	movw	r2, #47552	; 0xb9c0
20000514:	f2c0 629d 	movt	r2, #1693	; 0x69d
20000518:	601a      	str	r2, [r3, #0]
            g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
2000051a:	f641 2320 	movw	r3, #6688	; 0x1a20
2000051e:	f2c2 0300 	movt	r3, #8192	; 0x2000
20000522:	f646 6270 	movw	r2, #28272	; 0x6e70
20000526:	f2c0 12a7 	movt	r2, #423	; 0x1a7
2000052a:	601a      	str	r2, [r3, #0]
            g_FrequencyFIC0 = MSS_SYS_FIC_0_CLK_FREQ;
2000052c:	f641 2324 	movw	r3, #6692	; 0x1a24
20000530:	f2c2 0300 	movt	r3, #8192	; 0x2000
20000534:	f64b 12c0 	movw	r2, #47552	; 0xb9c0
20000538:	f2c0 629d 	movt	r2, #1693	; 0x69d
2000053c:	601a      	str	r2, [r3, #0]
            g_FrequencyFIC1 = MSS_SYS_FIC_1_CLK_FREQ;
2000053e:	f641 2328 	movw	r3, #6696	; 0x1a28
20000542:	f2c2 0300 	movt	r3, #8192	; 0x2000
20000546:	f64b 12c0 	movw	r2, #47552	; 0xb9c0
2000054a:	f2c0 629d 	movt	r2, #1693	; 0x69d
2000054e:	601a      	str	r2, [r3, #0]
            g_FrequencyFIC64 = MSS_SYS_FIC64_CLK_FREQ;
20000550:	f641 232c 	movw	r3, #6700	; 0x1a2c
20000554:	f2c2 0300 	movt	r3, #8192	; 0x2000
20000558:	f642 5240 	movw	r2, #11584	; 0x2d40
2000055c:	f2c1 32d9 	movt	r2, #5081	; 0x13d9
20000560:	601a      	str	r2, [r3, #0]
                break;
                
                case CCC2ASCI_CLK_SRC:
                    /* Fall through. */
                default:
                    set_clock_frequency_globals(FREQ_1MHZ);
20000562:	e045      	b.n	200005f0 <SystemCoreClockUpdate+0x144>
                                                   RCOSC_25_50MHZ_CLK_SRC,
                                                   CLK_XTAL_CLK_SRC,
                                                   RCOSC_1_MHZ_CLK_SRC,
                                                   RCOSC_1_MHZ_CLK_SRC,
                                                   CCC2ASCI_CLK_SRC,
                                                   CCC2ASCI_CLK_SRC };
20000564:	f641 13e8 	movw	r3, #6632	; 0x19e8
20000568:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000056c:	f107 0204 	add.w	r2, r7, #4
20000570:	e893 0003 	ldmia.w	r3, {r0, r1}
20000574:	e882 0003 	stmia.w	r2, {r0, r1}
            
            uint32_t standby_sel;
            uint8_t clock_source;
            
            standby_sel = (SYSREG->MSSDDR_FACC2_CR >> FACC_STANDBY_SHIFT) & FACC_STANDBY_SEL_MASK;
20000578:	f248 0300 	movw	r3, #32768	; 0x8000
2000057c:	f2c4 0303 	movt	r3, #16387	; 0x4003
20000580:	f8d3 309c 	ldr.w	r3, [r3, #156]	; 0x9c
20000584:	ea4f 1393 	mov.w	r3, r3, lsr #6
20000588:	f003 0307 	and.w	r3, r3, #7
2000058c:	61bb      	str	r3, [r7, #24]
            clock_source = standby_clock_lut[standby_sel];
2000058e:	69bb      	ldr	r3, [r7, #24]
20000590:	f107 0220 	add.w	r2, r7, #32
20000594:	4413      	add	r3, r2
20000596:	f813 3c1c 	ldrb.w	r3, [r3, #-28]
2000059a:	77fb      	strb	r3, [r7, #31]
            switch(clock_source)
2000059c:	7ffb      	ldrb	r3, [r7, #31]
2000059e:	2b01      	cmp	r3, #1
200005a0:	d00b      	beq.n	200005ba <SystemCoreClockUpdate+0x10e>
200005a2:	2b02      	cmp	r3, #2
200005a4:	d00e      	beq.n	200005c4 <SystemCoreClockUpdate+0x118>
200005a6:	2b00      	cmp	r3, #0
200005a8:	d114      	bne.n	200005d4 <SystemCoreClockUpdate+0x128>
            {
                case RCOSC_25_50MHZ_CLK_SRC:
                    clk_src = get_rcosc_25_50mhz_frequency();
200005aa:	f000 f825 	bl	200005f8 <get_rcosc_25_50mhz_frequency>
200005ae:	4603      	mov	r3, r0
200005b0:	613b      	str	r3, [r7, #16]
                    set_clock_frequency_globals(clk_src);
200005b2:	6938      	ldr	r0, [r7, #16]
200005b4:	f000 f842 	bl	2000063c <set_clock_frequency_globals>
                break;
200005b8:	e01a      	b.n	200005f0 <SystemCoreClockUpdate+0x144>
                
                case CLK_XTAL_CLK_SRC:
                    set_clock_frequency_globals(FREQ_32KHZ);
200005ba:	f44f 4000 	mov.w	r0, #32768	; 0x8000
200005be:	f000 f83d 	bl	2000063c <set_clock_frequency_globals>
                break;
200005c2:	e015      	b.n	200005f0 <SystemCoreClockUpdate+0x144>
                
                case RCOSC_1_MHZ_CLK_SRC:
                    set_clock_frequency_globals(FREQ_1MHZ);
200005c4:	f244 2040 	movw	r0, #16960	; 0x4240
200005c8:	f2c0 000f 	movt	r0, #15
200005cc:	f000 f836 	bl	2000063c <set_clock_frequency_globals>
                break;
200005d0:	bf00      	nop
200005d2:	e00d      	b.n	200005f0 <SystemCoreClockUpdate+0x144>
                
                case CCC2ASCI_CLK_SRC:
                    /* Fall through. */
                default:
                    set_clock_frequency_globals(FREQ_1MHZ);
200005d4:	f244 2040 	movw	r0, #16960	; 0x4240
200005d8:	f2c0 000f 	movt	r0, #15
200005dc:	f000 f82e 	bl	2000063c <set_clock_frequency_globals>
200005e0:	e006      	b.n	200005f0 <SystemCoreClockUpdate+0x144>
        }
    }
    else
    {
        /* PLL initialization mode. Running from 25/50MHZ RC oscillator. */
        clk_src = get_rcosc_25_50mhz_frequency();
200005e2:	f000 f809 	bl	200005f8 <get_rcosc_25_50mhz_frequency>
200005e6:	4603      	mov	r3, r0
200005e8:	613b      	str	r3, [r7, #16]
        set_clock_frequency_globals(clk_src);
200005ea:	6938      	ldr	r0, [r7, #16]
200005ec:	f000 f826 	bl	2000063c <set_clock_frequency_globals>
    }
}
200005f0:	f107 0720 	add.w	r7, r7, #32
200005f4:	46bd      	mov	sp, r7
200005f6:	bd80      	pop	{r7, pc}

200005f8 <get_rcosc_25_50mhz_frequency>:

/***************************************************************************//**
 * Find out frequency generated by the 25_50mhz RC osciallator.
 */
static uint32_t get_rcosc_25_50mhz_frequency(void)
{
200005f8:	b480      	push	{r7}
200005fa:	b083      	sub	sp, #12
200005fc:	af00      	add	r7, sp, #0
    uint32_t rcosc_div2;
    uint32_t rcosc_frequency;
    
    rcosc_div2 = SYSREG->MSSDDR_PLL_STATUS & RCOSC_DIV2_MASK;
200005fe:	f248 0300 	movw	r3, #32768	; 0x8000
20000602:	f2c4 0303 	movt	r3, #16387	; 0x4003
20000606:	f8d3 3150 	ldr.w	r3, [r3, #336]	; 0x150
2000060a:	f003 0304 	and.w	r3, r3, #4
2000060e:	603b      	str	r3, [r7, #0]
    if(0u == rcosc_div2)
20000610:	683b      	ldr	r3, [r7, #0]
20000612:	2b00      	cmp	r3, #0
20000614:	d105      	bne.n	20000622 <get_rcosc_25_50mhz_frequency+0x2a>
    {
        /* 25_50mhz oscillator is configured for 25 MHz operations. */
        rcosc_frequency = FREQ_25MHZ;
20000616:	f647 0340 	movw	r3, #30784	; 0x7840
2000061a:	f2c0 137d 	movt	r3, #381	; 0x17d
2000061e:	607b      	str	r3, [r7, #4]
20000620:	e004      	b.n	2000062c <get_rcosc_25_50mhz_frequency+0x34>
    }
    else
    {
        /* 25_50mhz oscillator is configured for 50 MHz operations. */
        rcosc_frequency = FREQ_50MHZ;
20000622:	f24f 0380 	movw	r3, #61568	; 0xf080
20000626:	f2c0 23fa 	movt	r3, #762	; 0x2fa
2000062a:	607b      	str	r3, [r7, #4]
    }
    
    return rcosc_frequency;
2000062c:	687b      	ldr	r3, [r7, #4]
}
2000062e:	4618      	mov	r0, r3
20000630:	f107 070c 	add.w	r7, r7, #12
20000634:	46bd      	mov	sp, r7
20000636:	bc80      	pop	{r7}
20000638:	4770      	bx	lr
2000063a:	bf00      	nop

2000063c <set_clock_frequency_globals>:
        - g_FrequencyFIC0
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
2000063c:	b480      	push	{r7}
2000063e:	b083      	sub	sp, #12
20000640:	af00      	add	r7, sp, #0
20000642:	6078      	str	r0, [r7, #4]
    SystemCoreClock = standby_clk;
20000644:	f641 2314 	movw	r3, #6676	; 0x1a14
20000648:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000064c:	687a      	ldr	r2, [r7, #4]
2000064e:	601a      	str	r2, [r3, #0]
    g_FrequencyPCLK0 = standby_clk;
20000650:	f641 2318 	movw	r3, #6680	; 0x1a18
20000654:	f2c2 0300 	movt	r3, #8192	; 0x2000
20000658:	687a      	ldr	r2, [r7, #4]
2000065a:	601a      	str	r2, [r3, #0]
    g_FrequencyPCLK1 = standby_clk;
2000065c:	f641 231c 	movw	r3, #6684	; 0x1a1c
20000660:	f2c2 0300 	movt	r3, #8192	; 0x2000
20000664:	687a      	ldr	r2, [r7, #4]
20000666:	601a      	str	r2, [r3, #0]
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
20000668:	f641 2320 	movw	r3, #6688	; 0x1a20
2000066c:	f2c2 0300 	movt	r3, #8192	; 0x2000
20000670:	f646 6270 	movw	r2, #28272	; 0x6e70
20000674:	f2c0 12a7 	movt	r2, #423	; 0x1a7
20000678:	601a      	str	r2, [r3, #0]
    g_FrequencyFIC0 = standby_clk;
2000067a:	f641 2324 	movw	r3, #6692	; 0x1a24
2000067e:	f2c2 0300 	movt	r3, #8192	; 0x2000
20000682:	687a      	ldr	r2, [r7, #4]
20000684:	601a      	str	r2, [r3, #0]
    g_FrequencyFIC1 = standby_clk;
20000686:	f641 2328 	movw	r3, #6696	; 0x1a28
2000068a:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000068e:	687a      	ldr	r2, [r7, #4]
20000690:	601a      	str	r2, [r3, #0]
    g_FrequencyFIC64 = standby_clk;
20000692:	f641 232c 	movw	r3, #6700	; 0x1a2c
20000696:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000069a:	687a      	ldr	r2, [r7, #4]
2000069c:	601a      	str	r2, [r3, #0]
}
2000069e:	f107 070c 	add.w	r7, r7, #12
200006a2:	46bd      	mov	sp, r7
200006a4:	bc80      	pop	{r7}
200006a6:	4770      	bx	lr

200006a8 <copy_cfg16_to_regs>:
(
    volatile uint32_t * p_regs,
    const uint16_t * p_cfg,
    uint32_t nb_16bit_words
)
{
200006a8:	b480      	push	{r7}
200006aa:	b087      	sub	sp, #28
200006ac:	af00      	add	r7, sp, #0
200006ae:	60f8      	str	r0, [r7, #12]
200006b0:	60b9      	str	r1, [r7, #8]
200006b2:	607a      	str	r2, [r7, #4]
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
200006b4:	f04f 0300 	mov.w	r3, #0
200006b8:	617b      	str	r3, [r7, #20]
200006ba:	e00f      	b.n	200006dc <copy_cfg16_to_regs+0x34>
    {
        p_regs[inc] = p_cfg[inc];
200006bc:	697b      	ldr	r3, [r7, #20]
200006be:	ea4f 0283 	mov.w	r2, r3, lsl #2
200006c2:	68fb      	ldr	r3, [r7, #12]
200006c4:	4413      	add	r3, r2
200006c6:	697a      	ldr	r2, [r7, #20]
200006c8:	ea4f 0142 	mov.w	r1, r2, lsl #1
200006cc:	68ba      	ldr	r2, [r7, #8]
200006ce:	440a      	add	r2, r1
200006d0:	8812      	ldrh	r2, [r2, #0]
200006d2:	601a      	str	r2, [r3, #0]
    uint32_t nb_16bit_words
)
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
200006d4:	697b      	ldr	r3, [r7, #20]
200006d6:	f103 0301 	add.w	r3, r3, #1
200006da:	617b      	str	r3, [r7, #20]
200006dc:	697a      	ldr	r2, [r7, #20]
200006de:	687b      	ldr	r3, [r7, #4]
200006e0:	429a      	cmp	r2, r3
200006e2:	d3eb      	bcc.n	200006bc <copy_cfg16_to_regs+0x14>
    {
        p_regs[inc] = p_cfg[inc];
    }
}
200006e4:	f107 071c 	add.w	r7, r7, #28
200006e8:	46bd      	mov	sp, r7
200006ea:	bc80      	pop	{r7}
200006ec:	4770      	bx	lr
200006ee:	bf00      	nop

200006f0 <config_ddr_subsys>:
static void config_ddr_subsys
(
    const ddr_subsys_cfg_t * p_ddr_subsys_cfg,
    DDRCore_TypeDef * p_ddr_subsys_regs
)
{
200006f0:	b580      	push	{r7, lr}
200006f2:	b084      	sub	sp, #16
200006f4:	af00      	add	r7, sp, #0
200006f6:	6078      	str	r0, [r7, #4]
200006f8:	6039      	str	r1, [r7, #0]
    const uint16_t * p_cfg;
    
    /*--------------------------------------------------------------------------
     * Configure DDR controller part of the MDDR subsystem.
     */
    p_cfg = &p_ddr_subsys_cfg->ddrc.DYN_SOFT_RESET_CR;
200006fa:	687b      	ldr	r3, [r7, #4]
200006fc:	60fb      	str	r3, [r7, #12]
    p_regs = &p_ddr_subsys_regs->ddrc.DYN_SOFT_RESET_CR;
200006fe:	683b      	ldr	r3, [r7, #0]
20000700:	60bb      	str	r3, [r7, #8]

    copy_cfg16_to_regs(p_regs, p_cfg, NB_OF_DDRC_REGS_TO_CONFIG);
20000702:	68b8      	ldr	r0, [r7, #8]
20000704:	68f9      	ldr	r1, [r7, #12]
20000706:	f04f 0239 	mov.w	r2, #57	; 0x39
2000070a:	f7ff ffcd 	bl	200006a8 <copy_cfg16_to_regs>
    
    /*--------------------------------------------------------------------------
     * Configure DDR PHY.
     */
    p_cfg = &p_ddr_subsys_cfg->phy.LOOPBACK_TEST_CR;
2000070e:	687b      	ldr	r3, [r7, #4]
20000710:	f103 0372 	add.w	r3, r3, #114	; 0x72
20000714:	60fb      	str	r3, [r7, #12]
    p_regs = &p_ddr_subsys_regs->phy.LOOPBACK_TEST_CR;
20000716:	683b      	ldr	r3, [r7, #0]
20000718:	f503 7307 	add.w	r3, r3, #540	; 0x21c
2000071c:	60bb      	str	r3, [r7, #8]

    copy_cfg16_to_regs(p_regs, p_cfg, NB_OF_DDR_PHY_REGS_TO_CONFIG);
2000071e:	68b8      	ldr	r0, [r7, #8]
20000720:	68f9      	ldr	r1, [r7, #12]
20000722:	f04f 0241 	mov.w	r2, #65	; 0x41
20000726:	f7ff ffbf 	bl	200006a8 <copy_cfg16_to_regs>
    
    /*--------------------------------------------------------------------------
     * Configure DDR FIC.
     */
    p_ddr_subsys_regs->fic.NB_ADDR_CR = p_ddr_subsys_cfg->fic.NB_ADDR_CR;
2000072a:	687b      	ldr	r3, [r7, #4]
2000072c:	f8b3 30f4 	ldrh.w	r3, [r3, #244]	; 0xf4
20000730:	461a      	mov	r2, r3
20000732:	683b      	ldr	r3, [r7, #0]
20000734:	f8c3 2400 	str.w	r2, [r3, #1024]	; 0x400
    p_ddr_subsys_regs->fic.NBRWB_SIZE_CR = p_ddr_subsys_cfg->fic.NBRWB_SIZE_CR;
20000738:	687b      	ldr	r3, [r7, #4]
2000073a:	f8b3 30f6 	ldrh.w	r3, [r3, #246]	; 0xf6
2000073e:	461a      	mov	r2, r3
20000740:	683b      	ldr	r3, [r7, #0]
20000742:	f8c3 2404 	str.w	r2, [r3, #1028]	; 0x404
    p_ddr_subsys_regs->fic.WB_TIMEOUT_CR = p_ddr_subsys_cfg->fic.WB_TIMEOUT_CR;
20000746:	687b      	ldr	r3, [r7, #4]
20000748:	f8b3 30f8 	ldrh.w	r3, [r3, #248]	; 0xf8
2000074c:	461a      	mov	r2, r3
2000074e:	683b      	ldr	r3, [r7, #0]
20000750:	f8c3 2408 	str.w	r2, [r3, #1032]	; 0x408
    p_ddr_subsys_regs->fic.HPD_SW_RW_EN_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_EN_CR;
20000754:	687b      	ldr	r3, [r7, #4]
20000756:	f8b3 30fa 	ldrh.w	r3, [r3, #250]	; 0xfa
2000075a:	461a      	mov	r2, r3
2000075c:	683b      	ldr	r3, [r7, #0]
2000075e:	f8c3 240c 	str.w	r2, [r3, #1036]	; 0x40c
    p_ddr_subsys_regs->fic.HPD_SW_RW_INVAL_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_INVAL_CR;
20000762:	687b      	ldr	r3, [r7, #4]
20000764:	f8b3 30fc 	ldrh.w	r3, [r3, #252]	; 0xfc
20000768:	461a      	mov	r2, r3
2000076a:	683b      	ldr	r3, [r7, #0]
2000076c:	f8c3 2410 	str.w	r2, [r3, #1040]	; 0x410
    p_ddr_subsys_regs->fic.SW_WR_ERCLR_CR = p_ddr_subsys_cfg->fic.SW_WR_ERCLR_CR;
20000770:	687b      	ldr	r3, [r7, #4]
20000772:	f8b3 30fe 	ldrh.w	r3, [r3, #254]	; 0xfe
20000776:	461a      	mov	r2, r3
20000778:	683b      	ldr	r3, [r7, #0]
2000077a:	f8c3 2414 	str.w	r2, [r3, #1044]	; 0x414
    p_ddr_subsys_regs->fic.ERR_INT_ENABLE_CR = p_ddr_subsys_cfg->fic.ERR_INT_ENABLE_CR;
2000077e:	687b      	ldr	r3, [r7, #4]
20000780:	f8b3 3100 	ldrh.w	r3, [r3, #256]	; 0x100
20000784:	461a      	mov	r2, r3
20000786:	683b      	ldr	r3, [r7, #0]
20000788:	f8c3 2418 	str.w	r2, [r3, #1048]	; 0x418
    p_ddr_subsys_regs->fic.NUM_AHB_MASTERS_CR = p_ddr_subsys_cfg->fic.NUM_AHB_MASTERS_CR;
2000078c:	687b      	ldr	r3, [r7, #4]
2000078e:	f8b3 3102 	ldrh.w	r3, [r3, #258]	; 0x102
20000792:	461a      	mov	r2, r3
20000794:	683b      	ldr	r3, [r7, #0]
20000796:	f8c3 241c 	str.w	r2, [r3, #1052]	; 0x41c
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[0] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_1_CR;
2000079a:	687b      	ldr	r3, [r7, #4]
2000079c:	f8b3 3104 	ldrh.w	r3, [r3, #260]	; 0x104
200007a0:	461a      	mov	r2, r3
200007a2:	683b      	ldr	r3, [r7, #0]
200007a4:	f8c3 2440 	str.w	r2, [r3, #1088]	; 0x440
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[1] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_2_CR;
200007a8:	687b      	ldr	r3, [r7, #4]
200007aa:	f8b3 3106 	ldrh.w	r3, [r3, #262]	; 0x106
200007ae:	461a      	mov	r2, r3
200007b0:	683b      	ldr	r3, [r7, #0]
200007b2:	f8c3 2444 	str.w	r2, [r3, #1092]	; 0x444
    p_ddr_subsys_regs->fic.LOCK_TIMEOUT_EN_CR = p_ddr_subsys_cfg->fic.LOCK_TIMEOUT_EN_CR;
200007b6:	687b      	ldr	r3, [r7, #4]
200007b8:	f8b3 3108 	ldrh.w	r3, [r3, #264]	; 0x108
200007bc:	461a      	mov	r2, r3
200007be:	683b      	ldr	r3, [r7, #0]
200007c0:	f8c3 2448 	str.w	r2, [r3, #1096]	; 0x448

    /*--------------------------------------------------------------------------
     * Enable DDR.
     */
    p_ddr_subsys_regs->ddrc.DYN_SOFT_RESET_CR = 0x01u;
200007c4:	683b      	ldr	r3, [r7, #0]
200007c6:	f04f 0201 	mov.w	r2, #1
200007ca:	601a      	str	r2, [r3, #0]
    
    while(0x0000u == p_ddr_subsys_regs->ddrc.DDRC_SR)
200007cc:	683b      	ldr	r3, [r7, #0]
200007ce:	f8d3 30e4 	ldr.w	r3, [r3, #228]	; 0xe4
200007d2:	2b00      	cmp	r3, #0
200007d4:	d0fa      	beq.n	200007cc <config_ddr_subsys+0xdc>
    {
        ;
    }        
}
200007d6:	f107 0710 	add.w	r7, r7, #16
200007da:	46bd      	mov	sp, r7
200007dc:	bd80      	pop	{r7, pc}
200007de:	bf00      	nop

200007e0 <get_silicon_revision>:

/*------------------------------------------------------------------------------
  Retrieve silicon revision from system registers.
 */
static uint32_t get_silicon_revision(void)
{
200007e0:	b480      	push	{r7}
200007e2:	b083      	sub	sp, #12
200007e4:	af00      	add	r7, sp, #0
    uint32_t silicon_revision;
    uint32_t device_version;
    
    device_version = SYSREG->DEVICE_VERSION;
200007e6:	f248 0300 	movw	r3, #32768	; 0x8000
200007ea:	f2c4 0303 	movt	r3, #16387	; 0x4003
200007ee:	f8d3 314c 	ldr.w	r3, [r3, #332]	; 0x14c
200007f2:	607b      	str	r3, [r7, #4]
    switch(device_version)
200007f4:	687a      	ldr	r2, [r7, #4]
200007f6:	f64f 0302 	movw	r3, #63490	; 0xf802
200007fa:	429a      	cmp	r2, r3
200007fc:	d006      	beq.n	2000080c <get_silicon_revision+0x2c>
200007fe:	f64f 0302 	movw	r3, #63490	; 0xf802
20000802:	f2c0 0301 	movt	r3, #1
20000806:	429a      	cmp	r2, r3
20000808:	d004      	beq.n	20000814 <get_silicon_revision+0x34>
2000080a:	e007      	b.n	2000081c <get_silicon_revision+0x3c>
    {
        case 0x0000F802:
            silicon_revision = M2S050_REV_A_SILICON;
2000080c:	f04f 0301 	mov.w	r3, #1
20000810:	603b      	str	r3, [r7, #0]
            break;
20000812:	e006      	b.n	20000822 <get_silicon_revision+0x42>
            
        case 0x0001F802:
            silicon_revision = M2S050_REV_B_SILICON;
20000814:	f04f 0302 	mov.w	r3, #2
20000818:	603b      	str	r3, [r7, #0]
            break;
2000081a:	e002      	b.n	20000822 <get_silicon_revision+0x42>
            
        default:
            silicon_revision = UNKNOWN_SILICON_REV;
2000081c:	f04f 0300 	mov.w	r3, #0
20000820:	603b      	str	r3, [r7, #0]
            break;
    }
    
    return silicon_revision;
20000822:	683b      	ldr	r3, [r7, #0]
}
20000824:	4618      	mov	r0, r3
20000826:	f107 070c 	add.w	r7, r7, #12
2000082a:	46bd      	mov	sp, r7
2000082c:	bc80      	pop	{r7}
2000082e:	4770      	bx	lr

20000830 <silicon_workarounds>:

/*------------------------------------------------------------------------------
  Workarounds for various silicon versions.
 */
static void silicon_workarounds(void)
{
20000830:	b580      	push	{r7, lr}
20000832:	b082      	sub	sp, #8
20000834:	af00      	add	r7, sp, #0
    uint32_t silicon_revision;
    
    silicon_revision = get_silicon_revision();
20000836:	f7ff ffd3 	bl	200007e0 <get_silicon_revision>
2000083a:	4603      	mov	r3, r0
2000083c:	607b      	str	r3, [r7, #4]
    
    switch(silicon_revision)
2000083e:	687b      	ldr	r3, [r7, #4]
20000840:	2b01      	cmp	r3, #1
20000842:	d101      	bne.n	20000848 <silicon_workarounds+0x18>
    {
        case M2S050_REV_A_SILICON:
            m2s050_rev_a_workarounds();
20000844:	f000 f804 	bl	20000850 <m2s050_rev_a_workarounds>
        case UNKNOWN_SILICON_REV:
            /* Fall through. */
        default:
            break;
    }
}
20000848:	f107 0708 	add.w	r7, r7, #8
2000084c:	46bd      	mov	sp, r7
2000084e:	bd80      	pop	{r7, pc}

20000850 <m2s050_rev_a_workarounds>:

/*------------------------------------------------------------------------------
  Silicon workarounds for M2S050 rev A.
 */
static void m2s050_rev_a_workarounds(void)
{
20000850:	b480      	push	{r7}
20000852:	af00      	add	r7, sp, #0
    /*--------------------------------------------------------------------------
     * Work around a couple of silicon issues:
     */
    /* DDR_CLK_EN <- 1 */
    SYSREG->MSSDDR_FACC1_CR |= (uint32_t)1 << DDR_CLK_EN_SHIFT;
20000854:	f248 0300 	movw	r3, #32768	; 0x8000
20000858:	f2c4 0303 	movt	r3, #16387	; 0x4003
2000085c:	f248 0200 	movw	r2, #32768	; 0x8000
20000860:	f2c4 0203 	movt	r2, #16387	; 0x4003
20000864:	f8d2 2098 	ldr.w	r2, [r2, #152]	; 0x98
20000868:	f442 7280 	orr.w	r2, r2, #256	; 0x100
2000086c:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98
    
    /* CONTROLLER_PLL_INIT <- 0 */
    SYSREG->MSSDDR_FACC1_CR = SYSREG->MSSDDR_FACC1_CR & ~CONTROLLER_PLL_INIT_MASK;
20000870:	f248 0300 	movw	r3, #32768	; 0x8000
20000874:	f2c4 0303 	movt	r3, #16387	; 0x4003
20000878:	f248 0200 	movw	r2, #32768	; 0x8000
2000087c:	f2c4 0203 	movt	r2, #16387	; 0x4003
20000880:	f8d2 2098 	ldr.w	r2, [r2, #152]	; 0x98
20000884:	f022 6280 	bic.w	r2, r2, #67108864	; 0x4000000
20000888:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98
}
2000088c:	46bd      	mov	sp, r7
2000088e:	bc80      	pop	{r7}
20000890:	4770      	bx	lr
20000892:	bf00      	nop

20000894 <g_m2s_mddr_addr>:
20000894:	0800 4002                                   ...@

20000898 <g_m2s_mddr_subsys_config>:
20000898:	0000 0000 27de 030f 0002 0000 0101 0999     .....'..........
200008a8:	0000 3333 ffff 8888 0888 0001 4242 0008     ..33........BB..
200008b8:	0528 0000 0000 0000 0ce0 0086 0235 0064     (...........5.d.
200008c8:	010f 0178 0033 1937 0010 0000 3300 0000     ..x.3.7......3..
200008d8:	0000 0406 0000 0200 0040 0012 0002 4000     ........@......@
200008e8:	80f8 0007 80f8 0007 0200 0400 0000 0005     ................
200008f8:	0003 0040 0000 0000 0000 0000 0309 0001     ..@.............
20000908:	0000 0000 0000 0080 0000 0000 0003 0000     ................
	...
20000920:	000b 0000 0000 0000 0000 0080 2004 0100     ............. ..
20000930:	0008 0000 0000 0000 0000 0000 0001 0000     ................
	...
20000948:	4050 0501 5014 0000 0000 0000 0000 0000     P@...P..........
	...
20000968:	0050 0501 5010 0000 0000 0000 0000 0000     P....P..........
20000978:	0000 0043 0000 0003 0001 0001 0000 0000     ..C.............
20000988:	0000 0001 0000 0000 0000 0000 0000 0000     ................
	...

Disassembly of section .text:

200009b0 <__do_global_dtors_aux>:
200009b0:	f641 2330 	movw	r3, #6704	; 0x1a30
200009b4:	f2c2 0300 	movt	r3, #8192	; 0x2000
200009b8:	781a      	ldrb	r2, [r3, #0]
200009ba:	b90a      	cbnz	r2, 200009c0 <__do_global_dtors_aux+0x10>
200009bc:	2001      	movs	r0, #1
200009be:	7018      	strb	r0, [r3, #0]
200009c0:	4770      	bx	lr
200009c2:	bf00      	nop

200009c4 <frame_dummy>:
200009c4:	f641 2010 	movw	r0, #6672	; 0x1a10
200009c8:	f2c2 0000 	movt	r0, #8192	; 0x2000
200009cc:	b508      	push	{r3, lr}
200009ce:	6803      	ldr	r3, [r0, #0]
200009d0:	b12b      	cbz	r3, 200009de <frame_dummy+0x1a>
200009d2:	f240 0300 	movw	r3, #0
200009d6:	f2c0 0300 	movt	r3, #0
200009da:	b103      	cbz	r3, 200009de <frame_dummy+0x1a>
200009dc:	4798      	blx	r3
200009de:	bd08      	pop	{r3, pc}

200009e0 <copy_image_to_ram>:
#define ENVM_DEMO_IMAGE_STORED_1 0x60008000
#define ENVM_DEMO_IMAGE_STORED_2 0x60012000
#define ENVM_DEMO_IMAGE_STORED_3 0x60016000

void copy_image_to_ram(int type)
{
200009e0:	b480      	push	{r7}
200009e2:	b087      	sub	sp, #28
200009e4:	af00      	add	r7, sp, #0
200009e6:	6078      	str	r0, [r7, #4]
    unsigned int ii=0;
200009e8:	f04f 0300 	mov.w	r3, #0
200009ec:	60fb      	str	r3, [r7, #12]
    unsigned long *exeDestAddr, *exeSrcAddr;

    switch(type)
200009ee:	687b      	ldr	r3, [r7, #4]
200009f0:	2b03      	cmp	r3, #3
200009f2:	f200 8096 	bhi.w	20000b22 <copy_image_to_ram+0x142>
200009f6:	a201      	add	r2, pc, #4	; (adr r2, 200009fc <copy_image_to_ram+0x1c>)
200009f8:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
200009fc:	20000a0d 	.word	0x20000a0d
20000a00:	20000a51 	.word	0x20000a51
20000a04:	20000a99 	.word	0x20000a99
20000a08:	20000add 	.word	0x20000add
    {
		case ESRAM0_REMAP:
		{
			exeDestAddr = (unsigned long *)ESRAM0_REMAP_BASE_ADDR;
20000a0c:	f04f 5300 	mov.w	r3, #536870912	; 0x20000000
20000a10:	613b      	str	r3, [r7, #16]
			exeSrcAddr = (unsigned long *)ENVM_DEMO_IMAGE_STORED_0;
20000a12:	f244 0300 	movw	r3, #16384	; 0x4000
20000a16:	f2c6 0300 	movt	r3, #24576	; 0x6000
20000a1a:	617b      	str	r3, [r7, #20]
			/* 16 K B = 16 KB /4 ptr increments by 4bytes*/
			for (ii=0; ii<4096; ii++ )
20000a1c:	f04f 0300 	mov.w	r3, #0
20000a20:	60fb      	str	r3, [r7, #12]
20000a22:	e00f      	b.n	20000a44 <copy_image_to_ram+0x64>
			{
				*exeDestAddr++ = *exeSrcAddr++;
20000a24:	697b      	ldr	r3, [r7, #20]
20000a26:	681a      	ldr	r2, [r3, #0]
20000a28:	693b      	ldr	r3, [r7, #16]
20000a2a:	601a      	str	r2, [r3, #0]
20000a2c:	693b      	ldr	r3, [r7, #16]
20000a2e:	f103 0304 	add.w	r3, r3, #4
20000a32:	613b      	str	r3, [r7, #16]
20000a34:	697b      	ldr	r3, [r7, #20]
20000a36:	f103 0304 	add.w	r3, r3, #4
20000a3a:	617b      	str	r3, [r7, #20]
		case ESRAM0_REMAP:
		{
			exeDestAddr = (unsigned long *)ESRAM0_REMAP_BASE_ADDR;
			exeSrcAddr = (unsigned long *)ENVM_DEMO_IMAGE_STORED_0;
			/* 16 K B = 16 KB /4 ptr increments by 4bytes*/
			for (ii=0; ii<4096; ii++ )
20000a3c:	68fb      	ldr	r3, [r7, #12]
20000a3e:	f103 0301 	add.w	r3, r3, #1
20000a42:	60fb      	str	r3, [r7, #12]
20000a44:	68fa      	ldr	r2, [r7, #12]
20000a46:	f640 73ff 	movw	r3, #4095	; 0xfff
20000a4a:	429a      	cmp	r2, r3
20000a4c:	d9ea      	bls.n	20000a24 <copy_image_to_ram+0x44>
			{
				*exeDestAddr++ = *exeSrcAddr++;
			}
		}
		break;
20000a4e:	e068      	b.n	20000b22 <copy_image_to_ram+0x142>
		case ESRAM1_REMAP:
		{
			exeDestAddr = (unsigned long *)ESRAM1_REMAP_BASE_ADDR;
20000a50:	f248 0300 	movw	r3, #32768	; 0x8000
20000a54:	f2c2 0300 	movt	r3, #8192	; 0x2000
20000a58:	613b      	str	r3, [r7, #16]
			exeSrcAddr = (unsigned long *)ENVM_DEMO_IMAGE_STORED_1;
20000a5a:	f248 0300 	movw	r3, #32768	; 0x8000
20000a5e:	f2c6 0300 	movt	r3, #24576	; 0x6000
20000a62:	617b      	str	r3, [r7, #20]
			/* 16 K B = 16 KB /4 ptr increments by 4bytes*/
			for (ii=0; ii<4096; ii++ )
20000a64:	f04f 0300 	mov.w	r3, #0
20000a68:	60fb      	str	r3, [r7, #12]
20000a6a:	e00f      	b.n	20000a8c <copy_image_to_ram+0xac>
			{
				*exeDestAddr++ = *exeSrcAddr++;
20000a6c:	697b      	ldr	r3, [r7, #20]
20000a6e:	681a      	ldr	r2, [r3, #0]
20000a70:	693b      	ldr	r3, [r7, #16]
20000a72:	601a      	str	r2, [r3, #0]
20000a74:	693b      	ldr	r3, [r7, #16]
20000a76:	f103 0304 	add.w	r3, r3, #4
20000a7a:	613b      	str	r3, [r7, #16]
20000a7c:	697b      	ldr	r3, [r7, #20]
20000a7e:	f103 0304 	add.w	r3, r3, #4
20000a82:	617b      	str	r3, [r7, #20]
		case ESRAM1_REMAP:
		{
			exeDestAddr = (unsigned long *)ESRAM1_REMAP_BASE_ADDR;
			exeSrcAddr = (unsigned long *)ENVM_DEMO_IMAGE_STORED_1;
			/* 16 K B = 16 KB /4 ptr increments by 4bytes*/
			for (ii=0; ii<4096; ii++ )
20000a84:	68fb      	ldr	r3, [r7, #12]
20000a86:	f103 0301 	add.w	r3, r3, #1
20000a8a:	60fb      	str	r3, [r7, #12]
20000a8c:	68fa      	ldr	r2, [r7, #12]
20000a8e:	f640 73ff 	movw	r3, #4095	; 0xfff
20000a92:	429a      	cmp	r2, r3
20000a94:	d9ea      	bls.n	20000a6c <copy_image_to_ram+0x8c>
			{
				*exeDestAddr++ = *exeSrcAddr++;
			}
		}
		break;
20000a96:	e044      	b.n	20000b22 <copy_image_to_ram+0x142>
		case ESRAM2_REMAP:
		{
			exeDestAddr = (unsigned long *)ESRAM0_REMAP_BASE_ADDR;
20000a98:	f04f 5300 	mov.w	r3, #536870912	; 0x20000000
20000a9c:	613b      	str	r3, [r7, #16]
			exeSrcAddr = (unsigned long *)ENVM_DEMO_IMAGE_STORED_2;
20000a9e:	f242 0300 	movw	r3, #8192	; 0x2000
20000aa2:	f2c6 0301 	movt	r3, #24577	; 0x6001
20000aa6:	617b      	str	r3, [r7, #20]
			/* 16 K B = 16 KB /4 ptr increments by 4bytes*/
			for (ii=0; ii<4096; ii++ )
20000aa8:	f04f 0300 	mov.w	r3, #0
20000aac:	60fb      	str	r3, [r7, #12]
20000aae:	e00f      	b.n	20000ad0 <copy_image_to_ram+0xf0>
			{
				*exeDestAddr++ = *exeSrcAddr++;
20000ab0:	697b      	ldr	r3, [r7, #20]
20000ab2:	681a      	ldr	r2, [r3, #0]
20000ab4:	693b      	ldr	r3, [r7, #16]
20000ab6:	601a      	str	r2, [r3, #0]
20000ab8:	693b      	ldr	r3, [r7, #16]
20000aba:	f103 0304 	add.w	r3, r3, #4
20000abe:	613b      	str	r3, [r7, #16]
20000ac0:	697b      	ldr	r3, [r7, #20]
20000ac2:	f103 0304 	add.w	r3, r3, #4
20000ac6:	617b      	str	r3, [r7, #20]
		case ESRAM2_REMAP:
		{
			exeDestAddr = (unsigned long *)ESRAM0_REMAP_BASE_ADDR;
			exeSrcAddr = (unsigned long *)ENVM_DEMO_IMAGE_STORED_2;
			/* 16 K B = 16 KB /4 ptr increments by 4bytes*/
			for (ii=0; ii<4096; ii++ )
20000ac8:	68fb      	ldr	r3, [r7, #12]
20000aca:	f103 0301 	add.w	r3, r3, #1
20000ace:	60fb      	str	r3, [r7, #12]
20000ad0:	68fa      	ldr	r2, [r7, #12]
20000ad2:	f640 73ff 	movw	r3, #4095	; 0xfff
20000ad6:	429a      	cmp	r2, r3
20000ad8:	d9ea      	bls.n	20000ab0 <copy_image_to_ram+0xd0>
			{
				*exeDestAddr++ = *exeSrcAddr++;
			}
		}
		break;
20000ada:	e022      	b.n	20000b22 <copy_image_to_ram+0x142>
		case ESRAM3_REMAP:
		{
			exeDestAddr = (unsigned long *)ESRAM1_REMAP_BASE_ADDR;
20000adc:	f248 0300 	movw	r3, #32768	; 0x8000
20000ae0:	f2c2 0300 	movt	r3, #8192	; 0x2000
20000ae4:	613b      	str	r3, [r7, #16]
			exeSrcAddr = (unsigned long *)ENVM_DEMO_IMAGE_STORED_3;
20000ae6:	f246 0300 	movw	r3, #24576	; 0x6000
20000aea:	f2c6 0301 	movt	r3, #24577	; 0x6001
20000aee:	617b      	str	r3, [r7, #20]
			/* 16 K B = 16 KB /4 ptr increments by 4bytes*/
			for (ii=0; ii<4096; ii++ )
20000af0:	f04f 0300 	mov.w	r3, #0
20000af4:	60fb      	str	r3, [r7, #12]
20000af6:	e00f      	b.n	20000b18 <copy_image_to_ram+0x138>
			{
				*exeDestAddr++ = *exeSrcAddr++;
20000af8:	697b      	ldr	r3, [r7, #20]
20000afa:	681a      	ldr	r2, [r3, #0]
20000afc:	693b      	ldr	r3, [r7, #16]
20000afe:	601a      	str	r2, [r3, #0]
20000b00:	693b      	ldr	r3, [r7, #16]
20000b02:	f103 0304 	add.w	r3, r3, #4
20000b06:	613b      	str	r3, [r7, #16]
20000b08:	697b      	ldr	r3, [r7, #20]
20000b0a:	f103 0304 	add.w	r3, r3, #4
20000b0e:	617b      	str	r3, [r7, #20]
		case ESRAM3_REMAP:
		{
			exeDestAddr = (unsigned long *)ESRAM1_REMAP_BASE_ADDR;
			exeSrcAddr = (unsigned long *)ENVM_DEMO_IMAGE_STORED_3;
			/* 16 K B = 16 KB /4 ptr increments by 4bytes*/
			for (ii=0; ii<4096; ii++ )
20000b10:	68fb      	ldr	r3, [r7, #12]
20000b12:	f103 0301 	add.w	r3, r3, #1
20000b16:	60fb      	str	r3, [r7, #12]
20000b18:	68fa      	ldr	r2, [r7, #12]
20000b1a:	f640 73ff 	movw	r3, #4095	; 0xfff
20000b1e:	429a      	cmp	r2, r3
20000b20:	d9ea      	bls.n	20000af8 <copy_image_to_ram+0x118>
		}
		break;
		default:
			break;
    }
}
20000b22:	f107 071c 	add.w	r7, r7, #28
20000b26:	46bd      	mov	sp, r7
20000b28:	bc80      	pop	{r7}
20000b2a:	4770      	bx	lr

20000b2c <UART_Polled_Rx>:
(
    mss_uart_instance_t * this_uart,
    uint8_t * rx_buff,
    size_t buff_size
)
{
20000b2c:	b480      	push	{r7}
20000b2e:	b087      	sub	sp, #28
20000b30:	af00      	add	r7, sp, #0
20000b32:	60f8      	str	r0, [r7, #12]
20000b34:	60b9      	str	r1, [r7, #8]
20000b36:	607a      	str	r2, [r7, #4]
    size_t rx_size = 0U;
20000b38:	f04f 0300 	mov.w	r3, #0
20000b3c:	617b      	str	r3, [r7, #20]

    while( rx_size < buff_size )
20000b3e:	e016      	b.n	20000b6e <UART_Polled_Rx+0x42>
    {
       while ( ((this_uart->hw_reg->LSR) & 0x1) != 0U  )
       {
           rx_buff[rx_size] = this_uart->hw_reg->RBR;
20000b40:	68ba      	ldr	r2, [r7, #8]
20000b42:	697b      	ldr	r3, [r7, #20]
20000b44:	4413      	add	r3, r2
20000b46:	68fa      	ldr	r2, [r7, #12]
20000b48:	6812      	ldr	r2, [r2, #0]
20000b4a:	7812      	ldrb	r2, [r2, #0]
20000b4c:	b2d2      	uxtb	r2, r2
20000b4e:	701a      	strb	r2, [r3, #0]
           ++rx_size;
20000b50:	697b      	ldr	r3, [r7, #20]
20000b52:	f103 0301 	add.w	r3, r3, #1
20000b56:	617b      	str	r3, [r7, #20]
20000b58:	e000      	b.n	20000b5c <UART_Polled_Rx+0x30>
{
    size_t rx_size = 0U;

    while( rx_size < buff_size )
    {
       while ( ((this_uart->hw_reg->LSR) & 0x1) != 0U  )
20000b5a:	bf00      	nop
20000b5c:	68fb      	ldr	r3, [r7, #12]
20000b5e:	681b      	ldr	r3, [r3, #0]
20000b60:	7d1b      	ldrb	r3, [r3, #20]
20000b62:	b2db      	uxtb	r3, r3
20000b64:	f003 0301 	and.w	r3, r3, #1
20000b68:	b2db      	uxtb	r3, r3
20000b6a:	2b00      	cmp	r3, #0
20000b6c:	d1e8      	bne.n	20000b40 <UART_Polled_Rx+0x14>
    size_t buff_size
)
{
    size_t rx_size = 0U;

    while( rx_size < buff_size )
20000b6e:	697a      	ldr	r2, [r7, #20]
20000b70:	687b      	ldr	r3, [r7, #4]
20000b72:	429a      	cmp	r2, r3
20000b74:	d3f1      	bcc.n	20000b5a <UART_Polled_Rx+0x2e>
           rx_buff[rx_size] = this_uart->hw_reg->RBR;
           ++rx_size;
       }
    }

    return rx_size;
20000b76:	697b      	ldr	r3, [r7, #20]
}
20000b78:	4618      	mov	r0, r3
20000b7a:	f107 071c 	add.w	r7, r7, #28
20000b7e:	46bd      	mov	sp, r7
20000b80:	bc80      	pop	{r7}
20000b82:	4770      	bx	lr

20000b84 <main>:

/****************************************************************/
/* Entry to Main form user bootcode                             */
/****************************************************************/
int main()
{
20000b84:	b580      	push	{r7, lr}
20000b86:	b082      	sub	sp, #8
20000b88:	af00      	add	r7, sp, #0
    uint8_t rx_buff[1];
	/* Initialization all necessary hardware components */
    MSS_UART_init( &g_mss_uart1,MSS_UART_57600_BAUD,MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT );
20000b8a:	f641 2034 	movw	r0, #6708	; 0x1a34
20000b8e:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000b92:	f44f 4161 	mov.w	r1, #57600	; 0xe100
20000b96:	f04f 0203 	mov.w	r2, #3
20000b9a:	f000 f9cb 	bl	20000f34 <MSS_UART_init>
    MSS_UART_polled_tx(&g_mss_uart1,(uint8_t *)"#Welcome to SmartFusion2 - Running HexFile0#\n\r",sizeof("#Welcome to SmartFusion2 - Running HexFile0#\n\r"));
20000b9e:	f641 2034 	movw	r0, #6708	; 0x1a34
20000ba2:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000ba6:	f641 0170 	movw	r1, #6256	; 0x1870
20000baa:	f2c2 0100 	movt	r1, #8192	; 0x2000
20000bae:	f04f 022f 	mov.w	r2, #47	; 0x2f
20000bb2:	f000 fa01 	bl	20000fb8 <MSS_UART_polled_tx>

  	while(1)
  	{
  	    MSS_UART_polled_tx(&g_mss_uart1,(uint8_t *)"Select the below option\n\r",sizeof("Select the below option\n\r"));
20000bb6:	f641 2034 	movw	r0, #6708	; 0x1a34
20000bba:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000bbe:	f641 01a0 	movw	r1, #6304	; 0x18a0
20000bc2:	f2c2 0100 	movt	r1, #8192	; 0x2000
20000bc6:	f04f 021a 	mov.w	r2, #26
20000bca:	f000 f9f5 	bl	20000fb8 <MSS_UART_polled_tx>
  	    MSS_UART_polled_tx(&g_mss_uart1,(uint8_t *)"1. Run Hex File1 from eSRAM\n\r",sizeof("1. Run Hex File1 from eSRAM\n\r"));
20000bce:	f641 2034 	movw	r0, #6708	; 0x1a34
20000bd2:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000bd6:	f641 01bc 	movw	r1, #6332	; 0x18bc
20000bda:	f2c2 0100 	movt	r1, #8192	; 0x2000
20000bde:	f04f 021e 	mov.w	r2, #30
20000be2:	f000 f9e9 	bl	20000fb8 <MSS_UART_polled_tx>
  	    MSS_UART_polled_tx(&g_mss_uart1,(uint8_t *)"2. Run Hex File2 from eSRAM\n\r",sizeof("2. Run Hex File2 from eSRAM\n\r"));
20000be6:	f641 2034 	movw	r0, #6708	; 0x1a34
20000bea:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000bee:	f641 01dc 	movw	r1, #6364	; 0x18dc
20000bf2:	f2c2 0100 	movt	r1, #8192	; 0x2000
20000bf6:	f04f 021e 	mov.w	r2, #30
20000bfa:	f000 f9dd 	bl	20000fb8 <MSS_UART_polled_tx>
  	    MSS_UART_polled_tx(&g_mss_uart1,(uint8_t *)"3. Run Hex File3 from eSRAM\n\r",sizeof("3. Run Hex File3 from eSRAM\n\r"));
20000bfe:	f641 2034 	movw	r0, #6708	; 0x1a34
20000c02:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000c06:	f641 01fc 	movw	r1, #6396	; 0x18fc
20000c0a:	f2c2 0100 	movt	r1, #8192	; 0x2000
20000c0e:	f04f 021e 	mov.w	r2, #30
20000c12:	f000 f9d1 	bl	20000fb8 <MSS_UART_polled_tx>
  	    MSS_UART_polled_tx(&g_mss_uart1,(uint8_t *)"4. Run Hex File4 from eSRAM\n\r",sizeof("4. Run Hex File4 from eSRAM\n\r"));
20000c16:	f641 2034 	movw	r0, #6708	; 0x1a34
20000c1a:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000c1e:	f641 111c 	movw	r1, #6428	; 0x191c
20000c22:	f2c2 0100 	movt	r1, #8192	; 0x2000
20000c26:	f04f 021e 	mov.w	r2, #30
20000c2a:	f000 f9c5 	bl	20000fb8 <MSS_UART_polled_tx>
  	    MSS_UART_polled_tx(&g_mss_uart1,(uint8_t *)"5. Run Hex File5 from eNVM\n\r", sizeof("5. Run Hex File5 from eNVM\n\r"));
20000c2e:	f641 2034 	movw	r0, #6708	; 0x1a34
20000c32:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000c36:	f641 113c 	movw	r1, #6460	; 0x193c
20000c3a:	f2c2 0100 	movt	r1, #8192	; 0x2000
20000c3e:	f04f 021d 	mov.w	r2, #29
20000c42:	f000 f9b9 	bl	20000fb8 <MSS_UART_polled_tx>

  		while( (!(UART_Polled_Rx ( &g_mss_uart1, rx_buff, 1 ))) )
20000c46:	f107 0304 	add.w	r3, r7, #4
20000c4a:	f641 2034 	movw	r0, #6708	; 0x1a34
20000c4e:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000c52:	4619      	mov	r1, r3
20000c54:	f04f 0201 	mov.w	r2, #1
20000c58:	f7ff ff68 	bl	20000b2c <UART_Polled_Rx>
20000c5c:	4603      	mov	r3, r0
20000c5e:	2b00      	cmp	r3, #0
20000c60:	d0f1      	beq.n	20000c46 <main+0xc2>
			;

  		if(rx_buff[0] == '1')
20000c62:	793b      	ldrb	r3, [r7, #4]
20000c64:	2b31      	cmp	r3, #49	; 0x31
20000c66:	d112      	bne.n	20000c8e <main+0x10a>
	    {
	  	    MSS_UART_polled_tx(&g_mss_uart1,(uint8_t *)"\n\rRunning Hex File1\n\r",sizeof("\n\rRunning Hex File1\n\r"));
20000c68:	f641 2034 	movw	r0, #6708	; 0x1a34
20000c6c:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000c70:	f641 115c 	movw	r1, #6492	; 0x195c
20000c74:	f2c2 0100 	movt	r1, #8192	; 0x2000
20000c78:	f04f 0216 	mov.w	r2, #22
20000c7c:	f000 f99c 	bl	20000fb8 <MSS_UART_polled_tx>
	    	copy_image_to_ram(ESRAM0_REMAP);
20000c80:	f04f 0000 	mov.w	r0, #0
20000c84:	f7ff feac 	bl	200009e0 <copy_image_to_ram>
	    	remap_user_code_eSRAM_0();
20000c88:	f000 f894 	bl	20000db4 <remap_user_code_eSRAM_0>
	    }
	    else
	    {
	  	    MSS_UART_polled_tx(&g_mss_uart1,(uint8_t *)"Incorrect option\n\r",sizeof("Incorrect option\n\r"));
	    }
  	}
20000c8c:	e793      	b.n	20000bb6 <main+0x32>
	    {
	  	    MSS_UART_polled_tx(&g_mss_uart1,(uint8_t *)"\n\rRunning Hex File1\n\r",sizeof("\n\rRunning Hex File1\n\r"));
	    	copy_image_to_ram(ESRAM0_REMAP);
	    	remap_user_code_eSRAM_0();
	    }
	    else if(rx_buff[0] == '2')
20000c8e:	793b      	ldrb	r3, [r7, #4]
20000c90:	2b32      	cmp	r3, #50	; 0x32
20000c92:	d112      	bne.n	20000cba <main+0x136>
	    {
	    	MSS_UART_polled_tx(&g_mss_uart1,(uint8_t *)"\n\rRunning Hex File2\n\r",sizeof("\n\rRunning Hex File2\n\r"));
20000c94:	f641 2034 	movw	r0, #6708	; 0x1a34
20000c98:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000c9c:	f641 1174 	movw	r1, #6516	; 0x1974
20000ca0:	f2c2 0100 	movt	r1, #8192	; 0x2000
20000ca4:	f04f 0216 	mov.w	r2, #22
20000ca8:	f000 f986 	bl	20000fb8 <MSS_UART_polled_tx>
	    	copy_image_to_ram(ESRAM1_REMAP);
20000cac:	f04f 0001 	mov.w	r0, #1
20000cb0:	f7ff fe96 	bl	200009e0 <copy_image_to_ram>
	    	remap_user_code_eSRAM_1();
20000cb4:	f000 f89e 	bl	20000df4 <remap_user_code_eSRAM_1>
	    }
	    else
	    {
	  	    MSS_UART_polled_tx(&g_mss_uart1,(uint8_t *)"Incorrect option\n\r",sizeof("Incorrect option\n\r"));
	    }
  	}
20000cb8:	e77d      	b.n	20000bb6 <main+0x32>
	    {
	    	MSS_UART_polled_tx(&g_mss_uart1,(uint8_t *)"\n\rRunning Hex File2\n\r",sizeof("\n\rRunning Hex File2\n\r"));
	    	copy_image_to_ram(ESRAM1_REMAP);
	    	remap_user_code_eSRAM_1();
	    }
	    else if(rx_buff[0] == '3')
20000cba:	793b      	ldrb	r3, [r7, #4]
20000cbc:	2b33      	cmp	r3, #51	; 0x33
20000cbe:	d112      	bne.n	20000ce6 <main+0x162>
	    {
	    	MSS_UART_polled_tx(&g_mss_uart1,(uint8_t *)"\n\rRunning Hex File3\n\r",sizeof("\n\rRunning Hex File3\n\r"));
20000cc0:	f641 2034 	movw	r0, #6708	; 0x1a34
20000cc4:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000cc8:	f641 118c 	movw	r1, #6540	; 0x198c
20000ccc:	f2c2 0100 	movt	r1, #8192	; 0x2000
20000cd0:	f04f 0216 	mov.w	r2, #22
20000cd4:	f000 f970 	bl	20000fb8 <MSS_UART_polled_tx>
	    	copy_image_to_ram(ESRAM2_REMAP);
20000cd8:	f04f 0002 	mov.w	r0, #2
20000cdc:	f7ff fe80 	bl	200009e0 <copy_image_to_ram>
	    	remap_user_code_eSRAM_0();
20000ce0:	f000 f868 	bl	20000db4 <remap_user_code_eSRAM_0>
	    }
	    else
	    {
	  	    MSS_UART_polled_tx(&g_mss_uart1,(uint8_t *)"Incorrect option\n\r",sizeof("Incorrect option\n\r"));
	    }
  	}
20000ce4:	e767      	b.n	20000bb6 <main+0x32>
	    else if(rx_buff[0] == '3')
	    {
	    	MSS_UART_polled_tx(&g_mss_uart1,(uint8_t *)"\n\rRunning Hex File3\n\r",sizeof("\n\rRunning Hex File3\n\r"));
	    	copy_image_to_ram(ESRAM2_REMAP);
	    	remap_user_code_eSRAM_0();
	    }else if(rx_buff[0] == '4')
20000ce6:	793b      	ldrb	r3, [r7, #4]
20000ce8:	2b34      	cmp	r3, #52	; 0x34
20000cea:	d112      	bne.n	20000d12 <main+0x18e>
	    {
	    	MSS_UART_polled_tx(&g_mss_uart1,(uint8_t *)"\n\rRunning Hex File4\n\r",sizeof("\n\rRunning Hex File4\n\r"));
20000cec:	f641 2034 	movw	r0, #6708	; 0x1a34
20000cf0:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000cf4:	f641 11a4 	movw	r1, #6564	; 0x19a4
20000cf8:	f2c2 0100 	movt	r1, #8192	; 0x2000
20000cfc:	f04f 0216 	mov.w	r2, #22
20000d00:	f000 f95a 	bl	20000fb8 <MSS_UART_polled_tx>
	        copy_image_to_ram(ESRAM3_REMAP);
20000d04:	f04f 0003 	mov.w	r0, #3
20000d08:	f7ff fe6a 	bl	200009e0 <copy_image_to_ram>
	    	remap_user_code_eSRAM_1();
20000d0c:	f000 f872 	bl	20000df4 <remap_user_code_eSRAM_1>
	    }
	    else
	    {
	  	    MSS_UART_polled_tx(&g_mss_uart1,(uint8_t *)"Incorrect option\n\r",sizeof("Incorrect option\n\r"));
	    }
  	}
20000d10:	e751      	b.n	20000bb6 <main+0x32>
	    {
	    	MSS_UART_polled_tx(&g_mss_uart1,(uint8_t *)"\n\rRunning Hex File4\n\r",sizeof("\n\rRunning Hex File4\n\r"));
	        copy_image_to_ram(ESRAM3_REMAP);
	    	remap_user_code_eSRAM_1();
	    }
	    else if(rx_buff[0] == '5')
20000d12:	793b      	ldrb	r3, [r7, #4]
20000d14:	2b35      	cmp	r3, #53	; 0x35
20000d16:	d10e      	bne.n	20000d36 <main+0x1b2>
	    {
	  	    MSS_UART_polled_tx(&g_mss_uart1,(uint8_t *)"\n\rRunning Hex File5\n\r",sizeof("\n\rRunning Hex File5\n\r"));
20000d18:	f641 2034 	movw	r0, #6708	; 0x1a34
20000d1c:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000d20:	f641 11bc 	movw	r1, #6588	; 0x19bc
20000d24:	f2c2 0100 	movt	r1, #8192	; 0x2000
20000d28:	f04f 0216 	mov.w	r2, #22
20000d2c:	f000 f944 	bl	20000fb8 <MSS_UART_polled_tx>
	    	remap_user_code_eNVM_128KB();
20000d30:	f000 f80e 	bl	20000d50 <remap_user_code_eNVM_128KB>
	    }
	    else
	    {
	  	    MSS_UART_polled_tx(&g_mss_uart1,(uint8_t *)"Incorrect option\n\r",sizeof("Incorrect option\n\r"));
	    }
  	}
20000d34:	e73f      	b.n	20000bb6 <main+0x32>
	  	    MSS_UART_polled_tx(&g_mss_uart1,(uint8_t *)"\n\rRunning Hex File5\n\r",sizeof("\n\rRunning Hex File5\n\r"));
	    	remap_user_code_eNVM_128KB();
	    }
	    else
	    {
	  	    MSS_UART_polled_tx(&g_mss_uart1,(uint8_t *)"Incorrect option\n\r",sizeof("Incorrect option\n\r"));
20000d36:	f641 2034 	movw	r0, #6708	; 0x1a34
20000d3a:	f2c2 0000 	movt	r0, #8192	; 0x2000
20000d3e:	f641 11d4 	movw	r1, #6612	; 0x19d4
20000d42:	f2c2 0100 	movt	r1, #8192	; 0x2000
20000d46:	f04f 0213 	mov.w	r2, #19
20000d4a:	f000 f935 	bl	20000fb8 <MSS_UART_polled_tx>
	    }
  	}
20000d4e:	e732      	b.n	20000bb6 <main+0x32>

20000d50 <remap_user_code_eNVM_128KB>:

    return 0;
}

void remap_user_code_eNVM_128KB(void)
{
20000d50:	b580      	push	{r7, lr}
20000d52:	b082      	sub	sp, #8
20000d54:	af00      	add	r7, sp, #0
	int * address = (int *)0x00000004; 		//pointer to reset handler of application
20000d56:	f04f 0304 	mov.w	r3, #4
20000d5a:	603b      	str	r3, [r7, #0]
    __set_MSP(*(int*)0x00000000); 			//set the stack pointer to that of the application
20000d5c:	f04f 0300 	mov.w	r3, #0
20000d60:	681b      	ldr	r3, [r3, #0]
20000d62:	607b      	str	r3, [r7, #4]

    \param [in]    topOfMainStack  Main Stack Pointer value to set
 */
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
20000d64:	687b      	ldr	r3, [r7, #4]
20000d66:	f383 8808 	msr	MSP, r3
    SYSREG->ENVM_CR &= 0xFFFFFFF0;
20000d6a:	f248 0300 	movw	r3, #32768	; 0x8000
20000d6e:	f2c4 0303 	movt	r3, #16387	; 0x4003
20000d72:	f248 0200 	movw	r2, #32768	; 0x8000
20000d76:	f2c4 0203 	movt	r2, #16387	; 0x4003
20000d7a:	68d2      	ldr	r2, [r2, #12]
20000d7c:	f022 020f 	bic.w	r2, r2, #15
20000d80:	60da      	str	r2, [r3, #12]
    SYSREG->ENVM_CR |= 0x10;
20000d82:	f248 0300 	movw	r3, #32768	; 0x8000
20000d86:	f2c4 0303 	movt	r3, #16387	; 0x4003
20000d8a:	f248 0200 	movw	r2, #32768	; 0x8000
20000d8e:	f2c4 0203 	movt	r2, #16387	; 0x4003
20000d92:	68d2      	ldr	r2, [r2, #12]
20000d94:	f042 0210 	orr.w	r2, r2, #16
20000d98:	60da      	str	r2, [r3, #12]
    SYSREG->ENVM_REMAP_BASE_CR = 0x20001;
20000d9a:	f248 0300 	movw	r3, #32768	; 0x8000
20000d9e:	f2c4 0303 	movt	r3, #16387	; 0x4003
20000da2:	f240 0201 	movw	r2, #1
20000da6:	f2c0 0202 	movt	r2, #2
20000daa:	611a      	str	r2, [r3, #16]
    ((void (*)())(*address))(); 				// pointer recast as function pointer and the dereferenced/called
20000dac:	683b      	ldr	r3, [r7, #0]
20000dae:	681b      	ldr	r3, [r3, #0]
20000db0:	4798      	blx	r3
    while(1)
    {
    };						    //This instruction never executed
20000db2:	e7fe      	b.n	20000db2 <remap_user_code_eNVM_128KB+0x62>

20000db4 <remap_user_code_eSRAM_0>:
}

void remap_user_code_eSRAM_0(void)
{
20000db4:	b580      	push	{r7, lr}
20000db6:	b082      	sub	sp, #8
20000db8:	af00      	add	r7, sp, #0
   int * address = (int *)0x20000004; 		//pointer to reset handler of application
20000dba:	f240 0304 	movw	r3, #4
20000dbe:	f2c2 0300 	movt	r3, #8192	; 0x2000
20000dc2:	603b      	str	r3, [r7, #0]
   __set_MSP(*(int*)0x20000000); 			//set the stack pointer to that of the application
20000dc4:	f04f 5300 	mov.w	r3, #536870912	; 0x20000000
20000dc8:	681b      	ldr	r3, [r3, #0]
20000dca:	607b      	str	r3, [r7, #4]
20000dcc:	687b      	ldr	r3, [r7, #4]
20000dce:	f383 8808 	msr	MSP, r3
   SYSREG->ESRAM_CR |= 0x1;
20000dd2:	f248 0300 	movw	r3, #32768	; 0x8000
20000dd6:	f2c4 0303 	movt	r3, #16387	; 0x4003
20000dda:	f248 0200 	movw	r2, #32768	; 0x8000
20000dde:	f2c4 0203 	movt	r2, #16387	; 0x4003
20000de2:	6812      	ldr	r2, [r2, #0]
20000de4:	f042 0201 	orr.w	r2, r2, #1
20000de8:	601a      	str	r2, [r3, #0]
   ((void (*)())(*address))(); 				// pointer recast as function pointer and the dereferenced/called
20000dea:	683b      	ldr	r3, [r7, #0]
20000dec:	681b      	ldr	r3, [r3, #0]
20000dee:	4798      	blx	r3
   while(1){ }; 						    //This instruction never executed
20000df0:	e7fe      	b.n	20000df0 <remap_user_code_eSRAM_0+0x3c>
20000df2:	bf00      	nop

20000df4 <remap_user_code_eSRAM_1>:
}


void remap_user_code_eSRAM_1()
{
20000df4:	b580      	push	{r7, lr}
20000df6:	b082      	sub	sp, #8
20000df8:	af00      	add	r7, sp, #0
    int * address = (int *)0x20008004; 		//pointer to reset handler of application
20000dfa:	f248 0304 	movw	r3, #32772	; 0x8004
20000dfe:	f2c2 0300 	movt	r3, #8192	; 0x2000
20000e02:	603b      	str	r3, [r7, #0]
   __set_MSP(*(int*)0x20008000); 			//set the stack pointer to that of the application
20000e04:	f248 0300 	movw	r3, #32768	; 0x8000
20000e08:	f2c2 0300 	movt	r3, #8192	; 0x2000
20000e0c:	681b      	ldr	r3, [r3, #0]
20000e0e:	607b      	str	r3, [r7, #4]
20000e10:	687b      	ldr	r3, [r7, #4]
20000e12:	f383 8808 	msr	MSP, r3
   SYSREG->ESRAM_CR |= 0x3;
20000e16:	f248 0300 	movw	r3, #32768	; 0x8000
20000e1a:	f2c4 0303 	movt	r3, #16387	; 0x4003
20000e1e:	f248 0200 	movw	r2, #32768	; 0x8000
20000e22:	f2c4 0203 	movt	r2, #16387	; 0x4003
20000e26:	6812      	ldr	r2, [r2, #0]
20000e28:	f042 0203 	orr.w	r2, r2, #3
20000e2c:	601a      	str	r2, [r3, #0]
   ((void (*)())(*address))(); 				// pointer recast as function pointer and the dereferenced/called
20000e2e:	683b      	ldr	r3, [r7, #0]
20000e30:	681b      	ldr	r3, [r3, #0]
20000e32:	4798      	blx	r3
   while(1){ }; 						    //This instruction never executed
20000e34:	e7fe      	b.n	20000e34 <remap_user_code_eSRAM_1+0x40>
20000e36:	bf00      	nop

20000e38 <NVIC_ClearPendingIRQ>:
    The function clears the pending bit of an external interrupt.

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
20000e38:	b480      	push	{r7}
20000e3a:	b083      	sub	sp, #12
20000e3c:	af00      	add	r7, sp, #0
20000e3e:	4603      	mov	r3, r0
20000e40:	71fb      	strb	r3, [r7, #7]
  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
20000e42:	f24e 1300 	movw	r3, #57600	; 0xe100
20000e46:	f2ce 0300 	movt	r3, #57344	; 0xe000
20000e4a:	f997 2007 	ldrsb.w	r2, [r7, #7]
20000e4e:	ea4f 1252 	mov.w	r2, r2, lsr #5
20000e52:	79f9      	ldrb	r1, [r7, #7]
20000e54:	f001 011f 	and.w	r1, r1, #31
20000e58:	f04f 0001 	mov.w	r0, #1
20000e5c:	fa00 f101 	lsl.w	r1, r0, r1
20000e60:	f102 0260 	add.w	r2, r2, #96	; 0x60
20000e64:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
}
20000e68:	f107 070c 	add.w	r7, r7, #12
20000e6c:	46bd      	mov	sp, r7
20000e6e:	bc80      	pop	{r7}
20000e70:	4770      	bx	lr
20000e72:	bf00      	nop

20000e74 <set_bit_reg8>:
static __INLINE void set_bit_reg16(volatile uint16_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
20000e74:	b480      	push	{r7}
20000e76:	b083      	sub	sp, #12
20000e78:	af00      	add	r7, sp, #0
20000e7a:	6078      	str	r0, [r7, #4]
20000e7c:	460b      	mov	r3, r1
20000e7e:	70fb      	strb	r3, [r7, #3]
    HW_REG_BIT(reg,bit) = 0x1;
20000e80:	687b      	ldr	r3, [r7, #4]
20000e82:	f003 4270 	and.w	r2, r3, #4026531840	; 0xf0000000
20000e86:	687b      	ldr	r3, [r7, #4]
20000e88:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
20000e8c:	f423 0370 	bic.w	r3, r3, #15728640	; 0xf00000
20000e90:	ea4f 1343 	mov.w	r3, r3, lsl #5
20000e94:	441a      	add	r2, r3
20000e96:	78fb      	ldrb	r3, [r7, #3]
20000e98:	ea4f 0383 	mov.w	r3, r3, lsl #2
20000e9c:	4413      	add	r3, r2
20000e9e:	f103 7300 	add.w	r3, r3, #33554432	; 0x2000000
20000ea2:	f04f 0201 	mov.w	r2, #1
20000ea6:	601a      	str	r2, [r3, #0]
}
20000ea8:	f107 070c 	add.w	r7, r7, #12
20000eac:	46bd      	mov	sp, r7
20000eae:	bc80      	pop	{r7}
20000eb0:	4770      	bx	lr
20000eb2:	bf00      	nop

20000eb4 <clear_bit_reg8>:
static __INLINE void clear_bit_reg16(volatile uint16_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
20000eb4:	b480      	push	{r7}
20000eb6:	b083      	sub	sp, #12
20000eb8:	af00      	add	r7, sp, #0
20000eba:	6078      	str	r0, [r7, #4]
20000ebc:	460b      	mov	r3, r1
20000ebe:	70fb      	strb	r3, [r7, #3]
    HW_REG_BIT(reg,bit) = 0x0;
20000ec0:	687b      	ldr	r3, [r7, #4]
20000ec2:	f003 4270 	and.w	r2, r3, #4026531840	; 0xf0000000
20000ec6:	687b      	ldr	r3, [r7, #4]
20000ec8:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
20000ecc:	f423 0370 	bic.w	r3, r3, #15728640	; 0xf00000
20000ed0:	ea4f 1343 	mov.w	r3, r3, lsl #5
20000ed4:	441a      	add	r2, r3
20000ed6:	78fb      	ldrb	r3, [r7, #3]
20000ed8:	ea4f 0383 	mov.w	r3, r3, lsl #2
20000edc:	4413      	add	r3, r2
20000ede:	f103 7300 	add.w	r3, r3, #33554432	; 0x2000000
20000ee2:	f04f 0200 	mov.w	r2, #0
20000ee6:	601a      	str	r2, [r3, #0]
}
20000ee8:	f107 070c 	add.w	r7, r7, #12
20000eec:	46bd      	mov	sp, r7
20000eee:	bc80      	pop	{r7}
20000ef0:	4770      	bx	lr
20000ef2:	bf00      	nop

20000ef4 <read_bit_reg8>:
static __INLINE uint8_t read_bit_reg16(volatile uint16_t * reg, uint8_t bit)
{
    return (HW_REG_BIT(reg,bit));
}
static __INLINE uint8_t read_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
20000ef4:	b480      	push	{r7}
20000ef6:	b083      	sub	sp, #12
20000ef8:	af00      	add	r7, sp, #0
20000efa:	6078      	str	r0, [r7, #4]
20000efc:	460b      	mov	r3, r1
20000efe:	70fb      	strb	r3, [r7, #3]
    return (HW_REG_BIT(reg,bit));
20000f00:	687b      	ldr	r3, [r7, #4]
20000f02:	f003 4270 	and.w	r2, r3, #4026531840	; 0xf0000000
20000f06:	687b      	ldr	r3, [r7, #4]
20000f08:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
20000f0c:	f423 0370 	bic.w	r3, r3, #15728640	; 0xf00000
20000f10:	ea4f 1343 	mov.w	r3, r3, lsl #5
20000f14:	441a      	add	r2, r3
20000f16:	78fb      	ldrb	r3, [r7, #3]
20000f18:	ea4f 0383 	mov.w	r3, r3, lsl #2
20000f1c:	4413      	add	r3, r2
20000f1e:	f103 7300 	add.w	r3, r3, #33554432	; 0x2000000
20000f22:	681b      	ldr	r3, [r3, #0]
20000f24:	b2db      	uxtb	r3, r3
}
20000f26:	4618      	mov	r0, r3
20000f28:	f107 070c 	add.w	r7, r7, #12
20000f2c:	46bd      	mov	sp, r7
20000f2e:	bc80      	pop	{r7}
20000f30:	4770      	bx	lr
20000f32:	bf00      	nop

20000f34 <MSS_UART_init>:
(
    mss_uart_instance_t* this_uart, 
    uint32_t baud_rate,
    uint8_t line_config
)
{
20000f34:	b580      	push	{r7, lr}
20000f36:	b084      	sub	sp, #16
20000f38:	af00      	add	r7, sp, #0
20000f3a:	60f8      	str	r0, [r7, #12]
20000f3c:	60b9      	str	r1, [r7, #8]
20000f3e:	4613      	mov	r3, r2
20000f40:	71fb      	strb	r3, [r7, #7]
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
20000f42:	68fa      	ldr	r2, [r7, #12]
20000f44:	f641 2374 	movw	r3, #6772	; 0x1a74
20000f48:	f2c2 0300 	movt	r3, #8192	; 0x2000
20000f4c:	429a      	cmp	r2, r3
20000f4e:	d007      	beq.n	20000f60 <MSS_UART_init+0x2c>
20000f50:	68fa      	ldr	r2, [r7, #12]
20000f52:	f641 2334 	movw	r3, #6708	; 0x1a34
20000f56:	f2c2 0300 	movt	r3, #8192	; 0x2000
20000f5a:	429a      	cmp	r2, r3
20000f5c:	d000      	beq.n	20000f60 <MSS_UART_init+0x2c>
20000f5e:	be00      	bkpt	0x0000

    /* Perform generic initialization */
    global_init(this_uart, baud_rate, line_config);
20000f60:	79fb      	ldrb	r3, [r7, #7]
20000f62:	68f8      	ldr	r0, [r7, #12]
20000f64:	68b9      	ldr	r1, [r7, #8]
20000f66:	461a      	mov	r2, r3
20000f68:	f000 f988 	bl	2000127c <global_init>

    /* Disable LIN mode */
    clear_bit_reg8(&this_uart->hw_reg->MM0, ELIN);
20000f6c:	68fb      	ldr	r3, [r7, #12]
20000f6e:	681b      	ldr	r3, [r3, #0]
20000f70:	f103 0330 	add.w	r3, r3, #48	; 0x30
20000f74:	4618      	mov	r0, r3
20000f76:	f04f 0103 	mov.w	r1, #3
20000f7a:	f7ff ff9b 	bl	20000eb4 <clear_bit_reg8>

    /* Disable IrDA mode */
    clear_bit_reg8(&this_uart->hw_reg->MM1, EIRD);
20000f7e:	68fb      	ldr	r3, [r7, #12]
20000f80:	681b      	ldr	r3, [r3, #0]
20000f82:	f103 0334 	add.w	r3, r3, #52	; 0x34
20000f86:	4618      	mov	r0, r3
20000f88:	f04f 0102 	mov.w	r1, #2
20000f8c:	f7ff ff92 	bl	20000eb4 <clear_bit_reg8>

    /* Disable SmartCard Mode */
    clear_bit_reg8(&this_uart->hw_reg->MM2, EERR);
20000f90:	68fb      	ldr	r3, [r7, #12]
20000f92:	681b      	ldr	r3, [r3, #0]
20000f94:	f103 0338 	add.w	r3, r3, #56	; 0x38
20000f98:	4618      	mov	r0, r3
20000f9a:	f04f 0100 	mov.w	r1, #0
20000f9e:	f7ff ff89 	bl	20000eb4 <clear_bit_reg8>

    /* set default tx handler for automated TX using interrupt in USART mode */
    this_uart->tx_handler = default_tx_handler;
20000fa2:	68fa      	ldr	r2, [r7, #12]
20000fa4:	f241 7315 	movw	r3, #5909	; 0x1715
20000fa8:	f2c2 0300 	movt	r3, #8192	; 0x2000
20000fac:	6253      	str	r3, [r2, #36]	; 0x24
}
20000fae:	f107 0710 	add.w	r7, r7, #16
20000fb2:	46bd      	mov	sp, r7
20000fb4:	bd80      	pop	{r7, pc}
20000fb6:	bf00      	nop

20000fb8 <MSS_UART_polled_tx>:
(
    mss_uart_instance_t * this_uart,
    const uint8_t * pbuff,
    uint32_t tx_size
)
{
20000fb8:	b480      	push	{r7}
20000fba:	b089      	sub	sp, #36	; 0x24
20000fbc:	af00      	add	r7, sp, #0
20000fbe:	60f8      	str	r0, [r7, #12]
20000fc0:	60b9      	str	r1, [r7, #8]
20000fc2:	607a      	str	r2, [r7, #4]
    uint32_t char_idx = 0u;
20000fc4:	f04f 0300 	mov.w	r3, #0
20000fc8:	613b      	str	r3, [r7, #16]
    uint32_t size_sent;
    uint8_t status;

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
20000fca:	68fa      	ldr	r2, [r7, #12]
20000fcc:	f641 2374 	movw	r3, #6772	; 0x1a74
20000fd0:	f2c2 0300 	movt	r3, #8192	; 0x2000
20000fd4:	429a      	cmp	r2, r3
20000fd6:	d007      	beq.n	20000fe8 <MSS_UART_polled_tx+0x30>
20000fd8:	68fa      	ldr	r2, [r7, #12]
20000fda:	f641 2334 	movw	r3, #6708	; 0x1a34
20000fde:	f2c2 0300 	movt	r3, #8192	; 0x2000
20000fe2:	429a      	cmp	r2, r3
20000fe4:	d000      	beq.n	20000fe8 <MSS_UART_polled_tx+0x30>
20000fe6:	be00      	bkpt	0x0000
    ASSERT(pbuff != ( (uint8_t *)0));
20000fe8:	68bb      	ldr	r3, [r7, #8]
20000fea:	2b00      	cmp	r3, #0
20000fec:	d100      	bne.n	20000ff0 <MSS_UART_polled_tx+0x38>
20000fee:	be00      	bkpt	0x0000
    ASSERT(tx_size > 0u);
20000ff0:	687b      	ldr	r3, [r7, #4]
20000ff2:	2b00      	cmp	r3, #0
20000ff4:	d100      	bne.n	20000ff8 <MSS_UART_polled_tx+0x40>
20000ff6:	be00      	bkpt	0x0000

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
20000ff8:	68fa      	ldr	r2, [r7, #12]
20000ffa:	f641 2374 	movw	r3, #6772	; 0x1a74
20000ffe:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001002:	429a      	cmp	r2, r3
20001004:	d006      	beq.n	20001014 <MSS_UART_polled_tx+0x5c>
20001006:	68fa      	ldr	r2, [r7, #12]
20001008:	f641 2334 	movw	r3, #6708	; 0x1a34
2000100c:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001010:	429a      	cmp	r2, r3
20001012:	d13d      	bne.n	20001090 <MSS_UART_polled_tx+0xd8>
20001014:	68bb      	ldr	r3, [r7, #8]
20001016:	2b00      	cmp	r3, #0
20001018:	d03a      	beq.n	20001090 <MSS_UART_polled_tx+0xd8>
2000101a:	687b      	ldr	r3, [r7, #4]
2000101c:	2b00      	cmp	r3, #0
2000101e:	d037      	beq.n	20001090 <MSS_UART_polled_tx+0xd8>
         /* Remain in this loop until the entire input buffer
          * has been transferred to the UART.
          */
        do {
            /* Read the Line Status Register and update the sticky record */
            status = this_uart->hw_reg->LSR;
20001020:	68fb      	ldr	r3, [r7, #12]
20001022:	681b      	ldr	r3, [r3, #0]
20001024:	7d1b      	ldrb	r3, [r3, #20]
20001026:	76fb      	strb	r3, [r7, #27]
            this_uart->status |= status;
20001028:	68fb      	ldr	r3, [r7, #12]
2000102a:	7b5a      	ldrb	r2, [r3, #13]
2000102c:	7efb      	ldrb	r3, [r7, #27]
2000102e:	ea42 0303 	orr.w	r3, r2, r3
20001032:	b2da      	uxtb	r2, r3
20001034:	68fb      	ldr	r3, [r7, #12]
20001036:	735a      	strb	r2, [r3, #13]

            /* Check if TX FIFO is empty. */
            if(status & MSS_UART_THRE)
20001038:	7efb      	ldrb	r3, [r7, #27]
2000103a:	f003 0320 	and.w	r3, r3, #32
2000103e:	2b00      	cmp	r3, #0
20001040:	d023      	beq.n	2000108a <MSS_UART_polled_tx+0xd2>
            {
                uint32_t fill_size = TX_FIFO_SIZE;
20001042:	f04f 0310 	mov.w	r3, #16
20001046:	61fb      	str	r3, [r7, #28]

                /* Calculate the number of bytes to transmit. */
                if(tx_size < TX_FIFO_SIZE)
20001048:	687b      	ldr	r3, [r7, #4]
2000104a:	2b0f      	cmp	r3, #15
2000104c:	d801      	bhi.n	20001052 <MSS_UART_polled_tx+0x9a>
                {
                    fill_size = tx_size;
2000104e:	687b      	ldr	r3, [r7, #4]
20001050:	61fb      	str	r3, [r7, #28]
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
20001052:	f04f 0300 	mov.w	r3, #0
20001056:	617b      	str	r3, [r7, #20]
20001058:	e00e      	b.n	20001078 <MSS_UART_polled_tx+0xc0>
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
2000105a:	68fb      	ldr	r3, [r7, #12]
2000105c:	681b      	ldr	r3, [r3, #0]
2000105e:	68b9      	ldr	r1, [r7, #8]
20001060:	693a      	ldr	r2, [r7, #16]
20001062:	440a      	add	r2, r1
20001064:	7812      	ldrb	r2, [r2, #0]
20001066:	701a      	strb	r2, [r3, #0]
                    char_idx++;
20001068:	693b      	ldr	r3, [r7, #16]
2000106a:	f103 0301 	add.w	r3, r3, #1
2000106e:	613b      	str	r3, [r7, #16]
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
20001070:	697b      	ldr	r3, [r7, #20]
20001072:	f103 0301 	add.w	r3, r3, #1
20001076:	617b      	str	r3, [r7, #20]
20001078:	697a      	ldr	r2, [r7, #20]
2000107a:	69fb      	ldr	r3, [r7, #28]
2000107c:	429a      	cmp	r2, r3
2000107e:	d3ec      	bcc.n	2000105a <MSS_UART_polled_tx+0xa2>
                    this_uart->hw_reg->THR = pbuff[char_idx];
                    char_idx++;
                }

                /* Calculate the number of untransmitted bytes remaining. */
                tx_size -= size_sent;
20001080:	687a      	ldr	r2, [r7, #4]
20001082:	697b      	ldr	r3, [r7, #20]
20001084:	ebc3 0302 	rsb	r3, r3, r2
20001088:	607b      	str	r3, [r7, #4]
            }
        } while(tx_size);
2000108a:	687b      	ldr	r3, [r7, #4]
2000108c:	2b00      	cmp	r3, #0
2000108e:	d1c7      	bne.n	20001020 <MSS_UART_polled_tx+0x68>
    }
}
20001090:	f107 0724 	add.w	r7, r7, #36	; 0x24
20001094:	46bd      	mov	sp, r7
20001096:	bc80      	pop	{r7}
20001098:	4770      	bx	lr
2000109a:	bf00      	nop

2000109c <UART0_IRQHandler>:
#if defined(__GNUC__)
__attribute__((__interrupt__)) void UART0_IRQHandler(void)
#else
void UART0_IRQHandler(void)
#endif
{
2000109c:	4668      	mov	r0, sp
2000109e:	f020 0107 	bic.w	r1, r0, #7
200010a2:	468d      	mov	sp, r1
200010a4:	b589      	push	{r0, r3, r7, lr}
200010a6:	af00      	add	r7, sp, #0
    MSS_UART_isr(&g_mss_uart0);
200010a8:	f641 2074 	movw	r0, #6772	; 0x1a74
200010ac:	f2c2 0000 	movt	r0, #8192	; 0x2000
200010b0:	f000 fa1a 	bl	200014e8 <MSS_UART_isr>
}
200010b4:	46bd      	mov	sp, r7
200010b6:	e8bd 4089 	ldmia.w	sp!, {r0, r3, r7, lr}
200010ba:	4685      	mov	sp, r0
200010bc:	4770      	bx	lr
200010be:	bf00      	nop

200010c0 <UART1_IRQHandler>:
#if defined(__GNUC__)
__attribute__((__interrupt__)) void UART1_IRQHandler(void)
#else
void UART1_IRQHandler(void)
#endif
{
200010c0:	4668      	mov	r0, sp
200010c2:	f020 0107 	bic.w	r1, r0, #7
200010c6:	468d      	mov	sp, r1
200010c8:	b589      	push	{r0, r3, r7, lr}
200010ca:	af00      	add	r7, sp, #0
    MSS_UART_isr(&g_mss_uart1);
200010cc:	f641 2034 	movw	r0, #6708	; 0x1a34
200010d0:	f2c2 0000 	movt	r0, #8192	; 0x2000
200010d4:	f000 fa08 	bl	200014e8 <MSS_UART_isr>
}
200010d8:	46bd      	mov	sp, r7
200010da:	e8bd 4089 	ldmia.w	sp!, {r0, r3, r7, lr}
200010de:	4685      	mov	sp, r0
200010e0:	4770      	bx	lr
200010e2:	bf00      	nop

200010e4 <config_baud_divisors>:
config_baud_divisors
(
    mss_uart_instance_t * this_uart,
    uint32_t baudrate    
)
{
200010e4:	b580      	push	{r7, lr}
200010e6:	b088      	sub	sp, #32
200010e8:	af00      	add	r7, sp, #0
200010ea:	6078      	str	r0, [r7, #4]
200010ec:	6039      	str	r1, [r7, #0]
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
200010ee:	687a      	ldr	r2, [r7, #4]
200010f0:	f641 2374 	movw	r3, #6772	; 0x1a74
200010f4:	f2c2 0300 	movt	r3, #8192	; 0x2000
200010f8:	429a      	cmp	r2, r3
200010fa:	d007      	beq.n	2000110c <config_baud_divisors+0x28>
200010fc:	687a      	ldr	r2, [r7, #4]
200010fe:	f641 2334 	movw	r3, #6708	; 0x1a34
20001102:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001106:	429a      	cmp	r2, r3
20001108:	d000      	beq.n	2000110c <config_baud_divisors+0x28>
2000110a:	be00      	bkpt	0x0000
    
    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
2000110c:	687a      	ldr	r2, [r7, #4]
2000110e:	f641 2374 	movw	r3, #6772	; 0x1a74
20001112:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001116:	429a      	cmp	r2, r3
20001118:	d007      	beq.n	2000112a <config_baud_divisors+0x46>
2000111a:	687a      	ldr	r2, [r7, #4]
2000111c:	f641 2334 	movw	r3, #6708	; 0x1a34
20001120:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001124:	429a      	cmp	r2, r3
20001126:	f040 80a4 	bne.w	20001272 <config_baud_divisors+0x18e>
        uint32_t baud_value_by_64;
        uint32_t baud_value_by_128;
        uint32_t fractional_baud_value;
        uint32_t pclk_freq;

        this_uart->baudrate = baudrate;
2000112a:	687b      	ldr	r3, [r7, #4]
2000112c:	683a      	ldr	r2, [r7, #0]
2000112e:	609a      	str	r2, [r3, #8]

        /* Force the value of the CMSIS global variables holding the various system
          * clock frequencies to be updated. */
        SystemCoreClockUpdate();
20001130:	f7ff f9bc 	bl	200004ac <SystemCoreClockUpdate>
        if(this_uart == &g_mss_uart0)
20001134:	687a      	ldr	r2, [r7, #4]
20001136:	f641 2374 	movw	r3, #6772	; 0x1a74
2000113a:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000113e:	429a      	cmp	r2, r3
20001140:	d106      	bne.n	20001150 <config_baud_divisors+0x6c>
        {
            pclk_freq = g_FrequencyPCLK0;
20001142:	f641 2318 	movw	r3, #6680	; 0x1a18
20001146:	f2c2 0300 	movt	r3, #8192	; 0x2000
2000114a:	681b      	ldr	r3, [r3, #0]
2000114c:	61fb      	str	r3, [r7, #28]
2000114e:	e005      	b.n	2000115c <config_baud_divisors+0x78>
        }
        else
        {
            pclk_freq = g_FrequencyPCLK1;
20001150:	f641 231c 	movw	r3, #6684	; 0x1a1c
20001154:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001158:	681b      	ldr	r3, [r3, #0]
2000115a:	61fb      	str	r3, [r7, #28]
        /*
         * Compute baud value based on requested baud rate and PCLK frequency.
         * The baud value is computed using the following equation:
         *      baud_value = PCLK_Frequency / (baud_rate * 16)
         */
        baud_value_by_128 = (8u * pclk_freq) / baudrate;
2000115c:	69fb      	ldr	r3, [r7, #28]
2000115e:	ea4f 02c3 	mov.w	r2, r3, lsl #3
20001162:	683b      	ldr	r3, [r7, #0]
20001164:	fbb2 f3f3 	udiv	r3, r2, r3
20001168:	617b      	str	r3, [r7, #20]
        baud_value_by_64 = baud_value_by_128 / 2u;
2000116a:	697b      	ldr	r3, [r7, #20]
2000116c:	ea4f 0353 	mov.w	r3, r3, lsr #1
20001170:	613b      	str	r3, [r7, #16]
        baud_value = baud_value_by_64 / 64u;
20001172:	693b      	ldr	r3, [r7, #16]
20001174:	ea4f 1393 	mov.w	r3, r3, lsr #6
20001178:	60fb      	str	r3, [r7, #12]
        fractional_baud_value = baud_value_by_64 - (baud_value * 64u);
2000117a:	68fb      	ldr	r3, [r7, #12]
2000117c:	ea4f 1383 	mov.w	r3, r3, lsl #6
20001180:	693a      	ldr	r2, [r7, #16]
20001182:	ebc3 0302 	rsb	r3, r3, r2
20001186:	61bb      	str	r3, [r7, #24]
        fractional_baud_value += (baud_value_by_128 - (baud_value * 128u)) - (fractional_baud_value * 2u);
20001188:	68fb      	ldr	r3, [r7, #12]
2000118a:	ea4f 13c3 	mov.w	r3, r3, lsl #7
2000118e:	697a      	ldr	r2, [r7, #20]
20001190:	ebc3 0202 	rsb	r2, r3, r2
20001194:	69bb      	ldr	r3, [r7, #24]
20001196:	ea4f 0343 	mov.w	r3, r3, lsl #1
2000119a:	ebc3 0302 	rsb	r3, r3, r2
2000119e:	69ba      	ldr	r2, [r7, #24]
200011a0:	4413      	add	r3, r2
200011a2:	61bb      	str	r3, [r7, #24]
        
        /* Assert if integer baud value fits in 16-bit. */
        ASSERT(baud_value <= UINT16_MAX);
200011a4:	68fa      	ldr	r2, [r7, #12]
200011a6:	f64f 73ff 	movw	r3, #65535	; 0xffff
200011aa:	429a      	cmp	r2, r3
200011ac:	d900      	bls.n	200011b0 <config_baud_divisors+0xcc>
200011ae:	be00      	bkpt	0x0000
    
        if(baud_value <= (uint32_t)UINT16_MAX)
200011b0:	68fa      	ldr	r2, [r7, #12]
200011b2:	f64f 73ff 	movw	r3, #65535	; 0xffff
200011b6:	429a      	cmp	r2, r3
200011b8:	d85b      	bhi.n	20001272 <config_baud_divisors+0x18e>
        {
            if(baud_value > 1u)
200011ba:	68fb      	ldr	r3, [r7, #12]
200011bc:	2b01      	cmp	r3, #1
200011be:	d931      	bls.n	20001224 <config_baud_divisors+0x140>
            {
                /* 
                 * Use Frational baud rate divisors
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
200011c0:	687b      	ldr	r3, [r7, #4]
200011c2:	681b      	ldr	r3, [r3, #0]
200011c4:	f103 030c 	add.w	r3, r3, #12
200011c8:	4618      	mov	r0, r3
200011ca:	f04f 0107 	mov.w	r1, #7
200011ce:	f7ff fe51 	bl	20000e74 <set_bit_reg8>
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8);
200011d2:	687b      	ldr	r3, [r7, #4]
200011d4:	681b      	ldr	r3, [r3, #0]
200011d6:	68fa      	ldr	r2, [r7, #12]
200011d8:	ea4f 2212 	mov.w	r2, r2, lsr #8
200011dc:	b2d2      	uxtb	r2, r2
200011de:	711a      	strb	r2, [r3, #4]
                /* lsb of baud value */
                this_uart->hw_reg->DLR = (uint8_t)baud_value;
200011e0:	687b      	ldr	r3, [r7, #4]
200011e2:	681b      	ldr	r3, [r3, #0]
200011e4:	68fa      	ldr	r2, [r7, #12]
200011e6:	b2d2      	uxtb	r2, r2
200011e8:	701a      	strb	r2, [r3, #0]
            
                /* reset divisor latch */
                clear_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
200011ea:	687b      	ldr	r3, [r7, #4]
200011ec:	681b      	ldr	r3, [r3, #0]
200011ee:	f103 030c 	add.w	r3, r3, #12
200011f2:	4618      	mov	r0, r3
200011f4:	f04f 0107 	mov.w	r1, #7
200011f8:	f7ff fe5c 	bl	20000eb4 <clear_bit_reg8>
        
                /* Enable Fractional baud rate */
                set_bit_reg8(&this_uart->hw_reg->MM0,EFBR);
200011fc:	687b      	ldr	r3, [r7, #4]
200011fe:	681b      	ldr	r3, [r3, #0]
20001200:	f103 0330 	add.w	r3, r3, #48	; 0x30
20001204:	4618      	mov	r0, r3
20001206:	f04f 0107 	mov.w	r1, #7
2000120a:	f7ff fe33 	bl	20000e74 <set_bit_reg8>
        
                /* Load the fractional baud rate register */
                ASSERT(fractional_baud_value <= (uint32_t)UINT8_MAX);
2000120e:	69bb      	ldr	r3, [r7, #24]
20001210:	2bff      	cmp	r3, #255	; 0xff
20001212:	d900      	bls.n	20001216 <config_baud_divisors+0x132>
20001214:	be00      	bkpt	0x0000
                this_uart->hw_reg->DFR = (uint8_t)fractional_baud_value;
20001216:	687b      	ldr	r3, [r7, #4]
20001218:	681b      	ldr	r3, [r3, #0]
2000121a:	69ba      	ldr	r2, [r7, #24]
2000121c:	b2d2      	uxtb	r2, r2
2000121e:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
20001222:	e026      	b.n	20001272 <config_baud_divisors+0x18e>
            {
                /*
                 * Do NOT use Frational baud rate divisors.
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
20001224:	687b      	ldr	r3, [r7, #4]
20001226:	681b      	ldr	r3, [r3, #0]
20001228:	f103 030c 	add.w	r3, r3, #12
2000122c:	4618      	mov	r0, r3
2000122e:	f04f 0107 	mov.w	r1, #7
20001232:	f7ff fe1f 	bl	20000e74 <set_bit_reg8>
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8u);
20001236:	687b      	ldr	r3, [r7, #4]
20001238:	681b      	ldr	r3, [r3, #0]
2000123a:	68fa      	ldr	r2, [r7, #12]
2000123c:	ea4f 2212 	mov.w	r2, r2, lsr #8
20001240:	b2d2      	uxtb	r2, r2
20001242:	711a      	strb	r2, [r3, #4]
                /* lsb of baud value */
                this_uart->hw_reg->DLR = (uint8_t)baud_value;
20001244:	687b      	ldr	r3, [r7, #4]
20001246:	681b      	ldr	r3, [r3, #0]
20001248:	68fa      	ldr	r2, [r7, #12]
2000124a:	b2d2      	uxtb	r2, r2
2000124c:	701a      	strb	r2, [r3, #0]
            
                /* reset divisor latch */
                clear_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
2000124e:	687b      	ldr	r3, [r7, #4]
20001250:	681b      	ldr	r3, [r3, #0]
20001252:	f103 030c 	add.w	r3, r3, #12
20001256:	4618      	mov	r0, r3
20001258:	f04f 0107 	mov.w	r1, #7
2000125c:	f7ff fe2a 	bl	20000eb4 <clear_bit_reg8>
                
                /* Disable Fractional baud rate */
                clear_bit_reg8(&this_uart->hw_reg->MM0,EFBR);
20001260:	687b      	ldr	r3, [r7, #4]
20001262:	681b      	ldr	r3, [r3, #0]
20001264:	f103 0330 	add.w	r3, r3, #48	; 0x30
20001268:	4618      	mov	r0, r3
2000126a:	f04f 0107 	mov.w	r1, #7
2000126e:	f7ff fe21 	bl	20000eb4 <clear_bit_reg8>
            }
        }
    }
}
20001272:	f107 0720 	add.w	r7, r7, #32
20001276:	46bd      	mov	sp, r7
20001278:	bd80      	pop	{r7, pc}
2000127a:	bf00      	nop

2000127c <global_init>:
(
    mss_uart_instance_t * this_uart,
    uint32_t baud_rate,
    uint8_t line_config
)
{
2000127c:	b580      	push	{r7, lr}
2000127e:	b084      	sub	sp, #16
20001280:	af00      	add	r7, sp, #0
20001282:	60f8      	str	r0, [r7, #12]
20001284:	60b9      	str	r1, [r7, #8]
20001286:	4613      	mov	r3, r2
20001288:	71fb      	strb	r3, [r7, #7]
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
2000128a:	68fa      	ldr	r2, [r7, #12]
2000128c:	f641 2374 	movw	r3, #6772	; 0x1a74
20001290:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001294:	429a      	cmp	r2, r3
20001296:	d007      	beq.n	200012a8 <global_init+0x2c>
20001298:	68fa      	ldr	r2, [r7, #12]
2000129a:	f641 2334 	movw	r3, #6708	; 0x1a34
2000129e:	f2c2 0300 	movt	r3, #8192	; 0x2000
200012a2:	429a      	cmp	r2, r3
200012a4:	d000      	beq.n	200012a8 <global_init+0x2c>
200012a6:	be00      	bkpt	0x0000

    if(this_uart == &g_mss_uart0)
200012a8:	68fa      	ldr	r2, [r7, #12]
200012aa:	f641 2374 	movw	r3, #6772	; 0x1a74
200012ae:	f2c2 0300 	movt	r3, #8192	; 0x2000
200012b2:	429a      	cmp	r2, r3
200012b4:	d124      	bne.n	20001300 <global_init+0x84>
    {
        this_uart->hw_reg = UART0;
200012b6:	68fb      	ldr	r3, [r7, #12]
200012b8:	f04f 4280 	mov.w	r2, #1073741824	; 0x40000000
200012bc:	601a      	str	r2, [r3, #0]
        this_uart->irqn = UART0_IRQn;
200012be:	68fb      	ldr	r3, [r7, #12]
200012c0:	f04f 020a 	mov.w	r2, #10
200012c4:	711a      	strb	r2, [r3, #4]
        /* reset UART0 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART0_SOFTRESET_MASK;
200012c6:	f248 0300 	movw	r3, #32768	; 0x8000
200012ca:	f2c4 0303 	movt	r3, #16387	; 0x4003
200012ce:	f248 0200 	movw	r2, #32768	; 0x8000
200012d2:	f2c4 0203 	movt	r2, #16387	; 0x4003
200012d6:	6c92      	ldr	r2, [r2, #72]	; 0x48
200012d8:	f042 0280 	orr.w	r2, r2, #128	; 0x80
200012dc:	649a      	str	r2, [r3, #72]	; 0x48
        /* Clear any previously pended UART0 interrupt */
        NVIC_ClearPendingIRQ(UART0_IRQn);
200012de:	f04f 000a 	mov.w	r0, #10
200012e2:	f7ff fda9 	bl	20000e38 <NVIC_ClearPendingIRQ>
        /* Take UART0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
200012e6:	f248 0300 	movw	r3, #32768	; 0x8000
200012ea:	f2c4 0303 	movt	r3, #16387	; 0x4003
200012ee:	f248 0200 	movw	r2, #32768	; 0x8000
200012f2:	f2c4 0203 	movt	r2, #16387	; 0x4003
200012f6:	6c92      	ldr	r2, [r2, #72]	; 0x48
200012f8:	f022 0280 	bic.w	r2, r2, #128	; 0x80
200012fc:	649a      	str	r2, [r3, #72]	; 0x48
200012fe:	e025      	b.n	2000134c <global_init+0xd0>
    }
    else
    {
        this_uart->hw_reg = UART1;
20001300:	68fa      	ldr	r2, [r7, #12]
20001302:	f240 0300 	movw	r3, #0
20001306:	f2c4 0301 	movt	r3, #16385	; 0x4001
2000130a:	6013      	str	r3, [r2, #0]
        this_uart->irqn = UART1_IRQn;
2000130c:	68fb      	ldr	r3, [r7, #12]
2000130e:	f04f 020b 	mov.w	r2, #11
20001312:	711a      	strb	r2, [r3, #4]
        /* Reset UART1 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART1_SOFTRESET_MASK;
20001314:	f248 0300 	movw	r3, #32768	; 0x8000
20001318:	f2c4 0303 	movt	r3, #16387	; 0x4003
2000131c:	f248 0200 	movw	r2, #32768	; 0x8000
20001320:	f2c4 0203 	movt	r2, #16387	; 0x4003
20001324:	6c92      	ldr	r2, [r2, #72]	; 0x48
20001326:	f442 7280 	orr.w	r2, r2, #256	; 0x100
2000132a:	649a      	str	r2, [r3, #72]	; 0x48
        /* Clear any previously pended UART1 interrupt */
        NVIC_ClearPendingIRQ(UART1_IRQn);
2000132c:	f04f 000b 	mov.w	r0, #11
20001330:	f7ff fd82 	bl	20000e38 <NVIC_ClearPendingIRQ>
        /* Take UART1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART1_SOFTRESET_MASK;
20001334:	f248 0300 	movw	r3, #32768	; 0x8000
20001338:	f2c4 0303 	movt	r3, #16387	; 0x4003
2000133c:	f248 0200 	movw	r2, #32768	; 0x8000
20001340:	f2c4 0203 	movt	r2, #16387	; 0x4003
20001344:	6c92      	ldr	r2, [r2, #72]	; 0x48
20001346:	f422 7280 	bic.w	r2, r2, #256	; 0x100
2000134a:	649a      	str	r2, [r3, #72]	; 0x48
    }

    /* disable interrupts */
    this_uart->hw_reg->IER = 0u;
2000134c:	68fb      	ldr	r3, [r7, #12]
2000134e:	681b      	ldr	r3, [r3, #0]
20001350:	f04f 0200 	mov.w	r2, #0
20001354:	711a      	strb	r2, [r3, #4]

    /* FIFO configuration */
    this_uart->hw_reg->FCR = (uint8_t)MSS_UART_FIFO_SINGLE_BYTE;
20001356:	68fb      	ldr	r3, [r7, #12]
20001358:	681b      	ldr	r3, [r3, #0]
2000135a:	f04f 0200 	mov.w	r2, #0
2000135e:	721a      	strb	r2, [r3, #8]
    /* clear receiver FIFO */
    set_bit_reg8(&this_uart->hw_reg->FCR,CLEAR_RX_FIFO);
20001360:	68fb      	ldr	r3, [r7, #12]
20001362:	681b      	ldr	r3, [r3, #0]
20001364:	f103 0308 	add.w	r3, r3, #8
20001368:	4618      	mov	r0, r3
2000136a:	f04f 0101 	mov.w	r1, #1
2000136e:	f7ff fd81 	bl	20000e74 <set_bit_reg8>
    /* clear transmitter FIFO */
    set_bit_reg8(&this_uart->hw_reg->FCR,CLEAR_TX_FIFO);
20001372:	68fb      	ldr	r3, [r7, #12]
20001374:	681b      	ldr	r3, [r3, #0]
20001376:	f103 0308 	add.w	r3, r3, #8
2000137a:	4618      	mov	r0, r3
2000137c:	f04f 0102 	mov.w	r1, #2
20001380:	f7ff fd78 	bl	20000e74 <set_bit_reg8>

    /* set default READY mode : Mode 0*/
    /* enable RXRDYN and TXRDYN pins. The earlier FCR write to set the TX FIFO
     * trigger level inadvertently disabled the FCR_RXRDY_TXRDYN_EN bit. */
    set_bit_reg8(&this_uart->hw_reg->FCR,RXRDY_TXRDYN_EN);
20001384:	68fb      	ldr	r3, [r7, #12]
20001386:	681b      	ldr	r3, [r3, #0]
20001388:	f103 0308 	add.w	r3, r3, #8
2000138c:	4618      	mov	r0, r3
2000138e:	f04f 0100 	mov.w	r1, #0
20001392:	f7ff fd6f 	bl	20000e74 <set_bit_reg8>

    /* disable loopback : local * remote */
    clear_bit_reg8(&this_uart->hw_reg->MCR,LOOP);
20001396:	68fb      	ldr	r3, [r7, #12]
20001398:	681b      	ldr	r3, [r3, #0]
2000139a:	f103 0310 	add.w	r3, r3, #16
2000139e:	4618      	mov	r0, r3
200013a0:	f04f 0104 	mov.w	r1, #4
200013a4:	f7ff fd86 	bl	20000eb4 <clear_bit_reg8>
    clear_bit_reg8(&this_uart->hw_reg->MCR,RLOOP);
200013a8:	68fb      	ldr	r3, [r7, #12]
200013aa:	681b      	ldr	r3, [r3, #0]
200013ac:	f103 0310 	add.w	r3, r3, #16
200013b0:	4618      	mov	r0, r3
200013b2:	f04f 0105 	mov.w	r1, #5
200013b6:	f7ff fd7d 	bl	20000eb4 <clear_bit_reg8>

    /* set default TX endian */
    clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_TX);
200013ba:	68fb      	ldr	r3, [r7, #12]
200013bc:	681b      	ldr	r3, [r3, #0]
200013be:	f103 0334 	add.w	r3, r3, #52	; 0x34
200013c2:	4618      	mov	r0, r3
200013c4:	f04f 0101 	mov.w	r1, #1
200013c8:	f7ff fd74 	bl	20000eb4 <clear_bit_reg8>
    /* set default RX endian */
    clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_RX);
200013cc:	68fb      	ldr	r3, [r7, #12]
200013ce:	681b      	ldr	r3, [r3, #0]
200013d0:	f103 0334 	add.w	r3, r3, #52	; 0x34
200013d4:	4618      	mov	r0, r3
200013d6:	f04f 0100 	mov.w	r1, #0
200013da:	f7ff fd6b 	bl	20000eb4 <clear_bit_reg8>

    /* default AFM : disabled */
    clear_bit_reg8(&this_uart->hw_reg->MM2,EAFM);
200013de:	68fb      	ldr	r3, [r7, #12]
200013e0:	681b      	ldr	r3, [r3, #0]
200013e2:	f103 0338 	add.w	r3, r3, #56	; 0x38
200013e6:	4618      	mov	r0, r3
200013e8:	f04f 0101 	mov.w	r1, #1
200013ec:	f7ff fd62 	bl	20000eb4 <clear_bit_reg8>

    /* disable TX time gaurd */
    clear_bit_reg8(&this_uart->hw_reg->MM0,ETTG); 
200013f0:	68fb      	ldr	r3, [r7, #12]
200013f2:	681b      	ldr	r3, [r3, #0]
200013f4:	f103 0330 	add.w	r3, r3, #48	; 0x30
200013f8:	4618      	mov	r0, r3
200013fa:	f04f 0105 	mov.w	r1, #5
200013fe:	f7ff fd59 	bl	20000eb4 <clear_bit_reg8>

    /* set default RX timeout */
    clear_bit_reg8(&this_uart->hw_reg->MM0,ERTO); 
20001402:	68fb      	ldr	r3, [r7, #12]
20001404:	681b      	ldr	r3, [r3, #0]
20001406:	f103 0330 	add.w	r3, r3, #48	; 0x30
2000140a:	4618      	mov	r0, r3
2000140c:	f04f 0106 	mov.w	r1, #6
20001410:	f7ff fd50 	bl	20000eb4 <clear_bit_reg8>

    /* disable fractional baud-rate */
    clear_bit_reg8(&this_uart->hw_reg->MM0,EFBR); 
20001414:	68fb      	ldr	r3, [r7, #12]
20001416:	681b      	ldr	r3, [r3, #0]
20001418:	f103 0330 	add.w	r3, r3, #48	; 0x30
2000141c:	4618      	mov	r0, r3
2000141e:	f04f 0107 	mov.w	r1, #7
20001422:	f7ff fd47 	bl	20000eb4 <clear_bit_reg8>

    /* disable single wire mode */
    clear_bit_reg8(&this_uart->hw_reg->MM2,ESWM);
20001426:	68fb      	ldr	r3, [r7, #12]
20001428:	681b      	ldr	r3, [r3, #0]
2000142a:	f103 0338 	add.w	r3, r3, #56	; 0x38
2000142e:	4618      	mov	r0, r3
20001430:	f04f 0103 	mov.w	r1, #3
20001434:	f7ff fd3e 	bl	20000eb4 <clear_bit_reg8>

    /* set filter to minimum value */
    this_uart->hw_reg->GFR = 0u;
20001438:	68fb      	ldr	r3, [r7, #12]
2000143a:	681b      	ldr	r3, [r3, #0]
2000143c:	f04f 0200 	mov.w	r2, #0
20001440:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
    /* set default TX time gaurd */
    this_uart->hw_reg->TTG = 0u;
20001444:	68fb      	ldr	r3, [r7, #12]
20001446:	681b      	ldr	r3, [r3, #0]
20001448:	f04f 0200 	mov.w	r2, #0
2000144c:	f883 2048 	strb.w	r2, [r3, #72]	; 0x48
    /* set default RX timeout */
    this_uart->hw_reg->RTO = 0u;
20001450:	68fb      	ldr	r3, [r7, #12]
20001452:	681b      	ldr	r3, [r3, #0]
20001454:	f04f 0200 	mov.w	r2, #0
20001458:	f883 204c 	strb.w	r2, [r3, #76]	; 0x4c
    
    /* 
     * Configure baud rate divisors. This uses the frational baud rate divisor
     * where possible to provide the most accurate baud rat possible.
     */
    config_baud_divisors(this_uart, baud_rate);
2000145c:	68f8      	ldr	r0, [r7, #12]
2000145e:	68b9      	ldr	r1, [r7, #8]
20001460:	f7ff fe40 	bl	200010e4 <config_baud_divisors>

    /* set the line control register (bit length, stop bits, parity) */
    this_uart->hw_reg->LCR = line_config;
20001464:	68fb      	ldr	r3, [r7, #12]
20001466:	681b      	ldr	r3, [r3, #0]
20001468:	79fa      	ldrb	r2, [r7, #7]
2000146a:	731a      	strb	r2, [r3, #12]

    /* Instance setup */
    this_uart->baudrate = baud_rate;
2000146c:	68fb      	ldr	r3, [r7, #12]
2000146e:	68ba      	ldr	r2, [r7, #8]
20001470:	609a      	str	r2, [r3, #8]
    this_uart->lineconfig = line_config;
20001472:	68fb      	ldr	r3, [r7, #12]
20001474:	79fa      	ldrb	r2, [r7, #7]
20001476:	731a      	strb	r2, [r3, #12]
    this_uart->tx_buff_size = TX_COMPLETE;
20001478:	68fb      	ldr	r3, [r7, #12]
2000147a:	f04f 0200 	mov.w	r2, #0
2000147e:	615a      	str	r2, [r3, #20]
    this_uart->tx_buffer = (const uint8_t *)0;
20001480:	68fb      	ldr	r3, [r7, #12]
20001482:	f04f 0200 	mov.w	r2, #0
20001486:	611a      	str	r2, [r3, #16]
    this_uart->tx_idx = 0u;
20001488:	68fb      	ldr	r3, [r7, #12]
2000148a:	f04f 0200 	mov.w	r2, #0
2000148e:	619a      	str	r2, [r3, #24]

    /* Default handlers for MSS UART interrupts */
    this_uart->rx_handler       = NULL_HANDLER;
20001490:	68fb      	ldr	r3, [r7, #12]
20001492:	f04f 0200 	mov.w	r2, #0
20001496:	621a      	str	r2, [r3, #32]
    this_uart->tx_handler       = NULL_HANDLER;
20001498:	68fb      	ldr	r3, [r7, #12]
2000149a:	f04f 0200 	mov.w	r2, #0
2000149e:	625a      	str	r2, [r3, #36]	; 0x24
    this_uart->linests_handler  = NULL_HANDLER;
200014a0:	68fb      	ldr	r3, [r7, #12]
200014a2:	f04f 0200 	mov.w	r2, #0
200014a6:	61da      	str	r2, [r3, #28]
    this_uart->modemsts_handler = NULL_HANDLER;
200014a8:	68fb      	ldr	r3, [r7, #12]
200014aa:	f04f 0200 	mov.w	r2, #0
200014ae:	629a      	str	r2, [r3, #40]	; 0x28
    this_uart->rto_handler      = NULL_HANDLER;    
200014b0:	68fb      	ldr	r3, [r7, #12]
200014b2:	f04f 0200 	mov.w	r2, #0
200014b6:	62da      	str	r2, [r3, #44]	; 0x2c
    this_uart->nack_handler     = NULL_HANDLER;   
200014b8:	68fb      	ldr	r3, [r7, #12]
200014ba:	f04f 0200 	mov.w	r2, #0
200014be:	631a      	str	r2, [r3, #48]	; 0x30
    this_uart->pid_pei_handler  = NULL_HANDLER;
200014c0:	68fb      	ldr	r3, [r7, #12]
200014c2:	f04f 0200 	mov.w	r2, #0
200014c6:	635a      	str	r2, [r3, #52]	; 0x34
    this_uart->break_handler    = NULL_HANDLER;    
200014c8:	68fb      	ldr	r3, [r7, #12]
200014ca:	f04f 0200 	mov.w	r2, #0
200014ce:	639a      	str	r2, [r3, #56]	; 0x38
    this_uart->sync_handler     = NULL_HANDLER;   
200014d0:	68fb      	ldr	r3, [r7, #12]
200014d2:	f04f 0200 	mov.w	r2, #0
200014d6:	63da      	str	r2, [r3, #60]	; 0x3c

    /* Initialize the sticky status */
    this_uart->status = 0u;
200014d8:	68fb      	ldr	r3, [r7, #12]
200014da:	f04f 0200 	mov.w	r2, #0
200014de:	735a      	strb	r2, [r3, #13]
}
200014e0:	f107 0710 	add.w	r7, r7, #16
200014e4:	46bd      	mov	sp, r7
200014e6:	bd80      	pop	{r7, pc}

200014e8 <MSS_UART_isr>:
static void
MSS_UART_isr
(
    mss_uart_instance_t * this_uart
)
{
200014e8:	b580      	push	{r7, lr}
200014ea:	b084      	sub	sp, #16
200014ec:	af00      	add	r7, sp, #0
200014ee:	6078      	str	r0, [r7, #4]
    uint8_t iirf;

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
200014f0:	687a      	ldr	r2, [r7, #4]
200014f2:	f641 2374 	movw	r3, #6772	; 0x1a74
200014f6:	f2c2 0300 	movt	r3, #8192	; 0x2000
200014fa:	429a      	cmp	r2, r3
200014fc:	d007      	beq.n	2000150e <MSS_UART_isr+0x26>
200014fe:	687a      	ldr	r2, [r7, #4]
20001500:	f641 2334 	movw	r3, #6708	; 0x1a34
20001504:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001508:	429a      	cmp	r2, r3
2000150a:	d000      	beq.n	2000150e <MSS_UART_isr+0x26>
2000150c:	be00      	bkpt	0x0000

    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
2000150e:	687a      	ldr	r2, [r7, #4]
20001510:	f641 2374 	movw	r3, #6772	; 0x1a74
20001514:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001518:	429a      	cmp	r2, r3
2000151a:	d007      	beq.n	2000152c <MSS_UART_isr+0x44>
2000151c:	687a      	ldr	r2, [r7, #4]
2000151e:	f641 2334 	movw	r3, #6708	; 0x1a34
20001522:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001526:	429a      	cmp	r2, r3
20001528:	f040 80ef 	bne.w	2000170a <MSS_UART_isr+0x222>
    {
        iirf = this_uart->hw_reg->IIR & IIRF_MASK;
2000152c:	687b      	ldr	r3, [r7, #4]
2000152e:	681b      	ldr	r3, [r3, #0]
20001530:	7a1b      	ldrb	r3, [r3, #8]
20001532:	b2db      	uxtb	r3, r3
20001534:	f003 030f 	and.w	r3, r3, #15
20001538:	73fb      	strb	r3, [r7, #15]

        switch (iirf)
2000153a:	7bfb      	ldrb	r3, [r7, #15]
2000153c:	2b0c      	cmp	r3, #12
2000153e:	f200 80d7 	bhi.w	200016f0 <MSS_UART_isr+0x208>
20001542:	a201      	add	r2, pc, #4	; (adr r2, 20001548 <MSS_UART_isr+0x60>)
20001544:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
20001548:	2000157d 	.word	0x2000157d
2000154c:	200016f1 	.word	0x200016f1
20001550:	2000159b 	.word	0x2000159b
20001554:	200015f5 	.word	0x200015f5
20001558:	200015b9 	.word	0x200015b9
2000155c:	200016f1 	.word	0x200016f1
20001560:	200015d7 	.word	0x200015d7
20001564:	200016f1 	.word	0x200016f1
20001568:	200016f1 	.word	0x200016f1
2000156c:	200016f1 	.word	0x200016f1
20001570:	200016f1 	.word	0x200016f1
20001574:	200016f1 	.word	0x200016f1
20001578:	200015b9 	.word	0x200015b9
        {
            case IIRF_MODEM_STATUS:  /* Modem status interrupt */
            {
                ASSERT(NULL_HANDLER != this_uart->modemsts_handler);
2000157c:	687b      	ldr	r3, [r7, #4]
2000157e:	6a9b      	ldr	r3, [r3, #40]	; 0x28
20001580:	2b00      	cmp	r3, #0
20001582:	d100      	bne.n	20001586 <MSS_UART_isr+0x9e>
20001584:	be00      	bkpt	0x0000
                if(NULL_HANDLER != this_uart->modemsts_handler)
20001586:	687b      	ldr	r3, [r7, #4]
20001588:	6a9b      	ldr	r3, [r3, #40]	; 0x28
2000158a:	2b00      	cmp	r3, #0
2000158c:	f000 80b2 	beq.w	200016f4 <MSS_UART_isr+0x20c>
                {
                   (*(this_uart->modemsts_handler))(this_uart);
20001590:	687b      	ldr	r3, [r7, #4]
20001592:	6a9b      	ldr	r3, [r3, #40]	; 0x28
20001594:	6878      	ldr	r0, [r7, #4]
20001596:	4798      	blx	r3
                }
            }
            break;
20001598:	e0b7      	b.n	2000170a <MSS_UART_isr+0x222>

            case IIRF_THRE: /* Transmitter Holding Register Empty */
            {
                ASSERT(NULL_HANDLER != this_uart->tx_handler);
2000159a:	687b      	ldr	r3, [r7, #4]
2000159c:	6a5b      	ldr	r3, [r3, #36]	; 0x24
2000159e:	2b00      	cmp	r3, #0
200015a0:	d100      	bne.n	200015a4 <MSS_UART_isr+0xbc>
200015a2:	be00      	bkpt	0x0000
                if(NULL_HANDLER != this_uart->tx_handler)
200015a4:	687b      	ldr	r3, [r7, #4]
200015a6:	6a5b      	ldr	r3, [r3, #36]	; 0x24
200015a8:	2b00      	cmp	r3, #0
200015aa:	f000 80a5 	beq.w	200016f8 <MSS_UART_isr+0x210>
                {
                    (*(this_uart->tx_handler))(this_uart);
200015ae:	687b      	ldr	r3, [r7, #4]
200015b0:	6a5b      	ldr	r3, [r3, #36]	; 0x24
200015b2:	6878      	ldr	r0, [r7, #4]
200015b4:	4798      	blx	r3
                }
            }
            break;
200015b6:	e0a8      	b.n	2000170a <MSS_UART_isr+0x222>

            case IIRF_RX_DATA:      /* Received Data Available */
            case IIRF_DATA_TIMEOUT: /* Received Data Timed-out */
            {
                ASSERT(NULL_HANDLER != this_uart->rx_handler);
200015b8:	687b      	ldr	r3, [r7, #4]
200015ba:	6a1b      	ldr	r3, [r3, #32]
200015bc:	2b00      	cmp	r3, #0
200015be:	d100      	bne.n	200015c2 <MSS_UART_isr+0xda>
200015c0:	be00      	bkpt	0x0000
                if(NULL_HANDLER != this_uart->rx_handler)
200015c2:	687b      	ldr	r3, [r7, #4]
200015c4:	6a1b      	ldr	r3, [r3, #32]
200015c6:	2b00      	cmp	r3, #0
200015c8:	f000 8098 	beq.w	200016fc <MSS_UART_isr+0x214>
                {
                    (*(this_uart->rx_handler))(this_uart);
200015cc:	687b      	ldr	r3, [r7, #4]
200015ce:	6a1b      	ldr	r3, [r3, #32]
200015d0:	6878      	ldr	r0, [r7, #4]
200015d2:	4798      	blx	r3
                }
            }
            break;
200015d4:	e099      	b.n	2000170a <MSS_UART_isr+0x222>

            case IIRF_RX_LINE_STATUS:  /* Line Status Interrupt */
            {
                ASSERT(NULL_HANDLER != this_uart->linests_handler);
200015d6:	687b      	ldr	r3, [r7, #4]
200015d8:	69db      	ldr	r3, [r3, #28]
200015da:	2b00      	cmp	r3, #0
200015dc:	d100      	bne.n	200015e0 <MSS_UART_isr+0xf8>
200015de:	be00      	bkpt	0x0000
                if(NULL_HANDLER != this_uart->linests_handler)
200015e0:	687b      	ldr	r3, [r7, #4]
200015e2:	69db      	ldr	r3, [r3, #28]
200015e4:	2b00      	cmp	r3, #0
200015e6:	f000 808b 	beq.w	20001700 <MSS_UART_isr+0x218>
                {
                   (*(this_uart->linests_handler))(this_uart);
200015ea:	687b      	ldr	r3, [r7, #4]
200015ec:	69db      	ldr	r3, [r3, #28]
200015ee:	6878      	ldr	r0, [r7, #4]
200015f0:	4798      	blx	r3
                }
            }
            break;
200015f2:	e08a      	b.n	2000170a <MSS_UART_isr+0x222>
            case IIRF_MMI:
            {
                /* Identify multimode interrupts and handle */

                /* Receiver time-out interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,ERTOI))
200015f4:	687b      	ldr	r3, [r7, #4]
200015f6:	681b      	ldr	r3, [r3, #0]
200015f8:	f103 0328 	add.w	r3, r3, #40	; 0x28
200015fc:	4618      	mov	r0, r3
200015fe:	f04f 0100 	mov.w	r1, #0
20001602:	f7ff fc77 	bl	20000ef4 <read_bit_reg8>
20001606:	4603      	mov	r3, r0
20001608:	2b00      	cmp	r3, #0
2000160a:	d00c      	beq.n	20001626 <MSS_UART_isr+0x13e>
                {
                    ASSERT(NULL_HANDLER != this_uart->rto_handler);
2000160c:	687b      	ldr	r3, [r7, #4]
2000160e:	6adb      	ldr	r3, [r3, #44]	; 0x2c
20001610:	2b00      	cmp	r3, #0
20001612:	d100      	bne.n	20001616 <MSS_UART_isr+0x12e>
20001614:	be00      	bkpt	0x0000
                    if(NULL_HANDLER != this_uart->rto_handler)
20001616:	687b      	ldr	r3, [r7, #4]
20001618:	6adb      	ldr	r3, [r3, #44]	; 0x2c
2000161a:	2b00      	cmp	r3, #0
2000161c:	d003      	beq.n	20001626 <MSS_UART_isr+0x13e>
                    {
                        (*(this_uart->rto_handler))(this_uart);
2000161e:	687b      	ldr	r3, [r7, #4]
20001620:	6adb      	ldr	r3, [r3, #44]	; 0x2c
20001622:	6878      	ldr	r0, [r7, #4]
20001624:	4798      	blx	r3
                    }
                }
                /* NACK interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,ENACKI))
20001626:	687b      	ldr	r3, [r7, #4]
20001628:	681b      	ldr	r3, [r3, #0]
2000162a:	f103 0328 	add.w	r3, r3, #40	; 0x28
2000162e:	4618      	mov	r0, r3
20001630:	f04f 0101 	mov.w	r1, #1
20001634:	f7ff fc5e 	bl	20000ef4 <read_bit_reg8>
20001638:	4603      	mov	r3, r0
2000163a:	2b00      	cmp	r3, #0
2000163c:	d00c      	beq.n	20001658 <MSS_UART_isr+0x170>
                {
                    ASSERT(NULL_HANDLER != this_uart->nack_handler);
2000163e:	687b      	ldr	r3, [r7, #4]
20001640:	6b1b      	ldr	r3, [r3, #48]	; 0x30
20001642:	2b00      	cmp	r3, #0
20001644:	d100      	bne.n	20001648 <MSS_UART_isr+0x160>
20001646:	be00      	bkpt	0x0000
                    if(NULL_HANDLER != this_uart->nack_handler)
20001648:	687b      	ldr	r3, [r7, #4]
2000164a:	6b1b      	ldr	r3, [r3, #48]	; 0x30
2000164c:	2b00      	cmp	r3, #0
2000164e:	d003      	beq.n	20001658 <MSS_UART_isr+0x170>
                    {
                        (*(this_uart->nack_handler))(this_uart);
20001650:	687b      	ldr	r3, [r7, #4]
20001652:	6b1b      	ldr	r3, [r3, #48]	; 0x30
20001654:	6878      	ldr	r0, [r7, #4]
20001656:	4798      	blx	r3
                    }
                }

                /* PID parity error interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,EPID_PEI))
20001658:	687b      	ldr	r3, [r7, #4]
2000165a:	681b      	ldr	r3, [r3, #0]
2000165c:	f103 0328 	add.w	r3, r3, #40	; 0x28
20001660:	4618      	mov	r0, r3
20001662:	f04f 0102 	mov.w	r1, #2
20001666:	f7ff fc45 	bl	20000ef4 <read_bit_reg8>
2000166a:	4603      	mov	r3, r0
2000166c:	2b00      	cmp	r3, #0
2000166e:	d00c      	beq.n	2000168a <MSS_UART_isr+0x1a2>
                {
                    ASSERT(NULL_HANDLER != this_uart->pid_pei_handler);
20001670:	687b      	ldr	r3, [r7, #4]
20001672:	6b5b      	ldr	r3, [r3, #52]	; 0x34
20001674:	2b00      	cmp	r3, #0
20001676:	d100      	bne.n	2000167a <MSS_UART_isr+0x192>
20001678:	be00      	bkpt	0x0000
                    if(NULL_HANDLER != this_uart->pid_pei_handler)
2000167a:	687b      	ldr	r3, [r7, #4]
2000167c:	6b5b      	ldr	r3, [r3, #52]	; 0x34
2000167e:	2b00      	cmp	r3, #0
20001680:	d003      	beq.n	2000168a <MSS_UART_isr+0x1a2>
                    {
                        (*(this_uart->pid_pei_handler))(this_uart);
20001682:	687b      	ldr	r3, [r7, #4]
20001684:	6b5b      	ldr	r3, [r3, #52]	; 0x34
20001686:	6878      	ldr	r0, [r7, #4]
20001688:	4798      	blx	r3
                    }
                }

                /* LIN break detection interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,ELINBI))
2000168a:	687b      	ldr	r3, [r7, #4]
2000168c:	681b      	ldr	r3, [r3, #0]
2000168e:	f103 0328 	add.w	r3, r3, #40	; 0x28
20001692:	4618      	mov	r0, r3
20001694:	f04f 0103 	mov.w	r1, #3
20001698:	f7ff fc2c 	bl	20000ef4 <read_bit_reg8>
2000169c:	4603      	mov	r3, r0
2000169e:	2b00      	cmp	r3, #0
200016a0:	d00c      	beq.n	200016bc <MSS_UART_isr+0x1d4>
                {
                    ASSERT(NULL_HANDLER != this_uart->break_handler);
200016a2:	687b      	ldr	r3, [r7, #4]
200016a4:	6b9b      	ldr	r3, [r3, #56]	; 0x38
200016a6:	2b00      	cmp	r3, #0
200016a8:	d100      	bne.n	200016ac <MSS_UART_isr+0x1c4>
200016aa:	be00      	bkpt	0x0000
                    if(NULL_HANDLER != this_uart->break_handler)
200016ac:	687b      	ldr	r3, [r7, #4]
200016ae:	6b9b      	ldr	r3, [r3, #56]	; 0x38
200016b0:	2b00      	cmp	r3, #0
200016b2:	d003      	beq.n	200016bc <MSS_UART_isr+0x1d4>
                    {
                        (*(this_uart->break_handler))(this_uart);
200016b4:	687b      	ldr	r3, [r7, #4]
200016b6:	6b9b      	ldr	r3, [r3, #56]	; 0x38
200016b8:	6878      	ldr	r0, [r7, #4]
200016ba:	4798      	blx	r3
                    }
                }

                /* LIN Sync detection interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,ELINSI))
200016bc:	687b      	ldr	r3, [r7, #4]
200016be:	681b      	ldr	r3, [r3, #0]
200016c0:	f103 0328 	add.w	r3, r3, #40	; 0x28
200016c4:	4618      	mov	r0, r3
200016c6:	f04f 0104 	mov.w	r1, #4
200016ca:	f7ff fc13 	bl	20000ef4 <read_bit_reg8>
200016ce:	4603      	mov	r3, r0
200016d0:	2b00      	cmp	r3, #0
200016d2:	d017      	beq.n	20001704 <MSS_UART_isr+0x21c>
                {
                    ASSERT(NULL_HANDLER != this_uart->sync_handler);
200016d4:	687b      	ldr	r3, [r7, #4]
200016d6:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
200016d8:	2b00      	cmp	r3, #0
200016da:	d100      	bne.n	200016de <MSS_UART_isr+0x1f6>
200016dc:	be00      	bkpt	0x0000
                    if(NULL_HANDLER != this_uart->sync_handler)
200016de:	687b      	ldr	r3, [r7, #4]
200016e0:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
200016e2:	2b00      	cmp	r3, #0
200016e4:	d010      	beq.n	20001708 <MSS_UART_isr+0x220>
                    {
                        (*(this_uart->sync_handler))(this_uart);
200016e6:	687b      	ldr	r3, [r7, #4]
200016e8:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
200016ea:	6878      	ldr	r0, [r7, #4]
200016ec:	4798      	blx	r3
                    }
                }
                break;
200016ee:	e00c      	b.n	2000170a <MSS_UART_isr+0x222>
            }

            default:
            {
                ASSERT(INVALID_INTERRUPT);
200016f0:	be00      	bkpt	0x0000
200016f2:	e00a      	b.n	2000170a <MSS_UART_isr+0x222>
                if(NULL_HANDLER != this_uart->modemsts_handler)
                {
                   (*(this_uart->modemsts_handler))(this_uart);
                }
            }
            break;
200016f4:	bf00      	nop
200016f6:	e008      	b.n	2000170a <MSS_UART_isr+0x222>
                if(NULL_HANDLER != this_uart->tx_handler)
                {
                    (*(this_uart->tx_handler))(this_uart);
                }
            }
            break;
200016f8:	bf00      	nop
200016fa:	e006      	b.n	2000170a <MSS_UART_isr+0x222>
                if(NULL_HANDLER != this_uart->rx_handler)
                {
                    (*(this_uart->rx_handler))(this_uart);
                }
            }
            break;
200016fc:	bf00      	nop
200016fe:	e004      	b.n	2000170a <MSS_UART_isr+0x222>
                if(NULL_HANDLER != this_uart->linests_handler)
                {
                   (*(this_uart->linests_handler))(this_uart);
                }
            }
            break;
20001700:	bf00      	nop
20001702:	e002      	b.n	2000170a <MSS_UART_isr+0x222>
                    if(NULL_HANDLER != this_uart->sync_handler)
                    {
                        (*(this_uart->sync_handler))(this_uart);
                    }
                }
                break;
20001704:	bf00      	nop
20001706:	e000      	b.n	2000170a <MSS_UART_isr+0x222>
20001708:	bf00      	nop
                ASSERT(INVALID_INTERRUPT);
            }
            break;
        }
    }
}
2000170a:	f107 0710 	add.w	r7, r7, #16
2000170e:	46bd      	mov	sp, r7
20001710:	bd80      	pop	{r7, pc}
20001712:	bf00      	nop

20001714 <default_tx_handler>:
static void
default_tx_handler
(
    mss_uart_instance_t * this_uart
)
{
20001714:	b580      	push	{r7, lr}
20001716:	b086      	sub	sp, #24
20001718:	af00      	add	r7, sp, #0
2000171a:	6078      	str	r0, [r7, #4]
    uint8_t status;

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
2000171c:	687a      	ldr	r2, [r7, #4]
2000171e:	f641 2374 	movw	r3, #6772	; 0x1a74
20001722:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001726:	429a      	cmp	r2, r3
20001728:	d007      	beq.n	2000173a <default_tx_handler+0x26>
2000172a:	687a      	ldr	r2, [r7, #4]
2000172c:	f641 2334 	movw	r3, #6708	; 0x1a34
20001730:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001734:	429a      	cmp	r2, r3
20001736:	d000      	beq.n	2000173a <default_tx_handler+0x26>
20001738:	be00      	bkpt	0x0000
    ASSERT(( (uint8_t *)0 ) != this_uart->tx_buffer);
2000173a:	687b      	ldr	r3, [r7, #4]
2000173c:	691b      	ldr	r3, [r3, #16]
2000173e:	2b00      	cmp	r3, #0
20001740:	d100      	bne.n	20001744 <default_tx_handler+0x30>
20001742:	be00      	bkpt	0x0000
    ASSERT(0u < this_uart->tx_buff_size);
20001744:	687b      	ldr	r3, [r7, #4]
20001746:	695b      	ldr	r3, [r3, #20]
20001748:	2b00      	cmp	r3, #0
2000174a:	d100      	bne.n	2000174e <default_tx_handler+0x3a>
2000174c:	be00      	bkpt	0x0000

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
2000174e:	687a      	ldr	r2, [r7, #4]
20001750:	f641 2374 	movw	r3, #6772	; 0x1a74
20001754:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001758:	429a      	cmp	r2, r3
2000175a:	d006      	beq.n	2000176a <default_tx_handler+0x56>
2000175c:	687a      	ldr	r2, [r7, #4]
2000175e:	f641 2334 	movw	r3, #6708	; 0x1a34
20001762:	f2c2 0300 	movt	r3, #8192	; 0x2000
20001766:	429a      	cmp	r2, r3
20001768:	d155      	bne.n	20001816 <default_tx_handler+0x102>
       (((uint8_t *)0 ) != this_uart->tx_buffer) &&
2000176a:	687b      	ldr	r3, [r7, #4]
2000176c:	691b      	ldr	r3, [r3, #16]

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(( (uint8_t *)0 ) != this_uart->tx_buffer);
    ASSERT(0u < this_uart->tx_buff_size);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
2000176e:	2b00      	cmp	r3, #0
20001770:	d051      	beq.n	20001816 <default_tx_handler+0x102>
       (((uint8_t *)0 ) != this_uart->tx_buffer) &&
       (0u < this_uart->tx_buff_size))
20001772:	687b      	ldr	r3, [r7, #4]
20001774:	695b      	ldr	r3, [r3, #20]

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(( (uint8_t *)0 ) != this_uart->tx_buffer);
    ASSERT(0u < this_uart->tx_buff_size);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
20001776:	2b00      	cmp	r3, #0
20001778:	d04d      	beq.n	20001816 <default_tx_handler+0x102>
       (((uint8_t *)0 ) != this_uart->tx_buffer) &&
       (0u < this_uart->tx_buff_size))
    {
        /* Read the Line Status Register and update the sticky record. */
        status = this_uart->hw_reg->LSR;
2000177a:	687b      	ldr	r3, [r7, #4]
2000177c:	681b      	ldr	r3, [r3, #0]
2000177e:	7d1b      	ldrb	r3, [r3, #20]
20001780:	72fb      	strb	r3, [r7, #11]
        this_uart->status |= status;
20001782:	687b      	ldr	r3, [r7, #4]
20001784:	7b5a      	ldrb	r2, [r3, #13]
20001786:	7afb      	ldrb	r3, [r7, #11]
20001788:	ea42 0303 	orr.w	r3, r2, r3
2000178c:	b2da      	uxtb	r2, r3
2000178e:	687b      	ldr	r3, [r7, #4]
20001790:	735a      	strb	r2, [r3, #13]

        /*
         * This function should only be called as a result of a THRE interrupt.
         * Verify that this is true before proceeding to transmit data.
         */
        if(status & MSS_UART_THRE)
20001792:	7afb      	ldrb	r3, [r7, #11]
20001794:	f003 0320 	and.w	r3, r3, #32
20001798:	2b00      	cmp	r3, #0
2000179a:	d029      	beq.n	200017f0 <default_tx_handler+0xdc>
        {
            uint32_t i;
            uint32_t fill_size = TX_FIFO_SIZE;
2000179c:	f04f 0310 	mov.w	r3, #16
200017a0:	613b      	str	r3, [r7, #16]
            uint32_t tx_remain = this_uart->tx_buff_size - this_uart->tx_idx;
200017a2:	687b      	ldr	r3, [r7, #4]
200017a4:	695a      	ldr	r2, [r3, #20]
200017a6:	687b      	ldr	r3, [r7, #4]
200017a8:	699b      	ldr	r3, [r3, #24]
200017aa:	ebc3 0302 	rsb	r3, r3, r2
200017ae:	617b      	str	r3, [r7, #20]

            /* Calculate the number of bytes to transmit. */
            if(tx_remain < TX_FIFO_SIZE)
200017b0:	697b      	ldr	r3, [r7, #20]
200017b2:	2b0f      	cmp	r3, #15
200017b4:	d801      	bhi.n	200017ba <default_tx_handler+0xa6>
            {
                fill_size = tx_remain;
200017b6:	697b      	ldr	r3, [r7, #20]
200017b8:	613b      	str	r3, [r7, #16]
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
200017ba:	f04f 0300 	mov.w	r3, #0
200017be:	60fb      	str	r3, [r7, #12]
200017c0:	e012      	b.n	200017e8 <default_tx_handler+0xd4>
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
200017c2:	687b      	ldr	r3, [r7, #4]
200017c4:	681b      	ldr	r3, [r3, #0]
200017c6:	687a      	ldr	r2, [r7, #4]
200017c8:	6911      	ldr	r1, [r2, #16]
200017ca:	687a      	ldr	r2, [r7, #4]
200017cc:	6992      	ldr	r2, [r2, #24]
200017ce:	440a      	add	r2, r1
200017d0:	7812      	ldrb	r2, [r2, #0]
200017d2:	701a      	strb	r2, [r3, #0]
                ++this_uart->tx_idx;
200017d4:	687b      	ldr	r3, [r7, #4]
200017d6:	699b      	ldr	r3, [r3, #24]
200017d8:	f103 0201 	add.w	r2, r3, #1
200017dc:	687b      	ldr	r3, [r7, #4]
200017de:	619a      	str	r2, [r3, #24]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
200017e0:	68fb      	ldr	r3, [r7, #12]
200017e2:	f103 0301 	add.w	r3, r3, #1
200017e6:	60fb      	str	r3, [r7, #12]
200017e8:	68fa      	ldr	r2, [r7, #12]
200017ea:	693b      	ldr	r3, [r7, #16]
200017ec:	429a      	cmp	r2, r3
200017ee:	d3e8      	bcc.n	200017c2 <default_tx_handler+0xae>
                ++this_uart->tx_idx;
            }
        }

        /* Flag Tx as complete if all data has been pushed into the Tx FIFO. */
        if(this_uart->tx_idx == this_uart->tx_buff_size)
200017f0:	687b      	ldr	r3, [r7, #4]
200017f2:	699a      	ldr	r2, [r3, #24]
200017f4:	687b      	ldr	r3, [r7, #4]
200017f6:	695b      	ldr	r3, [r3, #20]
200017f8:	429a      	cmp	r2, r3
200017fa:	d10c      	bne.n	20001816 <default_tx_handler+0x102>
        {
            this_uart->tx_buff_size = TX_COMPLETE;
200017fc:	687b      	ldr	r3, [r7, #4]
200017fe:	f04f 0200 	mov.w	r2, #0
20001802:	615a      	str	r2, [r3, #20]
            /* disables TX interrupt */
            clear_bit_reg8(&this_uart->hw_reg->IER,ETBEI);
20001804:	687b      	ldr	r3, [r7, #4]
20001806:	681b      	ldr	r3, [r3, #0]
20001808:	f103 0304 	add.w	r3, r3, #4
2000180c:	4618      	mov	r0, r3
2000180e:	f04f 0101 	mov.w	r1, #1
20001812:	f7ff fb4f 	bl	20000eb4 <clear_bit_reg8>
        }
    }
}
20001816:	f107 0718 	add.w	r7, r7, #24
2000181a:	46bd      	mov	sp, r7
2000181c:	bd80      	pop	{r7, pc}
2000181e:	bf00      	nop

20001820 <__libc_init_array>:
20001820:	b570      	push	{r4, r5, r6, lr}
20001822:	f641 2608 	movw	r6, #6664	; 0x1a08
20001826:	f641 2508 	movw	r5, #6664	; 0x1a08
2000182a:	f2c2 0600 	movt	r6, #8192	; 0x2000
2000182e:	f2c2 0500 	movt	r5, #8192	; 0x2000
20001832:	1b76      	subs	r6, r6, r5
20001834:	10b6      	asrs	r6, r6, #2
20001836:	d006      	beq.n	20001846 <__libc_init_array+0x26>
20001838:	2400      	movs	r4, #0
2000183a:	f855 3024 	ldr.w	r3, [r5, r4, lsl #2]
2000183e:	3401      	adds	r4, #1
20001840:	4798      	blx	r3
20001842:	42a6      	cmp	r6, r4
20001844:	d8f9      	bhi.n	2000183a <__libc_init_array+0x1a>
20001846:	f641 2508 	movw	r5, #6664	; 0x1a08
2000184a:	f641 260c 	movw	r6, #6668	; 0x1a0c
2000184e:	f2c2 0500 	movt	r5, #8192	; 0x2000
20001852:	f2c2 0600 	movt	r6, #8192	; 0x2000
20001856:	1b76      	subs	r6, r6, r5
20001858:	f000 f8ca 	bl	200019f0 <_init>
2000185c:	10b6      	asrs	r6, r6, #2
2000185e:	d006      	beq.n	2000186e <__libc_init_array+0x4e>
20001860:	2400      	movs	r4, #0
20001862:	f855 3024 	ldr.w	r3, [r5, r4, lsl #2]
20001866:	3401      	adds	r4, #1
20001868:	4798      	blx	r3
2000186a:	42a6      	cmp	r6, r4
2000186c:	d8f9      	bhi.n	20001862 <__libc_init_array+0x42>
2000186e:	bd70      	pop	{r4, r5, r6, pc}
20001870:	6c655723 	.word	0x6c655723
20001874:	656d6f63 	.word	0x656d6f63
20001878:	206f7420 	.word	0x206f7420
2000187c:	72616d53 	.word	0x72616d53
20001880:	73754674 	.word	0x73754674
20001884:	326e6f69 	.word	0x326e6f69
20001888:	52202d20 	.word	0x52202d20
2000188c:	696e6e75 	.word	0x696e6e75
20001890:	4820676e 	.word	0x4820676e
20001894:	69467865 	.word	0x69467865
20001898:	2330656c 	.word	0x2330656c
2000189c:	00000d0a 	.word	0x00000d0a
200018a0:	656c6553 	.word	0x656c6553
200018a4:	74207463 	.word	0x74207463
200018a8:	62206568 	.word	0x62206568
200018ac:	776f6c65 	.word	0x776f6c65
200018b0:	74706f20 	.word	0x74706f20
200018b4:	0a6e6f69 	.word	0x0a6e6f69
200018b8:	0000000d 	.word	0x0000000d
200018bc:	52202e31 	.word	0x52202e31
200018c0:	48206e75 	.word	0x48206e75
200018c4:	46207865 	.word	0x46207865
200018c8:	31656c69 	.word	0x31656c69
200018cc:	6f726620 	.word	0x6f726620
200018d0:	5365206d 	.word	0x5365206d
200018d4:	0a4d4152 	.word	0x0a4d4152
200018d8:	0000000d 	.word	0x0000000d
200018dc:	52202e32 	.word	0x52202e32
200018e0:	48206e75 	.word	0x48206e75
200018e4:	46207865 	.word	0x46207865
200018e8:	32656c69 	.word	0x32656c69
200018ec:	6f726620 	.word	0x6f726620
200018f0:	5365206d 	.word	0x5365206d
200018f4:	0a4d4152 	.word	0x0a4d4152
200018f8:	0000000d 	.word	0x0000000d
200018fc:	52202e33 	.word	0x52202e33
20001900:	48206e75 	.word	0x48206e75
20001904:	46207865 	.word	0x46207865
20001908:	33656c69 	.word	0x33656c69
2000190c:	6f726620 	.word	0x6f726620
20001910:	5365206d 	.word	0x5365206d
20001914:	0a4d4152 	.word	0x0a4d4152
20001918:	0000000d 	.word	0x0000000d
2000191c:	52202e34 	.word	0x52202e34
20001920:	48206e75 	.word	0x48206e75
20001924:	46207865 	.word	0x46207865
20001928:	34656c69 	.word	0x34656c69
2000192c:	6f726620 	.word	0x6f726620
20001930:	5365206d 	.word	0x5365206d
20001934:	0a4d4152 	.word	0x0a4d4152
20001938:	0000000d 	.word	0x0000000d
2000193c:	52202e35 	.word	0x52202e35
20001940:	48206e75 	.word	0x48206e75
20001944:	46207865 	.word	0x46207865
20001948:	35656c69 	.word	0x35656c69
2000194c:	6f726620 	.word	0x6f726620
20001950:	4e65206d 	.word	0x4e65206d
20001954:	0d0a4d56 	.word	0x0d0a4d56
20001958:	00000000 	.word	0x00000000
2000195c:	75520d0a 	.word	0x75520d0a
20001960:	6e696e6e 	.word	0x6e696e6e
20001964:	65482067 	.word	0x65482067
20001968:	69462078 	.word	0x69462078
2000196c:	0a31656c 	.word	0x0a31656c
20001970:	0000000d 	.word	0x0000000d
20001974:	75520d0a 	.word	0x75520d0a
20001978:	6e696e6e 	.word	0x6e696e6e
2000197c:	65482067 	.word	0x65482067
20001980:	69462078 	.word	0x69462078
20001984:	0a32656c 	.word	0x0a32656c
20001988:	0000000d 	.word	0x0000000d
2000198c:	75520d0a 	.word	0x75520d0a
20001990:	6e696e6e 	.word	0x6e696e6e
20001994:	65482067 	.word	0x65482067
20001998:	69462078 	.word	0x69462078
2000199c:	0a33656c 	.word	0x0a33656c
200019a0:	0000000d 	.word	0x0000000d
200019a4:	75520d0a 	.word	0x75520d0a
200019a8:	6e696e6e 	.word	0x6e696e6e
200019ac:	65482067 	.word	0x65482067
200019b0:	69462078 	.word	0x69462078
200019b4:	0a34656c 	.word	0x0a34656c
200019b8:	0000000d 	.word	0x0000000d
200019bc:	75520d0a 	.word	0x75520d0a
200019c0:	6e696e6e 	.word	0x6e696e6e
200019c4:	65482067 	.word	0x65482067
200019c8:	69462078 	.word	0x69462078
200019cc:	0a35656c 	.word	0x0a35656c
200019d0:	0000000d 	.word	0x0000000d
200019d4:	6f636e49 	.word	0x6f636e49
200019d8:	63657272 	.word	0x63657272
200019dc:	706f2074 	.word	0x706f2074
200019e0:	6e6f6974 	.word	0x6e6f6974
200019e4:	00000d0a 	.word	0x00000d0a

200019e8 <C.19.3551>:
200019e8:	01000100 03030202                       ........

200019f0 <_init>:
200019f0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
200019f2:	bf00      	nop
200019f4:	bcf8      	pop	{r3, r4, r5, r6, r7}
200019f6:	bc08      	pop	{r3}
200019f8:	469e      	mov	lr, r3
200019fa:	4770      	bx	lr

200019fc <_fini>:
200019fc:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
200019fe:	bf00      	nop
20001a00:	bcf8      	pop	{r3, r4, r5, r6, r7}
20001a02:	bc08      	pop	{r3}
20001a04:	469e      	mov	lr, r3
20001a06:	4770      	bx	lr

20001a08 <__frame_dummy_init_array_entry>:
20001a08:	09c5 2000                                   ... 

20001a0c <__do_global_dtors_aux_fini_array_entry>:
20001a0c:	09b1 2000                                   ... 
