
eNVM_to_SRAM_image3:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .vector_table 00000190  00000000  00000000  00008000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .boot_code    00000280  00000190  00000190  00008190  2**4
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  2 .text         00000db0  00000410  00000410  00008410  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  3 .data         00000020  00000000  000011c0  00010000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  4 .bss          00000090  00000020  00000020  00010020  2**2
                  ALLOC
  5 .heap         00006f50  000000b0  000011e0  000100b0  2**0
                  ALLOC
  6 .stack        00001000  00007000  000011e0  00017000  2**0
                  ALLOC
  7 .comment      00000102  00000000  00000000  00010020  2**0
                  CONTENTS, READONLY
  8 .debug_aranges 000002b8  00000000  00000000  00010122  2**0
                  CONTENTS, READONLY, DEBUGGING
  9 .debug_pubnames 000007b9  00000000  00000000  000103da  2**0
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_info   000075b0  00000000  00000000  00010b93  2**0
                  CONTENTS, READONLY, DEBUGGING
 11 .debug_abbrev 00000b0f  00000000  00000000  00018143  2**0
                  CONTENTS, READONLY, DEBUGGING
 12 .debug_line   0000158b  00000000  00000000  00018c52  2**0
                  CONTENTS, READONLY, DEBUGGING
 13 .debug_frame  000006fc  00000000  00000000  0001a1e0  2**2
                  CONTENTS, READONLY, DEBUGGING
 14 .debug_str    000030b9  00000000  00000000  0001a8dc  2**0
                  CONTENTS, READONLY, DEBUGGING
 15 .debug_loc    00001182  00000000  00000000  0001d995  2**0
                  CONTENTS, READONLY, DEBUGGING
 16 .ARM.attributes 00000025  00000000  00000000  0001eb17  2**0
                  CONTENTS, READONLY
 17 .debug_ranges 00000eb8  00000000  00000000  0001eb3c  2**0
                  CONTENTS, READONLY, DEBUGGING

Disassembly of section .text:

00000410 <__do_global_dtors_aux>:
     410:	f240 0320 	movw	r3, #32
     414:	f2c0 0300 	movt	r3, #0
     418:	781a      	ldrb	r2, [r3, #0]
     41a:	b90a      	cbnz	r2, 420 <__do_global_dtors_aux+0x10>
     41c:	2001      	movs	r0, #1
     41e:	7018      	strb	r0, [r3, #0]
     420:	4770      	bx	lr
     422:	bf00      	nop

00000424 <frame_dummy>:
     424:	f240 0000 	movw	r0, #0
     428:	f2c0 0000 	movt	r0, #0
     42c:	b508      	push	{r3, lr}
     42e:	6803      	ldr	r3, [r0, #0]
     430:	b12b      	cbz	r3, 43e <frame_dummy+0x1a>
     432:	f240 0300 	movw	r3, #0
     436:	f2c0 0300 	movt	r3, #0
     43a:	b103      	cbz	r3, 43e <frame_dummy+0x1a>
     43c:	4798      	blx	r3
     43e:	bd08      	pop	{r3, pc}

00000440 <main>:
     440:	b580      	push	{r7, lr}
     442:	b082      	sub	sp, #8
     444:	af00      	add	r7, sp, #0
     446:	f04f 0300 	mov.w	r3, #0
     44a:	607b      	str	r3, [r7, #4]
     44c:	f240 0024 	movw	r0, #36	; 0x24
     450:	f2c0 0000 	movt	r0, #0
     454:	f44f 4161 	mov.w	r1, #57600	; 0xe100
     458:	f04f 0203 	mov.w	r2, #3
     45c:	f000 fb88 	bl	b70 <MSS_UART_init>
     460:	f000 fbb6 	bl	bd0 <MSS_GPIO_init>
     464:	f04f 0000 	mov.w	r0, #0
     468:	f04f 0105 	mov.w	r1, #5
     46c:	f000 fbfc 	bl	c68 <MSS_GPIO_config>
     470:	f04f 0001 	mov.w	r0, #1
     474:	f04f 0105 	mov.w	r1, #5
     478:	f000 fbf6 	bl	c68 <MSS_GPIO_config>
     47c:	f04f 0002 	mov.w	r0, #2
     480:	f04f 0105 	mov.w	r1, #5
     484:	f000 fbf0 	bl	c68 <MSS_GPIO_config>
     488:	f04f 0003 	mov.w	r0, #3
     48c:	f04f 0105 	mov.w	r1, #5
     490:	f000 fbea 	bl	c68 <MSS_GPIO_config>
     494:	f04f 0004 	mov.w	r0, #4
     498:	f04f 0105 	mov.w	r1, #5
     49c:	f000 fbe4 	bl	c68 <MSS_GPIO_config>
     4a0:	f04f 0008 	mov.w	r0, #8
     4a4:	f04f 0105 	mov.w	r1, #5
     4a8:	f000 fbde 	bl	c68 <MSS_GPIO_config>
     4ac:	f04f 0009 	mov.w	r0, #9
     4b0:	f04f 0105 	mov.w	r1, #5
     4b4:	f000 fbd8 	bl	c68 <MSS_GPIO_config>
     4b8:	f04f 000a 	mov.w	r0, #10
     4bc:	f04f 0105 	mov.w	r1, #5
     4c0:	f000 fbd2 	bl	c68 <MSS_GPIO_config>
     4c4:	f04f 0064 	mov.w	r0, #100	; 0x64
     4c8:	f000 f83e 	bl	548 <delay>
     4cc:	f04f 0300 	mov.w	r3, #0
     4d0:	607b      	str	r3, [r7, #4]
     4d2:	f240 0024 	movw	r0, #36	; 0x24
     4d6:	f2c0 0000 	movt	r0, #0
     4da:	f640 71d4 	movw	r1, #4052	; 0xfd4
     4de:	f2c0 0100 	movt	r1, #0
     4e2:	f04f 0210 	mov.w	r2, #16
     4e6:	f000 f841 	bl	56c <MSS_UART_polled_tx>
     4ea:	687b      	ldr	r3, [r7, #4]
     4ec:	f103 0301 	add.w	r3, r3, #1
     4f0:	607b      	str	r3, [r7, #4]
     4f2:	f04f 0004 	mov.w	r0, #4
     4f6:	f04f 0100 	mov.w	r1, #0
     4fa:	f000 fbbf 	bl	c7c <MSS_GPIO_set_output>
     4fe:	f640 5040 	movw	r0, #3392	; 0xd40
     502:	f2c0 0003 	movt	r0, #3
     506:	f000 f81f 	bl	548 <delay>
     50a:	f04f 0004 	mov.w	r0, #4
     50e:	f04f 0101 	mov.w	r1, #1
     512:	f000 fbb3 	bl	c7c <MSS_GPIO_set_output>
     516:	f640 5040 	movw	r0, #3392	; 0xd40
     51a:	f2c0 0003 	movt	r0, #3
     51e:	f000 f813 	bl	548 <delay>
     522:	f04f 0008 	mov.w	r0, #8
     526:	f04f 0100 	mov.w	r1, #0
     52a:	f000 fba7 	bl	c7c <MSS_GPIO_set_output>
     52e:	f640 5040 	movw	r0, #3392	; 0xd40
     532:	f2c0 0003 	movt	r0, #3
     536:	f000 f807 	bl	548 <delay>
     53a:	f04f 0008 	mov.w	r0, #8
     53e:	f04f 0101 	mov.w	r1, #1
     542:	f000 fb9b 	bl	c7c <MSS_GPIO_set_output>
     546:	e7c4      	b.n	4d2 <main+0x92>

00000548 <delay>:
     548:	b480      	push	{r7}
     54a:	b083      	sub	sp, #12
     54c:	af00      	add	r7, sp, #0
     54e:	6078      	str	r0, [r7, #4]
     550:	e003      	b.n	55a <delay+0x12>
     552:	687b      	ldr	r3, [r7, #4]
     554:	f103 33ff 	add.w	r3, r3, #4294967295
     558:	607b      	str	r3, [r7, #4]
     55a:	687b      	ldr	r3, [r7, #4]
     55c:	2b00      	cmp	r3, #0
     55e:	dcf8      	bgt.n	552 <delay+0xa>
     560:	f107 070c 	add.w	r7, r7, #12
     564:	46bd      	mov	sp, r7
     566:	bc80      	pop	{r7}
     568:	4770      	bx	lr
     56a:	bf00      	nop

0000056c <MSS_UART_polled_tx>:

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(pbuff != ( (uint8_t *)0));
    ASSERT(tx_size > 0u);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
     56c:	f240 0364 	movw	r3, #100	; 0x64
     570:	f2c0 0300 	movt	r3, #0
     574:	4298      	cmp	r0, r3
(
    mss_uart_instance_t * this_uart,
    const uint8_t * pbuff,
    uint32_t tx_size
)
{
     576:	e92d 05f0 	stmdb	sp!, {r4, r5, r6, r7, r8, sl}

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(pbuff != ( (uint8_t *)0));
    ASSERT(tx_size > 0u);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
     57a:	d008      	beq.n	58e <MSS_UART_polled_tx+0x22>
     57c:	f240 0c24 	movw	ip, #36	; 0x24
     580:	f2c0 0c00 	movt	ip, #0
     584:	4560      	cmp	r0, ip
     586:	d002      	beq.n	58e <MSS_UART_polled_tx+0x22>
                /* Calculate the number of untransmitted bytes remaining. */
                tx_size -= size_sent;
            }
        } while(tx_size);
    }
}
     588:	e8bd 05f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, sl}
     58c:	4770      	bx	lr

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(pbuff != ( (uint8_t *)0));
    ASSERT(tx_size > 0u);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
     58e:	1e0b      	subs	r3, r1, #0
     590:	bf18      	it	ne
     592:	2301      	movne	r3, #1
     594:	2a00      	cmp	r2, #0
     596:	bf0c      	ite	eq
     598:	2300      	moveq	r3, #0
     59a:	f003 0301 	andne.w	r3, r3, #1
     59e:	2b00      	cmp	r3, #0
     5a0:	d0f2      	beq.n	588 <MSS_UART_polled_tx+0x1c>
     5a2:	f890 800d 	ldrb.w	r8, [r0, #13]
         /* Remain in this loop until the entire input buffer
          * has been transferred to the UART.
          */
        do {
            /* Read the Line Status Register and update the sticky record */
            status = this_uart->hw_reg->LSR;
     5a6:	f8d0 a000 	ldr.w	sl, [r0]
     5aa:	2500      	movs	r5, #0
     5ac:	f89a c014 	ldrb.w	ip, [sl, #20]
            this_uart->status |= status;
     5b0:	ea48 080c 	orr.w	r8, r8, ip

            /* Check if TX FIFO is empty. */
            if(status & MSS_UART_THRE)
     5b4:	f01c 0f20 	tst.w	ip, #32
          * has been transferred to the UART.
          */
        do {
            /* Read the Line Status Register and update the sticky record */
            status = this_uart->hw_reg->LSR;
            this_uart->status |= status;
     5b8:	f880 800d 	strb.w	r8, [r0, #13]

            /* Check if TX FIFO is empty. */
            if(status & MSS_UART_THRE)
     5bc:	d023      	beq.n	606 <MSS_UART_polled_tx+0x9a>
            {
                uint32_t fill_size = TX_FIFO_SIZE;

                /* Calculate the number of bytes to transmit. */
                if(tx_size < TX_FIFO_SIZE)
     5be:	2a0f      	cmp	r2, #15
     5c0:	d924      	bls.n	60c <MSS_UART_polled_tx+0xa0>
     5c2:	2710      	movs	r7, #16

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     5c4:	5d4e      	ldrb	r6, [r1, r5]
            if(status & MSS_UART_THRE)
            {
                uint32_t fill_size = TX_FIFO_SIZE;

                /* Calculate the number of bytes to transmit. */
                if(tx_size < TX_FIFO_SIZE)
     5c6:	6804      	ldr	r4, [r0, #0]
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     5c8:	2301      	movs	r3, #1
     5ca:	f107 3cff 	add.w	ip, r7, #4294967295
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     5ce:	7026      	strb	r6, [r4, #0]
     5d0:	ea0c 0603 	and.w	r6, ip, r3
                    char_idx++;
     5d4:	eb05 0c03 	add.w	ip, r5, r3
     5d8:	194d      	adds	r5, r1, r5
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     5da:	42bb      	cmp	r3, r7
     5dc:	d211      	bcs.n	602 <MSS_UART_polled_tx+0x96>
     5de:	b136      	cbz	r6, 5ee <MSS_UART_polled_tx+0x82>
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     5e0:	5cee      	ldrb	r6, [r5, r3]
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     5e2:	2302      	movs	r3, #2
     5e4:	42bb      	cmp	r3, r7
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     5e6:	7026      	strb	r6, [r4, #0]
                    char_idx++;
     5e8:	f10c 0c01 	add.w	ip, ip, #1
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     5ec:	d209      	bcs.n	602 <MSS_UART_polled_tx+0x96>
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     5ee:	5cee      	ldrb	r6, [r5, r3]
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     5f0:	3301      	adds	r3, #1
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     5f2:	7026      	strb	r6, [r4, #0]
     5f4:	5cee      	ldrb	r6, [r5, r3]
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     5f6:	3301      	adds	r3, #1
     5f8:	42bb      	cmp	r3, r7
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     5fa:	7026      	strb	r6, [r4, #0]
                    char_idx++;
     5fc:	f10c 0c02 	add.w	ip, ip, #2
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     600:	d3f5      	bcc.n	5ee <MSS_UART_polled_tx+0x82>
     602:	4665      	mov	r5, ip
                    this_uart->hw_reg->THR = pbuff[char_idx];
                    char_idx++;
                }

                /* Calculate the number of untransmitted bytes remaining. */
                tx_size -= size_sent;
     604:	1ad2      	subs	r2, r2, r3
            }
        } while(tx_size);
     606:	2a00      	cmp	r2, #0
     608:	d1d0      	bne.n	5ac <MSS_UART_polled_tx+0x40>
     60a:	e7bd      	b.n	588 <MSS_UART_polled_tx+0x1c>
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     60c:	b10a      	cbz	r2, 612 <MSS_UART_polled_tx+0xa6>
     60e:	4617      	mov	r7, r2
     610:	e7d8      	b.n	5c4 <MSS_UART_polled_tx+0x58>
     612:	4613      	mov	r3, r2
                    this_uart->hw_reg->THR = pbuff[char_idx];
                    char_idx++;
                }

                /* Calculate the number of untransmitted bytes remaining. */
                tx_size -= size_sent;
     614:	1ad2      	subs	r2, r2, r3
     616:	e7f6      	b.n	606 <MSS_UART_polled_tx+0x9a>

00000618 <MSS_UART_isr>:
{
    uint8_t iirf;

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
     618:	f240 0364 	movw	r3, #100	; 0x64
     61c:	f2c0 0300 	movt	r3, #0
     620:	4298      	cmp	r0, r3
static void
MSS_UART_isr
(
    mss_uart_instance_t * this_uart
)
{
     622:	b510      	push	{r4, lr}
     624:	4604      	mov	r4, r0
    uint8_t iirf;

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
     626:	d006      	beq.n	636 <MSS_UART_isr+0x1e>
     628:	f240 0024 	movw	r0, #36	; 0x24
     62c:	f2c0 0000 	movt	r0, #0
     630:	4284      	cmp	r4, r0
     632:	d000      	beq.n	636 <MSS_UART_isr+0x1e>
     634:	bd10      	pop	{r4, pc}
    {
        iirf = this_uart->hw_reg->IIR & IIRF_MASK;
     636:	6822      	ldr	r2, [r4, #0]
     638:	7a11      	ldrb	r1, [r2, #8]

        switch (iirf)
     63a:	f001 0c0f 	and.w	ip, r1, #15
     63e:	f1bc 0f0c 	cmp.w	ip, #12
     642:	d8f7      	bhi.n	634 <MSS_UART_isr+0x1c>
     644:	a101      	add	r1, pc, #4	; (adr r1, 64c <MSS_UART_isr+0x34>)
     646:	f851 f02c 	ldr.w	pc, [r1, ip, lsl #2]
     64a:	bf00      	nop
     64c:	0000069d 	.word	0x0000069d
     650:	00000635 	.word	0x00000635
     654:	00000695 	.word	0x00000695
     658:	000006a5 	.word	0x000006a5
     65c:	0000068d 	.word	0x0000068d
     660:	00000635 	.word	0x00000635
     664:	00000681 	.word	0x00000681
     668:	00000635 	.word	0x00000635
     66c:	00000635 	.word	0x00000635
     670:	00000635 	.word	0x00000635
     674:	00000635 	.word	0x00000635
     678:	00000635 	.word	0x00000635
     67c:	0000068d 	.word	0x0000068d
            break;

            case IIRF_RX_LINE_STATUS:  /* Line Status Interrupt */
            {
                ASSERT(NULL_HANDLER != this_uart->linests_handler);
                if(NULL_HANDLER != this_uart->linests_handler)
     680:	69e3      	ldr	r3, [r4, #28]
     682:	2b00      	cmp	r3, #0
     684:	d0d6      	beq.n	634 <MSS_UART_isr+0x1c>
                {
                   (*(this_uart->linests_handler))(this_uart);
     686:	4620      	mov	r0, r4
     688:	4798      	blx	r3
     68a:	bd10      	pop	{r4, pc}

            case IIRF_RX_DATA:      /* Received Data Available */
            case IIRF_DATA_TIMEOUT: /* Received Data Timed-out */
            {
                ASSERT(NULL_HANDLER != this_uart->rx_handler);
                if(NULL_HANDLER != this_uart->rx_handler)
     68c:	6a23      	ldr	r3, [r4, #32]
     68e:	2b00      	cmp	r3, #0
     690:	d1f9      	bne.n	686 <MSS_UART_isr+0x6e>
     692:	e7cf      	b.n	634 <MSS_UART_isr+0x1c>
            break;

            case IIRF_THRE: /* Transmitter Holding Register Empty */
            {
                ASSERT(NULL_HANDLER != this_uart->tx_handler);
                if(NULL_HANDLER != this_uart->tx_handler)
     694:	6a63      	ldr	r3, [r4, #36]	; 0x24
     696:	2b00      	cmp	r3, #0
     698:	d1f5      	bne.n	686 <MSS_UART_isr+0x6e>
     69a:	e7cb      	b.n	634 <MSS_UART_isr+0x1c>
        switch (iirf)
        {
            case IIRF_MODEM_STATUS:  /* Modem status interrupt */
            {
                ASSERT(NULL_HANDLER != this_uart->modemsts_handler);
                if(NULL_HANDLER != this_uart->modemsts_handler)
     69c:	6aa3      	ldr	r3, [r4, #40]	; 0x28
     69e:	2b00      	cmp	r3, #0
     6a0:	d1f1      	bne.n	686 <MSS_UART_isr+0x6e>
     6a2:	e7c7      	b.n	634 <MSS_UART_isr+0x1c>
            case IIRF_MMI:
            {
                /* Identify multimode interrupts and handle */

                /* Receiver time-out interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,ERTOI))
     6a4:	3228      	adds	r2, #40	; 0x28
{
    return (HW_REG_BIT(reg,bit));
}
static __INLINE uint8_t read_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    return (HW_REG_BIT(reg,bit));
     6a6:	f022 407f 	bic.w	r0, r2, #4278190080	; 0xff000000
     6aa:	f420 0370 	bic.w	r3, r0, #15728640	; 0xf00000
     6ae:	f002 4170 	and.w	r1, r2, #4026531840	; 0xf0000000
     6b2:	0158      	lsls	r0, r3, #5
     6b4:	f101 7c00 	add.w	ip, r1, #33554432	; 0x2000000
     6b8:	f85c 3000 	ldr.w	r3, [ip, r0]
     6bc:	f013 0fff 	tst.w	r3, #255	; 0xff
     6c0:	d005      	beq.n	6ce <MSS_UART_isr+0xb6>
                {
                    ASSERT(NULL_HANDLER != this_uart->rto_handler);
                    if(NULL_HANDLER != this_uart->rto_handler)
     6c2:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
     6c4:	b11b      	cbz	r3, 6ce <MSS_UART_isr+0xb6>
                    {
                        (*(this_uart->rto_handler))(this_uart);
     6c6:	4620      	mov	r0, r4
     6c8:	4798      	blx	r3
     6ca:	6822      	ldr	r2, [r4, #0]
     6cc:	3228      	adds	r2, #40	; 0x28
     6ce:	f002 4070 	and.w	r0, r2, #4026531840	; 0xf0000000
     6d2:	f022 4c7f 	bic.w	ip, r2, #4278190080	; 0xff000000
     6d6:	f100 7300 	add.w	r3, r0, #33554432	; 0x2000000
     6da:	f42c 0170 	bic.w	r1, ip, #15728640	; 0xf00000
     6de:	1d18      	adds	r0, r3, #4
     6e0:	0149      	lsls	r1, r1, #5
     6e2:	5843      	ldr	r3, [r0, r1]
                    }
                }
                /* NACK interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,ENACKI))
     6e4:	f013 0fff 	tst.w	r3, #255	; 0xff
     6e8:	d005      	beq.n	6f6 <MSS_UART_isr+0xde>
                {
                    ASSERT(NULL_HANDLER != this_uart->nack_handler);
                    if(NULL_HANDLER != this_uart->nack_handler)
     6ea:	6b23      	ldr	r3, [r4, #48]	; 0x30
     6ec:	b11b      	cbz	r3, 6f6 <MSS_UART_isr+0xde>
                    {
                        (*(this_uart->nack_handler))(this_uart);
     6ee:	4620      	mov	r0, r4
     6f0:	4798      	blx	r3
     6f2:	6822      	ldr	r2, [r4, #0]
     6f4:	3228      	adds	r2, #40	; 0x28
     6f6:	f002 4370 	and.w	r3, r2, #4026531840	; 0xf0000000
     6fa:	f022 4c7f 	bic.w	ip, r2, #4278190080	; 0xff000000
     6fe:	f103 7000 	add.w	r0, r3, #33554432	; 0x2000000
     702:	f42c 0170 	bic.w	r1, ip, #15728640	; 0xf00000
     706:	3008      	adds	r0, #8
     708:	0149      	lsls	r1, r1, #5
     70a:	5843      	ldr	r3, [r0, r1]
                    }
                }

                /* PID parity error interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,EPID_PEI))
     70c:	f013 0fff 	tst.w	r3, #255	; 0xff
     710:	d005      	beq.n	71e <MSS_UART_isr+0x106>
                {
                    ASSERT(NULL_HANDLER != this_uart->pid_pei_handler);
                    if(NULL_HANDLER != this_uart->pid_pei_handler)
     712:	6b63      	ldr	r3, [r4, #52]	; 0x34
     714:	b11b      	cbz	r3, 71e <MSS_UART_isr+0x106>
                    {
                        (*(this_uart->pid_pei_handler))(this_uart);
     716:	4620      	mov	r0, r4
     718:	4798      	blx	r3
     71a:	6822      	ldr	r2, [r4, #0]
     71c:	3228      	adds	r2, #40	; 0x28
     71e:	f002 4370 	and.w	r3, r2, #4026531840	; 0xf0000000
     722:	f022 4c7f 	bic.w	ip, r2, #4278190080	; 0xff000000
     726:	f42c 0070 	bic.w	r0, ip, #15728640	; 0xf00000
     72a:	f103 7300 	add.w	r3, r3, #33554432	; 0x2000000
     72e:	330c      	adds	r3, #12
     730:	0141      	lsls	r1, r0, #5
     732:	5858      	ldr	r0, [r3, r1]
                    }
                }

                /* LIN break detection interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,ELINBI))
     734:	f010 0fff 	tst.w	r0, #255	; 0xff
     738:	d005      	beq.n	746 <MSS_UART_isr+0x12e>
                {
                    ASSERT(NULL_HANDLER != this_uart->break_handler);
                    if(NULL_HANDLER != this_uart->break_handler)
     73a:	6ba3      	ldr	r3, [r4, #56]	; 0x38
     73c:	b11b      	cbz	r3, 746 <MSS_UART_isr+0x12e>
                    {
                        (*(this_uart->break_handler))(this_uart);
     73e:	4620      	mov	r0, r4
     740:	4798      	blx	r3
     742:	6822      	ldr	r2, [r4, #0]
     744:	3228      	adds	r2, #40	; 0x28
     746:	f022 4c7f 	bic.w	ip, r2, #4278190080	; 0xff000000
     74a:	f002 4170 	and.w	r1, r2, #4026531840	; 0xf0000000
     74e:	f101 7200 	add.w	r2, r1, #33554432	; 0x2000000
     752:	f42c 0370 	bic.w	r3, ip, #15728640	; 0xf00000
     756:	3210      	adds	r2, #16
     758:	0158      	lsls	r0, r3, #5
     75a:	5811      	ldr	r1, [r2, r0]
                    }
                }

                /* LIN Sync detection interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,ELINSI))
     75c:	f011 0fff 	tst.w	r1, #255	; 0xff
     760:	f43f af68 	beq.w	634 <MSS_UART_isr+0x1c>
                {
                    ASSERT(NULL_HANDLER != this_uart->sync_handler);
                    if(NULL_HANDLER != this_uart->sync_handler)
     764:	6be3      	ldr	r3, [r4, #60]	; 0x3c
     766:	2b00      	cmp	r3, #0
     768:	f43f af64 	beq.w	634 <MSS_UART_isr+0x1c>
                    {
                        (*(this_uart->sync_handler))(this_uart);
     76c:	4620      	mov	r0, r4
     76e:	4798      	blx	r3
     770:	e760      	b.n	634 <MSS_UART_isr+0x1c>
     772:	bf00      	nop

00000774 <UART1_IRQHandler>:
#if defined(__GNUC__)
__attribute__((__interrupt__)) void UART1_IRQHandler(void)
#else
void UART1_IRQHandler(void)
#endif
{
     774:	4668      	mov	r0, sp
     776:	f020 0107 	bic.w	r1, r0, #7
     77a:	468d      	mov	sp, r1
     77c:	b501      	push	{r0, lr}
    MSS_UART_isr(&g_mss_uart1);
     77e:	f240 0024 	movw	r0, #36	; 0x24
     782:	f2c0 0000 	movt	r0, #0
     786:	f7ff ff47 	bl	618 <MSS_UART_isr>
}
     78a:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
     78e:	4685      	mov	sp, r0
     790:	4770      	bx	lr
     792:	bf00      	nop

00000794 <UART0_IRQHandler>:
#if defined(__GNUC__)
__attribute__((__interrupt__)) void UART0_IRQHandler(void)
#else
void UART0_IRQHandler(void)
#endif
{
     794:	4668      	mov	r0, sp
     796:	f020 0107 	bic.w	r1, r0, #7
     79a:	468d      	mov	sp, r1
     79c:	b501      	push	{r0, lr}
    MSS_UART_isr(&g_mss_uart0);
     79e:	f240 0064 	movw	r0, #100	; 0x64
     7a2:	f2c0 0000 	movt	r0, #0
     7a6:	f7ff ff37 	bl	618 <MSS_UART_isr>
}
     7aa:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
     7ae:	4685      	mov	sp, r0
     7b0:	4770      	bx	lr
     7b2:	bf00      	nop

000007b4 <default_tx_handler>:

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(( (uint8_t *)0 ) != this_uart->tx_buffer);
    ASSERT(0u < this_uart->tx_buff_size);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
     7b4:	f240 0364 	movw	r3, #100	; 0x64
     7b8:	f2c0 0300 	movt	r3, #0
     7bc:	4298      	cmp	r0, r3
static void
default_tx_handler
(
    mss_uart_instance_t * this_uart
)
{
     7be:	b470      	push	{r4, r5, r6}

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(( (uint8_t *)0 ) != this_uart->tx_buffer);
    ASSERT(0u < this_uart->tx_buff_size);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
     7c0:	d007      	beq.n	7d2 <default_tx_handler+0x1e>
     7c2:	f240 0124 	movw	r1, #36	; 0x24
     7c6:	f2c0 0100 	movt	r1, #0
     7ca:	4288      	cmp	r0, r1
     7cc:	d001      	beq.n	7d2 <default_tx_handler+0x1e>
            this_uart->tx_buff_size = TX_COMPLETE;
            /* disables TX interrupt */
            clear_bit_reg8(&this_uart->hw_reg->IER,ETBEI);
        }
    }
}
     7ce:	bc70      	pop	{r4, r5, r6}
     7d0:	4770      	bx	lr
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(( (uint8_t *)0 ) != this_uart->tx_buffer);
    ASSERT(0u < this_uart->tx_buff_size);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
       (((uint8_t *)0 ) != this_uart->tx_buffer) &&
     7d2:	6904      	ldr	r4, [r0, #16]
     7d4:	2c00      	cmp	r4, #0
     7d6:	d0fa      	beq.n	7ce <default_tx_handler+0x1a>
       (0u < this_uart->tx_buff_size))
     7d8:	6943      	ldr	r3, [r0, #20]
     7da:	2b00      	cmp	r3, #0
     7dc:	d0f7      	beq.n	7ce <default_tx_handler+0x1a>
    {
        /* Read the Line Status Register and update the sticky record. */
        status = this_uart->hw_reg->LSR;
     7de:	6801      	ldr	r1, [r0, #0]
        this_uart->status |= status;
     7e0:	f890 c00d 	ldrb.w	ip, [r0, #13]
    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
       (((uint8_t *)0 ) != this_uart->tx_buffer) &&
       (0u < this_uart->tx_buff_size))
    {
        /* Read the Line Status Register and update the sticky record. */
        status = this_uart->hw_reg->LSR;
     7e4:	7d0a      	ldrb	r2, [r1, #20]
        this_uart->status |= status;
     7e6:	ea42 0c0c 	orr.w	ip, r2, ip

        /*
         * This function should only be called as a result of a THRE interrupt.
         * Verify that this is true before proceeding to transmit data.
         */
        if(status & MSS_UART_THRE)
     7ea:	f012 0f20 	tst.w	r2, #32
       (((uint8_t *)0 ) != this_uart->tx_buffer) &&
       (0u < this_uart->tx_buff_size))
    {
        /* Read the Line Status Register and update the sticky record. */
        status = this_uart->hw_reg->LSR;
        this_uart->status |= status;
     7ee:	f880 c00d 	strb.w	ip, [r0, #13]

        /*
         * This function should only be called as a result of a THRE interrupt.
         * Verify that this is true before proceeding to transmit data.
         */
        if(status & MSS_UART_THRE)
     7f2:	6982      	ldr	r2, [r0, #24]
     7f4:	d029      	beq.n	84a <default_tx_handler+0x96>
        {
            uint32_t i;
            uint32_t fill_size = TX_FIFO_SIZE;
            uint32_t tx_remain = this_uart->tx_buff_size - this_uart->tx_idx;
     7f6:	1a9d      	subs	r5, r3, r2

            /* Calculate the number of bytes to transmit. */
            if(tx_remain < TX_FIFO_SIZE)
     7f8:	2d0f      	cmp	r5, #15
     7fa:	d938      	bls.n	86e <default_tx_handler+0xba>
     7fc:	2510      	movs	r5, #16
     7fe:	18a4      	adds	r4, r4, r2

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     800:	7826      	ldrb	r6, [r4, #0]
     802:	1e6b      	subs	r3, r5, #1
     804:	700e      	strb	r6, [r1, #0]
     806:	f003 0601 	and.w	r6, r3, #1
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     80a:	2301      	movs	r3, #1
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
                ++this_uart->tx_idx;
     80c:	3201      	adds	r2, #1
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     80e:	429d      	cmp	r5, r3
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
                ++this_uart->tx_idx;
     810:	6182      	str	r2, [r0, #24]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     812:	d919      	bls.n	848 <default_tx_handler+0x94>
     814:	b146      	cbz	r6, 828 <default_tx_handler+0x74>
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     816:	f894 c001 	ldrb.w	ip, [r4, #1]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     81a:	2302      	movs	r3, #2
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
                ++this_uart->tx_idx;
     81c:	3201      	adds	r2, #1
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     81e:	429d      	cmp	r5, r3
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     820:	f881 c000 	strb.w	ip, [r1]
                ++this_uart->tx_idx;
     824:	6182      	str	r2, [r0, #24]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     826:	d90f      	bls.n	848 <default_tx_handler+0x94>
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     828:	f814 c003 	ldrb.w	ip, [r4, r3]
                ++this_uart->tx_idx;
     82c:	3201      	adds	r2, #1

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     82e:	f881 c000 	strb.w	ip, [r1]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     832:	3301      	adds	r3, #1
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
                ++this_uart->tx_idx;
     834:	6182      	str	r2, [r0, #24]

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     836:	f814 c003 	ldrb.w	ip, [r4, r3]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     83a:	3301      	adds	r3, #1
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
                ++this_uart->tx_idx;
     83c:	3201      	adds	r2, #1
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     83e:	429d      	cmp	r5, r3
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     840:	f881 c000 	strb.w	ip, [r1]
                ++this_uart->tx_idx;
     844:	6182      	str	r2, [r0, #24]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     846:	d8ef      	bhi.n	828 <default_tx_handler+0x74>
     848:	6943      	ldr	r3, [r0, #20]
                ++this_uart->tx_idx;
            }
        }

        /* Flag Tx as complete if all data has been pushed into the Tx FIFO. */
        if(this_uart->tx_idx == this_uart->tx_buff_size)
     84a:	429a      	cmp	r2, r3
     84c:	d1bf      	bne.n	7ce <default_tx_handler+0x1a>
        {
            this_uart->tx_buff_size = TX_COMPLETE;
            /* disables TX interrupt */
            clear_bit_reg8(&this_uart->hw_reg->IER,ETBEI);
     84e:	6802      	ldr	r2, [r0, #0]
        }

        /* Flag Tx as complete if all data has been pushed into the Tx FIFO. */
        if(this_uart->tx_idx == this_uart->tx_buff_size)
        {
            this_uart->tx_buff_size = TX_COMPLETE;
     850:	2100      	movs	r1, #0
            /* disables TX interrupt */
            clear_bit_reg8(&this_uart->hw_reg->IER,ETBEI);
     852:	1d13      	adds	r3, r2, #4
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     854:	f023 4c7f 	bic.w	ip, r3, #4278190080	; 0xff000000
     858:	f003 4270 	and.w	r2, r3, #4026531840	; 0xf0000000
     85c:	f102 7300 	add.w	r3, r2, #33554432	; 0x2000000
     860:	f42c 0270 	bic.w	r2, ip, #15728640	; 0xf00000
     864:	3304      	adds	r3, #4
     866:	0152      	lsls	r2, r2, #5
     868:	5099      	str	r1, [r3, r2]
        }

        /* Flag Tx as complete if all data has been pushed into the Tx FIFO. */
        if(this_uart->tx_idx == this_uart->tx_buff_size)
        {
            this_uart->tx_buff_size = TX_COMPLETE;
     86a:	6141      	str	r1, [r0, #20]
     86c:	e7af      	b.n	7ce <default_tx_handler+0x1a>
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     86e:	2d00      	cmp	r5, #0
     870:	d1c5      	bne.n	7fe <default_tx_handler+0x4a>
     872:	e7ea      	b.n	84a <default_tx_handler+0x96>

00000874 <global_init>:
(
    mss_uart_instance_t * this_uart,
    uint32_t baud_rate,
    uint8_t line_config
)
{
     874:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
     878:	f240 0364 	movw	r3, #100	; 0x64
(
    mss_uart_instance_t * this_uart,
    uint32_t baud_rate,
    uint8_t line_config
)
{
     87c:	b08f      	sub	sp, #60	; 0x3c
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
     87e:	f2c0 0300 	movt	r3, #0
(
    mss_uart_instance_t * this_uart,
    uint32_t baud_rate,
    uint8_t line_config
)
{
     882:	920b      	str	r2, [sp, #44]	; 0x2c
    if(this_uart == &g_mss_uart0)
    {
        this_uart->hw_reg = UART0;
        this_uart->irqn = UART0_IRQn;
        /* reset UART0 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART0_SOFTRESET_MASK;
     884:	f248 0200 	movw	r2, #32768	; 0x8000
{
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
     888:	4298      	cmp	r0, r3
    {
        this_uart->hw_reg = UART0;
        this_uart->irqn = UART0_IRQn;
        /* reset UART0 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART0_SOFTRESET_MASK;
     88a:	f2c4 0203 	movt	r2, #16387	; 0x4003
(
    mss_uart_instance_t * this_uart,
    uint32_t baud_rate,
    uint8_t line_config
)
{
     88e:	4604      	mov	r4, r0
     890:	910d      	str	r1, [sp, #52]	; 0x34
    if(this_uart == &g_mss_uart0)
    {
        this_uart->hw_reg = UART0;
        this_uart->irqn = UART0_IRQn;
        /* reset UART0 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART0_SOFTRESET_MASK;
     892:	6c90      	ldr	r0, [r2, #72]	; 0x48

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
     894:	f24e 1100 	movw	r1, #57600	; 0xe100
{
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
     898:	f000 8129 	beq.w	aee <global_init+0x27a>
    else
    {
        this_uart->hw_reg = UART1;
        this_uart->irqn = UART1_IRQn;
        /* Reset UART1 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART1_SOFTRESET_MASK;
     89c:	f440 7780 	orr.w	r7, r0, #256	; 0x100
     8a0:	f2ce 0100 	movt	r1, #57344	; 0xe000
     8a4:	f44f 6600 	mov.w	r6, #2048	; 0x800
     8a8:	6497      	str	r7, [r2, #72]	; 0x48
     8aa:	f8c1 6180 	str.w	r6, [r1, #384]	; 0x180
        /* Clear any previously pended UART1 interrupt */
        NVIC_ClearPendingIRQ(UART1_IRQn);
        /* Take UART1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART1_SOFTRESET_MASK;
     8ae:	6c95      	ldr	r5, [r2, #72]	; 0x48
        /* Take UART0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
    }
    else
    {
        this_uart->hw_reg = UART1;
     8b0:	f240 0100 	movw	r1, #0
        /* Reset UART1 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART1_SOFTRESET_MASK;
        /* Clear any previously pended UART1 interrupt */
        NVIC_ClearPendingIRQ(UART1_IRQn);
        /* Take UART1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART1_SOFTRESET_MASK;
     8b4:	f425 7080 	bic.w	r0, r5, #256	; 0x100
        /* Take UART0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
    }
    else
    {
        this_uart->hw_reg = UART1;
     8b8:	f2c4 0101 	movt	r1, #16385	; 0x4001
        /* Reset UART1 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART1_SOFTRESET_MASK;
        /* Clear any previously pended UART1 interrupt */
        NVIC_ClearPendingIRQ(UART1_IRQn);
        /* Take UART1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART1_SOFTRESET_MASK;
     8bc:	6490      	str	r0, [r2, #72]	; 0x48
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
    }
    else
    {
        this_uart->hw_reg = UART1;
        this_uart->irqn = UART1_IRQn;
     8be:	220b      	movs	r2, #11
     8c0:	7122      	strb	r2, [r4, #4]
        /* Take UART0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
    }
    else
    {
        this_uart->hw_reg = UART1;
     8c2:	6021      	str	r1, [r4, #0]
        /* Take UART1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART1_SOFTRESET_MASK;
    }

    /* disable interrupts */
    this_uart->hw_reg->IER = 0u;
     8c4:	2200      	movs	r2, #0

    /* FIFO configuration */
    this_uart->hw_reg->FCR = (uint8_t)MSS_UART_FIFO_SINGLE_BYTE;
     8c6:	460d      	mov	r5, r1
        /* Take UART1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART1_SOFTRESET_MASK;
    }

    /* disable interrupts */
    this_uart->hw_reg->IER = 0u;
     8c8:	710a      	strb	r2, [r1, #4]
    /* enable RXRDYN and TXRDYN pins. The earlier FCR write to set the TX FIFO
     * trigger level inadvertently disabled the FCR_RXRDY_TXRDYN_EN bit. */
    set_bit_reg8(&this_uart->hw_reg->FCR,RXRDY_TXRDYN_EN);

    /* disable loopback : local * remote */
    clear_bit_reg8(&this_uart->hw_reg->MCR,LOOP);
     8ca:	f101 0610 	add.w	r6, r1, #16

    /* disable interrupts */
    this_uart->hw_reg->IER = 0u;

    /* FIFO configuration */
    this_uart->hw_reg->FCR = (uint8_t)MSS_UART_FIFO_SINGLE_BYTE;
     8ce:	f805 2f08 	strb.w	r2, [r5, #8]!
    clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_TX);
    /* set default RX endian */
    clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_RX);

    /* default AFM : disabled */
    clear_bit_reg8(&this_uart->hw_reg->MM2,EAFM);
     8d2:	f101 0a38 	add.w	sl, r1, #56	; 0x38
     8d6:	f02a 4b7f 	bic.w	fp, sl, #4278190080	; 0xff000000
    /* disable loopback : local * remote */
    clear_bit_reg8(&this_uart->hw_reg->MCR,LOOP);
    clear_bit_reg8(&this_uart->hw_reg->MCR,RLOOP);

    /* set default TX endian */
    clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_TX);
     8da:	f101 0934 	add.w	r9, r1, #52	; 0x34
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     8de:	f025 477f 	bic.w	r7, r5, #4278190080	; 0xff000000
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     8e2:	f026 487f 	bic.w	r8, r6, #4278190080	; 0xff000000
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     8e6:	f005 4570 	and.w	r5, r5, #4026531840	; 0xf0000000
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     8ea:	f006 4670 	and.w	r6, r6, #4026531840	; 0xf0000000
     8ee:	f00a 4a70 	and.w	sl, sl, #4026531840	; 0xf0000000
     8f2:	f8cd a010 	str.w	sl, [sp, #16]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     8f6:	9506      	str	r5, [sp, #24]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     8f8:	f029 407f 	bic.w	r0, r9, #4278190080	; 0xff000000
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     8fc:	f106 7500 	add.w	r5, r6, #33554432	; 0x2000000
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     900:	9003      	str	r0, [sp, #12]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     902:	9501      	str	r5, [sp, #4]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     904:	f009 4970 	and.w	r9, r9, #4026531840	; 0xf0000000
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     908:	9d04      	ldr	r5, [sp, #16]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     90a:	f8cd 901c 	str.w	r9, [sp, #28]
     90e:	f8dd 900c 	ldr.w	r9, [sp, #12]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     912:	f105 7500 	add.w	r5, r5, #33554432	; 0x2000000
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     916:	f429 0a70 	bic.w	sl, r9, #15728640	; 0xf00000
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     91a:	950a      	str	r5, [sp, #40]	; 0x28
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     91c:	f42b 0970 	bic.w	r9, fp, #15728640	; 0xf00000
     920:	9d07      	ldr	r5, [sp, #28]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     922:	f8dd b018 	ldr.w	fp, [sp, #24]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     926:	f8cd 9014 	str.w	r9, [sp, #20]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     92a:	f10b 7900 	add.w	r9, fp, #33554432	; 0x2000000
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     92e:	f105 7b00 	add.w	fp, r5, #33554432	; 0x2000000
     932:	9d04      	ldr	r5, [sp, #16]

    /* default AFM : disabled */
    clear_bit_reg8(&this_uart->hw_reg->MM2,EAFM);

    /* disable TX time gaurd */
    clear_bit_reg8(&this_uart->hw_reg->MM0,ETTG); 
     934:	f101 0c30 	add.w	ip, r1, #48	; 0x30
     938:	f02c 407f 	bic.w	r0, ip, #4278190080	; 0xff000000
     93c:	f105 7500 	add.w	r5, r5, #33554432	; 0x2000000
     940:	f00c 4c70 	and.w	ip, ip, #4026531840	; 0xf0000000
     944:	f8cd a00c 	str.w	sl, [sp, #12]
     948:	9504      	str	r5, [sp, #16]
     94a:	f10c 7500 	add.w	r5, ip, #33554432	; 0x2000000
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     94e:	f10c 7a00 	add.w	sl, ip, #33554432	; 0x2000000
     952:	46ac      	mov	ip, r5
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     954:	9d03      	ldr	r5, [sp, #12]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     956:	f8cd a024 	str.w	sl, [sp, #36]	; 0x24
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     95a:	016d      	lsls	r5, r5, #5
     95c:	9503      	str	r5, [sp, #12]
     95e:	9d05      	ldr	r5, [sp, #20]
     960:	f428 0870 	bic.w	r8, r8, #15728640	; 0xf00000
     964:	016d      	lsls	r5, r5, #5
     966:	9505      	str	r5, [sp, #20]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     968:	9d06      	ldr	r5, [sp, #24]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     96a:	46ca      	mov	sl, r9
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     96c:	f105 7500 	add.w	r5, r5, #33554432	; 0x2000000
     970:	9506      	str	r5, [sp, #24]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     972:	9d01      	ldr	r5, [sp, #4]
     974:	ea4f 1848 	mov.w	r8, r8, lsl #5
     978:	3514      	adds	r5, #20
     97a:	9501      	str	r5, [sp, #4]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     97c:	9d07      	ldr	r5, [sp, #28]
     97e:	f427 0770 	bic.w	r7, r7, #15728640	; 0xf00000
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     982:	f105 7500 	add.w	r5, r5, #33554432	; 0x2000000
     986:	9507      	str	r5, [sp, #28]
     988:	9d04      	ldr	r5, [sp, #16]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     98a:	017f      	lsls	r7, r7, #5
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     98c:	3504      	adds	r5, #4
     98e:	9504      	str	r5, [sp, #16]
     990:	4665      	mov	r5, ip
     992:	3514      	adds	r5, #20
     994:	9508      	str	r5, [sp, #32]
     996:	9d09      	ldr	r5, [sp, #36]	; 0x24
     998:	f8cd 8030 	str.w	r8, [sp, #48]	; 0x30
     99c:	351c      	adds	r5, #28
     99e:	9509      	str	r5, [sp, #36]	; 0x24
     9a0:	9d0a      	ldr	r5, [sp, #40]	; 0x28
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     9a2:	f04f 0801 	mov.w	r8, #1
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     9a6:	350c      	adds	r5, #12
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     9a8:	f10a 0a08 	add.w	sl, sl, #8
     9ac:	f109 0904 	add.w	r9, r9, #4
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     9b0:	950a      	str	r5, [sp, #40]	; 0x28
     9b2:	f106 7600 	add.w	r6, r6, #33554432	; 0x2000000
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     9b6:	f849 8007 	str.w	r8, [r9, r7]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     9ba:	9d0c      	ldr	r5, [sp, #48]	; 0x30
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     9bc:	f84a 8007 	str.w	r8, [sl, r7]
     9c0:	f8dd a018 	ldr.w	sl, [sp, #24]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     9c4:	3610      	adds	r6, #16
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     9c6:	f84a 8007 	str.w	r8, [sl, r7]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     9ca:	5172      	str	r2, [r6, r5]
     9cc:	f8dd a00c 	ldr.w	sl, [sp, #12]
     9d0:	9e01      	ldr	r6, [sp, #4]
     9d2:	f10b 0b04 	add.w	fp, fp, #4
     9d6:	5172      	str	r2, [r6, r5]
     9d8:	f84b 200a 	str.w	r2, [fp, sl]
     9dc:	f8dd b01c 	ldr.w	fp, [sp, #28]
     9e0:	9d05      	ldr	r5, [sp, #20]
     9e2:	f84b 200a 	str.w	r2, [fp, sl]
     9e6:	9e04      	ldr	r6, [sp, #16]
     9e8:	f8dd a020 	ldr.w	sl, [sp, #32]
     9ec:	f420 0070 	bic.w	r0, r0, #15728640	; 0xf00000
     9f0:	0140      	lsls	r0, r0, #5
     9f2:	f10c 0c18 	add.w	ip, ip, #24
     9f6:	5172      	str	r2, [r6, r5]
     9f8:	f8dd b024 	ldr.w	fp, [sp, #36]	; 0x24
     9fc:	f84a 2000 	str.w	r2, [sl, r0]
     a00:	f84c 2000 	str.w	r2, [ip, r0]
     a04:	f8dd c028 	ldr.w	ip, [sp, #40]	; 0x28
    uint32_t baudrate    
)
{
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    
    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
     a08:	429c      	cmp	r4, r3
     a0a:	f84b 2000 	str.w	r2, [fp, r0]
     a0e:	f84c 2005 	str.w	r2, [ip, r5]

    /* disable single wire mode */
    clear_bit_reg8(&this_uart->hw_reg->MM2,ESWM);

    /* set filter to minimum value */
    this_uart->hw_reg->GFR = 0u;
     a12:	f881 2044 	strb.w	r2, [r1, #68]	; 0x44
    /* set default TX time gaurd */
    this_uart->hw_reg->TTG = 0u;
     a16:	f881 2048 	strb.w	r2, [r1, #72]	; 0x48
    /* set default RX timeout */
    this_uart->hw_reg->RTO = 0u;
     a1a:	f881 204c 	strb.w	r2, [r1, #76]	; 0x4c
    uint32_t baudrate    
)
{
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    
    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
     a1e:	d079      	beq.n	b14 <global_init+0x2a0>
     a20:	f240 0324 	movw	r3, #36	; 0x24
     a24:	f2c0 0300 	movt	r3, #0
     a28:	429c      	cmp	r4, r3
     a2a:	d015      	beq.n	a58 <global_init+0x1e4>
     * where possible to provide the most accurate baud rat possible.
     */
    config_baud_divisors(this_uart, baud_rate);

    /* set the line control register (bit length, stop bits, parity) */
    this_uart->hw_reg->LCR = line_config;
     a2c:	9d0b      	ldr	r5, [sp, #44]	; 0x2c

    /* Instance setup */
    this_uart->baudrate = baud_rate;
    this_uart->lineconfig = line_config;
    this_uart->tx_buff_size = TX_COMPLETE;
     a2e:	2000      	movs	r0, #0
     * where possible to provide the most accurate baud rat possible.
     */
    config_baud_divisors(this_uart, baud_rate);

    /* set the line control register (bit length, stop bits, parity) */
    this_uart->hw_reg->LCR = line_config;
     a30:	730d      	strb	r5, [r1, #12]
    this_uart->pid_pei_handler  = NULL_HANDLER;
    this_uart->break_handler    = NULL_HANDLER;    
    this_uart->sync_handler     = NULL_HANDLER;   

    /* Initialize the sticky status */
    this_uart->status = 0u;
     a32:	7360      	strb	r0, [r4, #13]

    /* set the line control register (bit length, stop bits, parity) */
    this_uart->hw_reg->LCR = line_config;

    /* Instance setup */
    this_uart->baudrate = baud_rate;
     a34:	9e0d      	ldr	r6, [sp, #52]	; 0x34
    this_uart->lineconfig = line_config;
    this_uart->tx_buff_size = TX_COMPLETE;
     a36:	6160      	str	r0, [r4, #20]

    /* set the line control register (bit length, stop bits, parity) */
    this_uart->hw_reg->LCR = line_config;

    /* Instance setup */
    this_uart->baudrate = baud_rate;
     a38:	60a6      	str	r6, [r4, #8]
    this_uart->lineconfig = line_config;
     a3a:	7325      	strb	r5, [r4, #12]
    this_uart->tx_buff_size = TX_COMPLETE;
    this_uart->tx_buffer = (const uint8_t *)0;
     a3c:	6120      	str	r0, [r4, #16]
    this_uart->tx_idx = 0u;
     a3e:	61a0      	str	r0, [r4, #24]

    /* Default handlers for MSS UART interrupts */
    this_uart->rx_handler       = NULL_HANDLER;
     a40:	6220      	str	r0, [r4, #32]
    this_uart->tx_handler       = NULL_HANDLER;
     a42:	6260      	str	r0, [r4, #36]	; 0x24
    this_uart->linests_handler  = NULL_HANDLER;
     a44:	61e0      	str	r0, [r4, #28]
    this_uart->modemsts_handler = NULL_HANDLER;
     a46:	62a0      	str	r0, [r4, #40]	; 0x28
    this_uart->rto_handler      = NULL_HANDLER;    
     a48:	62e0      	str	r0, [r4, #44]	; 0x2c
    this_uart->nack_handler     = NULL_HANDLER;   
     a4a:	6320      	str	r0, [r4, #48]	; 0x30
    this_uart->pid_pei_handler  = NULL_HANDLER;
     a4c:	6360      	str	r0, [r4, #52]	; 0x34
    this_uart->break_handler    = NULL_HANDLER;    
     a4e:	63a0      	str	r0, [r4, #56]	; 0x38
    this_uart->sync_handler     = NULL_HANDLER;   
     a50:	63e0      	str	r0, [r4, #60]	; 0x3c

    /* Initialize the sticky status */
    this_uart->status = 0u;
}
     a52:	b00f      	add	sp, #60	; 0x3c
     a54:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
        uint32_t baud_value_by_64;
        uint32_t baud_value_by_128;
        uint32_t fractional_baud_value;
        uint32_t pclk_freq;

        this_uart->baudrate = baudrate;
     a58:	9f0d      	ldr	r7, [sp, #52]	; 0x34
     a5a:	60a7      	str	r7, [r4, #8]

        /* Force the value of the CMSIS global variables holding the various system
          * clock frequencies to be updated. */
        SystemCoreClockUpdate();
     a5c:	f000 f924 	bl	ca8 <SystemCoreClockUpdate>
        {
            pclk_freq = g_FrequencyPCLK0;
        }
        else
        {
            pclk_freq = g_FrequencyPCLK1;
     a60:	f240 0118 	movw	r1, #24
     a64:	f2c0 0100 	movt	r1, #0
     a68:	680a      	ldr	r2, [r1, #0]
        /*
         * Compute baud value based on requested baud rate and PCLK frequency.
         * The baud value is computed using the following equation:
         *      baud_value = PCLK_Frequency / (baud_rate * 16)
         */
        baud_value_by_128 = (8u * pclk_freq) / baudrate;
     a6a:	9e0d      	ldr	r6, [sp, #52]	; 0x34
     a6c:	00d7      	lsls	r7, r2, #3
     a6e:	fbb7 f2f6 	udiv	r2, r7, r6
        baud_value_by_64 = baud_value_by_128 / 2u;
        baud_value = baud_value_by_64 / 64u;
     a72:	09d3      	lsrs	r3, r2, #7
         * Compute baud value based on requested baud rate and PCLK frequency.
         * The baud value is computed using the following equation:
         *      baud_value = PCLK_Frequency / (baud_rate * 16)
         */
        baud_value_by_128 = (8u * pclk_freq) / baudrate;
        baud_value_by_64 = baud_value_by_128 / 2u;
     a74:	0857      	lsrs	r7, r2, #1
        fractional_baud_value += (baud_value_by_128 - (baud_value * 128u)) - (fractional_baud_value * 2u);
        
        /* Assert if integer baud value fits in 16-bit. */
        ASSERT(baud_value <= UINT16_MAX);
    
        if(baud_value <= (uint32_t)UINT16_MAX)
     a76:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
     a7a:	bf28      	it	cs
     a7c:	6821      	ldrcs	r1, [r4, #0]
     a7e:	d2d5      	bcs.n	a2c <global_init+0x1b8>
        {
            if(baud_value > 1u)
     a80:	2b01      	cmp	r3, #1
            {
                /* 
                 * Use Frational baud rate divisors
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
     a82:	6821      	ldr	r1, [r4, #0]
        /* Assert if integer baud value fits in 16-bit. */
        ASSERT(baud_value <= UINT16_MAX);
    
        if(baud_value <= (uint32_t)UINT16_MAX)
        {
            if(baud_value > 1u)
     a84:	d950      	bls.n	b28 <global_init+0x2b4>
            {
                /* 
                 * Use Frational baud rate divisors
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
     a86:	f101 000c 	add.w	r0, r1, #12
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     a8a:	f020 4c7f 	bic.w	ip, r0, #4278190080	; 0xff000000
     a8e:	f000 4670 	and.w	r6, r0, #4026531840	; 0xf0000000
     a92:	f106 7000 	add.w	r0, r6, #33554432	; 0x2000000
     a96:	f42c 0a70 	bic.w	sl, ip, #15728640	; 0xf00000
     a9a:	ea4f 1e4a 	mov.w	lr, sl, lsl #5
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8);
                /* lsb of baud value */
                this_uart->hw_reg->DLR = (uint8_t)baud_value;
     a9e:	460d      	mov	r5, r1
     aa0:	fa5f f883 	uxtb.w	r8, r3
         *      baud_value = PCLK_Frequency / (baud_rate * 16)
         */
        baud_value_by_128 = (8u * pclk_freq) / baudrate;
        baud_value_by_64 = baud_value_by_128 / 2u;
        baud_value = baud_value_by_64 / 64u;
        fractional_baud_value = baud_value_by_64 - (baud_value * 64u);
     aa4:	eba7 1783 	sub.w	r7, r7, r3, lsl #6
     aa8:	301c      	adds	r0, #28
     aaa:	2601      	movs	r6, #1
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8);
     aac:	f3c2 3ac7 	ubfx	sl, r2, #15, #8
     ab0:	f840 600e 	str.w	r6, [r0, lr]
         */
        baud_value_by_128 = (8u * pclk_freq) / baudrate;
        baud_value_by_64 = baud_value_by_128 / 2u;
        baud_value = baud_value_by_64 / 64u;
        fractional_baud_value = baud_value_by_64 - (baud_value * 64u);
        fractional_baud_value += (baud_value_by_128 - (baud_value * 128u)) - (fractional_baud_value * 2u);
     ab4:	eba7 13c3 	sub.w	r3, r7, r3, lsl #7
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8);
     ab8:	f881 a004 	strb.w	sl, [r1, #4]
                /* lsb of baud value */
                this_uart->hw_reg->DLR = (uint8_t)baud_value;
     abc:	f805 8b30 	strb.w	r8, [r5], #48
         */
        baud_value_by_128 = (8u * pclk_freq) / baudrate;
        baud_value_by_64 = baud_value_by_128 / 2u;
        baud_value = baud_value_by_64 / 64u;
        fractional_baud_value = baud_value_by_64 - (baud_value * 64u);
        fractional_baud_value += (baud_value_by_128 - (baud_value * 128u)) - (fractional_baud_value * 2u);
     ac0:	189a      	adds	r2, r3, r2
     ac2:	f025 437f 	bic.w	r3, r5, #4278190080	; 0xff000000
     ac6:	f005 4570 	and.w	r5, r5, #4026531840	; 0xf0000000
     aca:	f423 0870 	bic.w	r8, r3, #15728640	; 0xf00000
                /* Enable Fractional baud rate */
                set_bit_reg8(&this_uart->hw_reg->MM0,EFBR);
        
                /* Load the fractional baud rate register */
                ASSERT(fractional_baud_value <= (uint32_t)UINT8_MAX);
                this_uart->hw_reg->DFR = (uint8_t)fractional_baud_value;
     ace:	eba2 0747 	sub.w	r7, r2, r7, lsl #1
     ad2:	f105 7500 	add.w	r5, r5, #33554432	; 0x2000000
     ad6:	351c      	adds	r5, #28
     ad8:	ea4f 1848 	mov.w	r8, r8, lsl #5
     adc:	b2ff      	uxtb	r7, r7
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     ade:	2300      	movs	r3, #0
     ae0:	f840 300e 	str.w	r3, [r0, lr]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     ae4:	f845 6008 	str.w	r6, [r5, r8]
     ae8:	f881 703c 	strb.w	r7, [r1, #60]	; 0x3c
     aec:	e79e      	b.n	a2c <global_init+0x1b8>
    if(this_uart == &g_mss_uart0)
    {
        this_uart->hw_reg = UART0;
        this_uart->irqn = UART0_IRQn;
        /* reset UART0 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART0_SOFTRESET_MASK;
     aee:	f040 0780 	orr.w	r7, r0, #128	; 0x80
     af2:	f2ce 0100 	movt	r1, #57344	; 0xe000
     af6:	f44f 6680 	mov.w	r6, #1024	; 0x400
     afa:	6497      	str	r7, [r2, #72]	; 0x48
     afc:	f8c1 6180 	str.w	r6, [r1, #384]	; 0x180
        /* Clear any previously pended UART0 interrupt */
        NVIC_ClearPendingIRQ(UART0_IRQn);
        /* Take UART0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
     b00:	6c95      	ldr	r5, [r2, #72]	; 0x48
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
    {
        this_uart->hw_reg = UART0;
     b02:	f04f 4180 	mov.w	r1, #1073741824	; 0x40000000
        /* reset UART0 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART0_SOFTRESET_MASK;
        /* Clear any previously pended UART0 interrupt */
        NVIC_ClearPendingIRQ(UART0_IRQn);
        /* Take UART0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
     b06:	f025 0080 	bic.w	r0, r5, #128	; 0x80
     b0a:	6490      	str	r0, [r2, #72]	; 0x48
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
    {
        this_uart->hw_reg = UART0;
        this_uart->irqn = UART0_IRQn;
     b0c:	220a      	movs	r2, #10
     b0e:	7122      	strb	r2, [r4, #4]
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
    {
        this_uart->hw_reg = UART0;
     b10:	6021      	str	r1, [r4, #0]
     b12:	e6d7      	b.n	8c4 <global_init+0x50>
        uint32_t baud_value_by_64;
        uint32_t baud_value_by_128;
        uint32_t fractional_baud_value;
        uint32_t pclk_freq;

        this_uart->baudrate = baudrate;
     b14:	9a0d      	ldr	r2, [sp, #52]	; 0x34
     b16:	60a2      	str	r2, [r4, #8]

        /* Force the value of the CMSIS global variables holding the various system
          * clock frequencies to be updated. */
        SystemCoreClockUpdate();
     b18:	f000 f8c6 	bl	ca8 <SystemCoreClockUpdate>
        if(this_uart == &g_mss_uart0)
        {
            pclk_freq = g_FrequencyPCLK0;
     b1c:	f240 0114 	movw	r1, #20
     b20:	f2c0 0100 	movt	r1, #0
     b24:	680a      	ldr	r2, [r1, #0]
     b26:	e7a0      	b.n	a6a <global_init+0x1f6>
            {
                /*
                 * Do NOT use Frational baud rate divisors.
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
     b28:	f101 0c0c 	add.w	ip, r1, #12
     b2c:	f02c 4e7f 	bic.w	lr, ip, #4278190080	; 0xff000000
     b30:	f00c 4270 	and.w	r2, ip, #4026531840	; 0xf0000000
     b34:	f42e 0570 	bic.w	r5, lr, #15728640	; 0xf00000
     b38:	f102 7200 	add.w	r2, r2, #33554432	; 0x2000000
     b3c:	ea4f 1e45 	mov.w	lr, r5, lsl #5
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8u);
                /* lsb of baud value */
                this_uart->hw_reg->DLR = (uint8_t)baud_value;
     b40:	4608      	mov	r0, r1
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8u);
     b42:	2500      	movs	r5, #0
                /* lsb of baud value */
                this_uart->hw_reg->DLR = (uint8_t)baud_value;
     b44:	b2db      	uxtb	r3, r3
     b46:	321c      	adds	r2, #28
     b48:	2601      	movs	r6, #1
     b4a:	f842 600e 	str.w	r6, [r2, lr]
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8u);
     b4e:	710d      	strb	r5, [r1, #4]
                /* lsb of baud value */
                this_uart->hw_reg->DLR = (uint8_t)baud_value;
     b50:	f800 3b30 	strb.w	r3, [r0], #48
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     b54:	f020 4c7f 	bic.w	ip, r0, #4278190080	; 0xff000000
     b58:	f000 4070 	and.w	r0, r0, #4026531840	; 0xf0000000
     b5c:	f100 7600 	add.w	r6, r0, #33554432	; 0x2000000
     b60:	f42c 0370 	bic.w	r3, ip, #15728640	; 0xf00000
     b64:	361c      	adds	r6, #28
     b66:	015b      	lsls	r3, r3, #5
     b68:	f842 500e 	str.w	r5, [r2, lr]
     b6c:	50f5      	str	r5, [r6, r3]
     b6e:	e75d      	b.n	a2c <global_init+0x1b8>

00000b70 <MSS_UART_init>:
(
    mss_uart_instance_t* this_uart, 
    uint32_t baud_rate,
    uint8_t line_config
)
{
     b70:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
     b72:	4604      	mov	r4, r0
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    /* Perform generic initialization */
    global_init(this_uart, baud_rate, line_config);
     b74:	f7ff fe7e 	bl	874 <global_init>

    /* Disable LIN mode */
    clear_bit_reg8(&this_uart->hw_reg->MM0, ELIN);
     b78:	6822      	ldr	r2, [r4, #0]
     b7a:	f64f 73ff 	movw	r3, #65535	; 0xffff

    /* Disable IrDA mode */
    clear_bit_reg8(&this_uart->hw_reg->MM1, EIRD);
     b7e:	f102 0034 	add.w	r0, r2, #52	; 0x34

    /* Perform generic initialization */
    global_init(this_uart, baud_rate, line_config);

    /* Disable LIN mode */
    clear_bit_reg8(&this_uart->hw_reg->MM0, ELIN);
     b82:	f102 0530 	add.w	r5, r2, #48	; 0x30
     b86:	f2c0 030f 	movt	r3, #15
     b8a:	f005 4770 	and.w	r7, r5, #4026531840	; 0xf0000000

    /* Disable IrDA mode */
    clear_bit_reg8(&this_uart->hw_reg->MM1, EIRD);

    /* Disable SmartCard Mode */
    clear_bit_reg8(&this_uart->hw_reg->MM2, EERR);
     b8e:	3238      	adds	r2, #56	; 0x38
     b90:	f000 4170 	and.w	r1, r0, #4026531840	; 0xf0000000

    /* set default tx handler for automated TX using interrupt in USART mode */
    this_uart->tx_handler = default_tx_handler;
     b94:	ea02 0603 	and.w	r6, r2, r3
     b98:	f107 7c00 	add.w	ip, r7, #33554432	; 0x2000000
     b9c:	401d      	ands	r5, r3
     b9e:	ea00 0703 	and.w	r7, r0, r3
     ba2:	f002 4270 	and.w	r2, r2, #4026531840	; 0xf0000000
     ba6:	f101 7100 	add.w	r1, r1, #33554432	; 0x2000000
     baa:	f240 70b5 	movw	r0, #1973	; 0x7b5
     bae:	017b      	lsls	r3, r7, #5
     bb0:	f10c 0c0c 	add.w	ip, ip, #12
     bb4:	f102 7700 	add.w	r7, r2, #33554432	; 0x2000000
     bb8:	016d      	lsls	r5, r5, #5
     bba:	2200      	movs	r2, #0
     bbc:	3108      	adds	r1, #8
     bbe:	0176      	lsls	r6, r6, #5
     bc0:	f2c0 0000 	movt	r0, #0
     bc4:	f84c 2005 	str.w	r2, [ip, r5]
     bc8:	6260      	str	r0, [r4, #36]	; 0x24
     bca:	50ca      	str	r2, [r1, r3]
     bcc:	51ba      	str	r2, [r7, r6]
}
     bce:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

00000bd0 <MSS_GPIO_init>:
void MSS_GPIO_init( void )
{
    uint32_t inc;
    
    /* reset MSS GPIO hardware */
    SYSREG->SOFT_RST_CR |= SYSREG_GPIO_SOFTRESET_MASK;
     bd0:	f248 0200 	movw	r2, #32768	; 0x8000
     bd4:	f2c4 0203 	movt	r2, #16387	; 0x4003
/*-------------------------------------------------------------------------*//**
 * MSS_GPIO_init
 * See "mss_gpio.h" for details of how to use this function.
 */
void MSS_GPIO_init( void )
{
     bd8:	e92d 05f0 	stmdb	sp!, {r4, r5, r6, r7, r8, sl}
    uint32_t inc;
    
    /* reset MSS GPIO hardware */
    SYSREG->SOFT_RST_CR |= SYSREG_GPIO_SOFTRESET_MASK;
     bdc:	6c94      	ldr	r4, [r2, #72]	; 0x48
     bde:	f640 76e4 	movw	r6, #4068	; 0xfe4
     be2:	f444 1380 	orr.w	r3, r4, #1048576	; 0x100000
     be6:	6493      	str	r3, [r2, #72]	; 0x48
    SYSREG->SOFT_RST_CR |= (SYSREG_GPIO_7_0_SOFTRESET_MASK |
     be8:	6c90      	ldr	r0, [r2, #72]	; 0x48

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
     bea:	f24e 1300 	movw	r3, #57600	; 0xe100
     bee:	f040 71f0 	orr.w	r1, r0, #31457280	; 0x1e00000
     bf2:	6491      	str	r1, [r2, #72]	; 0x48
     bf4:	f2c0 0600 	movt	r6, #0
     bf8:	f2ce 0300 	movt	r3, #57344	; 0xe000
     bfc:	2200      	movs	r2, #0
     bfe:	2701      	movs	r7, #1
                            SYSREG_GPIO_15_8_SOFTRESET_MASK |
                            SYSREG_GPIO_23_16_SOFTRESET_MASK |
                            SYSREG_GPIO_31_24_SOFTRESET_MASK);
                            
    /* Clear any previously pended MSS GPIO interrupt */
    for(inc = 0U; inc < NB_OF_GPIO; ++inc)
     c00:	1c55      	adds	r5, r2, #1
    {
        NVIC_DisableIRQ(g_gpio_irqn_lut[inc]);
     c02:	5cb4      	ldrb	r4, [r6, r2]
     c04:	f816 a005 	ldrb.w	sl, [r6, r5]
     c08:	f004 001f 	and.w	r0, r4, #31
     c0c:	f00a 011f 	and.w	r1, sl, #31
     c10:	fa17 f000 	lsls.w	r0, r7, r0
     c14:	fa17 f101 	lsls.w	r1, r7, r1
     c18:	fa4f f88a 	sxtb.w	r8, sl
     c1c:	b262      	sxtb	r2, r4
     c1e:	0954      	lsrs	r4, r2, #5
     c20:	ea4f 1c58 	mov.w	ip, r8, lsr #5
                            SYSREG_GPIO_15_8_SOFTRESET_MASK |
                            SYSREG_GPIO_23_16_SOFTRESET_MASK |
                            SYSREG_GPIO_31_24_SOFTRESET_MASK);
                            
    /* Clear any previously pended MSS GPIO interrupt */
    for(inc = 0U; inc < NB_OF_GPIO; ++inc)
     c24:	1c6a      	adds	r2, r5, #1

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
     c26:	f104 0a60 	add.w	sl, r4, #96	; 0x60
     c2a:	f10c 0860 	add.w	r8, ip, #96	; 0x60

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
     c2e:	3420      	adds	r4, #32
     c30:	f10c 0c20 	add.w	ip, ip, #32
     c34:	2a20      	cmp	r2, #32
     c36:	f843 0024 	str.w	r0, [r3, r4, lsl #2]

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
     c3a:	f843 002a 	str.w	r0, [r3, sl, lsl #2]

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
     c3e:	f843 102c 	str.w	r1, [r3, ip, lsl #2]

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
     c42:	f843 1028 	str.w	r1, [r3, r8, lsl #2]
     c46:	d1db      	bne.n	c00 <MSS_GPIO_init+0x30>
    {
        NVIC_DisableIRQ(g_gpio_irqn_lut[inc]);
        NVIC_ClearPendingIRQ(g_gpio_irqn_lut[inc]);
    }
    /* Take MSS GPIO hardware out of reset. */
    SYSREG->SOFT_RST_CR &= ~(SYSREG_GPIO_7_0_SOFTRESET_MASK |
     c48:	f248 0300 	movw	r3, #32768	; 0x8000
     c4c:	f2c4 0303 	movt	r3, #16387	; 0x4003
     c50:	6c9a      	ldr	r2, [r3, #72]	; 0x48
     c52:	f022 70f0 	bic.w	r0, r2, #31457280	; 0x1e00000
     c56:	6498      	str	r0, [r3, #72]	; 0x48
                             SYSREG_GPIO_15_8_SOFTRESET_MASK |
                             SYSREG_GPIO_23_16_SOFTRESET_MASK |
                             SYSREG_GPIO_31_24_SOFTRESET_MASK);
    SYSREG->SOFT_RST_CR &= ~SYSREG_GPIO_SOFTRESET_MASK;
     c58:	6c99      	ldr	r1, [r3, #72]	; 0x48
     c5a:	f421 1280 	bic.w	r2, r1, #1048576	; 0x100000
     c5e:	649a      	str	r2, [r3, #72]	; 0x48
}
     c60:	e8bd 05f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, sl}
     c64:	4770      	bx	lr
     c66:	bf00      	nop

00000c68 <MSS_GPIO_config>:
{
    uint32_t gpio_idx = (uint32_t)port_id;
    
    ASSERT(gpio_idx < NB_OF_GPIO);

    if(gpio_idx < NB_OF_GPIO)
     c68:	281f      	cmp	r0, #31
    {
        *(g_config_reg_lut[gpio_idx]) = config;
     c6a:	bf9f      	itttt	ls
     c6c:	f241 0304 	movwls	r3, #4100	; 0x1004
     c70:	f2c0 0300 	movtls	r3, #0
     c74:	f853 3020 	ldrls.w	r3, [r3, r0, lsl #2]
     c78:	6019      	strls	r1, [r3, #0]
     c7a:	4770      	bx	lr

00000c7c <MSS_GPIO_set_output>:
    uint32_t gpio_setting;
    uint32_t gpio_idx = (uint32_t)port_id;
    
    ASSERT(gpio_idx < NB_OF_GPIO);
    
    if(gpio_idx < NB_OF_GPIO)
     c7c:	281f      	cmp	r0, #31
     c7e:	d812      	bhi.n	ca6 <MSS_GPIO_set_output+0x2a>
    {
        gpio_setting = GPIO->GPIO_OUT;
        gpio_setting &= ~((uint32_t)0x01u << gpio_idx);
     c80:	2201      	movs	r2, #1
     c82:	fa02 fc00 	lsl.w	ip, r2, r0
        gpio_setting |= ((uint32_t)value & 0x01u) << gpio_idx;
     c86:	f001 0301 	and.w	r3, r1, #1
     c8a:	fa13 f000 	lsls.w	r0, r3, r0
    
    ASSERT(gpio_idx < NB_OF_GPIO);
    
    if(gpio_idx < NB_OF_GPIO)
    {
        gpio_setting = GPIO->GPIO_OUT;
     c8e:	f243 0300 	movw	r3, #12288	; 0x3000
     c92:	f2c4 0301 	movt	r3, #16385	; 0x4001
     c96:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
        gpio_setting &= ~((uint32_t)0x01u << gpio_idx);
     c9a:	ea22 010c 	bic.w	r1, r2, ip
        gpio_setting |= ((uint32_t)value & 0x01u) << gpio_idx;
     c9e:	ea41 0000 	orr.w	r0, r1, r0
        GPIO->GPIO_OUT = gpio_setting;
     ca2:	f8c3 0088 	str.w	r0, [r3, #136]	; 0x88
     ca6:	4770      	bx	lr

00000ca8 <SystemCoreClockUpdate>:
#define FREQ_1MHZ    1000000u
#define FREQ_25MHZ   25000000u
#define FREQ_50MHZ   50000000u

void SystemCoreClockUpdate(void)
{
     ca8:	e92d 01f0 	stmdb	sp!, {r4, r5, r6, r7, r8}
    uint32_t controller_pll_init;
    uint32_t clk_src;

    controller_pll_init = SYSREG->MSSDDR_FACC1_CR & CONTROLLER_PLL_INIT_MASK;
     cac:	f248 0300 	movw	r3, #32768	; 0x8000
     cb0:	f2c4 0303 	movt	r3, #16387	; 0x4003
     cb4:	f8d3 2098 	ldr.w	r2, [r3, #152]	; 0x98
#define FREQ_1MHZ    1000000u
#define FREQ_25MHZ   25000000u
#define FREQ_50MHZ   50000000u

void SystemCoreClockUpdate(void)
{
     cb8:	b083      	sub	sp, #12
    uint32_t controller_pll_init;
    uint32_t clk_src;

    controller_pll_init = SYSREG->MSSDDR_FACC1_CR & CONTROLLER_PLL_INIT_MASK;
    
    if(0u == controller_pll_init)
     cba:	f012 6f80 	tst.w	r2, #67108864	; 0x4000000
     cbe:	d118      	bne.n	cf2 <SystemCoreClockUpdate+0x4a>
    {
        /* Normal operations. */
        uint32_t global_mux_sel;
        
        global_mux_sel = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK;
     cc0:	f8d3 0098 	ldr.w	r0, [r3, #152]	; 0x98
        if(0u == global_mux_sel)
     cc4:	f410 5f80 	tst.w	r0, #4096	; 0x1000
     cc8:	d04d      	beq.n	d66 <SystemCoreClockUpdate+0xbe>
                                                   RCOSC_25_50MHZ_CLK_SRC,
                                                   CLK_XTAL_CLK_SRC,
                                                   RCOSC_1_MHZ_CLK_SRC,
                                                   RCOSC_1_MHZ_CLK_SRC,
                                                   CCC2ASCI_CLK_SRC,
                                                   CCC2ASCI_CLK_SRC };
     cca:	f241 0184 	movw	r1, #4228	; 0x1084
     cce:	f2c0 0100 	movt	r1, #0
     cd2:	46ec      	mov	ip, sp
     cd4:	c903      	ldmia	r1!, {r0, r1}
     cd6:	e88c 0003 	stmia.w	ip, {r0, r1}
            
            uint32_t standby_sel;
            uint8_t clock_source;
            
            standby_sel = (SYSREG->MSSDDR_FACC2_CR >> FACC_STANDBY_SHIFT) & FACC_STANDBY_SEL_MASK;
     cda:	f8d3 209c 	ldr.w	r2, [r3, #156]	; 0x9c
            clock_source = standby_clock_lut[standby_sel];
            switch(clock_source)
     cde:	af02      	add	r7, sp, #8
     ce0:	f3c2 1682 	ubfx	r6, r2, #6, #3
     ce4:	19bd      	adds	r5, r7, r6
     ce6:	f815 4c08 	ldrb.w	r4, [r5, #-8]
     cea:	2c01      	cmp	r4, #1
     cec:	f000 8081 	beq.w	df2 <SystemCoreClockUpdate+0x14a>
     cf0:	d26a      	bcs.n	dc8 <SystemCoreClockUpdate+0x120>
static uint32_t get_rcosc_25_50mhz_frequency(void)
{
    uint32_t rcosc_div2;
    uint32_t rcosc_frequency;
    
    rcosc_div2 = SYSREG->MSSDDR_PLL_STATUS & RCOSC_DIV2_MASK;
     cf2:	f8d3 0150 	ldr.w	r0, [r3, #336]	; 0x150
    if(0u == rcosc_div2)
     cf6:	f647 0840 	movw	r8, #30784	; 0x7840
     cfa:	f24f 0380 	movw	r3, #61568	; 0xf080
     cfe:	f010 0f04 	tst.w	r0, #4
     d02:	f2c0 187d 	movt	r8, #381	; 0x17d
     d06:	f2c0 23fa 	movt	r3, #762	; 0x2fa
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     d0a:	f240 051c 	movw	r5, #28
    g_FrequencyPCLK0 = standby_clk;
     d0e:	f240 0414 	movw	r4, #20
    g_FrequencyPCLK1 = standby_clk;
     d12:	f240 0018 	movw	r0, #24
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     d16:	f240 0708 	movw	r7, #8
     d1a:	f646 6c70 	movw	ip, #28272	; 0x6e70
    g_FrequencyFIC0 = standby_clk;
     d1e:	f240 010c 	movw	r1, #12
    g_FrequencyFIC1 = standby_clk;
     d22:	f240 0210 	movw	r2, #16
    g_FrequencyFIC64 = standby_clk;
     d26:	f240 0604 	movw	r6, #4
{
    uint32_t rcosc_div2;
    uint32_t rcosc_frequency;
    
    rcosc_div2 = SYSREG->MSSDDR_PLL_STATUS & RCOSC_DIV2_MASK;
    if(0u == rcosc_div2)
     d2a:	bf08      	it	eq
     d2c:	4643      	moveq	r3, r8
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     d2e:	f2c0 0500 	movt	r5, #0
    g_FrequencyPCLK0 = standby_clk;
     d32:	f2c0 0400 	movt	r4, #0
    g_FrequencyPCLK1 = standby_clk;
     d36:	f2c0 0000 	movt	r0, #0
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     d3a:	f2c0 0700 	movt	r7, #0
     d3e:	f2c0 1ca7 	movt	ip, #423	; 0x1a7
    g_FrequencyFIC0 = standby_clk;
     d42:	f2c0 0100 	movt	r1, #0
    g_FrequencyFIC1 = standby_clk;
     d46:	f2c0 0200 	movt	r2, #0
    g_FrequencyFIC64 = standby_clk;
     d4a:	f2c0 0600 	movt	r6, #0
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
    g_FrequencyPCLK0 = standby_clk;
    g_FrequencyPCLK1 = standby_clk;
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     d4e:	f8c7 c000 	str.w	ip, [r7]
    g_FrequencyFIC0 = standby_clk;
    g_FrequencyFIC1 = standby_clk;
    g_FrequencyFIC64 = standby_clk;
     d52:	6033      	str	r3, [r6, #0]
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     d54:	602b      	str	r3, [r5, #0]
    g_FrequencyPCLK0 = standby_clk;
     d56:	6023      	str	r3, [r4, #0]
    g_FrequencyPCLK1 = standby_clk;
     d58:	6003      	str	r3, [r0, #0]
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
    g_FrequencyFIC0 = standby_clk;
     d5a:	600b      	str	r3, [r1, #0]
    g_FrequencyFIC1 = standby_clk;
     d5c:	6013      	str	r3, [r2, #0]
    {
        /* PLL initialization mode. Running from 25/50MHZ RC oscillator. */
        clk_src = get_rcosc_25_50mhz_frequency();
        set_clock_frequency_globals(clk_src);
    }
}
     d5e:	b003      	add	sp, #12
     d60:	e8bd 01f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8}
     d64:	4770      	bx	lr
        
        global_mux_sel = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK;
        if(0u == global_mux_sel)
        {
            /* MSS clocked from MSS PLL. Use Libero flow defines. */
            SystemCoreClock = MSS_SYS_M3_CLK_FREQ;
     d66:	f240 041c 	movw	r4, #28
     d6a:	f64b 13c0 	movw	r3, #47552	; 0xb9c0
            g_FrequencyPCLK0 = MSS_SYS_APB_0_CLK_FREQ;
     d6e:	f240 0014 	movw	r0, #20
            g_FrequencyPCLK1 = MSS_SYS_APB_1_CLK_FREQ;
     d72:	f240 0118 	movw	r1, #24
            g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     d76:	f240 0c08 	movw	ip, #8
     d7a:	f646 6870 	movw	r8, #28272	; 0x6e70
            g_FrequencyFIC0 = MSS_SYS_FIC_0_CLK_FREQ;
     d7e:	f240 020c 	movw	r2, #12
            g_FrequencyFIC1 = MSS_SYS_FIC_1_CLK_FREQ;
     d82:	f240 0710 	movw	r7, #16
            g_FrequencyFIC64 = MSS_SYS_FIC64_CLK_FREQ;
     d86:	f240 0504 	movw	r5, #4
     d8a:	f642 5640 	movw	r6, #11584	; 0x2d40
        
        global_mux_sel = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK;
        if(0u == global_mux_sel)
        {
            /* MSS clocked from MSS PLL. Use Libero flow defines. */
            SystemCoreClock = MSS_SYS_M3_CLK_FREQ;
     d8e:	f2c0 639d 	movt	r3, #1693	; 0x69d
     d92:	f2c0 0400 	movt	r4, #0
            g_FrequencyPCLK0 = MSS_SYS_APB_0_CLK_FREQ;
     d96:	f2c0 0000 	movt	r0, #0
            g_FrequencyPCLK1 = MSS_SYS_APB_1_CLK_FREQ;
     d9a:	f2c0 0100 	movt	r1, #0
            g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     d9e:	f2c0 0c00 	movt	ip, #0
     da2:	f2c0 18a7 	movt	r8, #423	; 0x1a7
            g_FrequencyFIC0 = MSS_SYS_FIC_0_CLK_FREQ;
     da6:	f2c0 0200 	movt	r2, #0
            g_FrequencyFIC1 = MSS_SYS_FIC_1_CLK_FREQ;
     daa:	f2c0 0700 	movt	r7, #0
            g_FrequencyFIC64 = MSS_SYS_FIC64_CLK_FREQ;
     dae:	f2c0 0500 	movt	r5, #0
     db2:	f2c1 36d9 	movt	r6, #5081	; 0x13d9
        {
            /* MSS clocked from MSS PLL. Use Libero flow defines. */
            SystemCoreClock = MSS_SYS_M3_CLK_FREQ;
            g_FrequencyPCLK0 = MSS_SYS_APB_0_CLK_FREQ;
            g_FrequencyPCLK1 = MSS_SYS_APB_1_CLK_FREQ;
            g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     db6:	f8cc 8000 	str.w	r8, [ip]
            g_FrequencyFIC0 = MSS_SYS_FIC_0_CLK_FREQ;
            g_FrequencyFIC1 = MSS_SYS_FIC_1_CLK_FREQ;
     dba:	603b      	str	r3, [r7, #0]
            g_FrequencyFIC64 = MSS_SYS_FIC64_CLK_FREQ;
     dbc:	602e      	str	r6, [r5, #0]
        
        global_mux_sel = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK;
        if(0u == global_mux_sel)
        {
            /* MSS clocked from MSS PLL. Use Libero flow defines. */
            SystemCoreClock = MSS_SYS_M3_CLK_FREQ;
     dbe:	6023      	str	r3, [r4, #0]
            g_FrequencyPCLK0 = MSS_SYS_APB_0_CLK_FREQ;
     dc0:	6003      	str	r3, [r0, #0]
            g_FrequencyPCLK1 = MSS_SYS_APB_1_CLK_FREQ;
     dc2:	600b      	str	r3, [r1, #0]
            g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
            g_FrequencyFIC0 = MSS_SYS_FIC_0_CLK_FREQ;
     dc4:	6013      	str	r3, [r2, #0]
     dc6:	e7ca      	b.n	d5e <SystemCoreClockUpdate+0xb6>
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     dc8:	f244 2340 	movw	r3, #16960	; 0x4240
     dcc:	f240 051c 	movw	r5, #28
    g_FrequencyPCLK0 = standby_clk;
     dd0:	f240 0414 	movw	r4, #20
    g_FrequencyPCLK1 = standby_clk;
     dd4:	f240 0018 	movw	r0, #24
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     dd8:	f240 0708 	movw	r7, #8
     ddc:	f646 6c70 	movw	ip, #28272	; 0x6e70
    g_FrequencyFIC0 = standby_clk;
     de0:	f240 010c 	movw	r1, #12
    g_FrequencyFIC1 = standby_clk;
     de4:	f240 0210 	movw	r2, #16
    g_FrequencyFIC64 = standby_clk;
     de8:	f240 0604 	movw	r6, #4
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     dec:	f2c0 030f 	movt	r3, #15
     df0:	e79d      	b.n	d2e <SystemCoreClockUpdate+0x86>
    g_FrequencyPCLK0 = standby_clk;
     df2:	f240 051c 	movw	r5, #28
     df6:	f240 0414 	movw	r4, #20
    g_FrequencyPCLK1 = standby_clk;
     dfa:	f240 0018 	movw	r0, #24
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     dfe:	f240 0708 	movw	r7, #8
     e02:	f646 6c70 	movw	ip, #28272	; 0x6e70
    g_FrequencyFIC0 = standby_clk;
     e06:	f240 010c 	movw	r1, #12
    g_FrequencyFIC1 = standby_clk;
     e0a:	f240 0210 	movw	r2, #16
    g_FrequencyFIC64 = standby_clk;
     e0e:	f240 0604 	movw	r6, #4
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     e12:	f2c0 0500 	movt	r5, #0
    g_FrequencyPCLK0 = standby_clk;
     e16:	f2c0 0400 	movt	r4, #0
    g_FrequencyPCLK1 = standby_clk;
     e1a:	f2c0 0000 	movt	r0, #0
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     e1e:	f2c0 0700 	movt	r7, #0
     e22:	f2c0 1ca7 	movt	ip, #423	; 0x1a7
    g_FrequencyFIC0 = standby_clk;
     e26:	f2c0 0100 	movt	r1, #0
    g_FrequencyFIC1 = standby_clk;
     e2a:	f2c0 0200 	movt	r2, #0
    g_FrequencyFIC64 = standby_clk;
     e2e:	f2c0 0600 	movt	r6, #0
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     e32:	f44f 4300 	mov.w	r3, #32768	; 0x8000
     e36:	e78a      	b.n	d4e <SystemCoreClockUpdate+0xa6>

00000e38 <SystemInit>:
static uint32_t get_silicon_revision(void)
{
    uint32_t silicon_revision;
    uint32_t device_version;
    
    device_version = SYSREG->DEVICE_VERSION;
     e38:	f248 0300 	movw	r3, #32768	; 0x8000
     e3c:	f2c4 0303 	movt	r3, #16387	; 0x4003
     e40:	f8d3 114c 	ldr.w	r1, [r3, #332]	; 0x14c
    switch(device_version)
     e44:	f64f 0202 	movw	r2, #63490	; 0xf802
     e48:	4291      	cmp	r1, r2

/***************************************************************************//**
 * See system_m2sxxx.h for details.
 */
void SystemInit(void)
{
     e4a:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
{
    uint32_t silicon_revision;
    uint32_t device_version;
    
    device_version = SYSREG->DEVICE_VERSION;
    switch(device_version)
     e4e:	d10b      	bne.n	e68 <SystemInit+0x30>
{
    /*--------------------------------------------------------------------------
     * Work around a couple of silicon issues:
     */
    /* DDR_CLK_EN <- 1 */
    SYSREG->MSSDDR_FACC1_CR |= (uint32_t)1 << DDR_CLK_EN_SHIFT;
     e50:	f8d3 0098 	ldr.w	r0, [r3, #152]	; 0x98
     e54:	f440 7280 	orr.w	r2, r0, #256	; 0x100
     e58:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98
    
    /* CONTROLLER_PLL_INIT <- 0 */
    SYSREG->MSSDDR_FACC1_CR = SYSREG->MSSDDR_FACC1_CR & ~CONTROLLER_PLL_INIT_MASK;
     e5c:	f8d3 1098 	ldr.w	r1, [r3, #152]	; 0x98
     e60:	f021 6080 	bic.w	r0, r1, #67108864	; 0x4000000
     e64:	f8c3 0098 	str.w	r0, [r3, #152]	; 0x98
    /*--------------------------------------------------------------------------
     * Set STKALIGN to ensure exception stacking starts on 8 bytes address
     * boundary. This ensures compliance with the "Procedure Call Standards for
     * the ARM Architecture" (AAPCS).
     */
    SCB->CCR |= SCB_CCR_STKALIGN_Msk;
     e68:	f64e 5300 	movw	r3, #60672	; 0xed00
     e6c:	f2ce 0300 	movt	r3, #57344	; 0xe000
     e70:	6958      	ldr	r0, [r3, #20]
    
    /*--------------------------------------------------------------------------
     * MDDR configuration
     */
#if MSS_SYS_MDDR_CONFIG_BY_CORTEX
    if(0u == SYSREG->DDR_CR)
     e72:	f248 0200 	movw	r2, #32768	; 0x8000
    /*--------------------------------------------------------------------------
     * Set STKALIGN to ensure exception stacking starts on 8 bytes address
     * boundary. This ensures compliance with the "Procedure Call Standards for
     * the ARM Architecture" (AAPCS).
     */
    SCB->CCR |= SCB_CCR_STKALIGN_Msk;
     e76:	f440 7100 	orr.w	r1, r0, #512	; 0x200
     e7a:	6159      	str	r1, [r3, #20]
    
    /*--------------------------------------------------------------------------
     * MDDR configuration
     */
#if MSS_SYS_MDDR_CONFIG_BY_CORTEX
    if(0u == SYSREG->DDR_CR)
     e7c:	f2c4 0203 	movt	r2, #16387	; 0x4003
     e80:	6893      	ldr	r3, [r2, #8]
     e82:	2b00      	cmp	r3, #0
     e84:	d164      	bne.n	f50 <SystemInit+0x118>
         * to address 0x00000000. If MDDR is remapped to 0x00000000 then we are
         * probably executing this code from MDDR in a debugging session and
         * attempting to reconfigure the MDDR memory controller will cause the
         * Cortex-M3 to crash.
         */
        config_ddr_subsys(&g_m2s_mddr_subsys_config, &g_m2s_mddr_addr->core);
     e86:	f241 1498 	movw	r4, #4504	; 0x1198
     e8a:	f2c0 0400 	movt	r4, #0
     e8e:	6826      	ldr	r6, [r4, #0]
     e90:	f241 048c 	movw	r4, #4236	; 0x108c
     e94:	f2c0 0400 	movt	r4, #0
    
    /*--------------------------------------------------------------------------
     * Configure DDR controller part of the MDDR subsystem.
     */
    p_cfg = &p_ddr_subsys_cfg->ddrc.DYN_SOFT_RESET_CR;
    p_regs = &p_ddr_subsys_regs->ddrc.DYN_SOFT_RESET_CR;
     e98:	4632      	mov	r2, r6
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
    {
        p_regs[inc] = p_cfg[inc];
     e9a:	1c98      	adds	r0, r3, #2
     e9c:	1c81      	adds	r1, r0, #2
     e9e:	5b1f      	ldrh	r7, [r3, r4]
     ea0:	5b00      	ldrh	r0, [r0, r4]
     ea2:	5b0d      	ldrh	r5, [r1, r4]
     ea4:	3306      	adds	r3, #6
     ea6:	4611      	mov	r1, r2
     ea8:	f841 7b04 	str.w	r7, [r1], #4
     eac:	6050      	str	r0, [r2, #4]
     eae:	320c      	adds	r2, #12
    uint32_t nb_16bit_words
)
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
     eb0:	2b72      	cmp	r3, #114	; 0x72
    {
        p_regs[inc] = p_cfg[inc];
     eb2:	604d      	str	r5, [r1, #4]
    uint32_t nb_16bit_words
)
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
     eb4:	d1f1      	bne.n	e9a <SystemInit+0x62>
    
    /*--------------------------------------------------------------------------
     * Configure DDR PHY.
     */
    p_cfg = &p_ddr_subsys_cfg->phy.LOOPBACK_TEST_CR;
    p_regs = &p_ddr_subsys_regs->phy.LOOPBACK_TEST_CR;
     eb6:	f241 028c 	movw	r2, #4236	; 0x108c
     eba:	f2c0 0200 	movt	r2, #0
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
    {
        p_regs[inc] = p_cfg[inc];
     ebe:	f8b2 5072 	ldrh.w	r5, [r2, #114]	; 0x72
    
    /*--------------------------------------------------------------------------
     * Configure DDR PHY.
     */
    p_cfg = &p_ddr_subsys_cfg->phy.LOOPBACK_TEST_CR;
    p_regs = &p_ddr_subsys_regs->phy.LOOPBACK_TEST_CR;
     ec2:	f506 7307 	add.w	r3, r6, #540	; 0x21c
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
    {
        p_regs[inc] = p_cfg[inc];
     ec6:	601d      	str	r5, [r3, #0]
static void set_clock_frequency_globals(uint32_t fclk);

/***************************************************************************//**
 * See system_m2sxxx.h for details.
 */
void SystemInit(void)
     ec8:	f102 0c82 	add.w	ip, r2, #130	; 0x82
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
    {
        p_regs[inc] = p_cfg[inc];
     ecc:	1c93      	adds	r3, r2, #2
     ece:	f506 7108 	add.w	r1, r6, #544	; 0x220
     ed2:	1c98      	adds	r0, r3, #2
     ed4:	f8b3 5072 	ldrh.w	r5, [r3, #114]	; 0x72
     ed8:	460f      	mov	r7, r1
     eda:	f8b0 2072 	ldrh.w	r2, [r0, #114]	; 0x72
     ede:	f847 5b04 	str.w	r5, [r7], #4
     ee2:	1c83      	adds	r3, r0, #2
     ee4:	604a      	str	r2, [r1, #4]
     ee6:	1d39      	adds	r1, r7, #4
    uint32_t nb_16bit_words
)
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
     ee8:	4563      	cmp	r3, ip
     eea:	d1f2      	bne.n	ed2 <SystemInit+0x9a>
    p_ddr_subsys_regs->fic.HPD_SW_RW_EN_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_EN_CR;
    p_ddr_subsys_regs->fic.HPD_SW_RW_INVAL_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_INVAL_CR;
    p_ddr_subsys_regs->fic.SW_WR_ERCLR_CR = p_ddr_subsys_cfg->fic.SW_WR_ERCLR_CR;
    p_ddr_subsys_regs->fic.ERR_INT_ENABLE_CR = p_ddr_subsys_cfg->fic.ERR_INT_ENABLE_CR;
    p_ddr_subsys_regs->fic.NUM_AHB_MASTERS_CR = p_ddr_subsys_cfg->fic.NUM_AHB_MASTERS_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[0] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_1_CR;
     eec:	f8b4 1104 	ldrh.w	r1, [r4, #260]	; 0x104
    copy_cfg16_to_regs(p_regs, p_cfg, NB_OF_DDR_PHY_REGS_TO_CONFIG);
    
    /*--------------------------------------------------------------------------
     * Configure DDR FIC.
     */
    p_ddr_subsys_regs->fic.NB_ADDR_CR = p_ddr_subsys_cfg->fic.NB_ADDR_CR;
     ef0:	f8b4 90f4 	ldrh.w	r9, [r4, #244]	; 0xf4
    p_ddr_subsys_regs->fic.NBRWB_SIZE_CR = p_ddr_subsys_cfg->fic.NBRWB_SIZE_CR;
     ef4:	f8b4 a0f6 	ldrh.w	sl, [r4, #246]	; 0xf6
    p_ddr_subsys_regs->fic.WB_TIMEOUT_CR = p_ddr_subsys_cfg->fic.WB_TIMEOUT_CR;
     ef8:	f8b4 80f8 	ldrh.w	r8, [r4, #248]	; 0xf8
    p_ddr_subsys_regs->fic.HPD_SW_RW_EN_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_EN_CR;
     efc:	f8b4 e0fa 	ldrh.w	lr, [r4, #250]	; 0xfa
    p_ddr_subsys_regs->fic.HPD_SW_RW_INVAL_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_INVAL_CR;
     f00:	f8b4 c0fc 	ldrh.w	ip, [r4, #252]	; 0xfc
    p_ddr_subsys_regs->fic.SW_WR_ERCLR_CR = p_ddr_subsys_cfg->fic.SW_WR_ERCLR_CR;
     f04:	f8b4 70fe 	ldrh.w	r7, [r4, #254]	; 0xfe
    p_ddr_subsys_regs->fic.ERR_INT_ENABLE_CR = p_ddr_subsys_cfg->fic.ERR_INT_ENABLE_CR;
     f08:	f8b4 5100 	ldrh.w	r5, [r4, #256]	; 0x100
    p_ddr_subsys_regs->fic.NUM_AHB_MASTERS_CR = p_ddr_subsys_cfg->fic.NUM_AHB_MASTERS_CR;
     f0c:	f8b4 0102 	ldrh.w	r0, [r4, #258]	; 0x102
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[0] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_1_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[1] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_2_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUT_EN_CR = p_ddr_subsys_cfg->fic.LOCK_TIMEOUT_EN_CR;
     f10:	f8b4 3108 	ldrh.w	r3, [r4, #264]	; 0x108
    p_ddr_subsys_regs->fic.HPD_SW_RW_INVAL_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_INVAL_CR;
    p_ddr_subsys_regs->fic.SW_WR_ERCLR_CR = p_ddr_subsys_cfg->fic.SW_WR_ERCLR_CR;
    p_ddr_subsys_regs->fic.ERR_INT_ENABLE_CR = p_ddr_subsys_cfg->fic.ERR_INT_ENABLE_CR;
    p_ddr_subsys_regs->fic.NUM_AHB_MASTERS_CR = p_ddr_subsys_cfg->fic.NUM_AHB_MASTERS_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[0] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_1_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[1] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_2_CR;
     f14:	f8b4 2106 	ldrh.w	r2, [r4, #262]	; 0x106
    copy_cfg16_to_regs(p_regs, p_cfg, NB_OF_DDR_PHY_REGS_TO_CONFIG);
    
    /*--------------------------------------------------------------------------
     * Configure DDR FIC.
     */
    p_ddr_subsys_regs->fic.NB_ADDR_CR = p_ddr_subsys_cfg->fic.NB_ADDR_CR;
     f18:	f8c6 9400 	str.w	r9, [r6, #1024]	; 0x400
    p_ddr_subsys_regs->fic.NBRWB_SIZE_CR = p_ddr_subsys_cfg->fic.NBRWB_SIZE_CR;
     f1c:	f8c6 a404 	str.w	sl, [r6, #1028]	; 0x404
    p_ddr_subsys_regs->fic.WB_TIMEOUT_CR = p_ddr_subsys_cfg->fic.WB_TIMEOUT_CR;
     f20:	f8c6 8408 	str.w	r8, [r6, #1032]	; 0x408
    p_ddr_subsys_regs->fic.HPD_SW_RW_EN_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_EN_CR;
     f24:	f8c6 e40c 	str.w	lr, [r6, #1036]	; 0x40c
    p_ddr_subsys_regs->fic.HPD_SW_RW_INVAL_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_INVAL_CR;
     f28:	f8c6 c410 	str.w	ip, [r6, #1040]	; 0x410
    p_ddr_subsys_regs->fic.SW_WR_ERCLR_CR = p_ddr_subsys_cfg->fic.SW_WR_ERCLR_CR;
     f2c:	f8c6 7414 	str.w	r7, [r6, #1044]	; 0x414
    p_ddr_subsys_regs->fic.ERR_INT_ENABLE_CR = p_ddr_subsys_cfg->fic.ERR_INT_ENABLE_CR;
     f30:	f8c6 5418 	str.w	r5, [r6, #1048]	; 0x418
    p_ddr_subsys_regs->fic.NUM_AHB_MASTERS_CR = p_ddr_subsys_cfg->fic.NUM_AHB_MASTERS_CR;
     f34:	f8c6 041c 	str.w	r0, [r6, #1052]	; 0x41c
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[0] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_1_CR;
     f38:	f8c6 1440 	str.w	r1, [r6, #1088]	; 0x440
    p_ddr_subsys_regs->fic.LOCK_TIMEOUT_EN_CR = p_ddr_subsys_cfg->fic.LOCK_TIMEOUT_EN_CR;

    /*--------------------------------------------------------------------------
     * Enable DDR.
     */
    p_ddr_subsys_regs->ddrc.DYN_SOFT_RESET_CR = 0x01u;
     f3c:	2101      	movs	r1, #1
    p_ddr_subsys_regs->fic.HPD_SW_RW_INVAL_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_INVAL_CR;
    p_ddr_subsys_regs->fic.SW_WR_ERCLR_CR = p_ddr_subsys_cfg->fic.SW_WR_ERCLR_CR;
    p_ddr_subsys_regs->fic.ERR_INT_ENABLE_CR = p_ddr_subsys_cfg->fic.ERR_INT_ENABLE_CR;
    p_ddr_subsys_regs->fic.NUM_AHB_MASTERS_CR = p_ddr_subsys_cfg->fic.NUM_AHB_MASTERS_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[0] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_1_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[1] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_2_CR;
     f3e:	f8c6 2444 	str.w	r2, [r6, #1092]	; 0x444
    p_ddr_subsys_regs->fic.LOCK_TIMEOUT_EN_CR = p_ddr_subsys_cfg->fic.LOCK_TIMEOUT_EN_CR;
     f42:	f8c6 3448 	str.w	r3, [r6, #1096]	; 0x448

    /*--------------------------------------------------------------------------
     * Enable DDR.
     */
    p_ddr_subsys_regs->ddrc.DYN_SOFT_RESET_CR = 0x01u;
     f46:	6031      	str	r1, [r6, #0]
    
    while(0x0000u == p_ddr_subsys_regs->ddrc.DDRC_SR)
     f48:	f8d6 30e4 	ldr.w	r3, [r6, #228]	; 0xe4
     f4c:	2b00      	cmp	r3, #0
     f4e:	d0fb      	beq.n	f48 <SystemInit+0x110>
#endif

    /*--------------------------------------------------------------------------
     * Call user defined configuration function.
     */
    mscc_post_hw_cfg_init();
     f50:	f7ff fa1e 	bl	390 <mscc_post_hw_cfg_init>
     * do this here because this signal is only deasserted by the System
     * Controller on a power-on reset. Other types of reset such as a watchdog
     * reset would result in the FPGA fabric being held in reset and getting
     * stuck waiting for the CoreSF2Config INIT_DONE to become asserted.
     */
    SYSREG->SOFT_RST_CR &= ~SYSREG_FPGA_SOFTRESET_MASK;
     f54:	f248 0200 	movw	r2, #32768	; 0x8000
     f58:	f2c4 0203 	movt	r2, #16387	; 0x4003
     f5c:	6c93      	ldr	r3, [r2, #72]	; 0x48

    /*
     * Signal to CoreSF2Reset that peripheral configuration registers have been
     * written.
     */
    CORE_SF2_CFG->CONFIG_DONE |= (CONFIG_1_DONE | CONFIG_2_DONE);
     f5e:	f242 0000 	movw	r0, #8192	; 0x2000
     * do this here because this signal is only deasserted by the System
     * Controller on a power-on reset. Other types of reset such as a watchdog
     * reset would result in the FPGA fabric being held in reset and getting
     * stuck waiting for the CoreSF2Config INIT_DONE to become asserted.
     */
    SYSREG->SOFT_RST_CR &= ~SYSREG_FPGA_SOFTRESET_MASK;
     f62:	f423 3180 	bic.w	r1, r3, #65536	; 0x10000
     f66:	6491      	str	r1, [r2, #72]	; 0x48

    /*
     * Signal to CoreSF2Reset that peripheral configuration registers have been
     * written.
     */
    CORE_SF2_CFG->CONFIG_DONE |= (CONFIG_1_DONE | CONFIG_2_DONE);
     f68:	f2c4 0002 	movt	r0, #16386	; 0x4002
     f6c:	6803      	ldr	r3, [r0, #0]
     
    /* Wait for INIT_DONE from CoreSF2Reset. */
    do
    {
        init_done = CORE_SF2_CFG->INIT_DONE & INIT_DONE_MASK;
     f6e:	4602      	mov	r2, r0

    /*
     * Signal to CoreSF2Reset that peripheral configuration registers have been
     * written.
     */
    CORE_SF2_CFG->CONFIG_DONE |= (CONFIG_1_DONE | CONFIG_2_DONE);
     f70:	f043 0103 	orr.w	r1, r3, #3
     f74:	6001      	str	r1, [r0, #0]
     
    /* Wait for INIT_DONE from CoreSF2Reset. */
    do
    {
        init_done = CORE_SF2_CFG->INIT_DONE & INIT_DONE_MASK;
     f76:	6850      	ldr	r0, [r2, #4]
    } while (0u == init_done);
     f78:	f010 0f01 	tst.w	r0, #1
     f7c:	d0fb      	beq.n	f76 <SystemInit+0x13e>
#endif
}
     f7e:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     f82:	bf00      	nop

00000f84 <__libc_init_array>:
     f84:	b570      	push	{r4, r5, r6, lr}
     f86:	f241 16b4 	movw	r6, #4532	; 0x11b4
     f8a:	f241 15b4 	movw	r5, #4532	; 0x11b4
     f8e:	f2c0 0600 	movt	r6, #0
     f92:	f2c0 0500 	movt	r5, #0
     f96:	1b76      	subs	r6, r6, r5
     f98:	10b6      	asrs	r6, r6, #2
     f9a:	d006      	beq.n	faa <__libc_init_array+0x26>
     f9c:	2400      	movs	r4, #0
     f9e:	f855 3024 	ldr.w	r3, [r5, r4, lsl #2]
     fa2:	3401      	adds	r4, #1
     fa4:	4798      	blx	r3
     fa6:	42a6      	cmp	r6, r4
     fa8:	d8f9      	bhi.n	f9e <__libc_init_array+0x1a>
     faa:	f241 15b4 	movw	r5, #4532	; 0x11b4
     fae:	f241 16b8 	movw	r6, #4536	; 0x11b8
     fb2:	f2c0 0500 	movt	r5, #0
     fb6:	f2c0 0600 	movt	r6, #0
     fba:	1b76      	subs	r6, r6, r5
     fbc:	f000 f8ee 	bl	119c <_init>
     fc0:	10b6      	asrs	r6, r6, #2
     fc2:	d006      	beq.n	fd2 <__libc_init_array+0x4e>
     fc4:	2400      	movs	r4, #0
     fc6:	f855 3024 	ldr.w	r3, [r5, r4, lsl #2]
     fca:	3401      	adds	r4, #1
     fcc:	4798      	blx	r3
     fce:	42a6      	cmp	r6, r4
     fd0:	d8f9      	bhi.n	fc6 <__libc_init_array+0x42>
     fd2:	bd70      	pop	{r4, r5, r6, pc}
     fd4:	7344454c 	.word	0x7344454c
     fd8:	696c4220 	.word	0x696c4220
     fdc:	6e696b6e 	.word	0x6e696b6e
     fe0:	000d0a67 	.word	0x000d0a67

00000fe4 <g_gpio_irqn_lut>:
     fe4:	35343332 39383736 3d3c3b3a 41403f3e     23456789:;<=>?@A
     ff4:	45444342 49484746 4d4c4b4a 51504f4e     BCDEFGHIJKLMNOPQ

00001004 <g_config_reg_lut>:
    1004:	40013000 40013004 40013008 4001300c     .0.@.0.@.0.@.0.@
    1014:	40013010 40013014 40013018 4001301c     .0.@.0.@.0.@.0.@
    1024:	40013020 40013024 40013028 4001302c      0.@$0.@(0.@,0.@
    1034:	40013030 40013034 40013038 4001303c     00.@40.@80.@<0.@
    1044:	40013040 40013044 40013048 4001304c     @0.@D0.@H0.@L0.@
    1054:	40013050 40013054 40013058 4001305c     P0.@T0.@X0.@\0.@
    1064:	40013060 40013064 40013068 4001306c     `0.@d0.@h0.@l0.@
    1074:	40013070 40013074 40013078 4001307c     p0.@t0.@x0.@|0.@

00001084 <C.17.3534>:
    1084:	01000100 03030202                       ........

0000108c <g_m2s_mddr_subsys_config>:
    108c:	00000000 030f27de 00000002 09990101     .....'..........
    109c:	33330000 8888ffff 00010888 00084242     ..33........BB..
    10ac:	00000528 00000000 00860ce0 00640235     (...........5.d.
    10bc:	0178010f 19370033 00000010 00003300     ..x.3.7......3..
    10cc:	04060000 02000000 00120040 40000002     ........@......@
    10dc:	000780f8 000780f8 04000200 00050000     ................
    10ec:	00400003 00000000 00000000 00010309     ..@.............
    10fc:	00000000 00800000 00000000 00000003     ................
	...
    1114:	0000000b 00000000 00800000 01002004     ............. ..
    1124:	00000008 00000000 00000000 00000001     ................
	...
    113c:	05014050 00005014 00000000 00000000     P@...P..........
	...
    115c:	05010050 00005010 00000000 00000000     P....P..........
    116c:	00430000 00030000 00010001 00000000     ..C.............
    117c:	00010000 00000000 00000000 00000000     ................
	...

00001198 <g_m2s_mddr_addr>:
    1198:	40020800                                ...@

0000119c <_init>:
    119c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    119e:	bf00      	nop
    11a0:	bcf8      	pop	{r3, r4, r5, r6, r7}
    11a2:	bc08      	pop	{r3}
    11a4:	469e      	mov	lr, r3
    11a6:	4770      	bx	lr

000011a8 <_fini>:
    11a8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    11aa:	bf00      	nop
    11ac:	bcf8      	pop	{r3, r4, r5, r6, r7}
    11ae:	bc08      	pop	{r3}
    11b0:	469e      	mov	lr, r3
    11b2:	4770      	bx	lr

000011b4 <__frame_dummy_init_array_entry>:
    11b4:	0425 0000                                   %...

000011b8 <__do_global_dtors_aux_fini_array_entry>:
    11b8:	0411 0000 0000 0000                         ........
