
eNVM_to_SRAM_image1:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .vector_table 00000190  00000000  00000000  00008000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .boot_code    00000280  00000190  00000190  00008190  2**4
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  2 .text         00000d20  00000410  00000410  00008410  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  3 .data         00000020  00000000  00001130  00010000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  4 .bss          00000090  00000020  00000020  00010020  2**2
                  ALLOC
  5 .heap         00006f50  000000b0  00001150  000100b0  2**0
                  ALLOC
  6 .stack        00001000  00007000  00001150  00017000  2**0
                  ALLOC
  7 .comment      00000102  00000000  00000000  00010020  2**0
                  CONTENTS, READONLY
  8 .debug_aranges 000002b8  00000000  00000000  00010122  2**0
                  CONTENTS, READONLY, DEBUGGING
  9 .debug_pubnames 000007b9  00000000  00000000  000103da  2**0
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_info   000075b0  00000000  00000000  00010b93  2**0
                  CONTENTS, READONLY, DEBUGGING
 11 .debug_abbrev 00000b0f  00000000  00000000  00018143  2**0
                  CONTENTS, READONLY, DEBUGGING
 12 .debug_line   0000158b  00000000  00000000  00018c52  2**0
                  CONTENTS, READONLY, DEBUGGING
 13 .debug_frame  000006fc  00000000  00000000  0001a1e0  2**2
                  CONTENTS, READONLY, DEBUGGING
 14 .debug_str    000030b9  00000000  00000000  0001a8dc  2**0
                  CONTENTS, READONLY, DEBUGGING
 15 .debug_loc    00001182  00000000  00000000  0001d995  2**0
                  CONTENTS, READONLY, DEBUGGING
 16 .ARM.attributes 00000025  00000000  00000000  0001eb17  2**0
                  CONTENTS, READONLY
 17 .debug_ranges 00000eb8  00000000  00000000  0001eb3c  2**0
                  CONTENTS, READONLY, DEBUGGING

Disassembly of section .text:

00000410 <__do_global_dtors_aux>:
     410:	f240 0320 	movw	r3, #32
     414:	f2c0 0300 	movt	r3, #0
     418:	781a      	ldrb	r2, [r3, #0]
     41a:	b90a      	cbnz	r2, 420 <__do_global_dtors_aux+0x10>
     41c:	2001      	movs	r0, #1
     41e:	7018      	strb	r0, [r3, #0]
     420:	4770      	bx	lr
     422:	bf00      	nop

00000424 <frame_dummy>:
     424:	f240 0000 	movw	r0, #0
     428:	f2c0 0000 	movt	r0, #0
     42c:	b508      	push	{r3, lr}
     42e:	6803      	ldr	r3, [r0, #0]
     430:	b12b      	cbz	r3, 43e <frame_dummy+0x1a>
     432:	f240 0300 	movw	r3, #0
     436:	f2c0 0300 	movt	r3, #0
     43a:	b103      	cbz	r3, 43e <frame_dummy+0x1a>
     43c:	4798      	blx	r3
     43e:	bd08      	pop	{r3, pc}

00000440 <delay>:
     440:	4770      	bx	lr
     442:	bf00      	nop

00000444 <main>:
     444:	f240 0024 	movw	r0, #36	; 0x24
     448:	b508      	push	{r3, lr}
     44a:	2203      	movs	r2, #3
     44c:	f2c0 0000 	movt	r0, #0
     450:	f44f 4161 	mov.w	r1, #57600	; 0xe100
     454:	f000 fb40 	bl	ad8 <MSS_UART_init>
     458:	f000 fb6e 	bl	b38 <MSS_GPIO_init>
     45c:	2000      	movs	r0, #0
     45e:	2105      	movs	r1, #5
     460:	f000 fbb6 	bl	bd0 <MSS_GPIO_config>
     464:	2001      	movs	r0, #1
     466:	2105      	movs	r1, #5
     468:	f000 fbb2 	bl	bd0 <MSS_GPIO_config>
     46c:	2002      	movs	r0, #2
     46e:	2105      	movs	r1, #5
     470:	f000 fbae 	bl	bd0 <MSS_GPIO_config>
     474:	2003      	movs	r0, #3
     476:	2105      	movs	r1, #5
     478:	f000 fbaa 	bl	bd0 <MSS_GPIO_config>
     47c:	2004      	movs	r0, #4
     47e:	2105      	movs	r1, #5
     480:	f000 fba6 	bl	bd0 <MSS_GPIO_config>
     484:	2008      	movs	r0, #8
     486:	2105      	movs	r1, #5
     488:	f000 fba2 	bl	bd0 <MSS_GPIO_config>
     48c:	2009      	movs	r0, #9
     48e:	2105      	movs	r1, #5
     490:	f000 fb9e 	bl	bd0 <MSS_GPIO_config>
     494:	200a      	movs	r0, #10
     496:	2105      	movs	r1, #5
     498:	f000 fb9a 	bl	bd0 <MSS_GPIO_config>
     49c:	f240 0024 	movw	r0, #36	; 0x24
     4a0:	f640 713c 	movw	r1, #3900	; 0xf3c
     4a4:	2210      	movs	r2, #16
     4a6:	f2c0 0000 	movt	r0, #0
     4aa:	f2c0 0100 	movt	r1, #0
     4ae:	f000 f811 	bl	4d4 <MSS_UART_polled_tx>
     4b2:	2000      	movs	r0, #0
     4b4:	4601      	mov	r1, r0
     4b6:	f000 fb95 	bl	be4 <MSS_GPIO_set_output>
     4ba:	2000      	movs	r0, #0
     4bc:	2101      	movs	r1, #1
     4be:	f000 fb91 	bl	be4 <MSS_GPIO_set_output>
     4c2:	2001      	movs	r0, #1
     4c4:	2100      	movs	r1, #0
     4c6:	f000 fb8d 	bl	be4 <MSS_GPIO_set_output>
     4ca:	2001      	movs	r0, #1
     4cc:	4601      	mov	r1, r0
     4ce:	f000 fb89 	bl	be4 <MSS_GPIO_set_output>
     4d2:	e7e3      	b.n	49c <main+0x58>

000004d4 <MSS_UART_polled_tx>:

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(pbuff != ( (uint8_t *)0));
    ASSERT(tx_size > 0u);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
     4d4:	f240 0364 	movw	r3, #100	; 0x64
     4d8:	f2c0 0300 	movt	r3, #0
     4dc:	4298      	cmp	r0, r3
(
    mss_uart_instance_t * this_uart,
    const uint8_t * pbuff,
    uint32_t tx_size
)
{
     4de:	e92d 05f0 	stmdb	sp!, {r4, r5, r6, r7, r8, sl}

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(pbuff != ( (uint8_t *)0));
    ASSERT(tx_size > 0u);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
     4e2:	d008      	beq.n	4f6 <MSS_UART_polled_tx+0x22>
     4e4:	f240 0c24 	movw	ip, #36	; 0x24
     4e8:	f2c0 0c00 	movt	ip, #0
     4ec:	4560      	cmp	r0, ip
     4ee:	d002      	beq.n	4f6 <MSS_UART_polled_tx+0x22>
                /* Calculate the number of untransmitted bytes remaining. */
                tx_size -= size_sent;
            }
        } while(tx_size);
    }
}
     4f0:	e8bd 05f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, sl}
     4f4:	4770      	bx	lr

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(pbuff != ( (uint8_t *)0));
    ASSERT(tx_size > 0u);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
     4f6:	1e0b      	subs	r3, r1, #0
     4f8:	bf18      	it	ne
     4fa:	2301      	movne	r3, #1
     4fc:	2a00      	cmp	r2, #0
     4fe:	bf0c      	ite	eq
     500:	2300      	moveq	r3, #0
     502:	f003 0301 	andne.w	r3, r3, #1
     506:	2b00      	cmp	r3, #0
     508:	d0f2      	beq.n	4f0 <MSS_UART_polled_tx+0x1c>
     50a:	f890 800d 	ldrb.w	r8, [r0, #13]
         /* Remain in this loop until the entire input buffer
          * has been transferred to the UART.
          */
        do {
            /* Read the Line Status Register and update the sticky record */
            status = this_uart->hw_reg->LSR;
     50e:	f8d0 a000 	ldr.w	sl, [r0]
     512:	2500      	movs	r5, #0
     514:	f89a c014 	ldrb.w	ip, [sl, #20]
            this_uart->status |= status;
     518:	ea48 080c 	orr.w	r8, r8, ip

            /* Check if TX FIFO is empty. */
            if(status & MSS_UART_THRE)
     51c:	f01c 0f20 	tst.w	ip, #32
          * has been transferred to the UART.
          */
        do {
            /* Read the Line Status Register and update the sticky record */
            status = this_uart->hw_reg->LSR;
            this_uart->status |= status;
     520:	f880 800d 	strb.w	r8, [r0, #13]

            /* Check if TX FIFO is empty. */
            if(status & MSS_UART_THRE)
     524:	d023      	beq.n	56e <MSS_UART_polled_tx+0x9a>
            {
                uint32_t fill_size = TX_FIFO_SIZE;

                /* Calculate the number of bytes to transmit. */
                if(tx_size < TX_FIFO_SIZE)
     526:	2a0f      	cmp	r2, #15
     528:	d924      	bls.n	574 <MSS_UART_polled_tx+0xa0>
     52a:	2710      	movs	r7, #16

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     52c:	5d4e      	ldrb	r6, [r1, r5]
            if(status & MSS_UART_THRE)
            {
                uint32_t fill_size = TX_FIFO_SIZE;

                /* Calculate the number of bytes to transmit. */
                if(tx_size < TX_FIFO_SIZE)
     52e:	6804      	ldr	r4, [r0, #0]
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     530:	2301      	movs	r3, #1
     532:	f107 3cff 	add.w	ip, r7, #4294967295
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     536:	7026      	strb	r6, [r4, #0]
     538:	ea0c 0603 	and.w	r6, ip, r3
                    char_idx++;
     53c:	eb05 0c03 	add.w	ip, r5, r3
     540:	194d      	adds	r5, r1, r5
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     542:	42bb      	cmp	r3, r7
     544:	d211      	bcs.n	56a <MSS_UART_polled_tx+0x96>
     546:	b136      	cbz	r6, 556 <MSS_UART_polled_tx+0x82>
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     548:	5cee      	ldrb	r6, [r5, r3]
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     54a:	2302      	movs	r3, #2
     54c:	42bb      	cmp	r3, r7
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     54e:	7026      	strb	r6, [r4, #0]
                    char_idx++;
     550:	f10c 0c01 	add.w	ip, ip, #1
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     554:	d209      	bcs.n	56a <MSS_UART_polled_tx+0x96>
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     556:	5cee      	ldrb	r6, [r5, r3]
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     558:	3301      	adds	r3, #1
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     55a:	7026      	strb	r6, [r4, #0]
     55c:	5cee      	ldrb	r6, [r5, r3]
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     55e:	3301      	adds	r3, #1
     560:	42bb      	cmp	r3, r7
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     562:	7026      	strb	r6, [r4, #0]
                    char_idx++;
     564:	f10c 0c02 	add.w	ip, ip, #2
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     568:	d3f5      	bcc.n	556 <MSS_UART_polled_tx+0x82>
     56a:	4665      	mov	r5, ip
                    this_uart->hw_reg->THR = pbuff[char_idx];
                    char_idx++;
                }

                /* Calculate the number of untransmitted bytes remaining. */
                tx_size -= size_sent;
     56c:	1ad2      	subs	r2, r2, r3
            }
        } while(tx_size);
     56e:	2a00      	cmp	r2, #0
     570:	d1d0      	bne.n	514 <MSS_UART_polled_tx+0x40>
     572:	e7bd      	b.n	4f0 <MSS_UART_polled_tx+0x1c>
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     574:	b10a      	cbz	r2, 57a <MSS_UART_polled_tx+0xa6>
     576:	4617      	mov	r7, r2
     578:	e7d8      	b.n	52c <MSS_UART_polled_tx+0x58>
     57a:	4613      	mov	r3, r2
                    this_uart->hw_reg->THR = pbuff[char_idx];
                    char_idx++;
                }

                /* Calculate the number of untransmitted bytes remaining. */
                tx_size -= size_sent;
     57c:	1ad2      	subs	r2, r2, r3
     57e:	e7f6      	b.n	56e <MSS_UART_polled_tx+0x9a>

00000580 <MSS_UART_isr>:
{
    uint8_t iirf;

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
     580:	f240 0364 	movw	r3, #100	; 0x64
     584:	f2c0 0300 	movt	r3, #0
     588:	4298      	cmp	r0, r3
static void
MSS_UART_isr
(
    mss_uart_instance_t * this_uart
)
{
     58a:	b510      	push	{r4, lr}
     58c:	4604      	mov	r4, r0
    uint8_t iirf;

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
     58e:	d006      	beq.n	59e <MSS_UART_isr+0x1e>
     590:	f240 0024 	movw	r0, #36	; 0x24
     594:	f2c0 0000 	movt	r0, #0
     598:	4284      	cmp	r4, r0
     59a:	d000      	beq.n	59e <MSS_UART_isr+0x1e>
     59c:	bd10      	pop	{r4, pc}
    {
        iirf = this_uart->hw_reg->IIR & IIRF_MASK;
     59e:	6822      	ldr	r2, [r4, #0]
     5a0:	7a11      	ldrb	r1, [r2, #8]

        switch (iirf)
     5a2:	f001 0c0f 	and.w	ip, r1, #15
     5a6:	f1bc 0f0c 	cmp.w	ip, #12
     5aa:	d8f7      	bhi.n	59c <MSS_UART_isr+0x1c>
     5ac:	a101      	add	r1, pc, #4	; (adr r1, 5b4 <MSS_UART_isr+0x34>)
     5ae:	f851 f02c 	ldr.w	pc, [r1, ip, lsl #2]
     5b2:	bf00      	nop
     5b4:	00000605 	.word	0x00000605
     5b8:	0000059d 	.word	0x0000059d
     5bc:	000005fd 	.word	0x000005fd
     5c0:	0000060d 	.word	0x0000060d
     5c4:	000005f5 	.word	0x000005f5
     5c8:	0000059d 	.word	0x0000059d
     5cc:	000005e9 	.word	0x000005e9
     5d0:	0000059d 	.word	0x0000059d
     5d4:	0000059d 	.word	0x0000059d
     5d8:	0000059d 	.word	0x0000059d
     5dc:	0000059d 	.word	0x0000059d
     5e0:	0000059d 	.word	0x0000059d
     5e4:	000005f5 	.word	0x000005f5
            break;

            case IIRF_RX_LINE_STATUS:  /* Line Status Interrupt */
            {
                ASSERT(NULL_HANDLER != this_uart->linests_handler);
                if(NULL_HANDLER != this_uart->linests_handler)
     5e8:	69e3      	ldr	r3, [r4, #28]
     5ea:	2b00      	cmp	r3, #0
     5ec:	d0d6      	beq.n	59c <MSS_UART_isr+0x1c>
                {
                   (*(this_uart->linests_handler))(this_uart);
     5ee:	4620      	mov	r0, r4
     5f0:	4798      	blx	r3
     5f2:	bd10      	pop	{r4, pc}

            case IIRF_RX_DATA:      /* Received Data Available */
            case IIRF_DATA_TIMEOUT: /* Received Data Timed-out */
            {
                ASSERT(NULL_HANDLER != this_uart->rx_handler);
                if(NULL_HANDLER != this_uart->rx_handler)
     5f4:	6a23      	ldr	r3, [r4, #32]
     5f6:	2b00      	cmp	r3, #0
     5f8:	d1f9      	bne.n	5ee <MSS_UART_isr+0x6e>
     5fa:	e7cf      	b.n	59c <MSS_UART_isr+0x1c>
            break;

            case IIRF_THRE: /* Transmitter Holding Register Empty */
            {
                ASSERT(NULL_HANDLER != this_uart->tx_handler);
                if(NULL_HANDLER != this_uart->tx_handler)
     5fc:	6a63      	ldr	r3, [r4, #36]	; 0x24
     5fe:	2b00      	cmp	r3, #0
     600:	d1f5      	bne.n	5ee <MSS_UART_isr+0x6e>
     602:	e7cb      	b.n	59c <MSS_UART_isr+0x1c>
        switch (iirf)
        {
            case IIRF_MODEM_STATUS:  /* Modem status interrupt */
            {
                ASSERT(NULL_HANDLER != this_uart->modemsts_handler);
                if(NULL_HANDLER != this_uart->modemsts_handler)
     604:	6aa3      	ldr	r3, [r4, #40]	; 0x28
     606:	2b00      	cmp	r3, #0
     608:	d1f1      	bne.n	5ee <MSS_UART_isr+0x6e>
     60a:	e7c7      	b.n	59c <MSS_UART_isr+0x1c>
            case IIRF_MMI:
            {
                /* Identify multimode interrupts and handle */

                /* Receiver time-out interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,ERTOI))
     60c:	3228      	adds	r2, #40	; 0x28
{
    return (HW_REG_BIT(reg,bit));
}
static __INLINE uint8_t read_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    return (HW_REG_BIT(reg,bit));
     60e:	f022 407f 	bic.w	r0, r2, #4278190080	; 0xff000000
     612:	f420 0370 	bic.w	r3, r0, #15728640	; 0xf00000
     616:	f002 4170 	and.w	r1, r2, #4026531840	; 0xf0000000
     61a:	0158      	lsls	r0, r3, #5
     61c:	f101 7c00 	add.w	ip, r1, #33554432	; 0x2000000
     620:	f85c 3000 	ldr.w	r3, [ip, r0]
     624:	f013 0fff 	tst.w	r3, #255	; 0xff
     628:	d005      	beq.n	636 <MSS_UART_isr+0xb6>
                {
                    ASSERT(NULL_HANDLER != this_uart->rto_handler);
                    if(NULL_HANDLER != this_uart->rto_handler)
     62a:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
     62c:	b11b      	cbz	r3, 636 <MSS_UART_isr+0xb6>
                    {
                        (*(this_uart->rto_handler))(this_uart);
     62e:	4620      	mov	r0, r4
     630:	4798      	blx	r3
     632:	6822      	ldr	r2, [r4, #0]
     634:	3228      	adds	r2, #40	; 0x28
     636:	f002 4070 	and.w	r0, r2, #4026531840	; 0xf0000000
     63a:	f022 4c7f 	bic.w	ip, r2, #4278190080	; 0xff000000
     63e:	f100 7300 	add.w	r3, r0, #33554432	; 0x2000000
     642:	f42c 0170 	bic.w	r1, ip, #15728640	; 0xf00000
     646:	1d18      	adds	r0, r3, #4
     648:	0149      	lsls	r1, r1, #5
     64a:	5843      	ldr	r3, [r0, r1]
                    }
                }
                /* NACK interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,ENACKI))
     64c:	f013 0fff 	tst.w	r3, #255	; 0xff
     650:	d005      	beq.n	65e <MSS_UART_isr+0xde>
                {
                    ASSERT(NULL_HANDLER != this_uart->nack_handler);
                    if(NULL_HANDLER != this_uart->nack_handler)
     652:	6b23      	ldr	r3, [r4, #48]	; 0x30
     654:	b11b      	cbz	r3, 65e <MSS_UART_isr+0xde>
                    {
                        (*(this_uart->nack_handler))(this_uart);
     656:	4620      	mov	r0, r4
     658:	4798      	blx	r3
     65a:	6822      	ldr	r2, [r4, #0]
     65c:	3228      	adds	r2, #40	; 0x28
     65e:	f002 4370 	and.w	r3, r2, #4026531840	; 0xf0000000
     662:	f022 4c7f 	bic.w	ip, r2, #4278190080	; 0xff000000
     666:	f103 7000 	add.w	r0, r3, #33554432	; 0x2000000
     66a:	f42c 0170 	bic.w	r1, ip, #15728640	; 0xf00000
     66e:	3008      	adds	r0, #8
     670:	0149      	lsls	r1, r1, #5
     672:	5843      	ldr	r3, [r0, r1]
                    }
                }

                /* PID parity error interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,EPID_PEI))
     674:	f013 0fff 	tst.w	r3, #255	; 0xff
     678:	d005      	beq.n	686 <MSS_UART_isr+0x106>
                {
                    ASSERT(NULL_HANDLER != this_uart->pid_pei_handler);
                    if(NULL_HANDLER != this_uart->pid_pei_handler)
     67a:	6b63      	ldr	r3, [r4, #52]	; 0x34
     67c:	b11b      	cbz	r3, 686 <MSS_UART_isr+0x106>
                    {
                        (*(this_uart->pid_pei_handler))(this_uart);
     67e:	4620      	mov	r0, r4
     680:	4798      	blx	r3
     682:	6822      	ldr	r2, [r4, #0]
     684:	3228      	adds	r2, #40	; 0x28
     686:	f002 4370 	and.w	r3, r2, #4026531840	; 0xf0000000
     68a:	f022 4c7f 	bic.w	ip, r2, #4278190080	; 0xff000000
     68e:	f42c 0070 	bic.w	r0, ip, #15728640	; 0xf00000
     692:	f103 7300 	add.w	r3, r3, #33554432	; 0x2000000
     696:	330c      	adds	r3, #12
     698:	0141      	lsls	r1, r0, #5
     69a:	5858      	ldr	r0, [r3, r1]
                    }
                }

                /* LIN break detection interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,ELINBI))
     69c:	f010 0fff 	tst.w	r0, #255	; 0xff
     6a0:	d005      	beq.n	6ae <MSS_UART_isr+0x12e>
                {
                    ASSERT(NULL_HANDLER != this_uart->break_handler);
                    if(NULL_HANDLER != this_uart->break_handler)
     6a2:	6ba3      	ldr	r3, [r4, #56]	; 0x38
     6a4:	b11b      	cbz	r3, 6ae <MSS_UART_isr+0x12e>
                    {
                        (*(this_uart->break_handler))(this_uart);
     6a6:	4620      	mov	r0, r4
     6a8:	4798      	blx	r3
     6aa:	6822      	ldr	r2, [r4, #0]
     6ac:	3228      	adds	r2, #40	; 0x28
     6ae:	f022 4c7f 	bic.w	ip, r2, #4278190080	; 0xff000000
     6b2:	f002 4170 	and.w	r1, r2, #4026531840	; 0xf0000000
     6b6:	f101 7200 	add.w	r2, r1, #33554432	; 0x2000000
     6ba:	f42c 0370 	bic.w	r3, ip, #15728640	; 0xf00000
     6be:	3210      	adds	r2, #16
     6c0:	0158      	lsls	r0, r3, #5
     6c2:	5811      	ldr	r1, [r2, r0]
                    }
                }

                /* LIN Sync detection interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,ELINSI))
     6c4:	f011 0fff 	tst.w	r1, #255	; 0xff
     6c8:	f43f af68 	beq.w	59c <MSS_UART_isr+0x1c>
                {
                    ASSERT(NULL_HANDLER != this_uart->sync_handler);
                    if(NULL_HANDLER != this_uart->sync_handler)
     6cc:	6be3      	ldr	r3, [r4, #60]	; 0x3c
     6ce:	2b00      	cmp	r3, #0
     6d0:	f43f af64 	beq.w	59c <MSS_UART_isr+0x1c>
                    {
                        (*(this_uart->sync_handler))(this_uart);
     6d4:	4620      	mov	r0, r4
     6d6:	4798      	blx	r3
     6d8:	e760      	b.n	59c <MSS_UART_isr+0x1c>
     6da:	bf00      	nop

000006dc <UART1_IRQHandler>:
#if defined(__GNUC__)
__attribute__((__interrupt__)) void UART1_IRQHandler(void)
#else
void UART1_IRQHandler(void)
#endif
{
     6dc:	4668      	mov	r0, sp
     6de:	f020 0107 	bic.w	r1, r0, #7
     6e2:	468d      	mov	sp, r1
     6e4:	b501      	push	{r0, lr}
    MSS_UART_isr(&g_mss_uart1);
     6e6:	f240 0024 	movw	r0, #36	; 0x24
     6ea:	f2c0 0000 	movt	r0, #0
     6ee:	f7ff ff47 	bl	580 <MSS_UART_isr>
}
     6f2:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
     6f6:	4685      	mov	sp, r0
     6f8:	4770      	bx	lr
     6fa:	bf00      	nop

000006fc <UART0_IRQHandler>:
#if defined(__GNUC__)
__attribute__((__interrupt__)) void UART0_IRQHandler(void)
#else
void UART0_IRQHandler(void)
#endif
{
     6fc:	4668      	mov	r0, sp
     6fe:	f020 0107 	bic.w	r1, r0, #7
     702:	468d      	mov	sp, r1
     704:	b501      	push	{r0, lr}
    MSS_UART_isr(&g_mss_uart0);
     706:	f240 0064 	movw	r0, #100	; 0x64
     70a:	f2c0 0000 	movt	r0, #0
     70e:	f7ff ff37 	bl	580 <MSS_UART_isr>
}
     712:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
     716:	4685      	mov	sp, r0
     718:	4770      	bx	lr
     71a:	bf00      	nop

0000071c <default_tx_handler>:

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(( (uint8_t *)0 ) != this_uart->tx_buffer);
    ASSERT(0u < this_uart->tx_buff_size);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
     71c:	f240 0364 	movw	r3, #100	; 0x64
     720:	f2c0 0300 	movt	r3, #0
     724:	4298      	cmp	r0, r3
static void
default_tx_handler
(
    mss_uart_instance_t * this_uart
)
{
     726:	b470      	push	{r4, r5, r6}

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(( (uint8_t *)0 ) != this_uart->tx_buffer);
    ASSERT(0u < this_uart->tx_buff_size);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
     728:	d007      	beq.n	73a <default_tx_handler+0x1e>
     72a:	f240 0124 	movw	r1, #36	; 0x24
     72e:	f2c0 0100 	movt	r1, #0
     732:	4288      	cmp	r0, r1
     734:	d001      	beq.n	73a <default_tx_handler+0x1e>
            this_uart->tx_buff_size = TX_COMPLETE;
            /* disables TX interrupt */
            clear_bit_reg8(&this_uart->hw_reg->IER,ETBEI);
        }
    }
}
     736:	bc70      	pop	{r4, r5, r6}
     738:	4770      	bx	lr
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(( (uint8_t *)0 ) != this_uart->tx_buffer);
    ASSERT(0u < this_uart->tx_buff_size);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
       (((uint8_t *)0 ) != this_uart->tx_buffer) &&
     73a:	6904      	ldr	r4, [r0, #16]
     73c:	2c00      	cmp	r4, #0
     73e:	d0fa      	beq.n	736 <default_tx_handler+0x1a>
       (0u < this_uart->tx_buff_size))
     740:	6943      	ldr	r3, [r0, #20]
     742:	2b00      	cmp	r3, #0
     744:	d0f7      	beq.n	736 <default_tx_handler+0x1a>
    {
        /* Read the Line Status Register and update the sticky record. */
        status = this_uart->hw_reg->LSR;
     746:	6801      	ldr	r1, [r0, #0]
        this_uart->status |= status;
     748:	f890 c00d 	ldrb.w	ip, [r0, #13]
    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
       (((uint8_t *)0 ) != this_uart->tx_buffer) &&
       (0u < this_uart->tx_buff_size))
    {
        /* Read the Line Status Register and update the sticky record. */
        status = this_uart->hw_reg->LSR;
     74c:	7d0a      	ldrb	r2, [r1, #20]
        this_uart->status |= status;
     74e:	ea42 0c0c 	orr.w	ip, r2, ip

        /*
         * This function should only be called as a result of a THRE interrupt.
         * Verify that this is true before proceeding to transmit data.
         */
        if(status & MSS_UART_THRE)
     752:	f012 0f20 	tst.w	r2, #32
       (((uint8_t *)0 ) != this_uart->tx_buffer) &&
       (0u < this_uart->tx_buff_size))
    {
        /* Read the Line Status Register and update the sticky record. */
        status = this_uart->hw_reg->LSR;
        this_uart->status |= status;
     756:	f880 c00d 	strb.w	ip, [r0, #13]

        /*
         * This function should only be called as a result of a THRE interrupt.
         * Verify that this is true before proceeding to transmit data.
         */
        if(status & MSS_UART_THRE)
     75a:	6982      	ldr	r2, [r0, #24]
     75c:	d029      	beq.n	7b2 <default_tx_handler+0x96>
        {
            uint32_t i;
            uint32_t fill_size = TX_FIFO_SIZE;
            uint32_t tx_remain = this_uart->tx_buff_size - this_uart->tx_idx;
     75e:	1a9d      	subs	r5, r3, r2

            /* Calculate the number of bytes to transmit. */
            if(tx_remain < TX_FIFO_SIZE)
     760:	2d0f      	cmp	r5, #15
     762:	d938      	bls.n	7d6 <default_tx_handler+0xba>
     764:	2510      	movs	r5, #16
     766:	18a4      	adds	r4, r4, r2

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     768:	7826      	ldrb	r6, [r4, #0]
     76a:	1e6b      	subs	r3, r5, #1
     76c:	700e      	strb	r6, [r1, #0]
     76e:	f003 0601 	and.w	r6, r3, #1
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     772:	2301      	movs	r3, #1
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
                ++this_uart->tx_idx;
     774:	3201      	adds	r2, #1
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     776:	429d      	cmp	r5, r3
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
                ++this_uart->tx_idx;
     778:	6182      	str	r2, [r0, #24]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     77a:	d919      	bls.n	7b0 <default_tx_handler+0x94>
     77c:	b146      	cbz	r6, 790 <default_tx_handler+0x74>
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     77e:	f894 c001 	ldrb.w	ip, [r4, #1]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     782:	2302      	movs	r3, #2
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
                ++this_uart->tx_idx;
     784:	3201      	adds	r2, #1
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     786:	429d      	cmp	r5, r3
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     788:	f881 c000 	strb.w	ip, [r1]
                ++this_uart->tx_idx;
     78c:	6182      	str	r2, [r0, #24]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     78e:	d90f      	bls.n	7b0 <default_tx_handler+0x94>
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     790:	f814 c003 	ldrb.w	ip, [r4, r3]
                ++this_uart->tx_idx;
     794:	3201      	adds	r2, #1

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     796:	f881 c000 	strb.w	ip, [r1]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     79a:	3301      	adds	r3, #1
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
                ++this_uart->tx_idx;
     79c:	6182      	str	r2, [r0, #24]

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     79e:	f814 c003 	ldrb.w	ip, [r4, r3]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     7a2:	3301      	adds	r3, #1
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
                ++this_uart->tx_idx;
     7a4:	3201      	adds	r2, #1
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     7a6:	429d      	cmp	r5, r3
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     7a8:	f881 c000 	strb.w	ip, [r1]
                ++this_uart->tx_idx;
     7ac:	6182      	str	r2, [r0, #24]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     7ae:	d8ef      	bhi.n	790 <default_tx_handler+0x74>
     7b0:	6943      	ldr	r3, [r0, #20]
                ++this_uart->tx_idx;
            }
        }

        /* Flag Tx as complete if all data has been pushed into the Tx FIFO. */
        if(this_uart->tx_idx == this_uart->tx_buff_size)
     7b2:	429a      	cmp	r2, r3
     7b4:	d1bf      	bne.n	736 <default_tx_handler+0x1a>
        {
            this_uart->tx_buff_size = TX_COMPLETE;
            /* disables TX interrupt */
            clear_bit_reg8(&this_uart->hw_reg->IER,ETBEI);
     7b6:	6802      	ldr	r2, [r0, #0]
        }

        /* Flag Tx as complete if all data has been pushed into the Tx FIFO. */
        if(this_uart->tx_idx == this_uart->tx_buff_size)
        {
            this_uart->tx_buff_size = TX_COMPLETE;
     7b8:	2100      	movs	r1, #0
            /* disables TX interrupt */
            clear_bit_reg8(&this_uart->hw_reg->IER,ETBEI);
     7ba:	1d13      	adds	r3, r2, #4
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     7bc:	f023 4c7f 	bic.w	ip, r3, #4278190080	; 0xff000000
     7c0:	f003 4270 	and.w	r2, r3, #4026531840	; 0xf0000000
     7c4:	f102 7300 	add.w	r3, r2, #33554432	; 0x2000000
     7c8:	f42c 0270 	bic.w	r2, ip, #15728640	; 0xf00000
     7cc:	3304      	adds	r3, #4
     7ce:	0152      	lsls	r2, r2, #5
     7d0:	5099      	str	r1, [r3, r2]
        }

        /* Flag Tx as complete if all data has been pushed into the Tx FIFO. */
        if(this_uart->tx_idx == this_uart->tx_buff_size)
        {
            this_uart->tx_buff_size = TX_COMPLETE;
     7d2:	6141      	str	r1, [r0, #20]
     7d4:	e7af      	b.n	736 <default_tx_handler+0x1a>
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     7d6:	2d00      	cmp	r5, #0
     7d8:	d1c5      	bne.n	766 <default_tx_handler+0x4a>
     7da:	e7ea      	b.n	7b2 <default_tx_handler+0x96>

000007dc <global_init>:
(
    mss_uart_instance_t * this_uart,
    uint32_t baud_rate,
    uint8_t line_config
)
{
     7dc:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
     7e0:	f240 0364 	movw	r3, #100	; 0x64
(
    mss_uart_instance_t * this_uart,
    uint32_t baud_rate,
    uint8_t line_config
)
{
     7e4:	b08f      	sub	sp, #60	; 0x3c
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
     7e6:	f2c0 0300 	movt	r3, #0
(
    mss_uart_instance_t * this_uart,
    uint32_t baud_rate,
    uint8_t line_config
)
{
     7ea:	920b      	str	r2, [sp, #44]	; 0x2c
    if(this_uart == &g_mss_uart0)
    {
        this_uart->hw_reg = UART0;
        this_uart->irqn = UART0_IRQn;
        /* reset UART0 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART0_SOFTRESET_MASK;
     7ec:	f248 0200 	movw	r2, #32768	; 0x8000
{
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
     7f0:	4298      	cmp	r0, r3
    {
        this_uart->hw_reg = UART0;
        this_uart->irqn = UART0_IRQn;
        /* reset UART0 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART0_SOFTRESET_MASK;
     7f2:	f2c4 0203 	movt	r2, #16387	; 0x4003
(
    mss_uart_instance_t * this_uart,
    uint32_t baud_rate,
    uint8_t line_config
)
{
     7f6:	4604      	mov	r4, r0
     7f8:	910d      	str	r1, [sp, #52]	; 0x34
    if(this_uart == &g_mss_uart0)
    {
        this_uart->hw_reg = UART0;
        this_uart->irqn = UART0_IRQn;
        /* reset UART0 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART0_SOFTRESET_MASK;
     7fa:	6c90      	ldr	r0, [r2, #72]	; 0x48

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
     7fc:	f24e 1100 	movw	r1, #57600	; 0xe100
{
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
     800:	f000 8129 	beq.w	a56 <global_init+0x27a>
    else
    {
        this_uart->hw_reg = UART1;
        this_uart->irqn = UART1_IRQn;
        /* Reset UART1 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART1_SOFTRESET_MASK;
     804:	f440 7780 	orr.w	r7, r0, #256	; 0x100
     808:	f2ce 0100 	movt	r1, #57344	; 0xe000
     80c:	f44f 6600 	mov.w	r6, #2048	; 0x800
     810:	6497      	str	r7, [r2, #72]	; 0x48
     812:	f8c1 6180 	str.w	r6, [r1, #384]	; 0x180
        /* Clear any previously pended UART1 interrupt */
        NVIC_ClearPendingIRQ(UART1_IRQn);
        /* Take UART1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART1_SOFTRESET_MASK;
     816:	6c95      	ldr	r5, [r2, #72]	; 0x48
        /* Take UART0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
    }
    else
    {
        this_uart->hw_reg = UART1;
     818:	f240 0100 	movw	r1, #0
        /* Reset UART1 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART1_SOFTRESET_MASK;
        /* Clear any previously pended UART1 interrupt */
        NVIC_ClearPendingIRQ(UART1_IRQn);
        /* Take UART1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART1_SOFTRESET_MASK;
     81c:	f425 7080 	bic.w	r0, r5, #256	; 0x100
        /* Take UART0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
    }
    else
    {
        this_uart->hw_reg = UART1;
     820:	f2c4 0101 	movt	r1, #16385	; 0x4001
        /* Reset UART1 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART1_SOFTRESET_MASK;
        /* Clear any previously pended UART1 interrupt */
        NVIC_ClearPendingIRQ(UART1_IRQn);
        /* Take UART1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART1_SOFTRESET_MASK;
     824:	6490      	str	r0, [r2, #72]	; 0x48
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
    }
    else
    {
        this_uart->hw_reg = UART1;
        this_uart->irqn = UART1_IRQn;
     826:	220b      	movs	r2, #11
     828:	7122      	strb	r2, [r4, #4]
        /* Take UART0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
    }
    else
    {
        this_uart->hw_reg = UART1;
     82a:	6021      	str	r1, [r4, #0]
        /* Take UART1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART1_SOFTRESET_MASK;
    }

    /* disable interrupts */
    this_uart->hw_reg->IER = 0u;
     82c:	2200      	movs	r2, #0

    /* FIFO configuration */
    this_uart->hw_reg->FCR = (uint8_t)MSS_UART_FIFO_SINGLE_BYTE;
     82e:	460d      	mov	r5, r1
        /* Take UART1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART1_SOFTRESET_MASK;
    }

    /* disable interrupts */
    this_uart->hw_reg->IER = 0u;
     830:	710a      	strb	r2, [r1, #4]
    /* enable RXRDYN and TXRDYN pins. The earlier FCR write to set the TX FIFO
     * trigger level inadvertently disabled the FCR_RXRDY_TXRDYN_EN bit. */
    set_bit_reg8(&this_uart->hw_reg->FCR,RXRDY_TXRDYN_EN);

    /* disable loopback : local * remote */
    clear_bit_reg8(&this_uart->hw_reg->MCR,LOOP);
     832:	f101 0610 	add.w	r6, r1, #16

    /* disable interrupts */
    this_uart->hw_reg->IER = 0u;

    /* FIFO configuration */
    this_uart->hw_reg->FCR = (uint8_t)MSS_UART_FIFO_SINGLE_BYTE;
     836:	f805 2f08 	strb.w	r2, [r5, #8]!
    clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_TX);
    /* set default RX endian */
    clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_RX);

    /* default AFM : disabled */
    clear_bit_reg8(&this_uart->hw_reg->MM2,EAFM);
     83a:	f101 0a38 	add.w	sl, r1, #56	; 0x38
     83e:	f02a 4b7f 	bic.w	fp, sl, #4278190080	; 0xff000000
    /* disable loopback : local * remote */
    clear_bit_reg8(&this_uart->hw_reg->MCR,LOOP);
    clear_bit_reg8(&this_uart->hw_reg->MCR,RLOOP);

    /* set default TX endian */
    clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_TX);
     842:	f101 0934 	add.w	r9, r1, #52	; 0x34
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     846:	f025 477f 	bic.w	r7, r5, #4278190080	; 0xff000000
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     84a:	f026 487f 	bic.w	r8, r6, #4278190080	; 0xff000000
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     84e:	f005 4570 	and.w	r5, r5, #4026531840	; 0xf0000000
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     852:	f006 4670 	and.w	r6, r6, #4026531840	; 0xf0000000
     856:	f00a 4a70 	and.w	sl, sl, #4026531840	; 0xf0000000
     85a:	f8cd a010 	str.w	sl, [sp, #16]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     85e:	9506      	str	r5, [sp, #24]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     860:	f029 407f 	bic.w	r0, r9, #4278190080	; 0xff000000
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     864:	f106 7500 	add.w	r5, r6, #33554432	; 0x2000000
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     868:	9003      	str	r0, [sp, #12]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     86a:	9501      	str	r5, [sp, #4]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     86c:	f009 4970 	and.w	r9, r9, #4026531840	; 0xf0000000
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     870:	9d04      	ldr	r5, [sp, #16]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     872:	f8cd 901c 	str.w	r9, [sp, #28]
     876:	f8dd 900c 	ldr.w	r9, [sp, #12]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     87a:	f105 7500 	add.w	r5, r5, #33554432	; 0x2000000
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     87e:	f429 0a70 	bic.w	sl, r9, #15728640	; 0xf00000
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     882:	950a      	str	r5, [sp, #40]	; 0x28
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     884:	f42b 0970 	bic.w	r9, fp, #15728640	; 0xf00000
     888:	9d07      	ldr	r5, [sp, #28]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     88a:	f8dd b018 	ldr.w	fp, [sp, #24]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     88e:	f8cd 9014 	str.w	r9, [sp, #20]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     892:	f10b 7900 	add.w	r9, fp, #33554432	; 0x2000000
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     896:	f105 7b00 	add.w	fp, r5, #33554432	; 0x2000000
     89a:	9d04      	ldr	r5, [sp, #16]

    /* default AFM : disabled */
    clear_bit_reg8(&this_uart->hw_reg->MM2,EAFM);

    /* disable TX time gaurd */
    clear_bit_reg8(&this_uart->hw_reg->MM0,ETTG); 
     89c:	f101 0c30 	add.w	ip, r1, #48	; 0x30
     8a0:	f02c 407f 	bic.w	r0, ip, #4278190080	; 0xff000000
     8a4:	f105 7500 	add.w	r5, r5, #33554432	; 0x2000000
     8a8:	f00c 4c70 	and.w	ip, ip, #4026531840	; 0xf0000000
     8ac:	f8cd a00c 	str.w	sl, [sp, #12]
     8b0:	9504      	str	r5, [sp, #16]
     8b2:	f10c 7500 	add.w	r5, ip, #33554432	; 0x2000000
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     8b6:	f10c 7a00 	add.w	sl, ip, #33554432	; 0x2000000
     8ba:	46ac      	mov	ip, r5
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     8bc:	9d03      	ldr	r5, [sp, #12]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     8be:	f8cd a024 	str.w	sl, [sp, #36]	; 0x24
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     8c2:	016d      	lsls	r5, r5, #5
     8c4:	9503      	str	r5, [sp, #12]
     8c6:	9d05      	ldr	r5, [sp, #20]
     8c8:	f428 0870 	bic.w	r8, r8, #15728640	; 0xf00000
     8cc:	016d      	lsls	r5, r5, #5
     8ce:	9505      	str	r5, [sp, #20]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     8d0:	9d06      	ldr	r5, [sp, #24]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     8d2:	46ca      	mov	sl, r9
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     8d4:	f105 7500 	add.w	r5, r5, #33554432	; 0x2000000
     8d8:	9506      	str	r5, [sp, #24]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     8da:	9d01      	ldr	r5, [sp, #4]
     8dc:	ea4f 1848 	mov.w	r8, r8, lsl #5
     8e0:	3514      	adds	r5, #20
     8e2:	9501      	str	r5, [sp, #4]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     8e4:	9d07      	ldr	r5, [sp, #28]
     8e6:	f427 0770 	bic.w	r7, r7, #15728640	; 0xf00000
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     8ea:	f105 7500 	add.w	r5, r5, #33554432	; 0x2000000
     8ee:	9507      	str	r5, [sp, #28]
     8f0:	9d04      	ldr	r5, [sp, #16]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     8f2:	017f      	lsls	r7, r7, #5
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     8f4:	3504      	adds	r5, #4
     8f6:	9504      	str	r5, [sp, #16]
     8f8:	4665      	mov	r5, ip
     8fa:	3514      	adds	r5, #20
     8fc:	9508      	str	r5, [sp, #32]
     8fe:	9d09      	ldr	r5, [sp, #36]	; 0x24
     900:	f8cd 8030 	str.w	r8, [sp, #48]	; 0x30
     904:	351c      	adds	r5, #28
     906:	9509      	str	r5, [sp, #36]	; 0x24
     908:	9d0a      	ldr	r5, [sp, #40]	; 0x28
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     90a:	f04f 0801 	mov.w	r8, #1
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     90e:	350c      	adds	r5, #12
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     910:	f10a 0a08 	add.w	sl, sl, #8
     914:	f109 0904 	add.w	r9, r9, #4
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     918:	950a      	str	r5, [sp, #40]	; 0x28
     91a:	f106 7600 	add.w	r6, r6, #33554432	; 0x2000000
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     91e:	f849 8007 	str.w	r8, [r9, r7]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     922:	9d0c      	ldr	r5, [sp, #48]	; 0x30
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     924:	f84a 8007 	str.w	r8, [sl, r7]
     928:	f8dd a018 	ldr.w	sl, [sp, #24]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     92c:	3610      	adds	r6, #16
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     92e:	f84a 8007 	str.w	r8, [sl, r7]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     932:	5172      	str	r2, [r6, r5]
     934:	f8dd a00c 	ldr.w	sl, [sp, #12]
     938:	9e01      	ldr	r6, [sp, #4]
     93a:	f10b 0b04 	add.w	fp, fp, #4
     93e:	5172      	str	r2, [r6, r5]
     940:	f84b 200a 	str.w	r2, [fp, sl]
     944:	f8dd b01c 	ldr.w	fp, [sp, #28]
     948:	9d05      	ldr	r5, [sp, #20]
     94a:	f84b 200a 	str.w	r2, [fp, sl]
     94e:	9e04      	ldr	r6, [sp, #16]
     950:	f8dd a020 	ldr.w	sl, [sp, #32]
     954:	f420 0070 	bic.w	r0, r0, #15728640	; 0xf00000
     958:	0140      	lsls	r0, r0, #5
     95a:	f10c 0c18 	add.w	ip, ip, #24
     95e:	5172      	str	r2, [r6, r5]
     960:	f8dd b024 	ldr.w	fp, [sp, #36]	; 0x24
     964:	f84a 2000 	str.w	r2, [sl, r0]
     968:	f84c 2000 	str.w	r2, [ip, r0]
     96c:	f8dd c028 	ldr.w	ip, [sp, #40]	; 0x28
    uint32_t baudrate    
)
{
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    
    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
     970:	429c      	cmp	r4, r3
     972:	f84b 2000 	str.w	r2, [fp, r0]
     976:	f84c 2005 	str.w	r2, [ip, r5]

    /* disable single wire mode */
    clear_bit_reg8(&this_uart->hw_reg->MM2,ESWM);

    /* set filter to minimum value */
    this_uart->hw_reg->GFR = 0u;
     97a:	f881 2044 	strb.w	r2, [r1, #68]	; 0x44
    /* set default TX time gaurd */
    this_uart->hw_reg->TTG = 0u;
     97e:	f881 2048 	strb.w	r2, [r1, #72]	; 0x48
    /* set default RX timeout */
    this_uart->hw_reg->RTO = 0u;
     982:	f881 204c 	strb.w	r2, [r1, #76]	; 0x4c
    uint32_t baudrate    
)
{
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    
    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
     986:	d079      	beq.n	a7c <global_init+0x2a0>
     988:	f240 0324 	movw	r3, #36	; 0x24
     98c:	f2c0 0300 	movt	r3, #0
     990:	429c      	cmp	r4, r3
     992:	d015      	beq.n	9c0 <global_init+0x1e4>
     * where possible to provide the most accurate baud rat possible.
     */
    config_baud_divisors(this_uart, baud_rate);

    /* set the line control register (bit length, stop bits, parity) */
    this_uart->hw_reg->LCR = line_config;
     994:	9d0b      	ldr	r5, [sp, #44]	; 0x2c

    /* Instance setup */
    this_uart->baudrate = baud_rate;
    this_uart->lineconfig = line_config;
    this_uart->tx_buff_size = TX_COMPLETE;
     996:	2000      	movs	r0, #0
     * where possible to provide the most accurate baud rat possible.
     */
    config_baud_divisors(this_uart, baud_rate);

    /* set the line control register (bit length, stop bits, parity) */
    this_uart->hw_reg->LCR = line_config;
     998:	730d      	strb	r5, [r1, #12]
    this_uart->pid_pei_handler  = NULL_HANDLER;
    this_uart->break_handler    = NULL_HANDLER;    
    this_uart->sync_handler     = NULL_HANDLER;   

    /* Initialize the sticky status */
    this_uart->status = 0u;
     99a:	7360      	strb	r0, [r4, #13]

    /* set the line control register (bit length, stop bits, parity) */
    this_uart->hw_reg->LCR = line_config;

    /* Instance setup */
    this_uart->baudrate = baud_rate;
     99c:	9e0d      	ldr	r6, [sp, #52]	; 0x34
    this_uart->lineconfig = line_config;
    this_uart->tx_buff_size = TX_COMPLETE;
     99e:	6160      	str	r0, [r4, #20]

    /* set the line control register (bit length, stop bits, parity) */
    this_uart->hw_reg->LCR = line_config;

    /* Instance setup */
    this_uart->baudrate = baud_rate;
     9a0:	60a6      	str	r6, [r4, #8]
    this_uart->lineconfig = line_config;
     9a2:	7325      	strb	r5, [r4, #12]
    this_uart->tx_buff_size = TX_COMPLETE;
    this_uart->tx_buffer = (const uint8_t *)0;
     9a4:	6120      	str	r0, [r4, #16]
    this_uart->tx_idx = 0u;
     9a6:	61a0      	str	r0, [r4, #24]

    /* Default handlers for MSS UART interrupts */
    this_uart->rx_handler       = NULL_HANDLER;
     9a8:	6220      	str	r0, [r4, #32]
    this_uart->tx_handler       = NULL_HANDLER;
     9aa:	6260      	str	r0, [r4, #36]	; 0x24
    this_uart->linests_handler  = NULL_HANDLER;
     9ac:	61e0      	str	r0, [r4, #28]
    this_uart->modemsts_handler = NULL_HANDLER;
     9ae:	62a0      	str	r0, [r4, #40]	; 0x28
    this_uart->rto_handler      = NULL_HANDLER;    
     9b0:	62e0      	str	r0, [r4, #44]	; 0x2c
    this_uart->nack_handler     = NULL_HANDLER;   
     9b2:	6320      	str	r0, [r4, #48]	; 0x30
    this_uart->pid_pei_handler  = NULL_HANDLER;
     9b4:	6360      	str	r0, [r4, #52]	; 0x34
    this_uart->break_handler    = NULL_HANDLER;    
     9b6:	63a0      	str	r0, [r4, #56]	; 0x38
    this_uart->sync_handler     = NULL_HANDLER;   
     9b8:	63e0      	str	r0, [r4, #60]	; 0x3c

    /* Initialize the sticky status */
    this_uart->status = 0u;
}
     9ba:	b00f      	add	sp, #60	; 0x3c
     9bc:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
        uint32_t baud_value_by_64;
        uint32_t baud_value_by_128;
        uint32_t fractional_baud_value;
        uint32_t pclk_freq;

        this_uart->baudrate = baudrate;
     9c0:	9f0d      	ldr	r7, [sp, #52]	; 0x34
     9c2:	60a7      	str	r7, [r4, #8]

        /* Force the value of the CMSIS global variables holding the various system
          * clock frequencies to be updated. */
        SystemCoreClockUpdate();
     9c4:	f000 f924 	bl	c10 <SystemCoreClockUpdate>
        {
            pclk_freq = g_FrequencyPCLK0;
        }
        else
        {
            pclk_freq = g_FrequencyPCLK1;
     9c8:	f240 0118 	movw	r1, #24
     9cc:	f2c0 0100 	movt	r1, #0
     9d0:	680a      	ldr	r2, [r1, #0]
        /*
         * Compute baud value based on requested baud rate and PCLK frequency.
         * The baud value is computed using the following equation:
         *      baud_value = PCLK_Frequency / (baud_rate * 16)
         */
        baud_value_by_128 = (8u * pclk_freq) / baudrate;
     9d2:	9e0d      	ldr	r6, [sp, #52]	; 0x34
     9d4:	00d7      	lsls	r7, r2, #3
     9d6:	fbb7 f2f6 	udiv	r2, r7, r6
        baud_value_by_64 = baud_value_by_128 / 2u;
        baud_value = baud_value_by_64 / 64u;
     9da:	09d3      	lsrs	r3, r2, #7
         * Compute baud value based on requested baud rate and PCLK frequency.
         * The baud value is computed using the following equation:
         *      baud_value = PCLK_Frequency / (baud_rate * 16)
         */
        baud_value_by_128 = (8u * pclk_freq) / baudrate;
        baud_value_by_64 = baud_value_by_128 / 2u;
     9dc:	0857      	lsrs	r7, r2, #1
        fractional_baud_value += (baud_value_by_128 - (baud_value * 128u)) - (fractional_baud_value * 2u);
        
        /* Assert if integer baud value fits in 16-bit. */
        ASSERT(baud_value <= UINT16_MAX);
    
        if(baud_value <= (uint32_t)UINT16_MAX)
     9de:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
     9e2:	bf28      	it	cs
     9e4:	6821      	ldrcs	r1, [r4, #0]
     9e6:	d2d5      	bcs.n	994 <global_init+0x1b8>
        {
            if(baud_value > 1u)
     9e8:	2b01      	cmp	r3, #1
            {
                /* 
                 * Use Frational baud rate divisors
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
     9ea:	6821      	ldr	r1, [r4, #0]
        /* Assert if integer baud value fits in 16-bit. */
        ASSERT(baud_value <= UINT16_MAX);
    
        if(baud_value <= (uint32_t)UINT16_MAX)
        {
            if(baud_value > 1u)
     9ec:	d950      	bls.n	a90 <global_init+0x2b4>
            {
                /* 
                 * Use Frational baud rate divisors
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
     9ee:	f101 000c 	add.w	r0, r1, #12
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     9f2:	f020 4c7f 	bic.w	ip, r0, #4278190080	; 0xff000000
     9f6:	f000 4670 	and.w	r6, r0, #4026531840	; 0xf0000000
     9fa:	f106 7000 	add.w	r0, r6, #33554432	; 0x2000000
     9fe:	f42c 0a70 	bic.w	sl, ip, #15728640	; 0xf00000
     a02:	ea4f 1e4a 	mov.w	lr, sl, lsl #5
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8);
                /* lsb of baud value */
                this_uart->hw_reg->DLR = (uint8_t)baud_value;
     a06:	460d      	mov	r5, r1
     a08:	fa5f f883 	uxtb.w	r8, r3
         *      baud_value = PCLK_Frequency / (baud_rate * 16)
         */
        baud_value_by_128 = (8u * pclk_freq) / baudrate;
        baud_value_by_64 = baud_value_by_128 / 2u;
        baud_value = baud_value_by_64 / 64u;
        fractional_baud_value = baud_value_by_64 - (baud_value * 64u);
     a0c:	eba7 1783 	sub.w	r7, r7, r3, lsl #6
     a10:	301c      	adds	r0, #28
     a12:	2601      	movs	r6, #1
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8);
     a14:	f3c2 3ac7 	ubfx	sl, r2, #15, #8
     a18:	f840 600e 	str.w	r6, [r0, lr]
         */
        baud_value_by_128 = (8u * pclk_freq) / baudrate;
        baud_value_by_64 = baud_value_by_128 / 2u;
        baud_value = baud_value_by_64 / 64u;
        fractional_baud_value = baud_value_by_64 - (baud_value * 64u);
        fractional_baud_value += (baud_value_by_128 - (baud_value * 128u)) - (fractional_baud_value * 2u);
     a1c:	eba7 13c3 	sub.w	r3, r7, r3, lsl #7
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8);
     a20:	f881 a004 	strb.w	sl, [r1, #4]
                /* lsb of baud value */
                this_uart->hw_reg->DLR = (uint8_t)baud_value;
     a24:	f805 8b30 	strb.w	r8, [r5], #48
         */
        baud_value_by_128 = (8u * pclk_freq) / baudrate;
        baud_value_by_64 = baud_value_by_128 / 2u;
        baud_value = baud_value_by_64 / 64u;
        fractional_baud_value = baud_value_by_64 - (baud_value * 64u);
        fractional_baud_value += (baud_value_by_128 - (baud_value * 128u)) - (fractional_baud_value * 2u);
     a28:	189a      	adds	r2, r3, r2
     a2a:	f025 437f 	bic.w	r3, r5, #4278190080	; 0xff000000
     a2e:	f005 4570 	and.w	r5, r5, #4026531840	; 0xf0000000
     a32:	f423 0870 	bic.w	r8, r3, #15728640	; 0xf00000
                /* Enable Fractional baud rate */
                set_bit_reg8(&this_uart->hw_reg->MM0,EFBR);
        
                /* Load the fractional baud rate register */
                ASSERT(fractional_baud_value <= (uint32_t)UINT8_MAX);
                this_uart->hw_reg->DFR = (uint8_t)fractional_baud_value;
     a36:	eba2 0747 	sub.w	r7, r2, r7, lsl #1
     a3a:	f105 7500 	add.w	r5, r5, #33554432	; 0x2000000
     a3e:	351c      	adds	r5, #28
     a40:	ea4f 1848 	mov.w	r8, r8, lsl #5
     a44:	b2ff      	uxtb	r7, r7
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     a46:	2300      	movs	r3, #0
     a48:	f840 300e 	str.w	r3, [r0, lr]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     a4c:	f845 6008 	str.w	r6, [r5, r8]
     a50:	f881 703c 	strb.w	r7, [r1, #60]	; 0x3c
     a54:	e79e      	b.n	994 <global_init+0x1b8>
    if(this_uart == &g_mss_uart0)
    {
        this_uart->hw_reg = UART0;
        this_uart->irqn = UART0_IRQn;
        /* reset UART0 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART0_SOFTRESET_MASK;
     a56:	f040 0780 	orr.w	r7, r0, #128	; 0x80
     a5a:	f2ce 0100 	movt	r1, #57344	; 0xe000
     a5e:	f44f 6680 	mov.w	r6, #1024	; 0x400
     a62:	6497      	str	r7, [r2, #72]	; 0x48
     a64:	f8c1 6180 	str.w	r6, [r1, #384]	; 0x180
        /* Clear any previously pended UART0 interrupt */
        NVIC_ClearPendingIRQ(UART0_IRQn);
        /* Take UART0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
     a68:	6c95      	ldr	r5, [r2, #72]	; 0x48
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
    {
        this_uart->hw_reg = UART0;
     a6a:	f04f 4180 	mov.w	r1, #1073741824	; 0x40000000
        /* reset UART0 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART0_SOFTRESET_MASK;
        /* Clear any previously pended UART0 interrupt */
        NVIC_ClearPendingIRQ(UART0_IRQn);
        /* Take UART0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
     a6e:	f025 0080 	bic.w	r0, r5, #128	; 0x80
     a72:	6490      	str	r0, [r2, #72]	; 0x48
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
    {
        this_uart->hw_reg = UART0;
        this_uart->irqn = UART0_IRQn;
     a74:	220a      	movs	r2, #10
     a76:	7122      	strb	r2, [r4, #4]
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
    {
        this_uart->hw_reg = UART0;
     a78:	6021      	str	r1, [r4, #0]
     a7a:	e6d7      	b.n	82c <global_init+0x50>
        uint32_t baud_value_by_64;
        uint32_t baud_value_by_128;
        uint32_t fractional_baud_value;
        uint32_t pclk_freq;

        this_uart->baudrate = baudrate;
     a7c:	9a0d      	ldr	r2, [sp, #52]	; 0x34
     a7e:	60a2      	str	r2, [r4, #8]

        /* Force the value of the CMSIS global variables holding the various system
          * clock frequencies to be updated. */
        SystemCoreClockUpdate();
     a80:	f000 f8c6 	bl	c10 <SystemCoreClockUpdate>
        if(this_uart == &g_mss_uart0)
        {
            pclk_freq = g_FrequencyPCLK0;
     a84:	f240 0114 	movw	r1, #20
     a88:	f2c0 0100 	movt	r1, #0
     a8c:	680a      	ldr	r2, [r1, #0]
     a8e:	e7a0      	b.n	9d2 <global_init+0x1f6>
            {
                /*
                 * Do NOT use Frational baud rate divisors.
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
     a90:	f101 0c0c 	add.w	ip, r1, #12
     a94:	f02c 4e7f 	bic.w	lr, ip, #4278190080	; 0xff000000
     a98:	f00c 4270 	and.w	r2, ip, #4026531840	; 0xf0000000
     a9c:	f42e 0570 	bic.w	r5, lr, #15728640	; 0xf00000
     aa0:	f102 7200 	add.w	r2, r2, #33554432	; 0x2000000
     aa4:	ea4f 1e45 	mov.w	lr, r5, lsl #5
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8u);
                /* lsb of baud value */
                this_uart->hw_reg->DLR = (uint8_t)baud_value;
     aa8:	4608      	mov	r0, r1
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8u);
     aaa:	2500      	movs	r5, #0
                /* lsb of baud value */
                this_uart->hw_reg->DLR = (uint8_t)baud_value;
     aac:	b2db      	uxtb	r3, r3
     aae:	321c      	adds	r2, #28
     ab0:	2601      	movs	r6, #1
     ab2:	f842 600e 	str.w	r6, [r2, lr]
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8u);
     ab6:	710d      	strb	r5, [r1, #4]
                /* lsb of baud value */
                this_uart->hw_reg->DLR = (uint8_t)baud_value;
     ab8:	f800 3b30 	strb.w	r3, [r0], #48
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     abc:	f020 4c7f 	bic.w	ip, r0, #4278190080	; 0xff000000
     ac0:	f000 4070 	and.w	r0, r0, #4026531840	; 0xf0000000
     ac4:	f100 7600 	add.w	r6, r0, #33554432	; 0x2000000
     ac8:	f42c 0370 	bic.w	r3, ip, #15728640	; 0xf00000
     acc:	361c      	adds	r6, #28
     ace:	015b      	lsls	r3, r3, #5
     ad0:	f842 500e 	str.w	r5, [r2, lr]
     ad4:	50f5      	str	r5, [r6, r3]
     ad6:	e75d      	b.n	994 <global_init+0x1b8>

00000ad8 <MSS_UART_init>:
(
    mss_uart_instance_t* this_uart, 
    uint32_t baud_rate,
    uint8_t line_config
)
{
     ad8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
     ada:	4604      	mov	r4, r0
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    /* Perform generic initialization */
    global_init(this_uart, baud_rate, line_config);
     adc:	f7ff fe7e 	bl	7dc <global_init>

    /* Disable LIN mode */
    clear_bit_reg8(&this_uart->hw_reg->MM0, ELIN);
     ae0:	6822      	ldr	r2, [r4, #0]
     ae2:	f64f 73ff 	movw	r3, #65535	; 0xffff

    /* Disable IrDA mode */
    clear_bit_reg8(&this_uart->hw_reg->MM1, EIRD);
     ae6:	f102 0034 	add.w	r0, r2, #52	; 0x34

    /* Perform generic initialization */
    global_init(this_uart, baud_rate, line_config);

    /* Disable LIN mode */
    clear_bit_reg8(&this_uart->hw_reg->MM0, ELIN);
     aea:	f102 0530 	add.w	r5, r2, #48	; 0x30
     aee:	f2c0 030f 	movt	r3, #15
     af2:	f005 4770 	and.w	r7, r5, #4026531840	; 0xf0000000

    /* Disable IrDA mode */
    clear_bit_reg8(&this_uart->hw_reg->MM1, EIRD);

    /* Disable SmartCard Mode */
    clear_bit_reg8(&this_uart->hw_reg->MM2, EERR);
     af6:	3238      	adds	r2, #56	; 0x38
     af8:	f000 4170 	and.w	r1, r0, #4026531840	; 0xf0000000

    /* set default tx handler for automated TX using interrupt in USART mode */
    this_uart->tx_handler = default_tx_handler;
     afc:	ea02 0603 	and.w	r6, r2, r3
     b00:	f107 7c00 	add.w	ip, r7, #33554432	; 0x2000000
     b04:	401d      	ands	r5, r3
     b06:	ea00 0703 	and.w	r7, r0, r3
     b0a:	f002 4270 	and.w	r2, r2, #4026531840	; 0xf0000000
     b0e:	f101 7100 	add.w	r1, r1, #33554432	; 0x2000000
     b12:	f240 701d 	movw	r0, #1821	; 0x71d
     b16:	017b      	lsls	r3, r7, #5
     b18:	f10c 0c0c 	add.w	ip, ip, #12
     b1c:	f102 7700 	add.w	r7, r2, #33554432	; 0x2000000
     b20:	016d      	lsls	r5, r5, #5
     b22:	2200      	movs	r2, #0
     b24:	3108      	adds	r1, #8
     b26:	0176      	lsls	r6, r6, #5
     b28:	f2c0 0000 	movt	r0, #0
     b2c:	f84c 2005 	str.w	r2, [ip, r5]
     b30:	6260      	str	r0, [r4, #36]	; 0x24
     b32:	50ca      	str	r2, [r1, r3]
     b34:	51ba      	str	r2, [r7, r6]
}
     b36:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

00000b38 <MSS_GPIO_init>:
void MSS_GPIO_init( void )
{
    uint32_t inc;
    
    /* reset MSS GPIO hardware */
    SYSREG->SOFT_RST_CR |= SYSREG_GPIO_SOFTRESET_MASK;
     b38:	f248 0200 	movw	r2, #32768	; 0x8000
     b3c:	f2c4 0203 	movt	r2, #16387	; 0x4003
/*-------------------------------------------------------------------------*//**
 * MSS_GPIO_init
 * See "mss_gpio.h" for details of how to use this function.
 */
void MSS_GPIO_init( void )
{
     b40:	e92d 05f0 	stmdb	sp!, {r4, r5, r6, r7, r8, sl}
    uint32_t inc;
    
    /* reset MSS GPIO hardware */
    SYSREG->SOFT_RST_CR |= SYSREG_GPIO_SOFTRESET_MASK;
     b44:	6c94      	ldr	r4, [r2, #72]	; 0x48
     b46:	f640 764c 	movw	r6, #3916	; 0xf4c
     b4a:	f444 1380 	orr.w	r3, r4, #1048576	; 0x100000
     b4e:	6493      	str	r3, [r2, #72]	; 0x48
    SYSREG->SOFT_RST_CR |= (SYSREG_GPIO_7_0_SOFTRESET_MASK |
     b50:	6c90      	ldr	r0, [r2, #72]	; 0x48

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
     b52:	f24e 1300 	movw	r3, #57600	; 0xe100
     b56:	f040 71f0 	orr.w	r1, r0, #31457280	; 0x1e00000
     b5a:	6491      	str	r1, [r2, #72]	; 0x48
     b5c:	f2c0 0600 	movt	r6, #0
     b60:	f2ce 0300 	movt	r3, #57344	; 0xe000
     b64:	2200      	movs	r2, #0
     b66:	2701      	movs	r7, #1
                            SYSREG_GPIO_15_8_SOFTRESET_MASK |
                            SYSREG_GPIO_23_16_SOFTRESET_MASK |
                            SYSREG_GPIO_31_24_SOFTRESET_MASK);
                            
    /* Clear any previously pended MSS GPIO interrupt */
    for(inc = 0U; inc < NB_OF_GPIO; ++inc)
     b68:	1c55      	adds	r5, r2, #1
    {
        NVIC_DisableIRQ(g_gpio_irqn_lut[inc]);
     b6a:	5cb4      	ldrb	r4, [r6, r2]
     b6c:	f816 a005 	ldrb.w	sl, [r6, r5]
     b70:	f004 001f 	and.w	r0, r4, #31
     b74:	f00a 011f 	and.w	r1, sl, #31
     b78:	fa17 f000 	lsls.w	r0, r7, r0
     b7c:	fa17 f101 	lsls.w	r1, r7, r1
     b80:	fa4f f88a 	sxtb.w	r8, sl
     b84:	b262      	sxtb	r2, r4
     b86:	0954      	lsrs	r4, r2, #5
     b88:	ea4f 1c58 	mov.w	ip, r8, lsr #5
                            SYSREG_GPIO_15_8_SOFTRESET_MASK |
                            SYSREG_GPIO_23_16_SOFTRESET_MASK |
                            SYSREG_GPIO_31_24_SOFTRESET_MASK);
                            
    /* Clear any previously pended MSS GPIO interrupt */
    for(inc = 0U; inc < NB_OF_GPIO; ++inc)
     b8c:	1c6a      	adds	r2, r5, #1

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
     b8e:	f104 0a60 	add.w	sl, r4, #96	; 0x60
     b92:	f10c 0860 	add.w	r8, ip, #96	; 0x60

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
     b96:	3420      	adds	r4, #32
     b98:	f10c 0c20 	add.w	ip, ip, #32
     b9c:	2a20      	cmp	r2, #32
     b9e:	f843 0024 	str.w	r0, [r3, r4, lsl #2]

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
     ba2:	f843 002a 	str.w	r0, [r3, sl, lsl #2]

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
     ba6:	f843 102c 	str.w	r1, [r3, ip, lsl #2]

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
     baa:	f843 1028 	str.w	r1, [r3, r8, lsl #2]
     bae:	d1db      	bne.n	b68 <MSS_GPIO_init+0x30>
    {
        NVIC_DisableIRQ(g_gpio_irqn_lut[inc]);
        NVIC_ClearPendingIRQ(g_gpio_irqn_lut[inc]);
    }
    /* Take MSS GPIO hardware out of reset. */
    SYSREG->SOFT_RST_CR &= ~(SYSREG_GPIO_7_0_SOFTRESET_MASK |
     bb0:	f248 0300 	movw	r3, #32768	; 0x8000
     bb4:	f2c4 0303 	movt	r3, #16387	; 0x4003
     bb8:	6c9a      	ldr	r2, [r3, #72]	; 0x48
     bba:	f022 70f0 	bic.w	r0, r2, #31457280	; 0x1e00000
     bbe:	6498      	str	r0, [r3, #72]	; 0x48
                             SYSREG_GPIO_15_8_SOFTRESET_MASK |
                             SYSREG_GPIO_23_16_SOFTRESET_MASK |
                             SYSREG_GPIO_31_24_SOFTRESET_MASK);
    SYSREG->SOFT_RST_CR &= ~SYSREG_GPIO_SOFTRESET_MASK;
     bc0:	6c99      	ldr	r1, [r3, #72]	; 0x48
     bc2:	f421 1280 	bic.w	r2, r1, #1048576	; 0x100000
     bc6:	649a      	str	r2, [r3, #72]	; 0x48
}
     bc8:	e8bd 05f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, sl}
     bcc:	4770      	bx	lr
     bce:	bf00      	nop

00000bd0 <MSS_GPIO_config>:
{
    uint32_t gpio_idx = (uint32_t)port_id;
    
    ASSERT(gpio_idx < NB_OF_GPIO);

    if(gpio_idx < NB_OF_GPIO)
     bd0:	281f      	cmp	r0, #31
    {
        *(g_config_reg_lut[gpio_idx]) = config;
     bd2:	bf9f      	itttt	ls
     bd4:	f640 736c 	movwls	r3, #3948	; 0xf6c
     bd8:	f2c0 0300 	movtls	r3, #0
     bdc:	f853 3020 	ldrls.w	r3, [r3, r0, lsl #2]
     be0:	6019      	strls	r1, [r3, #0]
     be2:	4770      	bx	lr

00000be4 <MSS_GPIO_set_output>:
    uint32_t gpio_setting;
    uint32_t gpio_idx = (uint32_t)port_id;
    
    ASSERT(gpio_idx < NB_OF_GPIO);
    
    if(gpio_idx < NB_OF_GPIO)
     be4:	281f      	cmp	r0, #31
     be6:	d812      	bhi.n	c0e <MSS_GPIO_set_output+0x2a>
    {
        gpio_setting = GPIO->GPIO_OUT;
        gpio_setting &= ~((uint32_t)0x01u << gpio_idx);
     be8:	2201      	movs	r2, #1
     bea:	fa02 fc00 	lsl.w	ip, r2, r0
        gpio_setting |= ((uint32_t)value & 0x01u) << gpio_idx;
     bee:	f001 0301 	and.w	r3, r1, #1
     bf2:	fa13 f000 	lsls.w	r0, r3, r0
    
    ASSERT(gpio_idx < NB_OF_GPIO);
    
    if(gpio_idx < NB_OF_GPIO)
    {
        gpio_setting = GPIO->GPIO_OUT;
     bf6:	f243 0300 	movw	r3, #12288	; 0x3000
     bfa:	f2c4 0301 	movt	r3, #16385	; 0x4001
     bfe:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
        gpio_setting &= ~((uint32_t)0x01u << gpio_idx);
     c02:	ea22 010c 	bic.w	r1, r2, ip
        gpio_setting |= ((uint32_t)value & 0x01u) << gpio_idx;
     c06:	ea41 0000 	orr.w	r0, r1, r0
        GPIO->GPIO_OUT = gpio_setting;
     c0a:	f8c3 0088 	str.w	r0, [r3, #136]	; 0x88
     c0e:	4770      	bx	lr

00000c10 <SystemCoreClockUpdate>:
#define FREQ_1MHZ    1000000u
#define FREQ_25MHZ   25000000u
#define FREQ_50MHZ   50000000u

void SystemCoreClockUpdate(void)
{
     c10:	e92d 01f0 	stmdb	sp!, {r4, r5, r6, r7, r8}
    uint32_t controller_pll_init;
    uint32_t clk_src;

    controller_pll_init = SYSREG->MSSDDR_FACC1_CR & CONTROLLER_PLL_INIT_MASK;
     c14:	f248 0300 	movw	r3, #32768	; 0x8000
     c18:	f2c4 0303 	movt	r3, #16387	; 0x4003
     c1c:	f8d3 2098 	ldr.w	r2, [r3, #152]	; 0x98
#define FREQ_1MHZ    1000000u
#define FREQ_25MHZ   25000000u
#define FREQ_50MHZ   50000000u

void SystemCoreClockUpdate(void)
{
     c20:	b083      	sub	sp, #12
    uint32_t controller_pll_init;
    uint32_t clk_src;

    controller_pll_init = SYSREG->MSSDDR_FACC1_CR & CONTROLLER_PLL_INIT_MASK;
    
    if(0u == controller_pll_init)
     c22:	f012 6f80 	tst.w	r2, #67108864	; 0x4000000
     c26:	d118      	bne.n	c5a <SystemCoreClockUpdate+0x4a>
    {
        /* Normal operations. */
        uint32_t global_mux_sel;
        
        global_mux_sel = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK;
     c28:	f8d3 0098 	ldr.w	r0, [r3, #152]	; 0x98
        if(0u == global_mux_sel)
     c2c:	f410 5f80 	tst.w	r0, #4096	; 0x1000
     c30:	d04d      	beq.n	cce <SystemCoreClockUpdate+0xbe>
                                                   RCOSC_25_50MHZ_CLK_SRC,
                                                   CLK_XTAL_CLK_SRC,
                                                   RCOSC_1_MHZ_CLK_SRC,
                                                   RCOSC_1_MHZ_CLK_SRC,
                                                   CCC2ASCI_CLK_SRC,
                                                   CCC2ASCI_CLK_SRC };
     c32:	f640 71ec 	movw	r1, #4076	; 0xfec
     c36:	f2c0 0100 	movt	r1, #0
     c3a:	46ec      	mov	ip, sp
     c3c:	c903      	ldmia	r1!, {r0, r1}
     c3e:	e88c 0003 	stmia.w	ip, {r0, r1}
            
            uint32_t standby_sel;
            uint8_t clock_source;
            
            standby_sel = (SYSREG->MSSDDR_FACC2_CR >> FACC_STANDBY_SHIFT) & FACC_STANDBY_SEL_MASK;
     c42:	f8d3 209c 	ldr.w	r2, [r3, #156]	; 0x9c
            clock_source = standby_clock_lut[standby_sel];
            switch(clock_source)
     c46:	af02      	add	r7, sp, #8
     c48:	f3c2 1682 	ubfx	r6, r2, #6, #3
     c4c:	19bd      	adds	r5, r7, r6
     c4e:	f815 4c08 	ldrb.w	r4, [r5, #-8]
     c52:	2c01      	cmp	r4, #1
     c54:	f000 8081 	beq.w	d5a <SystemCoreClockUpdate+0x14a>
     c58:	d26a      	bcs.n	d30 <SystemCoreClockUpdate+0x120>
static uint32_t get_rcosc_25_50mhz_frequency(void)
{
    uint32_t rcosc_div2;
    uint32_t rcosc_frequency;
    
    rcosc_div2 = SYSREG->MSSDDR_PLL_STATUS & RCOSC_DIV2_MASK;
     c5a:	f8d3 0150 	ldr.w	r0, [r3, #336]	; 0x150
    if(0u == rcosc_div2)
     c5e:	f647 0840 	movw	r8, #30784	; 0x7840
     c62:	f24f 0380 	movw	r3, #61568	; 0xf080
     c66:	f010 0f04 	tst.w	r0, #4
     c6a:	f2c0 187d 	movt	r8, #381	; 0x17d
     c6e:	f2c0 23fa 	movt	r3, #762	; 0x2fa
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     c72:	f240 051c 	movw	r5, #28
    g_FrequencyPCLK0 = standby_clk;
     c76:	f240 0414 	movw	r4, #20
    g_FrequencyPCLK1 = standby_clk;
     c7a:	f240 0018 	movw	r0, #24
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     c7e:	f240 0708 	movw	r7, #8
     c82:	f646 6c70 	movw	ip, #28272	; 0x6e70
    g_FrequencyFIC0 = standby_clk;
     c86:	f240 010c 	movw	r1, #12
    g_FrequencyFIC1 = standby_clk;
     c8a:	f240 0210 	movw	r2, #16
    g_FrequencyFIC64 = standby_clk;
     c8e:	f240 0604 	movw	r6, #4
{
    uint32_t rcosc_div2;
    uint32_t rcosc_frequency;
    
    rcosc_div2 = SYSREG->MSSDDR_PLL_STATUS & RCOSC_DIV2_MASK;
    if(0u == rcosc_div2)
     c92:	bf08      	it	eq
     c94:	4643      	moveq	r3, r8
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     c96:	f2c0 0500 	movt	r5, #0
    g_FrequencyPCLK0 = standby_clk;
     c9a:	f2c0 0400 	movt	r4, #0
    g_FrequencyPCLK1 = standby_clk;
     c9e:	f2c0 0000 	movt	r0, #0
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     ca2:	f2c0 0700 	movt	r7, #0
     ca6:	f2c0 1ca7 	movt	ip, #423	; 0x1a7
    g_FrequencyFIC0 = standby_clk;
     caa:	f2c0 0100 	movt	r1, #0
    g_FrequencyFIC1 = standby_clk;
     cae:	f2c0 0200 	movt	r2, #0
    g_FrequencyFIC64 = standby_clk;
     cb2:	f2c0 0600 	movt	r6, #0
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
    g_FrequencyPCLK0 = standby_clk;
    g_FrequencyPCLK1 = standby_clk;
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     cb6:	f8c7 c000 	str.w	ip, [r7]
    g_FrequencyFIC0 = standby_clk;
    g_FrequencyFIC1 = standby_clk;
    g_FrequencyFIC64 = standby_clk;
     cba:	6033      	str	r3, [r6, #0]
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     cbc:	602b      	str	r3, [r5, #0]
    g_FrequencyPCLK0 = standby_clk;
     cbe:	6023      	str	r3, [r4, #0]
    g_FrequencyPCLK1 = standby_clk;
     cc0:	6003      	str	r3, [r0, #0]
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
    g_FrequencyFIC0 = standby_clk;
     cc2:	600b      	str	r3, [r1, #0]
    g_FrequencyFIC1 = standby_clk;
     cc4:	6013      	str	r3, [r2, #0]
    {
        /* PLL initialization mode. Running from 25/50MHZ RC oscillator. */
        clk_src = get_rcosc_25_50mhz_frequency();
        set_clock_frequency_globals(clk_src);
    }
}
     cc6:	b003      	add	sp, #12
     cc8:	e8bd 01f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8}
     ccc:	4770      	bx	lr
        
        global_mux_sel = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK;
        if(0u == global_mux_sel)
        {
            /* MSS clocked from MSS PLL. Use Libero flow defines. */
            SystemCoreClock = MSS_SYS_M3_CLK_FREQ;
     cce:	f240 041c 	movw	r4, #28
     cd2:	f64b 13c0 	movw	r3, #47552	; 0xb9c0
            g_FrequencyPCLK0 = MSS_SYS_APB_0_CLK_FREQ;
     cd6:	f240 0014 	movw	r0, #20
            g_FrequencyPCLK1 = MSS_SYS_APB_1_CLK_FREQ;
     cda:	f240 0118 	movw	r1, #24
            g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     cde:	f240 0c08 	movw	ip, #8
     ce2:	f646 6870 	movw	r8, #28272	; 0x6e70
            g_FrequencyFIC0 = MSS_SYS_FIC_0_CLK_FREQ;
     ce6:	f240 020c 	movw	r2, #12
            g_FrequencyFIC1 = MSS_SYS_FIC_1_CLK_FREQ;
     cea:	f240 0710 	movw	r7, #16
            g_FrequencyFIC64 = MSS_SYS_FIC64_CLK_FREQ;
     cee:	f240 0504 	movw	r5, #4
     cf2:	f642 5640 	movw	r6, #11584	; 0x2d40
        
        global_mux_sel = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK;
        if(0u == global_mux_sel)
        {
            /* MSS clocked from MSS PLL. Use Libero flow defines. */
            SystemCoreClock = MSS_SYS_M3_CLK_FREQ;
     cf6:	f2c0 639d 	movt	r3, #1693	; 0x69d
     cfa:	f2c0 0400 	movt	r4, #0
            g_FrequencyPCLK0 = MSS_SYS_APB_0_CLK_FREQ;
     cfe:	f2c0 0000 	movt	r0, #0
            g_FrequencyPCLK1 = MSS_SYS_APB_1_CLK_FREQ;
     d02:	f2c0 0100 	movt	r1, #0
            g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     d06:	f2c0 0c00 	movt	ip, #0
     d0a:	f2c0 18a7 	movt	r8, #423	; 0x1a7
            g_FrequencyFIC0 = MSS_SYS_FIC_0_CLK_FREQ;
     d0e:	f2c0 0200 	movt	r2, #0
            g_FrequencyFIC1 = MSS_SYS_FIC_1_CLK_FREQ;
     d12:	f2c0 0700 	movt	r7, #0
            g_FrequencyFIC64 = MSS_SYS_FIC64_CLK_FREQ;
     d16:	f2c0 0500 	movt	r5, #0
     d1a:	f2c1 36d9 	movt	r6, #5081	; 0x13d9
        {
            /* MSS clocked from MSS PLL. Use Libero flow defines. */
            SystemCoreClock = MSS_SYS_M3_CLK_FREQ;
            g_FrequencyPCLK0 = MSS_SYS_APB_0_CLK_FREQ;
            g_FrequencyPCLK1 = MSS_SYS_APB_1_CLK_FREQ;
            g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     d1e:	f8cc 8000 	str.w	r8, [ip]
            g_FrequencyFIC0 = MSS_SYS_FIC_0_CLK_FREQ;
            g_FrequencyFIC1 = MSS_SYS_FIC_1_CLK_FREQ;
     d22:	603b      	str	r3, [r7, #0]
            g_FrequencyFIC64 = MSS_SYS_FIC64_CLK_FREQ;
     d24:	602e      	str	r6, [r5, #0]
        
        global_mux_sel = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK;
        if(0u == global_mux_sel)
        {
            /* MSS clocked from MSS PLL. Use Libero flow defines. */
            SystemCoreClock = MSS_SYS_M3_CLK_FREQ;
     d26:	6023      	str	r3, [r4, #0]
            g_FrequencyPCLK0 = MSS_SYS_APB_0_CLK_FREQ;
     d28:	6003      	str	r3, [r0, #0]
            g_FrequencyPCLK1 = MSS_SYS_APB_1_CLK_FREQ;
     d2a:	600b      	str	r3, [r1, #0]
            g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
            g_FrequencyFIC0 = MSS_SYS_FIC_0_CLK_FREQ;
     d2c:	6013      	str	r3, [r2, #0]
     d2e:	e7ca      	b.n	cc6 <SystemCoreClockUpdate+0xb6>
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     d30:	f244 2340 	movw	r3, #16960	; 0x4240
     d34:	f240 051c 	movw	r5, #28
    g_FrequencyPCLK0 = standby_clk;
     d38:	f240 0414 	movw	r4, #20
    g_FrequencyPCLK1 = standby_clk;
     d3c:	f240 0018 	movw	r0, #24
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     d40:	f240 0708 	movw	r7, #8
     d44:	f646 6c70 	movw	ip, #28272	; 0x6e70
    g_FrequencyFIC0 = standby_clk;
     d48:	f240 010c 	movw	r1, #12
    g_FrequencyFIC1 = standby_clk;
     d4c:	f240 0210 	movw	r2, #16
    g_FrequencyFIC64 = standby_clk;
     d50:	f240 0604 	movw	r6, #4
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     d54:	f2c0 030f 	movt	r3, #15
     d58:	e79d      	b.n	c96 <SystemCoreClockUpdate+0x86>
    g_FrequencyPCLK0 = standby_clk;
     d5a:	f240 051c 	movw	r5, #28
     d5e:	f240 0414 	movw	r4, #20
    g_FrequencyPCLK1 = standby_clk;
     d62:	f240 0018 	movw	r0, #24
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     d66:	f240 0708 	movw	r7, #8
     d6a:	f646 6c70 	movw	ip, #28272	; 0x6e70
    g_FrequencyFIC0 = standby_clk;
     d6e:	f240 010c 	movw	r1, #12
    g_FrequencyFIC1 = standby_clk;
     d72:	f240 0210 	movw	r2, #16
    g_FrequencyFIC64 = standby_clk;
     d76:	f240 0604 	movw	r6, #4
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     d7a:	f2c0 0500 	movt	r5, #0
    g_FrequencyPCLK0 = standby_clk;
     d7e:	f2c0 0400 	movt	r4, #0
    g_FrequencyPCLK1 = standby_clk;
     d82:	f2c0 0000 	movt	r0, #0
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     d86:	f2c0 0700 	movt	r7, #0
     d8a:	f2c0 1ca7 	movt	ip, #423	; 0x1a7
    g_FrequencyFIC0 = standby_clk;
     d8e:	f2c0 0100 	movt	r1, #0
    g_FrequencyFIC1 = standby_clk;
     d92:	f2c0 0200 	movt	r2, #0
    g_FrequencyFIC64 = standby_clk;
     d96:	f2c0 0600 	movt	r6, #0
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     d9a:	f44f 4300 	mov.w	r3, #32768	; 0x8000
     d9e:	e78a      	b.n	cb6 <SystemCoreClockUpdate+0xa6>

00000da0 <SystemInit>:
static uint32_t get_silicon_revision(void)
{
    uint32_t silicon_revision;
    uint32_t device_version;
    
    device_version = SYSREG->DEVICE_VERSION;
     da0:	f248 0300 	movw	r3, #32768	; 0x8000
     da4:	f2c4 0303 	movt	r3, #16387	; 0x4003
     da8:	f8d3 114c 	ldr.w	r1, [r3, #332]	; 0x14c
    switch(device_version)
     dac:	f64f 0202 	movw	r2, #63490	; 0xf802
     db0:	4291      	cmp	r1, r2

/***************************************************************************//**
 * See system_m2sxxx.h for details.
 */
void SystemInit(void)
{
     db2:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
{
    uint32_t silicon_revision;
    uint32_t device_version;
    
    device_version = SYSREG->DEVICE_VERSION;
    switch(device_version)
     db6:	d10b      	bne.n	dd0 <SystemInit+0x30>
{
    /*--------------------------------------------------------------------------
     * Work around a couple of silicon issues:
     */
    /* DDR_CLK_EN <- 1 */
    SYSREG->MSSDDR_FACC1_CR |= (uint32_t)1 << DDR_CLK_EN_SHIFT;
     db8:	f8d3 0098 	ldr.w	r0, [r3, #152]	; 0x98
     dbc:	f440 7280 	orr.w	r2, r0, #256	; 0x100
     dc0:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98
    
    /* CONTROLLER_PLL_INIT <- 0 */
    SYSREG->MSSDDR_FACC1_CR = SYSREG->MSSDDR_FACC1_CR & ~CONTROLLER_PLL_INIT_MASK;
     dc4:	f8d3 1098 	ldr.w	r1, [r3, #152]	; 0x98
     dc8:	f021 6080 	bic.w	r0, r1, #67108864	; 0x4000000
     dcc:	f8c3 0098 	str.w	r0, [r3, #152]	; 0x98
    /*--------------------------------------------------------------------------
     * Set STKALIGN to ensure exception stacking starts on 8 bytes address
     * boundary. This ensures compliance with the "Procedure Call Standards for
     * the ARM Architecture" (AAPCS).
     */
    SCB->CCR |= SCB_CCR_STKALIGN_Msk;
     dd0:	f64e 5300 	movw	r3, #60672	; 0xed00
     dd4:	f2ce 0300 	movt	r3, #57344	; 0xe000
     dd8:	6958      	ldr	r0, [r3, #20]
    
    /*--------------------------------------------------------------------------
     * MDDR configuration
     */
#if MSS_SYS_MDDR_CONFIG_BY_CORTEX
    if(0u == SYSREG->DDR_CR)
     dda:	f248 0200 	movw	r2, #32768	; 0x8000
    /*--------------------------------------------------------------------------
     * Set STKALIGN to ensure exception stacking starts on 8 bytes address
     * boundary. This ensures compliance with the "Procedure Call Standards for
     * the ARM Architecture" (AAPCS).
     */
    SCB->CCR |= SCB_CCR_STKALIGN_Msk;
     dde:	f440 7100 	orr.w	r1, r0, #512	; 0x200
     de2:	6159      	str	r1, [r3, #20]
    
    /*--------------------------------------------------------------------------
     * MDDR configuration
     */
#if MSS_SYS_MDDR_CONFIG_BY_CORTEX
    if(0u == SYSREG->DDR_CR)
     de4:	f2c4 0203 	movt	r2, #16387	; 0x4003
     de8:	6893      	ldr	r3, [r2, #8]
     dea:	2b00      	cmp	r3, #0
     dec:	d164      	bne.n	eb8 <SystemInit+0x118>
         * to address 0x00000000. If MDDR is remapped to 0x00000000 then we are
         * probably executing this code from MDDR in a debugging session and
         * attempting to reconfigure the MDDR memory controller will cause the
         * Cortex-M3 to crash.
         */
        config_ddr_subsys(&g_m2s_mddr_subsys_config, &g_m2s_mddr_addr->core);
     dee:	f241 1400 	movw	r4, #4352	; 0x1100
     df2:	f2c0 0400 	movt	r4, #0
     df6:	6826      	ldr	r6, [r4, #0]
     df8:	f640 74f4 	movw	r4, #4084	; 0xff4
     dfc:	f2c0 0400 	movt	r4, #0
    
    /*--------------------------------------------------------------------------
     * Configure DDR controller part of the MDDR subsystem.
     */
    p_cfg = &p_ddr_subsys_cfg->ddrc.DYN_SOFT_RESET_CR;
    p_regs = &p_ddr_subsys_regs->ddrc.DYN_SOFT_RESET_CR;
     e00:	4632      	mov	r2, r6
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
    {
        p_regs[inc] = p_cfg[inc];
     e02:	1c98      	adds	r0, r3, #2
     e04:	1c81      	adds	r1, r0, #2
     e06:	5b1f      	ldrh	r7, [r3, r4]
     e08:	5b00      	ldrh	r0, [r0, r4]
     e0a:	5b0d      	ldrh	r5, [r1, r4]
     e0c:	3306      	adds	r3, #6
     e0e:	4611      	mov	r1, r2
     e10:	f841 7b04 	str.w	r7, [r1], #4
     e14:	6050      	str	r0, [r2, #4]
     e16:	320c      	adds	r2, #12
    uint32_t nb_16bit_words
)
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
     e18:	2b72      	cmp	r3, #114	; 0x72
    {
        p_regs[inc] = p_cfg[inc];
     e1a:	604d      	str	r5, [r1, #4]
    uint32_t nb_16bit_words
)
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
     e1c:	d1f1      	bne.n	e02 <SystemInit+0x62>
    
    /*--------------------------------------------------------------------------
     * Configure DDR PHY.
     */
    p_cfg = &p_ddr_subsys_cfg->phy.LOOPBACK_TEST_CR;
    p_regs = &p_ddr_subsys_regs->phy.LOOPBACK_TEST_CR;
     e1e:	f640 72f4 	movw	r2, #4084	; 0xff4
     e22:	f2c0 0200 	movt	r2, #0
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
    {
        p_regs[inc] = p_cfg[inc];
     e26:	f8b2 5072 	ldrh.w	r5, [r2, #114]	; 0x72
    
    /*--------------------------------------------------------------------------
     * Configure DDR PHY.
     */
    p_cfg = &p_ddr_subsys_cfg->phy.LOOPBACK_TEST_CR;
    p_regs = &p_ddr_subsys_regs->phy.LOOPBACK_TEST_CR;
     e2a:	f506 7307 	add.w	r3, r6, #540	; 0x21c
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
    {
        p_regs[inc] = p_cfg[inc];
     e2e:	601d      	str	r5, [r3, #0]
static void set_clock_frequency_globals(uint32_t fclk);

/***************************************************************************//**
 * See system_m2sxxx.h for details.
 */
void SystemInit(void)
     e30:	f102 0c82 	add.w	ip, r2, #130	; 0x82
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
    {
        p_regs[inc] = p_cfg[inc];
     e34:	1c93      	adds	r3, r2, #2
     e36:	f506 7108 	add.w	r1, r6, #544	; 0x220
     e3a:	1c98      	adds	r0, r3, #2
     e3c:	f8b3 5072 	ldrh.w	r5, [r3, #114]	; 0x72
     e40:	460f      	mov	r7, r1
     e42:	f8b0 2072 	ldrh.w	r2, [r0, #114]	; 0x72
     e46:	f847 5b04 	str.w	r5, [r7], #4
     e4a:	1c83      	adds	r3, r0, #2
     e4c:	604a      	str	r2, [r1, #4]
     e4e:	1d39      	adds	r1, r7, #4
    uint32_t nb_16bit_words
)
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
     e50:	4563      	cmp	r3, ip
     e52:	d1f2      	bne.n	e3a <SystemInit+0x9a>
    p_ddr_subsys_regs->fic.HPD_SW_RW_EN_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_EN_CR;
    p_ddr_subsys_regs->fic.HPD_SW_RW_INVAL_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_INVAL_CR;
    p_ddr_subsys_regs->fic.SW_WR_ERCLR_CR = p_ddr_subsys_cfg->fic.SW_WR_ERCLR_CR;
    p_ddr_subsys_regs->fic.ERR_INT_ENABLE_CR = p_ddr_subsys_cfg->fic.ERR_INT_ENABLE_CR;
    p_ddr_subsys_regs->fic.NUM_AHB_MASTERS_CR = p_ddr_subsys_cfg->fic.NUM_AHB_MASTERS_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[0] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_1_CR;
     e54:	f8b4 1104 	ldrh.w	r1, [r4, #260]	; 0x104
    copy_cfg16_to_regs(p_regs, p_cfg, NB_OF_DDR_PHY_REGS_TO_CONFIG);
    
    /*--------------------------------------------------------------------------
     * Configure DDR FIC.
     */
    p_ddr_subsys_regs->fic.NB_ADDR_CR = p_ddr_subsys_cfg->fic.NB_ADDR_CR;
     e58:	f8b4 90f4 	ldrh.w	r9, [r4, #244]	; 0xf4
    p_ddr_subsys_regs->fic.NBRWB_SIZE_CR = p_ddr_subsys_cfg->fic.NBRWB_SIZE_CR;
     e5c:	f8b4 a0f6 	ldrh.w	sl, [r4, #246]	; 0xf6
    p_ddr_subsys_regs->fic.WB_TIMEOUT_CR = p_ddr_subsys_cfg->fic.WB_TIMEOUT_CR;
     e60:	f8b4 80f8 	ldrh.w	r8, [r4, #248]	; 0xf8
    p_ddr_subsys_regs->fic.HPD_SW_RW_EN_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_EN_CR;
     e64:	f8b4 e0fa 	ldrh.w	lr, [r4, #250]	; 0xfa
    p_ddr_subsys_regs->fic.HPD_SW_RW_INVAL_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_INVAL_CR;
     e68:	f8b4 c0fc 	ldrh.w	ip, [r4, #252]	; 0xfc
    p_ddr_subsys_regs->fic.SW_WR_ERCLR_CR = p_ddr_subsys_cfg->fic.SW_WR_ERCLR_CR;
     e6c:	f8b4 70fe 	ldrh.w	r7, [r4, #254]	; 0xfe
    p_ddr_subsys_regs->fic.ERR_INT_ENABLE_CR = p_ddr_subsys_cfg->fic.ERR_INT_ENABLE_CR;
     e70:	f8b4 5100 	ldrh.w	r5, [r4, #256]	; 0x100
    p_ddr_subsys_regs->fic.NUM_AHB_MASTERS_CR = p_ddr_subsys_cfg->fic.NUM_AHB_MASTERS_CR;
     e74:	f8b4 0102 	ldrh.w	r0, [r4, #258]	; 0x102
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[0] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_1_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[1] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_2_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUT_EN_CR = p_ddr_subsys_cfg->fic.LOCK_TIMEOUT_EN_CR;
     e78:	f8b4 3108 	ldrh.w	r3, [r4, #264]	; 0x108
    p_ddr_subsys_regs->fic.HPD_SW_RW_INVAL_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_INVAL_CR;
    p_ddr_subsys_regs->fic.SW_WR_ERCLR_CR = p_ddr_subsys_cfg->fic.SW_WR_ERCLR_CR;
    p_ddr_subsys_regs->fic.ERR_INT_ENABLE_CR = p_ddr_subsys_cfg->fic.ERR_INT_ENABLE_CR;
    p_ddr_subsys_regs->fic.NUM_AHB_MASTERS_CR = p_ddr_subsys_cfg->fic.NUM_AHB_MASTERS_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[0] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_1_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[1] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_2_CR;
     e7c:	f8b4 2106 	ldrh.w	r2, [r4, #262]	; 0x106
    copy_cfg16_to_regs(p_regs, p_cfg, NB_OF_DDR_PHY_REGS_TO_CONFIG);
    
    /*--------------------------------------------------------------------------
     * Configure DDR FIC.
     */
    p_ddr_subsys_regs->fic.NB_ADDR_CR = p_ddr_subsys_cfg->fic.NB_ADDR_CR;
     e80:	f8c6 9400 	str.w	r9, [r6, #1024]	; 0x400
    p_ddr_subsys_regs->fic.NBRWB_SIZE_CR = p_ddr_subsys_cfg->fic.NBRWB_SIZE_CR;
     e84:	f8c6 a404 	str.w	sl, [r6, #1028]	; 0x404
    p_ddr_subsys_regs->fic.WB_TIMEOUT_CR = p_ddr_subsys_cfg->fic.WB_TIMEOUT_CR;
     e88:	f8c6 8408 	str.w	r8, [r6, #1032]	; 0x408
    p_ddr_subsys_regs->fic.HPD_SW_RW_EN_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_EN_CR;
     e8c:	f8c6 e40c 	str.w	lr, [r6, #1036]	; 0x40c
    p_ddr_subsys_regs->fic.HPD_SW_RW_INVAL_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_INVAL_CR;
     e90:	f8c6 c410 	str.w	ip, [r6, #1040]	; 0x410
    p_ddr_subsys_regs->fic.SW_WR_ERCLR_CR = p_ddr_subsys_cfg->fic.SW_WR_ERCLR_CR;
     e94:	f8c6 7414 	str.w	r7, [r6, #1044]	; 0x414
    p_ddr_subsys_regs->fic.ERR_INT_ENABLE_CR = p_ddr_subsys_cfg->fic.ERR_INT_ENABLE_CR;
     e98:	f8c6 5418 	str.w	r5, [r6, #1048]	; 0x418
    p_ddr_subsys_regs->fic.NUM_AHB_MASTERS_CR = p_ddr_subsys_cfg->fic.NUM_AHB_MASTERS_CR;
     e9c:	f8c6 041c 	str.w	r0, [r6, #1052]	; 0x41c
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[0] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_1_CR;
     ea0:	f8c6 1440 	str.w	r1, [r6, #1088]	; 0x440
    p_ddr_subsys_regs->fic.LOCK_TIMEOUT_EN_CR = p_ddr_subsys_cfg->fic.LOCK_TIMEOUT_EN_CR;

    /*--------------------------------------------------------------------------
     * Enable DDR.
     */
    p_ddr_subsys_regs->ddrc.DYN_SOFT_RESET_CR = 0x01u;
     ea4:	2101      	movs	r1, #1
    p_ddr_subsys_regs->fic.HPD_SW_RW_INVAL_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_INVAL_CR;
    p_ddr_subsys_regs->fic.SW_WR_ERCLR_CR = p_ddr_subsys_cfg->fic.SW_WR_ERCLR_CR;
    p_ddr_subsys_regs->fic.ERR_INT_ENABLE_CR = p_ddr_subsys_cfg->fic.ERR_INT_ENABLE_CR;
    p_ddr_subsys_regs->fic.NUM_AHB_MASTERS_CR = p_ddr_subsys_cfg->fic.NUM_AHB_MASTERS_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[0] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_1_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[1] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_2_CR;
     ea6:	f8c6 2444 	str.w	r2, [r6, #1092]	; 0x444
    p_ddr_subsys_regs->fic.LOCK_TIMEOUT_EN_CR = p_ddr_subsys_cfg->fic.LOCK_TIMEOUT_EN_CR;
     eaa:	f8c6 3448 	str.w	r3, [r6, #1096]	; 0x448

    /*--------------------------------------------------------------------------
     * Enable DDR.
     */
    p_ddr_subsys_regs->ddrc.DYN_SOFT_RESET_CR = 0x01u;
     eae:	6031      	str	r1, [r6, #0]
    
    while(0x0000u == p_ddr_subsys_regs->ddrc.DDRC_SR)
     eb0:	f8d6 30e4 	ldr.w	r3, [r6, #228]	; 0xe4
     eb4:	2b00      	cmp	r3, #0
     eb6:	d0fb      	beq.n	eb0 <SystemInit+0x110>
#endif

    /*--------------------------------------------------------------------------
     * Call user defined configuration function.
     */
    mscc_post_hw_cfg_init();
     eb8:	f7ff fa6a 	bl	390 <mscc_post_hw_cfg_init>
     * do this here because this signal is only deasserted by the System
     * Controller on a power-on reset. Other types of reset such as a watchdog
     * reset would result in the FPGA fabric being held in reset and getting
     * stuck waiting for the CoreSF2Config INIT_DONE to become asserted.
     */
    SYSREG->SOFT_RST_CR &= ~SYSREG_FPGA_SOFTRESET_MASK;
     ebc:	f248 0200 	movw	r2, #32768	; 0x8000
     ec0:	f2c4 0203 	movt	r2, #16387	; 0x4003
     ec4:	6c93      	ldr	r3, [r2, #72]	; 0x48

    /*
     * Signal to CoreSF2Reset that peripheral configuration registers have been
     * written.
     */
    CORE_SF2_CFG->CONFIG_DONE |= (CONFIG_1_DONE | CONFIG_2_DONE);
     ec6:	f242 0000 	movw	r0, #8192	; 0x2000
     * do this here because this signal is only deasserted by the System
     * Controller on a power-on reset. Other types of reset such as a watchdog
     * reset would result in the FPGA fabric being held in reset and getting
     * stuck waiting for the CoreSF2Config INIT_DONE to become asserted.
     */
    SYSREG->SOFT_RST_CR &= ~SYSREG_FPGA_SOFTRESET_MASK;
     eca:	f423 3180 	bic.w	r1, r3, #65536	; 0x10000
     ece:	6491      	str	r1, [r2, #72]	; 0x48

    /*
     * Signal to CoreSF2Reset that peripheral configuration registers have been
     * written.
     */
    CORE_SF2_CFG->CONFIG_DONE |= (CONFIG_1_DONE | CONFIG_2_DONE);
     ed0:	f2c4 0002 	movt	r0, #16386	; 0x4002
     ed4:	6803      	ldr	r3, [r0, #0]
     
    /* Wait for INIT_DONE from CoreSF2Reset. */
    do
    {
        init_done = CORE_SF2_CFG->INIT_DONE & INIT_DONE_MASK;
     ed6:	4602      	mov	r2, r0

    /*
     * Signal to CoreSF2Reset that peripheral configuration registers have been
     * written.
     */
    CORE_SF2_CFG->CONFIG_DONE |= (CONFIG_1_DONE | CONFIG_2_DONE);
     ed8:	f043 0103 	orr.w	r1, r3, #3
     edc:	6001      	str	r1, [r0, #0]
     
    /* Wait for INIT_DONE from CoreSF2Reset. */
    do
    {
        init_done = CORE_SF2_CFG->INIT_DONE & INIT_DONE_MASK;
     ede:	6850      	ldr	r0, [r2, #4]
    } while (0u == init_done);
     ee0:	f010 0f01 	tst.w	r0, #1
     ee4:	d0fb      	beq.n	ede <SystemInit+0x13e>
#endif
}
     ee6:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
     eea:	bf00      	nop

00000eec <__libc_init_array>:
     eec:	b570      	push	{r4, r5, r6, lr}
     eee:	f241 161c 	movw	r6, #4380	; 0x111c
     ef2:	f241 151c 	movw	r5, #4380	; 0x111c
     ef6:	f2c0 0600 	movt	r6, #0
     efa:	f2c0 0500 	movt	r5, #0
     efe:	1b76      	subs	r6, r6, r5
     f00:	10b6      	asrs	r6, r6, #2
     f02:	d006      	beq.n	f12 <__libc_init_array+0x26>
     f04:	2400      	movs	r4, #0
     f06:	f855 3024 	ldr.w	r3, [r5, r4, lsl #2]
     f0a:	3401      	adds	r4, #1
     f0c:	4798      	blx	r3
     f0e:	42a6      	cmp	r6, r4
     f10:	d8f9      	bhi.n	f06 <__libc_init_array+0x1a>
     f12:	f241 151c 	movw	r5, #4380	; 0x111c
     f16:	f241 1620 	movw	r6, #4384	; 0x1120
     f1a:	f2c0 0500 	movt	r5, #0
     f1e:	f2c0 0600 	movt	r6, #0
     f22:	1b76      	subs	r6, r6, r5
     f24:	f000 f8ee 	bl	1104 <_init>
     f28:	10b6      	asrs	r6, r6, #2
     f2a:	d006      	beq.n	f3a <__libc_init_array+0x4e>
     f2c:	2400      	movs	r4, #0
     f2e:	f855 3024 	ldr.w	r3, [r5, r4, lsl #2]
     f32:	3401      	adds	r4, #1
     f34:	4798      	blx	r3
     f36:	42a6      	cmp	r6, r4
     f38:	d8f9      	bhi.n	f2e <__libc_init_array+0x42>
     f3a:	bd70      	pop	{r4, r5, r6, pc}
     f3c:	7344454c 	.word	0x7344454c
     f40:	696c4220 	.word	0x696c4220
     f44:	6e696b6e 	.word	0x6e696b6e
     f48:	000d0a67 	.word	0x000d0a67

00000f4c <g_gpio_irqn_lut>:
     f4c:	35343332 39383736 3d3c3b3a 41403f3e     23456789:;<=>?@A
     f5c:	45444342 49484746 4d4c4b4a 51504f4e     BCDEFGHIJKLMNOPQ

00000f6c <g_config_reg_lut>:
     f6c:	40013000 40013004 40013008 4001300c     .0.@.0.@.0.@.0.@
     f7c:	40013010 40013014 40013018 4001301c     .0.@.0.@.0.@.0.@
     f8c:	40013020 40013024 40013028 4001302c      0.@$0.@(0.@,0.@
     f9c:	40013030 40013034 40013038 4001303c     00.@40.@80.@<0.@
     fac:	40013040 40013044 40013048 4001304c     @0.@D0.@H0.@L0.@
     fbc:	40013050 40013054 40013058 4001305c     P0.@T0.@X0.@\0.@
     fcc:	40013060 40013064 40013068 4001306c     `0.@d0.@h0.@l0.@
     fdc:	40013070 40013074 40013078 4001307c     p0.@t0.@x0.@|0.@

00000fec <C.17.3534>:
     fec:	01000100 03030202                       ........

00000ff4 <g_m2s_mddr_subsys_config>:
     ff4:	00000000 030f27de 00000002 09990101     .....'..........
    1004:	33330000 8888ffff 00010888 00084242     ..33........BB..
    1014:	00000528 00000000 00860ce0 00640235     (...........5.d.
    1024:	0178010f 19370033 00000010 00003300     ..x.3.7......3..
    1034:	04060000 02000000 00120040 40000002     ........@......@
    1044:	000780f8 000780f8 04000200 00050000     ................
    1054:	00400003 00000000 00000000 00010309     ..@.............
    1064:	00000000 00800000 00000000 00000003     ................
	...
    107c:	0000000b 00000000 00800000 01002004     ............. ..
    108c:	00000008 00000000 00000000 00000001     ................
	...
    10a4:	05014050 00005014 00000000 00000000     P@...P..........
	...
    10c4:	05010050 00005010 00000000 00000000     P....P..........
    10d4:	00430000 00030000 00010001 00000000     ..C.............
    10e4:	00010000 00000000 00000000 00000000     ................
	...

00001100 <g_m2s_mddr_addr>:
    1100:	40020800                                ...@

00001104 <_init>:
    1104:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    1106:	bf00      	nop
    1108:	bcf8      	pop	{r3, r4, r5, r6, r7}
    110a:	bc08      	pop	{r3}
    110c:	469e      	mov	lr, r3
    110e:	4770      	bx	lr

00001110 <_fini>:
    1110:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    1112:	bf00      	nop
    1114:	bcf8      	pop	{r3, r4, r5, r6, r7}
    1116:	bc08      	pop	{r3}
    1118:	469e      	mov	lr, r3
    111a:	4770      	bx	lr

0000111c <__frame_dummy_init_array_entry>:
    111c:	0425 0000                                   %...

00001120 <__do_global_dtors_aux_fini_array_entry>:
    1120:	0411 0000 0000 0000 0000 0000 0000 0000     ................
