
sample_image_eNVM_128KB:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .vector_table 00000190  00000000  00000000  00008000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .boot_code    00000280  00000190  00000190  00008190  2**4
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  2 .text         00000e80  00000410  00000410  00008410  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  3 .data         00000020  20000000  00001290  00010000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  4 .bss          00000090  20000020  000012b0  00010020  2**2
                  ALLOC
  5 .heap         0000cf50  200000b0  000012b0  000100b0  2**0
                  ALLOC
  6 .stack        00002000  2000d000  000012b0  00015000  2**0
                  ALLOC
  7 .comment      00000102  00000000  00000000  00010020  2**0
                  CONTENTS, READONLY
  8 .debug_aranges 000002b8  00000000  00000000  00010122  2**0
                  CONTENTS, READONLY, DEBUGGING
  9 .debug_pubnames 000007b9  00000000  00000000  000103da  2**0
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_info   000075b0  00000000  00000000  00010b93  2**0
                  CONTENTS, READONLY, DEBUGGING
 11 .debug_abbrev 00000b0f  00000000  00000000  00018143  2**0
                  CONTENTS, READONLY, DEBUGGING
 12 .debug_line   0000158b  00000000  00000000  00018c52  2**0
                  CONTENTS, READONLY, DEBUGGING
 13 .debug_frame  000006fc  00000000  00000000  0001a1e0  2**2
                  CONTENTS, READONLY, DEBUGGING
 14 .debug_str    000030b9  00000000  00000000  0001a8dc  2**0
                  CONTENTS, READONLY, DEBUGGING
 15 .debug_loc    00001182  00000000  00000000  0001d995  2**0
                  CONTENTS, READONLY, DEBUGGING
 16 .ARM.attributes 00000025  00000000  00000000  0001eb17  2**0
                  CONTENTS, READONLY
 17 .debug_ranges 00000eb8  00000000  00000000  0001eb3c  2**0
                  CONTENTS, READONLY, DEBUGGING

Disassembly of section .text:

00000410 <__do_global_dtors_aux>:
     410:	f240 0320 	movw	r3, #32
     414:	f2c2 0300 	movt	r3, #8192	; 0x2000
     418:	781a      	ldrb	r2, [r3, #0]
     41a:	b90a      	cbnz	r2, 420 <__do_global_dtors_aux+0x10>
     41c:	2001      	movs	r0, #1
     41e:	7018      	strb	r0, [r3, #0]
     420:	4770      	bx	lr
     422:	bf00      	nop

00000424 <frame_dummy>:
     424:	f240 0000 	movw	r0, #0
     428:	f2c2 0000 	movt	r0, #8192	; 0x2000
     42c:	b508      	push	{r3, lr}
     42e:	6803      	ldr	r3, [r0, #0]
     430:	b12b      	cbz	r3, 43e <frame_dummy+0x1a>
     432:	f240 0300 	movw	r3, #0
     436:	f2c0 0300 	movt	r3, #0
     43a:	b103      	cbz	r3, 43e <frame_dummy+0x1a>
     43c:	4798      	blx	r3
     43e:	bd08      	pop	{r3, pc}

00000440 <main>:
     440:	b580      	push	{r7, lr}
     442:	b082      	sub	sp, #8
     444:	af00      	add	r7, sp, #0
     446:	f04f 0300 	mov.w	r3, #0
     44a:	607b      	str	r3, [r7, #4]
     44c:	f640 5040 	movw	r0, #3392	; 0xd40
     450:	f2c0 0003 	movt	r0, #3
     454:	f000 f8e0 	bl	618 <delay>
     458:	f640 5040 	movw	r0, #3392	; 0xd40
     45c:	f2c0 0003 	movt	r0, #3
     460:	f000 f8da 	bl	618 <delay>
     464:	f240 0024 	movw	r0, #36	; 0x24
     468:	f2c2 0000 	movt	r0, #8192	; 0x2000
     46c:	f44f 4161 	mov.w	r1, #57600	; 0xe100
     470:	f04f 0203 	mov.w	r2, #3
     474:	f000 fbe4 	bl	c40 <MSS_UART_init>
     478:	f000 fc12 	bl	ca0 <MSS_GPIO_init>
     47c:	f04f 0000 	mov.w	r0, #0
     480:	f04f 0105 	mov.w	r1, #5
     484:	f000 fc58 	bl	d38 <MSS_GPIO_config>
     488:	f04f 0001 	mov.w	r0, #1
     48c:	f04f 0105 	mov.w	r1, #5
     490:	f000 fc52 	bl	d38 <MSS_GPIO_config>
     494:	f04f 0002 	mov.w	r0, #2
     498:	f04f 0105 	mov.w	r1, #5
     49c:	f000 fc4c 	bl	d38 <MSS_GPIO_config>
     4a0:	f04f 0003 	mov.w	r0, #3
     4a4:	f04f 0105 	mov.w	r1, #5
     4a8:	f000 fc46 	bl	d38 <MSS_GPIO_config>
     4ac:	f04f 0004 	mov.w	r0, #4
     4b0:	f04f 0105 	mov.w	r1, #5
     4b4:	f000 fc40 	bl	d38 <MSS_GPIO_config>
     4b8:	f04f 0008 	mov.w	r0, #8
     4bc:	f04f 0105 	mov.w	r1, #5
     4c0:	f000 fc3a 	bl	d38 <MSS_GPIO_config>
     4c4:	f04f 0009 	mov.w	r0, #9
     4c8:	f04f 0105 	mov.w	r1, #5
     4cc:	f000 fc34 	bl	d38 <MSS_GPIO_config>
     4d0:	f04f 000a 	mov.w	r0, #10
     4d4:	f04f 0105 	mov.w	r1, #5
     4d8:	f000 fc2e 	bl	d38 <MSS_GPIO_config>
     4dc:	f04f 0300 	mov.w	r3, #0
     4e0:	607b      	str	r3, [r7, #4]
     4e2:	f240 0024 	movw	r0, #36	; 0x24
     4e6:	f2c2 0000 	movt	r0, #8192	; 0x2000
     4ea:	f241 01a4 	movw	r1, #4260	; 0x10a4
     4ee:	f2c0 0100 	movt	r1, #0
     4f2:	f04f 0210 	mov.w	r2, #16
     4f6:	f000 f8a1 	bl	63c <MSS_UART_polled_tx>
     4fa:	687b      	ldr	r3, [r7, #4]
     4fc:	f103 0301 	add.w	r3, r3, #1
     500:	607b      	str	r3, [r7, #4]
     502:	f04f 0000 	mov.w	r0, #0
     506:	f04f 0100 	mov.w	r1, #0
     50a:	f000 fc1f 	bl	d4c <MSS_GPIO_set_output>
     50e:	f04f 0001 	mov.w	r0, #1
     512:	f04f 0100 	mov.w	r1, #0
     516:	f000 fc19 	bl	d4c <MSS_GPIO_set_output>
     51a:	f640 5040 	movw	r0, #3392	; 0xd40
     51e:	f2c0 0003 	movt	r0, #3
     522:	f000 f879 	bl	618 <delay>
     526:	f04f 0000 	mov.w	r0, #0
     52a:	f04f 0101 	mov.w	r1, #1
     52e:	f000 fc0d 	bl	d4c <MSS_GPIO_set_output>
     532:	f04f 0001 	mov.w	r0, #1
     536:	f04f 0101 	mov.w	r1, #1
     53a:	f000 fc07 	bl	d4c <MSS_GPIO_set_output>
     53e:	f640 5040 	movw	r0, #3392	; 0xd40
     542:	f2c0 0003 	movt	r0, #3
     546:	f000 f867 	bl	618 <delay>
     54a:	f04f 0002 	mov.w	r0, #2
     54e:	f04f 0100 	mov.w	r1, #0
     552:	f000 fbfb 	bl	d4c <MSS_GPIO_set_output>
     556:	f04f 0003 	mov.w	r0, #3
     55a:	f04f 0100 	mov.w	r1, #0
     55e:	f000 fbf5 	bl	d4c <MSS_GPIO_set_output>
     562:	f640 5040 	movw	r0, #3392	; 0xd40
     566:	f2c0 0003 	movt	r0, #3
     56a:	f000 f855 	bl	618 <delay>
     56e:	f04f 0002 	mov.w	r0, #2
     572:	f04f 0101 	mov.w	r1, #1
     576:	f000 fbe9 	bl	d4c <MSS_GPIO_set_output>
     57a:	f04f 0003 	mov.w	r0, #3
     57e:	f04f 0101 	mov.w	r1, #1
     582:	f000 fbe3 	bl	d4c <MSS_GPIO_set_output>
     586:	f640 5040 	movw	r0, #3392	; 0xd40
     58a:	f2c0 0003 	movt	r0, #3
     58e:	f000 f843 	bl	618 <delay>
     592:	f04f 0004 	mov.w	r0, #4
     596:	f04f 0100 	mov.w	r1, #0
     59a:	f000 fbd7 	bl	d4c <MSS_GPIO_set_output>
     59e:	f04f 0008 	mov.w	r0, #8
     5a2:	f04f 0100 	mov.w	r1, #0
     5a6:	f000 fbd1 	bl	d4c <MSS_GPIO_set_output>
     5aa:	f640 5040 	movw	r0, #3392	; 0xd40
     5ae:	f2c0 0003 	movt	r0, #3
     5b2:	f000 f831 	bl	618 <delay>
     5b6:	f04f 0004 	mov.w	r0, #4
     5ba:	f04f 0101 	mov.w	r1, #1
     5be:	f000 fbc5 	bl	d4c <MSS_GPIO_set_output>
     5c2:	f04f 0008 	mov.w	r0, #8
     5c6:	f04f 0101 	mov.w	r1, #1
     5ca:	f000 fbbf 	bl	d4c <MSS_GPIO_set_output>
     5ce:	f640 5040 	movw	r0, #3392	; 0xd40
     5d2:	f2c0 0003 	movt	r0, #3
     5d6:	f000 f81f 	bl	618 <delay>
     5da:	f04f 0009 	mov.w	r0, #9
     5de:	f04f 0100 	mov.w	r1, #0
     5e2:	f000 fbb3 	bl	d4c <MSS_GPIO_set_output>
     5e6:	f04f 000a 	mov.w	r0, #10
     5ea:	f04f 0100 	mov.w	r1, #0
     5ee:	f000 fbad 	bl	d4c <MSS_GPIO_set_output>
     5f2:	f640 5040 	movw	r0, #3392	; 0xd40
     5f6:	f2c0 0003 	movt	r0, #3
     5fa:	f000 f80d 	bl	618 <delay>
     5fe:	f04f 0009 	mov.w	r0, #9
     602:	f04f 0101 	mov.w	r1, #1
     606:	f000 fba1 	bl	d4c <MSS_GPIO_set_output>
     60a:	f04f 000a 	mov.w	r0, #10
     60e:	f04f 0101 	mov.w	r1, #1
     612:	f000 fb9b 	bl	d4c <MSS_GPIO_set_output>
     616:	e764      	b.n	4e2 <main+0xa2>

00000618 <delay>:
     618:	b480      	push	{r7}
     61a:	b083      	sub	sp, #12
     61c:	af00      	add	r7, sp, #0
     61e:	6078      	str	r0, [r7, #4]
     620:	e003      	b.n	62a <delay+0x12>
     622:	687b      	ldr	r3, [r7, #4]
     624:	f103 33ff 	add.w	r3, r3, #4294967295
     628:	607b      	str	r3, [r7, #4]
     62a:	687b      	ldr	r3, [r7, #4]
     62c:	2b00      	cmp	r3, #0
     62e:	dcf8      	bgt.n	622 <delay+0xa>
     630:	f107 070c 	add.w	r7, r7, #12
     634:	46bd      	mov	sp, r7
     636:	bc80      	pop	{r7}
     638:	4770      	bx	lr
     63a:	bf00      	nop

0000063c <MSS_UART_polled_tx>:

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(pbuff != ( (uint8_t *)0));
    ASSERT(tx_size > 0u);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
     63c:	f240 0364 	movw	r3, #100	; 0x64
     640:	f2c2 0300 	movt	r3, #8192	; 0x2000
     644:	4298      	cmp	r0, r3
(
    mss_uart_instance_t * this_uart,
    const uint8_t * pbuff,
    uint32_t tx_size
)
{
     646:	e92d 05f0 	stmdb	sp!, {r4, r5, r6, r7, r8, sl}

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(pbuff != ( (uint8_t *)0));
    ASSERT(tx_size > 0u);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
     64a:	d008      	beq.n	65e <MSS_UART_polled_tx+0x22>
     64c:	f240 0c24 	movw	ip, #36	; 0x24
     650:	f2c2 0c00 	movt	ip, #8192	; 0x2000
     654:	4560      	cmp	r0, ip
     656:	d002      	beq.n	65e <MSS_UART_polled_tx+0x22>
                /* Calculate the number of untransmitted bytes remaining. */
                tx_size -= size_sent;
            }
        } while(tx_size);
    }
}
     658:	e8bd 05f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, sl}
     65c:	4770      	bx	lr

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(pbuff != ( (uint8_t *)0));
    ASSERT(tx_size > 0u);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
     65e:	1e0b      	subs	r3, r1, #0
     660:	bf18      	it	ne
     662:	2301      	movne	r3, #1
     664:	2a00      	cmp	r2, #0
     666:	bf0c      	ite	eq
     668:	2300      	moveq	r3, #0
     66a:	f003 0301 	andne.w	r3, r3, #1
     66e:	2b00      	cmp	r3, #0
     670:	d0f2      	beq.n	658 <MSS_UART_polled_tx+0x1c>
     672:	f890 800d 	ldrb.w	r8, [r0, #13]
         /* Remain in this loop until the entire input buffer
          * has been transferred to the UART.
          */
        do {
            /* Read the Line Status Register and update the sticky record */
            status = this_uart->hw_reg->LSR;
     676:	f8d0 a000 	ldr.w	sl, [r0]
     67a:	2500      	movs	r5, #0
     67c:	f89a c014 	ldrb.w	ip, [sl, #20]
            this_uart->status |= status;
     680:	ea48 080c 	orr.w	r8, r8, ip

            /* Check if TX FIFO is empty. */
            if(status & MSS_UART_THRE)
     684:	f01c 0f20 	tst.w	ip, #32
          * has been transferred to the UART.
          */
        do {
            /* Read the Line Status Register and update the sticky record */
            status = this_uart->hw_reg->LSR;
            this_uart->status |= status;
     688:	f880 800d 	strb.w	r8, [r0, #13]

            /* Check if TX FIFO is empty. */
            if(status & MSS_UART_THRE)
     68c:	d023      	beq.n	6d6 <MSS_UART_polled_tx+0x9a>
            {
                uint32_t fill_size = TX_FIFO_SIZE;

                /* Calculate the number of bytes to transmit. */
                if(tx_size < TX_FIFO_SIZE)
     68e:	2a0f      	cmp	r2, #15
     690:	d924      	bls.n	6dc <MSS_UART_polled_tx+0xa0>
     692:	2710      	movs	r7, #16

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     694:	5d4e      	ldrb	r6, [r1, r5]
            if(status & MSS_UART_THRE)
            {
                uint32_t fill_size = TX_FIFO_SIZE;

                /* Calculate the number of bytes to transmit. */
                if(tx_size < TX_FIFO_SIZE)
     696:	6804      	ldr	r4, [r0, #0]
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     698:	2301      	movs	r3, #1
     69a:	f107 3cff 	add.w	ip, r7, #4294967295
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     69e:	7026      	strb	r6, [r4, #0]
     6a0:	ea0c 0603 	and.w	r6, ip, r3
                    char_idx++;
     6a4:	eb05 0c03 	add.w	ip, r5, r3
     6a8:	194d      	adds	r5, r1, r5
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     6aa:	42bb      	cmp	r3, r7
     6ac:	d211      	bcs.n	6d2 <MSS_UART_polled_tx+0x96>
     6ae:	b136      	cbz	r6, 6be <MSS_UART_polled_tx+0x82>
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     6b0:	5cee      	ldrb	r6, [r5, r3]
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     6b2:	2302      	movs	r3, #2
     6b4:	42bb      	cmp	r3, r7
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     6b6:	7026      	strb	r6, [r4, #0]
                    char_idx++;
     6b8:	f10c 0c01 	add.w	ip, ip, #1
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     6bc:	d209      	bcs.n	6d2 <MSS_UART_polled_tx+0x96>
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     6be:	5cee      	ldrb	r6, [r5, r3]
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     6c0:	3301      	adds	r3, #1
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     6c2:	7026      	strb	r6, [r4, #0]
     6c4:	5cee      	ldrb	r6, [r5, r3]
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     6c6:	3301      	adds	r3, #1
     6c8:	42bb      	cmp	r3, r7
                {
                    /* Send next character in the buffer. */
                    this_uart->hw_reg->THR = pbuff[char_idx];
     6ca:	7026      	strb	r6, [r4, #0]
                    char_idx++;
     6cc:	f10c 0c02 	add.w	ip, ip, #2
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     6d0:	d3f5      	bcc.n	6be <MSS_UART_polled_tx+0x82>
     6d2:	4665      	mov	r5, ip
                    this_uart->hw_reg->THR = pbuff[char_idx];
                    char_idx++;
                }

                /* Calculate the number of untransmitted bytes remaining. */
                tx_size -= size_sent;
     6d4:	1ad2      	subs	r2, r2, r3
            }
        } while(tx_size);
     6d6:	2a00      	cmp	r2, #0
     6d8:	d1d0      	bne.n	67c <MSS_UART_polled_tx+0x40>
     6da:	e7bd      	b.n	658 <MSS_UART_polled_tx+0x1c>
                {
                    fill_size = tx_size;
                }

                /* Fill the TX FIFO with the calculated the number of bytes. */
                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
     6dc:	b10a      	cbz	r2, 6e2 <MSS_UART_polled_tx+0xa6>
     6de:	4617      	mov	r7, r2
     6e0:	e7d8      	b.n	694 <MSS_UART_polled_tx+0x58>
     6e2:	4613      	mov	r3, r2
                    this_uart->hw_reg->THR = pbuff[char_idx];
                    char_idx++;
                }

                /* Calculate the number of untransmitted bytes remaining. */
                tx_size -= size_sent;
     6e4:	1ad2      	subs	r2, r2, r3
     6e6:	e7f6      	b.n	6d6 <MSS_UART_polled_tx+0x9a>

000006e8 <MSS_UART_isr>:
{
    uint8_t iirf;

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
     6e8:	f240 0364 	movw	r3, #100	; 0x64
     6ec:	f2c2 0300 	movt	r3, #8192	; 0x2000
     6f0:	4298      	cmp	r0, r3
static void
MSS_UART_isr
(
    mss_uart_instance_t * this_uart
)
{
     6f2:	b510      	push	{r4, lr}
     6f4:	4604      	mov	r4, r0
    uint8_t iirf;

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
     6f6:	d006      	beq.n	706 <MSS_UART_isr+0x1e>
     6f8:	f240 0024 	movw	r0, #36	; 0x24
     6fc:	f2c2 0000 	movt	r0, #8192	; 0x2000
     700:	4284      	cmp	r4, r0
     702:	d000      	beq.n	706 <MSS_UART_isr+0x1e>
     704:	bd10      	pop	{r4, pc}
    {
        iirf = this_uart->hw_reg->IIR & IIRF_MASK;
     706:	6822      	ldr	r2, [r4, #0]
     708:	7a11      	ldrb	r1, [r2, #8]

        switch (iirf)
     70a:	f001 0c0f 	and.w	ip, r1, #15
     70e:	f1bc 0f0c 	cmp.w	ip, #12
     712:	d8f7      	bhi.n	704 <MSS_UART_isr+0x1c>
     714:	a101      	add	r1, pc, #4	; (adr r1, 71c <MSS_UART_isr+0x34>)
     716:	f851 f02c 	ldr.w	pc, [r1, ip, lsl #2]
     71a:	bf00      	nop
     71c:	0000076d 	.word	0x0000076d
     720:	00000705 	.word	0x00000705
     724:	00000765 	.word	0x00000765
     728:	00000775 	.word	0x00000775
     72c:	0000075d 	.word	0x0000075d
     730:	00000705 	.word	0x00000705
     734:	00000751 	.word	0x00000751
     738:	00000705 	.word	0x00000705
     73c:	00000705 	.word	0x00000705
     740:	00000705 	.word	0x00000705
     744:	00000705 	.word	0x00000705
     748:	00000705 	.word	0x00000705
     74c:	0000075d 	.word	0x0000075d
            break;

            case IIRF_RX_LINE_STATUS:  /* Line Status Interrupt */
            {
                ASSERT(NULL_HANDLER != this_uart->linests_handler);
                if(NULL_HANDLER != this_uart->linests_handler)
     750:	69e3      	ldr	r3, [r4, #28]
     752:	2b00      	cmp	r3, #0
     754:	d0d6      	beq.n	704 <MSS_UART_isr+0x1c>
                {
                   (*(this_uart->linests_handler))(this_uart);
     756:	4620      	mov	r0, r4
     758:	4798      	blx	r3
     75a:	bd10      	pop	{r4, pc}

            case IIRF_RX_DATA:      /* Received Data Available */
            case IIRF_DATA_TIMEOUT: /* Received Data Timed-out */
            {
                ASSERT(NULL_HANDLER != this_uart->rx_handler);
                if(NULL_HANDLER != this_uart->rx_handler)
     75c:	6a23      	ldr	r3, [r4, #32]
     75e:	2b00      	cmp	r3, #0
     760:	d1f9      	bne.n	756 <MSS_UART_isr+0x6e>
     762:	e7cf      	b.n	704 <MSS_UART_isr+0x1c>
            break;

            case IIRF_THRE: /* Transmitter Holding Register Empty */
            {
                ASSERT(NULL_HANDLER != this_uart->tx_handler);
                if(NULL_HANDLER != this_uart->tx_handler)
     764:	6a63      	ldr	r3, [r4, #36]	; 0x24
     766:	2b00      	cmp	r3, #0
     768:	d1f5      	bne.n	756 <MSS_UART_isr+0x6e>
     76a:	e7cb      	b.n	704 <MSS_UART_isr+0x1c>
        switch (iirf)
        {
            case IIRF_MODEM_STATUS:  /* Modem status interrupt */
            {
                ASSERT(NULL_HANDLER != this_uart->modemsts_handler);
                if(NULL_HANDLER != this_uart->modemsts_handler)
     76c:	6aa3      	ldr	r3, [r4, #40]	; 0x28
     76e:	2b00      	cmp	r3, #0
     770:	d1f1      	bne.n	756 <MSS_UART_isr+0x6e>
     772:	e7c7      	b.n	704 <MSS_UART_isr+0x1c>
            case IIRF_MMI:
            {
                /* Identify multimode interrupts and handle */

                /* Receiver time-out interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,ERTOI))
     774:	3228      	adds	r2, #40	; 0x28
{
    return (HW_REG_BIT(reg,bit));
}
static __INLINE uint8_t read_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    return (HW_REG_BIT(reg,bit));
     776:	f022 407f 	bic.w	r0, r2, #4278190080	; 0xff000000
     77a:	f420 0370 	bic.w	r3, r0, #15728640	; 0xf00000
     77e:	f002 4170 	and.w	r1, r2, #4026531840	; 0xf0000000
     782:	0158      	lsls	r0, r3, #5
     784:	f101 7c00 	add.w	ip, r1, #33554432	; 0x2000000
     788:	f85c 3000 	ldr.w	r3, [ip, r0]
     78c:	f013 0fff 	tst.w	r3, #255	; 0xff
     790:	d005      	beq.n	79e <MSS_UART_isr+0xb6>
                {
                    ASSERT(NULL_HANDLER != this_uart->rto_handler);
                    if(NULL_HANDLER != this_uart->rto_handler)
     792:	6ae3      	ldr	r3, [r4, #44]	; 0x2c
     794:	b11b      	cbz	r3, 79e <MSS_UART_isr+0xb6>
                    {
                        (*(this_uart->rto_handler))(this_uart);
     796:	4620      	mov	r0, r4
     798:	4798      	blx	r3
     79a:	6822      	ldr	r2, [r4, #0]
     79c:	3228      	adds	r2, #40	; 0x28
     79e:	f002 4070 	and.w	r0, r2, #4026531840	; 0xf0000000
     7a2:	f022 4c7f 	bic.w	ip, r2, #4278190080	; 0xff000000
     7a6:	f100 7300 	add.w	r3, r0, #33554432	; 0x2000000
     7aa:	f42c 0170 	bic.w	r1, ip, #15728640	; 0xf00000
     7ae:	1d18      	adds	r0, r3, #4
     7b0:	0149      	lsls	r1, r1, #5
     7b2:	5843      	ldr	r3, [r0, r1]
                    }
                }
                /* NACK interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,ENACKI))
     7b4:	f013 0fff 	tst.w	r3, #255	; 0xff
     7b8:	d005      	beq.n	7c6 <MSS_UART_isr+0xde>
                {
                    ASSERT(NULL_HANDLER != this_uart->nack_handler);
                    if(NULL_HANDLER != this_uart->nack_handler)
     7ba:	6b23      	ldr	r3, [r4, #48]	; 0x30
     7bc:	b11b      	cbz	r3, 7c6 <MSS_UART_isr+0xde>
                    {
                        (*(this_uart->nack_handler))(this_uart);
     7be:	4620      	mov	r0, r4
     7c0:	4798      	blx	r3
     7c2:	6822      	ldr	r2, [r4, #0]
     7c4:	3228      	adds	r2, #40	; 0x28
     7c6:	f002 4370 	and.w	r3, r2, #4026531840	; 0xf0000000
     7ca:	f022 4c7f 	bic.w	ip, r2, #4278190080	; 0xff000000
     7ce:	f103 7000 	add.w	r0, r3, #33554432	; 0x2000000
     7d2:	f42c 0170 	bic.w	r1, ip, #15728640	; 0xf00000
     7d6:	3008      	adds	r0, #8
     7d8:	0149      	lsls	r1, r1, #5
     7da:	5843      	ldr	r3, [r0, r1]
                    }
                }

                /* PID parity error interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,EPID_PEI))
     7dc:	f013 0fff 	tst.w	r3, #255	; 0xff
     7e0:	d005      	beq.n	7ee <MSS_UART_isr+0x106>
                {
                    ASSERT(NULL_HANDLER != this_uart->pid_pei_handler);
                    if(NULL_HANDLER != this_uart->pid_pei_handler)
     7e2:	6b63      	ldr	r3, [r4, #52]	; 0x34
     7e4:	b11b      	cbz	r3, 7ee <MSS_UART_isr+0x106>
                    {
                        (*(this_uart->pid_pei_handler))(this_uart);
     7e6:	4620      	mov	r0, r4
     7e8:	4798      	blx	r3
     7ea:	6822      	ldr	r2, [r4, #0]
     7ec:	3228      	adds	r2, #40	; 0x28
     7ee:	f002 4370 	and.w	r3, r2, #4026531840	; 0xf0000000
     7f2:	f022 4c7f 	bic.w	ip, r2, #4278190080	; 0xff000000
     7f6:	f42c 0070 	bic.w	r0, ip, #15728640	; 0xf00000
     7fa:	f103 7300 	add.w	r3, r3, #33554432	; 0x2000000
     7fe:	330c      	adds	r3, #12
     800:	0141      	lsls	r1, r0, #5
     802:	5858      	ldr	r0, [r3, r1]
                    }
                }

                /* LIN break detection interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,ELINBI))
     804:	f010 0fff 	tst.w	r0, #255	; 0xff
     808:	d005      	beq.n	816 <MSS_UART_isr+0x12e>
                {
                    ASSERT(NULL_HANDLER != this_uart->break_handler);
                    if(NULL_HANDLER != this_uart->break_handler)
     80a:	6ba3      	ldr	r3, [r4, #56]	; 0x38
     80c:	b11b      	cbz	r3, 816 <MSS_UART_isr+0x12e>
                    {
                        (*(this_uart->break_handler))(this_uart);
     80e:	4620      	mov	r0, r4
     810:	4798      	blx	r3
     812:	6822      	ldr	r2, [r4, #0]
     814:	3228      	adds	r2, #40	; 0x28
     816:	f022 4c7f 	bic.w	ip, r2, #4278190080	; 0xff000000
     81a:	f002 4170 	and.w	r1, r2, #4026531840	; 0xf0000000
     81e:	f101 7200 	add.w	r2, r1, #33554432	; 0x2000000
     822:	f42c 0370 	bic.w	r3, ip, #15728640	; 0xf00000
     826:	3210      	adds	r2, #16
     828:	0158      	lsls	r0, r3, #5
     82a:	5811      	ldr	r1, [r2, r0]
                    }
                }

                /* LIN Sync detection interrupt */
                if(read_bit_reg8(&this_uart->hw_reg->IIM,ELINSI))
     82c:	f011 0fff 	tst.w	r1, #255	; 0xff
     830:	f43f af68 	beq.w	704 <MSS_UART_isr+0x1c>
                {
                    ASSERT(NULL_HANDLER != this_uart->sync_handler);
                    if(NULL_HANDLER != this_uart->sync_handler)
     834:	6be3      	ldr	r3, [r4, #60]	; 0x3c
     836:	2b00      	cmp	r3, #0
     838:	f43f af64 	beq.w	704 <MSS_UART_isr+0x1c>
                    {
                        (*(this_uart->sync_handler))(this_uart);
     83c:	4620      	mov	r0, r4
     83e:	4798      	blx	r3
     840:	e760      	b.n	704 <MSS_UART_isr+0x1c>
     842:	bf00      	nop

00000844 <UART1_IRQHandler>:
#if defined(__GNUC__)
__attribute__((__interrupt__)) void UART1_IRQHandler(void)
#else
void UART1_IRQHandler(void)
#endif
{
     844:	4668      	mov	r0, sp
     846:	f020 0107 	bic.w	r1, r0, #7
     84a:	468d      	mov	sp, r1
     84c:	b501      	push	{r0, lr}
    MSS_UART_isr(&g_mss_uart1);
     84e:	f240 0024 	movw	r0, #36	; 0x24
     852:	f2c2 0000 	movt	r0, #8192	; 0x2000
     856:	f7ff ff47 	bl	6e8 <MSS_UART_isr>
}
     85a:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
     85e:	4685      	mov	sp, r0
     860:	4770      	bx	lr
     862:	bf00      	nop

00000864 <UART0_IRQHandler>:
#if defined(__GNUC__)
__attribute__((__interrupt__)) void UART0_IRQHandler(void)
#else
void UART0_IRQHandler(void)
#endif
{
     864:	4668      	mov	r0, sp
     866:	f020 0107 	bic.w	r1, r0, #7
     86a:	468d      	mov	sp, r1
     86c:	b501      	push	{r0, lr}
    MSS_UART_isr(&g_mss_uart0);
     86e:	f240 0064 	movw	r0, #100	; 0x64
     872:	f2c2 0000 	movt	r0, #8192	; 0x2000
     876:	f7ff ff37 	bl	6e8 <MSS_UART_isr>
}
     87a:	e8bd 4001 	ldmia.w	sp!, {r0, lr}
     87e:	4685      	mov	sp, r0
     880:	4770      	bx	lr
     882:	bf00      	nop

00000884 <default_tx_handler>:

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(( (uint8_t *)0 ) != this_uart->tx_buffer);
    ASSERT(0u < this_uart->tx_buff_size);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
     884:	f240 0364 	movw	r3, #100	; 0x64
     888:	f2c2 0300 	movt	r3, #8192	; 0x2000
     88c:	4298      	cmp	r0, r3
static void
default_tx_handler
(
    mss_uart_instance_t * this_uart
)
{
     88e:	b470      	push	{r4, r5, r6}

    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(( (uint8_t *)0 ) != this_uart->tx_buffer);
    ASSERT(0u < this_uart->tx_buff_size);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
     890:	d007      	beq.n	8a2 <default_tx_handler+0x1e>
     892:	f240 0124 	movw	r1, #36	; 0x24
     896:	f2c2 0100 	movt	r1, #8192	; 0x2000
     89a:	4288      	cmp	r0, r1
     89c:	d001      	beq.n	8a2 <default_tx_handler+0x1e>
            this_uart->tx_buff_size = TX_COMPLETE;
            /* disables TX interrupt */
            clear_bit_reg8(&this_uart->hw_reg->IER,ETBEI);
        }
    }
}
     89e:	bc70      	pop	{r4, r5, r6}
     8a0:	4770      	bx	lr
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    ASSERT(( (uint8_t *)0 ) != this_uart->tx_buffer);
    ASSERT(0u < this_uart->tx_buff_size);

    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
       (((uint8_t *)0 ) != this_uart->tx_buffer) &&
     8a2:	6904      	ldr	r4, [r0, #16]
     8a4:	2c00      	cmp	r4, #0
     8a6:	d0fa      	beq.n	89e <default_tx_handler+0x1a>
       (0u < this_uart->tx_buff_size))
     8a8:	6943      	ldr	r3, [r0, #20]
     8aa:	2b00      	cmp	r3, #0
     8ac:	d0f7      	beq.n	89e <default_tx_handler+0x1a>
    {
        /* Read the Line Status Register and update the sticky record. */
        status = this_uart->hw_reg->LSR;
     8ae:	6801      	ldr	r1, [r0, #0]
        this_uart->status |= status;
     8b0:	f890 c00d 	ldrb.w	ip, [r0, #13]
    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
       (((uint8_t *)0 ) != this_uart->tx_buffer) &&
       (0u < this_uart->tx_buff_size))
    {
        /* Read the Line Status Register and update the sticky record. */
        status = this_uart->hw_reg->LSR;
     8b4:	7d0a      	ldrb	r2, [r1, #20]
        this_uart->status |= status;
     8b6:	ea42 0c0c 	orr.w	ip, r2, ip

        /*
         * This function should only be called as a result of a THRE interrupt.
         * Verify that this is true before proceeding to transmit data.
         */
        if(status & MSS_UART_THRE)
     8ba:	f012 0f20 	tst.w	r2, #32
       (((uint8_t *)0 ) != this_uart->tx_buffer) &&
       (0u < this_uart->tx_buff_size))
    {
        /* Read the Line Status Register and update the sticky record. */
        status = this_uart->hw_reg->LSR;
        this_uart->status |= status;
     8be:	f880 c00d 	strb.w	ip, [r0, #13]

        /*
         * This function should only be called as a result of a THRE interrupt.
         * Verify that this is true before proceeding to transmit data.
         */
        if(status & MSS_UART_THRE)
     8c2:	6982      	ldr	r2, [r0, #24]
     8c4:	d029      	beq.n	91a <default_tx_handler+0x96>
        {
            uint32_t i;
            uint32_t fill_size = TX_FIFO_SIZE;
            uint32_t tx_remain = this_uart->tx_buff_size - this_uart->tx_idx;
     8c6:	1a9d      	subs	r5, r3, r2

            /* Calculate the number of bytes to transmit. */
            if(tx_remain < TX_FIFO_SIZE)
     8c8:	2d0f      	cmp	r5, #15
     8ca:	d938      	bls.n	93e <default_tx_handler+0xba>
     8cc:	2510      	movs	r5, #16
     8ce:	18a4      	adds	r4, r4, r2

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     8d0:	7826      	ldrb	r6, [r4, #0]
     8d2:	1e6b      	subs	r3, r5, #1
     8d4:	700e      	strb	r6, [r1, #0]
     8d6:	f003 0601 	and.w	r6, r3, #1
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     8da:	2301      	movs	r3, #1
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
                ++this_uart->tx_idx;
     8dc:	3201      	adds	r2, #1
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     8de:	429d      	cmp	r5, r3
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
                ++this_uart->tx_idx;
     8e0:	6182      	str	r2, [r0, #24]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     8e2:	d919      	bls.n	918 <default_tx_handler+0x94>
     8e4:	b146      	cbz	r6, 8f8 <default_tx_handler+0x74>
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     8e6:	f894 c001 	ldrb.w	ip, [r4, #1]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     8ea:	2302      	movs	r3, #2
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
                ++this_uart->tx_idx;
     8ec:	3201      	adds	r2, #1
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     8ee:	429d      	cmp	r5, r3
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     8f0:	f881 c000 	strb.w	ip, [r1]
                ++this_uart->tx_idx;
     8f4:	6182      	str	r2, [r0, #24]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     8f6:	d90f      	bls.n	918 <default_tx_handler+0x94>
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     8f8:	f814 c003 	ldrb.w	ip, [r4, r3]
                ++this_uart->tx_idx;
     8fc:	3201      	adds	r2, #1

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     8fe:	f881 c000 	strb.w	ip, [r1]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     902:	3301      	adds	r3, #1
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
                ++this_uart->tx_idx;
     904:	6182      	str	r2, [r0, #24]

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     906:	f814 c003 	ldrb.w	ip, [r4, r3]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     90a:	3301      	adds	r3, #1
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
                ++this_uart->tx_idx;
     90c:	3201      	adds	r2, #1
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     90e:	429d      	cmp	r5, r3
            {
                /* Send next character in the buffer. */
                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
     910:	f881 c000 	strb.w	ip, [r1]
                ++this_uart->tx_idx;
     914:	6182      	str	r2, [r0, #24]
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     916:	d8ef      	bhi.n	8f8 <default_tx_handler+0x74>
     918:	6943      	ldr	r3, [r0, #20]
                ++this_uart->tx_idx;
            }
        }

        /* Flag Tx as complete if all data has been pushed into the Tx FIFO. */
        if(this_uart->tx_idx == this_uart->tx_buff_size)
     91a:	429a      	cmp	r2, r3
     91c:	d1bf      	bne.n	89e <default_tx_handler+0x1a>
        {
            this_uart->tx_buff_size = TX_COMPLETE;
            /* disables TX interrupt */
            clear_bit_reg8(&this_uart->hw_reg->IER,ETBEI);
     91e:	6802      	ldr	r2, [r0, #0]
        }

        /* Flag Tx as complete if all data has been pushed into the Tx FIFO. */
        if(this_uart->tx_idx == this_uart->tx_buff_size)
        {
            this_uart->tx_buff_size = TX_COMPLETE;
     920:	2100      	movs	r1, #0
            /* disables TX interrupt */
            clear_bit_reg8(&this_uart->hw_reg->IER,ETBEI);
     922:	1d13      	adds	r3, r2, #4
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     924:	f023 4c7f 	bic.w	ip, r3, #4278190080	; 0xff000000
     928:	f003 4270 	and.w	r2, r3, #4026531840	; 0xf0000000
     92c:	f102 7300 	add.w	r3, r2, #33554432	; 0x2000000
     930:	f42c 0270 	bic.w	r2, ip, #15728640	; 0xf00000
     934:	3304      	adds	r3, #4
     936:	0152      	lsls	r2, r2, #5
     938:	5099      	str	r1, [r3, r2]
        }

        /* Flag Tx as complete if all data has been pushed into the Tx FIFO. */
        if(this_uart->tx_idx == this_uart->tx_buff_size)
        {
            this_uart->tx_buff_size = TX_COMPLETE;
     93a:	6141      	str	r1, [r0, #20]
     93c:	e7af      	b.n	89e <default_tx_handler+0x1a>
            {
                fill_size = tx_remain;
            }

            /* Fill the TX FIFO with the calculated the number of bytes. */
            for(i = 0u; i < fill_size; ++i)
     93e:	2d00      	cmp	r5, #0
     940:	d1c5      	bne.n	8ce <default_tx_handler+0x4a>
     942:	e7ea      	b.n	91a <default_tx_handler+0x96>

00000944 <global_init>:
(
    mss_uart_instance_t * this_uart,
    uint32_t baud_rate,
    uint8_t line_config
)
{
     944:	e92d 4ff0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
     948:	f240 0364 	movw	r3, #100	; 0x64
(
    mss_uart_instance_t * this_uart,
    uint32_t baud_rate,
    uint8_t line_config
)
{
     94c:	b08f      	sub	sp, #60	; 0x3c
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
     94e:	f2c2 0300 	movt	r3, #8192	; 0x2000
(
    mss_uart_instance_t * this_uart,
    uint32_t baud_rate,
    uint8_t line_config
)
{
     952:	920b      	str	r2, [sp, #44]	; 0x2c
    if(this_uart == &g_mss_uart0)
    {
        this_uart->hw_reg = UART0;
        this_uart->irqn = UART0_IRQn;
        /* reset UART0 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART0_SOFTRESET_MASK;
     954:	f248 0200 	movw	r2, #32768	; 0x8000
{
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
     958:	4298      	cmp	r0, r3
    {
        this_uart->hw_reg = UART0;
        this_uart->irqn = UART0_IRQn;
        /* reset UART0 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART0_SOFTRESET_MASK;
     95a:	f2c4 0203 	movt	r2, #16387	; 0x4003
(
    mss_uart_instance_t * this_uart,
    uint32_t baud_rate,
    uint8_t line_config
)
{
     95e:	4604      	mov	r4, r0
     960:	910d      	str	r1, [sp, #52]	; 0x34
    if(this_uart == &g_mss_uart0)
    {
        this_uart->hw_reg = UART0;
        this_uart->irqn = UART0_IRQn;
        /* reset UART0 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART0_SOFTRESET_MASK;
     962:	6c90      	ldr	r0, [r2, #72]	; 0x48

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
     964:	f24e 1100 	movw	r1, #57600	; 0xe100
{
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
     968:	f000 8129 	beq.w	bbe <global_init+0x27a>
    else
    {
        this_uart->hw_reg = UART1;
        this_uart->irqn = UART1_IRQn;
        /* Reset UART1 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART1_SOFTRESET_MASK;
     96c:	f440 7780 	orr.w	r7, r0, #256	; 0x100
     970:	f2ce 0100 	movt	r1, #57344	; 0xe000
     974:	f44f 6600 	mov.w	r6, #2048	; 0x800
     978:	6497      	str	r7, [r2, #72]	; 0x48
     97a:	f8c1 6180 	str.w	r6, [r1, #384]	; 0x180
        /* Clear any previously pended UART1 interrupt */
        NVIC_ClearPendingIRQ(UART1_IRQn);
        /* Take UART1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART1_SOFTRESET_MASK;
     97e:	6c95      	ldr	r5, [r2, #72]	; 0x48
        /* Take UART0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
    }
    else
    {
        this_uart->hw_reg = UART1;
     980:	f240 0100 	movw	r1, #0
        /* Reset UART1 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART1_SOFTRESET_MASK;
        /* Clear any previously pended UART1 interrupt */
        NVIC_ClearPendingIRQ(UART1_IRQn);
        /* Take UART1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART1_SOFTRESET_MASK;
     984:	f425 7080 	bic.w	r0, r5, #256	; 0x100
        /* Take UART0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
    }
    else
    {
        this_uart->hw_reg = UART1;
     988:	f2c4 0101 	movt	r1, #16385	; 0x4001
        /* Reset UART1 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART1_SOFTRESET_MASK;
        /* Clear any previously pended UART1 interrupt */
        NVIC_ClearPendingIRQ(UART1_IRQn);
        /* Take UART1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART1_SOFTRESET_MASK;
     98c:	6490      	str	r0, [r2, #72]	; 0x48
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
    }
    else
    {
        this_uart->hw_reg = UART1;
        this_uart->irqn = UART1_IRQn;
     98e:	220b      	movs	r2, #11
     990:	7122      	strb	r2, [r4, #4]
        /* Take UART0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
    }
    else
    {
        this_uart->hw_reg = UART1;
     992:	6021      	str	r1, [r4, #0]
        /* Take UART1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART1_SOFTRESET_MASK;
    }

    /* disable interrupts */
    this_uart->hw_reg->IER = 0u;
     994:	2200      	movs	r2, #0

    /* FIFO configuration */
    this_uart->hw_reg->FCR = (uint8_t)MSS_UART_FIFO_SINGLE_BYTE;
     996:	460d      	mov	r5, r1
        /* Take UART1 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART1_SOFTRESET_MASK;
    }

    /* disable interrupts */
    this_uart->hw_reg->IER = 0u;
     998:	710a      	strb	r2, [r1, #4]
    /* enable RXRDYN and TXRDYN pins. The earlier FCR write to set the TX FIFO
     * trigger level inadvertently disabled the FCR_RXRDY_TXRDYN_EN bit. */
    set_bit_reg8(&this_uart->hw_reg->FCR,RXRDY_TXRDYN_EN);

    /* disable loopback : local * remote */
    clear_bit_reg8(&this_uart->hw_reg->MCR,LOOP);
     99a:	f101 0610 	add.w	r6, r1, #16

    /* disable interrupts */
    this_uart->hw_reg->IER = 0u;

    /* FIFO configuration */
    this_uart->hw_reg->FCR = (uint8_t)MSS_UART_FIFO_SINGLE_BYTE;
     99e:	f805 2f08 	strb.w	r2, [r5, #8]!
    clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_TX);
    /* set default RX endian */
    clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_RX);

    /* default AFM : disabled */
    clear_bit_reg8(&this_uart->hw_reg->MM2,EAFM);
     9a2:	f101 0a38 	add.w	sl, r1, #56	; 0x38
     9a6:	f02a 4b7f 	bic.w	fp, sl, #4278190080	; 0xff000000
    /* disable loopback : local * remote */
    clear_bit_reg8(&this_uart->hw_reg->MCR,LOOP);
    clear_bit_reg8(&this_uart->hw_reg->MCR,RLOOP);

    /* set default TX endian */
    clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_TX);
     9aa:	f101 0934 	add.w	r9, r1, #52	; 0x34
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     9ae:	f025 477f 	bic.w	r7, r5, #4278190080	; 0xff000000
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     9b2:	f026 487f 	bic.w	r8, r6, #4278190080	; 0xff000000
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     9b6:	f005 4570 	and.w	r5, r5, #4026531840	; 0xf0000000
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     9ba:	f006 4670 	and.w	r6, r6, #4026531840	; 0xf0000000
     9be:	f00a 4a70 	and.w	sl, sl, #4026531840	; 0xf0000000
     9c2:	f8cd a010 	str.w	sl, [sp, #16]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     9c6:	9506      	str	r5, [sp, #24]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     9c8:	f029 407f 	bic.w	r0, r9, #4278190080	; 0xff000000
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     9cc:	f106 7500 	add.w	r5, r6, #33554432	; 0x2000000
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     9d0:	9003      	str	r0, [sp, #12]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     9d2:	9501      	str	r5, [sp, #4]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     9d4:	f009 4970 	and.w	r9, r9, #4026531840	; 0xf0000000
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     9d8:	9d04      	ldr	r5, [sp, #16]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     9da:	f8cd 901c 	str.w	r9, [sp, #28]
     9de:	f8dd 900c 	ldr.w	r9, [sp, #12]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     9e2:	f105 7500 	add.w	r5, r5, #33554432	; 0x2000000
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     9e6:	f429 0a70 	bic.w	sl, r9, #15728640	; 0xf00000
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     9ea:	950a      	str	r5, [sp, #40]	; 0x28
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     9ec:	f42b 0970 	bic.w	r9, fp, #15728640	; 0xf00000
     9f0:	9d07      	ldr	r5, [sp, #28]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     9f2:	f8dd b018 	ldr.w	fp, [sp, #24]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     9f6:	f8cd 9014 	str.w	r9, [sp, #20]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     9fa:	f10b 7900 	add.w	r9, fp, #33554432	; 0x2000000
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     9fe:	f105 7b00 	add.w	fp, r5, #33554432	; 0x2000000
     a02:	9d04      	ldr	r5, [sp, #16]

    /* default AFM : disabled */
    clear_bit_reg8(&this_uart->hw_reg->MM2,EAFM);

    /* disable TX time gaurd */
    clear_bit_reg8(&this_uart->hw_reg->MM0,ETTG); 
     a04:	f101 0c30 	add.w	ip, r1, #48	; 0x30
     a08:	f02c 407f 	bic.w	r0, ip, #4278190080	; 0xff000000
     a0c:	f105 7500 	add.w	r5, r5, #33554432	; 0x2000000
     a10:	f00c 4c70 	and.w	ip, ip, #4026531840	; 0xf0000000
     a14:	f8cd a00c 	str.w	sl, [sp, #12]
     a18:	9504      	str	r5, [sp, #16]
     a1a:	f10c 7500 	add.w	r5, ip, #33554432	; 0x2000000
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     a1e:	f10c 7a00 	add.w	sl, ip, #33554432	; 0x2000000
     a22:	46ac      	mov	ip, r5
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     a24:	9d03      	ldr	r5, [sp, #12]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     a26:	f8cd a024 	str.w	sl, [sp, #36]	; 0x24
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     a2a:	016d      	lsls	r5, r5, #5
     a2c:	9503      	str	r5, [sp, #12]
     a2e:	9d05      	ldr	r5, [sp, #20]
     a30:	f428 0870 	bic.w	r8, r8, #15728640	; 0xf00000
     a34:	016d      	lsls	r5, r5, #5
     a36:	9505      	str	r5, [sp, #20]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     a38:	9d06      	ldr	r5, [sp, #24]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     a3a:	46ca      	mov	sl, r9
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     a3c:	f105 7500 	add.w	r5, r5, #33554432	; 0x2000000
     a40:	9506      	str	r5, [sp, #24]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     a42:	9d01      	ldr	r5, [sp, #4]
     a44:	ea4f 1848 	mov.w	r8, r8, lsl #5
     a48:	3514      	adds	r5, #20
     a4a:	9501      	str	r5, [sp, #4]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     a4c:	9d07      	ldr	r5, [sp, #28]
     a4e:	f427 0770 	bic.w	r7, r7, #15728640	; 0xf00000
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     a52:	f105 7500 	add.w	r5, r5, #33554432	; 0x2000000
     a56:	9507      	str	r5, [sp, #28]
     a58:	9d04      	ldr	r5, [sp, #16]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     a5a:	017f      	lsls	r7, r7, #5
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     a5c:	3504      	adds	r5, #4
     a5e:	9504      	str	r5, [sp, #16]
     a60:	4665      	mov	r5, ip
     a62:	3514      	adds	r5, #20
     a64:	9508      	str	r5, [sp, #32]
     a66:	9d09      	ldr	r5, [sp, #36]	; 0x24
     a68:	f8cd 8030 	str.w	r8, [sp, #48]	; 0x30
     a6c:	351c      	adds	r5, #28
     a6e:	9509      	str	r5, [sp, #36]	; 0x24
     a70:	9d0a      	ldr	r5, [sp, #40]	; 0x28
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     a72:	f04f 0801 	mov.w	r8, #1
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     a76:	350c      	adds	r5, #12
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     a78:	f10a 0a08 	add.w	sl, sl, #8
     a7c:	f109 0904 	add.w	r9, r9, #4
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     a80:	950a      	str	r5, [sp, #40]	; 0x28
     a82:	f106 7600 	add.w	r6, r6, #33554432	; 0x2000000
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     a86:	f849 8007 	str.w	r8, [r9, r7]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     a8a:	9d0c      	ldr	r5, [sp, #48]	; 0x30
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     a8c:	f84a 8007 	str.w	r8, [sl, r7]
     a90:	f8dd a018 	ldr.w	sl, [sp, #24]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     a94:	3610      	adds	r6, #16
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     a96:	f84a 8007 	str.w	r8, [sl, r7]
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     a9a:	5172      	str	r2, [r6, r5]
     a9c:	f8dd a00c 	ldr.w	sl, [sp, #12]
     aa0:	9e01      	ldr	r6, [sp, #4]
     aa2:	f10b 0b04 	add.w	fp, fp, #4
     aa6:	5172      	str	r2, [r6, r5]
     aa8:	f84b 200a 	str.w	r2, [fp, sl]
     aac:	f8dd b01c 	ldr.w	fp, [sp, #28]
     ab0:	9d05      	ldr	r5, [sp, #20]
     ab2:	f84b 200a 	str.w	r2, [fp, sl]
     ab6:	9e04      	ldr	r6, [sp, #16]
     ab8:	f8dd a020 	ldr.w	sl, [sp, #32]
     abc:	f420 0070 	bic.w	r0, r0, #15728640	; 0xf00000
     ac0:	0140      	lsls	r0, r0, #5
     ac2:	f10c 0c18 	add.w	ip, ip, #24
     ac6:	5172      	str	r2, [r6, r5]
     ac8:	f8dd b024 	ldr.w	fp, [sp, #36]	; 0x24
     acc:	f84a 2000 	str.w	r2, [sl, r0]
     ad0:	f84c 2000 	str.w	r2, [ip, r0]
     ad4:	f8dd c028 	ldr.w	ip, [sp, #40]	; 0x28
    uint32_t baudrate    
)
{
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    
    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
     ad8:	429c      	cmp	r4, r3
     ada:	f84b 2000 	str.w	r2, [fp, r0]
     ade:	f84c 2005 	str.w	r2, [ip, r5]

    /* disable single wire mode */
    clear_bit_reg8(&this_uart->hw_reg->MM2,ESWM);

    /* set filter to minimum value */
    this_uart->hw_reg->GFR = 0u;
     ae2:	f881 2044 	strb.w	r2, [r1, #68]	; 0x44
    /* set default TX time gaurd */
    this_uart->hw_reg->TTG = 0u;
     ae6:	f881 2048 	strb.w	r2, [r1, #72]	; 0x48
    /* set default RX timeout */
    this_uart->hw_reg->RTO = 0u;
     aea:	f881 204c 	strb.w	r2, [r1, #76]	; 0x4c
    uint32_t baudrate    
)
{
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
    
    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
     aee:	d079      	beq.n	be4 <global_init+0x2a0>
     af0:	f240 0324 	movw	r3, #36	; 0x24
     af4:	f2c2 0300 	movt	r3, #8192	; 0x2000
     af8:	429c      	cmp	r4, r3
     afa:	d015      	beq.n	b28 <global_init+0x1e4>
     * where possible to provide the most accurate baud rat possible.
     */
    config_baud_divisors(this_uart, baud_rate);

    /* set the line control register (bit length, stop bits, parity) */
    this_uart->hw_reg->LCR = line_config;
     afc:	9d0b      	ldr	r5, [sp, #44]	; 0x2c

    /* Instance setup */
    this_uart->baudrate = baud_rate;
    this_uart->lineconfig = line_config;
    this_uart->tx_buff_size = TX_COMPLETE;
     afe:	2000      	movs	r0, #0
     * where possible to provide the most accurate baud rat possible.
     */
    config_baud_divisors(this_uart, baud_rate);

    /* set the line control register (bit length, stop bits, parity) */
    this_uart->hw_reg->LCR = line_config;
     b00:	730d      	strb	r5, [r1, #12]
    this_uart->pid_pei_handler  = NULL_HANDLER;
    this_uart->break_handler    = NULL_HANDLER;    
    this_uart->sync_handler     = NULL_HANDLER;   

    /* Initialize the sticky status */
    this_uart->status = 0u;
     b02:	7360      	strb	r0, [r4, #13]

    /* set the line control register (bit length, stop bits, parity) */
    this_uart->hw_reg->LCR = line_config;

    /* Instance setup */
    this_uart->baudrate = baud_rate;
     b04:	9e0d      	ldr	r6, [sp, #52]	; 0x34
    this_uart->lineconfig = line_config;
    this_uart->tx_buff_size = TX_COMPLETE;
     b06:	6160      	str	r0, [r4, #20]

    /* set the line control register (bit length, stop bits, parity) */
    this_uart->hw_reg->LCR = line_config;

    /* Instance setup */
    this_uart->baudrate = baud_rate;
     b08:	60a6      	str	r6, [r4, #8]
    this_uart->lineconfig = line_config;
     b0a:	7325      	strb	r5, [r4, #12]
    this_uart->tx_buff_size = TX_COMPLETE;
    this_uart->tx_buffer = (const uint8_t *)0;
     b0c:	6120      	str	r0, [r4, #16]
    this_uart->tx_idx = 0u;
     b0e:	61a0      	str	r0, [r4, #24]

    /* Default handlers for MSS UART interrupts */
    this_uart->rx_handler       = NULL_HANDLER;
     b10:	6220      	str	r0, [r4, #32]
    this_uart->tx_handler       = NULL_HANDLER;
     b12:	6260      	str	r0, [r4, #36]	; 0x24
    this_uart->linests_handler  = NULL_HANDLER;
     b14:	61e0      	str	r0, [r4, #28]
    this_uart->modemsts_handler = NULL_HANDLER;
     b16:	62a0      	str	r0, [r4, #40]	; 0x28
    this_uart->rto_handler      = NULL_HANDLER;    
     b18:	62e0      	str	r0, [r4, #44]	; 0x2c
    this_uart->nack_handler     = NULL_HANDLER;   
     b1a:	6320      	str	r0, [r4, #48]	; 0x30
    this_uart->pid_pei_handler  = NULL_HANDLER;
     b1c:	6360      	str	r0, [r4, #52]	; 0x34
    this_uart->break_handler    = NULL_HANDLER;    
     b1e:	63a0      	str	r0, [r4, #56]	; 0x38
    this_uart->sync_handler     = NULL_HANDLER;   
     b20:	63e0      	str	r0, [r4, #60]	; 0x3c

    /* Initialize the sticky status */
    this_uart->status = 0u;
}
     b22:	b00f      	add	sp, #60	; 0x3c
     b24:	e8bd 8ff0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
        uint32_t baud_value_by_64;
        uint32_t baud_value_by_128;
        uint32_t fractional_baud_value;
        uint32_t pclk_freq;

        this_uart->baudrate = baudrate;
     b28:	9f0d      	ldr	r7, [sp, #52]	; 0x34
     b2a:	60a7      	str	r7, [r4, #8]

        /* Force the value of the CMSIS global variables holding the various system
          * clock frequencies to be updated. */
        SystemCoreClockUpdate();
     b2c:	f000 f924 	bl	d78 <SystemCoreClockUpdate>
        {
            pclk_freq = g_FrequencyPCLK0;
        }
        else
        {
            pclk_freq = g_FrequencyPCLK1;
     b30:	f240 0118 	movw	r1, #24
     b34:	f2c2 0100 	movt	r1, #8192	; 0x2000
     b38:	680a      	ldr	r2, [r1, #0]
        /*
         * Compute baud value based on requested baud rate and PCLK frequency.
         * The baud value is computed using the following equation:
         *      baud_value = PCLK_Frequency / (baud_rate * 16)
         */
        baud_value_by_128 = (8u * pclk_freq) / baudrate;
     b3a:	9e0d      	ldr	r6, [sp, #52]	; 0x34
     b3c:	00d7      	lsls	r7, r2, #3
     b3e:	fbb7 f2f6 	udiv	r2, r7, r6
        baud_value_by_64 = baud_value_by_128 / 2u;
        baud_value = baud_value_by_64 / 64u;
     b42:	09d3      	lsrs	r3, r2, #7
         * Compute baud value based on requested baud rate and PCLK frequency.
         * The baud value is computed using the following equation:
         *      baud_value = PCLK_Frequency / (baud_rate * 16)
         */
        baud_value_by_128 = (8u * pclk_freq) / baudrate;
        baud_value_by_64 = baud_value_by_128 / 2u;
     b44:	0857      	lsrs	r7, r2, #1
        fractional_baud_value += (baud_value_by_128 - (baud_value * 128u)) - (fractional_baud_value * 2u);
        
        /* Assert if integer baud value fits in 16-bit. */
        ASSERT(baud_value <= UINT16_MAX);
    
        if(baud_value <= (uint32_t)UINT16_MAX)
     b46:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
     b4a:	bf28      	it	cs
     b4c:	6821      	ldrcs	r1, [r4, #0]
     b4e:	d2d5      	bcs.n	afc <global_init+0x1b8>
        {
            if(baud_value > 1u)
     b50:	2b01      	cmp	r3, #1
            {
                /* 
                 * Use Frational baud rate divisors
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
     b52:	6821      	ldr	r1, [r4, #0]
        /* Assert if integer baud value fits in 16-bit. */
        ASSERT(baud_value <= UINT16_MAX);
    
        if(baud_value <= (uint32_t)UINT16_MAX)
        {
            if(baud_value > 1u)
     b54:	d950      	bls.n	bf8 <global_init+0x2b4>
            {
                /* 
                 * Use Frational baud rate divisors
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
     b56:	f101 000c 	add.w	r0, r1, #12
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     b5a:	f020 4c7f 	bic.w	ip, r0, #4278190080	; 0xff000000
     b5e:	f000 4670 	and.w	r6, r0, #4026531840	; 0xf0000000
     b62:	f106 7000 	add.w	r0, r6, #33554432	; 0x2000000
     b66:	f42c 0a70 	bic.w	sl, ip, #15728640	; 0xf00000
     b6a:	ea4f 1e4a 	mov.w	lr, sl, lsl #5
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8);
                /* lsb of baud value */
                this_uart->hw_reg->DLR = (uint8_t)baud_value;
     b6e:	460d      	mov	r5, r1
     b70:	fa5f f883 	uxtb.w	r8, r3
         *      baud_value = PCLK_Frequency / (baud_rate * 16)
         */
        baud_value_by_128 = (8u * pclk_freq) / baudrate;
        baud_value_by_64 = baud_value_by_128 / 2u;
        baud_value = baud_value_by_64 / 64u;
        fractional_baud_value = baud_value_by_64 - (baud_value * 64u);
     b74:	eba7 1783 	sub.w	r7, r7, r3, lsl #6
     b78:	301c      	adds	r0, #28
     b7a:	2601      	movs	r6, #1
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8);
     b7c:	f3c2 3ac7 	ubfx	sl, r2, #15, #8
     b80:	f840 600e 	str.w	r6, [r0, lr]
         */
        baud_value_by_128 = (8u * pclk_freq) / baudrate;
        baud_value_by_64 = baud_value_by_128 / 2u;
        baud_value = baud_value_by_64 / 64u;
        fractional_baud_value = baud_value_by_64 - (baud_value * 64u);
        fractional_baud_value += (baud_value_by_128 - (baud_value * 128u)) - (fractional_baud_value * 2u);
     b84:	eba7 13c3 	sub.w	r3, r7, r3, lsl #7
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8);
     b88:	f881 a004 	strb.w	sl, [r1, #4]
                /* lsb of baud value */
                this_uart->hw_reg->DLR = (uint8_t)baud_value;
     b8c:	f805 8b30 	strb.w	r8, [r5], #48
         */
        baud_value_by_128 = (8u * pclk_freq) / baudrate;
        baud_value_by_64 = baud_value_by_128 / 2u;
        baud_value = baud_value_by_64 / 64u;
        fractional_baud_value = baud_value_by_64 - (baud_value * 64u);
        fractional_baud_value += (baud_value_by_128 - (baud_value * 128u)) - (fractional_baud_value * 2u);
     b90:	189a      	adds	r2, r3, r2
     b92:	f025 437f 	bic.w	r3, r5, #4278190080	; 0xff000000
     b96:	f005 4570 	and.w	r5, r5, #4026531840	; 0xf0000000
     b9a:	f423 0870 	bic.w	r8, r3, #15728640	; 0xf00000
                /* Enable Fractional baud rate */
                set_bit_reg8(&this_uart->hw_reg->MM0,EFBR);
        
                /* Load the fractional baud rate register */
                ASSERT(fractional_baud_value <= (uint32_t)UINT8_MAX);
                this_uart->hw_reg->DFR = (uint8_t)fractional_baud_value;
     b9e:	eba2 0747 	sub.w	r7, r2, r7, lsl #1
     ba2:	f105 7500 	add.w	r5, r5, #33554432	; 0x2000000
     ba6:	351c      	adds	r5, #28
     ba8:	ea4f 1848 	mov.w	r8, r8, lsl #5
     bac:	b2ff      	uxtb	r7, r7
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     bae:	2300      	movs	r3, #0
     bb0:	f840 300e 	str.w	r3, [r0, lr]
{
    HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x1;
     bb4:	f845 6008 	str.w	r6, [r5, r8]
     bb8:	f881 703c 	strb.w	r7, [r1, #60]	; 0x3c
     bbc:	e79e      	b.n	afc <global_init+0x1b8>
    if(this_uart == &g_mss_uart0)
    {
        this_uart->hw_reg = UART0;
        this_uart->irqn = UART0_IRQn;
        /* reset UART0 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART0_SOFTRESET_MASK;
     bbe:	f040 0780 	orr.w	r7, r0, #128	; 0x80
     bc2:	f2ce 0100 	movt	r1, #57344	; 0xe000
     bc6:	f44f 6680 	mov.w	r6, #1024	; 0x400
     bca:	6497      	str	r7, [r2, #72]	; 0x48
     bcc:	f8c1 6180 	str.w	r6, [r1, #384]	; 0x180
        /* Clear any previously pended UART0 interrupt */
        NVIC_ClearPendingIRQ(UART0_IRQn);
        /* Take UART0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
     bd0:	6c95      	ldr	r5, [r2, #72]	; 0x48
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
    {
        this_uart->hw_reg = UART0;
     bd2:	f04f 4180 	mov.w	r1, #1073741824	; 0x40000000
        /* reset UART0 */
        SYSREG->SOFT_RST_CR |= SYSREG_MMUART0_SOFTRESET_MASK;
        /* Clear any previously pended UART0 interrupt */
        NVIC_ClearPendingIRQ(UART0_IRQn);
        /* Take UART0 out of reset. */
        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
     bd6:	f025 0080 	bic.w	r0, r5, #128	; 0x80
     bda:	6490      	str	r0, [r2, #72]	; 0x48
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
    {
        this_uart->hw_reg = UART0;
        this_uart->irqn = UART0_IRQn;
     bdc:	220a      	movs	r2, #10
     bde:	7122      	strb	r2, [r4, #4]
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    if(this_uart == &g_mss_uart0)
    {
        this_uart->hw_reg = UART0;
     be0:	6021      	str	r1, [r4, #0]
     be2:	e6d7      	b.n	994 <global_init+0x50>
        uint32_t baud_value_by_64;
        uint32_t baud_value_by_128;
        uint32_t fractional_baud_value;
        uint32_t pclk_freq;

        this_uart->baudrate = baudrate;
     be4:	9a0d      	ldr	r2, [sp, #52]	; 0x34
     be6:	60a2      	str	r2, [r4, #8]

        /* Force the value of the CMSIS global variables holding the various system
          * clock frequencies to be updated. */
        SystemCoreClockUpdate();
     be8:	f000 f8c6 	bl	d78 <SystemCoreClockUpdate>
        if(this_uart == &g_mss_uart0)
        {
            pclk_freq = g_FrequencyPCLK0;
     bec:	f240 0114 	movw	r1, #20
     bf0:	f2c2 0100 	movt	r1, #8192	; 0x2000
     bf4:	680a      	ldr	r2, [r1, #0]
     bf6:	e7a0      	b.n	b3a <global_init+0x1f6>
            {
                /*
                 * Do NOT use Frational baud rate divisors.
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
     bf8:	f101 0c0c 	add.w	ip, r1, #12
     bfc:	f02c 4e7f 	bic.w	lr, ip, #4278190080	; 0xff000000
     c00:	f00c 4270 	and.w	r2, ip, #4026531840	; 0xf0000000
     c04:	f42e 0570 	bic.w	r5, lr, #15728640	; 0xf00000
     c08:	f102 7200 	add.w	r2, r2, #33554432	; 0x2000000
     c0c:	ea4f 1e45 	mov.w	lr, r5, lsl #5
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8u);
                /* lsb of baud value */
                this_uart->hw_reg->DLR = (uint8_t)baud_value;
     c10:	4608      	mov	r0, r1
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8u);
     c12:	2500      	movs	r5, #0
                /* lsb of baud value */
                this_uart->hw_reg->DLR = (uint8_t)baud_value;
     c14:	b2db      	uxtb	r3, r3
     c16:	321c      	adds	r2, #28
     c18:	2601      	movs	r6, #1
     c1a:	f842 600e 	str.w	r6, [r2, lr]
                 */
                /* set divisor latch */
                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
            
                /* msb of baud value */
                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8u);
     c1e:	710d      	strb	r5, [r1, #4]
                /* lsb of baud value */
                this_uart->hw_reg->DLR = (uint8_t)baud_value;
     c20:	f800 3b30 	strb.w	r3, [r0], #48
{
    HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
    HW_REG_BIT(reg,bit) = 0x0;
     c24:	f020 4c7f 	bic.w	ip, r0, #4278190080	; 0xff000000
     c28:	f000 4070 	and.w	r0, r0, #4026531840	; 0xf0000000
     c2c:	f100 7600 	add.w	r6, r0, #33554432	; 0x2000000
     c30:	f42c 0370 	bic.w	r3, ip, #15728640	; 0xf00000
     c34:	361c      	adds	r6, #28
     c36:	015b      	lsls	r3, r3, #5
     c38:	f842 500e 	str.w	r5, [r2, lr]
     c3c:	50f5      	str	r5, [r6, r3]
     c3e:	e75d      	b.n	afc <global_init+0x1b8>

00000c40 <MSS_UART_init>:
(
    mss_uart_instance_t* this_uart, 
    uint32_t baud_rate,
    uint8_t line_config
)
{
     c40:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
     c42:	4604      	mov	r4, r0
    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
     * mss_uart_instance_t instances used to identify UART0 and UART1. */
    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));

    /* Perform generic initialization */
    global_init(this_uart, baud_rate, line_config);
     c44:	f7ff fe7e 	bl	944 <global_init>

    /* Disable LIN mode */
    clear_bit_reg8(&this_uart->hw_reg->MM0, ELIN);
     c48:	6822      	ldr	r2, [r4, #0]
     c4a:	f64f 73ff 	movw	r3, #65535	; 0xffff

    /* Disable IrDA mode */
    clear_bit_reg8(&this_uart->hw_reg->MM1, EIRD);
     c4e:	f102 0034 	add.w	r0, r2, #52	; 0x34

    /* Perform generic initialization */
    global_init(this_uart, baud_rate, line_config);

    /* Disable LIN mode */
    clear_bit_reg8(&this_uart->hw_reg->MM0, ELIN);
     c52:	f102 0530 	add.w	r5, r2, #48	; 0x30
     c56:	f2c0 030f 	movt	r3, #15
     c5a:	f005 4770 	and.w	r7, r5, #4026531840	; 0xf0000000

    /* Disable IrDA mode */
    clear_bit_reg8(&this_uart->hw_reg->MM1, EIRD);

    /* Disable SmartCard Mode */
    clear_bit_reg8(&this_uart->hw_reg->MM2, EERR);
     c5e:	3238      	adds	r2, #56	; 0x38
     c60:	f000 4170 	and.w	r1, r0, #4026531840	; 0xf0000000

    /* set default tx handler for automated TX using interrupt in USART mode */
    this_uart->tx_handler = default_tx_handler;
     c64:	ea02 0603 	and.w	r6, r2, r3
     c68:	f107 7c00 	add.w	ip, r7, #33554432	; 0x2000000
     c6c:	401d      	ands	r5, r3
     c6e:	ea00 0703 	and.w	r7, r0, r3
     c72:	f002 4270 	and.w	r2, r2, #4026531840	; 0xf0000000
     c76:	f101 7100 	add.w	r1, r1, #33554432	; 0x2000000
     c7a:	f640 0085 	movw	r0, #2181	; 0x885
     c7e:	017b      	lsls	r3, r7, #5
     c80:	f10c 0c0c 	add.w	ip, ip, #12
     c84:	f102 7700 	add.w	r7, r2, #33554432	; 0x2000000
     c88:	016d      	lsls	r5, r5, #5
     c8a:	2200      	movs	r2, #0
     c8c:	3108      	adds	r1, #8
     c8e:	0176      	lsls	r6, r6, #5
     c90:	f2c0 0000 	movt	r0, #0
     c94:	f84c 2005 	str.w	r2, [ip, r5]
     c98:	6260      	str	r0, [r4, #36]	; 0x24
     c9a:	50ca      	str	r2, [r1, r3]
     c9c:	51ba      	str	r2, [r7, r6]
}
     c9e:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}

00000ca0 <MSS_GPIO_init>:
void MSS_GPIO_init( void )
{
    uint32_t inc;
    
    /* reset MSS GPIO hardware */
    SYSREG->SOFT_RST_CR |= SYSREG_GPIO_SOFTRESET_MASK;
     ca0:	f248 0200 	movw	r2, #32768	; 0x8000
     ca4:	f2c4 0203 	movt	r2, #16387	; 0x4003
/*-------------------------------------------------------------------------*//**
 * MSS_GPIO_init
 * See "mss_gpio.h" for details of how to use this function.
 */
void MSS_GPIO_init( void )
{
     ca8:	e92d 05f0 	stmdb	sp!, {r4, r5, r6, r7, r8, sl}
    uint32_t inc;
    
    /* reset MSS GPIO hardware */
    SYSREG->SOFT_RST_CR |= SYSREG_GPIO_SOFTRESET_MASK;
     cac:	6c94      	ldr	r4, [r2, #72]	; 0x48
     cae:	f241 06b4 	movw	r6, #4276	; 0x10b4
     cb2:	f444 1380 	orr.w	r3, r4, #1048576	; 0x100000
     cb6:	6493      	str	r3, [r2, #72]	; 0x48
    SYSREG->SOFT_RST_CR |= (SYSREG_GPIO_7_0_SOFTRESET_MASK |
     cb8:	6c90      	ldr	r0, [r2, #72]	; 0x48

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
     cba:	f24e 1300 	movw	r3, #57600	; 0xe100
     cbe:	f040 71f0 	orr.w	r1, r0, #31457280	; 0x1e00000
     cc2:	6491      	str	r1, [r2, #72]	; 0x48
     cc4:	f2c0 0600 	movt	r6, #0
     cc8:	f2ce 0300 	movt	r3, #57344	; 0xe000
     ccc:	2200      	movs	r2, #0
     cce:	2701      	movs	r7, #1
                            SYSREG_GPIO_15_8_SOFTRESET_MASK |
                            SYSREG_GPIO_23_16_SOFTRESET_MASK |
                            SYSREG_GPIO_31_24_SOFTRESET_MASK);
                            
    /* Clear any previously pended MSS GPIO interrupt */
    for(inc = 0U; inc < NB_OF_GPIO; ++inc)
     cd0:	1c55      	adds	r5, r2, #1
    {
        NVIC_DisableIRQ(g_gpio_irqn_lut[inc]);
     cd2:	5cb4      	ldrb	r4, [r6, r2]
     cd4:	f816 a005 	ldrb.w	sl, [r6, r5]
     cd8:	f004 001f 	and.w	r0, r4, #31
     cdc:	f00a 011f 	and.w	r1, sl, #31
     ce0:	fa17 f000 	lsls.w	r0, r7, r0
     ce4:	fa17 f101 	lsls.w	r1, r7, r1
     ce8:	fa4f f88a 	sxtb.w	r8, sl
     cec:	b262      	sxtb	r2, r4
     cee:	0954      	lsrs	r4, r2, #5
     cf0:	ea4f 1c58 	mov.w	ip, r8, lsr #5
                            SYSREG_GPIO_15_8_SOFTRESET_MASK |
                            SYSREG_GPIO_23_16_SOFTRESET_MASK |
                            SYSREG_GPIO_31_24_SOFTRESET_MASK);
                            
    /* Clear any previously pended MSS GPIO interrupt */
    for(inc = 0U; inc < NB_OF_GPIO; ++inc)
     cf4:	1c6a      	adds	r2, r5, #1

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
     cf6:	f104 0a60 	add.w	sl, r4, #96	; 0x60
     cfa:	f10c 0860 	add.w	r8, ip, #96	; 0x60

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
     cfe:	3420      	adds	r4, #32
     d00:	f10c 0c20 	add.w	ip, ip, #32
     d04:	2a20      	cmp	r2, #32
     d06:	f843 0024 	str.w	r0, [r3, r4, lsl #2]

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
     d0a:	f843 002a 	str.w	r0, [r3, sl, lsl #2]

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
     d0e:	f843 102c 	str.w	r1, [r3, ip, lsl #2]

    \param [in]      IRQn  External interrupt number. Value cannot be negative.
 */
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
     d12:	f843 1028 	str.w	r1, [r3, r8, lsl #2]
     d16:	d1db      	bne.n	cd0 <MSS_GPIO_init+0x30>
    {
        NVIC_DisableIRQ(g_gpio_irqn_lut[inc]);
        NVIC_ClearPendingIRQ(g_gpio_irqn_lut[inc]);
    }
    /* Take MSS GPIO hardware out of reset. */
    SYSREG->SOFT_RST_CR &= ~(SYSREG_GPIO_7_0_SOFTRESET_MASK |
     d18:	f248 0300 	movw	r3, #32768	; 0x8000
     d1c:	f2c4 0303 	movt	r3, #16387	; 0x4003
     d20:	6c9a      	ldr	r2, [r3, #72]	; 0x48
     d22:	f022 70f0 	bic.w	r0, r2, #31457280	; 0x1e00000
     d26:	6498      	str	r0, [r3, #72]	; 0x48
                             SYSREG_GPIO_15_8_SOFTRESET_MASK |
                             SYSREG_GPIO_23_16_SOFTRESET_MASK |
                             SYSREG_GPIO_31_24_SOFTRESET_MASK);
    SYSREG->SOFT_RST_CR &= ~SYSREG_GPIO_SOFTRESET_MASK;
     d28:	6c99      	ldr	r1, [r3, #72]	; 0x48
     d2a:	f421 1280 	bic.w	r2, r1, #1048576	; 0x100000
     d2e:	649a      	str	r2, [r3, #72]	; 0x48
}
     d30:	e8bd 05f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, sl}
     d34:	4770      	bx	lr
     d36:	bf00      	nop

00000d38 <MSS_GPIO_config>:
{
    uint32_t gpio_idx = (uint32_t)port_id;
    
    ASSERT(gpio_idx < NB_OF_GPIO);

    if(gpio_idx < NB_OF_GPIO)
     d38:	281f      	cmp	r0, #31
    {
        *(g_config_reg_lut[gpio_idx]) = config;
     d3a:	bf9f      	itttt	ls
     d3c:	f241 03d4 	movwls	r3, #4308	; 0x10d4
     d40:	f2c0 0300 	movtls	r3, #0
     d44:	f853 3020 	ldrls.w	r3, [r3, r0, lsl #2]
     d48:	6019      	strls	r1, [r3, #0]
     d4a:	4770      	bx	lr

00000d4c <MSS_GPIO_set_output>:
    uint32_t gpio_setting;
    uint32_t gpio_idx = (uint32_t)port_id;
    
    ASSERT(gpio_idx < NB_OF_GPIO);
    
    if(gpio_idx < NB_OF_GPIO)
     d4c:	281f      	cmp	r0, #31
     d4e:	d812      	bhi.n	d76 <MSS_GPIO_set_output+0x2a>
    {
        gpio_setting = GPIO->GPIO_OUT;
        gpio_setting &= ~((uint32_t)0x01u << gpio_idx);
     d50:	2201      	movs	r2, #1
     d52:	fa02 fc00 	lsl.w	ip, r2, r0
        gpio_setting |= ((uint32_t)value & 0x01u) << gpio_idx;
     d56:	f001 0301 	and.w	r3, r1, #1
     d5a:	fa13 f000 	lsls.w	r0, r3, r0
    
    ASSERT(gpio_idx < NB_OF_GPIO);
    
    if(gpio_idx < NB_OF_GPIO)
    {
        gpio_setting = GPIO->GPIO_OUT;
     d5e:	f243 0300 	movw	r3, #12288	; 0x3000
     d62:	f2c4 0301 	movt	r3, #16385	; 0x4001
     d66:	f8d3 2088 	ldr.w	r2, [r3, #136]	; 0x88
        gpio_setting &= ~((uint32_t)0x01u << gpio_idx);
     d6a:	ea22 010c 	bic.w	r1, r2, ip
        gpio_setting |= ((uint32_t)value & 0x01u) << gpio_idx;
     d6e:	ea41 0000 	orr.w	r0, r1, r0
        GPIO->GPIO_OUT = gpio_setting;
     d72:	f8c3 0088 	str.w	r0, [r3, #136]	; 0x88
     d76:	4770      	bx	lr

00000d78 <SystemCoreClockUpdate>:
#define FREQ_1MHZ    1000000u
#define FREQ_25MHZ   25000000u
#define FREQ_50MHZ   50000000u

void SystemCoreClockUpdate(void)
{
     d78:	e92d 01f0 	stmdb	sp!, {r4, r5, r6, r7, r8}
    uint32_t controller_pll_init;
    uint32_t clk_src;

    controller_pll_init = SYSREG->MSSDDR_FACC1_CR & CONTROLLER_PLL_INIT_MASK;
     d7c:	f248 0300 	movw	r3, #32768	; 0x8000
     d80:	f2c4 0303 	movt	r3, #16387	; 0x4003
     d84:	f8d3 2098 	ldr.w	r2, [r3, #152]	; 0x98
#define FREQ_1MHZ    1000000u
#define FREQ_25MHZ   25000000u
#define FREQ_50MHZ   50000000u

void SystemCoreClockUpdate(void)
{
     d88:	b083      	sub	sp, #12
    uint32_t controller_pll_init;
    uint32_t clk_src;

    controller_pll_init = SYSREG->MSSDDR_FACC1_CR & CONTROLLER_PLL_INIT_MASK;
    
    if(0u == controller_pll_init)
     d8a:	f012 6f80 	tst.w	r2, #67108864	; 0x4000000
     d8e:	d118      	bne.n	dc2 <SystemCoreClockUpdate+0x4a>
    {
        /* Normal operations. */
        uint32_t global_mux_sel;
        
        global_mux_sel = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK;
     d90:	f8d3 0098 	ldr.w	r0, [r3, #152]	; 0x98
        if(0u == global_mux_sel)
     d94:	f410 5f80 	tst.w	r0, #4096	; 0x1000
     d98:	d04d      	beq.n	e36 <SystemCoreClockUpdate+0xbe>
                                                   RCOSC_25_50MHZ_CLK_SRC,
                                                   CLK_XTAL_CLK_SRC,
                                                   RCOSC_1_MHZ_CLK_SRC,
                                                   RCOSC_1_MHZ_CLK_SRC,
                                                   CCC2ASCI_CLK_SRC,
                                                   CCC2ASCI_CLK_SRC };
     d9a:	f241 1154 	movw	r1, #4436	; 0x1154
     d9e:	f2c0 0100 	movt	r1, #0
     da2:	46ec      	mov	ip, sp
     da4:	c903      	ldmia	r1!, {r0, r1}
     da6:	e88c 0003 	stmia.w	ip, {r0, r1}
            
            uint32_t standby_sel;
            uint8_t clock_source;
            
            standby_sel = (SYSREG->MSSDDR_FACC2_CR >> FACC_STANDBY_SHIFT) & FACC_STANDBY_SEL_MASK;
     daa:	f8d3 209c 	ldr.w	r2, [r3, #156]	; 0x9c
            clock_source = standby_clock_lut[standby_sel];
            switch(clock_source)
     dae:	af02      	add	r7, sp, #8
     db0:	f3c2 1682 	ubfx	r6, r2, #6, #3
     db4:	19bd      	adds	r5, r7, r6
     db6:	f815 4c08 	ldrb.w	r4, [r5, #-8]
     dba:	2c01      	cmp	r4, #1
     dbc:	f000 8081 	beq.w	ec2 <SystemCoreClockUpdate+0x14a>
     dc0:	d26a      	bcs.n	e98 <SystemCoreClockUpdate+0x120>
static uint32_t get_rcosc_25_50mhz_frequency(void)
{
    uint32_t rcosc_div2;
    uint32_t rcosc_frequency;
    
    rcosc_div2 = SYSREG->MSSDDR_PLL_STATUS & RCOSC_DIV2_MASK;
     dc2:	f8d3 0150 	ldr.w	r0, [r3, #336]	; 0x150
    if(0u == rcosc_div2)
     dc6:	f647 0840 	movw	r8, #30784	; 0x7840
     dca:	f24f 0380 	movw	r3, #61568	; 0xf080
     dce:	f010 0f04 	tst.w	r0, #4
     dd2:	f2c0 187d 	movt	r8, #381	; 0x17d
     dd6:	f2c0 23fa 	movt	r3, #762	; 0x2fa
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     dda:	f240 051c 	movw	r5, #28
    g_FrequencyPCLK0 = standby_clk;
     dde:	f240 0414 	movw	r4, #20
    g_FrequencyPCLK1 = standby_clk;
     de2:	f240 0018 	movw	r0, #24
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     de6:	f240 0708 	movw	r7, #8
     dea:	f646 6c70 	movw	ip, #28272	; 0x6e70
    g_FrequencyFIC0 = standby_clk;
     dee:	f240 010c 	movw	r1, #12
    g_FrequencyFIC1 = standby_clk;
     df2:	f240 0210 	movw	r2, #16
    g_FrequencyFIC64 = standby_clk;
     df6:	f240 0604 	movw	r6, #4
{
    uint32_t rcosc_div2;
    uint32_t rcosc_frequency;
    
    rcosc_div2 = SYSREG->MSSDDR_PLL_STATUS & RCOSC_DIV2_MASK;
    if(0u == rcosc_div2)
     dfa:	bf08      	it	eq
     dfc:	4643      	moveq	r3, r8
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     dfe:	f2c2 0500 	movt	r5, #8192	; 0x2000
    g_FrequencyPCLK0 = standby_clk;
     e02:	f2c2 0400 	movt	r4, #8192	; 0x2000
    g_FrequencyPCLK1 = standby_clk;
     e06:	f2c2 0000 	movt	r0, #8192	; 0x2000
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     e0a:	f2c2 0700 	movt	r7, #8192	; 0x2000
     e0e:	f2c0 1ca7 	movt	ip, #423	; 0x1a7
    g_FrequencyFIC0 = standby_clk;
     e12:	f2c2 0100 	movt	r1, #8192	; 0x2000
    g_FrequencyFIC1 = standby_clk;
     e16:	f2c2 0200 	movt	r2, #8192	; 0x2000
    g_FrequencyFIC64 = standby_clk;
     e1a:	f2c2 0600 	movt	r6, #8192	; 0x2000
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
    g_FrequencyPCLK0 = standby_clk;
    g_FrequencyPCLK1 = standby_clk;
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     e1e:	f8c7 c000 	str.w	ip, [r7]
    g_FrequencyFIC0 = standby_clk;
    g_FrequencyFIC1 = standby_clk;
    g_FrequencyFIC64 = standby_clk;
     e22:	6033      	str	r3, [r6, #0]
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     e24:	602b      	str	r3, [r5, #0]
    g_FrequencyPCLK0 = standby_clk;
     e26:	6023      	str	r3, [r4, #0]
    g_FrequencyPCLK1 = standby_clk;
     e28:	6003      	str	r3, [r0, #0]
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
    g_FrequencyFIC0 = standby_clk;
     e2a:	600b      	str	r3, [r1, #0]
    g_FrequencyFIC1 = standby_clk;
     e2c:	6013      	str	r3, [r2, #0]
    {
        /* PLL initialization mode. Running from 25/50MHZ RC oscillator. */
        clk_src = get_rcosc_25_50mhz_frequency();
        set_clock_frequency_globals(clk_src);
    }
}
     e2e:	b003      	add	sp, #12
     e30:	e8bd 01f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8}
     e34:	4770      	bx	lr
        
        global_mux_sel = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK;
        if(0u == global_mux_sel)
        {
            /* MSS clocked from MSS PLL. Use Libero flow defines. */
            SystemCoreClock = MSS_SYS_M3_CLK_FREQ;
     e36:	f240 041c 	movw	r4, #28
     e3a:	f64b 13c0 	movw	r3, #47552	; 0xb9c0
            g_FrequencyPCLK0 = MSS_SYS_APB_0_CLK_FREQ;
     e3e:	f240 0014 	movw	r0, #20
            g_FrequencyPCLK1 = MSS_SYS_APB_1_CLK_FREQ;
     e42:	f240 0118 	movw	r1, #24
            g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     e46:	f240 0c08 	movw	ip, #8
     e4a:	f646 6870 	movw	r8, #28272	; 0x6e70
            g_FrequencyFIC0 = MSS_SYS_FIC_0_CLK_FREQ;
     e4e:	f240 020c 	movw	r2, #12
            g_FrequencyFIC1 = MSS_SYS_FIC_1_CLK_FREQ;
     e52:	f240 0710 	movw	r7, #16
            g_FrequencyFIC64 = MSS_SYS_FIC64_CLK_FREQ;
     e56:	f240 0504 	movw	r5, #4
     e5a:	f642 5640 	movw	r6, #11584	; 0x2d40
        
        global_mux_sel = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK;
        if(0u == global_mux_sel)
        {
            /* MSS clocked from MSS PLL. Use Libero flow defines. */
            SystemCoreClock = MSS_SYS_M3_CLK_FREQ;
     e5e:	f2c0 639d 	movt	r3, #1693	; 0x69d
     e62:	f2c2 0400 	movt	r4, #8192	; 0x2000
            g_FrequencyPCLK0 = MSS_SYS_APB_0_CLK_FREQ;
     e66:	f2c2 0000 	movt	r0, #8192	; 0x2000
            g_FrequencyPCLK1 = MSS_SYS_APB_1_CLK_FREQ;
     e6a:	f2c2 0100 	movt	r1, #8192	; 0x2000
            g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     e6e:	f2c2 0c00 	movt	ip, #8192	; 0x2000
     e72:	f2c0 18a7 	movt	r8, #423	; 0x1a7
            g_FrequencyFIC0 = MSS_SYS_FIC_0_CLK_FREQ;
     e76:	f2c2 0200 	movt	r2, #8192	; 0x2000
            g_FrequencyFIC1 = MSS_SYS_FIC_1_CLK_FREQ;
     e7a:	f2c2 0700 	movt	r7, #8192	; 0x2000
            g_FrequencyFIC64 = MSS_SYS_FIC64_CLK_FREQ;
     e7e:	f2c2 0500 	movt	r5, #8192	; 0x2000
     e82:	f2c1 36d9 	movt	r6, #5081	; 0x13d9
        {
            /* MSS clocked from MSS PLL. Use Libero flow defines. */
            SystemCoreClock = MSS_SYS_M3_CLK_FREQ;
            g_FrequencyPCLK0 = MSS_SYS_APB_0_CLK_FREQ;
            g_FrequencyPCLK1 = MSS_SYS_APB_1_CLK_FREQ;
            g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     e86:	f8cc 8000 	str.w	r8, [ip]
            g_FrequencyFIC0 = MSS_SYS_FIC_0_CLK_FREQ;
            g_FrequencyFIC1 = MSS_SYS_FIC_1_CLK_FREQ;
     e8a:	603b      	str	r3, [r7, #0]
            g_FrequencyFIC64 = MSS_SYS_FIC64_CLK_FREQ;
     e8c:	602e      	str	r6, [r5, #0]
        
        global_mux_sel = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK;
        if(0u == global_mux_sel)
        {
            /* MSS clocked from MSS PLL. Use Libero flow defines. */
            SystemCoreClock = MSS_SYS_M3_CLK_FREQ;
     e8e:	6023      	str	r3, [r4, #0]
            g_FrequencyPCLK0 = MSS_SYS_APB_0_CLK_FREQ;
     e90:	6003      	str	r3, [r0, #0]
            g_FrequencyPCLK1 = MSS_SYS_APB_1_CLK_FREQ;
     e92:	600b      	str	r3, [r1, #0]
            g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
            g_FrequencyFIC0 = MSS_SYS_FIC_0_CLK_FREQ;
     e94:	6013      	str	r3, [r2, #0]
     e96:	e7ca      	b.n	e2e <SystemCoreClockUpdate+0xb6>
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     e98:	f244 2340 	movw	r3, #16960	; 0x4240
     e9c:	f240 051c 	movw	r5, #28
    g_FrequencyPCLK0 = standby_clk;
     ea0:	f240 0414 	movw	r4, #20
    g_FrequencyPCLK1 = standby_clk;
     ea4:	f240 0018 	movw	r0, #24
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     ea8:	f240 0708 	movw	r7, #8
     eac:	f646 6c70 	movw	ip, #28272	; 0x6e70
    g_FrequencyFIC0 = standby_clk;
     eb0:	f240 010c 	movw	r1, #12
    g_FrequencyFIC1 = standby_clk;
     eb4:	f240 0210 	movw	r2, #16
    g_FrequencyFIC64 = standby_clk;
     eb8:	f240 0604 	movw	r6, #4
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     ebc:	f2c0 030f 	movt	r3, #15
     ec0:	e79d      	b.n	dfe <SystemCoreClockUpdate+0x86>
    g_FrequencyPCLK0 = standby_clk;
     ec2:	f240 051c 	movw	r5, #28
     ec6:	f240 0414 	movw	r4, #20
    g_FrequencyPCLK1 = standby_clk;
     eca:	f240 0018 	movw	r0, #24
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     ece:	f240 0708 	movw	r7, #8
     ed2:	f646 6c70 	movw	ip, #28272	; 0x6e70
    g_FrequencyFIC0 = standby_clk;
     ed6:	f240 010c 	movw	r1, #12
    g_FrequencyFIC1 = standby_clk;
     eda:	f240 0210 	movw	r2, #16
    g_FrequencyFIC64 = standby_clk;
     ede:	f240 0604 	movw	r6, #4
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     ee2:	f2c2 0500 	movt	r5, #8192	; 0x2000
    g_FrequencyPCLK0 = standby_clk;
     ee6:	f2c2 0400 	movt	r4, #8192	; 0x2000
    g_FrequencyPCLK1 = standby_clk;
     eea:	f2c2 0000 	movt	r0, #8192	; 0x2000
    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
     eee:	f2c2 0700 	movt	r7, #8192	; 0x2000
     ef2:	f2c0 1ca7 	movt	ip, #423	; 0x1a7
    g_FrequencyFIC0 = standby_clk;
     ef6:	f2c2 0100 	movt	r1, #8192	; 0x2000
    g_FrequencyFIC1 = standby_clk;
     efa:	f2c2 0200 	movt	r2, #8192	; 0x2000
    g_FrequencyFIC64 = standby_clk;
     efe:	f2c2 0600 	movt	r6, #8192	; 0x2000
        - g_FrequencyFIC1
        - g_FrequencyFIC64
 */
static void set_clock_frequency_globals(uint32_t standby_clk)
{
    SystemCoreClock = standby_clk;
     f02:	f44f 4300 	mov.w	r3, #32768	; 0x8000
     f06:	e78a      	b.n	e1e <SystemCoreClockUpdate+0xa6>

00000f08 <SystemInit>:
static uint32_t get_silicon_revision(void)
{
    uint32_t silicon_revision;
    uint32_t device_version;
    
    device_version = SYSREG->DEVICE_VERSION;
     f08:	f248 0300 	movw	r3, #32768	; 0x8000
     f0c:	f2c4 0303 	movt	r3, #16387	; 0x4003
     f10:	f8d3 114c 	ldr.w	r1, [r3, #332]	; 0x14c
    switch(device_version)
     f14:	f64f 0202 	movw	r2, #63490	; 0xf802
     f18:	4291      	cmp	r1, r2

/***************************************************************************//**
 * See system_m2sxxx.h for details.
 */
void SystemInit(void)
{
     f1a:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
{
    uint32_t silicon_revision;
    uint32_t device_version;
    
    device_version = SYSREG->DEVICE_VERSION;
    switch(device_version)
     f1e:	d10b      	bne.n	f38 <SystemInit+0x30>
{
    /*--------------------------------------------------------------------------
     * Work around a couple of silicon issues:
     */
    /* DDR_CLK_EN <- 1 */
    SYSREG->MSSDDR_FACC1_CR |= (uint32_t)1 << DDR_CLK_EN_SHIFT;
     f20:	f8d3 0098 	ldr.w	r0, [r3, #152]	; 0x98
     f24:	f440 7280 	orr.w	r2, r0, #256	; 0x100
     f28:	f8c3 2098 	str.w	r2, [r3, #152]	; 0x98
    
    /* CONTROLLER_PLL_INIT <- 0 */
    SYSREG->MSSDDR_FACC1_CR = SYSREG->MSSDDR_FACC1_CR & ~CONTROLLER_PLL_INIT_MASK;
     f2c:	f8d3 1098 	ldr.w	r1, [r3, #152]	; 0x98
     f30:	f021 6080 	bic.w	r0, r1, #67108864	; 0x4000000
     f34:	f8c3 0098 	str.w	r0, [r3, #152]	; 0x98
    /*--------------------------------------------------------------------------
     * Set STKALIGN to ensure exception stacking starts on 8 bytes address
     * boundary. This ensures compliance with the "Procedure Call Standards for
     * the ARM Architecture" (AAPCS).
     */
    SCB->CCR |= SCB_CCR_STKALIGN_Msk;
     f38:	f64e 5300 	movw	r3, #60672	; 0xed00
     f3c:	f2ce 0300 	movt	r3, #57344	; 0xe000
     f40:	6958      	ldr	r0, [r3, #20]
    
    /*--------------------------------------------------------------------------
     * MDDR configuration
     */
#if MSS_SYS_MDDR_CONFIG_BY_CORTEX
    if(0u == SYSREG->DDR_CR)
     f42:	f248 0200 	movw	r2, #32768	; 0x8000
    /*--------------------------------------------------------------------------
     * Set STKALIGN to ensure exception stacking starts on 8 bytes address
     * boundary. This ensures compliance with the "Procedure Call Standards for
     * the ARM Architecture" (AAPCS).
     */
    SCB->CCR |= SCB_CCR_STKALIGN_Msk;
     f46:	f440 7100 	orr.w	r1, r0, #512	; 0x200
     f4a:	6159      	str	r1, [r3, #20]
    
    /*--------------------------------------------------------------------------
     * MDDR configuration
     */
#if MSS_SYS_MDDR_CONFIG_BY_CORTEX
    if(0u == SYSREG->DDR_CR)
     f4c:	f2c4 0203 	movt	r2, #16387	; 0x4003
     f50:	6893      	ldr	r3, [r2, #8]
     f52:	2b00      	cmp	r3, #0
     f54:	d164      	bne.n	1020 <SystemInit+0x118>
         * to address 0x00000000. If MDDR is remapped to 0x00000000 then we are
         * probably executing this code from MDDR in a debugging session and
         * attempting to reconfigure the MDDR memory controller will cause the
         * Cortex-M3 to crash.
         */
        config_ddr_subsys(&g_m2s_mddr_subsys_config, &g_m2s_mddr_addr->core);
     f56:	f241 2468 	movw	r4, #4712	; 0x1268
     f5a:	f2c0 0400 	movt	r4, #0
     f5e:	6826      	ldr	r6, [r4, #0]
     f60:	f241 145c 	movw	r4, #4444	; 0x115c
     f64:	f2c0 0400 	movt	r4, #0
    
    /*--------------------------------------------------------------------------
     * Configure DDR controller part of the MDDR subsystem.
     */
    p_cfg = &p_ddr_subsys_cfg->ddrc.DYN_SOFT_RESET_CR;
    p_regs = &p_ddr_subsys_regs->ddrc.DYN_SOFT_RESET_CR;
     f68:	4632      	mov	r2, r6
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
    {
        p_regs[inc] = p_cfg[inc];
     f6a:	1c98      	adds	r0, r3, #2
     f6c:	1c81      	adds	r1, r0, #2
     f6e:	5b1f      	ldrh	r7, [r3, r4]
     f70:	5b00      	ldrh	r0, [r0, r4]
     f72:	5b0d      	ldrh	r5, [r1, r4]
     f74:	3306      	adds	r3, #6
     f76:	4611      	mov	r1, r2
     f78:	f841 7b04 	str.w	r7, [r1], #4
     f7c:	6050      	str	r0, [r2, #4]
     f7e:	320c      	adds	r2, #12
    uint32_t nb_16bit_words
)
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
     f80:	2b72      	cmp	r3, #114	; 0x72
    {
        p_regs[inc] = p_cfg[inc];
     f82:	604d      	str	r5, [r1, #4]
    uint32_t nb_16bit_words
)
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
     f84:	d1f1      	bne.n	f6a <SystemInit+0x62>
    
    /*--------------------------------------------------------------------------
     * Configure DDR PHY.
     */
    p_cfg = &p_ddr_subsys_cfg->phy.LOOPBACK_TEST_CR;
    p_regs = &p_ddr_subsys_regs->phy.LOOPBACK_TEST_CR;
     f86:	f241 125c 	movw	r2, #4444	; 0x115c
     f8a:	f2c0 0200 	movt	r2, #0
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
    {
        p_regs[inc] = p_cfg[inc];
     f8e:	f8b2 5072 	ldrh.w	r5, [r2, #114]	; 0x72
    
    /*--------------------------------------------------------------------------
     * Configure DDR PHY.
     */
    p_cfg = &p_ddr_subsys_cfg->phy.LOOPBACK_TEST_CR;
    p_regs = &p_ddr_subsys_regs->phy.LOOPBACK_TEST_CR;
     f92:	f506 7307 	add.w	r3, r6, #540	; 0x21c
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
    {
        p_regs[inc] = p_cfg[inc];
     f96:	601d      	str	r5, [r3, #0]
static void set_clock_frequency_globals(uint32_t fclk);

/***************************************************************************//**
 * See system_m2sxxx.h for details.
 */
void SystemInit(void)
     f98:	f102 0c82 	add.w	ip, r2, #130	; 0x82
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
    {
        p_regs[inc] = p_cfg[inc];
     f9c:	1c93      	adds	r3, r2, #2
     f9e:	f506 7108 	add.w	r1, r6, #544	; 0x220
     fa2:	1c98      	adds	r0, r3, #2
     fa4:	f8b3 5072 	ldrh.w	r5, [r3, #114]	; 0x72
     fa8:	460f      	mov	r7, r1
     faa:	f8b0 2072 	ldrh.w	r2, [r0, #114]	; 0x72
     fae:	f847 5b04 	str.w	r5, [r7], #4
     fb2:	1c83      	adds	r3, r0, #2
     fb4:	604a      	str	r2, [r1, #4]
     fb6:	1d39      	adds	r1, r7, #4
    uint32_t nb_16bit_words
)
{
    uint32_t inc;
    
    for(inc = 0u; inc < nb_16bit_words; ++inc)
     fb8:	4563      	cmp	r3, ip
     fba:	d1f2      	bne.n	fa2 <SystemInit+0x9a>
    p_ddr_subsys_regs->fic.HPD_SW_RW_EN_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_EN_CR;
    p_ddr_subsys_regs->fic.HPD_SW_RW_INVAL_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_INVAL_CR;
    p_ddr_subsys_regs->fic.SW_WR_ERCLR_CR = p_ddr_subsys_cfg->fic.SW_WR_ERCLR_CR;
    p_ddr_subsys_regs->fic.ERR_INT_ENABLE_CR = p_ddr_subsys_cfg->fic.ERR_INT_ENABLE_CR;
    p_ddr_subsys_regs->fic.NUM_AHB_MASTERS_CR = p_ddr_subsys_cfg->fic.NUM_AHB_MASTERS_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[0] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_1_CR;
     fbc:	f8b4 1104 	ldrh.w	r1, [r4, #260]	; 0x104
    copy_cfg16_to_regs(p_regs, p_cfg, NB_OF_DDR_PHY_REGS_TO_CONFIG);
    
    /*--------------------------------------------------------------------------
     * Configure DDR FIC.
     */
    p_ddr_subsys_regs->fic.NB_ADDR_CR = p_ddr_subsys_cfg->fic.NB_ADDR_CR;
     fc0:	f8b4 90f4 	ldrh.w	r9, [r4, #244]	; 0xf4
    p_ddr_subsys_regs->fic.NBRWB_SIZE_CR = p_ddr_subsys_cfg->fic.NBRWB_SIZE_CR;
     fc4:	f8b4 a0f6 	ldrh.w	sl, [r4, #246]	; 0xf6
    p_ddr_subsys_regs->fic.WB_TIMEOUT_CR = p_ddr_subsys_cfg->fic.WB_TIMEOUT_CR;
     fc8:	f8b4 80f8 	ldrh.w	r8, [r4, #248]	; 0xf8
    p_ddr_subsys_regs->fic.HPD_SW_RW_EN_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_EN_CR;
     fcc:	f8b4 e0fa 	ldrh.w	lr, [r4, #250]	; 0xfa
    p_ddr_subsys_regs->fic.HPD_SW_RW_INVAL_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_INVAL_CR;
     fd0:	f8b4 c0fc 	ldrh.w	ip, [r4, #252]	; 0xfc
    p_ddr_subsys_regs->fic.SW_WR_ERCLR_CR = p_ddr_subsys_cfg->fic.SW_WR_ERCLR_CR;
     fd4:	f8b4 70fe 	ldrh.w	r7, [r4, #254]	; 0xfe
    p_ddr_subsys_regs->fic.ERR_INT_ENABLE_CR = p_ddr_subsys_cfg->fic.ERR_INT_ENABLE_CR;
     fd8:	f8b4 5100 	ldrh.w	r5, [r4, #256]	; 0x100
    p_ddr_subsys_regs->fic.NUM_AHB_MASTERS_CR = p_ddr_subsys_cfg->fic.NUM_AHB_MASTERS_CR;
     fdc:	f8b4 0102 	ldrh.w	r0, [r4, #258]	; 0x102
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[0] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_1_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[1] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_2_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUT_EN_CR = p_ddr_subsys_cfg->fic.LOCK_TIMEOUT_EN_CR;
     fe0:	f8b4 3108 	ldrh.w	r3, [r4, #264]	; 0x108
    p_ddr_subsys_regs->fic.HPD_SW_RW_INVAL_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_INVAL_CR;
    p_ddr_subsys_regs->fic.SW_WR_ERCLR_CR = p_ddr_subsys_cfg->fic.SW_WR_ERCLR_CR;
    p_ddr_subsys_regs->fic.ERR_INT_ENABLE_CR = p_ddr_subsys_cfg->fic.ERR_INT_ENABLE_CR;
    p_ddr_subsys_regs->fic.NUM_AHB_MASTERS_CR = p_ddr_subsys_cfg->fic.NUM_AHB_MASTERS_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[0] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_1_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[1] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_2_CR;
     fe4:	f8b4 2106 	ldrh.w	r2, [r4, #262]	; 0x106
    copy_cfg16_to_regs(p_regs, p_cfg, NB_OF_DDR_PHY_REGS_TO_CONFIG);
    
    /*--------------------------------------------------------------------------
     * Configure DDR FIC.
     */
    p_ddr_subsys_regs->fic.NB_ADDR_CR = p_ddr_subsys_cfg->fic.NB_ADDR_CR;
     fe8:	f8c6 9400 	str.w	r9, [r6, #1024]	; 0x400
    p_ddr_subsys_regs->fic.NBRWB_SIZE_CR = p_ddr_subsys_cfg->fic.NBRWB_SIZE_CR;
     fec:	f8c6 a404 	str.w	sl, [r6, #1028]	; 0x404
    p_ddr_subsys_regs->fic.WB_TIMEOUT_CR = p_ddr_subsys_cfg->fic.WB_TIMEOUT_CR;
     ff0:	f8c6 8408 	str.w	r8, [r6, #1032]	; 0x408
    p_ddr_subsys_regs->fic.HPD_SW_RW_EN_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_EN_CR;
     ff4:	f8c6 e40c 	str.w	lr, [r6, #1036]	; 0x40c
    p_ddr_subsys_regs->fic.HPD_SW_RW_INVAL_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_INVAL_CR;
     ff8:	f8c6 c410 	str.w	ip, [r6, #1040]	; 0x410
    p_ddr_subsys_regs->fic.SW_WR_ERCLR_CR = p_ddr_subsys_cfg->fic.SW_WR_ERCLR_CR;
     ffc:	f8c6 7414 	str.w	r7, [r6, #1044]	; 0x414
    p_ddr_subsys_regs->fic.ERR_INT_ENABLE_CR = p_ddr_subsys_cfg->fic.ERR_INT_ENABLE_CR;
    1000:	f8c6 5418 	str.w	r5, [r6, #1048]	; 0x418
    p_ddr_subsys_regs->fic.NUM_AHB_MASTERS_CR = p_ddr_subsys_cfg->fic.NUM_AHB_MASTERS_CR;
    1004:	f8c6 041c 	str.w	r0, [r6, #1052]	; 0x41c
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[0] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_1_CR;
    1008:	f8c6 1440 	str.w	r1, [r6, #1088]	; 0x440
    p_ddr_subsys_regs->fic.LOCK_TIMEOUT_EN_CR = p_ddr_subsys_cfg->fic.LOCK_TIMEOUT_EN_CR;

    /*--------------------------------------------------------------------------
     * Enable DDR.
     */
    p_ddr_subsys_regs->ddrc.DYN_SOFT_RESET_CR = 0x01u;
    100c:	2101      	movs	r1, #1
    p_ddr_subsys_regs->fic.HPD_SW_RW_INVAL_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_INVAL_CR;
    p_ddr_subsys_regs->fic.SW_WR_ERCLR_CR = p_ddr_subsys_cfg->fic.SW_WR_ERCLR_CR;
    p_ddr_subsys_regs->fic.ERR_INT_ENABLE_CR = p_ddr_subsys_cfg->fic.ERR_INT_ENABLE_CR;
    p_ddr_subsys_regs->fic.NUM_AHB_MASTERS_CR = p_ddr_subsys_cfg->fic.NUM_AHB_MASTERS_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[0] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_1_CR;
    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[1] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_2_CR;
    100e:	f8c6 2444 	str.w	r2, [r6, #1092]	; 0x444
    p_ddr_subsys_regs->fic.LOCK_TIMEOUT_EN_CR = p_ddr_subsys_cfg->fic.LOCK_TIMEOUT_EN_CR;
    1012:	f8c6 3448 	str.w	r3, [r6, #1096]	; 0x448

    /*--------------------------------------------------------------------------
     * Enable DDR.
     */
    p_ddr_subsys_regs->ddrc.DYN_SOFT_RESET_CR = 0x01u;
    1016:	6031      	str	r1, [r6, #0]
    
    while(0x0000u == p_ddr_subsys_regs->ddrc.DDRC_SR)
    1018:	f8d6 30e4 	ldr.w	r3, [r6, #228]	; 0xe4
    101c:	2b00      	cmp	r3, #0
    101e:	d0fb      	beq.n	1018 <SystemInit+0x110>
#endif

    /*--------------------------------------------------------------------------
     * Call user defined configuration function.
     */
    mscc_post_hw_cfg_init();
    1020:	f7ff f9b6 	bl	390 <mscc_post_hw_cfg_init>
     * do this here because this signal is only deasserted by the System
     * Controller on a power-on reset. Other types of reset such as a watchdog
     * reset would result in the FPGA fabric being held in reset and getting
     * stuck waiting for the CoreSF2Config INIT_DONE to become asserted.
     */
    SYSREG->SOFT_RST_CR &= ~SYSREG_FPGA_SOFTRESET_MASK;
    1024:	f248 0200 	movw	r2, #32768	; 0x8000
    1028:	f2c4 0203 	movt	r2, #16387	; 0x4003
    102c:	6c93      	ldr	r3, [r2, #72]	; 0x48

    /*
     * Signal to CoreSF2Reset that peripheral configuration registers have been
     * written.
     */
    CORE_SF2_CFG->CONFIG_DONE |= (CONFIG_1_DONE | CONFIG_2_DONE);
    102e:	f242 0000 	movw	r0, #8192	; 0x2000
     * do this here because this signal is only deasserted by the System
     * Controller on a power-on reset. Other types of reset such as a watchdog
     * reset would result in the FPGA fabric being held in reset and getting
     * stuck waiting for the CoreSF2Config INIT_DONE to become asserted.
     */
    SYSREG->SOFT_RST_CR &= ~SYSREG_FPGA_SOFTRESET_MASK;
    1032:	f423 3180 	bic.w	r1, r3, #65536	; 0x10000
    1036:	6491      	str	r1, [r2, #72]	; 0x48

    /*
     * Signal to CoreSF2Reset that peripheral configuration registers have been
     * written.
     */
    CORE_SF2_CFG->CONFIG_DONE |= (CONFIG_1_DONE | CONFIG_2_DONE);
    1038:	f2c4 0002 	movt	r0, #16386	; 0x4002
    103c:	6803      	ldr	r3, [r0, #0]
     
    /* Wait for INIT_DONE from CoreSF2Reset. */
    do
    {
        init_done = CORE_SF2_CFG->INIT_DONE & INIT_DONE_MASK;
    103e:	4602      	mov	r2, r0

    /*
     * Signal to CoreSF2Reset that peripheral configuration registers have been
     * written.
     */
    CORE_SF2_CFG->CONFIG_DONE |= (CONFIG_1_DONE | CONFIG_2_DONE);
    1040:	f043 0103 	orr.w	r1, r3, #3
    1044:	6001      	str	r1, [r0, #0]
     
    /* Wait for INIT_DONE from CoreSF2Reset. */
    do
    {
        init_done = CORE_SF2_CFG->INIT_DONE & INIT_DONE_MASK;
    1046:	6850      	ldr	r0, [r2, #4]
    } while (0u == init_done);
    1048:	f010 0f01 	tst.w	r0, #1
    104c:	d0fb      	beq.n	1046 <SystemInit+0x13e>
#endif
}
    104e:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
    1052:	bf00      	nop

00001054 <__libc_init_array>:
    1054:	b570      	push	{r4, r5, r6, lr}
    1056:	f241 2684 	movw	r6, #4740	; 0x1284
    105a:	f241 2584 	movw	r5, #4740	; 0x1284
    105e:	f2c0 0600 	movt	r6, #0
    1062:	f2c0 0500 	movt	r5, #0
    1066:	1b76      	subs	r6, r6, r5
    1068:	10b6      	asrs	r6, r6, #2
    106a:	d006      	beq.n	107a <__libc_init_array+0x26>
    106c:	2400      	movs	r4, #0
    106e:	f855 3024 	ldr.w	r3, [r5, r4, lsl #2]
    1072:	3401      	adds	r4, #1
    1074:	4798      	blx	r3
    1076:	42a6      	cmp	r6, r4
    1078:	d8f9      	bhi.n	106e <__libc_init_array+0x1a>
    107a:	f241 2584 	movw	r5, #4740	; 0x1284
    107e:	f241 2688 	movw	r6, #4744	; 0x1288
    1082:	f2c0 0500 	movt	r5, #0
    1086:	f2c0 0600 	movt	r6, #0
    108a:	1b76      	subs	r6, r6, r5
    108c:	f000 f8ee 	bl	126c <_init>
    1090:	10b6      	asrs	r6, r6, #2
    1092:	d006      	beq.n	10a2 <__libc_init_array+0x4e>
    1094:	2400      	movs	r4, #0
    1096:	f855 3024 	ldr.w	r3, [r5, r4, lsl #2]
    109a:	3401      	adds	r4, #1
    109c:	4798      	blx	r3
    109e:	42a6      	cmp	r6, r4
    10a0:	d8f9      	bhi.n	1096 <__libc_init_array+0x42>
    10a2:	bd70      	pop	{r4, r5, r6, pc}
    10a4:	7344454c 	.word	0x7344454c
    10a8:	696c4220 	.word	0x696c4220
    10ac:	6e696b6e 	.word	0x6e696b6e
    10b0:	000d0a67 	.word	0x000d0a67

000010b4 <g_gpio_irqn_lut>:
    10b4:	35343332 39383736 3d3c3b3a 41403f3e     23456789:;<=>?@A
    10c4:	45444342 49484746 4d4c4b4a 51504f4e     BCDEFGHIJKLMNOPQ

000010d4 <g_config_reg_lut>:
    10d4:	40013000 40013004 40013008 4001300c     .0.@.0.@.0.@.0.@
    10e4:	40013010 40013014 40013018 4001301c     .0.@.0.@.0.@.0.@
    10f4:	40013020 40013024 40013028 4001302c      0.@$0.@(0.@,0.@
    1104:	40013030 40013034 40013038 4001303c     00.@40.@80.@<0.@
    1114:	40013040 40013044 40013048 4001304c     @0.@D0.@H0.@L0.@
    1124:	40013050 40013054 40013058 4001305c     P0.@T0.@X0.@\0.@
    1134:	40013060 40013064 40013068 4001306c     `0.@d0.@h0.@l0.@
    1144:	40013070 40013074 40013078 4001307c     p0.@t0.@x0.@|0.@

00001154 <C.17.3534>:
    1154:	01000100 03030202                       ........

0000115c <g_m2s_mddr_subsys_config>:
    115c:	00000000 030f27de 00000002 09990101     .....'..........
    116c:	33330000 8888ffff 00010888 00084242     ..33........BB..
    117c:	00000528 00000000 00860ce0 00640235     (...........5.d.
    118c:	0178010f 19370033 00000010 00003300     ..x.3.7......3..
    119c:	04060000 02000000 00120040 40000002     ........@......@
    11ac:	000780f8 000780f8 04000200 00050000     ................
    11bc:	00400003 00000000 00000000 00010309     ..@.............
    11cc:	00000000 00800000 00000000 00000003     ................
	...
    11e4:	0000000b 00000000 00800000 01002004     ............. ..
    11f4:	00000008 00000000 00000000 00000001     ................
	...
    120c:	05014050 00005014 00000000 00000000     P@...P..........
	...
    122c:	05010050 00005010 00000000 00000000     P....P..........
    123c:	00430000 00030000 00010001 00000000     ..C.............
    124c:	00010000 00000000 00000000 00000000     ................
	...

00001268 <g_m2s_mddr_addr>:
    1268:	40020800                                ...@

0000126c <_init>:
    126c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    126e:	bf00      	nop
    1270:	bcf8      	pop	{r3, r4, r5, r6, r7}
    1272:	bc08      	pop	{r3}
    1274:	469e      	mov	lr, r3
    1276:	4770      	bx	lr

00001278 <_fini>:
    1278:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
    127a:	bf00      	nop
    127c:	bcf8      	pop	{r3, r4, r5, r6, r7}
    127e:	bc08      	pop	{r3}
    1280:	469e      	mov	lr, r3
    1282:	4770      	bx	lr

00001284 <__frame_dummy_init_array_entry>:
    1284:	0425 0000                                   %...

00001288 <__do_global_dtors_aux_fini_array_entry>:
    1288:	0411 0000 0000 0000                         ........
