Project Settings
Project Name | eNVM_DataClient_top_syn | Implementation Name | synthesis
Top Module | eNVM_DataClient_top | Retiming | 0
Resource Sharing | 1 | Fanout Guide | 10000
Disable I/O Insertion | 0 | FSM Compiler | 1

Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
(compiler) | Complete | 38 | 48 | 0 | - | 0m:01s | - | 14-03-2016 10:33:09
(premap) | Complete | 30 | 4 | 0 | 0m:00s | 0m:00s | 137MB | 14-03-2016 10:33:11
(fpga_mapper) | Complete | 31 | 48 | 0 | 0m:01s | 0m:01s | 136MB | 14-03-2016 10:33:12
Multi-srs Generator | Complete |  |  |  | 0m:00s |  |  | 14-03-2016 10:33:10

Area Summary
Carry Cells | 14 | Sequential Cells | 124
DSP Blocks (MACC) (dsp_used) | 0 | I/O Cells | 51
Global Clock Buffers | 6 | LUTs (total_luts) | 74

Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
eNVM_DataClient_CCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | 499.9 MHz | 8.000
eNVM_DataClient_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | 100.0 MHz | 428.6 MHz | 7.667
eNVM_DataClient_MSS|FIC_2_APB_M_PCLK_inferred_clock | 100.0 MHz | 146.7 MHz | 1.835

Optimizations Summary
Combined Clock Conversion | 2 / 1 |  |