`timescale 1 ns/100 ps
// Version: v11.7 11.7.0.119


module RCOSC_25_50MHZ_FAB(
       A,
       CLKOUT
    );
input  A;
output CLKOUT;

    
endmodule


module RCOSC_25_50MHZ(
       CLKOUT
    );
output CLKOUT;

    parameter FREQUENCY = 50.0 ;
    
endmodule


module MSS_075(
       CAN_RXBUS_MGPIO3A_H2F_A,
       CAN_RXBUS_MGPIO3A_H2F_B,
       CAN_TX_EBL_MGPIO4A_H2F_A,
       CAN_TX_EBL_MGPIO4A_H2F_B,
       CAN_TXBUS_MGPIO2A_H2F_A,
       CAN_TXBUS_MGPIO2A_H2F_B,
       CLK_CONFIG_APB,
       COMMS_INT,
       CONFIG_PRESET_N,
       EDAC_ERROR,
       F_FM0_RDATA,
       F_FM0_READYOUT,
       F_FM0_RESP,
       F_HM0_ADDR,
       F_HM0_ENABLE,
       F_HM0_SEL,
       F_HM0_SIZE,
       F_HM0_TRANS1,
       F_HM0_WDATA,
       F_HM0_WRITE,
       FAB_CHRGVBUS,
       FAB_DISCHRGVBUS,
       FAB_DMPULLDOWN,
       FAB_DPPULLDOWN,
       FAB_DRVVBUS,
       FAB_IDPULLUP,
       FAB_OPMODE,
       FAB_SUSPENDM,
       FAB_TERMSEL,
       FAB_TXVALID,
       FAB_VCONTROL,
       FAB_VCONTROLLOADM,
       FAB_XCVRSEL,
       FAB_XDATAOUT,
       FACC_GLMUX_SEL,
       FIC32_0_MASTER,
       FIC32_1_MASTER,
       FPGA_RESET_N,
       GTX_CLK,
       H2F_INTERRUPT,
       H2F_NMI,
       H2FCALIB,
       I2C0_SCL_MGPIO31B_H2F_A,
       I2C0_SCL_MGPIO31B_H2F_B,
       I2C0_SDA_MGPIO30B_H2F_A,
       I2C0_SDA_MGPIO30B_H2F_B,
       I2C1_SCL_MGPIO1A_H2F_A,
       I2C1_SCL_MGPIO1A_H2F_B,
       I2C1_SDA_MGPIO0A_H2F_A,
       I2C1_SDA_MGPIO0A_H2F_B,
       MDCF,
       MDOENF,
       MDOF,
       MMUART0_CTS_MGPIO19B_H2F_A,
       MMUART0_CTS_MGPIO19B_H2F_B,
       MMUART0_DCD_MGPIO22B_H2F_A,
       MMUART0_DCD_MGPIO22B_H2F_B,
       MMUART0_DSR_MGPIO20B_H2F_A,
       MMUART0_DSR_MGPIO20B_H2F_B,
       MMUART0_DTR_MGPIO18B_H2F_A,
       MMUART0_DTR_MGPIO18B_H2F_B,
       MMUART0_RI_MGPIO21B_H2F_A,
       MMUART0_RI_MGPIO21B_H2F_B,
       MMUART0_RTS_MGPIO17B_H2F_A,
       MMUART0_RTS_MGPIO17B_H2F_B,
       MMUART0_RXD_MGPIO28B_H2F_A,
       MMUART0_RXD_MGPIO28B_H2F_B,
       MMUART0_SCK_MGPIO29B_H2F_A,
       MMUART0_SCK_MGPIO29B_H2F_B,
       MMUART0_TXD_MGPIO27B_H2F_A,
       MMUART0_TXD_MGPIO27B_H2F_B,
       MMUART1_DTR_MGPIO12B_H2F_A,
       MMUART1_RTS_MGPIO11B_H2F_A,
       MMUART1_RTS_MGPIO11B_H2F_B,
       MMUART1_RXD_MGPIO26B_H2F_A,
       MMUART1_RXD_MGPIO26B_H2F_B,
       MMUART1_SCK_MGPIO25B_H2F_A,
       MMUART1_SCK_MGPIO25B_H2F_B,
       MMUART1_TXD_MGPIO24B_H2F_A,
       MMUART1_TXD_MGPIO24B_H2F_B,
       MPLL_LOCK,
       PER2_FABRIC_PADDR,
       PER2_FABRIC_PENABLE,
       PER2_FABRIC_PSEL,
       PER2_FABRIC_PWDATA,
       PER2_FABRIC_PWRITE,
       RTC_MATCH,
       SLEEPDEEP,
       SLEEPHOLDACK,
       SLEEPING,
       SMBALERT_NO0,
       SMBALERT_NO1,
       SMBSUS_NO0,
       SMBSUS_NO1,
       SPI0_CLK_OUT,
       SPI0_SDI_MGPIO5A_H2F_A,
       SPI0_SDI_MGPIO5A_H2F_B,
       SPI0_SDO_MGPIO6A_H2F_A,
       SPI0_SDO_MGPIO6A_H2F_B,
       SPI0_SS0_MGPIO7A_H2F_A,
       SPI0_SS0_MGPIO7A_H2F_B,
       SPI0_SS1_MGPIO8A_H2F_A,
       SPI0_SS1_MGPIO8A_H2F_B,
       SPI0_SS2_MGPIO9A_H2F_A,
       SPI0_SS2_MGPIO9A_H2F_B,
       SPI0_SS3_MGPIO10A_H2F_A,
       SPI0_SS3_MGPIO10A_H2F_B,
       SPI0_SS4_MGPIO19A_H2F_A,
       SPI0_SS5_MGPIO20A_H2F_A,
       SPI0_SS6_MGPIO21A_H2F_A,
       SPI0_SS7_MGPIO22A_H2F_A,
       SPI1_CLK_OUT,
       SPI1_SDI_MGPIO11A_H2F_A,
       SPI1_SDI_MGPIO11A_H2F_B,
       SPI1_SDO_MGPIO12A_H2F_A,
       SPI1_SDO_MGPIO12A_H2F_B,
       SPI1_SS0_MGPIO13A_H2F_A,
       SPI1_SS0_MGPIO13A_H2F_B,
       SPI1_SS1_MGPIO14A_H2F_A,
       SPI1_SS1_MGPIO14A_H2F_B,
       SPI1_SS2_MGPIO15A_H2F_A,
       SPI1_SS2_MGPIO15A_H2F_B,
       SPI1_SS3_MGPIO16A_H2F_A,
       SPI1_SS3_MGPIO16A_H2F_B,
       SPI1_SS4_MGPIO17A_H2F_A,
       SPI1_SS5_MGPIO18A_H2F_A,
       SPI1_SS6_MGPIO23A_H2F_A,
       SPI1_SS7_MGPIO24A_H2F_A,
       TCGF,
       TRACECLK,
       TRACEDATA,
       TX_CLK,
       TX_ENF,
       TX_ERRF,
       TXCTL_EN_RIF,
       TXD_RIF,
       TXDF,
       TXEV,
       WDOGTIMEOUT,
       F_ARREADY_HREADYOUT1,
       F_AWREADY_HREADYOUT0,
       F_BID,
       F_BRESP_HRESP0,
       F_BVALID,
       F_RDATA_HRDATA01,
       F_RID,
       F_RLAST,
       F_RRESP_HRESP1,
       F_RVALID,
       F_WREADY,
       MDDR_FABRIC_PRDATA,
       MDDR_FABRIC_PREADY,
       MDDR_FABRIC_PSLVERR,
       CAN_RXBUS_F2H_SCP,
       CAN_TX_EBL_F2H_SCP,
       CAN_TXBUS_F2H_SCP,
       COLF,
       CRSF,
       F2_DMAREADY,
       F2H_INTERRUPT,
       F2HCALIB,
       F_DMAREADY,
       F_FM0_ADDR,
       F_FM0_ENABLE,
       F_FM0_MASTLOCK,
       F_FM0_READY,
       F_FM0_SEL,
       F_FM0_SIZE,
       F_FM0_TRANS1,
       F_FM0_WDATA,
       F_FM0_WRITE,
       F_HM0_RDATA,
       F_HM0_READY,
       F_HM0_RESP,
       FAB_AVALID,
       FAB_HOSTDISCON,
       FAB_IDDIG,
       FAB_LINESTATE,
       FAB_M3_RESET_N,
       FAB_PLL_LOCK,
       FAB_RXACTIVE,
       FAB_RXERROR,
       FAB_RXVALID,
       FAB_RXVALIDH,
       FAB_SESSEND,
       FAB_TXREADY,
       FAB_VBUSVALID,
       FAB_VSTATUS,
       FAB_XDATAIN,
       GTX_CLKPF,
       I2C0_BCLK,
       I2C0_SCL_F2H_SCP,
       I2C0_SDA_F2H_SCP,
       I2C1_BCLK,
       I2C1_SCL_F2H_SCP,
       I2C1_SDA_F2H_SCP,
       MDIF,
       MGPIO0A_F2H_GPIN,
       MGPIO10A_F2H_GPIN,
       MGPIO11A_F2H_GPIN,
       MGPIO11B_F2H_GPIN,
       MGPIO12A_F2H_GPIN,
       MGPIO13A_F2H_GPIN,
       MGPIO14A_F2H_GPIN,
       MGPIO15A_F2H_GPIN,
       MGPIO16A_F2H_GPIN,
       MGPIO17B_F2H_GPIN,
       MGPIO18B_F2H_GPIN,
       MGPIO19B_F2H_GPIN,
       MGPIO1A_F2H_GPIN,
       MGPIO20B_F2H_GPIN,
       MGPIO21B_F2H_GPIN,
       MGPIO22B_F2H_GPIN,
       MGPIO24B_F2H_GPIN,
       MGPIO25B_F2H_GPIN,
       MGPIO26B_F2H_GPIN,
       MGPIO27B_F2H_GPIN,
       MGPIO28B_F2H_GPIN,
       MGPIO29B_F2H_GPIN,
       MGPIO2A_F2H_GPIN,
       MGPIO30B_F2H_GPIN,
       MGPIO31B_F2H_GPIN,
       MGPIO3A_F2H_GPIN,
       MGPIO4A_F2H_GPIN,
       MGPIO5A_F2H_GPIN,
       MGPIO6A_F2H_GPIN,
       MGPIO7A_F2H_GPIN,
       MGPIO8A_F2H_GPIN,
       MGPIO9A_F2H_GPIN,
       MMUART0_CTS_F2H_SCP,
       MMUART0_DCD_F2H_SCP,
       MMUART0_DSR_F2H_SCP,
       MMUART0_DTR_F2H_SCP,
       MMUART0_RI_F2H_SCP,
       MMUART0_RTS_F2H_SCP,
       MMUART0_RXD_F2H_SCP,
       MMUART0_SCK_F2H_SCP,
       MMUART0_TXD_F2H_SCP,
       MMUART1_CTS_F2H_SCP,
       MMUART1_DCD_F2H_SCP,
       MMUART1_DSR_F2H_SCP,
       MMUART1_RI_F2H_SCP,
       MMUART1_RTS_F2H_SCP,
       MMUART1_RXD_F2H_SCP,
       MMUART1_SCK_F2H_SCP,
       MMUART1_TXD_F2H_SCP,
       PER2_FABRIC_PRDATA,
       PER2_FABRIC_PREADY,
       PER2_FABRIC_PSLVERR,
       RCGF,
       RX_CLKPF,
       RX_DVF,
       RX_ERRF,
       RX_EV,
       RXDF,
       SLEEPHOLDREQ,
       SMBALERT_NI0,
       SMBALERT_NI1,
       SMBSUS_NI0,
       SMBSUS_NI1,
       SPI0_CLK_IN,
       SPI0_SDI_F2H_SCP,
       SPI0_SDO_F2H_SCP,
       SPI0_SS0_F2H_SCP,
       SPI0_SS1_F2H_SCP,
       SPI0_SS2_F2H_SCP,
       SPI0_SS3_F2H_SCP,
       SPI1_CLK_IN,
       SPI1_SDI_F2H_SCP,
       SPI1_SDO_F2H_SCP,
       SPI1_SS0_F2H_SCP,
       SPI1_SS1_F2H_SCP,
       SPI1_SS2_F2H_SCP,
       SPI1_SS3_F2H_SCP,
       TX_CLKPF,
       USER_MSS_GPIO_RESET_N,
       USER_MSS_RESET_N,
       XCLK_FAB,
       CLK_BASE,
       CLK_MDDR_APB,
       F_ARADDR_HADDR1,
       F_ARBURST_HTRANS1,
       F_ARID_HSEL1,
       F_ARLEN_HBURST1,
       F_ARLOCK_HMASTLOCK1,
       F_ARSIZE_HSIZE1,
       F_ARVALID_HWRITE1,
       F_AWADDR_HADDR0,
       F_AWBURST_HTRANS0,
       F_AWID_HSEL0,
       F_AWLEN_HBURST0,
       F_AWLOCK_HMASTLOCK0,
       F_AWSIZE_HSIZE0,
       F_AWVALID_HWRITE0,
       F_BREADY,
       F_RMW_AXI,
       F_RREADY,
       F_WDATA_HWDATA01,
       F_WID_HREADY01,
       F_WLAST,
       F_WSTRB,
       F_WVALID,
       FPGA_MDDR_ARESET_N,
       MDDR_FABRIC_PADDR,
       MDDR_FABRIC_PENABLE,
       MDDR_FABRIC_PSEL,
       MDDR_FABRIC_PWDATA,
       MDDR_FABRIC_PWRITE,
       PRESET_N,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_IN,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_IN,
       DM_IN,
       DRAM_DQ_IN,
       DRAM_DQS_IN,
       DRAM_FIFO_WE_IN,
       I2C0_SCL_USBC_DATA1_MGPIO31B_IN,
       I2C0_SDA_USBC_DATA0_MGPIO30B_IN,
       I2C1_SCL_USBA_DATA4_MGPIO1A_IN,
       I2C1_SDA_USBA_DATA3_MGPIO0A_IN,
       MGPIO0B_IN,
       MGPIO10B_IN,
       MGPIO1B_IN,
       MGPIO25A_IN,
       MGPIO26A_IN,
       MGPIO27A_IN,
       MGPIO28A_IN,
       MGPIO29A_IN,
       MGPIO2B_IN,
       MGPIO30A_IN,
       MGPIO31A_IN,
       MGPIO3B_IN,
       MGPIO4B_IN,
       MGPIO5B_IN,
       MGPIO6B_IN,
       MGPIO7B_IN,
       MGPIO8B_IN,
       MGPIO9B_IN,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_IN,
       MMUART0_DCD_MGPIO22B_IN,
       MMUART0_DSR_MGPIO20B_IN,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_IN,
       MMUART0_RI_MGPIO21B_IN,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_IN,
       MMUART0_RXD_USBC_STP_MGPIO28B_IN,
       MMUART0_SCK_USBC_NXT_MGPIO29B_IN,
       MMUART0_TXD_USBC_DIR_MGPIO27B_IN,
       MMUART1_CTS_MGPIO13B_IN,
       MMUART1_DCD_MGPIO16B_IN,
       MMUART1_DSR_MGPIO14B_IN,
       MMUART1_DTR_MGPIO12B_IN,
       MMUART1_RI_MGPIO15B_IN,
       MMUART1_RTS_MGPIO11B_IN,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_IN,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_IN,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_IN,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN,
       RGMII_MDC_RMII_MDC_IN,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN,
       RGMII_RX_CLK_IN,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN,
       RGMII_RXD3_USBB_DATA4_IN,
       RGMII_TX_CLK_IN,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_IN,
       RGMII_TXD1_RMII_TXD1_USBB_STP_IN,
       RGMII_TXD2_USBB_DATA5_IN,
       RGMII_TXD3_USBB_DATA6_IN,
       SPI0_SCK_USBA_XCLK_IN,
       SPI0_SDI_USBA_DIR_MGPIO5A_IN,
       SPI0_SDO_USBA_STP_MGPIO6A_IN,
       SPI0_SS0_USBA_NXT_MGPIO7A_IN,
       SPI0_SS1_USBA_DATA5_MGPIO8A_IN,
       SPI0_SS2_USBA_DATA6_MGPIO9A_IN,
       SPI0_SS3_USBA_DATA7_MGPIO10A_IN,
       SPI0_SS4_MGPIO19A_IN,
       SPI0_SS5_MGPIO20A_IN,
       SPI0_SS6_MGPIO21A_IN,
       SPI0_SS7_MGPIO22A_IN,
       SPI1_SCK_IN,
       SPI1_SDI_MGPIO11A_IN,
       SPI1_SDO_MGPIO12A_IN,
       SPI1_SS0_MGPIO13A_IN,
       SPI1_SS1_MGPIO14A_IN,
       SPI1_SS2_MGPIO15A_IN,
       SPI1_SS3_MGPIO16A_IN,
       SPI1_SS4_MGPIO17A_IN,
       SPI1_SS5_MGPIO18A_IN,
       SPI1_SS6_MGPIO23A_IN,
       SPI1_SS7_MGPIO24A_IN,
       USBC_XCLK_IN,
       USBD_DATA0_IN,
       USBD_DATA1_IN,
       USBD_DATA2_IN,
       USBD_DATA3_IN,
       USBD_DATA4_IN,
       USBD_DATA5_IN,
       USBD_DATA6_IN,
       USBD_DATA7_MGPIO23B_IN,
       USBD_DIR_IN,
       USBD_NXT_IN,
       USBD_STP_IN,
       USBD_XCLK_IN,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT,
       DRAM_ADDR,
       DRAM_BA,
       DRAM_CASN,
       DRAM_CKE,
       DRAM_CLK,
       DRAM_CSN,
       DRAM_DM_RDQS_OUT,
       DRAM_DQ_OUT,
       DRAM_DQS_OUT,
       DRAM_FIFO_WE_OUT,
       DRAM_ODT,
       DRAM_RASN,
       DRAM_RSTN,
       DRAM_WEN,
       I2C0_SCL_USBC_DATA1_MGPIO31B_OUT,
       I2C0_SDA_USBC_DATA0_MGPIO30B_OUT,
       I2C1_SCL_USBA_DATA4_MGPIO1A_OUT,
       I2C1_SDA_USBA_DATA3_MGPIO0A_OUT,
       MGPIO0B_OUT,
       MGPIO10B_OUT,
       MGPIO1B_OUT,
       MGPIO25A_OUT,
       MGPIO26A_OUT,
       MGPIO27A_OUT,
       MGPIO28A_OUT,
       MGPIO29A_OUT,
       MGPIO2B_OUT,
       MGPIO30A_OUT,
       MGPIO31A_OUT,
       MGPIO3B_OUT,
       MGPIO4B_OUT,
       MGPIO5B_OUT,
       MGPIO6B_OUT,
       MGPIO7B_OUT,
       MGPIO8B_OUT,
       MGPIO9B_OUT,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT,
       MMUART0_DCD_MGPIO22B_OUT,
       MMUART0_DSR_MGPIO20B_OUT,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT,
       MMUART0_RI_MGPIO21B_OUT,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT,
       MMUART0_RXD_USBC_STP_MGPIO28B_OUT,
       MMUART0_SCK_USBC_NXT_MGPIO29B_OUT,
       MMUART0_TXD_USBC_DIR_MGPIO27B_OUT,
       MMUART1_CTS_MGPIO13B_OUT,
       MMUART1_DCD_MGPIO16B_OUT,
       MMUART1_DSR_MGPIO14B_OUT,
       MMUART1_DTR_MGPIO12B_OUT,
       MMUART1_RI_MGPIO15B_OUT,
       MMUART1_RTS_MGPIO11B_OUT,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT,
       RGMII_MDC_RMII_MDC_OUT,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT,
       RGMII_RX_CLK_OUT,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT,
       RGMII_RXD3_USBB_DATA4_OUT,
       RGMII_TX_CLK_OUT,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT,
       RGMII_TXD1_RMII_TXD1_USBB_STP_OUT,
       RGMII_TXD2_USBB_DATA5_OUT,
       RGMII_TXD3_USBB_DATA6_OUT,
       SPI0_SCK_USBA_XCLK_OUT,
       SPI0_SDI_USBA_DIR_MGPIO5A_OUT,
       SPI0_SDO_USBA_STP_MGPIO6A_OUT,
       SPI0_SS0_USBA_NXT_MGPIO7A_OUT,
       SPI0_SS1_USBA_DATA5_MGPIO8A_OUT,
       SPI0_SS2_USBA_DATA6_MGPIO9A_OUT,
       SPI0_SS3_USBA_DATA7_MGPIO10A_OUT,
       SPI0_SS4_MGPIO19A_OUT,
       SPI0_SS5_MGPIO20A_OUT,
       SPI0_SS6_MGPIO21A_OUT,
       SPI0_SS7_MGPIO22A_OUT,
       SPI1_SCK_OUT,
       SPI1_SDI_MGPIO11A_OUT,
       SPI1_SDO_MGPIO12A_OUT,
       SPI1_SS0_MGPIO13A_OUT,
       SPI1_SS1_MGPIO14A_OUT,
       SPI1_SS2_MGPIO15A_OUT,
       SPI1_SS3_MGPIO16A_OUT,
       SPI1_SS4_MGPIO17A_OUT,
       SPI1_SS5_MGPIO18A_OUT,
       SPI1_SS6_MGPIO23A_OUT,
       SPI1_SS7_MGPIO24A_OUT,
       USBC_XCLK_OUT,
       USBD_DATA0_OUT,
       USBD_DATA1_OUT,
       USBD_DATA2_OUT,
       USBD_DATA3_OUT,
       USBD_DATA4_OUT,
       USBD_DATA5_OUT,
       USBD_DATA6_OUT,
       USBD_DATA7_MGPIO23B_OUT,
       USBD_DIR_OUT,
       USBD_NXT_OUT,
       USBD_STP_OUT,
       USBD_XCLK_OUT,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_OE,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_OE,
       DM_OE,
       DRAM_DQ_OE,
       DRAM_DQS_OE,
       I2C0_SCL_USBC_DATA1_MGPIO31B_OE,
       I2C0_SDA_USBC_DATA0_MGPIO30B_OE,
       I2C1_SCL_USBA_DATA4_MGPIO1A_OE,
       I2C1_SDA_USBA_DATA3_MGPIO0A_OE,
       MGPIO0B_OE,
       MGPIO10B_OE,
       MGPIO1B_OE,
       MGPIO25A_OE,
       MGPIO26A_OE,
       MGPIO27A_OE,
       MGPIO28A_OE,
       MGPIO29A_OE,
       MGPIO2B_OE,
       MGPIO30A_OE,
       MGPIO31A_OE,
       MGPIO3B_OE,
       MGPIO4B_OE,
       MGPIO5B_OE,
       MGPIO6B_OE,
       MGPIO7B_OE,
       MGPIO8B_OE,
       MGPIO9B_OE,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_OE,
       MMUART0_DCD_MGPIO22B_OE,
       MMUART0_DSR_MGPIO20B_OE,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_OE,
       MMUART0_RI_MGPIO21B_OE,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_OE,
       MMUART0_RXD_USBC_STP_MGPIO28B_OE,
       MMUART0_SCK_USBC_NXT_MGPIO29B_OE,
       MMUART0_TXD_USBC_DIR_MGPIO27B_OE,
       MMUART1_CTS_MGPIO13B_OE,
       MMUART1_DCD_MGPIO16B_OE,
       MMUART1_DSR_MGPIO14B_OE,
       MMUART1_DTR_MGPIO12B_OE,
       MMUART1_RI_MGPIO15B_OE,
       MMUART1_RTS_MGPIO11B_OE,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_OE,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_OE,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_OE,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE,
       RGMII_MDC_RMII_MDC_OE,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE,
       RGMII_RX_CLK_OE,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE,
       RGMII_RXD3_USBB_DATA4_OE,
       RGMII_TX_CLK_OE,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_OE,
       RGMII_TXD1_RMII_TXD1_USBB_STP_OE,
       RGMII_TXD2_USBB_DATA5_OE,
       RGMII_TXD3_USBB_DATA6_OE,
       SPI0_SCK_USBA_XCLK_OE,
       SPI0_SDI_USBA_DIR_MGPIO5A_OE,
       SPI0_SDO_USBA_STP_MGPIO6A_OE,
       SPI0_SS0_USBA_NXT_MGPIO7A_OE,
       SPI0_SS1_USBA_DATA5_MGPIO8A_OE,
       SPI0_SS2_USBA_DATA6_MGPIO9A_OE,
       SPI0_SS3_USBA_DATA7_MGPIO10A_OE,
       SPI0_SS4_MGPIO19A_OE,
       SPI0_SS5_MGPIO20A_OE,
       SPI0_SS6_MGPIO21A_OE,
       SPI0_SS7_MGPIO22A_OE,
       SPI1_SCK_OE,
       SPI1_SDI_MGPIO11A_OE,
       SPI1_SDO_MGPIO12A_OE,
       SPI1_SS0_MGPIO13A_OE,
       SPI1_SS1_MGPIO14A_OE,
       SPI1_SS2_MGPIO15A_OE,
       SPI1_SS3_MGPIO16A_OE,
       SPI1_SS4_MGPIO17A_OE,
       SPI1_SS5_MGPIO18A_OE,
       SPI1_SS6_MGPIO23A_OE,
       SPI1_SS7_MGPIO24A_OE,
       USBC_XCLK_OE,
       USBD_DATA0_OE,
       USBD_DATA1_OE,
       USBD_DATA2_OE,
       USBD_DATA3_OE,
       USBD_DATA4_OE,
       USBD_DATA5_OE,
       USBD_DATA6_OE,
       USBD_DATA7_MGPIO23B_OE,
       USBD_DIR_OE,
       USBD_NXT_OE,
       USBD_STP_OE,
       USBD_XCLK_OE
    );
output CAN_RXBUS_MGPIO3A_H2F_A;
output CAN_RXBUS_MGPIO3A_H2F_B;
output CAN_TX_EBL_MGPIO4A_H2F_A;
output CAN_TX_EBL_MGPIO4A_H2F_B;
output CAN_TXBUS_MGPIO2A_H2F_A;
output CAN_TXBUS_MGPIO2A_H2F_B;
output CLK_CONFIG_APB;
output COMMS_INT;
output CONFIG_PRESET_N;
output [7:0] EDAC_ERROR;
output [31:0] F_FM0_RDATA;
output F_FM0_READYOUT;
output F_FM0_RESP;
output [31:0] F_HM0_ADDR;
output F_HM0_ENABLE;
output F_HM0_SEL;
output [1:0] F_HM0_SIZE;
output F_HM0_TRANS1;
output [31:0] F_HM0_WDATA;
output F_HM0_WRITE;
output FAB_CHRGVBUS;
output FAB_DISCHRGVBUS;
output FAB_DMPULLDOWN;
output FAB_DPPULLDOWN;
output FAB_DRVVBUS;
output FAB_IDPULLUP;
output [1:0] FAB_OPMODE;
output FAB_SUSPENDM;
output FAB_TERMSEL;
output FAB_TXVALID;
output [3:0] FAB_VCONTROL;
output FAB_VCONTROLLOADM;
output [1:0] FAB_XCVRSEL;
output [7:0] FAB_XDATAOUT;
output FACC_GLMUX_SEL;
output [1:0] FIC32_0_MASTER;
output [1:0] FIC32_1_MASTER;
output FPGA_RESET_N;
output GTX_CLK;
output [15:0] H2F_INTERRUPT;
output H2F_NMI;
output H2FCALIB;
output I2C0_SCL_MGPIO31B_H2F_A;
output I2C0_SCL_MGPIO31B_H2F_B;
output I2C0_SDA_MGPIO30B_H2F_A;
output I2C0_SDA_MGPIO30B_H2F_B;
output I2C1_SCL_MGPIO1A_H2F_A;
output I2C1_SCL_MGPIO1A_H2F_B;
output I2C1_SDA_MGPIO0A_H2F_A;
output I2C1_SDA_MGPIO0A_H2F_B;
output MDCF;
output MDOENF;
output MDOF;
output MMUART0_CTS_MGPIO19B_H2F_A;
output MMUART0_CTS_MGPIO19B_H2F_B;
output MMUART0_DCD_MGPIO22B_H2F_A;
output MMUART0_DCD_MGPIO22B_H2F_B;
output MMUART0_DSR_MGPIO20B_H2F_A;
output MMUART0_DSR_MGPIO20B_H2F_B;
output MMUART0_DTR_MGPIO18B_H2F_A;
output MMUART0_DTR_MGPIO18B_H2F_B;
output MMUART0_RI_MGPIO21B_H2F_A;
output MMUART0_RI_MGPIO21B_H2F_B;
output MMUART0_RTS_MGPIO17B_H2F_A;
output MMUART0_RTS_MGPIO17B_H2F_B;
output MMUART0_RXD_MGPIO28B_H2F_A;
output MMUART0_RXD_MGPIO28B_H2F_B;
output MMUART0_SCK_MGPIO29B_H2F_A;
output MMUART0_SCK_MGPIO29B_H2F_B;
output MMUART0_TXD_MGPIO27B_H2F_A;
output MMUART0_TXD_MGPIO27B_H2F_B;
output MMUART1_DTR_MGPIO12B_H2F_A;
output MMUART1_RTS_MGPIO11B_H2F_A;
output MMUART1_RTS_MGPIO11B_H2F_B;
output MMUART1_RXD_MGPIO26B_H2F_A;
output MMUART1_RXD_MGPIO26B_H2F_B;
output MMUART1_SCK_MGPIO25B_H2F_A;
output MMUART1_SCK_MGPIO25B_H2F_B;
output MMUART1_TXD_MGPIO24B_H2F_A;
output MMUART1_TXD_MGPIO24B_H2F_B;
output MPLL_LOCK;
output [15:2] PER2_FABRIC_PADDR;
output PER2_FABRIC_PENABLE;
output PER2_FABRIC_PSEL;
output [31:0] PER2_FABRIC_PWDATA;
output PER2_FABRIC_PWRITE;
output RTC_MATCH;
output SLEEPDEEP;
output SLEEPHOLDACK;
output SLEEPING;
output SMBALERT_NO0;
output SMBALERT_NO1;
output SMBSUS_NO0;
output SMBSUS_NO1;
output SPI0_CLK_OUT;
output SPI0_SDI_MGPIO5A_H2F_A;
output SPI0_SDI_MGPIO5A_H2F_B;
output SPI0_SDO_MGPIO6A_H2F_A;
output SPI0_SDO_MGPIO6A_H2F_B;
output SPI0_SS0_MGPIO7A_H2F_A;
output SPI0_SS0_MGPIO7A_H2F_B;
output SPI0_SS1_MGPIO8A_H2F_A;
output SPI0_SS1_MGPIO8A_H2F_B;
output SPI0_SS2_MGPIO9A_H2F_A;
output SPI0_SS2_MGPIO9A_H2F_B;
output SPI0_SS3_MGPIO10A_H2F_A;
output SPI0_SS3_MGPIO10A_H2F_B;
output SPI0_SS4_MGPIO19A_H2F_A;
output SPI0_SS5_MGPIO20A_H2F_A;
output SPI0_SS6_MGPIO21A_H2F_A;
output SPI0_SS7_MGPIO22A_H2F_A;
output SPI1_CLK_OUT;
output SPI1_SDI_MGPIO11A_H2F_A;
output SPI1_SDI_MGPIO11A_H2F_B;
output SPI1_SDO_MGPIO12A_H2F_A;
output SPI1_SDO_MGPIO12A_H2F_B;
output SPI1_SS0_MGPIO13A_H2F_A;
output SPI1_SS0_MGPIO13A_H2F_B;
output SPI1_SS1_MGPIO14A_H2F_A;
output SPI1_SS1_MGPIO14A_H2F_B;
output SPI1_SS2_MGPIO15A_H2F_A;
output SPI1_SS2_MGPIO15A_H2F_B;
output SPI1_SS3_MGPIO16A_H2F_A;
output SPI1_SS3_MGPIO16A_H2F_B;
output SPI1_SS4_MGPIO17A_H2F_A;
output SPI1_SS5_MGPIO18A_H2F_A;
output SPI1_SS6_MGPIO23A_H2F_A;
output SPI1_SS7_MGPIO24A_H2F_A;
output [9:0] TCGF;
output TRACECLK;
output [3:0] TRACEDATA;
output TX_CLK;
output TX_ENF;
output TX_ERRF;
output TXCTL_EN_RIF;
output [3:0] TXD_RIF;
output [7:0] TXDF;
output TXEV;
output WDOGTIMEOUT;
output F_ARREADY_HREADYOUT1;
output F_AWREADY_HREADYOUT0;
output [3:0] F_BID;
output [1:0] F_BRESP_HRESP0;
output F_BVALID;
output [63:0] F_RDATA_HRDATA01;
output [3:0] F_RID;
output F_RLAST;
output [1:0] F_RRESP_HRESP1;
output F_RVALID;
output F_WREADY;
output [15:0] MDDR_FABRIC_PRDATA;
output MDDR_FABRIC_PREADY;
output MDDR_FABRIC_PSLVERR;
input  CAN_RXBUS_F2H_SCP;
input  CAN_TX_EBL_F2H_SCP;
input  CAN_TXBUS_F2H_SCP;
input  COLF;
input  CRSF;
input  [1:0] F2_DMAREADY;
input  [15:0] F2H_INTERRUPT;
input  F2HCALIB;
input  [1:0] F_DMAREADY;
input  [31:0] F_FM0_ADDR;
input  F_FM0_ENABLE;
input  F_FM0_MASTLOCK;
input  F_FM0_READY;
input  F_FM0_SEL;
input  [1:0] F_FM0_SIZE;
input  F_FM0_TRANS1;
input  [31:0] F_FM0_WDATA;
input  F_FM0_WRITE;
input  [31:0] F_HM0_RDATA;
input  F_HM0_READY;
input  F_HM0_RESP;
input  FAB_AVALID;
input  FAB_HOSTDISCON;
input  FAB_IDDIG;
input  [1:0] FAB_LINESTATE;
input  FAB_M3_RESET_N;
input  FAB_PLL_LOCK;
input  FAB_RXACTIVE;
input  FAB_RXERROR;
input  FAB_RXVALID;
input  FAB_RXVALIDH;
input  FAB_SESSEND;
input  FAB_TXREADY;
input  FAB_VBUSVALID;
input  [7:0] FAB_VSTATUS;
input  [7:0] FAB_XDATAIN;
input  GTX_CLKPF;
input  I2C0_BCLK;
input  I2C0_SCL_F2H_SCP;
input  I2C0_SDA_F2H_SCP;
input  I2C1_BCLK;
input  I2C1_SCL_F2H_SCP;
input  I2C1_SDA_F2H_SCP;
input  MDIF;
input  MGPIO0A_F2H_GPIN;
input  MGPIO10A_F2H_GPIN;
input  MGPIO11A_F2H_GPIN;
input  MGPIO11B_F2H_GPIN;
input  MGPIO12A_F2H_GPIN;
input  MGPIO13A_F2H_GPIN;
input  MGPIO14A_F2H_GPIN;
input  MGPIO15A_F2H_GPIN;
input  MGPIO16A_F2H_GPIN;
input  MGPIO17B_F2H_GPIN;
input  MGPIO18B_F2H_GPIN;
input  MGPIO19B_F2H_GPIN;
input  MGPIO1A_F2H_GPIN;
input  MGPIO20B_F2H_GPIN;
input  MGPIO21B_F2H_GPIN;
input  MGPIO22B_F2H_GPIN;
input  MGPIO24B_F2H_GPIN;
input  MGPIO25B_F2H_GPIN;
input  MGPIO26B_F2H_GPIN;
input  MGPIO27B_F2H_GPIN;
input  MGPIO28B_F2H_GPIN;
input  MGPIO29B_F2H_GPIN;
input  MGPIO2A_F2H_GPIN;
input  MGPIO30B_F2H_GPIN;
input  MGPIO31B_F2H_GPIN;
input  MGPIO3A_F2H_GPIN;
input  MGPIO4A_F2H_GPIN;
input  MGPIO5A_F2H_GPIN;
input  MGPIO6A_F2H_GPIN;
input  MGPIO7A_F2H_GPIN;
input  MGPIO8A_F2H_GPIN;
input  MGPIO9A_F2H_GPIN;
input  MMUART0_CTS_F2H_SCP;
input  MMUART0_DCD_F2H_SCP;
input  MMUART0_DSR_F2H_SCP;
input  MMUART0_DTR_F2H_SCP;
input  MMUART0_RI_F2H_SCP;
input  MMUART0_RTS_F2H_SCP;
input  MMUART0_RXD_F2H_SCP;
input  MMUART0_SCK_F2H_SCP;
input  MMUART0_TXD_F2H_SCP;
input  MMUART1_CTS_F2H_SCP;
input  MMUART1_DCD_F2H_SCP;
input  MMUART1_DSR_F2H_SCP;
input  MMUART1_RI_F2H_SCP;
input  MMUART1_RTS_F2H_SCP;
input  MMUART1_RXD_F2H_SCP;
input  MMUART1_SCK_F2H_SCP;
input  MMUART1_TXD_F2H_SCP;
input  [31:0] PER2_FABRIC_PRDATA;
input  PER2_FABRIC_PREADY;
input  PER2_FABRIC_PSLVERR;
input  [9:0] RCGF;
input  RX_CLKPF;
input  RX_DVF;
input  RX_ERRF;
input  RX_EV;
input  [7:0] RXDF;
input  SLEEPHOLDREQ;
input  SMBALERT_NI0;
input  SMBALERT_NI1;
input  SMBSUS_NI0;
input  SMBSUS_NI1;
input  SPI0_CLK_IN;
input  SPI0_SDI_F2H_SCP;
input  SPI0_SDO_F2H_SCP;
input  SPI0_SS0_F2H_SCP;
input  SPI0_SS1_F2H_SCP;
input  SPI0_SS2_F2H_SCP;
input  SPI0_SS3_F2H_SCP;
input  SPI1_CLK_IN;
input  SPI1_SDI_F2H_SCP;
input  SPI1_SDO_F2H_SCP;
input  SPI1_SS0_F2H_SCP;
input  SPI1_SS1_F2H_SCP;
input  SPI1_SS2_F2H_SCP;
input  SPI1_SS3_F2H_SCP;
input  TX_CLKPF;
input  USER_MSS_GPIO_RESET_N;
input  USER_MSS_RESET_N;
input  XCLK_FAB;
input  CLK_BASE;
input  CLK_MDDR_APB;
input  [31:0] F_ARADDR_HADDR1;
input  [1:0] F_ARBURST_HTRANS1;
input  [3:0] F_ARID_HSEL1;
input  [3:0] F_ARLEN_HBURST1;
input  [1:0] F_ARLOCK_HMASTLOCK1;
input  [1:0] F_ARSIZE_HSIZE1;
input  F_ARVALID_HWRITE1;
input  [31:0] F_AWADDR_HADDR0;
input  [1:0] F_AWBURST_HTRANS0;
input  [3:0] F_AWID_HSEL0;
input  [3:0] F_AWLEN_HBURST0;
input  [1:0] F_AWLOCK_HMASTLOCK0;
input  [1:0] F_AWSIZE_HSIZE0;
input  F_AWVALID_HWRITE0;
input  F_BREADY;
input  F_RMW_AXI;
input  F_RREADY;
input  [63:0] F_WDATA_HWDATA01;
input  [3:0] F_WID_HREADY01;
input  F_WLAST;
input  [7:0] F_WSTRB;
input  F_WVALID;
input  FPGA_MDDR_ARESET_N;
input  [10:2] MDDR_FABRIC_PADDR;
input  MDDR_FABRIC_PENABLE;
input  MDDR_FABRIC_PSEL;
input  [15:0] MDDR_FABRIC_PWDATA;
input  MDDR_FABRIC_PWRITE;
input  PRESET_N;
input  CAN_RXBUS_USBA_DATA1_MGPIO3A_IN;
input  CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN;
input  CAN_TXBUS_USBA_DATA0_MGPIO2A_IN;
input  [2:0] DM_IN;
input  [17:0] DRAM_DQ_IN;
input  [2:0] DRAM_DQS_IN;
input  [1:0] DRAM_FIFO_WE_IN;
input  I2C0_SCL_USBC_DATA1_MGPIO31B_IN;
input  I2C0_SDA_USBC_DATA0_MGPIO30B_IN;
input  I2C1_SCL_USBA_DATA4_MGPIO1A_IN;
input  I2C1_SDA_USBA_DATA3_MGPIO0A_IN;
input  MGPIO0B_IN;
input  MGPIO10B_IN;
input  MGPIO1B_IN;
input  MGPIO25A_IN;
input  MGPIO26A_IN;
input  MGPIO27A_IN;
input  MGPIO28A_IN;
input  MGPIO29A_IN;
input  MGPIO2B_IN;
input  MGPIO30A_IN;
input  MGPIO31A_IN;
input  MGPIO3B_IN;
input  MGPIO4B_IN;
input  MGPIO5B_IN;
input  MGPIO6B_IN;
input  MGPIO7B_IN;
input  MGPIO8B_IN;
input  MGPIO9B_IN;
input  MMUART0_CTS_USBC_DATA7_MGPIO19B_IN;
input  MMUART0_DCD_MGPIO22B_IN;
input  MMUART0_DSR_MGPIO20B_IN;
input  MMUART0_DTR_USBC_DATA6_MGPIO18B_IN;
input  MMUART0_RI_MGPIO21B_IN;
input  MMUART0_RTS_USBC_DATA5_MGPIO17B_IN;
input  MMUART0_RXD_USBC_STP_MGPIO28B_IN;
input  MMUART0_SCK_USBC_NXT_MGPIO29B_IN;
input  MMUART0_TXD_USBC_DIR_MGPIO27B_IN;
input  MMUART1_CTS_MGPIO13B_IN;
input  MMUART1_DCD_MGPIO16B_IN;
input  MMUART1_DSR_MGPIO14B_IN;
input  MMUART1_DTR_MGPIO12B_IN;
input  MMUART1_RI_MGPIO15B_IN;
input  MMUART1_RTS_MGPIO11B_IN;
input  MMUART1_RXD_USBC_DATA3_MGPIO26B_IN;
input  MMUART1_SCK_USBC_DATA4_MGPIO25B_IN;
input  MMUART1_TXD_USBC_DATA2_MGPIO24B_IN;
input  RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN;
input  RGMII_MDC_RMII_MDC_IN;
input  RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN;
input  RGMII_RX_CLK_IN;
input  RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN;
input  RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN;
input  RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN;
input  RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN;
input  RGMII_RXD3_USBB_DATA4_IN;
input  RGMII_TX_CLK_IN;
input  RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN;
input  RGMII_TXD0_RMII_TXD0_USBB_DIR_IN;
input  RGMII_TXD1_RMII_TXD1_USBB_STP_IN;
input  RGMII_TXD2_USBB_DATA5_IN;
input  RGMII_TXD3_USBB_DATA6_IN;
input  SPI0_SCK_USBA_XCLK_IN;
input  SPI0_SDI_USBA_DIR_MGPIO5A_IN;
input  SPI0_SDO_USBA_STP_MGPIO6A_IN;
input  SPI0_SS0_USBA_NXT_MGPIO7A_IN;
input  SPI0_SS1_USBA_DATA5_MGPIO8A_IN;
input  SPI0_SS2_USBA_DATA6_MGPIO9A_IN;
input  SPI0_SS3_USBA_DATA7_MGPIO10A_IN;
input  SPI0_SS4_MGPIO19A_IN;
input  SPI0_SS5_MGPIO20A_IN;
input  SPI0_SS6_MGPIO21A_IN;
input  SPI0_SS7_MGPIO22A_IN;
input  SPI1_SCK_IN;
input  SPI1_SDI_MGPIO11A_IN;
input  SPI1_SDO_MGPIO12A_IN;
input  SPI1_SS0_MGPIO13A_IN;
input  SPI1_SS1_MGPIO14A_IN;
input  SPI1_SS2_MGPIO15A_IN;
input  SPI1_SS3_MGPIO16A_IN;
input  SPI1_SS4_MGPIO17A_IN;
input  SPI1_SS5_MGPIO18A_IN;
input  SPI1_SS6_MGPIO23A_IN;
input  SPI1_SS7_MGPIO24A_IN;
input  USBC_XCLK_IN;
input  USBD_DATA0_IN;
input  USBD_DATA1_IN;
input  USBD_DATA2_IN;
input  USBD_DATA3_IN;
input  USBD_DATA4_IN;
input  USBD_DATA5_IN;
input  USBD_DATA6_IN;
input  USBD_DATA7_MGPIO23B_IN;
input  USBD_DIR_IN;
input  USBD_NXT_IN;
input  USBD_STP_IN;
input  USBD_XCLK_IN;
output CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT;
output CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT;
output CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT;
output [15:0] DRAM_ADDR;
output [2:0] DRAM_BA;
output DRAM_CASN;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CSN;
output [2:0] DRAM_DM_RDQS_OUT;
output [17:0] DRAM_DQ_OUT;
output [2:0] DRAM_DQS_OUT;
output [1:0] DRAM_FIFO_WE_OUT;
output DRAM_ODT;
output DRAM_RASN;
output DRAM_RSTN;
output DRAM_WEN;
output I2C0_SCL_USBC_DATA1_MGPIO31B_OUT;
output I2C0_SDA_USBC_DATA0_MGPIO30B_OUT;
output I2C1_SCL_USBA_DATA4_MGPIO1A_OUT;
output I2C1_SDA_USBA_DATA3_MGPIO0A_OUT;
output MGPIO0B_OUT;
output MGPIO10B_OUT;
output MGPIO1B_OUT;
output MGPIO25A_OUT;
output MGPIO26A_OUT;
output MGPIO27A_OUT;
output MGPIO28A_OUT;
output MGPIO29A_OUT;
output MGPIO2B_OUT;
output MGPIO30A_OUT;
output MGPIO31A_OUT;
output MGPIO3B_OUT;
output MGPIO4B_OUT;
output MGPIO5B_OUT;
output MGPIO6B_OUT;
output MGPIO7B_OUT;
output MGPIO8B_OUT;
output MGPIO9B_OUT;
output MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT;
output MMUART0_DCD_MGPIO22B_OUT;
output MMUART0_DSR_MGPIO20B_OUT;
output MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT;
output MMUART0_RI_MGPIO21B_OUT;
output MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT;
output MMUART0_RXD_USBC_STP_MGPIO28B_OUT;
output MMUART0_SCK_USBC_NXT_MGPIO29B_OUT;
output MMUART0_TXD_USBC_DIR_MGPIO27B_OUT;
output MMUART1_CTS_MGPIO13B_OUT;
output MMUART1_DCD_MGPIO16B_OUT;
output MMUART1_DSR_MGPIO14B_OUT;
output MMUART1_DTR_MGPIO12B_OUT;
output MMUART1_RI_MGPIO15B_OUT;
output MMUART1_RTS_MGPIO11B_OUT;
output MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT;
output MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT;
output MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT;
output RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT;
output RGMII_MDC_RMII_MDC_OUT;
output RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT;
output RGMII_RX_CLK_OUT;
output RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT;
output RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT;
output RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT;
output RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT;
output RGMII_RXD3_USBB_DATA4_OUT;
output RGMII_TX_CLK_OUT;
output RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT;
output RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT;
output RGMII_TXD1_RMII_TXD1_USBB_STP_OUT;
output RGMII_TXD2_USBB_DATA5_OUT;
output RGMII_TXD3_USBB_DATA6_OUT;
output SPI0_SCK_USBA_XCLK_OUT;
output SPI0_SDI_USBA_DIR_MGPIO5A_OUT;
output SPI0_SDO_USBA_STP_MGPIO6A_OUT;
output SPI0_SS0_USBA_NXT_MGPIO7A_OUT;
output SPI0_SS1_USBA_DATA5_MGPIO8A_OUT;
output SPI0_SS2_USBA_DATA6_MGPIO9A_OUT;
output SPI0_SS3_USBA_DATA7_MGPIO10A_OUT;
output SPI0_SS4_MGPIO19A_OUT;
output SPI0_SS5_MGPIO20A_OUT;
output SPI0_SS6_MGPIO21A_OUT;
output SPI0_SS7_MGPIO22A_OUT;
output SPI1_SCK_OUT;
output SPI1_SDI_MGPIO11A_OUT;
output SPI1_SDO_MGPIO12A_OUT;
output SPI1_SS0_MGPIO13A_OUT;
output SPI1_SS1_MGPIO14A_OUT;
output SPI1_SS2_MGPIO15A_OUT;
output SPI1_SS3_MGPIO16A_OUT;
output SPI1_SS4_MGPIO17A_OUT;
output SPI1_SS5_MGPIO18A_OUT;
output SPI1_SS6_MGPIO23A_OUT;
output SPI1_SS7_MGPIO24A_OUT;
output USBC_XCLK_OUT;
output USBD_DATA0_OUT;
output USBD_DATA1_OUT;
output USBD_DATA2_OUT;
output USBD_DATA3_OUT;
output USBD_DATA4_OUT;
output USBD_DATA5_OUT;
output USBD_DATA6_OUT;
output USBD_DATA7_MGPIO23B_OUT;
output USBD_DIR_OUT;
output USBD_NXT_OUT;
output USBD_STP_OUT;
output USBD_XCLK_OUT;
output CAN_RXBUS_USBA_DATA1_MGPIO3A_OE;
output CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE;
output CAN_TXBUS_USBA_DATA0_MGPIO2A_OE;
output [2:0] DM_OE;
output [17:0] DRAM_DQ_OE;
output [2:0] DRAM_DQS_OE;
output I2C0_SCL_USBC_DATA1_MGPIO31B_OE;
output I2C0_SDA_USBC_DATA0_MGPIO30B_OE;
output I2C1_SCL_USBA_DATA4_MGPIO1A_OE;
output I2C1_SDA_USBA_DATA3_MGPIO0A_OE;
output MGPIO0B_OE;
output MGPIO10B_OE;
output MGPIO1B_OE;
output MGPIO25A_OE;
output MGPIO26A_OE;
output MGPIO27A_OE;
output MGPIO28A_OE;
output MGPIO29A_OE;
output MGPIO2B_OE;
output MGPIO30A_OE;
output MGPIO31A_OE;
output MGPIO3B_OE;
output MGPIO4B_OE;
output MGPIO5B_OE;
output MGPIO6B_OE;
output MGPIO7B_OE;
output MGPIO8B_OE;
output MGPIO9B_OE;
output MMUART0_CTS_USBC_DATA7_MGPIO19B_OE;
output MMUART0_DCD_MGPIO22B_OE;
output MMUART0_DSR_MGPIO20B_OE;
output MMUART0_DTR_USBC_DATA6_MGPIO18B_OE;
output MMUART0_RI_MGPIO21B_OE;
output MMUART0_RTS_USBC_DATA5_MGPIO17B_OE;
output MMUART0_RXD_USBC_STP_MGPIO28B_OE;
output MMUART0_SCK_USBC_NXT_MGPIO29B_OE;
output MMUART0_TXD_USBC_DIR_MGPIO27B_OE;
output MMUART1_CTS_MGPIO13B_OE;
output MMUART1_DCD_MGPIO16B_OE;
output MMUART1_DSR_MGPIO14B_OE;
output MMUART1_DTR_MGPIO12B_OE;
output MMUART1_RI_MGPIO15B_OE;
output MMUART1_RTS_MGPIO11B_OE;
output MMUART1_RXD_USBC_DATA3_MGPIO26B_OE;
output MMUART1_SCK_USBC_DATA4_MGPIO25B_OE;
output MMUART1_TXD_USBC_DATA2_MGPIO24B_OE;
output RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE;
output RGMII_MDC_RMII_MDC_OE;
output RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE;
output RGMII_RX_CLK_OE;
output RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE;
output RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE;
output RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE;
output RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE;
output RGMII_RXD3_USBB_DATA4_OE;
output RGMII_TX_CLK_OE;
output RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE;
output RGMII_TXD0_RMII_TXD0_USBB_DIR_OE;
output RGMII_TXD1_RMII_TXD1_USBB_STP_OE;
output RGMII_TXD2_USBB_DATA5_OE;
output RGMII_TXD3_USBB_DATA6_OE;
output SPI0_SCK_USBA_XCLK_OE;
output SPI0_SDI_USBA_DIR_MGPIO5A_OE;
output SPI0_SDO_USBA_STP_MGPIO6A_OE;
output SPI0_SS0_USBA_NXT_MGPIO7A_OE;
output SPI0_SS1_USBA_DATA5_MGPIO8A_OE;
output SPI0_SS2_USBA_DATA6_MGPIO9A_OE;
output SPI0_SS3_USBA_DATA7_MGPIO10A_OE;
output SPI0_SS4_MGPIO19A_OE;
output SPI0_SS5_MGPIO20A_OE;
output SPI0_SS6_MGPIO21A_OE;
output SPI0_SS7_MGPIO22A_OE;
output SPI1_SCK_OE;
output SPI1_SDI_MGPIO11A_OE;
output SPI1_SDO_MGPIO12A_OE;
output SPI1_SS0_MGPIO13A_OE;
output SPI1_SS1_MGPIO14A_OE;
output SPI1_SS2_MGPIO15A_OE;
output SPI1_SS3_MGPIO16A_OE;
output SPI1_SS4_MGPIO17A_OE;
output SPI1_SS5_MGPIO18A_OE;
output SPI1_SS6_MGPIO23A_OE;
output SPI1_SS7_MGPIO24A_OE;
output USBC_XCLK_OE;
output USBD_DATA0_OE;
output USBD_DATA1_OE;
output USBD_DATA2_OE;
output USBD_DATA3_OE;
output USBD_DATA4_OE;
output USBD_DATA5_OE;
output USBD_DATA6_OE;
output USBD_DATA7_MGPIO23B_OE;
output USBD_DIR_OE;
output USBD_NXT_OE;
output USBD_STP_OE;
output USBD_XCLK_OE;

    parameter INIT = 'h0 ;
    parameter ACT_UBITS = 'hFFFFFFFFFFFFFF ;
    parameter MEMORYFILE = "" ;
    parameter RTC_MAIN_XTL_FREQ = 0.0 ;
    parameter RTC_MAIN_XTL_MODE = "1" ;
    parameter DDR_CLK_FREQ = 0.0 ;
    
endmodule


module eNVM_DataClient_FABOSC_0_OSC(
       FABOSC_0_RCOSC_25_50MHZ_O2F,
       FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
    );
output FABOSC_0_RCOSC_25_50MHZ_O2F;
output FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC;

    wire N_RCOSC_25_50MHZ_CLKINT, GND_net_1, VCC_net_1;
    
    RCOSC_25_50MHZ_FAB I_RCOSC_25_50MHZ_FAB (.A(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC), .CLKOUT(
        N_RCOSC_25_50MHZ_CLKINT));
    RCOSC_25_50MHZ #( .FREQUENCY(50.0) )  I_RCOSC_25_50MHZ (.CLKOUT(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC));
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    CLKINT I_RCOSC_25_50MHZ_FAB_CLKINT (.A(N_RCOSC_25_50MHZ_CLKINT), 
        .Y(FABOSC_0_RCOSC_25_50MHZ_O2F));
    
endmodule


module CoreResetP_Z2(
       FABOSC_0_RCOSC_25_50MHZ_O2F,
       GL0_INST,
       INIT_DONE_int,
       SYSRESET_POR,
       eNVM_DataClient_MSS_TMP_0_MSS_RESET_N_M2F,
       CORECONFIGP_0_APB_S_PRESET_N,
       CORECONFIGP_0_CONFIG1_DONE,
       CORECONFIGP_0_CONFIG2_DONE
    );
input  FABOSC_0_RCOSC_25_50MHZ_O2F;
input  GL0_INST;
output INIT_DONE_int;
input  SYSRESET_POR;
input  eNVM_DataClient_MSS_TMP_0_MSS_RESET_N_M2F;
input  CORECONFIGP_0_APB_S_PRESET_N;
input  CORECONFIGP_0_CONFIG1_DONE;
input  CORECONFIGP_0_CONFIG2_DONE;

    wire sm0_areset_n_rcosc, sdif0_areset_n_rcosc_net_1, 
        sm0_areset_n_clk_base_net_1, sm0_areset_n_clk_base_0, 
        \count_ddr[0]_net_1 , \count_ddr_s[0] , ddr_settled_net_1, 
        VCC_net_1, ddr_settled4_net_1, GND_net_1, 
        count_ddr_enable_net_1, next_count_ddr_enable_0_sqmuxa, 
        un1_next_ddr_ready_0_sqmuxa_net_1, mss_ready_select_net_1, 
        POWER_ON_RESET_N_clk_base_net_1, mss_ready_select4_net_1, 
        \sm0_state[6]_net_1 , mss_ready_state_net_1, 
        RESET_N_M2F_clk_base_net_1, \sm0_state[2]_net_1 , 
        \sm0_state_ns[2]_net_1 , \sm0_state[3]_net_1 , 
        \sm0_state_ns[3]_net_1 , \sm0_state[4]_net_1 , 
        \sm0_state_ns[4]_net_1 , \sm0_state[5]_net_1 , 
        \sm0_state_ns[5]_net_1 , \sm0_state_ns_a3[6]_net_1 , 
        \sm0_state[0]_net_1 , \sm0_state[1]_net_1 , 
        count_ddr_enable_rcosc_net_1, count_ddr_enable_q1_net_1, 
        ddr_settled_clk_base_net_1, ddr_settled_q1_net_1, 
        release_sdif3_core_clk_base, release_sdif3_core_q1, 
        POWER_ON_RESET_N_q1_net_1, RESET_N_M2F_q1_net_1, 
        FIC_2_APB_M_PRESET_N_clk_base_net_1, 
        FIC_2_APB_M_PRESET_N_q1_net_1, sm0_areset_n_i_0_i, 
        sm0_areset_n_q1_net_1, sm0_areset_n_rcosc_q1_net_1, 
        MSS_HPMS_READY_int_net_1, MSS_HPMS_READY_int_4_net_1, 
        CONFIG1_DONE_clk_base_net_1, CONFIG1_DONE_q1_net_1, 
        CONFIG2_DONE_clk_base_net_1, CONFIG2_DONE_q1_net_1, 
        sdif3_spll_lock_q2_net_1, sdif3_spll_lock_q1_net_1, 
        release_sdif2_core, \count_ddr[1]_net_1 , \count_ddr_s[1] , 
        \count_ddr[2]_net_1 , \count_ddr_s[2] , \count_ddr[3]_net_1 , 
        \count_ddr_s[3] , \count_ddr[4]_net_1 , \count_ddr_s[4] , 
        \count_ddr[5]_net_1 , \count_ddr_s[5] , \count_ddr[6]_net_1 , 
        \count_ddr_s[6] , \count_ddr[7]_net_1 , \count_ddr_s[7] , 
        \count_ddr[8]_net_1 , \count_ddr_s[8] , \count_ddr[9]_net_1 , 
        \count_ddr_s[9] , \count_ddr[10]_net_1 , \count_ddr_s[10] , 
        \count_ddr[11]_net_1 , \count_ddr_s[11] , 
        \count_ddr[12]_net_1 , \count_ddr_s[12] , 
        \count_ddr[13]_net_1 , \count_ddr_s[13]_net_1 , 
        count_ddr_s_27_FCO, \count_ddr_cry[1]_net_1 , 
        \count_ddr_cry[2]_net_1 , \count_ddr_cry[3]_net_1 , 
        \count_ddr_cry[4]_net_1 , \count_ddr_cry[5]_net_1 , 
        \count_ddr_cry[6]_net_1 , \count_ddr_cry[7]_net_1 , 
        \count_ddr_cry[8]_net_1 , \count_ddr_cry[9]_net_1 , 
        \count_ddr_cry[10]_net_1 , \count_ddr_cry[11]_net_1 , 
        \count_ddr_cry[12]_net_1 , ddr_settled4_6_net_1, 
        next_sm0_state25_net_1, ddr_settled4_9_net_1, 
        ddr_settled4_8_net_1, ddr_settled4_7_net_1;
    
    CFG4 #( .INIT(16'hFF70) )  \sm0_state_ns[4]  (.A(
        release_sdif3_core_clk_base), .B(ddr_settled_clk_base_net_1), 
        .C(\sm0_state[4]_net_1 ), .D(next_count_ddr_enable_0_sqmuxa), 
        .Y(\sm0_state_ns[4]_net_1 ));
    SLE \count_ddr[3]  (.D(\count_ddr_s[3] ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[3]_net_1 ));
    SLE sm0_areset_n_q1 (.D(VCC_net_1), .CLK(GL0_INST), .EN(VCC_net_1), 
        .ALn(sm0_areset_n_i_0_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(sm0_areset_n_q1_net_1));
    SLE count_ddr_enable_q1 (.D(count_ddr_enable_net_1), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(VCC_net_1), .ALn(
        sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(count_ddr_enable_q1_net_1));
    SLE \sm0_state[6]  (.D(VCC_net_1), .CLK(GL0_INST), .EN(
        \sm0_state_ns_a3[6]_net_1 ), .ALn(sm0_areset_n_clk_base_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\sm0_state[6]_net_1 ));
    CFG3 #( .INIT(8'hE0) )  MSS_HPMS_READY_int_4 (.A(
        RESET_N_M2F_clk_base_net_1), .B(mss_ready_select_net_1), .C(
        FIC_2_APB_M_PRESET_N_clk_base_net_1), .Y(
        MSS_HPMS_READY_int_4_net_1));
    SLE \sm0_state[2]  (.D(\sm0_state_ns[2]_net_1 ), .CLK(GL0_INST), 
        .EN(VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\sm0_state[2]_net_1 ));
    SLE FIC_2_APB_M_PRESET_N_clk_base (.D(
        FIC_2_APB_M_PRESET_N_q1_net_1), .CLK(GL0_INST), .EN(VCC_net_1), 
        .ALn(CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        FIC_2_APB_M_PRESET_N_clk_base_net_1));
    CFG4 #( .INIT(16'h0002) )  ddr_settled4_8 (.A(
        \count_ddr[13]_net_1 ), .B(\count_ddr[5]_net_1 ), .C(
        \count_ddr[3]_net_1 ), .D(\count_ddr[1]_net_1 ), .Y(
        ddr_settled4_8_net_1));
    CLKINT sdif0_areset_n_rcosc_RNI3JN5 (.A(sdif0_areset_n_rcosc_net_1)
        , .Y(sm0_areset_n_rcosc));
    ARI1 #( .INIT(20'h4AA00) )  \count_ddr_cry[4]  (.A(VCC_net_1), .B(
        \count_ddr[4]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \count_ddr_cry[3]_net_1 ), .S(\count_ddr_s[4] ), .Y(), .FCO(
        \count_ddr_cry[4]_net_1 ));
    SLE INIT_DONE_int_inst_1 (.D(VCC_net_1), .CLK(GL0_INST), .EN(
        \sm0_state[6]_net_1 ), .ALn(sm0_areset_n_clk_base_net_1), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(INIT_DONE_int));
    SLE \count_ddr[9]  (.D(\count_ddr_s[9] ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[9]_net_1 ));
    SLE MSS_HPMS_READY_int (.D(MSS_HPMS_READY_int_4_net_1), .CLK(
        GL0_INST), .EN(VCC_net_1), .ALn(
        POWER_ON_RESET_N_clk_base_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MSS_HPMS_READY_int_net_1));
    SLE count_ddr_enable_rcosc (.D(count_ddr_enable_q1_net_1), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(VCC_net_1), .ALn(
        sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(count_ddr_enable_rcosc_net_1));
    SLE \count_ddr[7]  (.D(\count_ddr_s[7] ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[7]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \sm0_state_ns_a3[6]  (.A(
        CONFIG2_DONE_clk_base_net_1), .B(\sm0_state[5]_net_1 ), .Y(
        \sm0_state_ns_a3[6]_net_1 ));
    VCC VCC (.Y(VCC_net_1));
    SLE \sm0_state[4]  (.D(\sm0_state_ns[4]_net_1 ), .CLK(GL0_INST), 
        .EN(VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\sm0_state[4]_net_1 ));
    SLE count_ddr_enable (.D(next_count_ddr_enable_0_sqmuxa), .CLK(
        GL0_INST), .EN(un1_next_ddr_ready_0_sqmuxa_net_1), .ALn(
        sm0_areset_n_clk_base_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(count_ddr_enable_net_1));
    ARI1 #( .INIT(20'h4AA00) )  count_ddr_s_27 (.A(VCC_net_1), .B(
        \count_ddr[0]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        VCC_net_1), .S(), .Y(), .FCO(count_ddr_s_27_FCO));
    ARI1 #( .INIT(20'h4AA00) )  \count_ddr_cry[10]  (.A(VCC_net_1), .B(
        \count_ddr[10]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \count_ddr_cry[9]_net_1 ), .S(\count_ddr_s[10] ), .Y(), .FCO(
        \count_ddr_cry[10]_net_1 ));
    SLE \sm0_state[5]  (.D(\sm0_state_ns[5]_net_1 ), .CLK(GL0_INST), 
        .EN(VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\sm0_state[5]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \count_ddr_cry[11]  (.A(VCC_net_1), .B(
        \count_ddr[11]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \count_ddr_cry[10]_net_1 ), .S(\count_ddr_s[11] ), .Y(), .FCO(
        \count_ddr_cry[11]_net_1 ));
    SLE \count_ddr[8]  (.D(\count_ddr_s[8] ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[8]_net_1 ));
    CFG3 #( .INIT(8'hF2) )  \sm0_state_ns[2]  (.A(\sm0_state[2]_net_1 )
        , .B(CONFIG1_DONE_clk_base_net_1), .C(\sm0_state[1]_net_1 ), 
        .Y(\sm0_state_ns[2]_net_1 ));
    SLE sm0_areset_n_clk_base (.D(sm0_areset_n_q1_net_1), .CLK(
        GL0_INST), .EN(VCC_net_1), .ALn(sm0_areset_n_i_0_i), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(sm0_areset_n_clk_base_0));
    CFG2 #( .INIT(4'h8) )  next_sm0_state25 (.A(
        ddr_settled_clk_base_net_1), .B(release_sdif3_core_clk_base), 
        .Y(next_sm0_state25_net_1));
    ARI1 #( .INIT(20'h4AA00) )  \count_ddr_cry[12]  (.A(VCC_net_1), .B(
        \count_ddr[12]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \count_ddr_cry[11]_net_1 ), .S(\count_ddr_s[12] ), .Y(), .FCO(
        \count_ddr_cry[12]_net_1 ));
    SLE mss_ready_state (.D(VCC_net_1), .CLK(GL0_INST), .EN(
        RESET_N_M2F_clk_base_net_1), .ALn(
        POWER_ON_RESET_N_clk_base_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        mss_ready_state_net_1));
    CFG4 #( .INIT(16'h8000) )  ddr_settled4 (.A(ddr_settled4_6_net_1), 
        .B(ddr_settled4_7_net_1), .C(ddr_settled4_8_net_1), .D(
        ddr_settled4_9_net_1), .Y(ddr_settled4_net_1));
    SLE \sm0_state[1]  (.D(\sm0_state[0]_net_1 ), .CLK(GL0_INST), .EN(
        VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \sm0_state[1]_net_1 ));
    CFG2 #( .INIT(4'h8) )  next_count_ddr_enable_0_sqmuxa_0_a3 (.A(
        sdif3_spll_lock_q2_net_1), .B(\sm0_state[3]_net_1 ), .Y(
        next_count_ddr_enable_0_sqmuxa));
    CFG2 #( .INIT(4'h1) )  ddr_settled4_6 (.A(\count_ddr[2]_net_1 ), 
        .B(\count_ddr[7]_net_1 ), .Y(ddr_settled4_6_net_1));
    SLE ddr_settled_clk_base (.D(ddr_settled_q1_net_1), .CLK(GL0_INST), 
        .EN(VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(ddr_settled_clk_base_net_1));
    SLE FIC_2_APB_M_PRESET_N_q1 (.D(VCC_net_1), .CLK(GL0_INST), .EN(
        VCC_net_1), .ALn(CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1)
        , .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        FIC_2_APB_M_PRESET_N_q1_net_1));
    ARI1 #( .INIT(20'h4AA00) )  \count_ddr_cry[8]  (.A(VCC_net_1), .B(
        \count_ddr[8]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \count_ddr_cry[7]_net_1 ), .S(\count_ddr_s[8] ), .Y(), .FCO(
        \count_ddr_cry[8]_net_1 ));
    GND GND (.Y(GND_net_1));
    CFG1 #( .INIT(2'h1) )  \count_ddr_RNO[0]  (.A(\count_ddr[0]_net_1 )
        , .Y(\count_ddr_s[0] ));
    SLE POWER_ON_RESET_N_clk_base (.D(POWER_ON_RESET_N_q1_net_1), .CLK(
        GL0_INST), .EN(VCC_net_1), .ALn(SYSRESET_POR), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        POWER_ON_RESET_N_clk_base_net_1));
    ARI1 #( .INIT(20'h4AA00) )  \count_ddr_cry[1]  (.A(VCC_net_1), .B(
        \count_ddr[1]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        count_ddr_s_27_FCO), .S(\count_ddr_s[1] ), .Y(), .FCO(
        \count_ddr_cry[1]_net_1 ));
    CLKINT sm0_areset_n_clk_base_RNIN8M8 (.A(sm0_areset_n_clk_base_0), 
        .Y(sm0_areset_n_clk_base_net_1));
    SLE RESET_N_M2F_q1 (.D(VCC_net_1), .CLK(GL0_INST), .EN(VCC_net_1), 
        .ALn(eNVM_DataClient_MSS_TMP_0_MSS_RESET_N_M2F), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(RESET_N_M2F_q1_net_1));
    SLE release_sdif0_core_q1 (.D(release_sdif2_core), .CLK(GL0_INST), 
        .EN(VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(release_sdif3_core_q1));
    SLE \count_ddr[10]  (.D(\count_ddr_s[10] ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[10]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \count_ddr_cry[6]  (.A(VCC_net_1), .B(
        \count_ddr[6]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \count_ddr_cry[5]_net_1 ), .S(\count_ddr_s[6] ), .Y(), .FCO(
        \count_ddr_cry[6]_net_1 ));
    SLE sdif0_areset_n_rcosc (.D(sm0_areset_n_rcosc_q1_net_1), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(VCC_net_1), .ALn(
        sm0_areset_n_i_0_i), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(sdif0_areset_n_rcosc_net_1));
    ARI1 #( .INIT(20'h4AA00) )  \count_ddr_s[13]  (.A(VCC_net_1), .B(
        \count_ddr[13]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \count_ddr_cry[12]_net_1 ), .S(\count_ddr_s[13]_net_1 ), .Y(), 
        .FCO());
    SLE \count_ddr[5]  (.D(\count_ddr_s[5] ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[5]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \count_ddr_cry[3]  (.A(VCC_net_1), .B(
        \count_ddr[3]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \count_ddr_cry[2]_net_1 ), .S(\count_ddr_s[3] ), .Y(), .FCO(
        \count_ddr_cry[3]_net_1 ));
    SLE \count_ddr[2]  (.D(\count_ddr_s[2] ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[2]_net_1 ));
    SLE \count_ddr[1]  (.D(\count_ddr_s[1] ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[1]_net_1 ));
    SLE \sm0_state[0]  (.D(GND_net_1), .CLK(GL0_INST), .EN(VCC_net_1), 
        .ALn(sm0_areset_n_clk_base_net_1), .ADn(GND_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \sm0_state[0]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \count_ddr_cry[2]  (.A(VCC_net_1), .B(
        \count_ddr[2]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \count_ddr_cry[1]_net_1 ), .S(\count_ddr_s[2] ), .Y(), .FCO(
        \count_ddr_cry[2]_net_1 ));
    SLE sm0_areset_n_rcosc_q1 (.D(VCC_net_1), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(VCC_net_1), .ALn(
        sm0_areset_n_i_0_i), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(sm0_areset_n_rcosc_q1_net_1));
    ARI1 #( .INIT(20'h4AA00) )  \count_ddr_cry[5]  (.A(VCC_net_1), .B(
        \count_ddr[5]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \count_ddr_cry[4]_net_1 ), .S(\count_ddr_s[5] ), .Y(), .FCO(
        \count_ddr_cry[5]_net_1 ));
    SLE ddr_settled_q1 (.D(ddr_settled_net_1), .CLK(GL0_INST), .EN(
        VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        ddr_settled_q1_net_1));
    SLE \count_ddr[11]  (.D(\count_ddr_s[11] ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[11]_net_1 ));
    SLE \sm0_state[3]  (.D(\sm0_state_ns[3]_net_1 ), .CLK(GL0_INST), 
        .EN(VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\sm0_state[3]_net_1 ));
    CFG4 #( .INIT(16'h88F8) )  \sm0_state_ns[3]  (.A(
        \sm0_state[2]_net_1 ), .B(CONFIG1_DONE_clk_base_net_1), .C(
        \sm0_state[3]_net_1 ), .D(sdif3_spll_lock_q2_net_1), .Y(
        \sm0_state_ns[3]_net_1 ));
    SLE \count_ddr[0]  (.D(\count_ddr_s[0] ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[0]_net_1 ));
    SLE CONFIG2_DONE_q1 (.D(CORECONFIGP_0_CONFIG2_DONE), .CLK(GL0_INST)
        , .EN(VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(CONFIG2_DONE_q1_net_1));
    SLE CONFIG2_DONE_clk_base (.D(CONFIG2_DONE_q1_net_1), .CLK(
        GL0_INST), .EN(VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(CONFIG2_DONE_clk_base_net_1));
    CFG4 #( .INIT(16'h0001) )  ddr_settled4_9 (.A(
        \count_ddr[12]_net_1 ), .B(\count_ddr[11]_net_1 ), .C(
        \count_ddr[6]_net_1 ), .D(\count_ddr[0]_net_1 ), .Y(
        ddr_settled4_9_net_1));
    CFG4 #( .INIT(16'h8000) )  ddr_settled4_7 (.A(
        \count_ddr[10]_net_1 ), .B(\count_ddr[9]_net_1 ), .C(
        \count_ddr[8]_net_1 ), .D(\count_ddr[4]_net_1 ), .Y(
        ddr_settled4_7_net_1));
    SLE CONFIG1_DONE_clk_base (.D(CONFIG1_DONE_q1_net_1), .CLK(
        GL0_INST), .EN(VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(CONFIG1_DONE_clk_base_net_1));
    SLE mss_ready_select (.D(VCC_net_1), .CLK(GL0_INST), .EN(
        mss_ready_select4_net_1), .ALn(POWER_ON_RESET_N_clk_base_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(mss_ready_select_net_1));
    CFG2 #( .INIT(4'h8) )  MSS_HPMS_READY_int_RNI9ANL (.A(SYSRESET_POR)
        , .B(MSS_HPMS_READY_int_net_1), .Y(sm0_areset_n_i_0_i));
    SLE \count_ddr[4]  (.D(\count_ddr_s[4] ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[4]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \count_ddr_cry[7]  (.A(VCC_net_1), .B(
        \count_ddr[7]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \count_ddr_cry[6]_net_1 ), .S(\count_ddr_s[7] ), .Y(), .FCO(
        \count_ddr_cry[7]_net_1 ));
    SLE release_sdif0_core (.D(VCC_net_1), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(VCC_net_1), .ALn(
        sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(release_sdif2_core));
    SLE POWER_ON_RESET_N_q1 (.D(VCC_net_1), .CLK(GL0_INST), .EN(
        VCC_net_1), .ALn(SYSRESET_POR), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        POWER_ON_RESET_N_q1_net_1));
    CFG2 #( .INIT(4'h8) )  mss_ready_select4 (.A(
        FIC_2_APB_M_PRESET_N_clk_base_net_1), .B(mss_ready_state_net_1)
        , .Y(mss_ready_select4_net_1));
    SLE \count_ddr[12]  (.D(\count_ddr_s[12] ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[12]_net_1 ));
    SLE ddr_settled (.D(VCC_net_1), .CLK(FABOSC_0_RCOSC_25_50MHZ_O2F), 
        .EN(ddr_settled4_net_1), .ALn(sm0_areset_n_rcosc), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(ddr_settled_net_1));
    ARI1 #( .INIT(20'h4AA00) )  \count_ddr_cry[9]  (.A(VCC_net_1), .B(
        \count_ddr[9]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \count_ddr_cry[8]_net_1 ), .S(\count_ddr_s[9] ), .Y(), .FCO(
        \count_ddr_cry[9]_net_1 ));
    SLE \count_ddr[6]  (.D(\count_ddr_s[6] ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[6]_net_1 ));
    SLE CONFIG1_DONE_q1 (.D(CORECONFIGP_0_CONFIG1_DONE), .CLK(GL0_INST)
        , .EN(VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(CONFIG1_DONE_q1_net_1));
    SLE sdif3_spll_lock_q1 (.D(VCC_net_1), .CLK(GL0_INST), .EN(
        VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        sdif3_spll_lock_q1_net_1));
    SLE release_sdif0_core_clk_base (.D(release_sdif3_core_q1), .CLK(
        GL0_INST), .EN(VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(release_sdif3_core_clk_base));
    SLE sdif3_spll_lock_q2 (.D(sdif3_spll_lock_q1_net_1), .CLK(
        GL0_INST), .EN(VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(sdif3_spll_lock_q2_net_1));
    SLE RESET_N_M2F_clk_base (.D(RESET_N_M2F_q1_net_1), .CLK(GL0_INST), 
        .EN(VCC_net_1), .ALn(eNVM_DataClient_MSS_TMP_0_MSS_RESET_N_M2F)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(RESET_N_M2F_clk_base_net_1));
    CFG4 #( .INIT(16'hF888) )  un1_next_ddr_ready_0_sqmuxa (.A(
        sdif3_spll_lock_q2_net_1), .B(\sm0_state[3]_net_1 ), .C(
        ddr_settled_clk_base_net_1), .D(\sm0_state[4]_net_1 ), .Y(
        un1_next_ddr_ready_0_sqmuxa_net_1));
    SLE \count_ddr[13]  (.D(\count_ddr_s[13]_net_1 ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[13]_net_1 ));
    CFG4 #( .INIT(16'h88F8) )  \sm0_state_ns[5]  (.A(
        \sm0_state[4]_net_1 ), .B(next_sm0_state25_net_1), .C(
        \sm0_state[5]_net_1 ), .D(CONFIG2_DONE_clk_base_net_1), .Y(
        \sm0_state_ns[5]_net_1 ));
    
endmodule


module eNVM_DataClient_CCC_0_FCCC(
       GL0_INST,
       LOCK,
       FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
    );
output GL0_INST;
output LOCK;
input  FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC;

    wire GL0_net, VCC_net_1, GND_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    CLKINT GL0_INST_inst_1 (.A(GL0_net), .Y(GL0_INST));
    CCC #( .INIT(210'h0000007FB8000044D64000318C6318C1F18C61EC0404040400301)
        , .VCOFREQUENCY(800.0) )  CCC_INST (.Y0(), .Y1(), .Y2(), .Y3(), 
        .PRDATA({nc0, nc1, nc2, nc3, nc4, nc5, nc6, nc7}), .LOCK(LOCK), 
        .BUSY(), .CLK0(VCC_net_1), .CLK1(VCC_net_1), .CLK2(VCC_net_1), 
        .CLK3(VCC_net_1), .NGMUX0_SEL(GND_net_1), .NGMUX1_SEL(
        GND_net_1), .NGMUX2_SEL(GND_net_1), .NGMUX3_SEL(GND_net_1), 
        .NGMUX0_HOLD_N(VCC_net_1), .NGMUX1_HOLD_N(VCC_net_1), 
        .NGMUX2_HOLD_N(VCC_net_1), .NGMUX3_HOLD_N(VCC_net_1), 
        .NGMUX0_ARST_N(VCC_net_1), .NGMUX1_ARST_N(VCC_net_1), 
        .NGMUX2_ARST_N(VCC_net_1), .NGMUX3_ARST_N(VCC_net_1), 
        .PLL_BYPASS_N(VCC_net_1), .PLL_ARST_N(VCC_net_1), 
        .PLL_POWERDOWN_N(VCC_net_1), .GPD0_ARST_N(VCC_net_1), 
        .GPD1_ARST_N(VCC_net_1), .GPD2_ARST_N(VCC_net_1), .GPD3_ARST_N(
        VCC_net_1), .PRESET_N(GND_net_1), .PCLK(VCC_net_1), .PSEL(
        VCC_net_1), .PENABLE(VCC_net_1), .PWRITE(VCC_net_1), .PADDR({
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1}), .PWDATA({VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .CLK0_PAD(GND_net_1), .CLK1_PAD(GND_net_1), .CLK2_PAD(
        GND_net_1), .CLK3_PAD(GND_net_1), .GL0(GL0_net), .GL1(), .GL2()
        , .GL3(), .RCOSC_25_50MHZ(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC), 
        .RCOSC_1MHZ(GND_net_1), .XTLOSC(GND_net_1));
    
endmodule


module CoreConfigP_Z1(
       CORECONFIGP_0_MDDR_APBmslave_PADDR,
       CORECONFIGP_0_MDDR_APBmslave_PWDATA,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA,
       CORECONFIGP_0_MDDR_APBmslave_PRDATA,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_10,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_11,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_13,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_3,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_4,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_5,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_6,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_7,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_8,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_3,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_4,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_5,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_6,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_7,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_8,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_9,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_10,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_11,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_12,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_13,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_14,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_15,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_16,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_18,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_0,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_1,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_2,
       CORECONFIGP_0_SOFT_RESET_F2M_i_0,
       CORECONFIGP_0_SOFT_M3_RESET_i_0,
       CORECONFIGP_0_APB_S_PRESET_N,
       CORECONFIGP_0_APB_S_PCLK,
       CORECONFIGP_0_CONFIG1_DONE,
       CORECONFIGP_0_CONFIG2_DONE,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PREADY,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PSLVERR,
       CORECONFIGP_0_MDDR_APBmslave_PWRITE,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE,
       CORECONFIGP_0_APB_S_PCLK_i_0,
       INIT_DONE_int,
       CORECONFIGP_0_MDDR_APBmslave_PENABLE,
       CORECONFIGP_0_MDDR_APBmslave_PSELx,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PSELx,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE,
       CORECONFIGP_0_MDDR_APBmslave_PSLVERR,
       CORECONFIGP_0_MDDR_APBmslave_PREADY
    );
output [10:2] CORECONFIGP_0_MDDR_APBmslave_PADDR;
output [15:0] CORECONFIGP_0_MDDR_APBmslave_PWDATA;
input  [16:0] eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA;
input  [15:0] CORECONFIGP_0_MDDR_APBmslave_PRDATA;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_10;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_11;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_13;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_3;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_4;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_5;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_6;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_7;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_8;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_3;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_4;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_5;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_6;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_7;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_8;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_9;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_10;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_11;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_12;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_13;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_14;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_15;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_16;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_18;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_0;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_1;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_2;
output CORECONFIGP_0_SOFT_RESET_F2M_i_0;
output CORECONFIGP_0_SOFT_M3_RESET_i_0;
input  CORECONFIGP_0_APB_S_PRESET_N;
input  CORECONFIGP_0_APB_S_PCLK;
output CORECONFIGP_0_CONFIG1_DONE;
output CORECONFIGP_0_CONFIG2_DONE;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PREADY;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PSLVERR;
output CORECONFIGP_0_MDDR_APBmslave_PWRITE;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE;
input  CORECONFIGP_0_APB_S_PCLK_i_0;
input  INIT_DONE_int;
output CORECONFIGP_0_MDDR_APBmslave_PENABLE;
output CORECONFIGP_0_MDDR_APBmslave_PSELx;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PSELx;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE;
input  CORECONFIGP_0_MDDR_APBmslave_PSLVERR;
input  CORECONFIGP_0_MDDR_APBmslave_PREADY;

    wire CORECONFIGP_0_SOFT_RESET_F2M, CORECONFIGP_0_SOFT_M3_RESET, 
        \paddr[12]_net_1 , VCC_net_1, state_419_d, GND_net_1, 
        \paddr[13]_net_1 , \paddr[15]_net_1 , 
        \soft_reset_reg[14]_net_1 , soft_reset_reg6_net_1, 
        \soft_reset_reg[15]_net_1 , \soft_reset_reg[16]_net_1 , 
        control_reg_15_net_1, \soft_reset_reg[0]_net_1 , 
        \soft_reset_reg[3]_net_1 , \soft_reset_reg[4]_net_1 , 
        \soft_reset_reg[5]_net_1 , \soft_reset_reg[6]_net_1 , 
        \soft_reset_reg[7]_net_1 , \soft_reset_reg[8]_net_1 , 
        \soft_reset_reg[9]_net_1 , \soft_reset_reg[10]_net_1 , 
        \soft_reset_reg[11]_net_1 , \soft_reset_reg[12]_net_1 , 
        \soft_reset_reg[13]_net_1 , \prdata[3] , \state[1]_net_1 , 
        \prdata[4] , \prdata[5] , \prdata[6] , \prdata[7] , 
        \prdata[8] , \prdata[9] , \prdata[10] , \prdata[11] , 
        \prdata[12] , \prdata[13] , \prdata[14] , \prdata[15] , 
        \prdata[16] , int_prdata_5_sqmuxa_net_1, \prdata[0] , 
        \prdata[1] , \prdata[2] , 
        un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_net_1, pslverr, 
        \state[0]_net_1 , \state_ns[0] , \state_ns[1] , psel_net_1, 
        state_419_d_i_0, INIT_DONE_q1_net_1, INIT_DONE_q2_net_1, 
        MDDR_PENABLE_2_net_1, un1_R_SDIF3_PSEL_1_1_net_1, 
        int_prdata_4_sqmuxa_net_1, \prdata_0_iv_1[5]_net_1 , 
        int_prdata_3_sqmuxa_net_1, INIT_DONE_q2_m_1, 
        int_prdata19_net_1, \prdata_0_iv_0[0]_net_1 , int_psel_net_1, 
        int_prdata15_net_1, \MDDR_PRDATA_m[1] , \control_reg_1_m[0] , 
        \control_reg_1_m[1] ;
    
    SLE \soft_reset_reg[13]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[13]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6_net_1), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[13]_net_1 ));
    SLE \pwdata[15]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[15]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[15]));
    SLE \FIC_2_APB_M_PRDATA[13]  (.D(\prdata[13] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_13));
    SLE \pwdata[8]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[8]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[8]));
    SLE \pwdata[3]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[3]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[3]));
    SLE \soft_reset_reg[10]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[10]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6_net_1), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[10]_net_1 ));
    CFG4 #( .INIT(16'hECA0) )  \prdata_0_iv[12]  (.A(
        \soft_reset_reg[12]_net_1 ), .B(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .C(
        int_prdata_4_sqmuxa_net_1), .D(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[12]), .Y(\prdata[12] ));
    SLE \paddr[8]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_6), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[8]));
    CFG1 #( .INIT(2'h1) )  \soft_reset_reg_RNIR4Q2[1]  (.A(
        CORECONFIGP_0_SOFT_RESET_F2M), .Y(
        CORECONFIGP_0_SOFT_RESET_F2M_i_0));
    SLE \soft_reset_reg[2]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[2]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6_net_1), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_SOFT_M3_RESET));
    SLE \pwdata[5]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[5]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[5]));
    SLE \paddr[5]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_3), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[5]));
    SLE INIT_DONE_q1 (.D(INIT_DONE_int), .CLK(CORECONFIGP_0_APB_S_PCLK)
        , .EN(VCC_net_1), .ALn(CORECONFIGP_0_APB_S_PRESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(INIT_DONE_q1_net_1));
    SLE \paddr[3]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[3]));
    SLE \FIC_2_APB_M_PRDATA[5]  (.D(\prdata[5] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_5));
    SLE \pwdata[9]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[9]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[9]));
    SLE \FIC_2_APB_M_PRDATA[9]  (.D(\prdata[9] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_9));
    SLE \control_reg_1[0]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[0]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(control_reg_15_net_1), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_CONFIG1_DONE));
    CFG4 #( .INIT(16'h4000) )  int_prdata_3_sqmuxa (.A(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2), .B(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1), .C(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0), .D(
        un1_R_SDIF3_PSEL_1_1_net_1), .Y(int_prdata_3_sqmuxa_net_1));
    SLE FIC_2_APB_M_PREADY (.D(\state[1]_net_1 ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(
        un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_net_1), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(GND_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PREADY));
    SLE \pwdata[7]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[7]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[7]));
    SLE \soft_reset_reg[9]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[9]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6_net_1), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[9]_net_1 ));
    CFG3 #( .INIT(8'hEC) )  \prdata_0_iv[16]  (.A(
        \soft_reset_reg[16]_net_1 ), .B(int_prdata_5_sqmuxa_net_1), .C(
        int_prdata_4_sqmuxa_net_1), .Y(\prdata[16] ));
    SLE \FIC_2_APB_M_PRDATA[14]  (.D(\prdata[14] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_14));
    VCC VCC (.Y(VCC_net_1));
    SLE \pwdata[1]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[1]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[1]));
    SLE \pwdata[13]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[13]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[13]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_0_iv[11]  (.A(
        \soft_reset_reg[11]_net_1 ), .B(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .C(
        int_prdata_4_sqmuxa_net_1), .D(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[11]), .Y(\prdata[11] ));
    CFG4 #( .INIT(16'hECA0) )  \prdata_0_iv[10]  (.A(
        \soft_reset_reg[10]_net_1 ), .B(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .C(
        int_prdata_4_sqmuxa_net_1), .D(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[10]), .Y(\prdata[10] ));
    SLE psel (.D(state_419_d_i_0), .CLK(CORECONFIGP_0_APB_S_PCLK_i_0), 
        .EN(VCC_net_1), .ALn(CORECONFIGP_0_APB_S_PRESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(psel_net_1));
    CFG4 #( .INIT(16'h1000) )  \prdata_0_iv_0_RNO[0]  (.A(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2), .B(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1), .C(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0), .D(
        INIT_DONE_q2_net_1), .Y(INIT_DONE_q2_m_1));
    SLE \FIC_2_APB_M_PRDATA[11]  (.D(\prdata[11] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_11));
    CFG3 #( .INIT(8'h3B) )  un1_R_SDIF3_PSEL_1_1 (.A(\paddr[13]_net_1 )
        , .B(psel_net_1), .C(\paddr[15]_net_1 ), .Y(
        un1_R_SDIF3_PSEL_1_1_net_1));
    SLE pwrite (.D(eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE), 
        .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWRITE));
    SLE \pwdata[6]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[6]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[6]));
    CFG4 #( .INIT(16'hFFEA) )  \prdata_0_iv[0]  (.A(
        \prdata_0_iv_0[0]_net_1 ), .B(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[0]), .C(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .D(\control_reg_1_m[0] ), 
        .Y(\prdata[0] ));
    SLE \paddr[12]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_10), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(\paddr[12]_net_1 ));
    CFG4 #( .INIT(16'h2000) )  int_prdata_5_sqmuxa (.A(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2), .B(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1), .C(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0), .D(
        un1_R_SDIF3_PSEL_1_1_net_1), .Y(int_prdata_5_sqmuxa_net_1));
    SLE \paddr[13]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_11), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(\paddr[13]_net_1 ));
    SLE FIC_2_APB_M_PSLVERR (.D(pslverr), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PSLVERR));
    SLE \FIC_2_APB_M_PRDATA[17]  (.D(int_prdata_5_sqmuxa_net_1), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_18));
    SLE \FIC_2_APB_M_PRDATA[7]  (.D(\prdata[7] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_7));
    CFG4 #( .INIT(16'hECA0) )  \prdata_0_iv[14]  (.A(
        \soft_reset_reg[14]_net_1 ), .B(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .C(
        int_prdata_4_sqmuxa_net_1), .D(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[14]), .Y(\prdata[14] ));
    SLE \soft_reset_reg[0]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[0]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6_net_1), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[0]_net_1 ));
    SLE \pwdata[2]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[2]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[2]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_0_iv[2]  (.A(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .B(
        CORECONFIGP_0_SOFT_M3_RESET), .C(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[2]), .D(
        int_prdata_4_sqmuxa_net_1), .Y(\prdata[2] ));
    SLE \FIC_2_APB_M_PRDATA[0]  (.D(\prdata[0] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_0));
    CFG4 #( .INIT(16'hCECC) )  \state_ns_0[1]  (.A(\state[1]_net_1 ), 
        .B(\state[0]_net_1 ), .C(CORECONFIGP_0_MDDR_APBmslave_PREADY), 
        .D(CORECONFIGP_0_MDDR_APBmslave_PSELx), .Y(\state_ns[1] ));
    CFG4 #( .INIT(16'hECA0) )  \prdata_0_iv[3]  (.A(
        \soft_reset_reg[3]_net_1 ), .B(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .C(
        int_prdata_4_sqmuxa_net_1), .D(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[3]), .Y(\prdata[3] ));
    CFG4 #( .INIT(16'hEAEE) )  un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0 
        (.A(\state_ns[0] ), .B(\state[1]_net_1 ), .C(
        CORECONFIGP_0_MDDR_APBmslave_PREADY), .D(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .Y(
        un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_net_1));
    SLE \soft_reset_reg[15]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[15]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6_net_1), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[15]_net_1 ));
    CFG2 #( .INIT(4'h7) )  \prdata_0_iv_1[5]  (.A(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[5]), .B(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .Y(
        \prdata_0_iv_1[5]_net_1 ));
    SLE \paddr[7]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_5), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[7]));
    SLE \FIC_2_APB_M_PRDATA[3]  (.D(\prdata[3] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_3));
    CFG4 #( .INIT(16'hECA0) )  \prdata_0_iv[9]  (.A(
        \soft_reset_reg[9]_net_1 ), .B(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .C(
        int_prdata_4_sqmuxa_net_1), .D(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[9]), .Y(\prdata[9] ));
    SLE \FIC_2_APB_M_PRDATA[6]  (.D(\prdata[6] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_6));
    CFG4 #( .INIT(16'hFFB3) )  \prdata_0_iv[5]  (.A(
        int_prdata_4_sqmuxa_net_1), .B(\prdata_0_iv_1[5]_net_1 ), .C(
        \soft_reset_reg[5]_net_1 ), .D(int_prdata_3_sqmuxa_net_1), .Y(
        \prdata[5] ));
    CFG4 #( .INIT(16'hC888) )  \prdata_0_iv_0[0]  (.A(INIT_DONE_q2_m_1)
        , .B(un1_R_SDIF3_PSEL_1_1_net_1), .C(int_prdata19_net_1), .D(
        \soft_reset_reg[0]_net_1 ), .Y(\prdata_0_iv_0[0]_net_1 ));
    CFG4 #( .INIT(16'hECA0) )  \prdata_0_iv[13]  (.A(
        \soft_reset_reg[13]_net_1 ), .B(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .C(
        int_prdata_4_sqmuxa_net_1), .D(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[13]), .Y(\prdata[13] ));
    SLE \paddr[6]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_4), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[6]));
    SLE \control_reg_1[1]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[1]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(control_reg_15_net_1), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_CONFIG2_DONE));
    SLE \pwdata[11]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[11]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[11]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_0_iv[15]  (.A(
        \soft_reset_reg[15]_net_1 ), .B(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .C(
        int_prdata_4_sqmuxa_net_1), .D(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[15]), .Y(\prdata[15] ));
    GND GND (.Y(GND_net_1));
    SLE \soft_reset_reg[3]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[3]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6_net_1), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[3]_net_1 ));
    SLE \soft_reset_reg[12]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[12]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6_net_1), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[12]_net_1 ));
    CFG2 #( .INIT(4'h8) )  FIC_2_APB_M_PSLVERR_RNO (.A(
        CORECONFIGP_0_MDDR_APBmslave_PSLVERR), .B(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .Y(pslverr));
    SLE \state[0]  (.D(\state_ns[0] ), .CLK(CORECONFIGP_0_APB_S_PCLK), 
        .EN(VCC_net_1), .ALn(CORECONFIGP_0_APB_S_PRESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\state[0]_net_1 ));
    CFG4 #( .INIT(16'hECA0) )  \prdata_0_iv[4]  (.A(
        \soft_reset_reg[4]_net_1 ), .B(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .C(
        int_prdata_4_sqmuxa_net_1), .D(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[4]), .Y(\prdata[4] ));
    SLE \pwdata[14]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[14]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[14]));
    CFG3 #( .INIT(8'h80) )  \prdata_0_iv_RNO[1]  (.A(
        un1_R_SDIF3_PSEL_1_1_net_1), .B(int_prdata15_net_1), .C(
        CORECONFIGP_0_CONFIG2_DONE), .Y(\control_reg_1_m[1] ));
    CFG4 #( .INIT(16'h0100) )  MDDR_PENABLE_2 (.A(\paddr[12]_net_1 ), 
        .B(\paddr[15]_net_1 ), .C(\paddr[13]_net_1 ), .D(
        \state[1]_net_1 ), .Y(MDDR_PENABLE_2_net_1));
    SLE \soft_reset_reg[4]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[4]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6_net_1), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[4]_net_1 ));
    CFG4 #( .INIT(16'h8000) )  soft_reset_reg6 (.A(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE), .B(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE), .C(
        int_psel_net_1), .D(int_prdata19_net_1), .Y(
        soft_reset_reg6_net_1));
    CFG2 #( .INIT(4'h1) )  state_s0_0_a2 (.A(\state[1]_net_1 ), .B(
        \state[0]_net_1 ), .Y(state_419_d));
    CFG4 #( .INIT(16'hFFEC) )  \prdata_0_iv[1]  (.A(
        CORECONFIGP_0_SOFT_RESET_F2M), .B(\control_reg_1_m[1] ), .C(
        int_prdata_4_sqmuxa_net_1), .D(\MDDR_PRDATA_m[1] ), .Y(
        \prdata[1] ));
    SLE \soft_reset_reg[8]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[8]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6_net_1), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[8]_net_1 ));
    CFG4 #( .INIT(16'hECA0) )  \prdata_0_iv[8]  (.A(
        \soft_reset_reg[8]_net_1 ), .B(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .C(
        int_prdata_4_sqmuxa_net_1), .D(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[8]), .Y(\prdata[8] ));
    SLE MDDR_PENABLE (.D(MDDR_PENABLE_2_net_1), .CLK(
        CORECONFIGP_0_APB_S_PCLK_i_0), .EN(VCC_net_1), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PENABLE));
    SLE \FIC_2_APB_M_PRDATA[12]  (.D(\prdata[12] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_12));
    SLE \FIC_2_APB_M_PRDATA[16]  (.D(\prdata[16] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_16));
    CFG4 #( .INIT(16'h8000) )  control_reg_15 (.A(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE), .B(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE), .C(
        int_psel_net_1), .D(int_prdata15_net_1), .Y(
        control_reg_15_net_1));
    CFG4 #( .INIT(16'hECA0) )  \prdata_0_iv[6]  (.A(
        \soft_reset_reg[6]_net_1 ), .B(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .C(
        int_prdata_4_sqmuxa_net_1), .D(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[6]), .Y(\prdata[6] ));
    CFG3 #( .INIT(8'h02) )  int_prdata19 (.A(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2), .B(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1), .C(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0), .Y(
        int_prdata19_net_1));
    SLE \FIC_2_APB_M_PRDATA[2]  (.D(\prdata[2] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_2));
    SLE \pwdata[10]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[10]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[10]));
    CFG4 #( .INIT(16'hECA0) )  \prdata_0_iv[7]  (.A(
        \soft_reset_reg[7]_net_1 ), .B(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .C(
        int_prdata_4_sqmuxa_net_1), .D(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[7]), .Y(\prdata[7] ));
    CFG4 #( .INIT(16'h0100) )  MDDR_PSEL (.A(\paddr[12]_net_1 ), .B(
        \paddr[15]_net_1 ), .C(\paddr[13]_net_1 ), .D(psel_net_1), .Y(
        CORECONFIGP_0_MDDR_APBmslave_PSELx));
    SLE INIT_DONE_q2 (.D(INIT_DONE_q1_net_1), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(VCC_net_1), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(INIT_DONE_q2_net_1));
    SLE \state[1]  (.D(\state_ns[1] ), .CLK(CORECONFIGP_0_APB_S_PCLK), 
        .EN(VCC_net_1), .ALn(CORECONFIGP_0_APB_S_PRESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\state[1]_net_1 ));
    SLE \soft_reset_reg[6]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[6]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6_net_1), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[6]_net_1 ));
    SLE \FIC_2_APB_M_PRDATA[8]  (.D(\prdata[8] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_8));
    CFG3 #( .INIT(8'h01) )  int_prdata15 (.A(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2), .B(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1), .C(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0), .Y(
        int_prdata15_net_1));
    SLE \FIC_2_APB_M_PRDATA[4]  (.D(\prdata[4] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_4));
    CFG2 #( .INIT(4'h8) )  \prdata_0_iv_RNO_0[1]  (.A(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[1]), .B(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .Y(\MDDR_PRDATA_m[1] ));
    CFG4 #( .INIT(16'h1000) )  int_prdata_4_sqmuxa (.A(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0), .B(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1), .C(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2), .D(
        un1_R_SDIF3_PSEL_1_1_net_1), .Y(int_prdata_4_sqmuxa_net_1));
    SLE \soft_reset_reg[7]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[7]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6_net_1), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[7]_net_1 ));
    SLE \soft_reset_reg[11]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[11]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6_net_1), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[11]_net_1 ));
    SLE \paddr[4]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[4]));
    SLE \pwdata[12]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[12]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[12]));
    SLE \paddr[9]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_7), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[9]));
    CFG3 #( .INIT(8'h20) )  un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_a3 
        (.A(eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PSELx), .B(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE), .C(
        state_419_d), .Y(\state_ns[0] ));
    SLE \soft_reset_reg[1]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[1]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6_net_1), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_SOFT_RESET_F2M));
    CFG1 #( .INIT(2'h1) )  \soft_reset_reg_RNIS5Q2[2]  (.A(
        CORECONFIGP_0_SOFT_M3_RESET), .Y(
        CORECONFIGP_0_SOFT_M3_RESET_i_0));
    SLE \soft_reset_reg[16]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[16]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6_net_1), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[16]_net_1 ));
    SLE \pwdata[0]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[0]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[0]));
    CFG3 #( .INIT(8'h80) )  \prdata_0_iv_RNO[0]  (.A(
        un1_R_SDIF3_PSEL_1_1_net_1), .B(int_prdata15_net_1), .C(
        CORECONFIGP_0_CONFIG1_DONE), .Y(\control_reg_1_m[0] ));
    SLE \pwdata[4]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[4]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[4]));
    CFG3 #( .INIT(8'h08) )  int_psel (.A(\paddr[13]_net_1 ), .B(
        psel_net_1), .C(\paddr[15]_net_1 ), .Y(int_psel_net_1));
    SLE \FIC_2_APB_M_PRDATA[15]  (.D(\prdata[15] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_15));
    SLE \paddr[2]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[2]));
    SLE \paddr[10]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_8), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[10]));
    CFG2 #( .INIT(4'hE) )  state_s0_0_a2_i (.A(\state[1]_net_1 ), .B(
        \state[0]_net_1 ), .Y(state_419_d_i_0));
    SLE \FIC_2_APB_M_PRDATA[1]  (.D(\prdata[1] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_1));
    SLE \soft_reset_reg[14]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[14]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6_net_1), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[14]_net_1 ));
    SLE \paddr[15]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_13), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_419_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(\paddr[15]_net_1 ));
    SLE \FIC_2_APB_M_PRDATA[10]  (.D(\prdata[10] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_10));
    SLE \soft_reset_reg[5]  (.D(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[5]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6_net_1), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[5]_net_1 ));
    
endmodule


module eNVM_DataClient_MSS(
       MDDR_DQS,
       MDDR_DQ,
       MDDR_DM_RDQS,
       MDDR_BA,
       MDDR_ADDR,
       CORECONFIGP_0_MDDR_APBmslave_PRDATA,
       CORECONFIGP_0_MDDR_APBmslave_PADDR,
       CORECONFIGP_0_MDDR_APBmslave_PWDATA,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_3,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_4,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_5,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_6,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_7,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_8,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_10,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_11,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_13,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_0,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_1,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_2,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_3,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_4,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_5,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_6,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_7,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_8,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_9,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_10,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_11,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_12,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_13,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_14,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_15,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_16,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_0,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_1,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_2,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_3,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_4,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_5,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_6,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_7,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_8,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_9,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_10,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_11,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_12,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_13,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_14,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_15,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_16,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_18,
       CORECONFIGP_0_APB_S_PCLK,
       CORECONFIGP_0_APB_S_PRESET_N,
       CORECONFIGP_0_APB_S_PCLK_i_0,
       MMUART_1_TXD,
       MMUART_1_RXD,
       MDDR_WE_N,
       MDDR_RESET_N,
       MDDR_RAS_N,
       MDDR_ODT,
       MDDR_DQS_TMATCH_0_OUT,
       MDDR_DQS_TMATCH_0_IN,
       MDDR_CS_N,
       MDDR_CKE,
       MDDR_CAS_N,
       eNVM_DataClient_MSS_TMP_0_MSS_RESET_N_M2F,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PSELx,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE,
       CORECONFIGP_0_MDDR_APBmslave_PREADY,
       CORECONFIGP_0_MDDR_APBmslave_PSLVERR,
       CORECONFIGP_0_SOFT_M3_RESET_i_0,
       LOCK,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PREADY,
       eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PSLVERR,
       CORECONFIGP_0_SOFT_RESET_F2M_i_0,
       GL0_INST,
       CORECONFIGP_0_MDDR_APBmslave_PENABLE,
       CORECONFIGP_0_MDDR_APBmslave_PSELx,
       CORECONFIGP_0_MDDR_APBmslave_PWRITE,
       MDDR_CLK_N,
       MDDR_CLK
    );
inout  [1:0] MDDR_DQS;
inout  [15:0] MDDR_DQ;
inout  [1:0] MDDR_DM_RDQS;
output [2:0] MDDR_BA;
output [15:0] MDDR_ADDR;
output [15:0] CORECONFIGP_0_MDDR_APBmslave_PRDATA;
input  [10:2] CORECONFIGP_0_MDDR_APBmslave_PADDR;
input  [15:0] CORECONFIGP_0_MDDR_APBmslave_PWDATA;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_3;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_4;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_5;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_6;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_7;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_8;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_10;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_11;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_13;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_0;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_1;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_2;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_3;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_4;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_5;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_6;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_7;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_8;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_9;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_10;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_11;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_12;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_13;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_14;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_15;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_16;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_0;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_1;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_2;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_3;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_4;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_5;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_6;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_7;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_8;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_9;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_10;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_11;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_12;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_13;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_14;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_15;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_16;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_18;
output CORECONFIGP_0_APB_S_PCLK;
output CORECONFIGP_0_APB_S_PRESET_N;
output CORECONFIGP_0_APB_S_PCLK_i_0;
output MMUART_1_TXD;
input  MMUART_1_RXD;
output MDDR_WE_N;
output MDDR_RESET_N;
output MDDR_RAS_N;
output MDDR_ODT;
output MDDR_DQS_TMATCH_0_OUT;
input  MDDR_DQS_TMATCH_0_IN;
output MDDR_CS_N;
output MDDR_CKE;
output MDDR_CAS_N;
output eNVM_DataClient_MSS_TMP_0_MSS_RESET_N_M2F;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PSELx;
output eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE;
output CORECONFIGP_0_MDDR_APBmslave_PREADY;
output CORECONFIGP_0_MDDR_APBmslave_PSLVERR;
input  CORECONFIGP_0_SOFT_M3_RESET_i_0;
input  LOCK;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PREADY;
input  eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PSLVERR;
input  CORECONFIGP_0_SOFT_RESET_F2M_i_0;
input  GL0_INST;
input  CORECONFIGP_0_MDDR_APBmslave_PENABLE;
input  CORECONFIGP_0_MDDR_APBmslave_PSELx;
input  CORECONFIGP_0_MDDR_APBmslave_PWRITE;
output MDDR_CLK_N;
output MDDR_CLK;

    wire FIC_2_APB_M_PCLK, CONFIG_PRESET_N, 
        MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT, 
        MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OE, 
        MMUART_1_RXD_PAD_Y, MSS_ADLIB_INST_DRAM_WEN, 
        MSS_ADLIB_INST_DRAM_RSTN, MSS_ADLIB_INST_DRAM_RASN, 
        MSS_ADLIB_INST_DRAM_ODT, \DRAM_FIFO_WE_OUT_net_0[0] , 
        MDDR_DQS_TMATCH_0_IN_PAD_Y, MDDR_DQS_1_PAD_Y, 
        \DRAM_DQS_OUT_net_0[1] , \DRAM_DQS_OE_net_0[1] , 
        MDDR_DQS_0_PAD_Y, \DRAM_DQS_OUT_net_0[0] , 
        \DRAM_DQS_OE_net_0[0] , MDDR_DQ_15_PAD_Y, 
        \DRAM_DQ_OUT_net_0[15] , \DRAM_DQ_OE_net_0[15] , 
        MDDR_DQ_14_PAD_Y, \DRAM_DQ_OUT_net_0[14] , 
        \DRAM_DQ_OE_net_0[14] , MDDR_DQ_13_PAD_Y, 
        \DRAM_DQ_OUT_net_0[13] , \DRAM_DQ_OE_net_0[13] , 
        MDDR_DQ_12_PAD_Y, \DRAM_DQ_OUT_net_0[12] , 
        \DRAM_DQ_OE_net_0[12] , MDDR_DQ_11_PAD_Y, 
        \DRAM_DQ_OUT_net_0[11] , \DRAM_DQ_OE_net_0[11] , 
        MDDR_DQ_10_PAD_Y, \DRAM_DQ_OUT_net_0[10] , 
        \DRAM_DQ_OE_net_0[10] , MDDR_DQ_9_PAD_Y, 
        \DRAM_DQ_OUT_net_0[9] , \DRAM_DQ_OE_net_0[9] , MDDR_DQ_8_PAD_Y, 
        \DRAM_DQ_OUT_net_0[8] , \DRAM_DQ_OE_net_0[8] , MDDR_DQ_7_PAD_Y, 
        \DRAM_DQ_OUT_net_0[7] , \DRAM_DQ_OE_net_0[7] , MDDR_DQ_6_PAD_Y, 
        \DRAM_DQ_OUT_net_0[6] , \DRAM_DQ_OE_net_0[6] , MDDR_DQ_5_PAD_Y, 
        \DRAM_DQ_OUT_net_0[5] , \DRAM_DQ_OE_net_0[5] , MDDR_DQ_4_PAD_Y, 
        \DRAM_DQ_OUT_net_0[4] , \DRAM_DQ_OE_net_0[4] , MDDR_DQ_3_PAD_Y, 
        \DRAM_DQ_OUT_net_0[3] , \DRAM_DQ_OE_net_0[3] , MDDR_DQ_2_PAD_Y, 
        \DRAM_DQ_OUT_net_0[2] , \DRAM_DQ_OE_net_0[2] , MDDR_DQ_1_PAD_Y, 
        \DRAM_DQ_OUT_net_0[1] , \DRAM_DQ_OE_net_0[1] , MDDR_DQ_0_PAD_Y, 
        \DRAM_DQ_OUT_net_0[0] , \DRAM_DQ_OE_net_0[0] , 
        MDDR_DM_RDQS_1_PAD_Y, \DRAM_DM_RDQS_OUT_net_0[1] , 
        \DM_OE_net_0[1] , MDDR_DM_RDQS_0_PAD_Y, 
        \DRAM_DM_RDQS_OUT_net_0[0] , \DM_OE_net_0[0] , 
        MSS_ADLIB_INST_DRAM_CSN, MSS_ADLIB_INST_DRAM_CKE, 
        MSS_ADLIB_INST_DRAM_CASN, \DRAM_BA_net_0[2] , 
        \DRAM_BA_net_0[1] , \DRAM_BA_net_0[0] , \DRAM_ADDR_net_0[15] , 
        \DRAM_ADDR_net_0[14] , \DRAM_ADDR_net_0[13] , 
        \DRAM_ADDR_net_0[12] , \DRAM_ADDR_net_0[11] , 
        \DRAM_ADDR_net_0[10] , \DRAM_ADDR_net_0[9] , 
        \DRAM_ADDR_net_0[8] , \DRAM_ADDR_net_0[7] , 
        \DRAM_ADDR_net_0[6] , \DRAM_ADDR_net_0[5] , 
        \DRAM_ADDR_net_0[4] , \DRAM_ADDR_net_0[3] , 
        \DRAM_ADDR_net_0[2] , \DRAM_ADDR_net_0[1] , 
        \DRAM_ADDR_net_0[0] , VCC_net_1, GND_net_1, 
        MSS_ADLIB_INST_DRAM_CLK;
    
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_6_PAD (.D(
        \DRAM_ADDR_net_0[6] ), .PAD(MDDR_ADDR[6]));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_CAS_N_PAD (.D(
        MSS_ADLIB_INST_DRAM_CASN), .PAD(MDDR_CAS_N));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_RESET_N_PAD (.D(
        MSS_ADLIB_INST_DRAM_RSTN), .PAD(MDDR_RESET_N));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ODT_PAD (.D(
        MSS_ADLIB_INST_DRAM_ODT), .PAD(MDDR_ODT));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_11_PAD (.D(
        \DRAM_ADDR_net_0[11] ), .PAD(MDDR_ADDR[11]));
    TRIBUFF MMUART_1_TXD_PAD (.D(
        MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT), .E(
        MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OE), .PAD(
        MMUART_1_TXD));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_10_PAD (.PAD(MDDR_DQ[10]), .D(
        \DRAM_DQ_OUT_net_0[10] ), .E(\DRAM_DQ_OE_net_0[10] ), .Y(
        MDDR_DQ_10_PAD_Y));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_1_PAD (.PAD(MDDR_DQ[1]), .D(
        \DRAM_DQ_OUT_net_0[1] ), .E(\DRAM_DQ_OE_net_0[1] ), .Y(
        MDDR_DQ_1_PAD_Y));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_7_PAD (.D(
        \DRAM_ADDR_net_0[7] ), .PAD(MDDR_ADDR[7]));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_11_PAD (.PAD(MDDR_DQ[11]), .D(
        \DRAM_DQ_OUT_net_0[11] ), .E(\DRAM_DQ_OE_net_0[11] ), .Y(
        MDDR_DQ_11_PAD_Y));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_9_PAD (.PAD(MDDR_DQ[9]), .D(
        \DRAM_DQ_OUT_net_0[9] ), .E(\DRAM_DQ_OE_net_0[9] ), .Y(
        MDDR_DQ_9_PAD_Y));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_3_PAD (.PAD(MDDR_DQ[3]), .D(
        \DRAM_DQ_OUT_net_0[3] ), .E(\DRAM_DQ_OE_net_0[3] ), .Y(
        MDDR_DQ_3_PAD_Y));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_0_PAD (.PAD(MDDR_DQ[0]), .D(
        \DRAM_DQ_OUT_net_0[0] ), .E(\DRAM_DQ_OE_net_0[0] ), .Y(
        MDDR_DQ_0_PAD_Y));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_12_PAD (.D(
        \DRAM_ADDR_net_0[12] ), .PAD(MDDR_ADDR[12]));
    VCC VCC (.Y(VCC_net_1));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_2_PAD (.PAD(MDDR_DQ[2]), .D(
        \DRAM_DQ_OUT_net_0[2] ), .E(\DRAM_DQ_OE_net_0[2] ), .Y(
        MDDR_DQ_2_PAD_Y));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_12_PAD (.PAD(MDDR_DQ[12]), .D(
        \DRAM_DQ_OUT_net_0[12] ), .E(\DRAM_DQ_OE_net_0[12] ), .Y(
        MDDR_DQ_12_PAD_Y));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_CKE_PAD (.D(
        MSS_ADLIB_INST_DRAM_CKE), .PAD(MDDR_CKE));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_2_PAD (.D(
        \DRAM_ADDR_net_0[2] ), .PAD(MDDR_ADDR[2]));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_13_PAD (.D(
        \DRAM_ADDR_net_0[13] ), .PAD(MDDR_ADDR[13]));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_5_PAD (.D(
        \DRAM_ADDR_net_0[5] ), .PAD(MDDR_ADDR[5]));
    CLKINT FIC_2_APB_M_PCLK_inferred_clock_RNIBR72 (.A(
        FIC_2_APB_M_PCLK), .Y(CORECONFIGP_0_APB_S_PCLK));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DM_RDQS_1_PAD (.PAD(
        MDDR_DM_RDQS[1]), .D(\DRAM_DM_RDQS_OUT_net_0[1] ), .E(
        \DM_OE_net_0[1] ), .Y(MDDR_DM_RDQS_1_PAD_Y));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQS_0_PAD (.PAD(MDDR_DQS[0]), .D(
        \DRAM_DQS_OUT_net_0[0] ), .E(\DRAM_DQS_OE_net_0[0] ), .Y(
        MDDR_DQS_0_PAD_Y));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQS_1_PAD (.PAD(MDDR_DQS[1]), .D(
        \DRAM_DQS_OUT_net_0[1] ), .E(\DRAM_DQS_OE_net_0[1] ), .Y(
        MDDR_DQS_1_PAD_Y));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_15_PAD (.PAD(MDDR_DQ[15]), .D(
        \DRAM_DQ_OUT_net_0[15] ), .E(\DRAM_DQ_OE_net_0[15] ), .Y(
        MDDR_DQ_15_PAD_Y));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DM_RDQS_0_PAD (.PAD(
        MDDR_DM_RDQS[0]), .D(\DRAM_DM_RDQS_OUT_net_0[0] ), .E(
        \DM_OE_net_0[0] ), .Y(MDDR_DM_RDQS_0_PAD_Y));
    GND GND (.Y(GND_net_1));
    CFG1 #( .INIT(2'h1) )  FIC_2_APB_M_PCLK_inferred_clock_RNIBR72_0 (
        .A(CORECONFIGP_0_APB_S_PCLK), .Y(CORECONFIGP_0_APB_S_PCLK_i_0));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_8_PAD (.PAD(MDDR_DQ[8]), .D(
        \DRAM_DQ_OUT_net_0[8] ), .E(\DRAM_DQ_OE_net_0[8] ), .Y(
        MDDR_DQ_8_PAD_Y));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_9_PAD (.D(
        \DRAM_ADDR_net_0[9] ), .PAD(MDDR_ADDR[9]));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_BA_2_PAD (.D(\DRAM_BA_net_0[2] )
        , .PAD(MDDR_BA[2]));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_14_PAD (.D(
        \DRAM_ADDR_net_0[14] ), .PAD(MDDR_ADDR[14]));
    MSS_075 #( .INIT(1438'h00000000000000000000000000000036100080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000F00000000F000000000000000000000000000000007FFFFFFFB000001007C33F00020400E08454CC4003FFFFE400000000000040000000000F01C0000007EDFBC010842108421000001FE34001FF8000000400000000000AB1007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
        , .ACT_UBITS(56'hFFFFFFFFFFFFFF), .MEMORYFILE("ENVM_init.mem")
        , .RTC_MAIN_XTL_FREQ(0.0), .RTC_MAIN_XTL_MODE(""), .DDR_CLK_FREQ(333.0)
         )  MSS_ADLIB_INST (.CAN_RXBUS_MGPIO3A_H2F_A(), 
        .CAN_RXBUS_MGPIO3A_H2F_B(), .CAN_TX_EBL_MGPIO4A_H2F_A(), 
        .CAN_TX_EBL_MGPIO4A_H2F_B(), .CAN_TXBUS_MGPIO2A_H2F_A(), 
        .CAN_TXBUS_MGPIO2A_H2F_B(), .CLK_CONFIG_APB(FIC_2_APB_M_PCLK), 
        .COMMS_INT(), .CONFIG_PRESET_N(CONFIG_PRESET_N), .EDAC_ERROR({
        nc0, nc1, nc2, nc3, nc4, nc5, nc6, nc7}), .F_FM0_RDATA({nc8, 
        nc9, nc10, nc11, nc12, nc13, nc14, nc15, nc16, nc17, nc18, 
        nc19, nc20, nc21, nc22, nc23, nc24, nc25, nc26, nc27, nc28, 
        nc29, nc30, nc31, nc32, nc33, nc34, nc35, nc36, nc37, nc38, 
        nc39}), .F_FM0_READYOUT(), .F_FM0_RESP(), .F_HM0_ADDR({nc40, 
        nc41, nc42, nc43, nc44, nc45, nc46, nc47, nc48, nc49, nc50, 
        nc51, nc52, nc53, nc54, nc55, nc56, nc57, nc58, nc59, nc60, 
        nc61, nc62, nc63, nc64, nc65, nc66, nc67, nc68, nc69, nc70, 
        nc71}), .F_HM0_ENABLE(), .F_HM0_SEL(), .F_HM0_SIZE({nc72, nc73})
        , .F_HM0_TRANS1(), .F_HM0_WDATA({nc74, nc75, nc76, nc77, nc78, 
        nc79, nc80, nc81, nc82, nc83, nc84, nc85, nc86, nc87, nc88, 
        nc89, nc90, nc91, nc92, nc93, nc94, nc95, nc96, nc97, nc98, 
        nc99, nc100, nc101, nc102, nc103, nc104, nc105}), .F_HM0_WRITE(
        ), .FAB_CHRGVBUS(), .FAB_DISCHRGVBUS(), .FAB_DMPULLDOWN(), 
        .FAB_DPPULLDOWN(), .FAB_DRVVBUS(), .FAB_IDPULLUP(), 
        .FAB_OPMODE({nc106, nc107}), .FAB_SUSPENDM(), .FAB_TERMSEL(), 
        .FAB_TXVALID(), .FAB_VCONTROL({nc108, nc109, nc110, nc111}), 
        .FAB_VCONTROLLOADM(), .FAB_XCVRSEL({nc112, nc113}), 
        .FAB_XDATAOUT({nc114, nc115, nc116, nc117, nc118, nc119, nc120, 
        nc121}), .FACC_GLMUX_SEL(), .FIC32_0_MASTER({nc122, nc123}), 
        .FIC32_1_MASTER({nc124, nc125}), .FPGA_RESET_N(
        eNVM_DataClient_MSS_TMP_0_MSS_RESET_N_M2F), .GTX_CLK(), 
        .H2F_INTERRUPT({nc126, nc127, nc128, nc129, nc130, nc131, 
        nc132, nc133, nc134, nc135, nc136, nc137, nc138, nc139, nc140, 
        nc141}), .H2F_NMI(), .H2FCALIB(), .I2C0_SCL_MGPIO31B_H2F_A(), 
        .I2C0_SCL_MGPIO31B_H2F_B(), .I2C0_SDA_MGPIO30B_H2F_A(), 
        .I2C0_SDA_MGPIO30B_H2F_B(), .I2C1_SCL_MGPIO1A_H2F_A(), 
        .I2C1_SCL_MGPIO1A_H2F_B(), .I2C1_SDA_MGPIO0A_H2F_A(), 
        .I2C1_SDA_MGPIO0A_H2F_B(), .MDCF(), .MDOENF(), .MDOF(), 
        .MMUART0_CTS_MGPIO19B_H2F_A(), .MMUART0_CTS_MGPIO19B_H2F_B(), 
        .MMUART0_DCD_MGPIO22B_H2F_A(), .MMUART0_DCD_MGPIO22B_H2F_B(), 
        .MMUART0_DSR_MGPIO20B_H2F_A(), .MMUART0_DSR_MGPIO20B_H2F_B(), 
        .MMUART0_DTR_MGPIO18B_H2F_A(), .MMUART0_DTR_MGPIO18B_H2F_B(), 
        .MMUART0_RI_MGPIO21B_H2F_A(), .MMUART0_RI_MGPIO21B_H2F_B(), 
        .MMUART0_RTS_MGPIO17B_H2F_A(), .MMUART0_RTS_MGPIO17B_H2F_B(), 
        .MMUART0_RXD_MGPIO28B_H2F_A(), .MMUART0_RXD_MGPIO28B_H2F_B(), 
        .MMUART0_SCK_MGPIO29B_H2F_A(), .MMUART0_SCK_MGPIO29B_H2F_B(), 
        .MMUART0_TXD_MGPIO27B_H2F_A(), .MMUART0_TXD_MGPIO27B_H2F_B(), 
        .MMUART1_DTR_MGPIO12B_H2F_A(), .MMUART1_RTS_MGPIO11B_H2F_A(), 
        .MMUART1_RTS_MGPIO11B_H2F_B(), .MMUART1_RXD_MGPIO26B_H2F_A(), 
        .MMUART1_RXD_MGPIO26B_H2F_B(), .MMUART1_SCK_MGPIO25B_H2F_A(), 
        .MMUART1_SCK_MGPIO25B_H2F_B(), .MMUART1_TXD_MGPIO24B_H2F_A(), 
        .MMUART1_TXD_MGPIO24B_H2F_B(), .MPLL_LOCK(), 
        .PER2_FABRIC_PADDR({
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_13, nc142, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_11, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_10, nc143, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_8, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_7, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_6, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_5, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_4, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_3, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0}), 
        .PER2_FABRIC_PENABLE(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE), 
        .PER2_FABRIC_PSEL(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PSELx), 
        .PER2_FABRIC_PWDATA({nc144, nc145, nc146, nc147, nc148, nc149, 
        nc150, nc151, nc152, nc153, nc154, nc155, nc156, nc157, nc158, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_16, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_15, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_14, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_13, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_12, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_11, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_10, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_9, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_8, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_7, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_6, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_5, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_4, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_3, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_2, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_1, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_0}), 
        .PER2_FABRIC_PWRITE(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE), .RTC_MATCH(
        ), .SLEEPDEEP(), .SLEEPHOLDACK(), .SLEEPING(), .SMBALERT_NO0(), 
        .SMBALERT_NO1(), .SMBSUS_NO0(), .SMBSUS_NO1(), .SPI0_CLK_OUT(), 
        .SPI0_SDI_MGPIO5A_H2F_A(), .SPI0_SDI_MGPIO5A_H2F_B(), 
        .SPI0_SDO_MGPIO6A_H2F_A(), .SPI0_SDO_MGPIO6A_H2F_B(), 
        .SPI0_SS0_MGPIO7A_H2F_A(), .SPI0_SS0_MGPIO7A_H2F_B(), 
        .SPI0_SS1_MGPIO8A_H2F_A(), .SPI0_SS1_MGPIO8A_H2F_B(), 
        .SPI0_SS2_MGPIO9A_H2F_A(), .SPI0_SS2_MGPIO9A_H2F_B(), 
        .SPI0_SS3_MGPIO10A_H2F_A(), .SPI0_SS3_MGPIO10A_H2F_B(), 
        .SPI0_SS4_MGPIO19A_H2F_A(), .SPI0_SS5_MGPIO20A_H2F_A(), 
        .SPI0_SS6_MGPIO21A_H2F_A(), .SPI0_SS7_MGPIO22A_H2F_A(), 
        .SPI1_CLK_OUT(), .SPI1_SDI_MGPIO11A_H2F_A(), 
        .SPI1_SDI_MGPIO11A_H2F_B(), .SPI1_SDO_MGPIO12A_H2F_A(), 
        .SPI1_SDO_MGPIO12A_H2F_B(), .SPI1_SS0_MGPIO13A_H2F_A(), 
        .SPI1_SS0_MGPIO13A_H2F_B(), .SPI1_SS1_MGPIO14A_H2F_A(), 
        .SPI1_SS1_MGPIO14A_H2F_B(), .SPI1_SS2_MGPIO15A_H2F_A(), 
        .SPI1_SS2_MGPIO15A_H2F_B(), .SPI1_SS3_MGPIO16A_H2F_A(), 
        .SPI1_SS3_MGPIO16A_H2F_B(), .SPI1_SS4_MGPIO17A_H2F_A(), 
        .SPI1_SS5_MGPIO18A_H2F_A(), .SPI1_SS6_MGPIO23A_H2F_A(), 
        .SPI1_SS7_MGPIO24A_H2F_A(), .TCGF({nc159, nc160, nc161, nc162, 
        nc163, nc164, nc165, nc166, nc167, nc168}), .TRACECLK(), 
        .TRACEDATA({nc169, nc170, nc171, nc172}), .TX_CLK(), .TX_ENF(), 
        .TX_ERRF(), .TXCTL_EN_RIF(), .TXD_RIF({nc173, nc174, nc175, 
        nc176}), .TXDF({nc177, nc178, nc179, nc180, nc181, nc182, 
        nc183, nc184}), .TXEV(), .WDOGTIMEOUT(), .F_ARREADY_HREADYOUT1(
        ), .F_AWREADY_HREADYOUT0(), .F_BID({nc185, nc186, nc187, nc188})
        , .F_BRESP_HRESP0({nc189, nc190}), .F_BVALID(), 
        .F_RDATA_HRDATA01({nc191, nc192, nc193, nc194, nc195, nc196, 
        nc197, nc198, nc199, nc200, nc201, nc202, nc203, nc204, nc205, 
        nc206, nc207, nc208, nc209, nc210, nc211, nc212, nc213, nc214, 
        nc215, nc216, nc217, nc218, nc219, nc220, nc221, nc222, nc223, 
        nc224, nc225, nc226, nc227, nc228, nc229, nc230, nc231, nc232, 
        nc233, nc234, nc235, nc236, nc237, nc238, nc239, nc240, nc241, 
        nc242, nc243, nc244, nc245, nc246, nc247, nc248, nc249, nc250, 
        nc251, nc252, nc253, nc254}), .F_RID({nc255, nc256, nc257, 
        nc258}), .F_RLAST(), .F_RRESP_HRESP1({nc259, nc260}), 
        .F_RVALID(), .F_WREADY(), .MDDR_FABRIC_PRDATA({
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[15], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[14], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[13], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[12], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[11], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[10], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[9], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[8], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[7], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[6], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[5], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[4], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[3], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[2], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[1], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[0]}), .MDDR_FABRIC_PREADY(
        CORECONFIGP_0_MDDR_APBmslave_PREADY), .MDDR_FABRIC_PSLVERR(
        CORECONFIGP_0_MDDR_APBmslave_PSLVERR), .CAN_RXBUS_F2H_SCP(
        VCC_net_1), .CAN_TX_EBL_F2H_SCP(VCC_net_1), .CAN_TXBUS_F2H_SCP(
        VCC_net_1), .COLF(VCC_net_1), .CRSF(VCC_net_1), .F2_DMAREADY({
        VCC_net_1, VCC_net_1}), .F2H_INTERRUPT({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1}), .F2HCALIB(
        VCC_net_1), .F_DMAREADY({VCC_net_1, VCC_net_1}), .F_FM0_ADDR({
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1}), .F_FM0_ENABLE(GND_net_1), 
        .F_FM0_MASTLOCK(GND_net_1), .F_FM0_READY(VCC_net_1), 
        .F_FM0_SEL(GND_net_1), .F_FM0_SIZE({GND_net_1, GND_net_1}), 
        .F_FM0_TRANS1(GND_net_1), .F_FM0_WDATA({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .F_FM0_WRITE(GND_net_1), .F_HM0_RDATA({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .F_HM0_READY(VCC_net_1), .F_HM0_RESP(GND_net_1), .FAB_AVALID(
        VCC_net_1), .FAB_HOSTDISCON(VCC_net_1), .FAB_IDDIG(VCC_net_1), 
        .FAB_LINESTATE({VCC_net_1, VCC_net_1}), .FAB_M3_RESET_N(
        CORECONFIGP_0_SOFT_M3_RESET_i_0), .FAB_PLL_LOCK(LOCK), 
        .FAB_RXACTIVE(VCC_net_1), .FAB_RXERROR(VCC_net_1), 
        .FAB_RXVALID(VCC_net_1), .FAB_RXVALIDH(GND_net_1), 
        .FAB_SESSEND(VCC_net_1), .FAB_TXREADY(VCC_net_1), 
        .FAB_VBUSVALID(VCC_net_1), .FAB_VSTATUS({VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1}), .FAB_XDATAIN({VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .GTX_CLKPF(VCC_net_1), .I2C0_BCLK(VCC_net_1), 
        .I2C0_SCL_F2H_SCP(VCC_net_1), .I2C0_SDA_F2H_SCP(VCC_net_1), 
        .I2C1_BCLK(VCC_net_1), .I2C1_SCL_F2H_SCP(VCC_net_1), 
        .I2C1_SDA_F2H_SCP(VCC_net_1), .MDIF(VCC_net_1), 
        .MGPIO0A_F2H_GPIN(VCC_net_1), .MGPIO10A_F2H_GPIN(VCC_net_1), 
        .MGPIO11A_F2H_GPIN(VCC_net_1), .MGPIO11B_F2H_GPIN(VCC_net_1), 
        .MGPIO12A_F2H_GPIN(VCC_net_1), .MGPIO13A_F2H_GPIN(VCC_net_1), 
        .MGPIO14A_F2H_GPIN(VCC_net_1), .MGPIO15A_F2H_GPIN(VCC_net_1), 
        .MGPIO16A_F2H_GPIN(VCC_net_1), .MGPIO17B_F2H_GPIN(VCC_net_1), 
        .MGPIO18B_F2H_GPIN(VCC_net_1), .MGPIO19B_F2H_GPIN(VCC_net_1), 
        .MGPIO1A_F2H_GPIN(VCC_net_1), .MGPIO20B_F2H_GPIN(VCC_net_1), 
        .MGPIO21B_F2H_GPIN(VCC_net_1), .MGPIO22B_F2H_GPIN(VCC_net_1), 
        .MGPIO24B_F2H_GPIN(VCC_net_1), .MGPIO25B_F2H_GPIN(VCC_net_1), 
        .MGPIO26B_F2H_GPIN(VCC_net_1), .MGPIO27B_F2H_GPIN(VCC_net_1), 
        .MGPIO28B_F2H_GPIN(VCC_net_1), .MGPIO29B_F2H_GPIN(VCC_net_1), 
        .MGPIO2A_F2H_GPIN(VCC_net_1), .MGPIO30B_F2H_GPIN(VCC_net_1), 
        .MGPIO31B_F2H_GPIN(VCC_net_1), .MGPIO3A_F2H_GPIN(VCC_net_1), 
        .MGPIO4A_F2H_GPIN(VCC_net_1), .MGPIO5A_F2H_GPIN(VCC_net_1), 
        .MGPIO6A_F2H_GPIN(VCC_net_1), .MGPIO7A_F2H_GPIN(VCC_net_1), 
        .MGPIO8A_F2H_GPIN(VCC_net_1), .MGPIO9A_F2H_GPIN(VCC_net_1), 
        .MMUART0_CTS_F2H_SCP(VCC_net_1), .MMUART0_DCD_F2H_SCP(
        VCC_net_1), .MMUART0_DSR_F2H_SCP(VCC_net_1), 
        .MMUART0_DTR_F2H_SCP(VCC_net_1), .MMUART0_RI_F2H_SCP(VCC_net_1)
        , .MMUART0_RTS_F2H_SCP(VCC_net_1), .MMUART0_RXD_F2H_SCP(
        VCC_net_1), .MMUART0_SCK_F2H_SCP(VCC_net_1), 
        .MMUART0_TXD_F2H_SCP(VCC_net_1), .MMUART1_CTS_F2H_SCP(
        VCC_net_1), .MMUART1_DCD_F2H_SCP(VCC_net_1), 
        .MMUART1_DSR_F2H_SCP(VCC_net_1), .MMUART1_RI_F2H_SCP(VCC_net_1)
        , .MMUART1_RTS_F2H_SCP(VCC_net_1), .MMUART1_RXD_F2H_SCP(
        VCC_net_1), .MMUART1_SCK_F2H_SCP(VCC_net_1), 
        .MMUART1_TXD_F2H_SCP(VCC_net_1), .PER2_FABRIC_PRDATA({
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_18, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_18, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_16, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_15, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_14, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_13, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_12, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_11, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_10, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_9, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_8, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_7, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_6, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_5, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_4, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_3, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_2, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_1, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_0}), 
        .PER2_FABRIC_PREADY(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PREADY), 
        .PER2_FABRIC_PSLVERR(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PSLVERR), .RCGF({
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .RX_CLKPF(VCC_net_1), .RX_DVF(VCC_net_1), .RX_ERRF(VCC_net_1), 
        .RX_EV(VCC_net_1), .RXDF({VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .SLEEPHOLDREQ(GND_net_1), .SMBALERT_NI0(VCC_net_1), 
        .SMBALERT_NI1(VCC_net_1), .SMBSUS_NI0(VCC_net_1), .SMBSUS_NI1(
        VCC_net_1), .SPI0_CLK_IN(VCC_net_1), .SPI0_SDI_F2H_SCP(
        VCC_net_1), .SPI0_SDO_F2H_SCP(VCC_net_1), .SPI0_SS0_F2H_SCP(
        VCC_net_1), .SPI0_SS1_F2H_SCP(VCC_net_1), .SPI0_SS2_F2H_SCP(
        VCC_net_1), .SPI0_SS3_F2H_SCP(VCC_net_1), .SPI1_CLK_IN(
        VCC_net_1), .SPI1_SDI_F2H_SCP(VCC_net_1), .SPI1_SDO_F2H_SCP(
        VCC_net_1), .SPI1_SS0_F2H_SCP(VCC_net_1), .SPI1_SS1_F2H_SCP(
        VCC_net_1), .SPI1_SS2_F2H_SCP(VCC_net_1), .SPI1_SS3_F2H_SCP(
        VCC_net_1), .TX_CLKPF(VCC_net_1), .USER_MSS_GPIO_RESET_N(
        VCC_net_1), .USER_MSS_RESET_N(CORECONFIGP_0_SOFT_RESET_F2M_i_0)
        , .XCLK_FAB(VCC_net_1), .CLK_BASE(GL0_INST), .CLK_MDDR_APB(
        CORECONFIGP_0_APB_S_PCLK), .F_ARADDR_HADDR1({VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1}), .F_ARBURST_HTRANS1({GND_net_1, GND_net_1}), 
        .F_ARID_HSEL1({GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .F_ARLEN_HBURST1({GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .F_ARLOCK_HMASTLOCK1({GND_net_1, GND_net_1}), .F_ARSIZE_HSIZE1({
        GND_net_1, GND_net_1}), .F_ARVALID_HWRITE1(GND_net_1), 
        .F_AWADDR_HADDR0({VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1}), .F_AWBURST_HTRANS0({
        GND_net_1, GND_net_1}), .F_AWID_HSEL0({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1}), .F_AWLEN_HBURST0({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1}), .F_AWLOCK_HMASTLOCK0({GND_net_1, 
        GND_net_1}), .F_AWSIZE_HSIZE0({GND_net_1, GND_net_1}), 
        .F_AWVALID_HWRITE0(GND_net_1), .F_BREADY(GND_net_1), 
        .F_RMW_AXI(GND_net_1), .F_RREADY(GND_net_1), .F_WDATA_HWDATA01({
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), .F_WID_HREADY01({
        GND_net_1, GND_net_1, GND_net_1, GND_net_1}), .F_WLAST(
        GND_net_1), .F_WSTRB({GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .F_WVALID(GND_net_1), .FPGA_MDDR_ARESET_N(VCC_net_1), 
        .MDDR_FABRIC_PADDR({CORECONFIGP_0_MDDR_APBmslave_PADDR[10], 
        CORECONFIGP_0_MDDR_APBmslave_PADDR[9], 
        CORECONFIGP_0_MDDR_APBmslave_PADDR[8], 
        CORECONFIGP_0_MDDR_APBmslave_PADDR[7], 
        CORECONFIGP_0_MDDR_APBmslave_PADDR[6], 
        CORECONFIGP_0_MDDR_APBmslave_PADDR[5], 
        CORECONFIGP_0_MDDR_APBmslave_PADDR[4], 
        CORECONFIGP_0_MDDR_APBmslave_PADDR[3], 
        CORECONFIGP_0_MDDR_APBmslave_PADDR[2]}), .MDDR_FABRIC_PENABLE(
        CORECONFIGP_0_MDDR_APBmslave_PENABLE), .MDDR_FABRIC_PSEL(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .MDDR_FABRIC_PWDATA({
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[15], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[14], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[13], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[12], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[11], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[10], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[9], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[8], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[7], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[6], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[5], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[4], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[3], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[2], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[1], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[0]}), .MDDR_FABRIC_PWRITE(
        CORECONFIGP_0_MDDR_APBmslave_PWRITE), .PRESET_N(
        CORECONFIGP_0_APB_S_PRESET_N), 
        .CAN_RXBUS_USBA_DATA1_MGPIO3A_IN(GND_net_1), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN(GND_net_1), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_IN(GND_net_1), .DM_IN({GND_net_1, 
        MDDR_DM_RDQS_1_PAD_Y, MDDR_DM_RDQS_0_PAD_Y}), .DRAM_DQ_IN({
        GND_net_1, GND_net_1, MDDR_DQ_15_PAD_Y, MDDR_DQ_14_PAD_Y, 
        MDDR_DQ_13_PAD_Y, MDDR_DQ_12_PAD_Y, MDDR_DQ_11_PAD_Y, 
        MDDR_DQ_10_PAD_Y, MDDR_DQ_9_PAD_Y, MDDR_DQ_8_PAD_Y, 
        MDDR_DQ_7_PAD_Y, MDDR_DQ_6_PAD_Y, MDDR_DQ_5_PAD_Y, 
        MDDR_DQ_4_PAD_Y, MDDR_DQ_3_PAD_Y, MDDR_DQ_2_PAD_Y, 
        MDDR_DQ_1_PAD_Y, MDDR_DQ_0_PAD_Y}), .DRAM_DQS_IN({GND_net_1, 
        MDDR_DQS_1_PAD_Y, MDDR_DQS_0_PAD_Y}), .DRAM_FIFO_WE_IN({
        GND_net_1, MDDR_DQS_TMATCH_0_IN_PAD_Y}), 
        .I2C0_SCL_USBC_DATA1_MGPIO31B_IN(GND_net_1), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_IN(GND_net_1), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_IN(GND_net_1), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_IN(GND_net_1), .MGPIO0B_IN(
        GND_net_1), .MGPIO10B_IN(GND_net_1), .MGPIO1B_IN(GND_net_1), 
        .MGPIO25A_IN(GND_net_1), .MGPIO26A_IN(GND_net_1), .MGPIO27A_IN(
        GND_net_1), .MGPIO28A_IN(GND_net_1), .MGPIO29A_IN(GND_net_1), 
        .MGPIO2B_IN(GND_net_1), .MGPIO30A_IN(GND_net_1), .MGPIO31A_IN(
        GND_net_1), .MGPIO3B_IN(GND_net_1), .MGPIO4B_IN(GND_net_1), 
        .MGPIO5B_IN(GND_net_1), .MGPIO6B_IN(GND_net_1), .MGPIO7B_IN(
        GND_net_1), .MGPIO8B_IN(GND_net_1), .MGPIO9B_IN(GND_net_1), 
        .MMUART0_CTS_USBC_DATA7_MGPIO19B_IN(GND_net_1), 
        .MMUART0_DCD_MGPIO22B_IN(GND_net_1), .MMUART0_DSR_MGPIO20B_IN(
        GND_net_1), .MMUART0_DTR_USBC_DATA6_MGPIO18B_IN(GND_net_1), 
        .MMUART0_RI_MGPIO21B_IN(GND_net_1), 
        .MMUART0_RTS_USBC_DATA5_MGPIO17B_IN(GND_net_1), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_IN(GND_net_1), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_IN(GND_net_1), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_IN(GND_net_1), 
        .MMUART1_CTS_MGPIO13B_IN(GND_net_1), .MMUART1_DCD_MGPIO16B_IN(
        GND_net_1), .MMUART1_DSR_MGPIO14B_IN(GND_net_1), 
        .MMUART1_DTR_MGPIO12B_IN(GND_net_1), .MMUART1_RI_MGPIO15B_IN(
        GND_net_1), .MMUART1_RTS_MGPIO11B_IN(GND_net_1), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_IN(MMUART_1_RXD_PAD_Y), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_IN(GND_net_1), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_IN(GND_net_1), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN(GND_net_1), 
        .RGMII_MDC_RMII_MDC_IN(GND_net_1), 
        .RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN(GND_net_1), 
        .RGMII_RX_CLK_IN(GND_net_1), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN(GND_net_1), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN(GND_net_1), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN(GND_net_1), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN(GND_net_1), 
        .RGMII_RXD3_USBB_DATA4_IN(GND_net_1), .RGMII_TX_CLK_IN(
        GND_net_1), .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN(GND_net_1), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_IN(GND_net_1), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_IN(GND_net_1), 
        .RGMII_TXD2_USBB_DATA5_IN(GND_net_1), 
        .RGMII_TXD3_USBB_DATA6_IN(GND_net_1), .SPI0_SCK_USBA_XCLK_IN(
        GND_net_1), .SPI0_SDI_USBA_DIR_MGPIO5A_IN(GND_net_1), 
        .SPI0_SDO_USBA_STP_MGPIO6A_IN(GND_net_1), 
        .SPI0_SS0_USBA_NXT_MGPIO7A_IN(GND_net_1), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_IN(GND_net_1), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_IN(GND_net_1), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_IN(GND_net_1), 
        .SPI0_SS4_MGPIO19A_IN(GND_net_1), .SPI0_SS5_MGPIO20A_IN(
        GND_net_1), .SPI0_SS6_MGPIO21A_IN(GND_net_1), 
        .SPI0_SS7_MGPIO22A_IN(GND_net_1), .SPI1_SCK_IN(GND_net_1), 
        .SPI1_SDI_MGPIO11A_IN(GND_net_1), .SPI1_SDO_MGPIO12A_IN(
        GND_net_1), .SPI1_SS0_MGPIO13A_IN(GND_net_1), 
        .SPI1_SS1_MGPIO14A_IN(GND_net_1), .SPI1_SS2_MGPIO15A_IN(
        GND_net_1), .SPI1_SS3_MGPIO16A_IN(GND_net_1), 
        .SPI1_SS4_MGPIO17A_IN(GND_net_1), .SPI1_SS5_MGPIO18A_IN(
        GND_net_1), .SPI1_SS6_MGPIO23A_IN(GND_net_1), 
        .SPI1_SS7_MGPIO24A_IN(GND_net_1), .USBC_XCLK_IN(GND_net_1), 
        .USBD_DATA0_IN(GND_net_1), .USBD_DATA1_IN(GND_net_1), 
        .USBD_DATA2_IN(GND_net_1), .USBD_DATA3_IN(GND_net_1), 
        .USBD_DATA4_IN(GND_net_1), .USBD_DATA5_IN(GND_net_1), 
        .USBD_DATA6_IN(GND_net_1), .USBD_DATA7_MGPIO23B_IN(GND_net_1), 
        .USBD_DIR_IN(GND_net_1), .USBD_NXT_IN(GND_net_1), .USBD_STP_IN(
        GND_net_1), .USBD_XCLK_IN(GND_net_1), 
        .CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT(), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT(), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT(), .DRAM_ADDR({
        \DRAM_ADDR_net_0[15] , \DRAM_ADDR_net_0[14] , 
        \DRAM_ADDR_net_0[13] , \DRAM_ADDR_net_0[12] , 
        \DRAM_ADDR_net_0[11] , \DRAM_ADDR_net_0[10] , 
        \DRAM_ADDR_net_0[9] , \DRAM_ADDR_net_0[8] , 
        \DRAM_ADDR_net_0[7] , \DRAM_ADDR_net_0[6] , 
        \DRAM_ADDR_net_0[5] , \DRAM_ADDR_net_0[4] , 
        \DRAM_ADDR_net_0[3] , \DRAM_ADDR_net_0[2] , 
        \DRAM_ADDR_net_0[1] , \DRAM_ADDR_net_0[0] }), .DRAM_BA({
        \DRAM_BA_net_0[2] , \DRAM_BA_net_0[1] , \DRAM_BA_net_0[0] }), 
        .DRAM_CASN(MSS_ADLIB_INST_DRAM_CASN), .DRAM_CKE(
        MSS_ADLIB_INST_DRAM_CKE), .DRAM_CLK(MSS_ADLIB_INST_DRAM_CLK), 
        .DRAM_CSN(MSS_ADLIB_INST_DRAM_CSN), .DRAM_DM_RDQS_OUT({nc261, 
        \DRAM_DM_RDQS_OUT_net_0[1] , \DRAM_DM_RDQS_OUT_net_0[0] }), 
        .DRAM_DQ_OUT({nc262, nc263, \DRAM_DQ_OUT_net_0[15] , 
        \DRAM_DQ_OUT_net_0[14] , \DRAM_DQ_OUT_net_0[13] , 
        \DRAM_DQ_OUT_net_0[12] , \DRAM_DQ_OUT_net_0[11] , 
        \DRAM_DQ_OUT_net_0[10] , \DRAM_DQ_OUT_net_0[9] , 
        \DRAM_DQ_OUT_net_0[8] , \DRAM_DQ_OUT_net_0[7] , 
        \DRAM_DQ_OUT_net_0[6] , \DRAM_DQ_OUT_net_0[5] , 
        \DRAM_DQ_OUT_net_0[4] , \DRAM_DQ_OUT_net_0[3] , 
        \DRAM_DQ_OUT_net_0[2] , \DRAM_DQ_OUT_net_0[1] , 
        \DRAM_DQ_OUT_net_0[0] }), .DRAM_DQS_OUT({nc264, 
        \DRAM_DQS_OUT_net_0[1] , \DRAM_DQS_OUT_net_0[0] }), 
        .DRAM_FIFO_WE_OUT({nc265, \DRAM_FIFO_WE_OUT_net_0[0] }), 
        .DRAM_ODT(MSS_ADLIB_INST_DRAM_ODT), .DRAM_RASN(
        MSS_ADLIB_INST_DRAM_RASN), .DRAM_RSTN(MSS_ADLIB_INST_DRAM_RSTN)
        , .DRAM_WEN(MSS_ADLIB_INST_DRAM_WEN), 
        .I2C0_SCL_USBC_DATA1_MGPIO31B_OUT(), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_OUT(), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_OUT(), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_OUT(), .MGPIO0B_OUT(), 
        .MGPIO10B_OUT(), .MGPIO1B_OUT(), .MGPIO25A_OUT(), 
        .MGPIO26A_OUT(), .MGPIO27A_OUT(), .MGPIO28A_OUT(), 
        .MGPIO29A_OUT(), .MGPIO2B_OUT(), .MGPIO30A_OUT(), 
        .MGPIO31A_OUT(), .MGPIO3B_OUT(), .MGPIO4B_OUT(), .MGPIO5B_OUT()
        , .MGPIO6B_OUT(), .MGPIO7B_OUT(), .MGPIO8B_OUT(), .MGPIO9B_OUT(
        ), .MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT(), 
        .MMUART0_DCD_MGPIO22B_OUT(), .MMUART0_DSR_MGPIO20B_OUT(), 
        .MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT(), 
        .MMUART0_RI_MGPIO21B_OUT(), 
        .MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT(), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_OUT(), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_OUT(), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_OUT(), 
        .MMUART1_CTS_MGPIO13B_OUT(), .MMUART1_DCD_MGPIO16B_OUT(), 
        .MMUART1_DSR_MGPIO14B_OUT(), .MMUART1_DTR_MGPIO12B_OUT(), 
        .MMUART1_RI_MGPIO15B_OUT(), .MMUART1_RTS_MGPIO11B_OUT(), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT(), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT(), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT(
        MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT(), 
        .RGMII_MDC_RMII_MDC_OUT(), 
        .RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT(), .RGMII_RX_CLK_OUT(), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT(), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT(), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT(), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT(), 
        .RGMII_RXD3_USBB_DATA4_OUT(), .RGMII_TX_CLK_OUT(), 
        .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT(), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT(), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_OUT(), 
        .RGMII_TXD2_USBB_DATA5_OUT(), .RGMII_TXD3_USBB_DATA6_OUT(), 
        .SPI0_SCK_USBA_XCLK_OUT(), .SPI0_SDI_USBA_DIR_MGPIO5A_OUT(), 
        .SPI0_SDO_USBA_STP_MGPIO6A_OUT(), 
        .SPI0_SS0_USBA_NXT_MGPIO7A_OUT(), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_OUT(), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_OUT(), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_OUT(), .SPI0_SS4_MGPIO19A_OUT(), 
        .SPI0_SS5_MGPIO20A_OUT(), .SPI0_SS6_MGPIO21A_OUT(), 
        .SPI0_SS7_MGPIO22A_OUT(), .SPI1_SCK_OUT(), 
        .SPI1_SDI_MGPIO11A_OUT(), .SPI1_SDO_MGPIO12A_OUT(), 
        .SPI1_SS0_MGPIO13A_OUT(), .SPI1_SS1_MGPIO14A_OUT(), 
        .SPI1_SS2_MGPIO15A_OUT(), .SPI1_SS3_MGPIO16A_OUT(), 
        .SPI1_SS4_MGPIO17A_OUT(), .SPI1_SS5_MGPIO18A_OUT(), 
        .SPI1_SS6_MGPIO23A_OUT(), .SPI1_SS7_MGPIO24A_OUT(), 
        .USBC_XCLK_OUT(), .USBD_DATA0_OUT(), .USBD_DATA1_OUT(), 
        .USBD_DATA2_OUT(), .USBD_DATA3_OUT(), .USBD_DATA4_OUT(), 
        .USBD_DATA5_OUT(), .USBD_DATA6_OUT(), .USBD_DATA7_MGPIO23B_OUT(
        ), .USBD_DIR_OUT(), .USBD_NXT_OUT(), .USBD_STP_OUT(), 
        .USBD_XCLK_OUT(), .CAN_RXBUS_USBA_DATA1_MGPIO3A_OE(), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE(), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_OE(), .DM_OE({nc266, 
        \DM_OE_net_0[1] , \DM_OE_net_0[0] }), .DRAM_DQ_OE({nc267, 
        nc268, \DRAM_DQ_OE_net_0[15] , \DRAM_DQ_OE_net_0[14] , 
        \DRAM_DQ_OE_net_0[13] , \DRAM_DQ_OE_net_0[12] , 
        \DRAM_DQ_OE_net_0[11] , \DRAM_DQ_OE_net_0[10] , 
        \DRAM_DQ_OE_net_0[9] , \DRAM_DQ_OE_net_0[8] , 
        \DRAM_DQ_OE_net_0[7] , \DRAM_DQ_OE_net_0[6] , 
        \DRAM_DQ_OE_net_0[5] , \DRAM_DQ_OE_net_0[4] , 
        \DRAM_DQ_OE_net_0[3] , \DRAM_DQ_OE_net_0[2] , 
        \DRAM_DQ_OE_net_0[1] , \DRAM_DQ_OE_net_0[0] }), .DRAM_DQS_OE({
        nc269, \DRAM_DQS_OE_net_0[1] , \DRAM_DQS_OE_net_0[0] }), 
        .I2C0_SCL_USBC_DATA1_MGPIO31B_OE(), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_OE(), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_OE(), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_OE(), .MGPIO0B_OE(), .MGPIO10B_OE(
        ), .MGPIO1B_OE(), .MGPIO25A_OE(), .MGPIO26A_OE(), .MGPIO27A_OE(
        ), .MGPIO28A_OE(), .MGPIO29A_OE(), .MGPIO2B_OE(), .MGPIO30A_OE(
        ), .MGPIO31A_OE(), .MGPIO3B_OE(), .MGPIO4B_OE(), .MGPIO5B_OE(), 
        .MGPIO6B_OE(), .MGPIO7B_OE(), .MGPIO8B_OE(), .MGPIO9B_OE(), 
        .MMUART0_CTS_USBC_DATA7_MGPIO19B_OE(), 
        .MMUART0_DCD_MGPIO22B_OE(), .MMUART0_DSR_MGPIO20B_OE(), 
        .MMUART0_DTR_USBC_DATA6_MGPIO18B_OE(), .MMUART0_RI_MGPIO21B_OE(
        ), .MMUART0_RTS_USBC_DATA5_MGPIO17B_OE(), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_OE(), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_OE(), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_OE(), .MMUART1_CTS_MGPIO13B_OE()
        , .MMUART1_DCD_MGPIO16B_OE(), .MMUART1_DSR_MGPIO14B_OE(), 
        .MMUART1_DTR_MGPIO12B_OE(), .MMUART1_RI_MGPIO15B_OE(), 
        .MMUART1_RTS_MGPIO11B_OE(), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_OE(), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_OE(), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_OE(
        MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OE), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE(), .RGMII_MDC_RMII_MDC_OE(
        ), .RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE(), .RGMII_RX_CLK_OE(), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE(), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE(), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE(), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE(), 
        .RGMII_RXD3_USBB_DATA4_OE(), .RGMII_TX_CLK_OE(), 
        .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE(), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_OE(), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_OE(), .RGMII_TXD2_USBB_DATA5_OE(
        ), .RGMII_TXD3_USBB_DATA6_OE(), .SPI0_SCK_USBA_XCLK_OE(), 
        .SPI0_SDI_USBA_DIR_MGPIO5A_OE(), .SPI0_SDO_USBA_STP_MGPIO6A_OE(
        ), .SPI0_SS0_USBA_NXT_MGPIO7A_OE(), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_OE(), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_OE(), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_OE(), .SPI0_SS4_MGPIO19A_OE(), 
        .SPI0_SS5_MGPIO20A_OE(), .SPI0_SS6_MGPIO21A_OE(), 
        .SPI0_SS7_MGPIO22A_OE(), .SPI1_SCK_OE(), .SPI1_SDI_MGPIO11A_OE(
        ), .SPI1_SDO_MGPIO12A_OE(), .SPI1_SS0_MGPIO13A_OE(), 
        .SPI1_SS1_MGPIO14A_OE(), .SPI1_SS2_MGPIO15A_OE(), 
        .SPI1_SS3_MGPIO16A_OE(), .SPI1_SS4_MGPIO17A_OE(), 
        .SPI1_SS5_MGPIO18A_OE(), .SPI1_SS6_MGPIO23A_OE(), 
        .SPI1_SS7_MGPIO24A_OE(), .USBC_XCLK_OE(), .USBD_DATA0_OE(), 
        .USBD_DATA1_OE(), .USBD_DATA2_OE(), .USBD_DATA3_OE(), 
        .USBD_DATA4_OE(), .USBD_DATA5_OE(), .USBD_DATA6_OE(), 
        .USBD_DATA7_MGPIO23B_OE(), .USBD_DIR_OE(), .USBD_NXT_OE(), 
        .USBD_STP_OE(), .USBD_XCLK_OE());
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_RAS_N_PAD (.D(
        MSS_ADLIB_INST_DRAM_RASN), .PAD(MDDR_RAS_N));
    CLKINT MSS_ADLIB_INST_RNIJ44 (.A(CONFIG_PRESET_N), .Y(
        CORECONFIGP_0_APB_S_PRESET_N));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_4_PAD (.PAD(MDDR_DQ[4]), .D(
        \DRAM_DQ_OUT_net_0[4] ), .E(\DRAM_DQ_OE_net_0[4] ), .Y(
        MDDR_DQ_4_PAD_Y));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_10_PAD (.D(
        \DRAM_ADDR_net_0[10] ), .PAD(MDDR_ADDR[10]));
    INBUF #( .IOSTD("LPDDRI") )  MDDR_DQS_TMATCH_0_IN_PAD (.PAD(
        MDDR_DQS_TMATCH_0_IN), .Y(MDDR_DQS_TMATCH_0_IN_PAD_Y));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_CS_N_PAD (.D(
        MSS_ADLIB_INST_DRAM_CSN), .PAD(MDDR_CS_N));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_4_PAD (.D(
        \DRAM_ADDR_net_0[4] ), .PAD(MDDR_ADDR[4]));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_7_PAD (.PAD(MDDR_DQ[7]), .D(
        \DRAM_DQ_OUT_net_0[7] ), .E(\DRAM_DQ_OE_net_0[7] ), .Y(
        MDDR_DQ_7_PAD_Y));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_WE_N_PAD (.D(
        MSS_ADLIB_INST_DRAM_WEN), .PAD(MDDR_WE_N));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_8_PAD (.D(
        \DRAM_ADDR_net_0[8] ), .PAD(MDDR_ADDR[8]));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_15_PAD (.D(
        \DRAM_ADDR_net_0[15] ), .PAD(MDDR_ADDR[15]));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_0_PAD (.D(
        \DRAM_ADDR_net_0[0] ), .PAD(MDDR_ADDR[0]));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_1_PAD (.D(
        \DRAM_ADDR_net_0[1] ), .PAD(MDDR_ADDR[1]));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_13_PAD (.PAD(MDDR_DQ[13]), .D(
        \DRAM_DQ_OUT_net_0[13] ), .E(\DRAM_DQ_OE_net_0[13] ), .Y(
        MDDR_DQ_13_PAD_Y));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_ADDR_3_PAD (.D(
        \DRAM_ADDR_net_0[3] ), .PAD(MDDR_ADDR[3]));
    INBUF #( .IOSTD("") )  MMUART_1_RXD_PAD (.PAD(MMUART_1_RXD), .Y(
        MMUART_1_RXD_PAD_Y));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_BA_0_PAD (.D(\DRAM_BA_net_0[0] )
        , .PAD(MDDR_BA[0]));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_6_PAD (.PAD(MDDR_DQ[6]), .D(
        \DRAM_DQ_OUT_net_0[6] ), .E(\DRAM_DQ_OE_net_0[6] ), .Y(
        MDDR_DQ_6_PAD_Y));
    OUTBUF_DIFF #( .IOSTD("LPDDRI") )  MDDR_CLK_PAD (.D(
        MSS_ADLIB_INST_DRAM_CLK), .PADP(MDDR_CLK), .PADN(MDDR_CLK_N));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_14_PAD (.PAD(MDDR_DQ[14]), .D(
        \DRAM_DQ_OUT_net_0[14] ), .E(\DRAM_DQ_OE_net_0[14] ), .Y(
        MDDR_DQ_14_PAD_Y));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_DQS_TMATCH_0_OUT_PAD (.D(
        \DRAM_FIFO_WE_OUT_net_0[0] ), .PAD(MDDR_DQS_TMATCH_0_OUT));
    OUTBUF #( .IOSTD("LPDDRI") )  MDDR_BA_1_PAD (.D(\DRAM_BA_net_0[1] )
        , .PAD(MDDR_BA[1]));
    BIBUF #( .IOSTD("LPDDRI") )  MDDR_DQ_5_PAD (.PAD(MDDR_DQ[5]), .D(
        \DRAM_DQ_OUT_net_0[5] ), .E(\DRAM_DQ_OE_net_0[5] ), .Y(
        MDDR_DQ_5_PAD_Y));
    
endmodule


module eNVM_DataClient(
       MDDR_DQS,
       MDDR_DQ,
       MDDR_DM_RDQS,
       MDDR_BA,
       MDDR_ADDR,
       DEVRST_N,
       MMUART_1_TXD,
       MMUART_1_RXD,
       MDDR_WE_N,
       MDDR_RESET_N,
       MDDR_RAS_N,
       MDDR_ODT,
       MDDR_DQS_TMATCH_0_OUT,
       MDDR_DQS_TMATCH_0_IN,
       MDDR_CS_N,
       MDDR_CKE,
       MDDR_CAS_N,
       MDDR_CLK_N,
       MDDR_CLK
    );
inout  [1:0] MDDR_DQS;
inout  [15:0] MDDR_DQ;
inout  [1:0] MDDR_DM_RDQS;
output [2:0] MDDR_BA;
output [15:0] MDDR_ADDR;
input  DEVRST_N;
output MMUART_1_TXD;
input  MMUART_1_RXD;
output MDDR_WE_N;
output MDDR_RESET_N;
output MDDR_RAS_N;
output MDDR_ODT;
output MDDR_DQS_TMATCH_0_OUT;
input  MDDR_DQS_TMATCH_0_IN;
output MDDR_CS_N;
output MDDR_CKE;
output MDDR_CAS_N;
output MDDR_CLK_N;
output MDDR_CLK;

    wire SYSRESET_POR_net_1, GL0_INST, LOCK, 
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC, 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[2] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[3] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[4] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[5] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[6] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[7] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[8] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[9] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[10] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[12] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[13] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[15] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[2] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[3] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[4] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[5] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[6] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[7] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[8] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[9] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[10] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[0] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[1] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[2] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[3] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[4] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[5] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[6] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[7] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[8] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[9] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[10] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[11] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[12] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[13] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[14] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[15] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[0] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[1] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[2] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[3] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[4] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[5] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[6] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[7] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[8] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[9] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[10] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[11] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[12] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[13] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[14] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[15] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[16] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[3] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[4] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[5] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[6] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[7] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[8] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[9] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[10] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[11] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[12] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[13] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[14] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[15] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[16] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[18] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[0] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[1] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[2] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[0] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[1] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[2] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[3] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[4] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[5] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[6] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[7] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[8] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[9] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[10] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[11] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[12] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[13] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[14] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[15] , 
        CORECONFIGP_0_SOFT_RESET_F2M_i_0, 
        CORECONFIGP_0_SOFT_M3_RESET_i_0, CORECONFIGP_0_APB_S_PRESET_N, 
        CORECONFIGP_0_APB_S_PCLK, CORECONFIGP_0_CONFIG1_DONE, 
        CORECONFIGP_0_CONFIG2_DONE, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PREADY, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PSLVERR, 
        CORECONFIGP_0_MDDR_APBmslave_PWRITE, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE, 
        CORECONFIGP_0_APB_S_PCLK_i_0, INIT_DONE_int, 
        CORECONFIGP_0_MDDR_APBmslave_PENABLE, 
        CORECONFIGP_0_MDDR_APBmslave_PSELx, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PSELx, 
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE, 
        CORECONFIGP_0_MDDR_APBmslave_PSLVERR, 
        CORECONFIGP_0_MDDR_APBmslave_PREADY, 
        FABOSC_0_RCOSC_25_50MHZ_O2F, 
        eNVM_DataClient_MSS_TMP_0_MSS_RESET_N_M2F, GND_net_1, 
        VCC_net_1;
    
    eNVM_DataClient_FABOSC_0_OSC FABOSC_0 (
        .FABOSC_0_RCOSC_25_50MHZ_O2F(FABOSC_0_RCOSC_25_50MHZ_O2F), 
        .FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC));
    CoreResetP_Z2 CORERESETP_0 (.FABOSC_0_RCOSC_25_50MHZ_O2F(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .GL0_INST(GL0_INST), 
        .INIT_DONE_int(INIT_DONE_int), .SYSRESET_POR(
        SYSRESET_POR_net_1), 
        .eNVM_DataClient_MSS_TMP_0_MSS_RESET_N_M2F(
        eNVM_DataClient_MSS_TMP_0_MSS_RESET_N_M2F), 
        .CORECONFIGP_0_APB_S_PRESET_N(CORECONFIGP_0_APB_S_PRESET_N), 
        .CORECONFIGP_0_CONFIG1_DONE(CORECONFIGP_0_CONFIG1_DONE), 
        .CORECONFIGP_0_CONFIG2_DONE(CORECONFIGP_0_CONFIG2_DONE));
    VCC VCC (.Y(VCC_net_1));
    eNVM_DataClient_CCC_0_FCCC CCC_0 (.GL0_INST(GL0_INST), .LOCK(LOCK), 
        .FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC));
    GND GND (.Y(GND_net_1));
    CoreConfigP_Z1 CORECONFIGP_0 (.CORECONFIGP_0_MDDR_APBmslave_PADDR({
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[10] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[9] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[8] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[7] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[6] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[5] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[4] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[3] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[2] }), 
        .CORECONFIGP_0_MDDR_APBmslave_PWDATA({
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[15] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[14] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[13] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[12] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[11] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[10] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[9] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[8] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[7] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[6] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[5] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[4] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[3] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[2] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[1] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[0] }), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA({
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[16] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[15] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[14] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[13] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[12] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[11] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[10] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[9] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[8] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[7] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[6] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[5] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[4] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[3] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[2] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[1] , 
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[0] }), 
        .CORECONFIGP_0_MDDR_APBmslave_PRDATA({
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[15] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[14] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[13] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[12] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[11] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[10] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[9] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[8] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[7] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[6] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[5] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[4] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[3] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[2] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[1] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[0] }), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_10(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[12] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_11(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[13] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_13(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[15] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[2] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[3] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[4] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_3(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[5] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_4(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[6] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_5(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[7] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_6(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[8] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_7(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[9] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_8(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[10] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_3(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[3] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_4(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[4] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_5(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[5] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_6(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[6] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_7(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[7] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_8(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[8] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_9(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[9] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_10(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[10] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_11(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[11] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_12(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[12] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_13(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[13] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_14(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[14] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_15(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[15] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_16(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[16] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_18(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[18] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_0(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[0] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_1(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[1] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_2(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[2] ), 
        .CORECONFIGP_0_SOFT_RESET_F2M_i_0(
        CORECONFIGP_0_SOFT_RESET_F2M_i_0), 
        .CORECONFIGP_0_SOFT_M3_RESET_i_0(
        CORECONFIGP_0_SOFT_M3_RESET_i_0), 
        .CORECONFIGP_0_APB_S_PRESET_N(CORECONFIGP_0_APB_S_PRESET_N), 
        .CORECONFIGP_0_APB_S_PCLK(CORECONFIGP_0_APB_S_PCLK), 
        .CORECONFIGP_0_CONFIG1_DONE(CORECONFIGP_0_CONFIG1_DONE), 
        .CORECONFIGP_0_CONFIG2_DONE(CORECONFIGP_0_CONFIG2_DONE), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PREADY(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PREADY), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PSLVERR(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PSLVERR), 
        .CORECONFIGP_0_MDDR_APBmslave_PWRITE(
        CORECONFIGP_0_MDDR_APBmslave_PWRITE), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE), 
        .CORECONFIGP_0_APB_S_PCLK_i_0(CORECONFIGP_0_APB_S_PCLK_i_0), 
        .INIT_DONE_int(INIT_DONE_int), 
        .CORECONFIGP_0_MDDR_APBmslave_PENABLE(
        CORECONFIGP_0_MDDR_APBmslave_PENABLE), 
        .CORECONFIGP_0_MDDR_APBmslave_PSELx(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PSELx(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PSELx), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE), 
        .CORECONFIGP_0_MDDR_APBmslave_PSLVERR(
        CORECONFIGP_0_MDDR_APBmslave_PSLVERR), 
        .CORECONFIGP_0_MDDR_APBmslave_PREADY(
        CORECONFIGP_0_MDDR_APBmslave_PREADY));
    SYSRESET SYSRESET_POR (.POWER_ON_RESET_N(SYSRESET_POR_net_1), 
        .DEVRST_N(DEVRST_N));
    eNVM_DataClient_MSS eNVM_DataClient_MSS_0 (.MDDR_DQS({MDDR_DQS[1], 
        MDDR_DQS[0]}), .MDDR_DQ({MDDR_DQ[15], MDDR_DQ[14], MDDR_DQ[13], 
        MDDR_DQ[12], MDDR_DQ[11], MDDR_DQ[10], MDDR_DQ[9], MDDR_DQ[8], 
        MDDR_DQ[7], MDDR_DQ[6], MDDR_DQ[5], MDDR_DQ[4], MDDR_DQ[3], 
        MDDR_DQ[2], MDDR_DQ[1], MDDR_DQ[0]}), .MDDR_DM_RDQS({
        MDDR_DM_RDQS[1], MDDR_DM_RDQS[0]}), .MDDR_BA({MDDR_BA[2], 
        MDDR_BA[1], MDDR_BA[0]}), .MDDR_ADDR({MDDR_ADDR[15], 
        MDDR_ADDR[14], MDDR_ADDR[13], MDDR_ADDR[12], MDDR_ADDR[11], 
        MDDR_ADDR[10], MDDR_ADDR[9], MDDR_ADDR[8], MDDR_ADDR[7], 
        MDDR_ADDR[6], MDDR_ADDR[5], MDDR_ADDR[4], MDDR_ADDR[3], 
        MDDR_ADDR[2], MDDR_ADDR[1], MDDR_ADDR[0]}), 
        .CORECONFIGP_0_MDDR_APBmslave_PRDATA({
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[15] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[14] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[13] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[12] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[11] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[10] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[9] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[8] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[7] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[6] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[5] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[4] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[3] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[2] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[1] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[0] }), 
        .CORECONFIGP_0_MDDR_APBmslave_PADDR({
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[10] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[9] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[8] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[7] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[6] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[5] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[4] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[3] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[2] }), 
        .CORECONFIGP_0_MDDR_APBmslave_PWDATA({
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[15] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[14] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[13] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[12] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[11] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[10] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[9] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[8] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[7] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[6] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[5] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[4] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[3] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[2] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[1] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[0] }), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[2] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[3] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[4] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_3(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[5] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_4(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[6] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_5(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[7] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_6(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[8] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_7(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[9] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_8(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[10] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_10(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[12] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_11(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[13] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_13(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[15] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_0(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[0] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_1(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[1] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_2(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[2] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_3(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[3] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_4(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[4] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_5(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[5] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_6(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[6] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_7(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[7] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_8(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[8] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_9(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[9] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_10(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[10] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_11(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[11] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_12(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[12] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_13(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[13] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_14(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[14] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_15(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[15] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_16(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[16] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_0(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[0] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_1(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[1] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_2(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[2] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_3(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[3] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_4(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[4] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_5(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[5] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_6(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[6] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_7(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[7] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_8(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[8] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_9(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[9] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_10(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[10] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_11(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[11] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_12(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[12] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_13(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[13] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_14(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[14] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_15(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[15] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_16(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[16] ), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_18(
        \eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[18] ), 
        .CORECONFIGP_0_APB_S_PCLK(CORECONFIGP_0_APB_S_PCLK), 
        .CORECONFIGP_0_APB_S_PRESET_N(CORECONFIGP_0_APB_S_PRESET_N), 
        .CORECONFIGP_0_APB_S_PCLK_i_0(CORECONFIGP_0_APB_S_PCLK_i_0), 
        .MMUART_1_TXD(MMUART_1_TXD), .MMUART_1_RXD(MMUART_1_RXD), 
        .MDDR_WE_N(MDDR_WE_N), .MDDR_RESET_N(MDDR_RESET_N), 
        .MDDR_RAS_N(MDDR_RAS_N), .MDDR_ODT(MDDR_ODT), 
        .MDDR_DQS_TMATCH_0_OUT(MDDR_DQS_TMATCH_0_OUT), 
        .MDDR_DQS_TMATCH_0_IN(MDDR_DQS_TMATCH_0_IN), .MDDR_CS_N(
        MDDR_CS_N), .MDDR_CKE(MDDR_CKE), .MDDR_CAS_N(MDDR_CAS_N), 
        .eNVM_DataClient_MSS_TMP_0_MSS_RESET_N_M2F(
        eNVM_DataClient_MSS_TMP_0_MSS_RESET_N_M2F), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PSELx(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PSELx), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE), 
        .CORECONFIGP_0_MDDR_APBmslave_PREADY(
        CORECONFIGP_0_MDDR_APBmslave_PREADY), 
        .CORECONFIGP_0_MDDR_APBmslave_PSLVERR(
        CORECONFIGP_0_MDDR_APBmslave_PSLVERR), 
        .CORECONFIGP_0_SOFT_M3_RESET_i_0(
        CORECONFIGP_0_SOFT_M3_RESET_i_0), .LOCK(LOCK), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PREADY(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PREADY), 
        .eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PSLVERR(
        eNVM_DataClient_MSS_TMP_0_FIC_2_APB_MASTER_PSLVERR), 
        .CORECONFIGP_0_SOFT_RESET_F2M_i_0(
        CORECONFIGP_0_SOFT_RESET_F2M_i_0), .GL0_INST(GL0_INST), 
        .CORECONFIGP_0_MDDR_APBmslave_PENABLE(
        CORECONFIGP_0_MDDR_APBmslave_PENABLE), 
        .CORECONFIGP_0_MDDR_APBmslave_PSELx(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), 
        .CORECONFIGP_0_MDDR_APBmslave_PWRITE(
        CORECONFIGP_0_MDDR_APBmslave_PWRITE), .MDDR_CLK_N(MDDR_CLK_N), 
        .MDDR_CLK(MDDR_CLK));
    
endmodule


module eNVM_DataClient_top(
       MDDR_ADDR,
       MDDR_BA,
       MDDR_DM_RDQS,
       MDDR_DQ,
       MDDR_DQS,
       DEVRST_N,
       MDDR_DQS_TMATCH_0_IN,
       MMUART_1_RXD,
       MDDR_CAS_N,
       MDDR_CKE,
       MDDR_CLK,
       MDDR_CLK_N,
       MDDR_CS_N,
       MDDR_DQS_TMATCH_0_OUT,
       MDDR_ODT,
       MDDR_RAS_N,
       MDDR_RESET_N,
       MDDR_WE_N,
       MMUART_1_TXD
    );
output [15:0] MDDR_ADDR;
output [2:0] MDDR_BA;
inout  [1:0] MDDR_DM_RDQS;
inout  [15:0] MDDR_DQ;
inout  [1:0] MDDR_DQS;
input  DEVRST_N;
input  MDDR_DQS_TMATCH_0_IN;
input  MMUART_1_RXD;
output MDDR_CAS_N;
output MDDR_CKE;
output MDDR_CLK;
output MDDR_CLK_N;
output MDDR_CS_N;
output MDDR_DQS_TMATCH_0_OUT;
output MDDR_ODT;
output MDDR_RAS_N;
output MDDR_RESET_N;
output MDDR_WE_N;
output MMUART_1_TXD;

    wire VCC_net_1, GND_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    eNVM_DataClient eNVM_DataClient_0 (.MDDR_DQS({MDDR_DQS[1], 
        MDDR_DQS[0]}), .MDDR_DQ({MDDR_DQ[15], MDDR_DQ[14], MDDR_DQ[13], 
        MDDR_DQ[12], MDDR_DQ[11], MDDR_DQ[10], MDDR_DQ[9], MDDR_DQ[8], 
        MDDR_DQ[7], MDDR_DQ[6], MDDR_DQ[5], MDDR_DQ[4], MDDR_DQ[3], 
        MDDR_DQ[2], MDDR_DQ[1], MDDR_DQ[0]}), .MDDR_DM_RDQS({
        MDDR_DM_RDQS[1], MDDR_DM_RDQS[0]}), .MDDR_BA({MDDR_BA[2], 
        MDDR_BA[1], MDDR_BA[0]}), .MDDR_ADDR({MDDR_ADDR[15], 
        MDDR_ADDR[14], MDDR_ADDR[13], MDDR_ADDR[12], MDDR_ADDR[11], 
        MDDR_ADDR[10], MDDR_ADDR[9], MDDR_ADDR[8], MDDR_ADDR[7], 
        MDDR_ADDR[6], MDDR_ADDR[5], MDDR_ADDR[4], MDDR_ADDR[3], 
        MDDR_ADDR[2], MDDR_ADDR[1], MDDR_ADDR[0]}), .DEVRST_N(DEVRST_N)
        , .MMUART_1_TXD(MMUART_1_TXD), .MMUART_1_RXD(MMUART_1_RXD), 
        .MDDR_WE_N(MDDR_WE_N), .MDDR_RESET_N(MDDR_RESET_N), 
        .MDDR_RAS_N(MDDR_RAS_N), .MDDR_ODT(MDDR_ODT), 
        .MDDR_DQS_TMATCH_0_OUT(MDDR_DQS_TMATCH_0_OUT), 
        .MDDR_DQS_TMATCH_0_IN(MDDR_DQS_TMATCH_0_IN), .MDDR_CS_N(
        MDDR_CS_N), .MDDR_CKE(MDDR_CKE), .MDDR_CAS_N(MDDR_CAS_N), 
        .MDDR_CLK_N(MDDR_CLK_N), .MDDR_CLK(MDDR_CLK));
    
endmodule
