`

    #Build: Synplify Pro J-2015.03M-SP1-2, Build 266R, Dec 14 2015
    #install: D:\11.7 Installation\Synplify
    #OS: Windows 7 6.1
    #Hostname: W764-EDARAP1

    #Implementation: synthesis

    Synopsys HDL Compiler, version comp201503sp1p1, Build 240R, built Dec  1 2015
    @N: :  | Running in 64-bit mode
    Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

    Synopsys Verilog Compiler, version comp201503sp1p1, Build 240R, built Dec  1 2015
    @N: :  | Running in 64-bit mode
    Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

    @I::"D:\11.7 Installation\Synplify\lib\generic\smartfusion2.v"
    @I::"D:\11.7 Installation\Synplify\lib\vlog\hypermods.v"
    @I::"D:\11.7 Installation\Synplify\lib\vlog\umr_capim.v"
    @I::"D:\11.7 Installation\Synplify\lib\vlog\scemi_objects.v"
    @I::"D:\11.7 Installation\Synplify\lib\vlog\scemi_pipes.svh"
    @I::"C:\eNVM_Multiple_Images\LiberoProject\Remapping_Appnote\component\Actel\DirectCore\CoreConfigP\7.0.105\rtl\vlog\core\coreconfigp.v"
    @I::"C:\eNVM_Multiple_Images\LiberoProject\Remapping_Appnote\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp_pcie_hotreset.v"
    @I::"C:\eNVM_Multiple_Images\LiberoProject\Remapping_Appnote\component\Actel\DirectCore\CoreResetP\7.0.104\rtl\vlog\core\coreresetp.v"
    @I::"C:\eNVM_Multiple_Images\LiberoProject\Remapping_Appnote\component\work\Remapping_Appnote\CCC_0\Remapping_Appnote_CCC_0_FCCC.v"
    @I::"C:\eNVM_Multiple_Images\LiberoProject\Remapping_Appnote\component\Actel\SgCore\OSC\2.0.101\osc_comps.v"
    @I::"C:\eNVM_Multiple_Images\LiberoProject\Remapping_Appnote\component\work\Remapping_Appnote\FABOSC_0\Remapping_Appnote_FABOSC_0_OSC.v"
    @I::"C:\eNVM_Multiple_Images\LiberoProject\Remapping_Appnote\component\work\Remapping_Appnote_MSS\Remapping_Appnote_MSS_syn.v"
    @I::"C:\eNVM_Multiple_Images\LiberoProject\Remapping_Appnote\component\work\Remapping_Appnote_MSS\Remapping_Appnote_MSS.v"
    @I::"C:\eNVM_Multiple_Images\LiberoProject\Remapping_Appnote\component\work\Remapping_Appnote\Remapping_Appnote.v"
    @I::"C:\eNVM_Multiple_Images\LiberoProject\Remapping_Appnote\component\work\Remapping_Appnote_top\Remapping_Appnote_top.v"
    Verilog syntax check successful!
    Options changed - recompiling
    Selecting top level module Remapping_Appnote_top
    @N:CG364 : smartfusion2.v(376) | Synthesizing module VCC

    @N:CG364 : smartfusion2.v(372) | Synthesizing module GND

    @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT

    @N:CG364 : smartfusion2.v(727) | Synthesizing module CCC

    @N:CG364 : Remapping_Appnote_CCC_0_FCCC.v(5) | Synthesizing module Remapping_Appnote_CCC_0_FCCC

    @N:CG364 : coreconfigp.v(22) | Synthesizing module CoreConfigP

    	FAMILY=32'b00000000000000000000000000010011
    	MDDR_IN_USE=32'b00000000000000000000000000000001
    	FDDR_IN_USE=32'b00000000000000000000000000000000
    	SDIF0_IN_USE=32'b00000000000000000000000000000000
    	SDIF1_IN_USE=32'b00000000000000000000000000000000
    	SDIF2_IN_USE=32'b00000000000000000000000000000000
    	SDIF3_IN_USE=32'b00000000000000000000000000000000
    	SDIF0_PCIE=32'b00000000000000000000000000000000
    	SDIF1_PCIE=32'b00000000000000000000000000000000
    	SDIF2_PCIE=32'b00000000000000000000000000000000
    	SDIF3_PCIE=32'b00000000000000000000000000000000
    	ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001
    	DEVICE_090=32'b00000000000000000000000000000001
    	VERSION_MAJOR=32'b00000000000000000000000000000111
    	VERSION_MINOR=32'b00000000000000000000000000000000
    	VERSION_MAJOR_VECTOR=16'b0000000000000111
    	VERSION_MINOR_VECTOR=16'b0000000000000000
    	S0=2'b00
    	S1=2'b01
    	S2=2'b10
       Generated name = CoreConfigP_Z1

    @W:CL207 : coreconfigp.v(461) | All reachable assignments to SDIF1_PENABLE assign 0, register removed by optimization.
    @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP

    	FAMILY=32'b00000000000000000000000000010011
    	EXT_RESET_CFG=32'b00000000000000000000000000000000
    	DEVICE_VOLTAGE=32'b00000000000000000000000000000010
    	MDDR_IN_USE=32'b00000000000000000000000000000001
    	FDDR_IN_USE=32'b00000000000000000000000000000000
    	SDIF0_IN_USE=32'b00000000000000000000000000000000
    	SDIF1_IN_USE=32'b00000000000000000000000000000000
    	SDIF2_IN_USE=32'b00000000000000000000000000000000
    	SDIF3_IN_USE=32'b00000000000000000000000000000000
    	SDIF0_PCIE=32'b00000000000000000000000000000000
    	SDIF1_PCIE=32'b00000000000000000000000000000000
    	SDIF2_PCIE=32'b00000000000000000000000000000000
    	SDIF3_PCIE=32'b00000000000000000000000000000000
    	SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001
    	SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001
    	SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001
    	SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001
    	SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001
    	SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001
    	SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001
    	SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001
    	ENABLE_SOFT_RESETS=32'b00000000000000000000000000000001
    	DEVICE_090=32'b00000000000000000000000000000001
    	DDR_WAIT=32'b00000000000000000000000011001000
    	RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010
    	SDIF_INTERVAL=32'b00000000000000000001100101100100
    	DDR_INTERVAL=32'b00000000000000000010011100010000
    	COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101
    	COUNT_WIDTH_DDR=32'b00000000000000000000000000001110
    	S0=32'b00000000000000000000000000000000
    	S1=32'b00000000000000000000000000000001
    	S2=32'b00000000000000000000000000000010
    	S3=32'b00000000000000000000000000000011
    	S4=32'b00000000000000000000000000000100
    	S5=32'b00000000000000000000000000000101
    	S6=32'b00000000000000000000000000000110
       Generated name = CoreResetP_Z2

    @W:CL169 : coreresetp.v(1581) | Pruning register count_sdif3[12:0]

    @W:CL169 : coreresetp.v(1549) | Pruning register count_sdif2[12:0]

    @W:CL169 : coreresetp.v(1517) | Pruning register count_sdif1[12:0]

    @W:CL169 : coreresetp.v(1485) | Pruning register count_sdif0[12:0]

    @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif0_enable_q1

    @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_q1

    @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_q1

    @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_q1

    @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif0_enable_rcosc

    @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif1_enable_rcosc

    @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif2_enable_rcosc

    @W:CL169 : coreresetp.v(1455) | Pruning register count_sdif3_enable_rcosc

    @W:CL169 : coreresetp.v(1365) | Pruning register count_sdif3_enable

    @W:CL169 : coreresetp.v(1300) | Pruning register count_sdif2_enable

    @W:CL169 : coreresetp.v(1235) | Pruning register count_sdif1_enable

    @W:CL169 : coreresetp.v(1170) | Pruning register count_sdif0_enable

    @N:CL177 : coreresetp.v(1388) | Sharing sequential element M3_RESET_N_int.
    @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q1.
    @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q1.
    @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q1.
    @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q1.
    @W:CL190 : coreresetp.v(1433) | Optimizing register bit EXT_RESET_OUT_int to a constant 0
    @W:CL169 : coreresetp.v(1089) | Pruning register release_ext_reset

    @W:CL169 : coreresetp.v(1433) | Pruning register EXT_RESET_OUT_int

    @W:CL169 : coreresetp.v(1433) | Pruning register sm2_state[2:0]

    @W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_q1

    @W:CL169 : coreresetp.v(783) | Pruning register sm2_areset_n_clk_base

    @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB

    @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ

    @N:CG364 : Remapping_Appnote_FABOSC_0_OSC.v(5) | Synthesizing module Remapping_Appnote_FABOSC_0_OSC

    @N:CG364 : smartfusion2.v(274) | Synthesizing module OUTBUF

    @N:CG364 : smartfusion2.v(326) | Synthesizing module OUTBUF_DIFF

    @N:CG364 : smartfusion2.v(286) | Synthesizing module BIBUF

    @N:CG364 : smartfusion2.v(338) | Synthesizing module BIBUF_DIFF

    @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF

    @N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF

    @N:CG364 : Remapping_Appnote_MSS_syn.v(5) | Synthesizing module MSS_075

    @N:CG364 : Remapping_Appnote_MSS.v(9) | Synthesizing module Remapping_Appnote_MSS

    @N:CG364 : smartfusion2.v(718) | Synthesizing module SYSRESET

    @N:CG364 : Remapping_Appnote.v(9) | Synthesizing module Remapping_Appnote

    @N:CG364 : Remapping_Appnote_top.v(9) | Synthesizing module Remapping_Appnote_top

    @W:CL157 : Remapping_Appnote_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits -- simulation mismatch possible.
    @W:CL157 : Remapping_Appnote_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits -- simulation mismatch possible.
    @W:CL157 : Remapping_Appnote_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits -- simulation mismatch possible.
    @W:CL157 : Remapping_Appnote_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits -- simulation mismatch possible.
    @W:CL159 : Remapping_Appnote_FABOSC_0_OSC.v(14) | Input XTL is unused
    @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif0_spll_lock_q2.
    @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif1_spll_lock_q2.
    @N:CL177 : coreresetp.v(963) | Sharing sequential element sdif2_spll_lock_q2.
    @N:CL177 : coreresetp.v(963) | Sharing sequential element fpll_lock_q2.
    @N:CL201 : coreresetp.v(1365) | Trying to extract state machine for register sdif3_state
    Extracted state machine for register sdif3_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.v(1300) | Trying to extract state machine for register sdif2_state
    Extracted state machine for register sdif2_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.v(1235) | Trying to extract state machine for register sdif1_state
    Extracted state machine for register sdif1_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.v(1170) | Trying to extract state machine for register sdif0_state
    Extracted state machine for register sdif0_state
    State machine has 4 reachable states with original encodings of:
       000
       001
       010
       011
    @N:CL201 : coreresetp.v(1089) | Trying to extract state machine for register sm0_state
    Extracted state machine for register sm0_state
    State machine has 7 reachable states with original encodings of:
       000
       001
       010
       011
       100
       101
       110
    @W:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused
    @W:CL159 : coreresetp.v(56) | Input FPLL_LOCK is unused
    @W:CL159 : coreresetp.v(59) | Input SDIF0_SPLL_LOCK is unused
    @W:CL159 : coreresetp.v(68) | Input SDIF1_SPLL_LOCK is unused
    @W:CL159 : coreresetp.v(72) | Input SDIF2_SPLL_LOCK is unused
    @W:CL159 : coreresetp.v(76) | Input SDIF3_SPLL_LOCK is unused
    @W:CL159 : coreresetp.v(90) | Input SDIF0_PSEL is unused
    @W:CL159 : coreresetp.v(91) | Input SDIF0_PWRITE is unused
    @W:CL159 : coreresetp.v(92) | Input SDIF0_PRDATA is unused
    @W:CL159 : coreresetp.v(93) | Input SDIF1_PSEL is unused
    @W:CL159 : coreresetp.v(94) | Input SDIF1_PWRITE is unused
    @W:CL159 : coreresetp.v(95) | Input SDIF1_PRDATA is unused
    @W:CL159 : coreresetp.v(96) | Input SDIF2_PSEL is unused
    @W:CL159 : coreresetp.v(97) | Input SDIF2_PWRITE is unused
    @W:CL159 : coreresetp.v(98) | Input SDIF2_PRDATA is unused
    @W:CL159 : coreresetp.v(99) | Input SDIF3_PSEL is unused
    @W:CL159 : coreresetp.v(100) | Input SDIF3_PWRITE is unused
    @W:CL159 : coreresetp.v(101) | Input SDIF3_PRDATA is unused
    @N:CL201 : coreconfigp.v(447) | Trying to extract state machine for register state
    Extracted state machine for register state
    State machine has 3 reachable states with original encodings of:
       00
       01
       10
    @W:CL159 : coreconfigp.v(71) | Input SDIF1_PREADY is unused
    @W:CL159 : coreconfigp.v(72) | Input SDIF1_PSLVERR is unused

    At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 85MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Mon Mar 14 11:21:11 2016

    ###########################################################]
    Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec  1 2015
    @N: :  | Running in 64-bit mode

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Mon Mar 14 11:21:11 2016

    ###########################################################]
    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Mon Mar 14 11:21:11 2016

    ###########################################################]
    Synopsys Netlist Linker, version comp201503sp1p1, Build 240R, built Dec  1 2015
    @N: :  | Running in 64-bit mode
    File C:\Microsemi\Libero_v11.6\Synopsys\fpga_J-2015.03M-3\bin64\syn_nfilter.exe changed - recompiling
    File C:\eNVM_Multiple_Images\LiberoProject\Remapping_Appnote\synthesis\synwork\Remapping_Appnote_top_comp.srs changed - recompiling

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Mon Mar 14 11:21:12 2016

    ###########################################################]
    Pre-mapping Report

    Synopsys Generic Technology Pre-mapping, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42
    Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
    Product Version J-2015.03M-SP1-2

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    Linked File: Remapping_Appnote_top_scck.rpt
    Printing clock  summary report in "C:\eNVM_Multiple_Images\LiberoProject\Remapping_Appnote\synthesis\Remapping_Appnote_top_scck.rpt" file
    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 108MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 106MB peak: 108MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 108MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 109MB)

    @W:BN132 : coreresetp.v(1089) | Removing sequential instance Remapping_Appnote_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int,  because it is equivalent to instance Remapping_Appnote_0.CORERESETP_0.FDDR_CORE_RESET_N_int
    @N:BN362 : coreconfigp.v(461) | Removing sequential instance FDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z1(verilog) because there are no references to its outputs
    @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF0_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z1(verilog) because there are no references to its outputs
    @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF2_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z1(verilog) because there are no references to its outputs
    @N:BN362 : coreconfigp.v(461) | Removing sequential instance SDIF3_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z1(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance SDIF_RELEASED_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance FDDR_CORE_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1170) | Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1235) | Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1300) | Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1365) | Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1170) | Removing sequential instance sdif0_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1235) | Removing sequential instance sdif1_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1300) | Removing sequential instance sdif2_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(1365) | Removing sequential instance sdif3_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(797) | Removing sequential instance sdif0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(811) | Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(825) | Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs
    @N:BN362 : coreresetp.v(839) | Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z2(verilog) because there are no references to its outputs
    syn_allowed_resources : blockrams=109  set on top level netlist Remapping_Appnote_top

    Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 137MB)

    @S |Clock Summary
    *****************

    Start                                                                Requested     Requested     Clock        Clock
    Clock                                                                Frequency     Period        Type         Group
    ---------------------------------------------------------------------------------------------------------------------------------
    Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock                  100.0 MHz     10.000        inferred     Inferred_clkgroup_1
    Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     100.0 MHz     10.000        inferred     Inferred_clkgroup_2
    Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock                100.0 MHz     10.000        inferred     Inferred_clkgroup_0
    =================================================================================================================================

    @W:MT530 : coreconfigp.v(546) | Found inferred clock Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock which controls 110 sequential elements including Remapping_Appnote_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[31:0]. This clock has no specified timing constraint which may adversely impact design performance.
    @W:MT530 : coreresetp.v(1089) | Found inferred clock Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock which controls 56 sequential elements including Remapping_Appnote_0.CORERESETP_0.count_ddr_enable. This clock has no specified timing constraint which may adversely impact design performance.
    @W:MT530 : coreresetp.v(1613) | Found inferred clock Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 31 sequential elements including Remapping_Appnote_0.CORERESETP_0.count_ddr[13:0]. This clock has no specified timing constraint which may adversely impact design performance.

    Finished Pre Mapping Phase.
    @N:BN225 :  | Writing default property annotation file C:\eNVM_Multiple_Images\LiberoProject\Remapping_Appnote\synthesis\Remapping_Appnote_top.sap.
    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 137MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Mon Mar 14 11:21:13 2016

    ###########################################################]
    Map & Optimize Report

    Synopsys Generic Technology Mapper, Version mapact, Build 1659R, Built Dec 10 2015 09:44:42
    Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
    Product Version J-2015.03M-SP1-2

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

    @N:MF248 :  | Running in 64-bit mode.
    @N:MF667 :  | Clock conversion disabled

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

    @W:MO111 : remapping_appnote_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F on net XTLOSC_O2F has its enable tied to GND (module Remapping_Appnote_FABOSC_0_OSC)
    @W:MO111 : remapping_appnote_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC on net XTLOSC_CCC has its enable tied to GND (module Remapping_Appnote_FABOSC_0_OSC)
    @W:MO111 : remapping_appnote_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F on net RCOSC_1MHZ_O2F has its enable tied to GND (module Remapping_Appnote_FABOSC_0_OSC)
    @W:MO111 : remapping_appnote_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC on net RCOSC_1MHZ_CCC has its enable tied to GND (module Remapping_Appnote_FABOSC_0_OSC)
    @W:MO171 : coreresetp.v(676) | Sequential instance Remapping_Appnote_0.CORERESETP_0.SDIF0_PERST_N_q1 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(695) | Sequential instance Remapping_Appnote_0.CORERESETP_0.SDIF1_PERST_N_q1 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(714) | Sequential instance Remapping_Appnote_0.CORERESETP_0.SDIF2_PERST_N_q1 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(733) | Sequential instance Remapping_Appnote_0.CORERESETP_0.SDIF3_PERST_N_q1 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(676) | Sequential instance Remapping_Appnote_0.CORERESETP_0.SDIF0_PERST_N_q2 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(695) | Sequential instance Remapping_Appnote_0.CORERESETP_0.SDIF1_PERST_N_q2 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(714) | Sequential instance Remapping_Appnote_0.CORERESETP_0.SDIF2_PERST_N_q2 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(733) | Sequential instance Remapping_Appnote_0.CORERESETP_0.SDIF3_PERST_N_q2 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(676) | Sequential instance Remapping_Appnote_0.CORERESETP_0.SDIF0_PERST_N_q3 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(695) | Sequential instance Remapping_Appnote_0.CORERESETP_0.SDIF1_PERST_N_q3 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(714) | Sequential instance Remapping_Appnote_0.CORERESETP_0.SDIF2_PERST_N_q3 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(733) | Sequential instance Remapping_Appnote_0.CORERESETP_0.SDIF3_PERST_N_q3 reduced to a combinational gate by constant propagation
    @W:MO171 : coreconfigp.v(583) | Sequential instance Remapping_Appnote_0.CORECONFIGP_0.SDIF_RELEASED_q1 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(769) | Sequential instance Remapping_Appnote_0.CORERESETP_0.sm1_areset_n_q1 reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(769) | Sequential instance Remapping_Appnote_0.CORERESETP_0.sm1_areset_n_clk_base reduced to a combinational gate by constant propagation
    @W:MO171 : coreresetp.v(1388) | Sequential instance Remapping_Appnote_0.CORERESETP_0.RESET_N_F2M_int reduced to a combinational gate by constant propagation
    @W:BN132 : coreresetp.v(898) | Removing sequential instance Remapping_Appnote_0.CORERESETP_0.sdif2_areset_n_rcosc_q1,  because it is equivalent to instance Remapping_Appnote_0.CORERESETP_0.sm0_areset_n_rcosc_q1
    @W:BN132 : coreresetp.v(912) | Removing sequential instance Remapping_Appnote_0.CORERESETP_0.sdif3_areset_n_rcosc_q1,  because it is equivalent to instance Remapping_Appnote_0.CORERESETP_0.sm0_areset_n_rcosc_q1
    @W:BN132 : coreresetp.v(884) | Removing sequential instance Remapping_Appnote_0.CORERESETP_0.sdif1_areset_n_rcosc_q1,  because it is equivalent to instance Remapping_Appnote_0.CORERESETP_0.sm0_areset_n_rcosc_q1
    @W:BN132 : coreresetp.v(870) | Removing sequential instance Remapping_Appnote_0.CORERESETP_0.sdif0_areset_n_rcosc_q1,  because it is equivalent to instance Remapping_Appnote_0.CORERESETP_0.sm0_areset_n_rcosc_q1
    @W:BN132 : coreresetp.v(884) | Removing sequential instance Remapping_Appnote_0.CORERESETP_0.sdif1_areset_n_rcosc,  because it is equivalent to instance Remapping_Appnote_0.CORERESETP_0.sdif0_areset_n_rcosc
    @W:BN132 : coreresetp.v(912) | Removing sequential instance Remapping_Appnote_0.CORERESETP_0.sdif3_areset_n_rcosc,  because it is equivalent to instance Remapping_Appnote_0.CORERESETP_0.sdif0_areset_n_rcosc
    @W:BN132 : coreresetp.v(898) | Removing sequential instance Remapping_Appnote_0.CORERESETP_0.sdif2_areset_n_rcosc,  because it is equivalent to instance Remapping_Appnote_0.CORERESETP_0.sdif0_areset_n_rcosc
    @W:BN132 : coreresetp.v(856) | Removing sequential instance Remapping_Appnote_0.CORERESETP_0.sm0_areset_n_rcosc,  because it is equivalent to instance Remapping_Appnote_0.CORERESETP_0.sdif0_areset_n_rcosc
    @W:BN132 : coreresetp.v(1581) | Removing sequential instance Remapping_Appnote_0.CORERESETP_0.release_sdif3_core,  because it is equivalent to instance Remapping_Appnote_0.CORERESETP_0.release_sdif1_core
    @W:BN132 : coreresetp.v(1549) | Removing sequential instance Remapping_Appnote_0.CORERESETP_0.release_sdif2_core,  because it is equivalent to instance Remapping_Appnote_0.CORERESETP_0.release_sdif1_core

    Available hyper_sources - for debug and ip models
    	None Found

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)

    Encoding state machine state[2:0] (view:work.CoreConfigP_Z1(verilog))
    original code -> new code
       00 -> 00
       01 -> 01
       10 -> 10
    @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[16] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z1(verilog) because there are no references to its outputs
    @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[17] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z1(verilog) because there are no references to its outputs
    @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[18] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z1(verilog) because there are no references to its outputs
    @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[19] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z1(verilog) because there are no references to its outputs
    @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[20] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z1(verilog) because there are no references to its outputs
    @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[21] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z1(verilog) because there are no references to its outputs
    @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[22] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z1(verilog) because there are no references to its outputs
    @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[23] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z1(verilog) because there are no references to its outputs
    @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[24] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z1(verilog) because there are no references to its outputs
    @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[25] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z1(verilog) because there are no references to its outputs
    @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[26] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z1(verilog) because there are no references to its outputs
    @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[27] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z1(verilog) because there are no references to its outputs
    @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[28] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z1(verilog) because there are no references to its outputs
    @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[29] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z1(verilog) because there are no references to its outputs
    @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[30] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z1(verilog) because there are no references to its outputs
    @N:BN362 : coreconfigp.v(255) | Removing sequential instance pwdata[31] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z1(verilog) because there are no references to its outputs
    @N:BN362 : coreconfigp.v(255) | Removing sequential instance paddr[11] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z1(verilog) because there are no references to its outputs
    @W:MO160 : coreconfigp.v(255) | Register bit paddr[16] is always 0, optimizing ...
    @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[31] is always 0, optimizing ...
    @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[30] is always 0, optimizing ...
    @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[29] is always 0, optimizing ...
    @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[28] is always 0, optimizing ...
    @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[27] is always 0, optimizing ...
    @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[26] is always 0, optimizing ...
    @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[25] is always 0, optimizing ...
    @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[24] is always 0, optimizing ...
    @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[23] is always 0, optimizing ...
    @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[22] is always 0, optimizing ...
    @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[21] is always 0, optimizing ...
    @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[20] is always 0, optimizing ...
    @W:MO160 : coreconfigp.v(546) | Register bit FIC_2_APB_M_PRDATA[19] is always 0, optimizing ...
    @N:BN362 : coreconfigp.v(255) | Removing sequential instance paddr[14] of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z1(verilog) because there are no references to its outputs
    Encoding state machine sm0_state[6:0] (view:work.CoreResetP_Z2(verilog))
    original code -> new code
       000 -> 0000001
       001 -> 0000010
       010 -> 0000100
       011 -> 0001000
       100 -> 0010000
       101 -> 0100000
       110 -> 1000000
    @N: : coreresetp.v(1613) | Found counter in view:work.CoreResetP_Z2(verilog) inst count_ddr[13:0]
    @N:BN362 : coreresetp.v(1089) | Removing sequential instance Remapping_Appnote_0.CORERESETP_0.DDR_READY_int in hierarchy view:work.Remapping_Appnote_top(verilog) because there are no references to its outputs

    Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)

    Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)

    Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)

    Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:00s		     0.72ns		  99 /       124
       2		0h:00m:00s		     0.72ns		  99 /       124
    @N:FP130 :  | Promoting Net Remapping_Appnote_0.CORECONFIGP_0_APB_S_PRESET_N on CLKINT  I_28
    @N:FP130 :  | Promoting Net Remapping_Appnote_0.CORECONFIGP_0_APB_S_PCLK on CLKINT  I_29
    @N:FP130 :  | Promoting Net Remapping_Appnote_0.CORERESETP_0.sm0_areset_n_clk_base on CLKINT  I_30
    @N:FP130 :  | Promoting Net Remapping_Appnote_0.CORERESETP_0.sm0_areset_n_rcosc on CLKINT  I_31

    Added 0 Buffers
    Added 0 Cells via replication
    	Added 0 Sequential Cells via replication
    	Added 0 Combinational Cells via replication

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)

    Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)

    #### START OF CLOCK OPTIMIZATION REPORT #####[

    Clock optimization not enabled
    2 non-gated/non-generated clock tree(s) driving 51 clock pin(s) of sequential element(s)
    1 gated/generated clock tree(s) driving 75 clock pin(s) of sequential element(s)
    0 instances converted, 75 sequential instances remain driven by gated/generated clocks

    ===================================================================== Non-Gated/Non-Generated Clocks ======================================================================
    Clock Tree ID     Driving Element                                              Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    ClockId0002        Remapping_Appnote_0.CCC_0.GL0_INST                           CLKINT                 31         Remapping_Appnote_0.Remapping_Appnote_MSS_0.MSS_ADLIB_INST
    ClockId0003        Remapping_Appnote_0.FABOSC_0.I_RCOSC_25_50MHZ_FAB_CLKINT     CLKINT                 20         Remapping_Appnote_0.CORERESETP_0.count_ddr[13]
    ===========================================================================================================================================================================
    ========================================================================================================== Gated/Generated Clocks ===========================================================================================================
    Clock Tree ID     Driving Element                                                Drive Element Type     Fanout     Sample Instance                                                Explanation
    ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    ClockId0001        Remapping_Appnote_0.Remapping_Appnote_MSS_0.MSS_ADLIB_INST     MSS_075                75         Remapping_Appnote_0.Remapping_Appnote_MSS_0.MSS_ADLIB_INST     No gated clock conversion method for cell cell:work.MSS_075
    =============================================================================================================================================================================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######]

    Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 136MB)

    Writing Analyst data base C:\eNVM_Multiple_Images\LiberoProject\Remapping_Appnote\synthesis\synwork\Remapping_Appnote_top_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)

    Writing EDIF Netlist and constraint files
    @N:BW103 :  | Synopsys Constraint File time units using default value of 1ns
    @N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF
    J-2015.03M-SP1-2

    Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 135MB peak: 137MB)

    Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 135MB peak: 137MB)

    @W:MT246 : remapping_appnote_ccc_0_fccc.v(20) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @W:MT420 :  | Found inferred clock Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:Remapping_Appnote_0.Remapping_Appnote_MSS_0.FIC_2_APB_M_PCLK"

    @W:MT420 :  | Found inferred clock Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:Remapping_Appnote_0.FABOSC_0.RCOSC_25_50MHZ_CCC"

    @W:MT420 :  | Found inferred clock Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:Remapping_Appnote_0.CCC_0.GL0_net"

    @S |##### START OF TIMING REPORT #####[
    # Timing Report written on Mon Mar 14 11:21:14 2016
    #

    Top view:               Remapping_Appnote_top
    Requested Frequency:    100.0 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):
    @N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing.

    @N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock.

    Performance Summary
    *******************

    Worst slack in design: 1.835

                                                                         Requested     Estimated     Requested     Estimated               Clock        Clock
    Starting Clock                                                       Frequency     Frequency     Period        Period        Slack     Type         Group
    -----------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock                  100.0 MHz     499.9 MHz     10.000        2.000         8.000     inferred     Inferred_clkgroup_1
    Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     100.0 MHz     428.6 MHz     10.000        2.333         7.667     inferred     Inferred_clkgroup_2
    Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock                100.0 MHz     146.7 MHz     10.000        6.816         1.835     inferred     Inferred_clkgroup_0
    =======================================================================================================================================================================

    Clock Relationships
    *******************

    Clocks                                                                                                                              |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Starting                                                          Ending                                                            |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock             Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock             |  10.000      3.184  |  No paths    -      |  5.000       2.990  |  5.000       1.835
    Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock             Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock               |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -
    Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock               Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock             |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -
    Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock               Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock               |  10.000      8.000  |  No paths    -      |  No paths    -      |  No paths    -
    Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock               Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock  |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -
    Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock  Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock               |  Diff grp    -      |  No paths    -      |  No paths    -      |  No paths    -
    Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock  Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock  |  10.000      7.667  |  No paths    -      |  No paths    -      |  No paths    -
    ==========================================================================================================================================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                                       Starting                                                                                                   Arrival
    Instance                                                           Reference                                               Type     Pin     Net                               Time        Slack
                                                                       Clock
    -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Remapping_Appnote_0.CORERESETP_0.sm0_state[3]                      Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       sm0_state[3]                      0.076       8.000
    Remapping_Appnote_0.CORERESETP_0.sdif3_spll_lock_q2                Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       sdif3_spll_lock_q2                0.076       8.075
    Remapping_Appnote_0.CORERESETP_0.release_sdif0_core_clk_base       Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       release_sdif3_core_clk_base       0.076       8.208
    Remapping_Appnote_0.CORERESETP_0.ddr_settled_clk_base              Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       ddr_settled_clk_base              0.076       8.233
    Remapping_Appnote_0.CORERESETP_0.sm0_state[4]                      Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       sm0_state[4]                      0.094       8.587
    Remapping_Appnote_0.CORERESETP_0.CONFIG2_DONE_clk_base             Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       CONFIG2_DONE_clk_base             0.094       8.684
    Remapping_Appnote_0.CORERESETP_0.sm0_state[5]                      Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       sm0_state[5]                      0.094       8.745
    Remapping_Appnote_0.CORERESETP_0.FIC_2_APB_M_PRESET_N_clk_base     Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       FIC_2_APB_M_PRESET_N_clk_base     0.076       8.801
    Remapping_Appnote_0.CORERESETP_0.RESET_N_M2F_clk_base              Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       RESET_N_M2F_clk_base              0.076       8.811
    Remapping_Appnote_0.CORERESETP_0.mss_ready_state                   Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock     SLE      Q       mss_ready_state                   0.094       8.823
    ===============================================================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                            Starting                                                                                                    Required
    Instance                                                Reference                                               Type     Pin     Net                                Time         Slack
                                                            Clock
    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Remapping_Appnote_0.CORERESETP_0.sm0_state[4]           Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       sm0_state_ns[4]                    9.778        8.000
    Remapping_Appnote_0.CORERESETP_0.sm0_state[5]           Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       sm0_state_ns[5]                    9.778        8.208
    Remapping_Appnote_0.CORERESETP_0.count_ddr_enable       Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       next_count_ddr_enable_0_sqmuxa     9.778        8.373
    Remapping_Appnote_0.CORERESETP_0.count_ddr_enable       Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock     SLE      EN      un1_next_ddr_ready_0_sqmuxa        9.707        8.587
    Remapping_Appnote_0.CORERESETP_0.sm0_state[3]           Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       sm0_state_ns[3]                    9.778        8.633
    Remapping_Appnote_0.CORERESETP_0.sm0_state[6]           Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock     SLE      EN      sm0_state_ns_a3[6]                 9.707        8.745
    Remapping_Appnote_0.CORERESETP_0.MSS_HPMS_READY_int     Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       MSS_HPMS_READY_int_4               9.778        8.801
    Remapping_Appnote_0.CORERESETP_0.mss_ready_select       Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock     SLE      EN      mss_ready_select4                  9.707        8.812
    Remapping_Appnote_0.CORERESETP_0.sm0_state[2]           Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock     SLE      D       sm0_state_ns[2]                    9.778        8.830
    Remapping_Appnote_0.CORERESETP_0.mss_ready_state        Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock     SLE      EN      RESET_N_M2F_clk_base               9.707        8.926
    ======================================================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.778

        - Propagation time:                      1.778
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 8.000

        Number of logic level(s):                2
        Starting point:                          Remapping_Appnote_0.CORERESETP_0.sm0_state[3] / Q
        Ending point:                            Remapping_Appnote_0.CORERESETP_0.sm0_state[4] / D
        The start point is clocked by            Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK
        The end   point is clocked by            Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK

    Instance / Net                                                                    Pin      Pin               Arrival     No. of
    Name                                                                     Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------------------------
    Remapping_Appnote_0.CORERESETP_0.sm0_state[3]                            SLE      Q        Out     0.076     0.076       -
    sm0_state[3]                                                             Net      -        -       0.637     -           3
    Remapping_Appnote_0.CORERESETP_0.next_count_ddr_enable_0_sqmuxa_0_a3     CFG2     B        In      -         0.714       -
    Remapping_Appnote_0.CORERESETP_0.next_count_ddr_enable_0_sqmuxa_0_a3     CFG2     Y        Out     0.143     0.857       -
    next_count_ddr_enable_0_sqmuxa                                           Net      -        -       0.548     -           2
    Remapping_Appnote_0.CORERESETP_0.sm0_state_ns[4]                         CFG4     D        In      -         1.405       -
    Remapping_Appnote_0.CORERESETP_0.sm0_state_ns[4]                         CFG4     Y        Out     0.236     1.641       -
    sm0_state_ns[4]                                                          Net      -        -       0.138     -           1
    Remapping_Appnote_0.CORERESETP_0.sm0_state[4]                            SLE      D        In      -         1.778       -
    ===================================================================================================================================
    Total path delay (propagation time + setup) of 2.000 is 0.677(33.9%) logic and 1.323(66.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                      Starting                                                                                               Arrival
    Instance                                          Reference                                                            Type     Pin     Net              Time        Slack
                                                      Clock
    --------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Remapping_Appnote_0.CORERESETP_0.count_ddr[0]     Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[0]     0.094       7.667
    Remapping_Appnote_0.CORERESETP_0.count_ddr[1]     Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[1]     0.094       7.732
    Remapping_Appnote_0.CORERESETP_0.count_ddr[2]     Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[2]     0.094       7.746
    Remapping_Appnote_0.CORERESETP_0.count_ddr[3]     Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[3]     0.094       7.760
    Remapping_Appnote_0.CORERESETP_0.count_ddr[4]     Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[4]     0.094       7.774
    Remapping_Appnote_0.CORERESETP_0.count_ddr[5]     Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[5]     0.094       7.789
    Remapping_Appnote_0.CORERESETP_0.count_ddr[6]     Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[6]     0.094       7.803
    Remapping_Appnote_0.CORERESETP_0.count_ddr[7]     Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[7]     0.094       7.817
    Remapping_Appnote_0.CORERESETP_0.count_ddr[8]     Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[8]     0.094       7.831
    Remapping_Appnote_0.CORERESETP_0.count_ddr[9]     Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      Q       count_ddr[9]     0.094       7.845
    ==========================================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                       Starting                                                                                                  Required
    Instance                                           Reference                                                            Type     Pin     Net                 Time         Slack
                                                       Clock
    -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Remapping_Appnote_0.CORERESETP_0.count_ddr[13]     Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      D       count_ddr_s[13]     9.778        7.667
    Remapping_Appnote_0.CORERESETP_0.count_ddr[12]     Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      D       count_ddr_s[12]     9.778        7.681
    Remapping_Appnote_0.CORERESETP_0.count_ddr[11]     Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      D       count_ddr_s[11]     9.778        7.695
    Remapping_Appnote_0.CORERESETP_0.count_ddr[10]     Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      D       count_ddr_s[10]     9.778        7.709
    Remapping_Appnote_0.CORERESETP_0.count_ddr[9]      Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      D       count_ddr_s[9]      9.778        7.723
    Remapping_Appnote_0.CORERESETP_0.count_ddr[8]      Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      D       count_ddr_s[8]      9.778        7.738
    Remapping_Appnote_0.CORERESETP_0.count_ddr[7]      Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      D       count_ddr_s[7]      9.778        7.752
    Remapping_Appnote_0.CORERESETP_0.count_ddr[6]      Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      D       count_ddr_s[6]      9.778        7.766
    Remapping_Appnote_0.CORERESETP_0.count_ddr[5]      Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      D       count_ddr_s[5]      9.778        7.780
    Remapping_Appnote_0.CORERESETP_0.count_ddr[4]      Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock     SLE      D       count_ddr_s[4]      9.778        7.795
    ===============================================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      10.000
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         9.778

        - Propagation time:                      2.111
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (non-critical) :                 7.667

        Number of logic level(s):                14
        Starting point:                          Remapping_Appnote_0.CORERESETP_0.count_ddr[0] / Q
        Ending point:                            Remapping_Appnote_0.CORERESETP_0.count_ddr[13] / D
        The start point is clocked by            Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock [rising] on pin CLK
        The end   point is clocked by            Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock [rising] on pin CLK

    Instance / Net                                                  Pin      Pin               Arrival     No. of
    Name                                                   Type     Name     Dir     Delay     Time        Fan Out(s)
    -----------------------------------------------------------------------------------------------------------------
    Remapping_Appnote_0.CORERESETP_0.count_ddr[0]          SLE      Q        Out     0.094     0.094       -
    count_ddr[0]                                           Net      -        -       0.637     -           3
    Remapping_Appnote_0.CORERESETP_0.count_ddr_s_27        ARI1     B        In      -         0.732       -
    Remapping_Appnote_0.CORERESETP_0.count_ddr_s_27        ARI1     FCO      Out     0.174     0.906       -
    count_ddr_s_27_FCO                                     Net      -        -       0.000     -           1
    Remapping_Appnote_0.CORERESETP_0.count_ddr_cry[1]      ARI1     FCI      In      -         0.906       -
    Remapping_Appnote_0.CORERESETP_0.count_ddr_cry[1]      ARI1     FCO      Out     0.014     0.920       -
    count_ddr_cry[1]                                       Net      -        -       0.000     -           1
    Remapping_Appnote_0.CORERESETP_0.count_ddr_cry[2]      ARI1     FCI      In      -         0.920       -
    Remapping_Appnote_0.CORERESETP_0.count_ddr_cry[2]      ARI1     FCO      Out     0.014     0.935       -
    count_ddr_cry[2]                                       Net      -        -       0.000     -           1
    Remapping_Appnote_0.CORERESETP_0.count_ddr_cry[3]      ARI1     FCI      In      -         0.935       -
    Remapping_Appnote_0.CORERESETP_0.count_ddr_cry[3]      ARI1     FCO      Out     0.014     0.949       -
    count_ddr_cry[3]                                       Net      -        -       0.000     -           1
    Remapping_Appnote_0.CORERESETP_0.count_ddr_cry[4]      ARI1     FCI      In      -         0.949       -
    Remapping_Appnote_0.CORERESETP_0.count_ddr_cry[4]      ARI1     FCO      Out     0.014     0.963       -
    count_ddr_cry[4]                                       Net      -        -       0.000     -           1
    Remapping_Appnote_0.CORERESETP_0.count_ddr_cry[5]      ARI1     FCI      In      -         0.963       -
    Remapping_Appnote_0.CORERESETP_0.count_ddr_cry[5]      ARI1     FCO      Out     0.014     0.977       -
    count_ddr_cry[5]                                       Net      -        -       0.000     -           1
    Remapping_Appnote_0.CORERESETP_0.count_ddr_cry[6]      ARI1     FCI      In      -         0.977       -
    Remapping_Appnote_0.CORERESETP_0.count_ddr_cry[6]      ARI1     FCO      Out     0.014     0.991       -
    count_ddr_cry[6]                                       Net      -        -       0.000     -           1
    Remapping_Appnote_0.CORERESETP_0.count_ddr_cry[7]      ARI1     FCI      In      -         0.991       -
    Remapping_Appnote_0.CORERESETP_0.count_ddr_cry[7]      ARI1     FCO      Out     0.014     1.006       -
    count_ddr_cry[7]                                       Net      -        -       0.000     -           1
    Remapping_Appnote_0.CORERESETP_0.count_ddr_cry[8]      ARI1     FCI      In      -         1.006       -
    Remapping_Appnote_0.CORERESETP_0.count_ddr_cry[8]      ARI1     FCO      Out     0.014     1.020       -
    count_ddr_cry[8]                                       Net      -        -       0.000     -           1
    Remapping_Appnote_0.CORERESETP_0.count_ddr_cry[9]      ARI1     FCI      In      -         1.020       -
    Remapping_Appnote_0.CORERESETP_0.count_ddr_cry[9]      ARI1     FCO      Out     0.014     1.034       -
    count_ddr_cry[9]                                       Net      -        -       0.000     -           1
    Remapping_Appnote_0.CORERESETP_0.count_ddr_cry[10]     ARI1     FCI      In      -         1.034       -
    Remapping_Appnote_0.CORERESETP_0.count_ddr_cry[10]     ARI1     FCO      Out     0.014     1.048       -
    count_ddr_cry[10]                                      Net      -        -       0.000     -           1
    Remapping_Appnote_0.CORERESETP_0.count_ddr_cry[11]     ARI1     FCI      In      -         1.048       -
    Remapping_Appnote_0.CORERESETP_0.count_ddr_cry[11]     ARI1     FCO      Out     0.014     1.062       -
    count_ddr_cry[11]                                      Net      -        -       0.000     -           1
    Remapping_Appnote_0.CORERESETP_0.count_ddr_cry[12]     ARI1     FCI      In      -         1.062       -
    Remapping_Appnote_0.CORERESETP_0.count_ddr_cry[12]     ARI1     FCO      Out     0.014     1.077       -
    count_ddr_cry[12]                                      Net      -        -       0.000     -           1
    Remapping_Appnote_0.CORERESETP_0.count_ddr_s[13]       ARI1     FCI      In      -         1.077       -
    Remapping_Appnote_0.CORERESETP_0.count_ddr_s[13]       ARI1     S        Out     0.063     1.140       -
    count_ddr_s[13]                                        Net      -        -       0.971     -           1
    Remapping_Appnote_0.CORERESETP_0.count_ddr[13]         SLE      D        In      -         2.111       -
    =================================================================================================================
    Total path delay (propagation time + setup) of 2.333 is 0.724(31.1%) logic and 1.609(68.9%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ====================================
    Detailed Report for Clock: Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock
    ====================================

    Starting Points with Worst Slack
    ********************************

                                                                   Starting                                                                                                                                     Arrival
    Instance                                                       Reference                                                 Type        Pin                        Net                                         Time        Slack
                                                                   Clock
    -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Remapping_Appnote_0.CORECONFIGP_0.psel                         Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock     SLE         Q                          psel                                        0.076       1.835
    Remapping_Appnote_0.CORECONFIGP_0.state[1]                     Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock     SLE         Q                          state[1]                                    0.076       2.990
    Remapping_Appnote_0.Remapping_Appnote_MSS_0.MSS_ADLIB_INST     Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock     MSS_075     MDDR_FABRIC_PRDATA[5]      CORECONFIGP_0_MDDR_APBmslave_PRDATA[5]      4.785       3.184
    Remapping_Appnote_0.Remapping_Appnote_MSS_0.MSS_ADLIB_INST     Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock     MSS_075     MDDR_FABRIC_PRDATA[1]      CORECONFIGP_0_MDDR_APBmslave_PRDATA[1]      4.666       3.216
    Remapping_Appnote_0.Remapping_Appnote_MSS_0.MSS_ADLIB_INST     Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock     MSS_075     MDDR_FABRIC_PRDATA[15]     CORECONFIGP_0_MDDR_APBmslave_PRDATA[15]     4.956       3.477
    Remapping_Appnote_0.Remapping_Appnote_MSS_0.MSS_ADLIB_INST     Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock     MSS_075     MDDR_FABRIC_PRDATA[9]      CORECONFIGP_0_MDDR_APBmslave_PRDATA[9]      4.949       3.484
    Remapping_Appnote_0.Remapping_Appnote_MSS_0.MSS_ADLIB_INST     Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock     MSS_075     MDDR_FABRIC_PRDATA[4]      CORECONFIGP_0_MDDR_APBmslave_PRDATA[4]      4.943       3.490
    Remapping_Appnote_0.Remapping_Appnote_MSS_0.MSS_ADLIB_INST     Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock     MSS_075     MDDR_FABRIC_PRDATA[14]     CORECONFIGP_0_MDDR_APBmslave_PRDATA[14]     4.935       3.498
    Remapping_Appnote_0.Remapping_Appnote_MSS_0.MSS_ADLIB_INST     Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock     MSS_075     MDDR_FABRIC_PRDATA[10]     CORECONFIGP_0_MDDR_APBmslave_PRDATA[10]     4.892       3.541
    Remapping_Appnote_0.Remapping_Appnote_MSS_0.MSS_ADLIB_INST     Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock     MSS_075     MDDR_FABRIC_PRDATA[11]     CORECONFIGP_0_MDDR_APBmslave_PRDATA[11]     4.837       3.596
    =============================================================================================================================================================================================================================

    Ending Points with Worst Slack
    ******************************

                                                                 Starting                                                                                  Required
    Instance                                                     Reference                                                 Type     Pin     Net            Time         Slack
                                                                 Clock
    -------------------------------------------------------------------------------------------------------------------------------------------------------------------------
    Remapping_Appnote_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[1]      Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock     SLE      D       prdata[1]      4.778        1.835
    Remapping_Appnote_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[2]      Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock     SLE      D       prdata[2]      4.778        1.835
    Remapping_Appnote_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[3]      Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock     SLE      D       prdata[3]      4.778        1.895
    Remapping_Appnote_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[4]      Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock     SLE      D       prdata[4]      4.778        1.895
    Remapping_Appnote_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[6]      Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock     SLE      D       prdata[6]      4.778        1.895
    Remapping_Appnote_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[7]      Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock     SLE      D       prdata[7]      4.778        1.895
    Remapping_Appnote_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[8]      Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock     SLE      D       prdata[8]      4.778        1.895
    Remapping_Appnote_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[9]      Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock     SLE      D       prdata[9]      4.778        1.895
    Remapping_Appnote_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[10]     Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock     SLE      D       prdata[10]     4.778        1.895
    Remapping_Appnote_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[11]     Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock     SLE      D       prdata[11]     4.778        1.895
    =========================================================================================================================================================================

    Worst Path Information
    View Worst Path in Analyst
    ***********************

    Path information for path number 1:
          Requested Period:                      5.000
        - Setup time:                            0.222
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         4.778

        - Propagation time:                      2.943
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     1.835

        Number of logic level(s):                3
        Starting point:                          Remapping_Appnote_0.CORECONFIGP_0.psel / Q
        Ending point:                            Remapping_Appnote_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[1] / D
        The start point is clocked by            Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock [falling] on pin CLK
        The end   point is clocked by            Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock [rising] on pin CLK

    Instance / Net                                                       Pin      Pin               Arrival     No. of
    Name                                                        Type     Name     Dir     Delay     Time        Fan Out(s)
    ----------------------------------------------------------------------------------------------------------------------
    Remapping_Appnote_0.CORECONFIGP_0.psel                      SLE      Q        Out     0.076     0.076       -
    psel                                                        Net      -        -       0.637     -           3
    Remapping_Appnote_0.CORECONFIGP_0.MDDR_PSEL                 CFG4     D        In      -         0.714       -
    Remapping_Appnote_0.CORECONFIGP_0.MDDR_PSEL                 CFG4     Y        Out     0.236     0.950       -
    CORECONFIGP_0_MDDR_APBmslave_PSELx                          Net      -        -       0.994     -           20
    Remapping_Appnote_0.CORECONFIGP_0.prdata_0_iv_RNO_0[1]      CFG2     B        In      -         1.943       -
    Remapping_Appnote_0.CORECONFIGP_0.prdata_0_iv_RNO_0[1]      CFG2     Y        Out     0.143     2.086       -
    MDDR_PRDATA_m[1]                                            Net      -        -       0.483     -           1
    Remapping_Appnote_0.CORECONFIGP_0.prdata_0_iv[1]            CFG4     D        In      -         2.569       -
    Remapping_Appnote_0.CORECONFIGP_0.prdata_0_iv[1]            CFG4     Y        Out     0.236     2.805       -
    prdata[1]                                                   Net      -        -       0.138     -           1
    Remapping_Appnote_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[1]     SLE      D        In      -         2.943       -
    ======================================================================================================================
    Total path delay (propagation time + setup) of 3.165 is 0.913(28.9%) logic and 2.252(71.1%) route.
    Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value

    ##### END OF TIMING REPORT #####]

    Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 135MB peak: 137MB)

    Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 135MB peak: 137MB)

    ---------------------------------------
    Resource Usage Report for Remapping_Appnote_top

    Mapping to part: m2s090tfbga484-1
    Cell usage:
    CCC             1 use
    CLKINT          6 uses
    MSS_075         1 use
    RCOSC_25_50MHZ  1 use
    RCOSC_25_50MHZ_FAB  1 use
    SYSRESET        1 use
    CFG1           4 uses
    CFG2           11 uses
    CFG3           10 uses
    CFG4           35 uses

    Carry primitives used for arithmetic functions:
    ARI1           14 uses

    Sequential Cells:
    SLE            124 uses

    DSP Blocks:    0

    I/O ports: 63
    I/O primitives: 59
    BIBUF          18 uses
    BIBUF_DIFF     2 uses
    INBUF          2 uses
    OUTBUF         35 uses
    OUTBUF_DIFF    1 use
    TRIBUFF        1 use

    Global Clock Buffers: 6

    Total LUTs:    74

    Extra resources required for RAM and MACC interface logic during P&R:

    RAM64x18 Interface Logic : SLEs = 0; LUTs = 0;
    RAM1K18  Interface Logic : SLEs = 0; LUTs = 0;
    MACC     Interface Logic : SLEs = 0; LUTs = 0;

    Total number of SLEs after P&R:  124 + 0 + 0 + 0 = 124;
    Total number of LUTs after P&R:  74 + 0 + 0 + 0 = 74;

    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 50MB peak: 137MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Mon Mar 14 11:21:14 2016

    ###########################################################]

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