@W: BN132 :"c:\envm_multiple_images\liberoproject\remapping_appnote\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance Remapping_Appnote_0.CORERESETP_0.MDDR_DDR_AXI_S_CORE_RESET_N_int,  because it is equivalent to instance Remapping_Appnote_0.CORERESETP_0.FDDR_CORE_RESET_N_int
@W: MT530 :"c:\envm_multiple_images\liberoproject\remapping_appnote\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":546:4:546:9|Found inferred clock Remapping_Appnote_MSS|FIC_2_APB_M_PCLK_inferred_clock which controls 110 sequential elements including Remapping_Appnote_0.CORECONFIGP_0.FIC_2_APB_M_PRDATA[31:0]. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"c:\envm_multiple_images\liberoproject\remapping_appnote\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Found inferred clock Remapping_Appnote_CCC_0_FCCC|GL0_net_inferred_clock which controls 56 sequential elements including Remapping_Appnote_0.CORERESETP_0.count_ddr_enable. This clock has no specified timing constraint which may adversely impact design performance. 
@W: MT530 :"c:\envm_multiple_images\liberoproject\remapping_appnote\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1613:4:1613:9|Found inferred clock Remapping_Appnote_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 31 sequential elements including Remapping_Appnote_0.CORERESETP_0.count_ddr[13:0]. This clock has no specified timing constraint which may adversely impact design performance. 
