Project Settings Project Name MDDR_TA_top_syn Implementation Name synthesis_1 Top Module MDDR_TA_top Retiming 1 Resource Sharing 1 Fanout Guide 10000 Disable I/O Insertion 0 FSM Compiler 1 Run Status Job Name Status CPU Time Real Time Memory Date/Time Identify Database Generator out-of-date 0m:00s 8/4/2015 3:03:12 PM Identify Compile out-of-date 0m:00s 8/4/2015 3:03:22 PM (compiler) out-of-date 96 2118 0 - 0m:05s - 8/4/2015 3:03:28 PM (premap) out-of-date 78 17 0 0m:02s 0m:15s 171MB 8/4/2015 3:03:46 PM (fpga_mapper) Complete 437 3492 0 0m:06s 0m:07s 162MB 8/4/2015 3:03:54 PM Area Summary Carry Cells 260 Sequential Cells 1538 DSP Blocks (MACC) (dsp_used) 0 I/O Cells 51 Global Clock Buffers 10 Block Rams (RAM1K18) (v_ram) 55 LUTs (total_luts) 1062 Timing Summary Clock Name Req Freq Est Freq Slack MDDR_TA_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 139.7 MHz 2.841 MDDR_TA_CCC_0_FCCC|GL2_net_inferred_clock 100.0 MHz 153.4 MHz 3.480 MDDR_TA_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock 100.0 MHz 417.3 MHz 7.604 MDDR_TA_MSS|FIC_2_APB_M_PCLK_inferred_clock 100.0 MHz 110.0 MHz 0.909 ident_coreinst.comm_block_INST.dr2_tck 1.0 MHz 1016.2 MHz 999.016 ident_coreinst.comm_block_INST.tck 1.0 MHz 161.4 MHz 993.804 System 100.0 MHz 165.7 MHz 3.967 Optimizations Summary Retiming 33 / 96 Combined Clock Conversion 5 / 3