Microsemi Corporation - Microsemi Libero Software Release v11.7 (Version 11.7.0.119)

Date      :  Wed Mar 23 17:43:09 2016
Project   :  D:\Libero_11_7_publish\m2s_ac422_liberov11p6_df\Board_test\MDDR_TA
Component :  MDDR_TA
Family    :  SmartFusion2


HDL source files for all Synthesis and Simulation tools:
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_feedthrough.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_interconnect_ntom.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_master_stage.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_matrix_m.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_matrix_s.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_ra_arbiter.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_ra_channel.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rd_channel.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_16Sto1M.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S_hgs_high.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S_hgs_low.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_slave_stage.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wa_arbiter.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wa_channel.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wd_channel.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wresp_channel.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S_hgs_high.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S_hgs_low.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_addrdec.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_defaultslavesm.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_masterstage.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_matrix4x16.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavearbiter.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavestage.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/CoreConfigP/7.0.105/rtl/vlog/core/coreconfigp.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp_pcie_hotreset.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/work/MDDR_TA/CCC_0/MDDR_TA_CCC_0_FCCC.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/work/MDDR_TA/COREAXI_0/rtl/vlog/core/coreaxi.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/work/MDDR_TA/FABOSC_0/MDDR_TA_FABOSC_0_OSC.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/work/MDDR_TA/MDDR_TA.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/work/MDDR_TA_MSS/MDDR_TA_MSS.v

HDL source files for Synopsys SynplifyPro Synthesis tool:
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/SgCore/OSC/2.0.101/osc_comps.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/work/MDDR_TA_MSS/MDDR_TA_MSS_syn.v

HDL source files for Mentor Precision Synthesis tool:
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/SgCore/OSC/2.0.101/osc_comps_pre.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/work/MDDR_TA_MSS/MDDR_TA_MSS_pre.v

Stimulus files for all Simulation tools:
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/SmartFusion2MSS/MSS/1.1.400/peripheral_init.bfm
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/work/MDDR_TA_MSS/CM3_compile_bfm.tcl
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/work/MDDR_TA_MSS/test.bfm
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/work/MDDR_TA_MSS/user.bfm

    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/coreparameters.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/test/user/axi_master.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/test/user/axi_slave.v
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/work/MDDR_TA/COREAXI_0/rtl/vlog/test/user/testbench.v

Firmware files for all Software IDE tools:
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/work/MDDR_TA_MSS/sys_config_mddr_define.h
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/work/MDDR_TA_MSS/sys_config_mss_clocks.h

Configuration files to be used for Programming:
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/work/MDDR_TA_MSS/ENVM.cfg

Configuration files to be used for all Simulation tools:
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/work/MDDR_TA_MSS/ENVM.cfg
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/work/MDDR_TA_MSS/MDDR_init.bfm

Configuration files to be used for Power Analysis:
    D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/work/MDDR_TA_MSS/MDDR_init.reg

