Project Settings
Project Name | MDDR_TA_top_syn | Implementation Name | synthesis
Top Module | MDDR_TA_top | Retiming | 1
Resource Sharing | 0 | Fanout Guide | 10000
Disable I/O Insertion | 0 | FSM Compiler | 1

Run Status
Job Name | Status |  |  |  | CPU Time | Real Time | Memory | Date/Time
(compiler) | Complete | 72 | 2118 | 0 | - | 0m:03s | - | 3/23/2016 5:44:14 PM
(premap) | Complete | 51 | 10 | 0 | 0m:01s | 0m:01s | 167MB | 3/23/2016 5:44:19 PM
(fpga_mapper) | Complete | 225 | 3489 | 0 | 0m:04s | 0m:05s | 153MB | 3/23/2016 5:44:24 PM
Multi-srs Generator | Complete |  |  |  | 0m:01s |  |  | 3/23/2016 5:44:17 PM

Area Summary
Carry Cells | 218 | Sequential Cells | 632
DSP Blocks (MACC) (dsp_used) | 0 | I/O Cells | 53
Global Clock Buffers | 9 | Block Rams (RAM1K18) (v_ram) | 2
LUTs (total_luts) | 676 |  |

Timing Summary
Clock Name | Req Freq | Est Freq | Slack
--- | --- | --- | ---
MDDR_TA_0.CCC_0.GL0_net | 166.6 MHz | 150.8 MHz | -0.315
MDDR_TA_0.CCC_0.GL2_net | 166.6 MHz | 150.8 MHz | -0.099
MDDR_TA_0.FABOSC_0.I_RCOSC_25_50MHZ | 50.0 MHz | 111.9 MHz | 1.106
MDDR_TA_0.MDDR_TA_MSS_0.FIC_2_APB_M_PCLK | 41.7 MHz | 106.5 MHz | 5.016

Optimizations Summary
Retiming | 71 / 177 | Combined Clock Conversion | 4 / 0