Timing Report Max Delay Analysis

SmartTime Version 
Microsemi Corporation - Microsemi Libero Software Release  (Version 11.6.0.34)
Date: Fri Sep 11 17:05:37 2015


Design: MDDR_TA_top
Family: SmartFusion2
Die: M2S150T
Package: 1152 FC
Temperature Range: 0 - 85 C
Voltage Range: 1.14 - 1.26 V
Speed Grade: -1
Design State: Post-Layout
Data source: Production
Min Operating Conditions: BEST - 1.26 V - 0 C
Max Operating Conditions: WORST - 1.14 V - 85 C
Scenario for Timing Analysis: Primary


-----------------------------------------------------
SUMMARY

Clock Domain:               MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0                                        
Period (ns):                6.507                                                                           
Frequency (MHz):            153.681                                                                         
Required Period (ns):       6.002                                                                           
Required Frequency (MHz):   166.611                                                                         
External Setup (ns):        N/A                                                                             
External Hold (ns):         N/A                                                                             
Min Clock-To-Out (ns):      5.343                                                                           
Max Clock-To-Out (ns):      9.344                                                                           

Clock Domain:               MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2                                        
Period (ns):                5.608                                                                           
Frequency (MHz):            178.317                                                                         
Required Period (ns):       6.002                                                                           
Required Frequency (MHz):   166.611                                                                         
External Setup (ns):        N/A                                                                             
External Hold (ns):         N/A                                                                             
Min Clock-To-Out (ns):      N/A                                                                             
Max Clock-To-Out (ns):      N/A                                                                             

Clock Domain:               MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT                                      
Period (ns):                5.915                                                                           
Frequency (MHz):            169.062                                                                         
Required Period (ns):       20.000                                                                          
Required Frequency (MHz):   50.000                                                                          
External Setup (ns):        N/A                                                                             
External Hold (ns):         N/A                                                                             
Min Clock-To-Out (ns):      N/A                                                                             
Max Clock-To-Out (ns):      N/A                                                                             

Clock Domain:               fic2_apb_clk                                                                    
Period (ns):                8.736                                                                           
Frequency (MHz):            114.469                                                                         
Required Period (ns):       24.096                                                                          
Required Frequency (MHz):   41.501                                                                          
External Setup (ns):        N/A                                                                             
External Hold (ns):         N/A                                                                             
Min Clock-To-Out (ns):      N/A                                                                             
Max Clock-To-Out (ns):      N/A                                                                             

                            Input to Output                                                                 
Min Delay (ns):             N/A                                                                             
Max Delay (ns):             N/A                                                                             

END SUMMARY
-----------------------------------------------------

Clock Domain MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

SET Register to Register

Path 1
  From:                        MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel_fast:CLK
  To:                          MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[17]
  Delay (ns):                  3.223                                                                           
  Slack (ns):                  0.936                                                                           
  Arrival (ns):                8.552                                                                           
  Required (ns):               9.488                                                                           
  Setup (ns):                  2.051                                                                           
  Minimum Period (ns):         5.066                                                                           

Path 2
  From:                        MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel_fast:CLK
  To:                          MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_TRANS1
  Delay (ns):                  3.946                                                                           
  Slack (ns):                  0.939                                                                           
  Arrival (ns):                9.275                                                                           
  Required (ns):               10.214                                                                          
  Setup (ns):                  1.325                                                                           
  Minimum Period (ns):         5.063                                                                           

Path 3
  From:                        MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel_fast:CLK
  To:                          MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[11]
  Delay (ns):                  3.040                                                                           
  Slack (ns):                  0.955                                                                           
  Arrival (ns):                8.369                                                                           
  Required (ns):               9.324                                                                           
  Setup (ns):                  2.215                                                                           
  Minimum Period (ns):         5.047                                                                           

Path 4
  From:                        MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel_fast:CLK
  To:                          MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[22]
  Delay (ns):                  3.131                                                                           
  Slack (ns):                  0.971                                                                           
  Arrival (ns):                8.460                                                                           
  Required (ns):               9.431                                                                           
  Setup (ns):                  2.108                                                                           
  Minimum Period (ns):         5.031                                                                           

Path 5
  From:                        MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel_fast:CLK
  To:                          MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[9]
  Delay (ns):                  3.015                                                                           
  Slack (ns):                  1.017                                                                           
  Arrival (ns):                8.344                                                                           
  Required (ns):               9.361                                                                           
  Setup (ns):                  2.178                                                                           
  Minimum Period (ns):         4.985                                                                           


Expanded Path 1
  From: MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel_fast:CLK
  To: MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[17]
  data required time                             9.488     
  data arrival time                          -   8.552     
  slack                                          0.936     
  ________________________________________________________
  Data arrival time calculation
  0.000                        MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  0.000                        MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     3.422          Clock generation
  3.422                        
               +     0.282          net: MDDR_TA_0/CCC_0/GL0_net
  3.704                        MDDR_TA_0/CCC_0/GL0_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  3.847                        MDDR_TA_0/CCC_0/GL0_INST:YEn (f)
               +     0.594          net: MDDR_TA_0/CCC_0/GL0_INST/U0_YWn_GEast
  4.441                        MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB5:An (f)
               +     0.316          cell: ADLIB:RGB
  4.757                        MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB5:YR (r)
               +     0.572          net: MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB5_rgbr_net_1
  5.329                        MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel_fast:CLK (r)
               +     0.087          cell: ADLIB:SLE
  5.416                        MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel_fast:Q (r)
               +     0.851          net: MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterRegAddrSel_fast
  6.267                        MDDR_TA_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR_i_m2[31]:A (r)
               +     0.100          cell: ADLIB:CFG2
  6.367                        MDDR_TA_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR_i_m2[31]:Y (f)
               +     0.353          net: MDDR_TA_0/CoreAHBLite_0/matrix4x16/N_100
  6.720                        MDDR_TA_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_0_o2_0_RNI4S3Q_0[0]:B (f)
               +     0.087          cell: ADLIB:CFG4
  6.807                        MDDR_TA_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState_ns_i_0_o2_0_RNI4S3Q_0[0]:Y (f)
               +     0.389          net: MDDR_TA_0/CoreAHBLite_0/matrix4x16/slavestage_16/N_152
  7.196                        MDDR_TA_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR_0_a2[17]:B (f)
               +     0.095          cell: ADLIB:CFG4
  7.291                        MDDR_TA_0/CoreAHBLite_0/matrix4x16/slavestage_16/HADDR_0_a2[17]:Y (r)
               +     0.999          net: MDDR_TA_0/CoreAHBLite_0_AHBmslave16_HADDR[17]
  8.290                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_106:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  8.499                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_106:IPB (r)
               +     0.053          net: MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/F_FM0_ADDR_net[17]
  8.552                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[17] (r)
                                    
  8.552                        data arrival time
  ________________________________________________________
  Data required time calculation
  6.002                        MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  6.002                        MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     3.422          Clock generation
  9.424                        
               +     0.282          net: MDDR_TA_0/CCC_0/GL0_net
  9.706                        MDDR_TA_0/CCC_0/GL0_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  9.849                        MDDR_TA_0/CCC_0/GL0_INST:YEn (f)
               +     0.601          net: MDDR_TA_0/CCC_0/GL0_INST/U0_YWn_GEast
  10.450                       MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB3:An (f)
               +     0.316          cell: ADLIB:RGB
  10.766                       MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB3:YR (r)
               +     0.451          net: MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB3_rgbr_net_1
  11.217                       MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  11.426                       MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB (r)
               +     0.113          net: MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/CLK_BASE_net
  11.539                       MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE (r)
               -     2.051          Library setup time: ADLIB:MSS_120_IP
  9.488                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_FM0_ADDR[17]
                                    
  9.488                        data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path 

END SET External Setup

----------------------------------------------------

SET Clock to Output

Path 1
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE
  To:                          MMUART_0_TXD
  Delay (ns):                  3.794                                                                           
  Slack (ns):                                                                                                  
  Arrival (ns):                9.344                                                                           
  Required (ns):                                                                                               
  Clock to Out (ns):           9.344                                                                           


Expanded Path 1
  From: MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE
  To: MMUART_0_TXD
  data required time                             N/C       
  data arrival time                          -   9.344     
  slack                                          N/C       
  ________________________________________________________
  Data arrival time calculation
  0.000                        MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  0.000                        MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     3.422          Clock generation
  3.422                        
               +     0.282          net: MDDR_TA_0/CCC_0/GL0_net
  3.704                        MDDR_TA_0/CCC_0/GL0_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  3.847                        MDDR_TA_0/CCC_0/GL0_INST:YEn (f)
               +     0.601          net: MDDR_TA_0/CCC_0/GL0_INST/U0_YWn_GEast
  4.448                        MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB3:An (f)
               +     0.316          cell: ADLIB:RGB
  4.764                        MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB3:YR (r)
               +     0.451          net: MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB3_rgbr_net_1
  5.215                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  5.424                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB (r)
               +     0.126          net: MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/CLK_BASE_net
  5.550                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE (r)
               +     1.128          cell: ADLIB:MSS_120_IP
  6.678                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_TXD_USBC_DIR_MGPIO27B_OUT (f)
               +     0.000          net: MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OUT
  6.678                        MDDR_TA_0/MDDR_TA_MSS_0/MMUART_0_TXD_PAD/U_IOPAD:D (f)
               +     2.666          cell: ADLIB:IOPAD_TRI
  9.344                        MDDR_TA_0/MDDR_TA_MSS_0/MMUART_0_TXD_PAD/U_IOPAD:PAD (f)
               +     0.000          net: MMUART_0_TXD
  9.344                        MMUART_0_TXD (f)
                                    
  9.344                        data arrival time
  ________________________________________________________
  Data required time calculation
  N/C                          MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  N/C                          MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     3.422          Clock generation
  N/C                          
                                    
  N/C                          MMUART_0_TXD (f)


END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        MDDR_TA_0/CORERESETP_0/MSS_HPMS_READY_int:CLK
  To:                          MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHTRANS_fast:ALn
  Delay (ns):                  6.108                                                                           
  Slack (ns):                  -0.505                                                                          
  Arrival (ns):                11.426                                                                          
  Required (ns):               10.921                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         6.507                                                                           
  Skew (ns):                   0.046                                                                           

Path 2
  From:                        MDDR_TA_0/CORERESETP_0/MSS_HPMS_READY_int:CLK
  To:                          MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel_fast:ALn
  Delay (ns):                  6.108                                                                           
  Slack (ns):                  -0.505                                                                          
  Arrival (ns):                11.426                                                                          
  Required (ns):               10.921                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         6.507                                                                           
  Skew (ns):                   0.046                                                                           

Path 3
  From:                        MDDR_TA_0/CORERESETP_0/MSS_HPMS_READY_int:CLK
  To:                          MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel_rep1:ALn
  Delay (ns):                  6.095                                                                           
  Slack (ns):                  -0.493                                                                          
  Arrival (ns):                11.413                                                                          
  Required (ns):               10.920                                                                          
  Recovery (ns):               0.354                                                                           
  Minimum Period (ns):         6.495                                                                           
  Skew (ns):                   0.046                                                                           


Expanded Path 1
  From: MDDR_TA_0/CORERESETP_0/MSS_HPMS_READY_int:CLK
  To: MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHTRANS_fast:ALn
  data required time                             10.921    
  data arrival time                          -   11.426    
  slack                                          -0.505    
  ________________________________________________________
  Data arrival time calculation
  0.000                        MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  0.000                        MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     3.422          Clock generation
  3.422                        
               +     0.282          net: MDDR_TA_0/CCC_0/GL0_net
  3.704                        MDDR_TA_0/CCC_0/GL0_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  3.847                        MDDR_TA_0/CCC_0/GL0_INST:YEn (f)
               +     0.601          net: MDDR_TA_0/CCC_0/GL0_INST/U0_YWn_GEast
  4.448                        MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB2:An (f)
               +     0.316          cell: ADLIB:RGB
  4.764                        MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB2:YR (r)
               +     0.554          net: MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB2_rgbr_net_1
  5.318                        MDDR_TA_0/CORERESETP_0/MSS_HPMS_READY_int:CLK (r)
               +     0.087          cell: ADLIB:SLE
  5.405                        MDDR_TA_0/CORERESETP_0/MSS_HPMS_READY_int:Q (r)
               +     4.169          net: MDDR_TA_0/CORERESETP_0/MSS_HPMS_READY_int
  9.574                        MDDR_TA_0/CORERESETP_0/MSS_HPMS_READY_int_RNIPJE6:An (f)
               +     0.357          cell: ADLIB:GBM
  9.931                        MDDR_TA_0/CORERESETP_0/MSS_HPMS_READY_int_RNIPJE6:YEn (f)
               +     0.588          net: MDDR_TA_0/CORERESETP_0/MSS_HPMS_READY_int_RNIPJE6/U0_YWn_GEast
  10.519                       MDDR_TA_0/CORERESETP_0/MSS_HPMS_READY_int_RNIPJE6/U0_RGB1_RGB0:An (f)
               +     0.316          cell: ADLIB:RGB
  10.835                       MDDR_TA_0/CORERESETP_0/MSS_HPMS_READY_int_RNIPJE6/U0_RGB1_RGB0:YR (r)
               +     0.591          net: MDDR_TA_0/CORERESETP_0/MSS_HPMS_READY_int_RNIPJE6/U0_RGB1_RGB0_rgbr_net_1
  11.426                       MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHTRANS_fast:ALn (r)
                                    
  11.426                       data arrival time
  ________________________________________________________
  Data required time calculation
  6.002                        MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  6.002                        MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     3.422          Clock generation
  9.424                        
               +     0.282          net: MDDR_TA_0/CCC_0/GL0_net
  9.706                        MDDR_TA_0/CCC_0/GL0_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  9.849                        MDDR_TA_0/CCC_0/GL0_INST:YEn (f)
               +     0.594          net: MDDR_TA_0/CCC_0/GL0_INST/U0_YWn_GEast
  10.443                       MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB5:An (f)
               +     0.316          cell: ADLIB:RGB
  10.759                       MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB5:YR (r)
               +     0.515          net: MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB5_rgbr_net_1
  11.274                       MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHTRANS_fast:CLK (r)
               -     0.353          Library recovery time: ADLIB:SLE
  10.921                       MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHTRANS_fast:ALn
                                    
  10.921                       data required time


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path 

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

SET MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT to MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

No Path 

END SET MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT to MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

----------------------------------------------------

SET MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 to MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

Path 1
  From:                        AXI_IF_0/Rdata_mem_Rdata_mem_0_1/INST_RAM1K18_IP:A_CLK
  To:                          MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[47]
  Delay (ns):                  6.034                                                                           
  Slack (ns):                  -0.194                                                                          
  Arrival (ns):                11.464                                                                          
  Required (ns):               11.270                                                                          
  Setup (ns):                  4.267                                                                           

Path 2
  From:                        AXI_IF_0/Rdata_mem_Rdata_mem_0_1/INST_RAM1K18_IP:A_CLK
  To:                          MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[52]
  Delay (ns):                  5.967                                                                           
  Slack (ns):                  -0.071                                                                          
  Arrival (ns):                11.397                                                                          
  Required (ns):               11.326                                                                          
  Setup (ns):                  4.211                                                                           

Path 3
  From:                        AXI_IF_0/Rdata_mem_Rdata_mem_0_1/INST_RAM1K18_IP:A_CLK
  To:                          MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[60]
  Delay (ns):                  5.851                                                                           
  Slack (ns):                  0.013                                                                           
  Arrival (ns):                11.281                                                                          
  Required (ns):               11.294                                                                          
  Setup (ns):                  4.243                                                                           

Path 4
  From:                        AXI_IF_0/Rdata_mem_Rdata_mem_0_1/INST_RAM1K18_IP:A_CLK
  To:                          MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[48]
  Delay (ns):                  5.745                                                                           
  Slack (ns):                  0.020                                                                           
  Arrival (ns):                11.175                                                                          
  Required (ns):               11.195                                                                          
  Setup (ns):                  4.342                                                                           

Path 5
  From:                        AXI_IF_0/Rdata_mem_Rdata_mem_0_1/INST_RAM1K18_IP:A_CLK
  To:                          MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[45]
  Delay (ns):                  5.903                                                                           
  Slack (ns):                  0.103                                                                           
  Arrival (ns):                11.333                                                                          
  Required (ns):               11.436                                                                          
  Setup (ns):                  4.101                                                                           


Expanded Path 1
  From: AXI_IF_0/Rdata_mem_Rdata_mem_0_1/INST_RAM1K18_IP:A_CLK
  To: MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[47]
  data required time                             11.270    
  data arrival time                          -   11.464    
  slack                                          -0.194    
  ________________________________________________________
  Data arrival time calculation
  0.000                        MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2
               +     0.000          Clock source
  0.000                        MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 (r)
               +     3.421          Clock generation
  3.421                        
               +     0.288          net: MDDR_TA_0/CCC_0/GL2_net
  3.709                        MDDR_TA_0/CCC_0/GL2_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  3.852                        MDDR_TA_0/CCC_0/GL2_INST:YEn (f)
               +     0.602          net: MDDR_TA_0/CCC_0/GL2_INST/U0_YWn_GEast
  4.454                        MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB17:An (f)
               +     0.316          cell: ADLIB:RGB
  4.770                        MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB17:YR (r)
               +     0.524          net: MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB17_rgbr_net_1
  5.294                        AXI_IF_0/Rdata_mem_Rdata_mem_0_1/FF_0:CLK (r)
               +     0.059          cell: ADLIB:SLE_IP_CLK
  5.353                        AXI_IF_0/Rdata_mem_Rdata_mem_0_1/FF_0:IPCLKn (f)
               +     0.077          net: AXI_IF_0/Rdata_mem_Rdata_mem_0_1/A_CLK_net
  5.430                        AXI_IF_0/Rdata_mem_Rdata_mem_0_1/INST_RAM1K18_IP:A_CLK (r)
               +     2.143          cell: ADLIB:RAM1K18_IP
  7.573                        AXI_IF_0/Rdata_mem_Rdata_mem_0_1/INST_RAM1K18_IP:B_DOUT[15] (r)
               +     1.054          net: AXI_IF_0/Rdata_mem_reto[47]
  8.627                        AXI_IF_0/WDATA_ret_RNIC8IC[47]:A (r)
               +     0.303          cell: ADLIB:CFG3
  8.930                        AXI_IF_0/WDATA_ret_RNIC8IC[47]:Y (r)
               +     2.280          net: AXI_IF_0_BIF_1_WDATA[47]
  11.210                       MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_313:A (r)
               +     0.194          cell: ADLIB:IP_INTERFACE
  11.404                       MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_313:IPA (r)
               +     0.060          net: MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/F_WDATA_HWDATA01_net[47]
  11.464                       MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[47] (r)
                                    
  11.464                       data arrival time
  ________________________________________________________
  Data required time calculation
  10.000                       MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  10.000                       MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     3.422          Clock generation
  13.422                       
               +     0.282          net: MDDR_TA_0/CCC_0/GL0_net
  13.704                       MDDR_TA_0/CCC_0/GL0_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  13.847                       MDDR_TA_0/CCC_0/GL0_INST:YEn (f)
               +     0.601          net: MDDR_TA_0/CCC_0/GL0_INST/U0_YWn_GEast
  14.448                       MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB3:An (f)
               +     0.316          cell: ADLIB:RGB
  14.764                       MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB3:YR (r)
               +     0.451          net: MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB3_rgbr_net_1
  15.215                       MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B (r)
               +     0.209          cell: ADLIB:IP_INTERFACE
  15.424                       MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB (r)
               +     0.113          net: MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/CLK_BASE_net
  15.537                       MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE (r)
               -     4.267          Library setup time: ADLIB:MSS_120_IP
  11.270                       MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_WDATA_HWDATA01[47]
                                    
  11.270                       data required time


END SET MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 to MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

----------------------------------------------------

SET fic2_apb_clk to MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

Path 1
  From:                        MDDR_TA_0/CORECONFIGP_0/control_reg_1[0]:CLK
  To:                          MDDR_TA_0/CORERESETP_0/CONFIG1_DONE_q1:D
  Delay (ns):                  0.831                                                                           
  Slack (ns):                  3.603                                                                           
  Arrival (ns):                7.454                                                                           
  Required (ns):               11.057                                                                          
  Setup (ns):                  0.254                                                                           

Path 2
  From:                        MDDR_TA_0/CORECONFIGP_0/control_reg_1[1]:CLK
  To:                          MDDR_TA_0/CORERESETP_0/CONFIG2_DONE_q1:D
  Delay (ns):                  0.826                                                                           
  Slack (ns):                  3.613                                                                           
  Arrival (ns):                7.444                                                                           
  Required (ns):               11.057                                                                          
  Setup (ns):                  0.254                                                                           


Expanded Path 1
  From: MDDR_TA_0/CORECONFIGP_0/control_reg_1[0]:CLK
  To: MDDR_TA_0/CORERESETP_0/CONFIG1_DONE_q1:D
  data required time                             11.057    
  data arrival time                          -   7.454     
  slack                                          3.603     
  ________________________________________________________
  Data arrival time calculation
  0.000                        fic2_apb_clk
               +     0.000          Clock source
  0.000                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB (r)
               +     4.818          net: MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK
  4.818                        MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5:An (f)
               +     0.357          cell: ADLIB:GBM
  5.175                        MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5:YEn (f)
               +     0.594          net: MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5/U0_YWn_GEast
  5.769                        MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5/U0_RGB1_RGB1:An (f)
               +     0.316          cell: ADLIB:RGB
  6.085                        MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5/U0_RGB1_RGB1:YR (r)
               +     0.538          net: MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5/U0_RGB1_RGB1_rgbr_net_1
  6.623                        MDDR_TA_0/CORECONFIGP_0/control_reg_1[0]:CLK (r)
               +     0.087          cell: ADLIB:SLE
  6.710                        MDDR_TA_0/CORECONFIGP_0/control_reg_1[0]:Q (r)
               +     0.744          net: MDDR_TA_0/CORECONFIGP_0_CONFIG1_DONE
  7.454                        MDDR_TA_0/CORERESETP_0/CONFIG1_DONE_q1:D (r)
                                    
  7.454                        data arrival time
  ________________________________________________________
  Data required time calculation
  6.002                        MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  6.002                        MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     3.422          Clock generation
  9.424                        
               +     0.282          net: MDDR_TA_0/CCC_0/GL0_net
  9.706                        MDDR_TA_0/CCC_0/GL0_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  9.849                        MDDR_TA_0/CCC_0/GL0_INST:YEn (f)
               +     0.601          net: MDDR_TA_0/CCC_0/GL0_INST/U0_YWn_GEast
  10.450                       MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB1:An (f)
               +     0.316          cell: ADLIB:RGB
  10.766                       MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB1:YR (r)
               +     0.545          net: MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB1_rgbr_net_1
  11.311                       MDDR_TA_0/CORERESETP_0/CONFIG1_DONE_q1:CLK (r)
               -     0.254          Library setup time: ADLIB:SLE
  11.057                       MDDR_TA_0/CORERESETP_0/CONFIG1_DONE_q1:D
                                    
  11.057                       data required time


END SET fic2_apb_clk to MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0

----------------------------------------------------

Clock Domain MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2

SET Register to Register

Path 1
  From:                        AXI_IF_0/rburst_cnt[5]:CLK
  To:                          AXI_IF_0/WRITE_AHB:EN
  Delay (ns):                  5.229                                                                           
  Slack (ns):                  0.394                                                                           
  Arrival (ns):                10.569                                                                          
  Required (ns):               10.963                                                                          
  Setup (ns):                  0.335                                                                           
  Minimum Period (ns):         5.608                                                                           

Path 2
  From:                        AXI_IF_0/rburst_cnt[6]:CLK
  To:                          AXI_IF_0/WRITE_AHB:EN
  Delay (ns):                  4.901                                                                           
  Slack (ns):                  0.710                                                                           
  Arrival (ns):                10.253                                                                          
  Required (ns):               10.963                                                                          
  Setup (ns):                  0.335                                                                           
  Minimum Period (ns):         5.292                                                                           

Path 3
  From:                        AXI_IF_0/ARADDR[17]:CLK
  To:                          AXI_IF_0/ARADDR[30]:D
  Delay (ns):                  4.930                                                                           
  Slack (ns):                  0.773                                                                           
  Arrival (ns):                10.273                                                                          
  Required (ns):               11.046                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         5.229                                                                           

Path 4
  From:                        AXI_IF_0/ARADDR[17]:CLK
  To:                          AXI_IF_0/ARADDR[27]:D
  Delay (ns):                  4.885                                                                           
  Slack (ns):                  0.807                                                                           
  Arrival (ns):                10.228                                                                          
  Required (ns):               11.035                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         5.195                                                                           

Path 5
  From:                        AXI_IF_0/ARADDR[17]:CLK
  To:                          AXI_IF_0/ARADDR[29]:D
  Delay (ns):                  4.871                                                                           
  Slack (ns):                  0.821                                                                           
  Arrival (ns):                10.214                                                                          
  Required (ns):               11.035                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         5.181                                                                           


Expanded Path 1
  From: AXI_IF_0/rburst_cnt[5]:CLK
  To: AXI_IF_0/WRITE_AHB:EN
  data required time                             10.963    
  data arrival time                          -   10.569    
  slack                                          0.394     
  ________________________________________________________
  Data arrival time calculation
  0.000                        MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2
               +     0.000          Clock source
  0.000                        MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 (r)
               +     3.421          Clock generation
  3.421                        
               +     0.288          net: MDDR_TA_0/CCC_0/GL2_net
  3.709                        MDDR_TA_0/CCC_0/GL2_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  3.852                        MDDR_TA_0/CCC_0/GL2_INST:YEn (f)
               +     0.609          net: MDDR_TA_0/CCC_0/GL2_INST/U0_YWn_GEast
  4.461                        MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB0:An (f)
               +     0.316          cell: ADLIB:RGB
  4.777                        MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB0:YR (r)
               +     0.563          net: MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB0_rgbr_net_1
  5.340                        AXI_IF_0/rburst_cnt[5]:CLK (r)
               +     0.087          cell: ADLIB:SLE
  5.427                        AXI_IF_0/rburst_cnt[5]:Q (r)
               +     1.018          net: AXI_IF_0/rburst_cnt[5]
  6.445                        AXI_IF_0/rburst_cnt_RNI6BH21[5]:D (r)
               +     0.158          cell: ADLIB:CFG4
  6.603                        AXI_IF_0/rburst_cnt_RNI6BH21[5]:Y (r)
               +     0.426          net: AXI_IF_0/g0_1_1
  7.029                        AXI_IF_0/r_xfer_size_1_ret_4_RNIG0912:A (r)
               +     0.158          cell: ADLIB:CFG3
  7.187                        AXI_IF_0/r_xfer_size_1_ret_4_RNIG0912:Y (r)
               +     1.242          net: AXI_IF_0/un3_ahb1_NE
  8.429                        AXI_IF_0/ahb_state_ns_i_a3[0]:D (r)
               +     0.158          cell: ADLIB:CFG4
  8.587                        AXI_IF_0/ahb_state_ns_i_a3[0]:Y (r)
               +     0.357          net: AXI_IF_0/N_768
  8.944                        AXI_IF_0/WRITE_AHB_RNO_0:A (r)
               +     0.100          cell: ADLIB:CFG2
  9.044                        AXI_IF_0/WRITE_AHB_RNO_0:Y (f)
               +     1.525          net: AXI_IF_0/N_456_i_0
  10.569                       AXI_IF_0/WRITE_AHB:EN (f)
                                    
  10.569                       data arrival time
  ________________________________________________________
  Data required time calculation
  6.002                        MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2
               +     0.000          Clock source
  6.002                        MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 (r)
               +     3.421          Clock generation
  9.423                        
               +     0.288          net: MDDR_TA_0/CCC_0/GL2_net
  9.711                        MDDR_TA_0/CCC_0/GL2_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  9.854                        MDDR_TA_0/CCC_0/GL2_INST:YEn (f)
               +     0.599          net: MDDR_TA_0/CCC_0/GL2_INST/U0_YWn_GEast
  10.453                       MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB10:An (f)
               +     0.316          cell: ADLIB:RGB
  10.769                       MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB10:YR (r)
               +     0.529          net: MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB10_rgbr_net_1
  11.298                       AXI_IF_0/WRITE_AHB:CLK (r)
               -     0.335          Library setup time: ADLIB:SLE
  10.963                       AXI_IF_0/WRITE_AHB:EN
                                    
  10.963                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path 

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path 

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path 

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path 

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

SET MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2

Path 1
  From:                        MDDR_TA_0/CORERESETP_0/INIT_DONE_int:CLK
  To:                          AXI_IF_0/r_xfer_size_1_ret:ALn
  Delay (ns):                  6.503                                                                           
  Slack (ns):                  -0.870                                                                          
  Arrival (ns):                11.802                                                                          
  Required (ns):               10.932                                                                          
  Setup (ns):                                                                                                  

Path 2
  From:                        MDDR_TA_0/CORERESETP_0/INIT_DONE_int:CLK
  To:                          AXI_IF_0/rburst_cnt_fast[8]:ALn
  Delay (ns):                  6.503                                                                           
  Slack (ns):                  -0.870                                                                          
  Arrival (ns):                11.802                                                                          
  Required (ns):               10.932                                                                          
  Setup (ns):                                                                                                  

Path 3
  From:                        MDDR_TA_0/CORERESETP_0/INIT_DONE_int:CLK
  To:                          AXI_IF_0/rburst_cnt[4]:ALn
  Delay (ns):                  6.503                                                                           
  Slack (ns):                  -0.870                                                                          
  Arrival (ns):                11.802                                                                          
  Required (ns):               10.932                                                                          
  Setup (ns):                                                                                                  

Path 4
  From:                        MDDR_TA_0/CORERESETP_0/INIT_DONE_int:CLK
  To:                          AXI_IF_0/r_xfer_size_1_ret_4:ALn
  Delay (ns):                  6.503                                                                           
  Slack (ns):                  -0.870                                                                          
  Arrival (ns):                11.802                                                                          
  Required (ns):               10.932                                                                          
  Setup (ns):                                                                                                  

Path 5
  From:                        MDDR_TA_0/CORERESETP_0/INIT_DONE_int:CLK
  To:                          AXI_IF_0/rburst_cnt_fast[5]:ALn
  Delay (ns):                  6.504                                                                           
  Slack (ns):                  -0.870                                                                          
  Arrival (ns):                11.803                                                                          
  Required (ns):               10.933                                                                          
  Setup (ns):                                                                                                  


Expanded Path 1
  From: MDDR_TA_0/CORERESETP_0/INIT_DONE_int:CLK
  To: AXI_IF_0/r_xfer_size_1_ret:ALn
  data required time                             10.932    
  data arrival time                          -   11.802    
  slack                                          -0.870    
  ________________________________________________________
  Data arrival time calculation
  0.000                        MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  0.000                        MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     3.422          Clock generation
  3.422                        
               +     0.282          net: MDDR_TA_0/CCC_0/GL0_net
  3.704                        MDDR_TA_0/CCC_0/GL0_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  3.847                        MDDR_TA_0/CCC_0/GL0_INST:YEn (f)
               +     0.602          net: MDDR_TA_0/CCC_0/GL0_INST/U0_YWn_GEast
  4.449                        MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0:An (f)
               +     0.316          cell: ADLIB:RGB
  4.765                        MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0:YR (r)
               +     0.534          net: MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0_rgbr_net_1
  5.299                        MDDR_TA_0/CORERESETP_0/INIT_DONE_int:CLK (r)
               +     0.087          cell: ADLIB:SLE
  5.386                        MDDR_TA_0/CORERESETP_0/INIT_DONE_int:Q (r)
               +     4.535          net: MDDR_TA_0/CORERESETP_0/INIT_DONE_int
  9.921                        MDDR_TA_0/CORERESETP_0/INIT_DONE_int_RNIKK5F:An (f)
               +     0.357          cell: ADLIB:GBM
  10.278                       MDDR_TA_0/CORERESETP_0/INIT_DONE_int_RNIKK5F:YEn (f)
               +     0.615          net: MDDR_TA_0/CORERESETP_0/INIT_DONE_int_RNIKK5F/U0_YWn_GEast
  10.893                       MDDR_TA_0/CORERESETP_0/INIT_DONE_int_RNIKK5F/U0_RGB1_RGB0:An (f)
               +     0.316          cell: ADLIB:RGB
  11.209                       MDDR_TA_0/CORERESETP_0/INIT_DONE_int_RNIKK5F/U0_RGB1_RGB0:YR (r)
               +     0.593          net: MDDR_TA_0/CORERESETP_0/INIT_DONE_int_RNIKK5F/U0_RGB1_RGB0_rgbr_net_1
  11.802                       AXI_IF_0/r_xfer_size_1_ret:ALn (r)
                                    
  11.802                       data arrival time
  ________________________________________________________
  Data required time calculation
  6.002                        MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2
               +     0.000          Clock source
  6.002                        MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 (r)
               +     3.421          Clock generation
  9.423                        
               +     0.288          net: MDDR_TA_0/CCC_0/GL2_net
  9.711                        MDDR_TA_0/CCC_0/GL2_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  9.854                        MDDR_TA_0/CCC_0/GL2_INST:YEn (f)
               +     0.609          net: MDDR_TA_0/CCC_0/GL2_INST/U0_YWn_GEast
  10.463                       MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB0:An (f)
               +     0.316          cell: ADLIB:RGB
  10.779                       MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB0:YR (r)
               +     0.506          net: MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB0_rgbr_net_1
  11.285                       AXI_IF_0/r_xfer_size_1_ret:CLK (r)
               -     0.353          Library recovery time: ADLIB:SLE
  10.932                       AXI_IF_0/r_xfer_size_1_ret:ALn
                                    
  10.932                       data required time


END SET MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2

----------------------------------------------------

Clock Domain MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT

SET Register to Register

Path 1
  From:                        MDDR_TA_0/CORERESETP_0/count_ddr[13]:CLK
  To:                          MDDR_TA_0/CORERESETP_0/ddr_settled:EN
  Delay (ns):                  2.358                                                                           
  Slack (ns):                  17.272                                                                          
  Arrival (ns):                10.723                                                                          
  Required (ns):               27.995                                                                          
  Setup (ns):                  0.335                                                                           
  Minimum Period (ns):         2.728                                                                           

Path 2
  From:                        MDDR_TA_0/CORERESETP_0/count_ddr[6]:CLK
  To:                          MDDR_TA_0/CORERESETP_0/ddr_settled:EN
  Delay (ns):                  2.334                                                                           
  Slack (ns):                  17.274                                                                          
  Arrival (ns):                10.721                                                                          
  Required (ns):               27.995                                                                          
  Setup (ns):                  0.335                                                                           
  Minimum Period (ns):         2.726                                                                           

Path 3
  From:                        MDDR_TA_0/CORERESETP_0/count_ddr[5]:CLK
  To:                          MDDR_TA_0/CORERESETP_0/ddr_settled:EN
  Delay (ns):                  2.202                                                                           
  Slack (ns):                  17.415                                                                          
  Arrival (ns):                10.580                                                                          
  Required (ns):               27.995                                                                          
  Setup (ns):                  0.335                                                                           
  Minimum Period (ns):         2.585                                                                           

Path 4
  From:                        MDDR_TA_0/CORERESETP_0/count_ddr[7]:CLK
  To:                          MDDR_TA_0/CORERESETP_0/ddr_settled:EN
  Delay (ns):                  2.164                                                                           
  Slack (ns):                  17.453                                                                          
  Arrival (ns):                10.542                                                                          
  Required (ns):               27.995                                                                          
  Setup (ns):                  0.335                                                                           
  Minimum Period (ns):         2.547                                                                           

Path 5
  From:                        MDDR_TA_0/CORERESETP_0/count_ddr[3]:CLK
  To:                          MDDR_TA_0/CORERESETP_0/ddr_settled:EN
  Delay (ns):                  2.149                                                                           
  Slack (ns):                  17.468                                                                          
  Arrival (ns):                10.527                                                                          
  Required (ns):               27.995                                                                          
  Setup (ns):                  0.335                                                                           
  Minimum Period (ns):         2.532                                                                           


Expanded Path 1
  From: MDDR_TA_0/CORERESETP_0/count_ddr[13]:CLK
  To: MDDR_TA_0/CORERESETP_0/ddr_settled:EN
  data required time                             27.995    
  data arrival time                          -   10.723    
  slack                                          17.272    
  ________________________________________________________
  Data arrival time calculation
  0.000                        MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT
               +     0.000          Clock source
  0.000                        MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT (r)
               +     1.392          net: MDDR_TA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
  1.392                        MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A (r)
               +     0.152          cell: ADLIB:RCOSC_25_50MHZ_FAB
  1.544                        MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT (r)
               +     5.005          net: MDDR_TA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT
  6.549                        MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An (f)
               +     0.357          cell: ADLIB:GBM
  6.906                        MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn (f)
               +     0.591          net: MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast
  7.497                        MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An (f)
               +     0.316          cell: ADLIB:RGB
  7.813                        MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YR (r)
               +     0.552          net: MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbr_net_1
  8.365                        MDDR_TA_0/CORERESETP_0/count_ddr[13]:CLK (r)
               +     0.108          cell: ADLIB:SLE
  8.473                        MDDR_TA_0/CORERESETP_0/count_ddr[13]:Q (f)
               +     0.610          net: MDDR_TA_0/CORERESETP_0/count_ddr[13]
  9.083                        MDDR_TA_0/CORERESETP_0/ddr_settled4_6:B (f)
               +     0.164          cell: ADLIB:CFG2
  9.247                        MDDR_TA_0/CORERESETP_0/ddr_settled4_6:Y (f)
               +     0.602          net: MDDR_TA_0/CORERESETP_0/ddr_settled4_6
  9.849                        MDDR_TA_0/CORERESETP_0/ddr_settled4:C (f)
               +     0.164          cell: ADLIB:CFG4
  10.013                       MDDR_TA_0/CORERESETP_0/ddr_settled4:Y (f)
               +     0.710          net: MDDR_TA_0/CORERESETP_0/ddr_settled4
  10.723                       MDDR_TA_0/CORERESETP_0/ddr_settled:EN (f)
                                    
  10.723                       data arrival time
  ________________________________________________________
  Data required time calculation
  20.000                       MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT
               +     0.000          Clock source
  20.000                       MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT (r)
               +     1.392          net: MDDR_TA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
  21.392                       MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A (r)
               +     0.152          cell: ADLIB:RCOSC_25_50MHZ_FAB
  21.544                       MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT (r)
               +     5.005          net: MDDR_TA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT
  26.549                       MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An (f)
               +     0.357          cell: ADLIB:GBM
  26.906                       MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn (f)
               +     0.591          net: MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast
  27.497                       MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An (f)
               +     0.316          cell: ADLIB:RGB
  27.813                       MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YR (r)
               +     0.517          net: MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbr_net_1
  28.330                       MDDR_TA_0/CORERESETP_0/ddr_settled:CLK (r)
               -     0.335          Library setup time: ADLIB:SLE
  27.995                       MDDR_TA_0/CORERESETP_0/ddr_settled:EN
                                    
  27.995                       data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path 

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path 

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

Path 1
  From:                        MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK
  To:                          MDDR_TA_0/CORERESETP_0/count_ddr[11]:ALn
  Delay (ns):                  5.543                                                                           
  Slack (ns):                  14.085                                                                          
  Arrival (ns):                13.872                                                                          
  Required (ns):               27.957                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         5.915                                                                           
  Skew (ns):                   0.019                                                                           

Path 2
  From:                        MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK
  To:                          MDDR_TA_0/CORERESETP_0/count_ddr[13]:ALn
  Delay (ns):                  5.543                                                                           
  Slack (ns):                  14.085                                                                          
  Arrival (ns):                13.872                                                                          
  Required (ns):               27.957                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         5.915                                                                           
  Skew (ns):                   0.019                                                                           

Path 3
  From:                        MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK
  To:                          MDDR_TA_0/CORERESETP_0/release_sdif0_core:ALn
  Delay (ns):                  5.543                                                                           
  Slack (ns):                  14.085                                                                          
  Arrival (ns):                13.872                                                                          
  Required (ns):               27.957                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         5.915                                                                           
  Skew (ns):                   0.019                                                                           

Path 4
  From:                        MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK
  To:                          MDDR_TA_0/CORERESETP_0/count_ddr[9]:ALn
  Delay (ns):                  5.543                                                                           
  Slack (ns):                  14.085                                                                          
  Arrival (ns):                13.872                                                                          
  Required (ns):               27.957                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         5.915                                                                           
  Skew (ns):                   0.019                                                                           

Path 5
  From:                        MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK
  To:                          MDDR_TA_0/CORERESETP_0/count_ddr[5]:ALn
  Delay (ns):                  5.552                                                                           
  Slack (ns):                  14.088                                                                          
  Arrival (ns):                13.881                                                                          
  Required (ns):               27.969                                                                          
  Recovery (ns):               0.353                                                                           
  Minimum Period (ns):         5.912                                                                           
  Skew (ns):                   0.007                                                                           


Expanded Path 1
  From: MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK
  To: MDDR_TA_0/CORERESETP_0/count_ddr[11]:ALn
  data required time                             27.957    
  data arrival time                          -   13.872    
  slack                                          14.085    
  ________________________________________________________
  Data arrival time calculation
  0.000                        MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT
               +     0.000          Clock source
  0.000                        MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT (r)
               +     1.392          net: MDDR_TA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
  1.392                        MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A (r)
               +     0.152          cell: ADLIB:RCOSC_25_50MHZ_FAB
  1.544                        MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT (r)
               +     5.005          net: MDDR_TA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT
  6.549                        MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An (f)
               +     0.357          cell: ADLIB:GBM
  6.906                        MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn (f)
               +     0.579          net: MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast
  7.485                        MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:An (f)
               +     0.316          cell: ADLIB:RGB
  7.801                        MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1:YR (r)
               +     0.528          net: MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB1_rgbr_net_1
  8.329                        MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK (r)
               +     0.087          cell: ADLIB:SLE
  8.416                        MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:Q (r)
               +     3.606          net: MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc
  12.022                       MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIGC0B:An (f)
               +     0.357          cell: ADLIB:GBM
  12.379                       MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIGC0B:YEn (f)
               +     0.602          net: MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIGC0B/U0_YWn_GEast
  12.981                       MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIGC0B/U0_RGB1_RGB0:An (f)
               +     0.316          cell: ADLIB:RGB
  13.297                       MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIGC0B/U0_RGB1_RGB0:YR (r)
               +     0.575          net: MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIGC0B/U0_RGB1_RGB0_rgbr_net_1
  13.872                       MDDR_TA_0/CORERESETP_0/count_ddr[11]:ALn (r)
                                    
  13.872                       data arrival time
  ________________________________________________________
  Data required time calculation
  20.000                       MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT
               +     0.000          Clock source
  20.000                       MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT (r)
               +     1.392          net: MDDR_TA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
  21.392                       MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A (r)
               +     0.152          cell: ADLIB:RCOSC_25_50MHZ_FAB
  21.544                       MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT (r)
               +     5.005          net: MDDR_TA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT
  26.549                       MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An (f)
               +     0.357          cell: ADLIB:GBM
  26.906                       MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn (f)
               +     0.591          net: MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast
  27.497                       MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:An (f)
               +     0.316          cell: ADLIB:RGB
  27.813                       MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0:YR (r)
               +     0.497          net: MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_RGB0_rgbr_net_1
  28.310                       MDDR_TA_0/CORERESETP_0/count_ddr[11]:CLK (r)
               -     0.353          Library recovery time: ADLIB:SLE
  27.957                       MDDR_TA_0/CORERESETP_0/count_ddr[11]:ALn
                                    
  27.957                       data required time


END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path 

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

SET MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT

No Path 

END SET MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT

----------------------------------------------------

Clock Domain fic2_apb_clk

SET Register to Register

Path 1
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN
  Delay (ns):                  2.828                                                                           
  Slack (ns):                  3.443                                                                           
  Arrival (ns):                2.828                                                                           
  Required (ns):               6.271                                                                           
  Setup (ns):                  0.335                                                                           
  Minimum Period (ns):         -3.443                                                                          

Path 2
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/state[0]:D
  Delay (ns):                  2.553                                                                           
  Slack (ns):                  3.789                                                                           
  Arrival (ns):                2.553                                                                           
  Required (ns):               6.342                                                                           
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         -3.789                                                                          

Path 3
  From:                        MDDR_TA_0/CORECONFIGP_0/psel:CLK
  To:                          MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[9]:D
  Delay (ns):                  2.765                                                                           
  Slack (ns):                  8.694                                                                           
  Arrival (ns):                9.706                                                                           
  Required (ns):               18.400                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         6.708                                                                           

Path 4
  From:                        MDDR_TA_0/CORECONFIGP_0/psel:CLK
  To:                          MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[2]:D
  Delay (ns):                  2.765                                                                           
  Slack (ns):                  8.695                                                                           
  Arrival (ns):                9.706                                                                           
  Required (ns):               18.401                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         6.706                                                                           

Path 5
  From:                        MDDR_TA_0/CORECONFIGP_0/psel:CLK
  To:                          MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[8]:D
  Delay (ns):                  2.764                                                                           
  Slack (ns):                  8.696                                                                           
  Arrival (ns):                9.705                                                                           
  Required (ns):               18.401                                                                          
  Setup (ns):                  0.254                                                                           
  Minimum Period (ns):         6.704                                                                           


Expanded Path 1
  From: MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To: MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN
  data required time                             6.271     
  data arrival time                          -   2.828     
  slack                                          3.443     
  ________________________________________________________
  Data arrival time calculation
  0.000                        fic2_apb_clk
               +     0.000          Clock source
  0.000                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB (r)
               +     0.310          cell: ADLIB:MSS_120_IP
  0.310                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:PER2_FABRIC_PENABLE (r)
               +     1.704          net: MDDR_TA_0/MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE
  2.014                        MDDR_TA_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_o3:B (r)
               +     0.074          cell: ADLIB:CFG3
  2.088                        MDDR_TA_0/CORECONFIGP_0/un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_o3:Y (r)
               +     0.098          net: MDDR_TA_0/CORECONFIGP_0/N_43
  2.186                        MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY_RNO:D (r)
               +     0.100          cell: ADLIB:CFG4
  2.286                        MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY_RNO:Y (f)
               +     0.542          net: MDDR_TA_0/CORECONFIGP_0/N_28_i_0
  2.828                        MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN (f)
                                    
  2.828                        data arrival time
  ________________________________________________________
  Data required time calculation
  0.000                        fic2_apb_clk
               +     0.000          Clock source
  0.000                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB (r)
               +     4.818          net: MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK
  4.818                        MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5:An (f)
               +     0.357          cell: ADLIB:GBM
  5.175                        MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5:YEn (f)
               +     0.594          net: MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5/U0_YWn_GEast
  5.769                        MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5/U0_RGB1_RGB1:An (f)
               +     0.316          cell: ADLIB:RGB
  6.085                        MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5/U0_RGB1_RGB1:YR (r)
               +     0.521          net: MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5/U0_RGB1_RGB1_rgbr_net_1
  6.606                        MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:CLK (r)
               -     0.335          Library setup time: ADLIB:SLE
  6.271                        MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PREADY:EN
                                    
  6.271                        data required time


END SET Register to Register

----------------------------------------------------

SET External Setup

No Path 

END SET External Setup

----------------------------------------------------

SET Clock to Output

No Path 

END SET Clock to Output

----------------------------------------------------

SET Register to Asynchronous

No Path 

END SET Register to Asynchronous

----------------------------------------------------

SET External Recovery

No Path 

END SET External Recovery

----------------------------------------------------

SET Asynchronous to Register

No Path 

END SET Asynchronous to Register

----------------------------------------------------

SET MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to fic2_apb_clk

Path 1
  From:                        MDDR_TA_0/CORERESETP_0/INIT_DONE_int:CLK
  To:                          MDDR_TA_0/CORECONFIGP_0/INIT_DONE_q1:D
  Delay (ns):                  0.489                                                                           
  Slack (ns):                  6.529                                                                           
  Arrival (ns):                5.788                                                                           
  Required (ns):               12.317                                                                          
  Setup (ns):                  0.254                                                                           


Expanded Path 1
  From: MDDR_TA_0/CORERESETP_0/INIT_DONE_int:CLK
  To: MDDR_TA_0/CORECONFIGP_0/INIT_DONE_q1:D
  data required time                             12.317    
  data arrival time                          -   5.788     
  slack                                          6.529     
  ________________________________________________________
  Data arrival time calculation
  0.000                        MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0
               +     0.000          Clock source
  0.000                        MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (r)
               +     3.422          Clock generation
  3.422                        
               +     0.282          net: MDDR_TA_0/CCC_0/GL0_net
  3.704                        MDDR_TA_0/CCC_0/GL0_INST:An (r)
               +     0.143          cell: ADLIB:GBM
  3.847                        MDDR_TA_0/CCC_0/GL0_INST:YEn (f)
               +     0.602          net: MDDR_TA_0/CCC_0/GL0_INST/U0_YWn_GEast
  4.449                        MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0:An (f)
               +     0.316          cell: ADLIB:RGB
  4.765                        MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0:YR (r)
               +     0.534          net: MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0_rgbr_net_1
  5.299                        MDDR_TA_0/CORERESETP_0/INIT_DONE_int:CLK (r)
               +     0.087          cell: ADLIB:SLE
  5.386                        MDDR_TA_0/CORERESETP_0/INIT_DONE_int:Q (r)
               +     0.402          net: MDDR_TA_0/CORERESETP_0/INIT_DONE_int
  5.788                        MDDR_TA_0/CORECONFIGP_0/INIT_DONE_q1:D (r)
                                    
  5.788                        data arrival time
  ________________________________________________________
  Data required time calculation
  6.002                        fic2_apb_clk
               +     0.000          Clock source
  6.002                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB (r)
               +     4.818          net: MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK
  10.820                       MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5:An (f)
               +     0.357          cell: ADLIB:GBM
  11.177                       MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5:YEn (f)
               +     0.594          net: MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5/U0_YWn_GEast
  11.771                       MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5/U0_RGB1_RGB1:An (f)
               +     0.316          cell: ADLIB:RGB
  12.087                       MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5/U0_RGB1_RGB1:YR (r)
               +     0.484          net: MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5/U0_RGB1_RGB1_rgbr_net_1
  12.571                       MDDR_TA_0/CORECONFIGP_0/INIT_DONE_q1:CLK (r)
               -     0.254          Library setup time: ADLIB:SLE
  12.317                       MDDR_TA_0/CORECONFIGP_0/INIT_DONE_q1:D
                                    
  12.317                       data required time


END SET MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to fic2_apb_clk

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Path set Pin to Pin

SET Input to Output

No Path 

END SET Input to Output

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Path set User Sets

