/*-----------------------------------------------------------------------------
 Title      : Command Decoder
-------------------------------------------------------------------------------
 File       : CMD_Decoder.v
 Author     : Corporate Applications Engineering
 Company    : Microsemi Corporation
 Device     : SmartFusion2
 Standard   : Verilog
-------------------------------------------------------------------------------
 Description: The command decoder receives the AXI transaction control from 
 Cortex-M3 via GPIOs and generates write, read, write size and read size signals
-------------------------------------------------------------------------------
 Copyright (c) 2014   Microsemi Corporation
                      All rights reserved.
-------------------------------------------------------------------------------
 Revisions  : V1.0
------------------------------------------------------------------------------- */ 
module CMD_Decode(
	input 		      CLK,
	input 		      RESETn,
	input  [7:0]      command,
	output reg        write_start,
	output reg        read_start,
	output reg [9:0]  w_xfer_size,
    output reg [9:0]  r_xfer_size);

wire [1:0] WR_CMD;
wire [2:0] WS_CMD;
wire [2:0] RS_CMD;

assign WR_CMD = {command[1],command[0]};
assign WS_CMD = {command[4],command[3],command[2]};
assign RS_CMD = {command[7],command[6],command[5]};

always@(posedge CLK, negedge RESETn)
begin	
  if( RESETn == 1'b0 )
    begin	
		write_start  <= 0;
		read_start   <= 0;
	end
  else
	begin
	  case (WR_CMD)
		2'b00:
		  begin
			write_start  <= 0;
			read_start   <= 0;
		  end
		2'b01:
		  begin
			write_start  <= 1;
			read_start   <= 0;
		  end
		2'b10:
		  begin
			write_start  <= 0;
			read_start   <= 1;
		  end
		2'b11:
		  begin
			write_start  <= 0;
			read_start   <= 0;
		  end
	  endcase
   end
end

always@(posedge CLK, negedge RESETn)
begin	
  if( RESETn == 1'b0 )
    begin	
      w_xfer_size   = 10'h00;
	end
  else
	begin
	  case (WS_CMD)
		3'b000:
		  begin
      		w_xfer_size   = 10'h00; 
		  end
		3'b001:
		  begin
      		w_xfer_size   = 10'h10;
		  end
		3'b010:
		  begin
      		w_xfer_size   = 10'h20;
		  end
		3'b011:
		  begin
      		w_xfer_size   = 10'h40;
		  end
		3'b100:
		  begin
      		w_xfer_size   = 10'h80;
		  end
		3'b101:
		  begin
      		w_xfer_size   = 10'h100;
		  end
        default : w_xfer_size   = 10'h00;
	  endcase
   end
end

always@(posedge CLK, negedge RESETn)
begin	
  if( RESETn == 1'b0 )
    begin	
      r_xfer_size   = 10'h00;
	end
  else
	begin
	  case (RS_CMD)
		3'b000:
		  begin
      		r_xfer_size   = 10'h00; 
		  end
		3'b001:
		  begin
      		r_xfer_size   = 10'h10;
		  end
		3'b010:
		  begin
      		r_xfer_size   = 10'h20;
		  end
		3'b011:
		  begin
      		r_xfer_size   = 10'h40;
		  end
		3'b100:
		  begin
      		r_xfer_size   = 10'h80;
		  end
		3'b101:
		  begin
      		r_xfer_size   = 10'h100;
		  end
        default : r_xfer_size   = 10'h00;
	  endcase
   end
end
endmodule

