@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 
@N: MF625 |Insert Identify debug core
@N: MF625 |Insert Identify debug core
@N: BN397 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\synthesis\synthesis_1\instr_sources\syn_dics.v":4860:19:4860:51|Connected syn_hyper_connect ident_coreinst.ident_hyperc_write_start_IICE_209, tag AXI_IF_0.write_start
@N: BN397 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\synthesis\synthesis_1\instr_sources\syn_dics.v":4852:19:4852:47|Connected syn_hyper_connect ident_coreinst.ident_hyperc_w_start_IICE_208, tag AXI_IF_0.w_start
@N: BN397 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\synthesis\synthesis_1\instr_sources\syn_dics.v":4844:19:4844:50|Connected syn_hyper_connect ident_coreinst.ident_hyperc_read_start_IICE_207, tag AXI_IF_0.read_start
@N: BN397 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\synthesis\synthesis_1\instr_sources\syn_dics.v":4836:19:4836:50|Connected syn_hyper_connect ident_coreinst.ident_hyperc_read_read1_IICE_206, tag AXI_IF_0.read_read1
@N: BN397 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\synthesis\synthesis_1\instr_sources\syn_dics.v":4828:19:4828:50|Connected syn_hyper_connect ident_coreinst.ident_hyperc_read_read0_IICE_205, tag AXI_IF_0.read_read0
@N: BN397 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\synthesis\synthesis_1\instr_sources\syn_dics.v":4820:19:4820:49|Connected syn_hyper_connect ident_coreinst.ident_hyperc_read_idle_IICE_204, tag AXI_IF_0.read_idle
@N: BN397 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\synthesis\synthesis_1\instr_sources\syn_dics.v":4812:19:4812:50|Connected syn_hyper_connect ident_coreinst.ident_hyperc_read1_idle_IICE_203, tag AXI_IF_0.read1_idle
@N: BN397 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\synthesis\synthesis_1\instr_sources\syn_dics.v":4804:19:4804:47|Connected syn_hyper_connect ident_coreinst.ident_hyperc_r_start_IICE_202, tag AXI_IF_0.r_start
@N: BN397 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\synthesis\synthesis_1\instr_sources\syn_dics.v":4796:19:4796:50|Connected syn_hyper_connect ident_coreinst.ident_hyperc_WVALID_ext_IICE_201, tag AXI_IF_0.WVALID_ext
@N: BN397 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\synthesis\synthesis_1\instr_sources\syn_dics.v":4788:19:4788:46|Connected syn_hyper_connect ident_coreinst.ident_hyperc_WREADY_IICE_200, tag AXI_IF_0.WREADY
@N: BN397 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\synthesis\synthesis_1\instr_sources\syn_dics.v":4780:19:4780:45|Connected syn_hyper_connect ident_coreinst.ident_hyperc_WLAST_IICE_199, tag AXI_IF_0.WLAST
@N: BN397 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\synthesis\synthesis_1\instr_sources\syn_dics.v":4772:19:4772:45|Connected syn_hyper_connect ident_coreinst.ident_hyperc_WDATA_IICE_135, tag AXI_IF_0.WDATA
@N: BN397 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\synthesis\synthesis_1\instr_sources\syn_dics.v":4764:19:4764:46|Connected syn_hyper_connect ident_coreinst.ident_hyperc_RVALID_IICE_134, tag AXI_IF_0.RVALID
@N: BN397 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\synthesis\synthesis_1\instr_sources\syn_dics.v":4756:19:4756:46|Connected syn_hyper_connect ident_coreinst.ident_hyperc_RREADY_IICE_133, tag AXI_IF_0.RREADY
@N: BN397 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\synthesis\synthesis_1\instr_sources\syn_dics.v":4748:19:4748:45|Connected syn_hyper_connect ident_coreinst.ident_hyperc_RLAST_IICE_132, tag AXI_IF_0.RLAST
@N: BN397 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\synthesis\synthesis_1\instr_sources\syn_dics.v":4740:19:4740:44|Connected syn_hyper_connect ident_coreinst.ident_hyperc_RDATA_IICE_68, tag AXI_IF_0.RDATA
@N: BN397 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\synthesis\synthesis_1\instr_sources\syn_dics.v":4732:19:4732:50|Connected syn_hyper_connect ident_coreinst.ident_hyperc_AWVALID_ext_IICE_67, tag AXI_IF_0.AWVALID_ext
@N: BN397 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\synthesis\synthesis_1\instr_sources\syn_dics.v":4724:19:4724:46|Connected syn_hyper_connect ident_coreinst.ident_hyperc_AWREADY_IICE_66, tag AXI_IF_0.AWREADY
@N: BN397 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\synthesis\synthesis_1\instr_sources\syn_dics.v":4716:19:4716:45|Connected syn_hyper_connect ident_coreinst.ident_hyperc_AWADDR_IICE_34, tag AXI_IF_0.AWADDR
@N: BN397 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\synthesis\synthesis_1\instr_sources\syn_dics.v":4708:19:4708:50|Connected syn_hyper_connect ident_coreinst.ident_hyperc_ARVALID_ext_IICE_33, tag AXI_IF_0.ARVALID_ext
@N: BN397 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\synthesis\synthesis_1\instr_sources\syn_dics.v":4700:19:4700:46|Connected syn_hyper_connect ident_coreinst.ident_hyperc_ARREADY_IICE_32, tag AXI_IF_0.ARREADY
@N: BN397 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\synthesis\synthesis_1\instr_sources\syn_dics.v":4692:19:4692:44|Connected syn_hyper_connect ident_coreinst.ident_hyperc_ARADDR_IICE_0, tag AXI_IF_0.ARADDR
@N: BN397 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\synthesis\synthesis_1\instr_sources\syn_dics.v":4684:19:4684:34|Connected syn_hyper_connect ident_coreinst.ident_hyperc_CLK, tag AXI_IF_0.CLK
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":461:4:461:9|Removing sequential instance FDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":461:4:461:9|Removing sequential instance SDIF0_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":461:4:461:9|Removing sequential instance SDIF1_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":461:4:461:9|Removing sequential instance SDIF2_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":461:4:461:9|Removing sequential instance SDIF3_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance SDIF_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance SDIF_RELEASED_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\synthesis\synthesis_1\instr_sources\syn_dics.v":852:2:852:7|Removing sequential instance b13_xYTFKCkrt_FH9 of view:PrimLib.dff(prim) in hierarchy view:VhdlGenLib.b7_OCByLXC_Z1_x(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\hdl\ahb_if.v":71:0:71:5|Removing sequential instance DATAOUT[31:0] of view:PrimLib.dffre(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\hdl\ahb_if.v":71:0:71:5|Removing sequential instance HSEL of view:PrimLib.dffre(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because there are no references to its outputs 
@N: BN115 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":2703:2:2703:14|Removing instance masterstage_1 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because there are no references to its outputs 
@N: BN115 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":2767:2:2767:14|Removing instance masterstage_2 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because there are no references to its outputs 
@N: BN115 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":2831:2:2831:14|Removing instance masterstage_3 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because there are no references to its outputs 
@N: BN115 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":2890:1:2890:12|Removing instance slavestage_0 of view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Removing sequential instance SDIF0_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Removing sequential instance sdif0_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Removing sequential instance sdif1_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Removing sequential instance sdif2_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Removing sequential instance sdif3_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":79:4:79:9|Removing sequential instance masterDataInProg[3:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":797:4:797:9|Removing sequential instance sdif0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":811:4:811:9|Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":825:4:825:9|Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":839:4:839:9|Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":797:4:797:9|Removing sequential instance sdif0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":811:4:811:9|Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":825:4:825:9|Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":839:4:839:9|Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN115 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":87:56:87:68|Removing instance slave_arbiter of view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z5_0(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11.6_migration\libero_designs\m2s_ac422_150kit\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance arbRegSMCurrentState[15:0] of view:PrimLib.statemachine(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z5_0(verilog) because there are no references to its outputs 
@N: MT480 :"D:/Libero_11.6_migration/Libero_designs/M2S_AC422_150KIT/Board_Test/MDDR_TA/synthesis/synthesis_1/instr_sources/syn_dics.sdc":2:0:2:0|Assigning clock "ident_coreinst.comm_block_INST.tck" to command: define_clock {n:ident_coreinst.comm_block_INST.tck} -period {1000.0} -clockgroup {identify_jtag_group1} 
@N: MT480 :"D:/Libero_11.6_migration/Libero_designs/M2S_AC422_150KIT/Board_Test/MDDR_TA/synthesis/synthesis_1/instr_sources/syn_dics.sdc":3:0:3:0|Assigning clock "ident_coreinst.comm_block_INST.dr2_tck" to command: define_clock {n:ident_coreinst.comm_block_INST.dr2_tck} -period {1000.0} -clockgroup {identify_jtag_group1} 
@N: MT480 :"D:/Libero_11.6_migration/Libero_designs/M2S_AC422_150KIT/Board_Test/MDDR_TA/synthesis/synthesis_1/instr_sources/syn_dics.sdc":2:0:2:0|Assigning clock "ident_coreinst.comm_block_INST.tck" to command: define_clock {n:ident_coreinst.comm_block_INST.tck} -period {1000.0} -clockgroup {identify_jtag_group1} 
@N: MT480 :"D:/Libero_11.6_migration/Libero_designs/M2S_AC422_150KIT/Board_Test/MDDR_TA/synthesis/synthesis_1/instr_sources/syn_dics.sdc":3:0:3:0|Assigning clock "ident_coreinst.comm_block_INST.dr2_tck" to command: define_clock {n:ident_coreinst.comm_block_INST.dr2_tck} -period {1000.0} -clockgroup {identify_jtag_group1} 
@N: BN225 |Writing default property annotation file D:\Libero_11.6_migration\Libero_designs\M2S_AC422_150KIT\Board_Test\MDDR_TA\synthesis\synthesis_1\MDDR_TA_top.sap.
