Timing Violation Report Min Delay Analysis

SmartTime Version v11.6
Microsemi Corporation - Microsemi Libero Software Release v11.6 (Version 11.6.0.34)
Date: Wed Oct 07 20:39:41 2015


Design: MDDR_TA_top
Family: SmartFusion2
Die: M2S150T
Package: 1152 FC
Temperature Range: 0 - 85 C
Voltage Range: 1.14 - 1.26 V
Speed Grade: -1
Design State: Post-Layout
Data source: Production
Min Operating Conditions: BEST - 1.26 V - 0 C
Max Operating Conditions: WORST - 1.14 V - 85 C
Scenario for Timing Analysis: Primary


Path 1
  From:                        AHB_IF_0/HADDR_int[24]:CLK
  To:                          AHB_IF_0/HADDR_ret_48:D
  Delay (ns):                  0.285                                                                           
  Slack (ns):                  0.236                                                                           
  Arrival (ns):                3.604                                                                           
  Required (ns):               3.368                                                                           

Path 2
  From:                        AHB_IF_0/HADDR_int[10]:CLK
  To:                          AHB_IF_0/HADDR_ret_39:D
  Delay (ns):                  0.285                                                                           
  Slack (ns):                  0.238                                                                           
  Arrival (ns):                3.592                                                                           
  Required (ns):               3.354                                                                           

Path 3
  From:                        AHB_IF_0/HADDR_int[14]:CLK
  To:                          AHB_IF_0/HADDR_ret_24:D
  Delay (ns):                  0.285                                                                           
  Slack (ns):                  0.238                                                                           
  Arrival (ns):                3.596                                                                           
  Required (ns):               3.358                                                                           

Path 4
  From:                        AHB_IF_0/HADDR_int[26]:CLK
  To:                          AHB_IF_0/HADDR_ret_42:D
  Delay (ns):                  0.285                                                                           
  Slack (ns):                  0.239                                                                           
  Arrival (ns):                3.599                                                                           
  Required (ns):               3.360                                                                           

Path 5
  From:                        AHB_IF_0/HADDR_int[13]:CLK
  To:                          AHB_IF_0/HADDR_ret_69:D
  Delay (ns):                  0.281                                                                           
  Slack (ns):                  0.240                                                                           
  Arrival (ns):                3.599                                                                           
  Required (ns):               3.359                                                                           

Path 6
  From:                        AHB_IF_0/HADDR_int[16]:CLK
  To:                          AHB_IF_0/HADDR_ret_45:D
  Delay (ns):                  0.285                                                                           
  Slack (ns):                  0.245                                                                           
  Arrival (ns):                3.595                                                                           
  Required (ns):               3.350                                                                           

Path 7
  From:                        AHB_IF_0/HADDR_int[6]:CLK
  To:                          AHB_IF_0/HADDR_ret_57:D
  Delay (ns):                  0.293                                                                           
  Slack (ns):                  0.248                                                                           
  Arrival (ns):                3.601                                                                           
  Required (ns):               3.353                                                                           

Path 8
  From:                        AHB_IF_0/HADDR_int[2]:CLK
  To:                          AHB_IF_0/HADDR_ret_27:D
  Delay (ns):                  0.293                                                                           
  Slack (ns):                  0.248                                                                           
  Arrival (ns):                3.601                                                                           
  Required (ns):               3.353                                                                           

Path 9
  From:                        AHB_IF_0/HWDATA_int[10]:CLK
  To:                          AHB_IF_0/HWDATA[10]:D
  Delay (ns):                  0.290                                                                           
  Slack (ns):                  0.250                                                                           
  Arrival (ns):                3.607                                                                           
  Required (ns):               3.357                                                                           

Path 10
  From:                        MDDR_TA_0/CORERESETP_0/CONFIG2_DONE_q1:CLK
  To:                          MDDR_TA_0/CORERESETP_0/CONFIG2_DONE_clk_base:D
  Delay (ns):                  0.298                                                                           
  Slack (ns):                  0.251                                                                           
  Arrival (ns):                3.609                                                                           
  Required (ns):               3.358                                                                           

Path 11
  From:                        AHB_IF_0/HADDR_int[29]:CLK
  To:                          AHB_IF_0/HADDR_ret_0:D
  Delay (ns):                  0.283                                                                           
  Slack (ns):                  0.251                                                                           
  Arrival (ns):                3.610                                                                           
  Required (ns):               3.359                                                                           

Path 12
  From:                        AXI_IF_0/AHB_DATA_1[12]:CLK
  To:                          AHB_IF_0/HWDATA_int[12]:D
  Delay (ns):                  0.300                                                                           
  Slack (ns):                  0.252                                                                           
  Arrival (ns):                3.611                                                                           
  Required (ns):               3.359                                                                           

Path 13
  From:                        MDDR_TA_0/CORERESETP_0/release_sdif0_core_q1:CLK
  To:                          MDDR_TA_0/CORERESETP_0/release_sdif0_core_clk_base:D
  Delay (ns):                  0.293                                                                           
  Slack (ns):                  0.255                                                                           
  Arrival (ns):                3.594                                                                           
  Required (ns):               3.339                                                                           

Path 14
  From:                        AXI_IF_0/AHB_DATA_1[10]:CLK
  To:                          AHB_IF_0/HWDATA_int[10]:D
  Delay (ns):                  0.295                                                                           
  Slack (ns):                  0.255                                                                           
  Arrival (ns):                3.612                                                                           
  Required (ns):               3.357                                                                           

Path 15
  From:                        AHB_IF_0/HADDR_int[3]:CLK
  To:                          AHB_IF_0/HADDR_ret_51:D
  Delay (ns):                  0.290                                                                           
  Slack (ns):                  0.256                                                                           
  Arrival (ns):                3.610                                                                           
  Required (ns):               3.354                                                                           

Path 16
  From:                        AHB_IF_0/HADDR_int[18]:CLK
  To:                          AHB_IF_0/HADDR_ret_12:D
  Delay (ns):                  0.290                                                                           
  Slack (ns):                  0.256                                                                           
  Arrival (ns):                3.607                                                                           
  Required (ns):               3.351                                                                           

Path 17
  From:                        AHB_IF_0/HADDR_int[4]:CLK
  To:                          AHB_IF_0/HADDR_ret_75:D
  Delay (ns):                  0.290                                                                           
  Slack (ns):                  0.257                                                                           
  Arrival (ns):                3.604                                                                           
  Required (ns):               3.347                                                                           

Path 18
  From:                        AHB_IF_0/HWDATA_int[3]:CLK
  To:                          AHB_IF_0/HWDATA[3]:D
  Delay (ns):                  0.298                                                                           
  Slack (ns):                  0.258                                                                           
  Arrival (ns):                3.609                                                                           
  Required (ns):               3.351                                                                           

Path 19
  From:                        AHB_IF_0/HADDR_int[23]:CLK
  To:                          AHB_IF_0/HADDR_ret_33:D
  Delay (ns):                  0.299                                                                           
  Slack (ns):                  0.258                                                                           
  Arrival (ns):                3.618                                                                           
  Required (ns):               3.360                                                                           

Path 20
  From:                        MDDR_TA_0/CORERESETP_0/CONFIG1_DONE_q1:CLK
  To:                          MDDR_TA_0/CORERESETP_0/CONFIG1_DONE_clk_base:D
  Delay (ns):                  0.297                                                                           
  Slack (ns):                  0.258                                                                           
  Arrival (ns):                3.608                                                                           
  Required (ns):               3.350                                                                           

Path 21
  From:                        MDDR_TA_0/CORERESETP_0/count_ddr_enable_q1:CLK
  To:                          MDDR_TA_0/CORERESETP_0/count_ddr_enable_rcosc:D
  Delay (ns):                  0.297                                                                           
  Slack (ns):                  0.259                                                                           
  Arrival (ns):                5.457                                                                           
  Required (ns):               5.198                                                                           

Path 22
  From:                        AHB_IF_0/HWDATA_int[6]:CLK
  To:                          AHB_IF_0/HWDATA[6]:D
  Delay (ns):                  0.297                                                                           
  Slack (ns):                  0.259                                                                           
  Arrival (ns):                3.609                                                                           
  Required (ns):               3.350                                                                           

Path 23
  From:                        AHB_IF_0/HADDR_int[19]:CLK
  To:                          AHB_IF_0/HADDR_ret_3:D
  Delay (ns):                  0.301                                                                           
  Slack (ns):                  0.260                                                                           
  Arrival (ns):                3.620                                                                           
  Required (ns):               3.360                                                                           

Path 24
  From:                        AHB_IF_0/HADDR_int[27]:CLK
  To:                          AHB_IF_0/HADDR_ret_60:D
  Delay (ns):                  0.300                                                                           
  Slack (ns):                  0.261                                                                           
  Arrival (ns):                3.612                                                                           
  Required (ns):               3.351                                                                           

Path 25
  From:                        AHB_IF_0/HADDR_int[17]:CLK
  To:                          AHB_IF_0/HADDR_ret_36:D
  Delay (ns):                  0.301                                                                           
  Slack (ns):                  0.261                                                                           
  Arrival (ns):                3.621                                                                           
  Required (ns):               3.360                                                                           

Path 26
  From:                        AXI_IF_0/AHB_DATA_1[1]:CLK
  To:                          AHB_IF_0/HWDATA_int[1]:D
  Delay (ns):                  0.301                                                                           
  Slack (ns):                  0.261                                                                           
  Arrival (ns):                3.620                                                                           
  Required (ns):               3.359                                                                           

Path 27
  From:                        AHB_IF_0/HWDATA_int[11]:CLK
  To:                          AHB_IF_0/HWDATA[11]:D
  Delay (ns):                  0.301                                                                           
  Slack (ns):                  0.262                                                                           
  Arrival (ns):                3.606                                                                           
  Required (ns):               3.344                                                                           

Path 28
  From:                        AHB_IF_0/HADDR_int[8]:CLK
  To:                          AHB_IF_0/HADDR_ret_30:D
  Delay (ns):                  0.299                                                                           
  Slack (ns):                  0.265                                                                           
  Arrival (ns):                3.612                                                                           
  Required (ns):               3.347                                                                           

Path 29
  From:                        AHB_IF_0/HADDR_int[7]:CLK
  To:                          AHB_IF_0/HADDR_ret_66:D
  Delay (ns):                  0.299                                                                           
  Slack (ns):                  0.265                                                                           
  Arrival (ns):                3.612                                                                           
  Required (ns):               3.347                                                                           

Path 30
  From:                        AHB_IF_0/HADDR_int[22]:CLK
  To:                          AHB_IF_0/HADDR_ret_21:D
  Delay (ns):                  0.299                                                                           
  Slack (ns):                  0.267                                                                           
  Arrival (ns):                3.618                                                                           
  Required (ns):               3.351                                                                           

Path 31
  From:                        AHB_IF_0/HADDR_int[12]:CLK
  To:                          AHB_IF_0/HADDR_ret_18:D
  Delay (ns):                  0.299                                                                           
  Slack (ns):                  0.267                                                                           
  Arrival (ns):                3.618                                                                           
  Required (ns):               3.351                                                                           

Path 32
  From:                        AXI_IF_0/rt_state[0]:CLK
  To:                          AXI_IF_0/rt_state[0]:D
  Delay (ns):                  0.307                                                                           
  Slack (ns):                  0.268                                                                           
  Arrival (ns):                3.615                                                                           
  Required (ns):               3.347                                                                           

Path 33
  From:                        AXI_IF_0/AHB_DATA_1[0]:CLK
  To:                          AHB_IF_0/HWDATA_int[0]:D
  Delay (ns):                  0.299                                                                           
  Slack (ns):                  0.268                                                                           
  Arrival (ns):                3.618                                                                           
  Required (ns):               3.350                                                                           

Path 34
  From:                        MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel:CLK
  To:                          MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel:D
  Delay (ns):                  0.308                                                                           
  Slack (ns):                  0.269                                                                           
  Arrival (ns):                3.613                                                                           
  Required (ns):               3.344                                                                           

Path 35
  From:                        MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel_rep1:CLK
  To:                          MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/masterRegAddrSel_rep1:D
  Delay (ns):                  0.309                                                                           
  Slack (ns):                  0.270                                                                           
  Arrival (ns):                3.614                                                                           
  Required (ns):               3.344                                                                           

Path 36
  From:                        MDDR_TA_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[1]:CLK
  To:                          MDDR_TA_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[1]:D
  Delay (ns):                  0.309                                                                           
  Slack (ns):                  0.270                                                                           
  Arrival (ns):                3.609                                                                           
  Required (ns):               3.339                                                                           

Path 37
  From:                        MDDR_TA_0/CORERESETP_0/ddr_settled_q1:CLK
  To:                          MDDR_TA_0/CORERESETP_0/ddr_settled_clk_base:D
  Delay (ns):                  0.301                                                                           
  Slack (ns):                  0.270                                                                           
  Arrival (ns):                3.620                                                                           
  Required (ns):               3.350                                                                           

Path 38
  From:                        MDDR_TA_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[0]:CLK
  To:                          MDDR_TA_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[0]:D
  Delay (ns):                  0.314                                                                           
  Slack (ns):                  0.275                                                                           
  Arrival (ns):                3.614                                                                           
  Required (ns):               3.339                                                                           

Path 39
  From:                        MDDR_TA_0/CORERESETP_0/sm0_state[5]:CLK
  To:                          MDDR_TA_0/CORERESETP_0/sm0_state[5]:D
  Delay (ns):                  0.315                                                                           
  Slack (ns):                  0.275                                                                           
  Arrival (ns):                3.634                                                                           
  Required (ns):               3.359                                                                           

Path 40
  From:                        AXI_IF_0/axi_fsm_read1_state[0]:CLK
  To:                          AXI_IF_0/axi_fsm_read1_state[0]:D
  Delay (ns):                  0.313                                                                           
  Slack (ns):                  0.275                                                                           
  Arrival (ns):                3.610                                                                           
  Required (ns):               3.335                                                                           

Path 41
  From:                        AXI_IF_0/w_loop[1]:CLK
  To:                          AXI_IF_0/w_loop[1]:D
  Delay (ns):                  0.315                                                                           
  Slack (ns):                  0.277                                                                           
  Arrival (ns):                3.613                                                                           
  Required (ns):               3.336                                                                           

Path 42
  From:                        AXI_IF_0/axi_fsm_current_state[0]:CLK
  To:                          AXI_IF_0/axi_fsm_current_state[0]:D
  Delay (ns):                  0.317                                                                           
  Slack (ns):                  0.280                                                                           
  Arrival (ns):                3.614                                                                           
  Required (ns):               3.334                                                                           

Path 43
  From:                        AXI_IF_0/r_loop[3]:CLK
  To:                          AXI_IF_0/r_loop[3]:D
  Delay (ns):                  0.319                                                                           
  Slack (ns):                  0.281                                                                           
  Arrival (ns):                3.619                                                                           
  Required (ns):               3.338                                                                           

Path 44
  From:                        AXI_IF_0/w_loop[0]:CLK
  To:                          AXI_IF_0/w_loop[0]:D
  Delay (ns):                  0.319                                                                           
  Slack (ns):                  0.282                                                                           
  Arrival (ns):                3.611                                                                           
  Required (ns):               3.329                                                                           

Path 45
  From:                        AXI_IF_0/rt_state[1]:CLK
  To:                          AXI_IF_0/rt_state[1]:D
  Delay (ns):                  0.322                                                                           
  Slack (ns):                  0.282                                                                           
  Arrival (ns):                3.637                                                                           
  Required (ns):               3.355                                                                           

Path 46
  From:                        AXI_IF_0/burst_cnt[0]:CLK
  To:                          AXI_IF_0/burst_cnt[0]:D
  Delay (ns):                  0.319                                                                           
  Slack (ns):                  0.282                                                                           
  Arrival (ns):                3.610                                                                           
  Required (ns):               3.328                                                                           

Path 47
  From:                        AXI_IF_0/r_loop[1]:CLK
  To:                          AXI_IF_0/r_loop[1]:D
  Delay (ns):                  0.319                                                                           
  Slack (ns):                  0.282                                                                           
  Arrival (ns):                3.613                                                                           
  Required (ns):               3.331                                                                           

Path 48
  From:                        AXI_IF_0/w_loop[3]:CLK
  To:                          AXI_IF_0/w_loop[3]:D
  Delay (ns):                  0.321                                                                           
  Slack (ns):                  0.284                                                                           
  Arrival (ns):                3.613                                                                           
  Required (ns):               3.329                                                                           

Path 49
  From:                        AXI_IF_0/AWADDR_int[31]:CLK
  To:                          AXI_IF_0/AWADDR_1[31]:D
  Delay (ns):                  0.321                                                                           
  Slack (ns):                  0.284                                                                           
  Arrival (ns):                3.618                                                                           
  Required (ns):               3.334                                                                           

Path 50
  From:                        AXI_IF_0/w_loop_state[0]:CLK
  To:                          AXI_IF_0/w_loop_state[0]:D
  Delay (ns):                  0.323                                                                           
  Slack (ns):                  0.285                                                                           
  Arrival (ns):                3.625                                                                           
  Required (ns):               3.340                                                                           

Path 51
  From:                        AXI_IF_0/axi_fsm_read_state[0]:CLK
  To:                          AXI_IF_0/axi_fsm_read_state[0]:D
  Delay (ns):                  0.327                                                                           
  Slack (ns):                  0.289                                                                           
  Arrival (ns):                3.631                                                                           
  Required (ns):               3.342                                                                           

Path 52
  From:                        AXI_IF_0/wt_state[0]:CLK
  To:                          AXI_IF_0/wt_state[0]:D
  Delay (ns):                  0.328                                                                           
  Slack (ns):                  0.291                                                                           
  Arrival (ns):                3.625                                                                           
  Required (ns):               3.334                                                                           

Path 53
  From:                        AXI_IF_0/burst_cnt[3]:CLK
  To:                          AXI_IF_0/burst_cnt[3]:D
  Delay (ns):                  0.334                                                                           
  Slack (ns):                  0.297                                                                           
  Arrival (ns):                3.631                                                                           
  Required (ns):               3.334                                                                           

Path 54
  From:                        MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/SDATASELInt_ret_1:CLK
  To:                          MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState:D
  Delay (ns):                  0.350                                                                           
  Slack (ns):                  0.306                                                                           
  Arrival (ns):                3.649                                                                           
  Required (ns):               3.343                                                                           

Path 55
  From:                        AXI_IF_0/rdata_cnt[3]:CLK
  To:                          AXI_IF_0/Rdata_mem_Rdata_mem_0_1/INST_RAM1K18_IP:B_ADDR[8]
  Delay (ns):                  0.485                                                                           
  Slack (ns):                  0.314                                                                           
  Arrival (ns):                3.798                                                                           
  Required (ns):               3.484                                                                           

Path 56
  From:                        AHB_IF_0/ahb_fsm_current_state[2]:CLK
  To:                          AHB_IF_0/ahb_fsm_current_state[2]:D
  Delay (ns):                  0.354                                                                           
  Slack (ns):                  0.315                                                                           
  Arrival (ns):                3.658                                                                           
  Required (ns):               3.343                                                                           

Path 57
  From:                        AXI_IF_0/ARADDR[7]:CLK
  To:                          AXI_IF_0/ARADDR[7]:D
  Delay (ns):                  0.357                                                                           
  Slack (ns):                  0.318                                                                           
  Arrival (ns):                3.670                                                                           
  Required (ns):               3.352                                                                           

Path 58
  From:                        AHB_IF_0/HADDR_int[5]:CLK
  To:                          AHB_IF_0/HADDR_ret_54:D
  Delay (ns):                  0.374                                                                           
  Slack (ns):                  0.324                                                                           
  Arrival (ns):                3.671                                                                           
  Required (ns):               3.347                                                                           

Path 59
  From:                        AXI_IF_0/AHB_DATA_1[8]:CLK
  To:                          AHB_IF_0/HWDATA_int[8]:D
  Delay (ns):                  0.369                                                                           
  Slack (ns):                  0.324                                                                           
  Arrival (ns):                3.679                                                                           
  Required (ns):               3.355                                                                           

Path 60
  From:                        AXI_IF_0/r_clk_cnt[0]:CLK
  To:                          AXI_IF_0/r_clk_cnt[0]:D
  Delay (ns):                  0.366                                                                           
  Slack (ns):                  0.328                                                                           
  Arrival (ns):                3.671                                                                           
  Required (ns):               3.343                                                                           

Path 61
  From:                        MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState:CLK
  To:                          MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/defSlaveSMCurrentState:D
  Delay (ns):                  0.368                                                                           
  Slack (ns):                  0.329                                                                           
  Arrival (ns):                3.672                                                                           
  Required (ns):               3.343                                                                           

Path 62
  From:                        MDDR_TA_0/CORERESETP_0/RESET_N_M2F_q1:CLK
  To:                          MDDR_TA_0/CORERESETP_0/RESET_N_M2F_clk_base:D
  Delay (ns):                  0.367                                                                           
  Slack (ns):                  0.330                                                                           
  Arrival (ns):                3.660                                                                           
  Required (ns):               3.330                                                                           

Path 63
  From:                        MDDR_TA_0/CORERESETP_0/sdif3_spll_lock_q1:CLK
  To:                          MDDR_TA_0/CORERESETP_0/sdif3_spll_lock_q2:D
  Delay (ns):                  0.361                                                                           
  Slack (ns):                  0.330                                                                           
  Arrival (ns):                3.680                                                                           
  Required (ns):               3.350                                                                           

Path 64
  From:                        AXI_IF_0/AHB_DATA_1[13]:CLK
  To:                          AHB_IF_0/HWDATA_int[13]:D
  Delay (ns):                  0.371                                                                           
  Slack (ns):                  0.331                                                                           
  Arrival (ns):                3.688                                                                           
  Required (ns):               3.357                                                                           

Path 65
  From:                        AHB_IF_0/HWDATA_int[13]:CLK
  To:                          AHB_IF_0/HWDATA[13]:D
  Delay (ns):                  0.366                                                                           
  Slack (ns):                  0.333                                                                           
  Arrival (ns):                3.683                                                                           
  Required (ns):               3.350                                                                           

Path 66
  From:                        AHB_IF_0/HWDATA_int[2]:CLK
  To:                          AHB_IF_0/HWDATA[2]:D
  Delay (ns):                  0.373                                                                           
  Slack (ns):                  0.334                                                                           
  Arrival (ns):                3.684                                                                           
  Required (ns):               3.350                                                                           

Path 67
  From:                        AHB_IF_0/HADDR_int[25]:CLK
  To:                          AHB_IF_0/HADDR_ret_63:D
  Delay (ns):                  0.383                                                                           
  Slack (ns):                  0.335                                                                           
  Arrival (ns):                3.695                                                                           
  Required (ns):               3.360                                                                           

Path 68
  From:                        AHB_IF_0/HADDR_int[30]:CLK
  To:                          AHB_IF_0/HADDR_ret_81:D
  Delay (ns):                  0.368                                                                           
  Slack (ns):                  0.336                                                                           
  Arrival (ns):                3.687                                                                           
  Required (ns):               3.351                                                                           

Path 69
  From:                        AHB_IF_0/ahb_fsm_current_state[0]:CLK
  To:                          AHB_IF_0/ahb_fsm_current_state[1]:D
  Delay (ns):                  0.380                                                                           
  Slack (ns):                  0.336                                                                           
  Arrival (ns):                3.679                                                                           
  Required (ns):               3.343                                                                           

Path 70
  From:                        AHB_IF_0/HWDATA_int[9]:CLK
  To:                          AHB_IF_0/HWDATA[9]:D
  Delay (ns):                  0.383                                                                           
  Slack (ns):                  0.336                                                                           
  Arrival (ns):                3.688                                                                           
  Required (ns):               3.352                                                                           

Path 71
  From:                        MDDR_TA_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_q1:CLK
  To:                          MDDR_TA_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_clk_base:D
  Delay (ns):                  0.369                                                                           
  Slack (ns):                  0.337                                                                           
  Arrival (ns):                3.676                                                                           
  Required (ns):               3.339                                                                           

Path 72
  From:                        MDDR_TA_0/CORERESETP_0/RESET_N_M2F_clk_base:CLK
  To:                          MDDR_TA_0/CORERESETP_0/mss_ready_state:EN
  Delay (ns):                  0.384                                                                           
  Slack (ns):                  0.337                                                                           
  Arrival (ns):                3.677                                                                           
  Required (ns):               3.340                                                                           

Path 73
  From:                        AXI_IF_0/AHB_DATA_1[4]:CLK
  To:                          AHB_IF_0/HWDATA_int[4]:D
  Delay (ns):                  0.369                                                                           
  Slack (ns):                  0.338                                                                           
  Arrival (ns):                3.688                                                                           
  Required (ns):               3.350                                                                           

Path 74
  From:                        AXI_IF_0/WDATA_int[0]:CLK
  To:                          AXI_IF_0/WDATA_int[0]:D
  Delay (ns):                  0.377                                                                           
  Slack (ns):                  0.338                                                                           
  Arrival (ns):                3.684                                                                           
  Required (ns):               3.346                                                                           

Path 75
  From:                        AHB_IF_0/ahb_fsm_current_state[2]:CLK
  To:                          AHB_IF_0/ahb_fsm_current_state[3]:D
  Delay (ns):                  0.372                                                                           
  Slack (ns):                  0.339                                                                           
  Arrival (ns):                3.676                                                                           
  Required (ns):               3.337                                                                           

Path 76
  From:                        AHB_IF_0/HADDR_int[15]:CLK
  To:                          AHB_IF_0/HADDR_ret_72:D
  Delay (ns):                  0.378                                                                           
  Slack (ns):                  0.339                                                                           
  Arrival (ns):                3.690                                                                           
  Required (ns):               3.351                                                                           

Path 77
  From:                        AHB_IF_0/HWRITE:CLK
  To:                          MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHWRITE:D
  Delay (ns):                  0.390                                                                           
  Slack (ns):                  0.347                                                                           
  Arrival (ns):                3.687                                                                           
  Required (ns):               3.340                                                                           

Path 78
  From:                        AXI_IF_0/AWADDR_int[25]:CLK
  To:                          AXI_IF_0/AWADDR_1[25]:D
  Delay (ns):                  0.389                                                                           
  Slack (ns):                  0.349                                                                           
  Arrival (ns):                3.709                                                                           
  Required (ns):               3.360                                                                           

Path 79
  From:                        AXI_IF_0/AWADDR_int[29]:CLK
  To:                          AXI_IF_0/AWADDR_1[29]:D
  Delay (ns):                  0.397                                                                           
  Slack (ns):                  0.349                                                                           
  Arrival (ns):                3.709                                                                           
  Required (ns):               3.360                                                                           

Path 80
  From:                        AXI_IF_0/burst_cnt[2]:CLK
  To:                          AXI_IF_0/burst_cnt[2]:D
  Delay (ns):                  0.387                                                                           
  Slack (ns):                  0.350                                                                           
  Arrival (ns):                3.684                                                                           
  Required (ns):               3.334                                                                           

Path 81
  From:                        AXI_IF_0/AWADDR_int[30]:CLK
  To:                          AXI_IF_0/AWADDR_1[30]:D
  Delay (ns):                  0.389                                                                           
  Slack (ns):                  0.350                                                                           
  Arrival (ns):                3.709                                                                           
  Required (ns):               3.359                                                                           

Path 82
  From:                        AXI_IF_0/burst_cnt[2]:CLK
  To:                          AXI_IF_0/burst_cnt[3]:D
  Delay (ns):                  0.387                                                                           
  Slack (ns):                  0.350                                                                           
  Arrival (ns):                3.684                                                                           
  Required (ns):               3.334                                                                           

Path 83
  From:                        AXI_IF_0/AWADDR_int[10]:CLK
  To:                          AXI_IF_0/AWADDR_1[10]:D
  Delay (ns):                  0.391                                                                           
  Slack (ns):                  0.351                                                                           
  Arrival (ns):                3.710                                                                           
  Required (ns):               3.359                                                                           

Path 84
  From:                        AXI_IF_0/AWADDR_int[9]:CLK
  To:                          AXI_IF_0/AWADDR_1[9]:D
  Delay (ns):                  0.391                                                                           
  Slack (ns):                  0.352                                                                           
  Arrival (ns):                3.703                                                                           
  Required (ns):               3.351                                                                           

Path 85
  From:                        AXI_IF_0/AWADDR_int[7]:CLK
  To:                          AXI_IF_0/AWADDR_int[7]:D
  Delay (ns):                  0.393                                                                           
  Slack (ns):                  0.353                                                                           
  Arrival (ns):                3.712                                                                           
  Required (ns):               3.359                                                                           

Path 86
  From:                        AXI_IF_0/AWADDR_int[19]:CLK
  To:                          AXI_IF_0/AWADDR_1[19]:D
  Delay (ns):                  0.393                                                                           
  Slack (ns):                  0.354                                                                           
  Arrival (ns):                3.705                                                                           
  Required (ns):               3.351                                                                           

Path 87
  From:                        MDDR_TA_0/CORERESETP_0/sm0_state[1]:CLK
  To:                          MDDR_TA_0/CORERESETP_0/FDDR_CORE_RESET_N_int:EN
  Delay (ns):                  0.394                                                                           
  Slack (ns):                  0.355                                                                           
  Arrival (ns):                3.701                                                                           
  Required (ns):               3.346                                                                           

Path 88
  From:                        AXI_IF_0/rdata_cnt[0]:CLK
  To:                          AXI_IF_0/rdata_cnt[0]:D
  Delay (ns):                  0.395                                                                           
  Slack (ns):                  0.356                                                                           
  Arrival (ns):                3.708                                                                           
  Required (ns):               3.352                                                                           

Path 89
  From:                        MDDR_TA_0/CORERESETP_0/count_ddr_enable_rcosc:CLK
  To:                          MDDR_TA_0/CORERESETP_0/count_ddr[12]:EN
  Delay (ns):                  0.395                                                                           
  Slack (ns):                  0.357                                                                           
  Arrival (ns):                5.555                                                                           
  Required (ns):               5.198                                                                           

Path 90
  From:                        MDDR_TA_0/CORERESETP_0/sm0_state[2]:CLK
  To:                          MDDR_TA_0/CORERESETP_0/sm0_state[3]:D
  Delay (ns):                  0.389                                                                           
  Slack (ns):                  0.358                                                                           
  Arrival (ns):                3.708                                                                           
  Required (ns):               3.350                                                                           

Path 91
  From:                        MDDR_TA_0/CORERESETP_0/count_ddr_enable_rcosc:CLK
  To:                          MDDR_TA_0/CORERESETP_0/count_ddr[13]:EN
  Delay (ns):                  0.395                                                                           
  Slack (ns):                  0.358                                                                           
  Arrival (ns):                5.555                                                                           
  Required (ns):               5.197                                                                           

Path 92
  From:                        MDDR_TA_0/CORERESETP_0/count_ddr_enable_rcosc:CLK
  To:                          MDDR_TA_0/CORERESETP_0/count_ddr[0]:EN
  Delay (ns):                  0.395                                                                           
  Slack (ns):                  0.358                                                                           
  Arrival (ns):                5.555                                                                           
  Required (ns):               5.197                                                                           

Path 93
  From:                        AHB_IF_0/HWDATA_int[7]:CLK
  To:                          AHB_IF_0/HWDATA[7]:D
  Delay (ns):                  0.368                                                                           
  Slack (ns):                  0.359                                                                           
  Arrival (ns):                3.695                                                                           
  Required (ns):               3.336                                                                           

Path 94
  From:                        AXI_IF_0/AWADDR_int[12]:CLK
  To:                          AXI_IF_0/AWADDR_1[12]:D
  Delay (ns):                  0.398                                                                           
  Slack (ns):                  0.359                                                                           
  Arrival (ns):                3.710                                                                           
  Required (ns):               3.351                                                                           

Path 95
  From:                        AXI_IF_0/AWADDR_int[26]:CLK
  To:                          AXI_IF_0/AWADDR_1[26]:D
  Delay (ns):                  0.391                                                                           
  Slack (ns):                  0.360                                                                           
  Arrival (ns):                3.711                                                                           
  Required (ns):               3.351                                                                           

Path 96
  From:                        AXI_IF_0/AWADDR_int[8]:CLK
  To:                          AXI_IF_0/AWADDR_1[8]:D
  Delay (ns):                  0.400                                                                           
  Slack (ns):                  0.360                                                                           
  Arrival (ns):                3.719                                                                           
  Required (ns):               3.359                                                                           

Path 97
  From:                        MDDR_TA_0/CORERESETP_0/count_ddr[0]:CLK
  To:                          MDDR_TA_0/CORERESETP_0/count_ddr[0]:D
  Delay (ns):                  0.399                                                                           
  Slack (ns):                  0.361                                                                           
  Arrival (ns):                5.558                                                                           
  Required (ns):               5.197                                                                           

Path 98
  From:                        AXI_IF_0/w_clk_cnt[0]:CLK
  To:                          AXI_IF_0/w_clk_cnt[0]:D
  Delay (ns):                  0.402                                                                           
  Slack (ns):                  0.362                                                                           
  Arrival (ns):                3.721                                                                           
  Required (ns):               3.359                                                                           

Path 99
  From:                        MDDR_TA_0/CORERESETP_0/count_ddr[1]:CLK
  To:                          MDDR_TA_0/CORERESETP_0/count_ddr[1]:D
  Delay (ns):                  0.402                                                                           
  Slack (ns):                  0.362                                                                           
  Arrival (ns):                5.578                                                                           
  Required (ns):               5.216                                                                           

Path 100
  From:                        MDDR_TA_0/CORERESETP_0/count_ddr[7]:CLK
  To:                          MDDR_TA_0/CORERESETP_0/count_ddr[7]:D
  Delay (ns):                  0.403                                                                           
  Slack (ns):                  0.362                                                                           
  Arrival (ns):                5.579                                                                           
  Required (ns):               5.217                                                                           

