//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Tue Mar 22 14:54:42 2016
// Version: v11.7 11.7.0.119
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

// MDDR_VIP_Simulation
module MDDR_VIP_Simulation(
);

//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire   [15:0] MDDR_TA_top_0_MDDR_ADDR;
wire   [2:0]  MDDR_TA_top_0_MDDR_BA;
wire          MDDR_TA_top_0_MDDR_CAS_N;
wire          MDDR_TA_top_0_MDDR_CKE;
wire          MDDR_TA_top_0_MDDR_CLK;
wire          MDDR_TA_top_0_MDDR_CLK_N;
wire          MDDR_TA_top_0_MDDR_CS_N;
wire          MDDR_TA_top_0_MDDR_DQS_TMATCH_0_OUT;
wire          MDDR_TA_top_0_MDDR_ODT;
wire          MDDR_TA_top_0_MDDR_RAS_N;
wire          MDDR_TA_top_0_MDDR_RESET_N;
wire          MDDR_TA_top_0_MDDR_WE_N;
wire          MDDR_TA_top_0_MMUART_0_TXD_M2F;
wire   [0:0]  net_0;
wire   [1:1]  net_1;
wire   [7:0]  net_2;
wire   [15:8] net_3;
wire   [0:0]  net_4;
wire   [1:1]  net_5;
wire   [0:0]  net_6;
wire   [1:1]  net_7;
wire          RESET_GEN_0_RESET;
wire   [1:0]  MDDR_DM_RDQS_net_0;
wire   [15:0] MDDR_DQ_net_0;
wire   [1:0]  MDDR_DQS_net_0;
wire   [1:0]  MDDR_DQS_N_net_0;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire          GND_net;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign GND_net    = 1'b0;
//--------------------------------------------------------------------
// Concatenation assignments
//--------------------------------------------------------------------
assign MDDR_DM_RDQS_net_0 = { net_1[1] , net_0[0] };
assign MDDR_DQ_net_0      = { net_3 , net_2 };
assign MDDR_DQS_net_0     = { net_5[1] , net_4[0] };
assign MDDR_DQS_N_net_0   = { net_7[1] , net_6[0] };

wire [1:0] MDDR_DM_RDQS;
wire [15:0] MDDR_DQ;
wire [1:0] MDDR_DQS;
wire [2:0] COMMAND;
assign COMMAND = {MDDR_TA_top_0_MDDR_RAS_N,MDDR_TA_top_0_MDDR_CAS_N,MDDR_TA_top_0_MDDR_WE_N};
assign MDDR_DM_RDQS = MDDR_DM_RDQS_net_0;
assign MDDR_DQ = MDDR_DQ_net_0;
assign MDDR_DQS = MDDR_DQS_net_0;
initial
begin
$display ("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++");
$display ("Loading LSRAM from lsram.mem file");
$display ("");
$readmemh("lsram_512x64.mem",MDDR_VIP_Simulation.MDDR_TA_top_0.AXI_IF_0.Rdata_mem);
$display (" Completed Loading LSRAM");
$display ("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++");
@(posedge MDDR_VIP_Simulation.MDDR_TA_top_0.AXI_IF_0.RESETn);
/* 2KB write */
repeat(9500) @(posedge MDDR_VIP_Simulation.MDDR_TA_top_0.AXI_IF_0.CLK);
force MDDR_VIP_Simulation.MDDR_TA_top_0.CMD_Decoder_0.command = 8'b001_001_01;
/* Disable Write */
repeat(15) @(posedge MDDR_VIP_Simulation.MDDR_TA_top_0.AXI_IF_0.CLK);
force MDDR_VIP_Simulation.MDDR_TA_top_0.CMD_Decoder_0.command = 8'b000_000_00;
/* 2KB Read */
repeat(5000) @(posedge MDDR_VIP_Simulation.MDDR_TA_top_0.AXI_IF_0.CLK);
force MDDR_VIP_Simulation.MDDR_TA_top_0.CMD_Decoder_0.command = 8'b001_001_10;

/* Disable Read */
repeat(15) @(posedge MDDR_VIP_Simulation.MDDR_TA_top_0.AXI_IF_0.CLK);
force MDDR_VIP_Simulation.MDDR_TA_top_0.CMD_Decoder_0.command = 8'b000_000_00;
end

//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------MDDR_TA_top
MDDR_TA_top MDDR_TA_top_0(
        // Inputs
        .MDDR_DQS_TMATCH_0_IN  ( MDDR_TA_top_0_MDDR_DQS_TMATCH_0_OUT ),
        .DEVRST_N              ( RESET_GEN_0_RESET ),
        .MMUART_0_RXD_F2M      ( MDDR_TA_top_0_MMUART_0_TXD_M2F ),
        // Outputs
        .MDDR_DQS_TMATCH_0_OUT ( MDDR_TA_top_0_MDDR_DQS_TMATCH_0_OUT ),
        .MDDR_CAS_N            ( MDDR_TA_top_0_MDDR_CAS_N ),
        .MDDR_CLK              ( MDDR_TA_top_0_MDDR_CLK ),
        .MDDR_CLK_N            ( MDDR_TA_top_0_MDDR_CLK_N ),
        .MDDR_CKE              ( MDDR_TA_top_0_MDDR_CKE ),
        .MDDR_CS_N             ( MDDR_TA_top_0_MDDR_CS_N ),
        .MDDR_ODT              ( MDDR_TA_top_0_MDDR_ODT ),
        .MDDR_RAS_N            ( MDDR_TA_top_0_MDDR_RAS_N ),
        .MDDR_RESET_N          ( MDDR_TA_top_0_MDDR_RESET_N ),
        .MDDR_WE_N             ( MDDR_TA_top_0_MDDR_WE_N ),
        .MMUART_0_TXD_M2F      ( MDDR_TA_top_0_MMUART_0_TXD_M2F ),
        .MDDR_ADDR             ( MDDR_TA_top_0_MDDR_ADDR ),
        .MDDR_BA               ( MDDR_TA_top_0_MDDR_BA ),
        // Inouts
        .MDDR_DM_RDQS          ( { net_1[1] , net_0[0] } ),
        .MDDR_DQ               ( { net_3 , net_2 } ),
        .MDDR_DQS              ( { net_5[1] , net_4[0] } ),
        .MDDR_DQS_N            ( { net_7[1] , net_6[0] } ) 
        );

//--------RESET_GEN   -   Actel:Simulation:RESET_GEN:1.0.1
RESET_GEN #( 
        .DELAY       ( 1000 ),
        .LOGIC_LEVEL ( 0 ) )
RESET_GEN_0(
        // Outputs
        .RESET ( RESET_GEN_0_RESET ) 
        );

//--------SimDRAM   -   Actel:Simulation:SimDRAM:1.0.102
SimDRAM #( 
        .AL                 ( 0 ),
        .BL_BITS            ( 8 ),
        .CL                 ( 5 ),
        .CWL                ( 5 ),
        .DQ_BITS            ( 8 ),
        .MEMORY             ( 0 ),
        .PARTIAL_REFRESH_EN ( 0 ),
        .RZQ                ( 240 ),
        .TRFC               ( 54 ),
        .WR                 ( 5 ) )
SimDRAM_0(
        // Inputs
        .DRAM_CAS_N   ( MDDR_TA_top_0_MDDR_CAS_N ),
        .DRAM_CKE     ( MDDR_TA_top_0_MDDR_CKE ),
        .DRAM_CLK     ( MDDR_TA_top_0_MDDR_CLK ),
        .DRAM_CLK_N   ( MDDR_TA_top_0_MDDR_CLK_N ),
        .DRAM_CS_N    ( MDDR_TA_top_0_MDDR_CS_N ),
        .DRAM_ODT     ( MDDR_TA_top_0_MDDR_ODT ),
        .DRAM_RAS_N   ( MDDR_TA_top_0_MDDR_RAS_N ),
        .DRAM_RESET_N ( MDDR_TA_top_0_MDDR_RESET_N ),
        .DRAM_WE_N    ( MDDR_TA_top_0_MDDR_WE_N ),
        .DRAM_ADDR    ( MDDR_TA_top_0_MDDR_ADDR ),
        .DRAM_BA      ( MDDR_TA_top_0_MDDR_BA ),
        .DRAM_DM      ( GND_net ), // tied to 1'b0 from definition
        // Outputs
        .DRAM_RDQS_N  (  ),
        // Inouts
        .DRAM_DM_RDQS ( net_0 ),
        .DRAM_DQS     ( net_4 ),
        .DRAM_DQS_N   ( net_6 ),
        .DRAM_DQ      ( net_2 ) 
        );

//--------SimDRAM   -   Actel:Simulation:SimDRAM:1.0.102
SimDRAM #( 
        .AL                 ( 0 ),
        .BL_BITS            ( 8 ),
        .CL                 ( 5 ),
        .CWL                ( 5 ),
        .DQ_BITS            ( 8 ),
        .MEMORY             ( 0 ),
        .PARTIAL_REFRESH_EN ( 0 ),
        .RZQ                ( 240 ),
        .TRFC               ( 54 ),
        .WR                 ( 5 ) )
SimDRAM_1(
        // Inputs
        .DRAM_CAS_N   ( MDDR_TA_top_0_MDDR_CAS_N ),
        .DRAM_CKE     ( MDDR_TA_top_0_MDDR_CKE ),
        .DRAM_CLK     ( MDDR_TA_top_0_MDDR_CLK ),
        .DRAM_CLK_N   ( MDDR_TA_top_0_MDDR_CLK_N ),
        .DRAM_CS_N    ( MDDR_TA_top_0_MDDR_CS_N ),
        .DRAM_ODT     ( MDDR_TA_top_0_MDDR_ODT ),
        .DRAM_RAS_N   ( MDDR_TA_top_0_MDDR_RAS_N ),
        .DRAM_RESET_N ( MDDR_TA_top_0_MDDR_RESET_N ),
        .DRAM_WE_N    ( MDDR_TA_top_0_MDDR_WE_N ),
        .DRAM_ADDR    ( MDDR_TA_top_0_MDDR_ADDR ),
        .DRAM_BA      ( MDDR_TA_top_0_MDDR_BA ),
        .DRAM_DM      ( GND_net ), // tied to 1'b0 from definition
        // Outputs
        .DRAM_RDQS_N  (  ),
        // Inouts
        .DRAM_DM_RDQS ( net_1 ),
        .DRAM_DQS     ( net_5 ),
        .DRAM_DQS_N   ( net_7 ),
        .DRAM_DQ      ( net_3 ) 
        );


endmodule
