`timescale 1 ns/100 ps
// Version: v11.7 11.7.0.119


module RCOSC_25_50MHZ_FAB(
       A,
       CLKOUT
    );
input  A;
output CLKOUT;

    
endmodule


module RCOSC_25_50MHZ(
       CLKOUT
    );
output CLKOUT;

    parameter FREQUENCY = 50.0 ;
    
endmodule


module MSS_120(
       CAN_RXBUS_MGPIO3A_H2F_A,
       CAN_RXBUS_MGPIO3A_H2F_B,
       CAN_TX_EBL_MGPIO4A_H2F_A,
       CAN_TX_EBL_MGPIO4A_H2F_B,
       CAN_TXBUS_MGPIO2A_H2F_A,
       CAN_TXBUS_MGPIO2A_H2F_B,
       CLK_CONFIG_APB,
       COMMS_INT,
       CONFIG_PRESET_N,
       EDAC_ERROR,
       F_FM0_RDATA,
       F_FM0_READYOUT,
       F_FM0_RESP,
       F_FM1_RDATA,
       F_FM1_READYOUT,
       F_FM1_RESP,
       F_HM0_ADDR,
       F_HM0_ENABLE,
       F_HM0_SEL,
       F_HM0_SIZE,
       F_HM0_TRANS1,
       F_HM0_WDATA,
       F_HM0_WRITE,
       F_HM1_ADDR,
       F_HM1_ENABLE,
       F_HM1_SEL,
       F_HM1_SIZE,
       F_HM1_TRANS1,
       F_HM1_WDATA,
       F_HM1_WRITE,
       FAB_CHRGVBUS,
       FAB_DISCHRGVBUS,
       FAB_DMPULLDOWN,
       FAB_DPPULLDOWN,
       FAB_DRVVBUS,
       FAB_IDPULLUP,
       FAB_OPMODE,
       FAB_SUSPENDM,
       FAB_TERMSEL,
       FAB_TXVALID,
       FAB_VCONTROL,
       FAB_VCONTROLLOADM,
       FAB_XCVRSEL,
       FAB_XDATAOUT,
       FACC_GLMUX_SEL,
       FIC32_0_MASTER,
       FIC32_1_MASTER,
       FPGA_RESET_N,
       GTX_CLK,
       H2F_INTERRUPT,
       H2F_NMI,
       H2FCALIB,
       I2C0_SCL_MGPIO31B_H2F_A,
       I2C0_SCL_MGPIO31B_H2F_B,
       I2C0_SDA_MGPIO30B_H2F_A,
       I2C0_SDA_MGPIO30B_H2F_B,
       I2C1_SCL_MGPIO1A_H2F_A,
       I2C1_SCL_MGPIO1A_H2F_B,
       I2C1_SDA_MGPIO0A_H2F_A,
       I2C1_SDA_MGPIO0A_H2F_B,
       MDCF,
       MDOENF,
       MDOF,
       MMUART0_CTS_MGPIO19B_H2F_A,
       MMUART0_CTS_MGPIO19B_H2F_B,
       MMUART0_DCD_MGPIO22B_H2F_A,
       MMUART0_DCD_MGPIO22B_H2F_B,
       MMUART0_DSR_MGPIO20B_H2F_A,
       MMUART0_DSR_MGPIO20B_H2F_B,
       MMUART0_DTR_MGPIO18B_H2F_A,
       MMUART0_DTR_MGPIO18B_H2F_B,
       MMUART0_RI_MGPIO21B_H2F_A,
       MMUART0_RI_MGPIO21B_H2F_B,
       MMUART0_RTS_MGPIO17B_H2F_A,
       MMUART0_RTS_MGPIO17B_H2F_B,
       MMUART0_RXD_MGPIO28B_H2F_A,
       MMUART0_RXD_MGPIO28B_H2F_B,
       MMUART0_SCK_MGPIO29B_H2F_A,
       MMUART0_SCK_MGPIO29B_H2F_B,
       MMUART0_TXD_MGPIO27B_H2F_A,
       MMUART0_TXD_MGPIO27B_H2F_B,
       MMUART1_DTR_MGPIO12B_H2F_A,
       MMUART1_RTS_MGPIO11B_H2F_A,
       MMUART1_RTS_MGPIO11B_H2F_B,
       MMUART1_RXD_MGPIO26B_H2F_A,
       MMUART1_RXD_MGPIO26B_H2F_B,
       MMUART1_SCK_MGPIO25B_H2F_A,
       MMUART1_SCK_MGPIO25B_H2F_B,
       MMUART1_TXD_MGPIO24B_H2F_A,
       MMUART1_TXD_MGPIO24B_H2F_B,
       MPLL_LOCK,
       PER2_FABRIC_PADDR,
       PER2_FABRIC_PENABLE,
       PER2_FABRIC_PSEL,
       PER2_FABRIC_PWDATA,
       PER2_FABRIC_PWRITE,
       RTC_MATCH,
       SLEEPDEEP,
       SLEEPHOLDACK,
       SLEEPING,
       SMBALERT_NO0,
       SMBALERT_NO1,
       SMBSUS_NO0,
       SMBSUS_NO1,
       SPI0_CLK_OUT,
       SPI0_SDI_MGPIO5A_H2F_A,
       SPI0_SDI_MGPIO5A_H2F_B,
       SPI0_SDO_MGPIO6A_H2F_A,
       SPI0_SDO_MGPIO6A_H2F_B,
       SPI0_SS0_MGPIO7A_H2F_A,
       SPI0_SS0_MGPIO7A_H2F_B,
       SPI0_SS1_MGPIO8A_H2F_A,
       SPI0_SS1_MGPIO8A_H2F_B,
       SPI0_SS2_MGPIO9A_H2F_A,
       SPI0_SS2_MGPIO9A_H2F_B,
       SPI0_SS3_MGPIO10A_H2F_A,
       SPI0_SS3_MGPIO10A_H2F_B,
       SPI0_SS4_MGPIO19A_H2F_A,
       SPI0_SS5_MGPIO20A_H2F_A,
       SPI0_SS6_MGPIO21A_H2F_A,
       SPI0_SS7_MGPIO22A_H2F_A,
       SPI1_CLK_OUT,
       SPI1_SDI_MGPIO11A_H2F_A,
       SPI1_SDI_MGPIO11A_H2F_B,
       SPI1_SDO_MGPIO12A_H2F_A,
       SPI1_SDO_MGPIO12A_H2F_B,
       SPI1_SS0_MGPIO13A_H2F_A,
       SPI1_SS0_MGPIO13A_H2F_B,
       SPI1_SS1_MGPIO14A_H2F_A,
       SPI1_SS1_MGPIO14A_H2F_B,
       SPI1_SS2_MGPIO15A_H2F_A,
       SPI1_SS2_MGPIO15A_H2F_B,
       SPI1_SS3_MGPIO16A_H2F_A,
       SPI1_SS3_MGPIO16A_H2F_B,
       SPI1_SS4_MGPIO17A_H2F_A,
       SPI1_SS5_MGPIO18A_H2F_A,
       SPI1_SS6_MGPIO23A_H2F_A,
       SPI1_SS7_MGPIO24A_H2F_A,
       TCGF,
       TRACECLK,
       TRACEDATA,
       TX_CLK,
       TX_ENF,
       TX_ERRF,
       TXCTL_EN_RIF,
       TXD_RIF,
       TXDF,
       TXEV,
       WDOGTIMEOUT,
       F_ARREADY_HREADYOUT1,
       F_AWREADY_HREADYOUT0,
       F_BID,
       F_BRESP_HRESP0,
       F_BVALID,
       F_RDATA_HRDATA01,
       F_RID,
       F_RLAST,
       F_RRESP_HRESP1,
       F_RVALID,
       F_WREADY,
       MDDR_FABRIC_PRDATA,
       MDDR_FABRIC_PREADY,
       MDDR_FABRIC_PSLVERR,
       REV_ARADDR,
       REV_ARBURST,
       REV_ARID,
       REV_ARLEN,
       REV_ARLOCK,
       REV_ARSIZE,
       REV_AWADDR,
       REV_AWLOCK,
       REV_AWSIZE,
       REV_RREADY,
       REV_WID,
       REV_WSTRB,
       CAN_RXBUS_F2H_SCP,
       CAN_TX_EBL_F2H_SCP,
       CAN_TXBUS_F2H_SCP,
       CLK_BASE,
       COLF,
       CRSF,
       F2_DMAREADY,
       F2H_INTERRUPT,
       F2HCALIB,
       F_DMAREADY,
       F_FM0_ADDR,
       F_FM0_ENABLE,
       F_FM0_MASTLOCK,
       F_FM0_READY,
       F_FM0_SEL,
       F_FM0_SIZE,
       F_FM0_TRANS1,
       F_FM0_WDATA,
       F_FM0_WRITE,
       F_FM1_ADDR,
       F_FM1_ENABLE,
       F_FM1_MASTLOCK,
       F_FM1_READY,
       F_FM1_SEL,
       F_FM1_SIZE,
       F_FM1_TRANS1,
       F_FM1_WDATA,
       F_FM1_WRITE,
       F_HM0_RDATA,
       F_HM0_READY,
       F_HM0_RESP,
       F_HM1_RDATA,
       F_HM1_READY,
       F_HM1_RESP,
       FAB_AVALID,
       FAB_HOSTDISCON,
       FAB_IDDIG,
       FAB_LINESTATE,
       FAB_M3_RESET_N,
       FAB_PLL_LOCK,
       FAB_RXACTIVE,
       FAB_RXERROR,
       FAB_RXVALID,
       FAB_RXVALIDH,
       FAB_SESSEND,
       FAB_TXREADY,
       FAB_VBUSVALID,
       FAB_VSTATUS,
       FAB_XDATAIN,
       GTX_CLKPF,
       I2C0_BCLK,
       I2C0_SCL_F2H_SCP,
       I2C0_SDA_F2H_SCP,
       I2C1_BCLK,
       I2C1_SCL_F2H_SCP,
       I2C1_SDA_F2H_SCP,
       MDIF,
       MGPIO0A_F2H_GPIN,
       MGPIO10A_F2H_GPIN,
       MGPIO11A_F2H_GPIN,
       MGPIO11B_F2H_GPIN,
       MGPIO12A_F2H_GPIN,
       MGPIO13A_F2H_GPIN,
       MGPIO14A_F2H_GPIN,
       MGPIO15A_F2H_GPIN,
       MGPIO16A_F2H_GPIN,
       MGPIO17B_F2H_GPIN,
       MGPIO18B_F2H_GPIN,
       MGPIO19B_F2H_GPIN,
       MGPIO1A_F2H_GPIN,
       MGPIO20B_F2H_GPIN,
       MGPIO21B_F2H_GPIN,
       MGPIO22B_F2H_GPIN,
       MGPIO24B_F2H_GPIN,
       MGPIO25B_F2H_GPIN,
       MGPIO26B_F2H_GPIN,
       MGPIO27B_F2H_GPIN,
       MGPIO28B_F2H_GPIN,
       MGPIO29B_F2H_GPIN,
       MGPIO2A_F2H_GPIN,
       MGPIO30B_F2H_GPIN,
       MGPIO31B_F2H_GPIN,
       MGPIO3A_F2H_GPIN,
       MGPIO4A_F2H_GPIN,
       MGPIO5A_F2H_GPIN,
       MGPIO6A_F2H_GPIN,
       MGPIO7A_F2H_GPIN,
       MGPIO8A_F2H_GPIN,
       MGPIO9A_F2H_GPIN,
       MMUART0_CTS_F2H_SCP,
       MMUART0_DCD_F2H_SCP,
       MMUART0_DSR_F2H_SCP,
       MMUART0_DTR_F2H_SCP,
       MMUART0_RI_F2H_SCP,
       MMUART0_RTS_F2H_SCP,
       MMUART0_RXD_F2H_SCP,
       MMUART0_SCK_F2H_SCP,
       MMUART0_TXD_F2H_SCP,
       MMUART1_CTS_F2H_SCP,
       MMUART1_DCD_F2H_SCP,
       MMUART1_DSR_F2H_SCP,
       MMUART1_RI_F2H_SCP,
       MMUART1_RTS_F2H_SCP,
       MMUART1_RXD_F2H_SCP,
       MMUART1_SCK_F2H_SCP,
       MMUART1_TXD_F2H_SCP,
       PER2_FABRIC_PRDATA,
       PER2_FABRIC_PREADY,
       PER2_FABRIC_PSLVERR,
       RCGF,
       RX_CLKPF,
       RX_DVF,
       RX_ERRF,
       RX_EV,
       RXDF,
       SLEEPHOLDREQ,
       SMBALERT_NI0,
       SMBALERT_NI1,
       SMBSUS_NI0,
       SMBSUS_NI1,
       SPI0_CLK_IN,
       SPI0_SDI_F2H_SCP,
       SPI0_SDO_F2H_SCP,
       SPI0_SS0_F2H_SCP,
       SPI0_SS1_F2H_SCP,
       SPI0_SS2_F2H_SCP,
       SPI0_SS3_F2H_SCP,
       SPI1_CLK_IN,
       SPI1_SDI_F2H_SCP,
       SPI1_SDO_F2H_SCP,
       SPI1_SS0_F2H_SCP,
       SPI1_SS1_F2H_SCP,
       SPI1_SS2_F2H_SCP,
       SPI1_SS3_F2H_SCP,
       TX_CLKPF,
       USER_MSS_GPIO_RESET_N,
       USER_MSS_RESET_N,
       XCLK_FAB,
       CLK_MDDR_APB,
       F_ARADDR_HADDR1,
       F_ARBURST_HTRANS1,
       F_ARID_HSEL1,
       F_ARLEN_HBURST1,
       F_ARLOCK_HMASTLOCK1,
       F_ARSIZE_HSIZE1,
       F_ARVALID_HWRITE1,
       F_AWADDR_HADDR0,
       F_AWBURST_HTRANS0,
       F_AWID_HSEL0,
       F_AWLEN_HBURST0,
       F_AWLOCK_HMASTLOCK0,
       F_AWSIZE_HSIZE0,
       F_AWVALID_HWRITE0,
       F_BREADY,
       F_RMW_AXI,
       F_RREADY,
       F_WDATA_HWDATA01,
       F_WID_HREADY01,
       F_WLAST,
       F_WSTRB,
       F_WVALID,
       FPGA_MDDR_ARESET_N,
       MDDR_FABRIC_PADDR,
       MDDR_FABRIC_PENABLE,
       MDDR_FABRIC_PSEL,
       MDDR_FABRIC_PWDATA,
       MDDR_FABRIC_PWRITE,
       PRESET_N,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_IN,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_IN,
       DM_IN,
       DRAM_DQ_IN,
       DRAM_DQS_IN,
       DRAM_FIFO_WE_IN,
       I2C0_SCL_USBC_DATA1_MGPIO31B_IN,
       I2C0_SDA_USBC_DATA0_MGPIO30B_IN,
       I2C1_SCL_USBA_DATA4_MGPIO1A_IN,
       I2C1_SDA_USBA_DATA3_MGPIO0A_IN,
       MGPIO0B_IN,
       MGPIO10B_IN,
       MGPIO1B_IN,
       MGPIO25A_IN,
       MGPIO26A_IN,
       MGPIO27A_IN,
       MGPIO28A_IN,
       MGPIO29A_IN,
       MGPIO2B_IN,
       MGPIO30A_IN,
       MGPIO31A_IN,
       MGPIO3B_IN,
       MGPIO4B_IN,
       MGPIO5B_IN,
       MGPIO6B_IN,
       MGPIO7B_IN,
       MGPIO8B_IN,
       MGPIO9B_IN,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_IN,
       MMUART0_DCD_MGPIO22B_IN,
       MMUART0_DSR_MGPIO20B_IN,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_IN,
       MMUART0_RI_MGPIO21B_IN,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_IN,
       MMUART0_RXD_USBC_STP_MGPIO28B_IN,
       MMUART0_SCK_USBC_NXT_MGPIO29B_IN,
       MMUART0_TXD_USBC_DIR_MGPIO27B_IN,
       MMUART1_CTS_MGPIO13B_IN,
       MMUART1_DCD_MGPIO16B_IN,
       MMUART1_DSR_MGPIO14B_IN,
       MMUART1_DTR_MGPIO12B_IN,
       MMUART1_RI_MGPIO15B_IN,
       MMUART1_RTS_MGPIO11B_IN,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_IN,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_IN,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_IN,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN,
       RGMII_MDC_RMII_MDC_IN,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN,
       RGMII_RX_CLK_IN,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN,
       RGMII_RXD3_USBB_DATA4_IN,
       RGMII_TX_CLK_IN,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_IN,
       RGMII_TXD1_RMII_TXD1_USBB_STP_IN,
       RGMII_TXD2_USBB_DATA5_IN,
       RGMII_TXD3_USBB_DATA6_IN,
       SPI0_SCK_USBA_XCLK_IN,
       SPI0_SDI_USBA_DIR_MGPIO5A_IN,
       SPI0_SDO_USBA_STP_MGPIO6A_IN,
       SPI0_SS0_USBA_NXT_MGPIO7A_IN,
       SPI0_SS1_USBA_DATA5_MGPIO8A_IN,
       SPI0_SS2_USBA_DATA6_MGPIO9A_IN,
       SPI0_SS3_USBA_DATA7_MGPIO10A_IN,
       SPI0_SS4_MGPIO19A_IN,
       SPI0_SS5_MGPIO20A_IN,
       SPI0_SS6_MGPIO21A_IN,
       SPI0_SS7_MGPIO22A_IN,
       SPI1_SCK_IN,
       SPI1_SDI_MGPIO11A_IN,
       SPI1_SDO_MGPIO12A_IN,
       SPI1_SS0_MGPIO13A_IN,
       SPI1_SS1_MGPIO14A_IN,
       SPI1_SS2_MGPIO15A_IN,
       SPI1_SS3_MGPIO16A_IN,
       SPI1_SS4_MGPIO17A_IN,
       SPI1_SS5_MGPIO18A_IN,
       SPI1_SS6_MGPIO23A_IN,
       SPI1_SS7_MGPIO24A_IN,
       USBC_XCLK_IN,
       USBD_DATA0_IN,
       USBD_DATA1_IN,
       USBD_DATA2_IN,
       USBD_DATA3_IN,
       USBD_DATA4_IN,
       USBD_DATA5_IN,
       USBD_DATA6_IN,
       USBD_DATA7_MGPIO23B_IN,
       USBD_DIR_IN,
       USBD_NXT_IN,
       USBD_STP_IN,
       USBD_XCLK_IN,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT,
       DRAM_ADDR,
       DRAM_BA,
       DRAM_CASN,
       DRAM_CKE,
       DRAM_CLK,
       DRAM_CSN,
       DRAM_DM_RDQS_OUT,
       DRAM_DQ_OUT,
       DRAM_DQS_OUT,
       DRAM_FIFO_WE_OUT,
       DRAM_ODT,
       DRAM_RASN,
       DRAM_RSTN,
       DRAM_WEN,
       I2C0_SCL_USBC_DATA1_MGPIO31B_OUT,
       I2C0_SDA_USBC_DATA0_MGPIO30B_OUT,
       I2C1_SCL_USBA_DATA4_MGPIO1A_OUT,
       I2C1_SDA_USBA_DATA3_MGPIO0A_OUT,
       MGPIO0B_OUT,
       MGPIO10B_OUT,
       MGPIO1B_OUT,
       MGPIO25A_OUT,
       MGPIO26A_OUT,
       MGPIO27A_OUT,
       MGPIO28A_OUT,
       MGPIO29A_OUT,
       MGPIO2B_OUT,
       MGPIO30A_OUT,
       MGPIO31A_OUT,
       MGPIO3B_OUT,
       MGPIO4B_OUT,
       MGPIO5B_OUT,
       MGPIO6B_OUT,
       MGPIO7B_OUT,
       MGPIO8B_OUT,
       MGPIO9B_OUT,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT,
       MMUART0_DCD_MGPIO22B_OUT,
       MMUART0_DSR_MGPIO20B_OUT,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT,
       MMUART0_RI_MGPIO21B_OUT,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT,
       MMUART0_RXD_USBC_STP_MGPIO28B_OUT,
       MMUART0_SCK_USBC_NXT_MGPIO29B_OUT,
       MMUART0_TXD_USBC_DIR_MGPIO27B_OUT,
       MMUART1_CTS_MGPIO13B_OUT,
       MMUART1_DCD_MGPIO16B_OUT,
       MMUART1_DSR_MGPIO14B_OUT,
       MMUART1_DTR_MGPIO12B_OUT,
       MMUART1_RI_MGPIO15B_OUT,
       MMUART1_RTS_MGPIO11B_OUT,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT,
       RGMII_MDC_RMII_MDC_OUT,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT,
       RGMII_RX_CLK_OUT,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT,
       RGMII_RXD3_USBB_DATA4_OUT,
       RGMII_TX_CLK_OUT,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT,
       RGMII_TXD1_RMII_TXD1_USBB_STP_OUT,
       RGMII_TXD2_USBB_DATA5_OUT,
       RGMII_TXD3_USBB_DATA6_OUT,
       SPI0_SCK_USBA_XCLK_OUT,
       SPI0_SDI_USBA_DIR_MGPIO5A_OUT,
       SPI0_SDO_USBA_STP_MGPIO6A_OUT,
       SPI0_SS0_USBA_NXT_MGPIO7A_OUT,
       SPI0_SS1_USBA_DATA5_MGPIO8A_OUT,
       SPI0_SS2_USBA_DATA6_MGPIO9A_OUT,
       SPI0_SS3_USBA_DATA7_MGPIO10A_OUT,
       SPI0_SS4_MGPIO19A_OUT,
       SPI0_SS5_MGPIO20A_OUT,
       SPI0_SS6_MGPIO21A_OUT,
       SPI0_SS7_MGPIO22A_OUT,
       SPI1_SCK_OUT,
       SPI1_SDI_MGPIO11A_OUT,
       SPI1_SDO_MGPIO12A_OUT,
       SPI1_SS0_MGPIO13A_OUT,
       SPI1_SS1_MGPIO14A_OUT,
       SPI1_SS2_MGPIO15A_OUT,
       SPI1_SS3_MGPIO16A_OUT,
       SPI1_SS4_MGPIO17A_OUT,
       SPI1_SS5_MGPIO18A_OUT,
       SPI1_SS6_MGPIO23A_OUT,
       SPI1_SS7_MGPIO24A_OUT,
       USBC_XCLK_OUT,
       USBD_DATA0_OUT,
       USBD_DATA1_OUT,
       USBD_DATA2_OUT,
       USBD_DATA3_OUT,
       USBD_DATA4_OUT,
       USBD_DATA5_OUT,
       USBD_DATA6_OUT,
       USBD_DATA7_MGPIO23B_OUT,
       USBD_DIR_OUT,
       USBD_NXT_OUT,
       USBD_STP_OUT,
       USBD_XCLK_OUT,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_OE,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_OE,
       DM_OE,
       DRAM_DQ_OE,
       DRAM_DQS_OE,
       I2C0_SCL_USBC_DATA1_MGPIO31B_OE,
       I2C0_SDA_USBC_DATA0_MGPIO30B_OE,
       I2C1_SCL_USBA_DATA4_MGPIO1A_OE,
       I2C1_SDA_USBA_DATA3_MGPIO0A_OE,
       MGPIO0B_OE,
       MGPIO10B_OE,
       MGPIO1B_OE,
       MGPIO25A_OE,
       MGPIO26A_OE,
       MGPIO27A_OE,
       MGPIO28A_OE,
       MGPIO29A_OE,
       MGPIO2B_OE,
       MGPIO30A_OE,
       MGPIO31A_OE,
       MGPIO3B_OE,
       MGPIO4B_OE,
       MGPIO5B_OE,
       MGPIO6B_OE,
       MGPIO7B_OE,
       MGPIO8B_OE,
       MGPIO9B_OE,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_OE,
       MMUART0_DCD_MGPIO22B_OE,
       MMUART0_DSR_MGPIO20B_OE,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_OE,
       MMUART0_RI_MGPIO21B_OE,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_OE,
       MMUART0_RXD_USBC_STP_MGPIO28B_OE,
       MMUART0_SCK_USBC_NXT_MGPIO29B_OE,
       MMUART0_TXD_USBC_DIR_MGPIO27B_OE,
       MMUART1_CTS_MGPIO13B_OE,
       MMUART1_DCD_MGPIO16B_OE,
       MMUART1_DSR_MGPIO14B_OE,
       MMUART1_DTR_MGPIO12B_OE,
       MMUART1_RI_MGPIO15B_OE,
       MMUART1_RTS_MGPIO11B_OE,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_OE,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_OE,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_OE,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE,
       RGMII_MDC_RMII_MDC_OE,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE,
       RGMII_RX_CLK_OE,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE,
       RGMII_RXD3_USBB_DATA4_OE,
       RGMII_TX_CLK_OE,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_OE,
       RGMII_TXD1_RMII_TXD1_USBB_STP_OE,
       RGMII_TXD2_USBB_DATA5_OE,
       RGMII_TXD3_USBB_DATA6_OE,
       SPI0_SCK_USBA_XCLK_OE,
       SPI0_SDI_USBA_DIR_MGPIO5A_OE,
       SPI0_SDO_USBA_STP_MGPIO6A_OE,
       SPI0_SS0_USBA_NXT_MGPIO7A_OE,
       SPI0_SS1_USBA_DATA5_MGPIO8A_OE,
       SPI0_SS2_USBA_DATA6_MGPIO9A_OE,
       SPI0_SS3_USBA_DATA7_MGPIO10A_OE,
       SPI0_SS4_MGPIO19A_OE,
       SPI0_SS5_MGPIO20A_OE,
       SPI0_SS6_MGPIO21A_OE,
       SPI0_SS7_MGPIO22A_OE,
       SPI1_SCK_OE,
       SPI1_SDI_MGPIO11A_OE,
       SPI1_SDO_MGPIO12A_OE,
       SPI1_SS0_MGPIO13A_OE,
       SPI1_SS1_MGPIO14A_OE,
       SPI1_SS2_MGPIO15A_OE,
       SPI1_SS3_MGPIO16A_OE,
       SPI1_SS4_MGPIO17A_OE,
       SPI1_SS5_MGPIO18A_OE,
       SPI1_SS6_MGPIO23A_OE,
       SPI1_SS7_MGPIO24A_OE,
       USBC_XCLK_OE,
       USBD_DATA0_OE,
       USBD_DATA1_OE,
       USBD_DATA2_OE,
       USBD_DATA3_OE,
       USBD_DATA4_OE,
       USBD_DATA5_OE,
       USBD_DATA6_OE,
       USBD_DATA7_MGPIO23B_OE,
       USBD_DIR_OE,
       USBD_NXT_OE,
       USBD_STP_OE,
       USBD_XCLK_OE
    );
output CAN_RXBUS_MGPIO3A_H2F_A;
output CAN_RXBUS_MGPIO3A_H2F_B;
output CAN_TX_EBL_MGPIO4A_H2F_A;
output CAN_TX_EBL_MGPIO4A_H2F_B;
output CAN_TXBUS_MGPIO2A_H2F_A;
output CAN_TXBUS_MGPIO2A_H2F_B;
output CLK_CONFIG_APB;
output COMMS_INT;
output CONFIG_PRESET_N;
output [7:0] EDAC_ERROR;
output [31:0] F_FM0_RDATA;
output F_FM0_READYOUT;
output F_FM0_RESP;
output [31:0] F_FM1_RDATA;
output F_FM1_READYOUT;
output F_FM1_RESP;
output [31:0] F_HM0_ADDR;
output F_HM0_ENABLE;
output F_HM0_SEL;
output [1:0] F_HM0_SIZE;
output F_HM0_TRANS1;
output [31:0] F_HM0_WDATA;
output F_HM0_WRITE;
output [31:0] F_HM1_ADDR;
output F_HM1_ENABLE;
output F_HM1_SEL;
output [1:0] F_HM1_SIZE;
output F_HM1_TRANS1;
output [31:0] F_HM1_WDATA;
output F_HM1_WRITE;
output FAB_CHRGVBUS;
output FAB_DISCHRGVBUS;
output FAB_DMPULLDOWN;
output FAB_DPPULLDOWN;
output FAB_DRVVBUS;
output FAB_IDPULLUP;
output [1:0] FAB_OPMODE;
output FAB_SUSPENDM;
output FAB_TERMSEL;
output FAB_TXVALID;
output [3:0] FAB_VCONTROL;
output FAB_VCONTROLLOADM;
output [1:0] FAB_XCVRSEL;
output [7:0] FAB_XDATAOUT;
output FACC_GLMUX_SEL;
output [1:0] FIC32_0_MASTER;
output [1:0] FIC32_1_MASTER;
output FPGA_RESET_N;
output GTX_CLK;
output [15:0] H2F_INTERRUPT;
output H2F_NMI;
output H2FCALIB;
output I2C0_SCL_MGPIO31B_H2F_A;
output I2C0_SCL_MGPIO31B_H2F_B;
output I2C0_SDA_MGPIO30B_H2F_A;
output I2C0_SDA_MGPIO30B_H2F_B;
output I2C1_SCL_MGPIO1A_H2F_A;
output I2C1_SCL_MGPIO1A_H2F_B;
output I2C1_SDA_MGPIO0A_H2F_A;
output I2C1_SDA_MGPIO0A_H2F_B;
output MDCF;
output MDOENF;
output MDOF;
output MMUART0_CTS_MGPIO19B_H2F_A;
output MMUART0_CTS_MGPIO19B_H2F_B;
output MMUART0_DCD_MGPIO22B_H2F_A;
output MMUART0_DCD_MGPIO22B_H2F_B;
output MMUART0_DSR_MGPIO20B_H2F_A;
output MMUART0_DSR_MGPIO20B_H2F_B;
output MMUART0_DTR_MGPIO18B_H2F_A;
output MMUART0_DTR_MGPIO18B_H2F_B;
output MMUART0_RI_MGPIO21B_H2F_A;
output MMUART0_RI_MGPIO21B_H2F_B;
output MMUART0_RTS_MGPIO17B_H2F_A;
output MMUART0_RTS_MGPIO17B_H2F_B;
output MMUART0_RXD_MGPIO28B_H2F_A;
output MMUART0_RXD_MGPIO28B_H2F_B;
output MMUART0_SCK_MGPIO29B_H2F_A;
output MMUART0_SCK_MGPIO29B_H2F_B;
output MMUART0_TXD_MGPIO27B_H2F_A;
output MMUART0_TXD_MGPIO27B_H2F_B;
output MMUART1_DTR_MGPIO12B_H2F_A;
output MMUART1_RTS_MGPIO11B_H2F_A;
output MMUART1_RTS_MGPIO11B_H2F_B;
output MMUART1_RXD_MGPIO26B_H2F_A;
output MMUART1_RXD_MGPIO26B_H2F_B;
output MMUART1_SCK_MGPIO25B_H2F_A;
output MMUART1_SCK_MGPIO25B_H2F_B;
output MMUART1_TXD_MGPIO24B_H2F_A;
output MMUART1_TXD_MGPIO24B_H2F_B;
output MPLL_LOCK;
output [16:2] PER2_FABRIC_PADDR;
output PER2_FABRIC_PENABLE;
output PER2_FABRIC_PSEL;
output [31:0] PER2_FABRIC_PWDATA;
output PER2_FABRIC_PWRITE;
output RTC_MATCH;
output SLEEPDEEP;
output SLEEPHOLDACK;
output SLEEPING;
output SMBALERT_NO0;
output SMBALERT_NO1;
output SMBSUS_NO0;
output SMBSUS_NO1;
output SPI0_CLK_OUT;
output SPI0_SDI_MGPIO5A_H2F_A;
output SPI0_SDI_MGPIO5A_H2F_B;
output SPI0_SDO_MGPIO6A_H2F_A;
output SPI0_SDO_MGPIO6A_H2F_B;
output SPI0_SS0_MGPIO7A_H2F_A;
output SPI0_SS0_MGPIO7A_H2F_B;
output SPI0_SS1_MGPIO8A_H2F_A;
output SPI0_SS1_MGPIO8A_H2F_B;
output SPI0_SS2_MGPIO9A_H2F_A;
output SPI0_SS2_MGPIO9A_H2F_B;
output SPI0_SS3_MGPIO10A_H2F_A;
output SPI0_SS3_MGPIO10A_H2F_B;
output SPI0_SS4_MGPIO19A_H2F_A;
output SPI0_SS5_MGPIO20A_H2F_A;
output SPI0_SS6_MGPIO21A_H2F_A;
output SPI0_SS7_MGPIO22A_H2F_A;
output SPI1_CLK_OUT;
output SPI1_SDI_MGPIO11A_H2F_A;
output SPI1_SDI_MGPIO11A_H2F_B;
output SPI1_SDO_MGPIO12A_H2F_A;
output SPI1_SDO_MGPIO12A_H2F_B;
output SPI1_SS0_MGPIO13A_H2F_A;
output SPI1_SS0_MGPIO13A_H2F_B;
output SPI1_SS1_MGPIO14A_H2F_A;
output SPI1_SS1_MGPIO14A_H2F_B;
output SPI1_SS2_MGPIO15A_H2F_A;
output SPI1_SS2_MGPIO15A_H2F_B;
output SPI1_SS3_MGPIO16A_H2F_A;
output SPI1_SS3_MGPIO16A_H2F_B;
output SPI1_SS4_MGPIO17A_H2F_A;
output SPI1_SS5_MGPIO18A_H2F_A;
output SPI1_SS6_MGPIO23A_H2F_A;
output SPI1_SS7_MGPIO24A_H2F_A;
output [9:0] TCGF;
output TRACECLK;
output [3:0] TRACEDATA;
output TX_CLK;
output TX_ENF;
output TX_ERRF;
output TXCTL_EN_RIF;
output [3:0] TXD_RIF;
output [7:0] TXDF;
output TXEV;
output WDOGTIMEOUT;
output F_ARREADY_HREADYOUT1;
output F_AWREADY_HREADYOUT0;
output [3:0] F_BID;
output [1:0] F_BRESP_HRESP0;
output F_BVALID;
output [63:0] F_RDATA_HRDATA01;
output [3:0] F_RID;
output F_RLAST;
output [1:0] F_RRESP_HRESP1;
output F_RVALID;
output F_WREADY;
output [15:0] MDDR_FABRIC_PRDATA;
output MDDR_FABRIC_PREADY;
output MDDR_FABRIC_PSLVERR;
output [31:0] REV_ARADDR;
output [1:0] REV_ARBURST;
output [3:0] REV_ARID;
output [3:0] REV_ARLEN;
output [1:0] REV_ARLOCK;
output [1:0] REV_ARSIZE;
output [31:0] REV_AWADDR;
output [1:0] REV_AWLOCK;
output [1:0] REV_AWSIZE;
output REV_RREADY;
output [3:0] REV_WID;
output [7:0] REV_WSTRB;
input  CAN_RXBUS_F2H_SCP;
input  CAN_TX_EBL_F2H_SCP;
input  CAN_TXBUS_F2H_SCP;
input  CLK_BASE;
input  COLF;
input  CRSF;
input  [1:0] F2_DMAREADY;
input  [15:0] F2H_INTERRUPT;
input  F2HCALIB;
input  [1:0] F_DMAREADY;
input  [31:0] F_FM0_ADDR;
input  F_FM0_ENABLE;
input  F_FM0_MASTLOCK;
input  F_FM0_READY;
input  F_FM0_SEL;
input  [1:0] F_FM0_SIZE;
input  F_FM0_TRANS1;
input  [31:0] F_FM0_WDATA;
input  F_FM0_WRITE;
input  [31:0] F_FM1_ADDR;
input  F_FM1_ENABLE;
input  F_FM1_MASTLOCK;
input  F_FM1_READY;
input  F_FM1_SEL;
input  [1:0] F_FM1_SIZE;
input  F_FM1_TRANS1;
input  [31:0] F_FM1_WDATA;
input  F_FM1_WRITE;
input  [31:0] F_HM0_RDATA;
input  F_HM0_READY;
input  F_HM0_RESP;
input  [31:0] F_HM1_RDATA;
input  F_HM1_READY;
input  F_HM1_RESP;
input  FAB_AVALID;
input  FAB_HOSTDISCON;
input  FAB_IDDIG;
input  [1:0] FAB_LINESTATE;
input  FAB_M3_RESET_N;
input  FAB_PLL_LOCK;
input  FAB_RXACTIVE;
input  FAB_RXERROR;
input  FAB_RXVALID;
input  FAB_RXVALIDH;
input  FAB_SESSEND;
input  FAB_TXREADY;
input  FAB_VBUSVALID;
input  [7:0] FAB_VSTATUS;
input  [7:0] FAB_XDATAIN;
input  GTX_CLKPF;
input  I2C0_BCLK;
input  I2C0_SCL_F2H_SCP;
input  I2C0_SDA_F2H_SCP;
input  I2C1_BCLK;
input  I2C1_SCL_F2H_SCP;
input  I2C1_SDA_F2H_SCP;
input  MDIF;
input  MGPIO0A_F2H_GPIN;
input  MGPIO10A_F2H_GPIN;
input  MGPIO11A_F2H_GPIN;
input  MGPIO11B_F2H_GPIN;
input  MGPIO12A_F2H_GPIN;
input  MGPIO13A_F2H_GPIN;
input  MGPIO14A_F2H_GPIN;
input  MGPIO15A_F2H_GPIN;
input  MGPIO16A_F2H_GPIN;
input  MGPIO17B_F2H_GPIN;
input  MGPIO18B_F2H_GPIN;
input  MGPIO19B_F2H_GPIN;
input  MGPIO1A_F2H_GPIN;
input  MGPIO20B_F2H_GPIN;
input  MGPIO21B_F2H_GPIN;
input  MGPIO22B_F2H_GPIN;
input  MGPIO24B_F2H_GPIN;
input  MGPIO25B_F2H_GPIN;
input  MGPIO26B_F2H_GPIN;
input  MGPIO27B_F2H_GPIN;
input  MGPIO28B_F2H_GPIN;
input  MGPIO29B_F2H_GPIN;
input  MGPIO2A_F2H_GPIN;
input  MGPIO30B_F2H_GPIN;
input  MGPIO31B_F2H_GPIN;
input  MGPIO3A_F2H_GPIN;
input  MGPIO4A_F2H_GPIN;
input  MGPIO5A_F2H_GPIN;
input  MGPIO6A_F2H_GPIN;
input  MGPIO7A_F2H_GPIN;
input  MGPIO8A_F2H_GPIN;
input  MGPIO9A_F2H_GPIN;
input  MMUART0_CTS_F2H_SCP;
input  MMUART0_DCD_F2H_SCP;
input  MMUART0_DSR_F2H_SCP;
input  MMUART0_DTR_F2H_SCP;
input  MMUART0_RI_F2H_SCP;
input  MMUART0_RTS_F2H_SCP;
input  MMUART0_RXD_F2H_SCP;
input  MMUART0_SCK_F2H_SCP;
input  MMUART0_TXD_F2H_SCP;
input  MMUART1_CTS_F2H_SCP;
input  MMUART1_DCD_F2H_SCP;
input  MMUART1_DSR_F2H_SCP;
input  MMUART1_RI_F2H_SCP;
input  MMUART1_RTS_F2H_SCP;
input  MMUART1_RXD_F2H_SCP;
input  MMUART1_SCK_F2H_SCP;
input  MMUART1_TXD_F2H_SCP;
input  [31:0] PER2_FABRIC_PRDATA;
input  PER2_FABRIC_PREADY;
input  PER2_FABRIC_PSLVERR;
input  [9:0] RCGF;
input  RX_CLKPF;
input  RX_DVF;
input  RX_ERRF;
input  RX_EV;
input  [7:0] RXDF;
input  SLEEPHOLDREQ;
input  SMBALERT_NI0;
input  SMBALERT_NI1;
input  SMBSUS_NI0;
input  SMBSUS_NI1;
input  SPI0_CLK_IN;
input  SPI0_SDI_F2H_SCP;
input  SPI0_SDO_F2H_SCP;
input  SPI0_SS0_F2H_SCP;
input  SPI0_SS1_F2H_SCP;
input  SPI0_SS2_F2H_SCP;
input  SPI0_SS3_F2H_SCP;
input  SPI1_CLK_IN;
input  SPI1_SDI_F2H_SCP;
input  SPI1_SDO_F2H_SCP;
input  SPI1_SS0_F2H_SCP;
input  SPI1_SS1_F2H_SCP;
input  SPI1_SS2_F2H_SCP;
input  SPI1_SS3_F2H_SCP;
input  TX_CLKPF;
input  USER_MSS_GPIO_RESET_N;
input  USER_MSS_RESET_N;
input  XCLK_FAB;
input  CLK_MDDR_APB;
input  [31:0] F_ARADDR_HADDR1;
input  [1:0] F_ARBURST_HTRANS1;
input  [3:0] F_ARID_HSEL1;
input  [3:0] F_ARLEN_HBURST1;
input  [1:0] F_ARLOCK_HMASTLOCK1;
input  [1:0] F_ARSIZE_HSIZE1;
input  F_ARVALID_HWRITE1;
input  [31:0] F_AWADDR_HADDR0;
input  [1:0] F_AWBURST_HTRANS0;
input  [3:0] F_AWID_HSEL0;
input  [3:0] F_AWLEN_HBURST0;
input  [1:0] F_AWLOCK_HMASTLOCK0;
input  [1:0] F_AWSIZE_HSIZE0;
input  F_AWVALID_HWRITE0;
input  F_BREADY;
input  F_RMW_AXI;
input  F_RREADY;
input  [63:0] F_WDATA_HWDATA01;
input  [3:0] F_WID_HREADY01;
input  F_WLAST;
input  [7:0] F_WSTRB;
input  F_WVALID;
input  FPGA_MDDR_ARESET_N;
input  [10:2] MDDR_FABRIC_PADDR;
input  MDDR_FABRIC_PENABLE;
input  MDDR_FABRIC_PSEL;
input  [15:0] MDDR_FABRIC_PWDATA;
input  MDDR_FABRIC_PWRITE;
input  PRESET_N;
input  CAN_RXBUS_USBA_DATA1_MGPIO3A_IN;
input  CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN;
input  CAN_TXBUS_USBA_DATA0_MGPIO2A_IN;
input  [4:0] DM_IN;
input  [35:0] DRAM_DQ_IN;
input  [4:0] DRAM_DQS_IN;
input  [2:0] DRAM_FIFO_WE_IN;
input  I2C0_SCL_USBC_DATA1_MGPIO31B_IN;
input  I2C0_SDA_USBC_DATA0_MGPIO30B_IN;
input  I2C1_SCL_USBA_DATA4_MGPIO1A_IN;
input  I2C1_SDA_USBA_DATA3_MGPIO0A_IN;
input  MGPIO0B_IN;
input  MGPIO10B_IN;
input  MGPIO1B_IN;
input  MGPIO25A_IN;
input  MGPIO26A_IN;
input  MGPIO27A_IN;
input  MGPIO28A_IN;
input  MGPIO29A_IN;
input  MGPIO2B_IN;
input  MGPIO30A_IN;
input  MGPIO31A_IN;
input  MGPIO3B_IN;
input  MGPIO4B_IN;
input  MGPIO5B_IN;
input  MGPIO6B_IN;
input  MGPIO7B_IN;
input  MGPIO8B_IN;
input  MGPIO9B_IN;
input  MMUART0_CTS_USBC_DATA7_MGPIO19B_IN;
input  MMUART0_DCD_MGPIO22B_IN;
input  MMUART0_DSR_MGPIO20B_IN;
input  MMUART0_DTR_USBC_DATA6_MGPIO18B_IN;
input  MMUART0_RI_MGPIO21B_IN;
input  MMUART0_RTS_USBC_DATA5_MGPIO17B_IN;
input  MMUART0_RXD_USBC_STP_MGPIO28B_IN;
input  MMUART0_SCK_USBC_NXT_MGPIO29B_IN;
input  MMUART0_TXD_USBC_DIR_MGPIO27B_IN;
input  MMUART1_CTS_MGPIO13B_IN;
input  MMUART1_DCD_MGPIO16B_IN;
input  MMUART1_DSR_MGPIO14B_IN;
input  MMUART1_DTR_MGPIO12B_IN;
input  MMUART1_RI_MGPIO15B_IN;
input  MMUART1_RTS_MGPIO11B_IN;
input  MMUART1_RXD_USBC_DATA3_MGPIO26B_IN;
input  MMUART1_SCK_USBC_DATA4_MGPIO25B_IN;
input  MMUART1_TXD_USBC_DATA2_MGPIO24B_IN;
input  RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN;
input  RGMII_MDC_RMII_MDC_IN;
input  RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN;
input  RGMII_RX_CLK_IN;
input  RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN;
input  RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN;
input  RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN;
input  RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN;
input  RGMII_RXD3_USBB_DATA4_IN;
input  RGMII_TX_CLK_IN;
input  RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN;
input  RGMII_TXD0_RMII_TXD0_USBB_DIR_IN;
input  RGMII_TXD1_RMII_TXD1_USBB_STP_IN;
input  RGMII_TXD2_USBB_DATA5_IN;
input  RGMII_TXD3_USBB_DATA6_IN;
input  SPI0_SCK_USBA_XCLK_IN;
input  SPI0_SDI_USBA_DIR_MGPIO5A_IN;
input  SPI0_SDO_USBA_STP_MGPIO6A_IN;
input  SPI0_SS0_USBA_NXT_MGPIO7A_IN;
input  SPI0_SS1_USBA_DATA5_MGPIO8A_IN;
input  SPI0_SS2_USBA_DATA6_MGPIO9A_IN;
input  SPI0_SS3_USBA_DATA7_MGPIO10A_IN;
input  SPI0_SS4_MGPIO19A_IN;
input  SPI0_SS5_MGPIO20A_IN;
input  SPI0_SS6_MGPIO21A_IN;
input  SPI0_SS7_MGPIO22A_IN;
input  SPI1_SCK_IN;
input  SPI1_SDI_MGPIO11A_IN;
input  SPI1_SDO_MGPIO12A_IN;
input  SPI1_SS0_MGPIO13A_IN;
input  SPI1_SS1_MGPIO14A_IN;
input  SPI1_SS2_MGPIO15A_IN;
input  SPI1_SS3_MGPIO16A_IN;
input  SPI1_SS4_MGPIO17A_IN;
input  SPI1_SS5_MGPIO18A_IN;
input  SPI1_SS6_MGPIO23A_IN;
input  SPI1_SS7_MGPIO24A_IN;
input  USBC_XCLK_IN;
input  USBD_DATA0_IN;
input  USBD_DATA1_IN;
input  USBD_DATA2_IN;
input  USBD_DATA3_IN;
input  USBD_DATA4_IN;
input  USBD_DATA5_IN;
input  USBD_DATA6_IN;
input  USBD_DATA7_MGPIO23B_IN;
input  USBD_DIR_IN;
input  USBD_NXT_IN;
input  USBD_STP_IN;
input  USBD_XCLK_IN;
output CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT;
output CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT;
output CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT;
output [15:0] DRAM_ADDR;
output [2:0] DRAM_BA;
output DRAM_CASN;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CSN;
output [4:0] DRAM_DM_RDQS_OUT;
output [35:0] DRAM_DQ_OUT;
output [4:0] DRAM_DQS_OUT;
output [2:0] DRAM_FIFO_WE_OUT;
output DRAM_ODT;
output DRAM_RASN;
output DRAM_RSTN;
output DRAM_WEN;
output I2C0_SCL_USBC_DATA1_MGPIO31B_OUT;
output I2C0_SDA_USBC_DATA0_MGPIO30B_OUT;
output I2C1_SCL_USBA_DATA4_MGPIO1A_OUT;
output I2C1_SDA_USBA_DATA3_MGPIO0A_OUT;
output MGPIO0B_OUT;
output MGPIO10B_OUT;
output MGPIO1B_OUT;
output MGPIO25A_OUT;
output MGPIO26A_OUT;
output MGPIO27A_OUT;
output MGPIO28A_OUT;
output MGPIO29A_OUT;
output MGPIO2B_OUT;
output MGPIO30A_OUT;
output MGPIO31A_OUT;
output MGPIO3B_OUT;
output MGPIO4B_OUT;
output MGPIO5B_OUT;
output MGPIO6B_OUT;
output MGPIO7B_OUT;
output MGPIO8B_OUT;
output MGPIO9B_OUT;
output MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT;
output MMUART0_DCD_MGPIO22B_OUT;
output MMUART0_DSR_MGPIO20B_OUT;
output MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT;
output MMUART0_RI_MGPIO21B_OUT;
output MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT;
output MMUART0_RXD_USBC_STP_MGPIO28B_OUT;
output MMUART0_SCK_USBC_NXT_MGPIO29B_OUT;
output MMUART0_TXD_USBC_DIR_MGPIO27B_OUT;
output MMUART1_CTS_MGPIO13B_OUT;
output MMUART1_DCD_MGPIO16B_OUT;
output MMUART1_DSR_MGPIO14B_OUT;
output MMUART1_DTR_MGPIO12B_OUT;
output MMUART1_RI_MGPIO15B_OUT;
output MMUART1_RTS_MGPIO11B_OUT;
output MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT;
output MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT;
output MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT;
output RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT;
output RGMII_MDC_RMII_MDC_OUT;
output RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT;
output RGMII_RX_CLK_OUT;
output RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT;
output RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT;
output RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT;
output RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT;
output RGMII_RXD3_USBB_DATA4_OUT;
output RGMII_TX_CLK_OUT;
output RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT;
output RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT;
output RGMII_TXD1_RMII_TXD1_USBB_STP_OUT;
output RGMII_TXD2_USBB_DATA5_OUT;
output RGMII_TXD3_USBB_DATA6_OUT;
output SPI0_SCK_USBA_XCLK_OUT;
output SPI0_SDI_USBA_DIR_MGPIO5A_OUT;
output SPI0_SDO_USBA_STP_MGPIO6A_OUT;
output SPI0_SS0_USBA_NXT_MGPIO7A_OUT;
output SPI0_SS1_USBA_DATA5_MGPIO8A_OUT;
output SPI0_SS2_USBA_DATA6_MGPIO9A_OUT;
output SPI0_SS3_USBA_DATA7_MGPIO10A_OUT;
output SPI0_SS4_MGPIO19A_OUT;
output SPI0_SS5_MGPIO20A_OUT;
output SPI0_SS6_MGPIO21A_OUT;
output SPI0_SS7_MGPIO22A_OUT;
output SPI1_SCK_OUT;
output SPI1_SDI_MGPIO11A_OUT;
output SPI1_SDO_MGPIO12A_OUT;
output SPI1_SS0_MGPIO13A_OUT;
output SPI1_SS1_MGPIO14A_OUT;
output SPI1_SS2_MGPIO15A_OUT;
output SPI1_SS3_MGPIO16A_OUT;
output SPI1_SS4_MGPIO17A_OUT;
output SPI1_SS5_MGPIO18A_OUT;
output SPI1_SS6_MGPIO23A_OUT;
output SPI1_SS7_MGPIO24A_OUT;
output USBC_XCLK_OUT;
output USBD_DATA0_OUT;
output USBD_DATA1_OUT;
output USBD_DATA2_OUT;
output USBD_DATA3_OUT;
output USBD_DATA4_OUT;
output USBD_DATA5_OUT;
output USBD_DATA6_OUT;
output USBD_DATA7_MGPIO23B_OUT;
output USBD_DIR_OUT;
output USBD_NXT_OUT;
output USBD_STP_OUT;
output USBD_XCLK_OUT;
output CAN_RXBUS_USBA_DATA1_MGPIO3A_OE;
output CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE;
output CAN_TXBUS_USBA_DATA0_MGPIO2A_OE;
output [4:0] DM_OE;
output [35:0] DRAM_DQ_OE;
output [4:0] DRAM_DQS_OE;
output I2C0_SCL_USBC_DATA1_MGPIO31B_OE;
output I2C0_SDA_USBC_DATA0_MGPIO30B_OE;
output I2C1_SCL_USBA_DATA4_MGPIO1A_OE;
output I2C1_SDA_USBA_DATA3_MGPIO0A_OE;
output MGPIO0B_OE;
output MGPIO10B_OE;
output MGPIO1B_OE;
output MGPIO25A_OE;
output MGPIO26A_OE;
output MGPIO27A_OE;
output MGPIO28A_OE;
output MGPIO29A_OE;
output MGPIO2B_OE;
output MGPIO30A_OE;
output MGPIO31A_OE;
output MGPIO3B_OE;
output MGPIO4B_OE;
output MGPIO5B_OE;
output MGPIO6B_OE;
output MGPIO7B_OE;
output MGPIO8B_OE;
output MGPIO9B_OE;
output MMUART0_CTS_USBC_DATA7_MGPIO19B_OE;
output MMUART0_DCD_MGPIO22B_OE;
output MMUART0_DSR_MGPIO20B_OE;
output MMUART0_DTR_USBC_DATA6_MGPIO18B_OE;
output MMUART0_RI_MGPIO21B_OE;
output MMUART0_RTS_USBC_DATA5_MGPIO17B_OE;
output MMUART0_RXD_USBC_STP_MGPIO28B_OE;
output MMUART0_SCK_USBC_NXT_MGPIO29B_OE;
output MMUART0_TXD_USBC_DIR_MGPIO27B_OE;
output MMUART1_CTS_MGPIO13B_OE;
output MMUART1_DCD_MGPIO16B_OE;
output MMUART1_DSR_MGPIO14B_OE;
output MMUART1_DTR_MGPIO12B_OE;
output MMUART1_RI_MGPIO15B_OE;
output MMUART1_RTS_MGPIO11B_OE;
output MMUART1_RXD_USBC_DATA3_MGPIO26B_OE;
output MMUART1_SCK_USBC_DATA4_MGPIO25B_OE;
output MMUART1_TXD_USBC_DATA2_MGPIO24B_OE;
output RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE;
output RGMII_MDC_RMII_MDC_OE;
output RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE;
output RGMII_RX_CLK_OE;
output RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE;
output RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE;
output RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE;
output RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE;
output RGMII_RXD3_USBB_DATA4_OE;
output RGMII_TX_CLK_OE;
output RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE;
output RGMII_TXD0_RMII_TXD0_USBB_DIR_OE;
output RGMII_TXD1_RMII_TXD1_USBB_STP_OE;
output RGMII_TXD2_USBB_DATA5_OE;
output RGMII_TXD3_USBB_DATA6_OE;
output SPI0_SCK_USBA_XCLK_OE;
output SPI0_SDI_USBA_DIR_MGPIO5A_OE;
output SPI0_SDO_USBA_STP_MGPIO6A_OE;
output SPI0_SS0_USBA_NXT_MGPIO7A_OE;
output SPI0_SS1_USBA_DATA5_MGPIO8A_OE;
output SPI0_SS2_USBA_DATA6_MGPIO9A_OE;
output SPI0_SS3_USBA_DATA7_MGPIO10A_OE;
output SPI0_SS4_MGPIO19A_OE;
output SPI0_SS5_MGPIO20A_OE;
output SPI0_SS6_MGPIO21A_OE;
output SPI0_SS7_MGPIO22A_OE;
output SPI1_SCK_OE;
output SPI1_SDI_MGPIO11A_OE;
output SPI1_SDO_MGPIO12A_OE;
output SPI1_SS0_MGPIO13A_OE;
output SPI1_SS1_MGPIO14A_OE;
output SPI1_SS2_MGPIO15A_OE;
output SPI1_SS3_MGPIO16A_OE;
output SPI1_SS4_MGPIO17A_OE;
output SPI1_SS5_MGPIO18A_OE;
output SPI1_SS6_MGPIO23A_OE;
output SPI1_SS7_MGPIO24A_OE;
output USBC_XCLK_OE;
output USBD_DATA0_OE;
output USBD_DATA1_OE;
output USBD_DATA2_OE;
output USBD_DATA3_OE;
output USBD_DATA4_OE;
output USBD_DATA5_OE;
output USBD_DATA6_OE;
output USBD_DATA7_MGPIO23B_OE;
output USBD_DIR_OE;
output USBD_NXT_OE;
output USBD_STP_OE;
output USBD_XCLK_OE;

    parameter INIT = 'h0 ;
    parameter ACT_UBITS = 'hFFFFFFFFFFFFFF ;
    parameter MEMORYFILE = "" ;
    parameter RTC_MAIN_XTL_FREQ = 0.0 ;
    parameter RTC_MAIN_XTL_MODE = "1" ;
    parameter DDR_CLK_FREQ = 0.0 ;
    
endmodule


module CMD_Decode(
       CMD_Decode_0_w_xfer_size,
       WS_d1,
       CMD_Decode_0_r_xfer_size_i_0,
       CMD_Decode_0_r_xfer_size,
       CMD_Decode_0_r_xfer_sizeoi,
       CMD_Decode_0_w_xfer_sizeoi_0,
       MDDR_TA_0_INIT_DONE,
       MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK,
       MDDR_TA_0_GPIO_7_M2F,
       MDDR_TA_0_GPIO_2_M2F,
       MDDR_TA_0_GPIO_3_M2F,
       MDDR_TA_0_GPIO_4_M2F,
       MDDR_TA_0_GPIO_0_M2F,
       MDDR_TA_0_GPIO_1_M2F,
       MDDR_TA_0_GPIO_5_M2F,
       MDDR_TA_0_GPIO_6_M2F,
       read_start_c,
       write_start_c
    );
output [8:4] CMD_Decode_0_w_xfer_size;
output [2:0] WS_d1;
output [4:4] CMD_Decode_0_r_xfer_size_i_0;
output [8:4] CMD_Decode_0_r_xfer_size;
output [8:4] CMD_Decode_0_r_xfer_sizeoi;
output CMD_Decode_0_w_xfer_sizeoi_0;
input  MDDR_TA_0_INIT_DONE;
input  MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK;
input  MDDR_TA_0_GPIO_7_M2F;
input  MDDR_TA_0_GPIO_2_M2F;
input  MDDR_TA_0_GPIO_3_M2F;
input  MDDR_TA_0_GPIO_4_M2F;
input  MDDR_TA_0_GPIO_0_M2F;
input  MDDR_TA_0_GPIO_1_M2F;
input  MDDR_TA_0_GPIO_5_M2F;
input  MDDR_TA_0_GPIO_6_M2F;
output read_start_c;
output write_start_c;

    wire \RS_d1[2]_net_1 , VCC_net_1, GND_net_1, 
        \CMD_Decode_0_w_xfer_sizeoi[5] , w_xfer_size19_net_1, 
        w_xfer_size20_net_1, w_xfer_size21_net_1, \WR_d1[0]_net_1 , 
        \WR_d1[1]_net_1 , \RS_d1[0]_net_1 , \RS_d1[1]_net_1 , 
        write_start11_net_1, write_start10_net_1, 
        \CMD_Decode_0_r_xfer_size_i_0_reti[4] ;
    
    SLE \r_xfer_size_1[5]  (.D(CMD_Decode_0_r_xfer_sizeoi[5]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(CMD_Decode_0_r_xfer_size[5]));
    SLE \w_xfer_size_1[4]  (.D(CMD_Decode_0_w_xfer_sizeoi_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(CMD_Decode_0_w_xfer_size[4]));
    CFG3 #( .INIT(8'h02) )  r_xfer_size14 (.A(\RS_d1[2]_net_1 ), .B(
        \RS_d1[1]_net_1 ), .C(\RS_d1[0]_net_1 ), .Y(
        CMD_Decode_0_r_xfer_sizeoi[7]));
    CFG3 #( .INIT(8'h10) )  r_xfer_size11 (.A(\RS_d1[2]_net_1 ), .B(
        \RS_d1[1]_net_1 ), .C(\RS_d1[0]_net_1 ), .Y(
        CMD_Decode_0_r_xfer_sizeoi[4]));
    CFG3 #( .INIT(8'h20) )  w_xfer_size21 (.A(WS_d1[2]), .B(WS_d1[1]), 
        .C(WS_d1[0]), .Y(w_xfer_size21_net_1));
    SLE r_xfer_size_1_ret_3 (.D(\CMD_Decode_0_r_xfer_size_i_0_reti[4] )
        , .CLK(MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), 
        .ALn(MDDR_TA_0_INIT_DONE), .ADn(GND_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CMD_Decode_0_r_xfer_size_i_0[4]));
    CFG3 #( .INIT(8'h04) )  w_xfer_size18 (.A(WS_d1[2]), .B(WS_d1[1]), 
        .C(WS_d1[0]), .Y(\CMD_Decode_0_w_xfer_sizeoi[5] ));
    SLE \r_xfer_size_1[8]  (.D(CMD_Decode_0_r_xfer_sizeoi[8]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(CMD_Decode_0_r_xfer_size[8]));
    VCC VCC (.Y(VCC_net_1));
    SLE \RS_d1[2]  (.D(MDDR_TA_0_GPIO_7_M2F), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\RS_d1[2]_net_1 ));
    SLE \w_xfer_size_1[5]  (.D(\CMD_Decode_0_w_xfer_sizeoi[5] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(CMD_Decode_0_w_xfer_size[5]));
    SLE \r_xfer_size_1[4]  (.D(CMD_Decode_0_r_xfer_sizeoi[4]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(CMD_Decode_0_r_xfer_size[4]));
    SLE \WS_d1[2]  (.D(MDDR_TA_0_GPIO_4_M2F), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(WS_d1[2]));
    CFG3 #( .INIT(8'hEF) )  r_xfer_size11_i (.A(\RS_d1[2]_net_1 ), .B(
        \RS_d1[1]_net_1 ), .C(\RS_d1[0]_net_1 ), .Y(
        \CMD_Decode_0_r_xfer_size_i_0_reti[4] ));
    SLE read_start (.D(write_start11_net_1), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(read_start_c));
    SLE \WR_d1[1]  (.D(MDDR_TA_0_GPIO_1_M2F), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WR_d1[1]_net_1 ));
    CFG3 #( .INIT(8'h10) )  w_xfer_size17 (.A(WS_d1[2]), .B(WS_d1[1]), 
        .C(WS_d1[0]), .Y(CMD_Decode_0_w_xfer_sizeoi_0));
    CFG3 #( .INIT(8'h40) )  w_xfer_size19 (.A(WS_d1[2]), .B(WS_d1[1]), 
        .C(WS_d1[0]), .Y(w_xfer_size19_net_1));
    GND GND (.Y(GND_net_1));
    SLE \WS_d1[1]  (.D(MDDR_TA_0_GPIO_3_M2F), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(WS_d1[1]));
    SLE \r_xfer_size_1[6]  (.D(CMD_Decode_0_r_xfer_sizeoi[6]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(CMD_Decode_0_r_xfer_size[6]));
    SLE \RS_d1[0]  (.D(MDDR_TA_0_GPIO_5_M2F), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\RS_d1[0]_net_1 ));
    SLE \RS_d1[1]  (.D(MDDR_TA_0_GPIO_6_M2F), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\RS_d1[1]_net_1 ));
    SLE \r_xfer_size_1[7]  (.D(CMD_Decode_0_r_xfer_sizeoi[7]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(CMD_Decode_0_r_xfer_size[7]));
    SLE write_start (.D(write_start10_net_1), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(write_start_c));
    SLE \WR_d1[0]  (.D(MDDR_TA_0_GPIO_0_M2F), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WR_d1[0]_net_1 ));
    SLE \WS_d1[0]  (.D(MDDR_TA_0_GPIO_2_M2F), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(WS_d1[0]));
    SLE \w_xfer_size_1[8]  (.D(w_xfer_size21_net_1), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(CMD_Decode_0_w_xfer_size[8]));
    CFG3 #( .INIT(8'h02) )  w_xfer_size20 (.A(WS_d1[2]), .B(WS_d1[1]), 
        .C(WS_d1[0]), .Y(w_xfer_size20_net_1));
    SLE \w_xfer_size_1[6]  (.D(w_xfer_size19_net_1), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(CMD_Decode_0_w_xfer_size[6]));
    CFG3 #( .INIT(8'h20) )  r_xfer_size15 (.A(\RS_d1[2]_net_1 ), .B(
        \RS_d1[1]_net_1 ), .C(\RS_d1[0]_net_1 ), .Y(
        CMD_Decode_0_r_xfer_sizeoi[8]));
    CFG3 #( .INIT(8'h40) )  r_xfer_size13 (.A(\RS_d1[2]_net_1 ), .B(
        \RS_d1[1]_net_1 ), .C(\RS_d1[0]_net_1 ), .Y(
        CMD_Decode_0_r_xfer_sizeoi[6]));
    SLE \w_xfer_size_1[7]  (.D(w_xfer_size20_net_1), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(CMD_Decode_0_w_xfer_size[7]));
    CFG3 #( .INIT(8'h04) )  r_xfer_size12 (.A(\RS_d1[2]_net_1 ), .B(
        \RS_d1[1]_net_1 ), .C(\RS_d1[0]_net_1 ), .Y(
        CMD_Decode_0_r_xfer_sizeoi[5]));
    CFG2 #( .INIT(4'h4) )  write_start11 (.A(\WR_d1[0]_net_1 ), .B(
        \WR_d1[1]_net_1 ), .Y(write_start11_net_1));
    CFG2 #( .INIT(4'h2) )  write_start10 (.A(\WR_d1[0]_net_1 ), .B(
        \WR_d1[1]_net_1 ), .Y(write_start10_net_1));
    
endmodule


module AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z1(
       AHB_IF_0_BIF_1_HWDATA,
       AXI_IF_0_AHB_DATA,
       AXI_IF_0_AHB_ADDR,
       AHB_IF_0_BIF_1_HTRANS,
       HTRANS_1_fast,
       AHB_IF_0_BIF_1_HADDR,
       AXI_IF_0_AHB_ADDR_reto_0_0,
       AXI_IF_0_AHB_ADDR_reto_0_4,
       AXI_IF_0_AHB_ADDR_reto_0_5,
       AXI_IF_0_AHB_ADDR_reto_0_11,
       AXI_IF_0_AHB_ADDR_reto_0_23,
       AXI_IF_0_AHB_ADDR_reto_0_24,
       AXI_IF_0_AHB_ADDR_reto_0_25,
       AXI_IF_0_AHB_ADDR_reto_0_22,
       AXI_IF_0_AHB_ADDR_reto_0_19,
       AXI_IF_0_AHB_ADDR_reto_0_18,
       AXI_IF_0_AHB_ADDR_reto_0_17,
       MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK,
       MDDR_TA_0_INIT_DONE,
       N_178_i_0,
       AHB_ADDR_6_cry_2_0_Y,
       AHB_IF_0_BIF_1_HWRITE,
       AHB_IF_0_AHB_BUSY,
       HREADY_M_iv_i_0,
       AXI_IF_0_WRITE_AHB,
       HREADY_M_iv
    );
output [13:0] AHB_IF_0_BIF_1_HWDATA;
input  [13:0] AXI_IF_0_AHB_DATA;
input  [31:3] AXI_IF_0_AHB_ADDR;
output [1:1] AHB_IF_0_BIF_1_HTRANS;
output [1:1] HTRANS_1_fast;
output [31:2] AHB_IF_0_BIF_1_HADDR;
input  AXI_IF_0_AHB_ADDR_reto_0_0;
input  AXI_IF_0_AHB_ADDR_reto_0_4;
input  AXI_IF_0_AHB_ADDR_reto_0_5;
input  AXI_IF_0_AHB_ADDR_reto_0_11;
input  AXI_IF_0_AHB_ADDR_reto_0_23;
input  AXI_IF_0_AHB_ADDR_reto_0_24;
input  AXI_IF_0_AHB_ADDR_reto_0_25;
input  AXI_IF_0_AHB_ADDR_reto_0_22;
input  AXI_IF_0_AHB_ADDR_reto_0_19;
input  AXI_IF_0_AHB_ADDR_reto_0_18;
input  AXI_IF_0_AHB_ADDR_reto_0_17;
input  MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK;
input  MDDR_TA_0_INIT_DONE;
output N_178_i_0;
input  AHB_ADDR_6_cry_2_0_Y;
output AHB_IF_0_BIF_1_HWRITE;
output AHB_IF_0_AHB_BUSY;
input  HREADY_M_iv_i_0;
input  AXI_IF_0_WRITE_AHB;
input  HREADY_M_iv;

    wire \HWDATA_int[1]_net_1 , VCC_net_1, HWDATA_int_0_sqmuxa_net_1, 
        GND_net_1, \HWDATA_int[2]_net_1 , \HWDATA_int[3]_net_1 , 
        \HWDATA_int[4]_net_1 , \HWDATA_int[5]_net_1 , 
        \HWDATA_int[6]_net_1 , \HWDATA_int[7]_net_1 , 
        \HWDATA_int[8]_net_1 , \HWDATA_int[9]_net_1 , 
        \HWDATA_int[10]_net_1 , \HWDATA_int[11]_net_1 , 
        \HWDATA_int[12]_net_1 , \HWDATA_int[13]_net_1 , 
        \HWDATA_int[0]_net_1 , HWDATA_1_sqmuxa, \HADDR_9[28]_net_1 , 
        \HADDR_9[31]_net_1 , \HADDR_int[19]_net_1 , 
        \HADDR_int[20]_net_1 , \HADDR_int[21]_net_1 , 
        \HADDR_int[22]_net_1 , \HADDR_int[23]_net_1 , 
        \HADDR_int[24]_net_1 , \HADDR_int[25]_net_1 , 
        \HADDR_int[26]_net_1 , \HADDR_int[27]_net_1 , 
        \HADDR_int[28]_net_1 , \HADDR_int[29]_net_1 , 
        \HADDR_int[30]_net_1 , \HADDR_int[31]_net_1 , 
        \HADDR_int[4]_net_1 , \HADDR_int[5]_net_1 , 
        \HADDR_int[6]_net_1 , \HADDR_int[7]_net_1 , 
        \HADDR_int[8]_net_1 , \HADDR_int[9]_net_1 , 
        \HADDR_int[10]_net_1 , \HADDR_int[11]_net_1 , 
        \HADDR_int[12]_net_1 , \HADDR_int[13]_net_1 , 
        \HADDR_int[14]_net_1 , \HADDR_int[15]_net_1 , 
        \HADDR_int[16]_net_1 , \HADDR_int[17]_net_1 , 
        \HADDR_int[18]_net_1 , \HADDR_int[2]_net_1 , 
        \HADDR_int[3]_net_1 , HWDATA_1_sqmuxa_i_0, 
        un1_ahb_fsm_current_state_7_0_net_1, N_188_i_0, N_182_i_0, 
        N_171_i_0, \ahb_fsm_current_state[0]_net_1 , 
        \ahb_fsm_current_state_ns[0]_net_1 , 
        \ahb_fsm_current_state[1]_net_1 , N_163_i_0, 
        \ahb_fsm_current_state[2]_net_1 , 
        \ahb_fsm_current_state_ns[2]_net_1 , 
        \ahb_fsm_current_state[3]_net_1 , \HADDR_int_reto[13] , 
        \HADDR_int_reto[25] , \HADDR_int_reto[19] , 
        \HADDR_int_reto[26] , \HADDR_int_reto[21] , 
        \HADDR_int_reto[27] , \HADDR_int_reto[20] , 
        \HADDR_int_reto[2] , \HADDR_int_reto[24] , \HADDR_int_reto[7] , 
        \HADDR_int_reto[6] , \HADDR_int_reto[18] , 
        HWDATA_1_sqmuxa_reto, \ahb_fsm_current_state_reto[0] , 
        \AXI_IF_0_AHB_ADDR_reto_0[18] , \HADDR_int_reto[17] , 
        \AXI_IF_0_AHB_ADDR_reto_0[17] , \HADDR_int_reto[5] , 
        \AXI_IF_0_AHB_ADDR_reto_0[5] , \HADDR_int_reto[4] , 
        \AXI_IF_0_AHB_ADDR_reto_0[4] , \HADDR_int_reto[16] , 
        \AXI_IF_0_AHB_ADDR_reto_0[16] , \HADDR_int_reto[8] , 
        \AXI_IF_0_AHB_ADDR_reto_0[8] , \HADDR_int_reto[23] , 
        \AXI_IF_0_AHB_ADDR_reto_0[23] , \HADDR_int_reto[22] , 
        \AXI_IF_0_AHB_ADDR_reto_0[22] , \HADDR_int_reto[12] , 
        \AXI_IF_0_AHB_ADDR_reto_0[12] , \HADDR_int_reto[14] , 
        HWDATA_1_sqmuxa_reto_0, \ahb_fsm_current_state_reto_0[0] , 
        \AXI_IF_0_AHB_ADDR_reto_0[14] , \HADDR_int_reto[15] , 
        \AXI_IF_0_AHB_ADDR_reto_0[15] , \HADDR_int_reto[3] , 
        \AXI_IF_0_AHB_ADDR_reto_0[3] , \HADDR_int_reto[10] , 
        \AXI_IF_0_AHB_ADDR_reto_0[10] , \HADDR_int_reto[9] , 
        \AXI_IF_0_AHB_ADDR_reto_0[9] , \HADDR_int_reto[11] , 
        \AXI_IF_0_AHB_ADDR_reto_0[11] , \HADDR_int_reto[29] , 
        HWDATA_1_sqmuxa_reto_1, \ahb_fsm_current_state_reto_1[0] , 
        \AXI_IF_0_AHB_ADDR_reto_0[29] , \HADDR_9[30]_net_1 ;
    
    SLE \HADDR_int[18]  (.D(AXI_IF_0_AHB_ADDR[18]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[18]_net_1 ));
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[18]  (.A(
        \ahb_fsm_current_state_reto[0] ), .B(HWDATA_1_sqmuxa_reto), .C(
        \AXI_IF_0_AHB_ADDR_reto_0[18] ), .D(\HADDR_int_reto[18] ), .Y(
        AHB_IF_0_BIF_1_HADDR[18]));
    SLE HADDR_ret_88 (.D(\HADDR_int[11]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[11] ));
    SLE \HWDATA_int[0]  (.D(AXI_IF_0_AHB_DATA[0]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HWDATA_int[0]_net_1 ));
    SLE \HADDR_int[12]  (.D(AXI_IF_0_AHB_ADDR[12]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[12]_net_1 ));
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[17]  (.A(
        \ahb_fsm_current_state_reto_0[0] ), .B(HWDATA_1_sqmuxa_reto_0), 
        .C(\AXI_IF_0_AHB_ADDR_reto_0[17] ), .D(\HADDR_int_reto[17] ), 
        .Y(AHB_IF_0_BIF_1_HADDR[17]));
    SLE HADDR_ret_6 (.D(\HADDR_int[19]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[19] ));
    SLE \HWDATA[5]  (.D(\HWDATA_int[5]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(HWDATA_1_sqmuxa), 
        .ALn(MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(AHB_IF_0_BIF_1_HWDATA[5]));
    SLE \ahb_fsm_current_state[3]  (.D(
        \ahb_fsm_current_state[2]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(HREADY_M_iv_i_0), 
        .ALn(MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \ahb_fsm_current_state[3]_net_1 ));
    SLE HADDR_ret_76 (.D(\HADDR_int[3]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[3] ));
    SLE \HADDR_int[13]  (.D(AXI_IF_0_AHB_ADDR[13]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[13]_net_1 ));
    CFG4 #( .INIT(16'h01AB) )  \ahb_fsm_current_state_ns[0]  (.A(
        \ahb_fsm_current_state[3]_net_1 ), .B(AXI_IF_0_WRITE_AHB), .C(
        un1_ahb_fsm_current_state_7_0_net_1), .D(HREADY_M_iv), .Y(
        \ahb_fsm_current_state_ns[0]_net_1 ));
    SLE \HWDATA_int[9]  (.D(AXI_IF_0_AHB_DATA[9]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HWDATA_int[9]_net_1 ));
    SLE HADDR_ret_36 (.D(\HADDR_int[17]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[17] ));
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[26]  (.A(
        \ahb_fsm_current_state_reto[0] ), .B(HWDATA_1_sqmuxa_reto), .C(
        AXI_IF_0_AHB_ADDR_reto_0_24), .D(\HADDR_int_reto[26] ), .Y(
        AHB_IF_0_BIF_1_HADDR[26]));
    SLE HADDR_ret_9 (.D(\HADDR_int[26]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[26] ));
    SLE \HWDATA_int[7]  (.D(AXI_IF_0_AHB_DATA[7]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HWDATA_int[7]_net_1 ));
    SLE HADDR_ret_84 (.D(\HADDR_int[9]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[9] ));
    SLE \HWDATA[2]  (.D(\HWDATA_int[2]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(HWDATA_1_sqmuxa), 
        .ALn(MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(AHB_IF_0_BIF_1_HWDATA[2]));
    SLE HADDR_ret_0 (.D(\HADDR_int[18]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[18] ));
    SLE \HADDR_int[26]  (.D(AXI_IF_0_AHB_ADDR[26]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[26]_net_1 ));
    CFG4 #( .INIT(16'h000B) )  \ahb_fsm_current_state_RNIMSRC[1]  (.A(
        AXI_IF_0_WRITE_AHB), .B(\ahb_fsm_current_state[0]_net_1 ), .C(
        \ahb_fsm_current_state[1]_net_1 ), .D(
        \ahb_fsm_current_state[3]_net_1 ), .Y(N_178_i_0));
    CFG2 #( .INIT(4'h8) )  \ahb_fsm_current_state_RNO[1]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(AXI_IF_0_WRITE_AHB), .Y(
        N_163_i_0));
    SLE \HADDR_int[2]  (.D(AHB_ADDR_6_cry_2_0_Y), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[2]_net_1 ));
    SLE \ahb_fsm_current_state[1]  (.D(N_163_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        \ahb_fsm_current_state[1]_net_1 ));
    SLE HADDR_ret_80 (.D(\HADDR_int[10]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[10] ));
    SLE HADDR_ret_33 (.D(HWDATA_1_sqmuxa), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(HWDATA_1_sqmuxa_reto));
    SLE \HWDATA[3]  (.D(\HWDATA_int[3]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(HWDATA_1_sqmuxa), 
        .ALn(MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(AHB_IF_0_BIF_1_HWDATA[3]));
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[23]  (.A(
        \ahb_fsm_current_state_reto_0[0] ), .B(HWDATA_1_sqmuxa_reto_0), 
        .C(\AXI_IF_0_AHB_ADDR_reto_0[23] ), .D(\HADDR_int_reto[23] ), 
        .Y(AHB_IF_0_BIF_1_HADDR[23]));
    CFG2 #( .INIT(4'h1) )  \ahb_fsm_current_state_RNI3KV[3]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(
        \ahb_fsm_current_state[3]_net_1 ), .Y(N_171_i_0));
    SLE HADDR_ret_12 (.D(\HADDR_int[21]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[21] ));
    SLE HADDR_ret_43 (.D(AXI_IF_0_AHB_ADDR[5]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto_0[5] ));
    SLE \HWDATA_int[1]  (.D(AXI_IF_0_AHB_DATA[1]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HWDATA_int[1]_net_1 ));
    GND GND (.Y(GND_net_1));
    CFG2 #( .INIT(4'hB) )  AHB_BUSY_RNO (.A(HREADY_M_iv), .B(
        \ahb_fsm_current_state[3]_net_1 ), .Y(N_188_i_0));
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[10]  (.A(
        \ahb_fsm_current_state_reto_1[0] ), .B(HWDATA_1_sqmuxa_reto_1), 
        .C(\AXI_IF_0_AHB_ADDR_reto_0[10] ), .D(\HADDR_int_reto[10] ), 
        .Y(AHB_IF_0_BIF_1_HADDR[10]));
    SLE HADDR_ret_55 (.D(AXI_IF_0_AHB_ADDR[8]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto_0[8] ));
    CFG2 #( .INIT(4'h4) )  \ahb_fsm_current_state_RNI305F_0[2]  (.A(
        HREADY_M_iv), .B(\ahb_fsm_current_state[2]_net_1 ), .Y(
        HWDATA_1_sqmuxa));
    SLE HADDR_ret_47 (.D(AXI_IF_0_AHB_ADDR[4]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto_0[4] ));
    SLE \HADDR[28]  (.D(\HADDR_9[28]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AHB_IF_0_BIF_1_HADDR[28]));
    SLE AHB_BUSY (.D(N_188_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_182_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AHB_IF_0_AHB_BUSY));
    CFG4 #( .INIT(16'h0E04) )  \HADDR_9[30]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(\HADDR_int[30]_net_1 ), 
        .C(HWDATA_1_sqmuxa), .D(AXI_IF_0_AHB_ADDR[30]), .Y(
        \HADDR_9[30]_net_1 ));
    SLE \HADDR_int[17]  (.D(AXI_IF_0_AHB_ADDR[17]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[17]_net_1 ));
    CFG2 #( .INIT(4'hB) )  \ahb_fsm_current_state_RNI305F[2]  (.A(
        HREADY_M_iv), .B(\ahb_fsm_current_state[2]_net_1 ), .Y(
        HWDATA_1_sqmuxa_i_0));
    SLE HADDR_ret_75 (.D(AXI_IF_0_AHB_ADDR[15]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto_0[15] )
        );
    SLE HADDR_ret_63 (.D(AXI_IF_0_AHB_ADDR[22]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto_0[22] )
        );
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[5]  (.A(
        \ahb_fsm_current_state_reto_0[0] ), .B(HWDATA_1_sqmuxa_reto_0), 
        .C(\AXI_IF_0_AHB_ADDR_reto_0[5] ), .D(\HADDR_int_reto[5] ), .Y(
        AHB_IF_0_BIF_1_HADDR[5]));
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[15]  (.A(
        \ahb_fsm_current_state_reto_1[0] ), .B(HWDATA_1_sqmuxa_reto_1), 
        .C(\AXI_IF_0_AHB_ADDR_reto_0[15] ), .D(\HADDR_int_reto[15] ), 
        .Y(AHB_IF_0_BIF_1_HADDR[15]));
    SLE HADDR_ret_35 (.D(AXI_IF_0_AHB_ADDR[18]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto_0[18] )
        );
    SLE \HADDR_int[31]  (.D(AXI_IF_0_AHB_ADDR[31]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[31]_net_1 ));
    VCC VCC (.Y(VCC_net_1));
    SLE \HWDATA[8]  (.D(\HWDATA_int[8]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(HWDATA_1_sqmuxa), 
        .ALn(MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(AHB_IF_0_BIF_1_HWDATA[8]));
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[29]  (.A(
        \ahb_fsm_current_state_reto_1[0] ), .B(HWDATA_1_sqmuxa_reto_1), 
        .C(\AXI_IF_0_AHB_ADDR_reto_0[29] ), .D(\HADDR_int_reto[29] ), 
        .Y(AHB_IF_0_BIF_1_HADDR[29]));
    SLE HADDR_ret_67 (.D(AXI_IF_0_AHB_ADDR[12]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto_0[12] )
        );
    SLE \HWDATA_int[5]  (.D(AXI_IF_0_AHB_DATA[5]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HWDATA_int[5]_net_1 ));
    SLE \HWDATA_int[11]  (.D(AXI_IF_0_AHB_DATA[11]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HWDATA_int[11]_net_1 ));
    CFG4 #( .INIT(16'h0E04) )  \HADDR_9[28]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(\HADDR_int[28]_net_1 ), 
        .C(HWDATA_1_sqmuxa), .D(AXI_IF_0_AHB_ADDR[28]), .Y(
        \HADDR_9[28]_net_1 ));
    SLE HADDR_ret_93 (.D(HWDATA_1_sqmuxa), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(HWDATA_1_sqmuxa_reto_1));
    SLE \HADDR_int[11]  (.D(AXI_IF_0_AHB_ADDR[11]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[11]_net_1 ));
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[27]  (.A(
        \ahb_fsm_current_state_reto[0] ), .B(HWDATA_1_sqmuxa_reto), .C(
        AXI_IF_0_AHB_ADDR_reto_0_25), .D(\HADDR_int_reto[27] ), .Y(
        AHB_IF_0_BIF_1_HADDR[27]));
    SLE \HADDR_int[19]  (.D(AXI_IF_0_AHB_ADDR[19]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[19]_net_1 ));
    SLE \HADDR_int[9]  (.D(AXI_IF_0_AHB_ADDR[9]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[9]_net_1 ));
    CFG3 #( .INIT(8'hEA) )  \ahb_fsm_current_state_ns[2]  (.A(
        \ahb_fsm_current_state[1]_net_1 ), .B(
        \ahb_fsm_current_state[2]_net_1 ), .C(HREADY_M_iv), .Y(
        \ahb_fsm_current_state_ns[2]_net_1 ));
    CFG2 #( .INIT(4'hE) )  un1_ahb_fsm_current_state_7_0 (.A(
        \ahb_fsm_current_state[2]_net_1 ), .B(
        \ahb_fsm_current_state[1]_net_1 ), .Y(
        un1_ahb_fsm_current_state_7_0_net_1));
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[14]  (.A(
        \ahb_fsm_current_state_reto_0[0] ), .B(HWDATA_1_sqmuxa_reto_0), 
        .C(\AXI_IF_0_AHB_ADDR_reto_0[14] ), .D(\HADDR_int_reto[14] ), 
        .Y(AHB_IF_0_BIF_1_HADDR[14]));
    SLE \HADDR_int[15]  (.D(AXI_IF_0_AHB_ADDR[15]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[15]_net_1 ));
    SLE \HWDATA_int[13]  (.D(AXI_IF_0_AHB_DATA[13]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HWDATA_int[13]_net_1 ));
    SLE HADDR_ret_51 (.D(AXI_IF_0_AHB_ADDR[16]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto_0[16] )
        );
    SLE \HWDATA[4]  (.D(\HWDATA_int[4]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(HWDATA_1_sqmuxa), 
        .ALn(MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(AHB_IF_0_BIF_1_HWDATA[4]));
    SLE \HADDR_int[24]  (.D(AXI_IF_0_AHB_ADDR[24]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[24]_net_1 ));
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[7]  (.A(
        \ahb_fsm_current_state_reto[0] ), .B(HWDATA_1_sqmuxa_reto), .C(
        AXI_IF_0_AHB_ADDR_reto_0_5), .D(\HADDR_int_reto[7] ), .Y(
        AHB_IF_0_BIF_1_HADDR[7]));
    SLE HADDR_ret_48 (.D(\HADDR_int[16]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[16] ));
    SLE \HWDATA[7]  (.D(\HWDATA_int[7]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(HWDATA_1_sqmuxa), 
        .ALn(MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(AHB_IF_0_BIF_1_HWDATA[7]));
    SLE \HWDATA[0]  (.D(\HWDATA_int[0]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(HWDATA_1_sqmuxa), 
        .ALn(MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(AHB_IF_0_BIF_1_HWDATA[0]));
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[11]  (.A(
        \ahb_fsm_current_state_reto_1[0] ), .B(HWDATA_1_sqmuxa_reto_1), 
        .C(\AXI_IF_0_AHB_ADDR_reto_0[11] ), .D(\HADDR_int_reto[11] ), 
        .Y(AHB_IF_0_BIF_1_HADDR[11]));
    SLE \HADDR_int[6]  (.D(AXI_IF_0_AHB_ADDR[6]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[6]_net_1 ));
    SLE HADDR_ret_27 (.D(\HADDR_int[7]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[7] ));
    SLE \HADDR_int[7]  (.D(AXI_IF_0_AHB_ADDR[7]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[7]_net_1 ));
    SLE \HWDATA[11]  (.D(\HWDATA_int[11]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(HWDATA_1_sqmuxa), 
        .ALn(MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(AHB_IF_0_BIF_1_HWDATA[11]));
    SLE HADDR_ret_71 (.D(AXI_IF_0_AHB_ADDR[14]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto_0[14] )
        );
    SLE \HWDATA_int[10]  (.D(AXI_IF_0_AHB_DATA[10]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HWDATA_int[10]_net_1 ));
    CFG4 #( .INIT(16'h0E04) )  \HADDR_9[31]  (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(\HADDR_int[31]_net_1 ), 
        .C(HWDATA_1_sqmuxa), .D(AXI_IF_0_AHB_ADDR[31]), .Y(
        \HADDR_9[31]_net_1 ));
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[3]  (.A(
        \ahb_fsm_current_state_reto_1[0] ), .B(HWDATA_1_sqmuxa_reto_1), 
        .C(\AXI_IF_0_AHB_ADDR_reto_0[3] ), .D(\HADDR_int_reto[3] ), .Y(
        AHB_IF_0_BIF_1_HADDR[3]));
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[12]  (.A(
        \ahb_fsm_current_state_reto_0[0] ), .B(HWDATA_1_sqmuxa_reto_0), 
        .C(\AXI_IF_0_AHB_ADDR_reto_0[12] ), .D(\HADDR_int_reto[12] ), 
        .Y(AHB_IF_0_BIF_1_HADDR[12]));
    SLE \HADDR_int[20]  (.D(AXI_IF_0_AHB_ADDR[20]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[20]_net_1 ));
    SLE HADDR_ret_95 (.D(AXI_IF_0_AHB_ADDR[29]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto_0[29] )
        );
    SLE HADDR_ret_34 (.D(\ahb_fsm_current_state[0]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        \ahb_fsm_current_state_reto[0] ));
    SLE \HTRANS_1[1]  (.D(HWDATA_1_sqmuxa_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_171_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AHB_IF_0_BIF_1_HTRANS[1]));
    SLE HADDR_ret_44 (.D(\HADDR_int[4]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[4] ));
    SLE \HWDATA_int[2]  (.D(AXI_IF_0_AHB_DATA[2]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HWDATA_int[2]_net_1 ));
    SLE \HADDR_int[28]  (.D(AXI_IF_0_AHB_ADDR[28]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[28]_net_1 ));
    SLE HADDR_ret_68 (.D(\HADDR_int[14]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[14] ));
    SLE HADDR_ret_70 (.D(\ahb_fsm_current_state[0]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        \ahb_fsm_current_state_reto_0[0] ));
    SLE \HADDR_int[16]  (.D(AXI_IF_0_AHB_ADDR[16]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[16]_net_1 ));
    SLE \HWDATA_int[6]  (.D(AXI_IF_0_AHB_DATA[6]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HWDATA_int[6]_net_1 ));
    SLE \HADDR_int[22]  (.D(AXI_IF_0_AHB_ADDR[22]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[22]_net_1 ));
    SLE \HWDATA[13]  (.D(\HWDATA_int[13]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(HWDATA_1_sqmuxa), 
        .ALn(MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(AHB_IF_0_BIF_1_HWDATA[13]));
    SLE HADDR_ret_30 (.D(\HADDR_int[6]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[6] ));
    SLE \HWDATA_int[8]  (.D(AXI_IF_0_AHB_DATA[8]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HWDATA_int[8]_net_1 ));
    SLE \HADDR_int[23]  (.D(AXI_IF_0_AHB_ADDR[23]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[23]_net_1 ));
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[20]  (.A(
        \ahb_fsm_current_state_reto[0] ), .B(HWDATA_1_sqmuxa_reto), .C(
        AXI_IF_0_AHB_ADDR_reto_0_18), .D(\HADDR_int_reto[20] ), .Y(
        AHB_IF_0_BIF_1_HADDR[20]));
    SLE \HADDR[31]  (.D(\HADDR_9[31]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AHB_IF_0_BIF_1_HADDR[31]));
    SLE HADDR_ret_40 (.D(\HADDR_int[5]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[5] ));
    SLE HADDR_ret_52 (.D(\HADDR_int[8]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[8] ));
    SLE HADDR_ret (.D(\HADDR_int[13]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[13] ));
    SLE \HWDATA_int[3]  (.D(AXI_IF_0_AHB_DATA[3]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HWDATA_int[3]_net_1 ));
    SLE HADDR_ret_64 (.D(\HADDR_int[12]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[12] ));
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[4]  (.A(
        \ahb_fsm_current_state_reto_0[0] ), .B(HWDATA_1_sqmuxa_reto_0), 
        .C(\AXI_IF_0_AHB_ADDR_reto_0[4] ), .D(\HADDR_int_reto[4] ), .Y(
        AHB_IF_0_BIF_1_HADDR[4]));
    SLE \HWDATA[1]  (.D(\HWDATA_int[1]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(HWDATA_1_sqmuxa), 
        .ALn(MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(AHB_IF_0_BIF_1_HWDATA[1]));
    SLE HWRITE (.D(HWDATA_1_sqmuxa_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_ahb_fsm_current_state_7_0_net_1), .ALn(MDDR_TA_0_INIT_DONE)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(AHB_IF_0_BIF_1_HWRITE));
    SLE \HADDR_int[4]  (.D(AXI_IF_0_AHB_ADDR[4]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[4]_net_1 ));
    SLE HADDR_ret_72 (.D(\HADDR_int[15]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[15] ));
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[25]  (.A(
        \ahb_fsm_current_state_reto[0] ), .B(HWDATA_1_sqmuxa_reto), .C(
        AXI_IF_0_AHB_ADDR_reto_0_23), .D(\HADDR_int_reto[25] ), .Y(
        AHB_IF_0_BIF_1_HADDR[25]));
    SLE HADDR_ret_59 (.D(AXI_IF_0_AHB_ADDR[23]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto_0[23] )
        );
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[16]  (.A(
        \ahb_fsm_current_state_reto_0[0] ), .B(HWDATA_1_sqmuxa_reto_0), 
        .C(\AXI_IF_0_AHB_ADDR_reto_0[16] ), .D(\HADDR_int_reto[16] ), 
        .Y(AHB_IF_0_BIF_1_HADDR[16]));
    SLE \ahb_fsm_current_state[2]  (.D(
        \ahb_fsm_current_state_ns[2]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        \ahb_fsm_current_state[2]_net_1 ));
    SLE HADDR_ret_91 (.D(AXI_IF_0_AHB_ADDR[11]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto_0[11] )
        );
    SLE HADDR_ret_94 (.D(\ahb_fsm_current_state[0]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        \ahb_fsm_current_state_reto_1[0] ));
    SLE HADDR_ret_60 (.D(\HADDR_int[22]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[22] ));
    CFG3 #( .INIT(8'h80) )  HWDATA_int_0_sqmuxa (.A(
        MDDR_TA_0_INIT_DONE), .B(\ahb_fsm_current_state[0]_net_1 ), .C(
        AXI_IF_0_WRITE_AHB), .Y(HWDATA_int_0_sqmuxa_net_1));
    SLE \HWDATA[12]  (.D(\HWDATA_int[12]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(HWDATA_1_sqmuxa), 
        .ALn(MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(AHB_IF_0_BIF_1_HWDATA[12]));
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[9]  (.A(
        \ahb_fsm_current_state_reto_1[0] ), .B(HWDATA_1_sqmuxa_reto_1), 
        .C(\AXI_IF_0_AHB_ADDR_reto_0[9] ), .D(\HADDR_int_reto[9] ), .Y(
        AHB_IF_0_BIF_1_HADDR[9]));
    SLE HADDR_ret_83 (.D(AXI_IF_0_AHB_ADDR[10]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto_0[10] )
        );
    SLE HADDR_ret_79 (.D(AXI_IF_0_AHB_ADDR[3]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto_0[3] ));
    SLE \HADDR_int[8]  (.D(AXI_IF_0_AHB_ADDR[8]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[8]_net_1 ));
    SLE \HADDR_int[3]  (.D(AXI_IF_0_AHB_ADDR[3]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[3]_net_1 ));
    SLE \HWDATA_int[4]  (.D(AXI_IF_0_AHB_DATA[4]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HWDATA_int[4]_net_1 ));
    SLE HADDR_ret_39 (.D(AXI_IF_0_AHB_ADDR[17]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto_0[17] )
        );
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[8]  (.A(
        \ahb_fsm_current_state_reto_0[0] ), .B(HWDATA_1_sqmuxa_reto_0), 
        .C(\AXI_IF_0_AHB_ADDR_reto_0[8] ), .D(\HADDR_int_reto[8] ), .Y(
        AHB_IF_0_BIF_1_HADDR[8]));
    SLE HADDR_ret_21 (.D(\HADDR_int[2]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[2] ));
    SLE HADDR_ret_24 (.D(\HADDR_int[24]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[24] ));
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[24]  (.A(
        \ahb_fsm_current_state_reto[0] ), .B(HWDATA_1_sqmuxa_reto), .C(
        AXI_IF_0_AHB_ADDR_reto_0_22), .D(\HADDR_int_reto[24] ), .Y(
        AHB_IF_0_BIF_1_HADDR[24]));
    SLE HADDR_ret_15 (.D(\HADDR_int[27]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[27] ));
    SLE \HWDATA_int[12]  (.D(AXI_IF_0_AHB_DATA[12]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HWDATA_int[12]_net_1 ));
    SLE HADDR_ret_87 (.D(AXI_IF_0_AHB_ADDR[9]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto_0[9] ));
    SLE \HWDATA[10]  (.D(\HWDATA_int[10]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(HWDATA_1_sqmuxa), 
        .ALn(MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(AHB_IF_0_BIF_1_HWDATA[10]));
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[13]  (.A(
        \ahb_fsm_current_state_reto[0] ), .B(HWDATA_1_sqmuxa_reto), .C(
        AXI_IF_0_AHB_ADDR_reto_0_11), .D(\HADDR_int_reto[13] ), .Y(
        AHB_IF_0_BIF_1_HADDR[13]));
    SLE \HTRANS_1_fast[1]  (.D(HWDATA_1_sqmuxa_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_171_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(HTRANS_1_fast[1]));
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[21]  (.A(
        \ahb_fsm_current_state_reto[0] ), .B(HWDATA_1_sqmuxa_reto), .C(
        AXI_IF_0_AHB_ADDR_reto_0_19), .D(\HADDR_int_reto[21] ), .Y(
        AHB_IF_0_BIF_1_HADDR[21]));
    SLE \HADDR_int[27]  (.D(AXI_IF_0_AHB_ADDR[27]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[27]_net_1 ));
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[2]  (.A(
        \ahb_fsm_current_state_reto[0] ), .B(HWDATA_1_sqmuxa_reto), .C(
        AXI_IF_0_AHB_ADDR_reto_0_0), .D(\HADDR_int_reto[2] ), .Y(
        AHB_IF_0_BIF_1_HADDR[2]));
    SLE \HWDATA[6]  (.D(\HWDATA_int[6]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(HWDATA_1_sqmuxa), 
        .ALn(MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(AHB_IF_0_BIF_1_HWDATA[6]));
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[22]  (.A(
        \ahb_fsm_current_state_reto_0[0] ), .B(HWDATA_1_sqmuxa_reto_0), 
        .C(\AXI_IF_0_AHB_ADDR_reto_0[22] ), .D(\HADDR_int_reto[22] ), 
        .Y(AHB_IF_0_BIF_1_HADDR[22]));
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[6]  (.A(
        \ahb_fsm_current_state_reto[0] ), .B(HWDATA_1_sqmuxa_reto), .C(
        AXI_IF_0_AHB_ADDR_reto_0_4), .D(\HADDR_int_reto[6] ), .Y(
        AHB_IF_0_BIF_1_HADDR[6]));
    SLE \HADDR_int[14]  (.D(AXI_IF_0_AHB_ADDR[14]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[14]_net_1 ));
    SLE HADDR_ret_3 (.D(\HADDR_int[25]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[25] ));
    SLE HADDR_ret_18 (.D(\HADDR_int[20]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[20] ));
    SLE \HADDR_int[5]  (.D(AXI_IF_0_AHB_ADDR[5]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[5]_net_1 ));
    SLE \HADDR[30]  (.D(\HADDR_9[30]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AHB_IF_0_BIF_1_HADDR[30]));
    SLE HADDR_ret_92 (.D(\HADDR_int[29]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[29] ));
    SLE HADDR_ret_69 (.D(HWDATA_1_sqmuxa), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(HWDATA_1_sqmuxa_reto_0));
    SLE \HADDR_int[30]  (.D(AXI_IF_0_AHB_ADDR[30]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[30]_net_1 ));
    CFG2 #( .INIT(4'hD) )  AHB_BUSY_RNO_0 (.A(
        \ahb_fsm_current_state[0]_net_1 ), .B(AXI_IF_0_WRITE_AHB), .Y(
        N_182_i_0));
    SLE \HADDR_int[21]  (.D(AXI_IF_0_AHB_ADDR[21]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[21]_net_1 ));
    SLE \ahb_fsm_current_state[0]  (.D(
        \ahb_fsm_current_state_ns[0]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(GND_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(
        \ahb_fsm_current_state[0]_net_1 ));
    SLE \HADDR_int[29]  (.D(AXI_IF_0_AHB_ADDR[29]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[29]_net_1 ));
    SLE \HADDR_int[10]  (.D(AXI_IF_0_AHB_ADDR[10]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[10]_net_1 ));
    SLE \HWDATA[9]  (.D(\HWDATA_int[9]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(HWDATA_1_sqmuxa), 
        .ALn(MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(AHB_IF_0_BIF_1_HWDATA[9]));
    SLE HADDR_ret_56 (.D(\HADDR_int[23]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\HADDR_int_reto[23] ));
    CFG4 #( .INIT(16'h3120) )  \HADDR_9[19]  (.A(
        \ahb_fsm_current_state_reto[0] ), .B(HWDATA_1_sqmuxa_reto), .C(
        AXI_IF_0_AHB_ADDR_reto_0_17), .D(\HADDR_int_reto[19] ), .Y(
        AHB_IF_0_BIF_1_HADDR[19]));
    SLE \HADDR_int[25]  (.D(AXI_IF_0_AHB_ADDR[25]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        HWDATA_int_0_sqmuxa_net_1), .ALn(VCC_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \HADDR_int[25]_net_1 ));
    
endmodule


module MDDR_TA_FABOSC_0_OSC(
       FABOSC_0_RCOSC_25_50MHZ_O2F,
       FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
    );
output FABOSC_0_RCOSC_25_50MHZ_O2F;
inout  FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC;

    wire N_RCOSC_25_50MHZ_CLKINT, GND_net_1, VCC_net_1;
    
    RCOSC_25_50MHZ_FAB I_RCOSC_25_50MHZ_FAB (.A(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC), .CLKOUT(
        N_RCOSC_25_50MHZ_CLKINT));
    RCOSC_25_50MHZ #( .FREQUENCY(50.0) )  I_RCOSC_25_50MHZ (.CLKOUT(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC));
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    CLKINT I_RCOSC_25_50MHZ_FAB_CLKINT (.A(N_RCOSC_25_50MHZ_CLKINT), 
        .Y(FABOSC_0_RCOSC_25_50MHZ_O2F));
    
endmodule


module CoreResetP_Z10(
       MSS_HPMS_READY_int_RNIPJE6,
       FABOSC_0_RCOSC_25_50MHZ_O2F,
       GL0_INST,
       INIT_DONE,
       POWER_ON_RESET_N,
       MDDR_TA_MSS_TMP_0_MSS_RESET_N_M2F,
       CORECONFIGP_0_APB_S_PRESET_N,
       CORECONFIGP_0_CONFIG1_DONE,
       CORECONFIGP_0_CONFIG2_DONE,
       CORECONFIGP_0_SOFT_MDDR_DDR_AXI_S_CORE_RESET,
       CORERESETP_0_MDDR_DDR_AXI_S_CORE_RESET_N
    );
output MSS_HPMS_READY_int_RNIPJE6;
input  FABOSC_0_RCOSC_25_50MHZ_O2F;
input  GL0_INST;
output INIT_DONE;
input  POWER_ON_RESET_N;
input  MDDR_TA_MSS_TMP_0_MSS_RESET_N_M2F;
input  CORECONFIGP_0_APB_S_PRESET_N;
input  CORECONFIGP_0_CONFIG1_DONE;
input  CORECONFIGP_0_CONFIG2_DONE;
input  CORECONFIGP_0_SOFT_MDDR_DDR_AXI_S_CORE_RESET;
output CORERESETP_0_MDDR_DDR_AXI_S_CORE_RESET_N;

    wire sm0_areset_n_rcosc, sdif0_areset_n_rcosc_net_1, 
        sm0_areset_n_clk_base_net_1, sm0_areset_n_clk_base_0, 
        MSS_HPMS_READY_int_net_1, \count_ddr[0]_net_1 , 
        \count_ddr_s[0] , ddr_settled_net_1, VCC_net_1, 
        ddr_settled4_net_1, GND_net_1, count_ddr_enable_net_1, 
        next_count_ddr_enable_0_sqmuxa, 
        un1_next_ddr_ready_0_sqmuxa_net_1, mss_ready_select_net_1, 
        POWER_ON_RESET_N_clk_base_net_1, mss_ready_select4_net_1, 
        \sm0_state[6]_net_1 , FDDR_CORE_RESET_N_int_net_1, 
        \sm0_state[1]_net_1 , mss_ready_state_net_1, 
        RESET_N_M2F_clk_base_net_1, \sm0_state[0]_net_1 , 
        \sm0_state[2]_net_1 , \sm0_state_ns[2]_net_1 , 
        \sm0_state[3]_net_1 , \sm0_state_ns[3]_net_1 , 
        \sm0_state[4]_net_1 , \sm0_state_ns[4]_net_1 , 
        \sm0_state[5]_net_1 , \sm0_state_ns[5]_net_1 , 
        \sm0_state_ns_a3[6]_net_1 , count_ddr_enable_rcosc_net_1, 
        count_ddr_enable_q1_net_1, ddr_settled_clk_base_net_1, 
        ddr_settled_q1_net_1, release_sdif3_core_clk_base, 
        release_sdif3_core_q1, POWER_ON_RESET_N_q1_net_1, 
        RESET_N_M2F_q1_net_1, FIC_2_APB_M_PRESET_N_clk_base_net_1, 
        FIC_2_APB_M_PRESET_N_q1_net_1, sm0_areset_n_i_0_i, 
        sm0_areset_n_q1_net_1, sm0_areset_n_rcosc_q1_net_1, 
        MSS_HPMS_READY_int_4_net_1, CONFIG1_DONE_clk_base_net_1, 
        CONFIG1_DONE_q1_net_1, CONFIG2_DONE_clk_base_net_1, 
        CONFIG2_DONE_q1_net_1, sdif3_spll_lock_q2_net_1, 
        sdif3_spll_lock_q1_net_1, release_sdif2_core, 
        \count_ddr[1]_net_1 , \count_ddr_s[1] , \count_ddr[2]_net_1 , 
        \count_ddr_s[2] , \count_ddr[3]_net_1 , \count_ddr_s[3] , 
        \count_ddr[4]_net_1 , \count_ddr_s[4] , \count_ddr[5]_net_1 , 
        \count_ddr_s[5] , \count_ddr[6]_net_1 , \count_ddr_s[6] , 
        \count_ddr[7]_net_1 , \count_ddr_s[7] , \count_ddr[8]_net_1 , 
        \count_ddr_s[8] , \count_ddr[9]_net_1 , \count_ddr_s[9] , 
        \count_ddr[10]_net_1 , \count_ddr_s[10] , 
        \count_ddr[11]_net_1 , \count_ddr_s[11] , 
        \count_ddr[12]_net_1 , \count_ddr_s[12] , 
        \count_ddr[13]_net_1 , \count_ddr_s[13]_net_1 , 
        count_ddr_s_550_FCO, \count_ddr_cry[1]_net_1 , 
        \count_ddr_cry[2]_net_1 , \count_ddr_cry[3]_net_1 , 
        \count_ddr_cry[4]_net_1 , \count_ddr_cry[5]_net_1 , 
        \count_ddr_cry[6]_net_1 , \count_ddr_cry[7]_net_1 , 
        \count_ddr_cry[8]_net_1 , \count_ddr_cry[9]_net_1 , 
        \count_ddr_cry[10]_net_1 , \count_ddr_cry[11]_net_1 , 
        \count_ddr_cry[12]_net_1 , ddr_settled4_6_net_1, 
        next_sm0_state25_net_1, ddr_settled4_9_net_1, 
        ddr_settled4_8_net_1, ddr_settled4_7_net_1;
    
    CFG4 #( .INIT(16'hFF70) )  \sm0_state_ns[4]  (.A(
        release_sdif3_core_clk_base), .B(ddr_settled_clk_base_net_1), 
        .C(\sm0_state[4]_net_1 ), .D(next_count_ddr_enable_0_sqmuxa), 
        .Y(\sm0_state_ns[4]_net_1 ));
    SLE \count_ddr[3]  (.D(\count_ddr_s[3] ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[3]_net_1 ));
    SLE sm0_areset_n_q1 (.D(VCC_net_1), .CLK(GL0_INST), .EN(VCC_net_1), 
        .ALn(sm0_areset_n_i_0_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(sm0_areset_n_q1_net_1));
    SLE count_ddr_enable_q1 (.D(count_ddr_enable_net_1), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(VCC_net_1), .ALn(
        sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(count_ddr_enable_q1_net_1));
    SLE \sm0_state[6]  (.D(VCC_net_1), .CLK(GL0_INST), .EN(
        \sm0_state_ns_a3[6]_net_1 ), .ALn(sm0_areset_n_clk_base_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\sm0_state[6]_net_1 ));
    CFG3 #( .INIT(8'hE0) )  MSS_HPMS_READY_int_4 (.A(
        RESET_N_M2F_clk_base_net_1), .B(mss_ready_select_net_1), .C(
        FIC_2_APB_M_PRESET_N_clk_base_net_1), .Y(
        MSS_HPMS_READY_int_4_net_1));
    SLE \sm0_state[2]  (.D(\sm0_state_ns[2]_net_1 ), .CLK(GL0_INST), 
        .EN(VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\sm0_state[2]_net_1 ));
    SLE FIC_2_APB_M_PRESET_N_clk_base (.D(
        FIC_2_APB_M_PRESET_N_q1_net_1), .CLK(GL0_INST), .EN(VCC_net_1), 
        .ALn(CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        FIC_2_APB_M_PRESET_N_clk_base_net_1));
    CFG4 #( .INIT(16'h0001) )  ddr_settled4_8 (.A(\count_ddr[7]_net_1 )
        , .B(\count_ddr[6]_net_1 ), .C(\count_ddr[2]_net_1 ), .D(
        \count_ddr[0]_net_1 ), .Y(ddr_settled4_8_net_1));
    ARI1 #( .INIT(20'h4AA00) )  \count_ddr_cry[4]  (.A(VCC_net_1), .B(
        \count_ddr[4]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \count_ddr_cry[3]_net_1 ), .S(\count_ddr_s[4] ), .Y(), .FCO(
        \count_ddr_cry[4]_net_1 ));
    SLE INIT_DONE_int (.D(VCC_net_1), .CLK(GL0_INST), .EN(
        \sm0_state[6]_net_1 ), .ALn(sm0_areset_n_clk_base_net_1), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(INIT_DONE));
    SLE \count_ddr[9]  (.D(\count_ddr_s[9] ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[9]_net_1 ));
    SLE MSS_HPMS_READY_int (.D(MSS_HPMS_READY_int_4_net_1), .CLK(
        GL0_INST), .EN(VCC_net_1), .ALn(
        POWER_ON_RESET_N_clk_base_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MSS_HPMS_READY_int_net_1));
    SLE count_ddr_enable_rcosc (.D(count_ddr_enable_q1_net_1), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(VCC_net_1), .ALn(
        sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(count_ddr_enable_rcosc_net_1));
    SLE \count_ddr[7]  (.D(\count_ddr_s[7] ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[7]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \sm0_state_ns_a3[6]  (.A(
        CONFIG2_DONE_clk_base_net_1), .B(\sm0_state[5]_net_1 ), .Y(
        \sm0_state_ns_a3[6]_net_1 ));
    VCC VCC (.Y(VCC_net_1));
    SLE \sm0_state[4]  (.D(\sm0_state_ns[4]_net_1 ), .CLK(GL0_INST), 
        .EN(VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\sm0_state[4]_net_1 ));
    SLE count_ddr_enable (.D(next_count_ddr_enable_0_sqmuxa), .CLK(
        GL0_INST), .EN(un1_next_ddr_ready_0_sqmuxa_net_1), .ALn(
        sm0_areset_n_clk_base_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(count_ddr_enable_net_1));
    ARI1 #( .INIT(20'h4AA00) )  \count_ddr_cry[10]  (.A(VCC_net_1), .B(
        \count_ddr[10]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \count_ddr_cry[9]_net_1 ), .S(\count_ddr_s[10] ), .Y(), .FCO(
        \count_ddr_cry[10]_net_1 ));
    SLE \sm0_state[5]  (.D(\sm0_state_ns[5]_net_1 ), .CLK(GL0_INST), 
        .EN(VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\sm0_state[5]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \count_ddr_cry[11]  (.A(VCC_net_1), .B(
        \count_ddr[11]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \count_ddr_cry[10]_net_1 ), .S(\count_ddr_s[11] ), .Y(), .FCO(
        \count_ddr_cry[11]_net_1 ));
    SLE \count_ddr[8]  (.D(\count_ddr_s[8] ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[8]_net_1 ));
    CFG3 #( .INIT(8'hAE) )  \sm0_state_ns[2]  (.A(\sm0_state[1]_net_1 )
        , .B(\sm0_state[2]_net_1 ), .C(CONFIG1_DONE_clk_base_net_1), 
        .Y(\sm0_state_ns[2]_net_1 ));
    SLE sm0_areset_n_clk_base (.D(sm0_areset_n_q1_net_1), .CLK(
        GL0_INST), .EN(VCC_net_1), .ALn(sm0_areset_n_i_0_i), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(sm0_areset_n_clk_base_0));
    CFG2 #( .INIT(4'h8) )  next_sm0_state25 (.A(
        ddr_settled_clk_base_net_1), .B(release_sdif3_core_clk_base), 
        .Y(next_sm0_state25_net_1));
    ARI1 #( .INIT(20'h4AA00) )  \count_ddr_cry[12]  (.A(VCC_net_1), .B(
        \count_ddr[12]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \count_ddr_cry[11]_net_1 ), .S(\count_ddr_s[12] ), .Y(), .FCO(
        \count_ddr_cry[12]_net_1 ));
    SLE mss_ready_state (.D(VCC_net_1), .CLK(GL0_INST), .EN(
        RESET_N_M2F_clk_base_net_1), .ALn(
        POWER_ON_RESET_N_clk_base_net_1), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        mss_ready_state_net_1));
    CFG4 #( .INIT(16'h8000) )  ddr_settled4 (.A(ddr_settled4_7_net_1), 
        .B(ddr_settled4_6_net_1), .C(ddr_settled4_8_net_1), .D(
        ddr_settled4_9_net_1), .Y(ddr_settled4_net_1));
    SLE \sm0_state[1]  (.D(\sm0_state[0]_net_1 ), .CLK(GL0_INST), .EN(
        VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \sm0_state[1]_net_1 ));
    CFG2 #( .INIT(4'h8) )  next_count_ddr_enable_0_sqmuxa_0_a3 (.A(
        sdif3_spll_lock_q2_net_1), .B(\sm0_state[3]_net_1 ), .Y(
        next_count_ddr_enable_0_sqmuxa));
    CFG2 #( .INIT(4'h4) )  ddr_settled4_6 (.A(\count_ddr[5]_net_1 ), 
        .B(\count_ddr[13]_net_1 ), .Y(ddr_settled4_6_net_1));
    SLE ddr_settled_clk_base (.D(ddr_settled_q1_net_1), .CLK(GL0_INST), 
        .EN(VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(ddr_settled_clk_base_net_1));
    SLE FIC_2_APB_M_PRESET_N_q1 (.D(VCC_net_1), .CLK(GL0_INST), .EN(
        VCC_net_1), .ALn(CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1)
        , .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        FIC_2_APB_M_PRESET_N_q1_net_1));
    ARI1 #( .INIT(20'h4AA00) )  \count_ddr_cry[8]  (.A(VCC_net_1), .B(
        \count_ddr[8]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \count_ddr_cry[7]_net_1 ), .S(\count_ddr_s[8] ), .Y(), .FCO(
        \count_ddr_cry[8]_net_1 ));
    GND GND (.Y(GND_net_1));
    CFG1 #( .INIT(2'h1) )  \count_ddr_RNO[0]  (.A(\count_ddr[0]_net_1 )
        , .Y(\count_ddr_s[0] ));
    SLE POWER_ON_RESET_N_clk_base (.D(POWER_ON_RESET_N_q1_net_1), .CLK(
        GL0_INST), .EN(VCC_net_1), .ALn(POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(POWER_ON_RESET_N_clk_base_net_1));
    ARI1 #( .INIT(20'h4AA00) )  \count_ddr_cry[1]  (.A(VCC_net_1), .B(
        \count_ddr[1]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        count_ddr_s_550_FCO), .S(\count_ddr_s[1] ), .Y(), .FCO(
        \count_ddr_cry[1]_net_1 ));
    SLE RESET_N_M2F_q1 (.D(VCC_net_1), .CLK(GL0_INST), .EN(VCC_net_1), 
        .ALn(MDDR_TA_MSS_TMP_0_MSS_RESET_N_M2F), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        RESET_N_M2F_q1_net_1));
    SLE release_sdif0_core_q1 (.D(release_sdif2_core), .CLK(GL0_INST), 
        .EN(VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(release_sdif3_core_q1));
    SLE \count_ddr[10]  (.D(\count_ddr_s[10] ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[10]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \count_ddr_cry[6]  (.A(VCC_net_1), .B(
        \count_ddr[6]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \count_ddr_cry[5]_net_1 ), .S(\count_ddr_s[6] ), .Y(), .FCO(
        \count_ddr_cry[6]_net_1 ));
    SLE sdif0_areset_n_rcosc (.D(sm0_areset_n_rcosc_q1_net_1), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(VCC_net_1), .ALn(
        sm0_areset_n_i_0_i), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(sdif0_areset_n_rcosc_net_1));
    ARI1 #( .INIT(20'h4AA00) )  \count_ddr_s[13]  (.A(VCC_net_1), .B(
        \count_ddr[13]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \count_ddr_cry[12]_net_1 ), .S(\count_ddr_s[13]_net_1 ), .Y(), 
        .FCO());
    SLE \count_ddr[5]  (.D(\count_ddr_s[5] ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[5]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \count_ddr_cry[3]  (.A(VCC_net_1), .B(
        \count_ddr[3]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \count_ddr_cry[2]_net_1 ), .S(\count_ddr_s[3] ), .Y(), .FCO(
        \count_ddr_cry[3]_net_1 ));
    SLE \count_ddr[2]  (.D(\count_ddr_s[2] ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[2]_net_1 ));
    SLE \count_ddr[1]  (.D(\count_ddr_s[1] ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[1]_net_1 ));
    SLE \sm0_state[0]  (.D(GND_net_1), .CLK(GL0_INST), .EN(VCC_net_1), 
        .ALn(sm0_areset_n_clk_base_net_1), .ADn(GND_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \sm0_state[0]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \count_ddr_cry[2]  (.A(VCC_net_1), .B(
        \count_ddr[2]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \count_ddr_cry[1]_net_1 ), .S(\count_ddr_s[2] ), .Y(), .FCO(
        \count_ddr_cry[2]_net_1 ));
    SLE sm0_areset_n_rcosc_q1 (.D(VCC_net_1), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(VCC_net_1), .ALn(
        sm0_areset_n_i_0_i), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(sm0_areset_n_rcosc_q1_net_1));
    CLKINT MSS_HPMS_READY_int_RNIPJE6_inst_1 (.A(
        MSS_HPMS_READY_int_net_1), .Y(MSS_HPMS_READY_int_RNIPJE6));
    ARI1 #( .INIT(20'h4AA00) )  \count_ddr_cry[5]  (.A(VCC_net_1), .B(
        \count_ddr[5]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \count_ddr_cry[4]_net_1 ), .S(\count_ddr_s[5] ), .Y(), .FCO(
        \count_ddr_cry[5]_net_1 ));
    CLKINT sdif0_areset_n_rcosc_RNIGC0B (.A(sdif0_areset_n_rcosc_net_1)
        , .Y(sm0_areset_n_rcosc));
    SLE ddr_settled_q1 (.D(ddr_settled_net_1), .CLK(GL0_INST), .EN(
        VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        ddr_settled_q1_net_1));
    ARI1 #( .INIT(20'h4AA00) )  count_ddr_s_550 (.A(VCC_net_1), .B(
        \count_ddr[0]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        VCC_net_1), .S(), .Y(), .FCO(count_ddr_s_550_FCO));
    SLE \count_ddr[11]  (.D(\count_ddr_s[11] ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[11]_net_1 ));
    SLE \sm0_state[3]  (.D(\sm0_state_ns[3]_net_1 ), .CLK(GL0_INST), 
        .EN(VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\sm0_state[3]_net_1 ));
    CFG4 #( .INIT(16'h88F8) )  \sm0_state_ns[3]  (.A(
        \sm0_state[2]_net_1 ), .B(CONFIG1_DONE_clk_base_net_1), .C(
        \sm0_state[3]_net_1 ), .D(sdif3_spll_lock_q2_net_1), .Y(
        \sm0_state_ns[3]_net_1 ));
    SLE \count_ddr[0]  (.D(\count_ddr_s[0] ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[0]_net_1 ));
    SLE CONFIG2_DONE_q1 (.D(CORECONFIGP_0_CONFIG2_DONE), .CLK(GL0_INST)
        , .EN(VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(CONFIG2_DONE_q1_net_1));
    SLE CONFIG2_DONE_clk_base (.D(CONFIG2_DONE_q1_net_1), .CLK(
        GL0_INST), .EN(VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(CONFIG2_DONE_clk_base_net_1));
    CFG4 #( .INIT(16'h0001) )  ddr_settled4_9 (.A(
        \count_ddr[12]_net_1 ), .B(\count_ddr[11]_net_1 ), .C(
        \count_ddr[3]_net_1 ), .D(\count_ddr[1]_net_1 ), .Y(
        ddr_settled4_9_net_1));
    CFG4 #( .INIT(16'h8000) )  ddr_settled4_7 (.A(
        \count_ddr[10]_net_1 ), .B(\count_ddr[9]_net_1 ), .C(
        \count_ddr[8]_net_1 ), .D(\count_ddr[4]_net_1 ), .Y(
        ddr_settled4_7_net_1));
    SLE CONFIG1_DONE_clk_base (.D(CONFIG1_DONE_q1_net_1), .CLK(
        GL0_INST), .EN(VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(CONFIG1_DONE_clk_base_net_1));
    SLE mss_ready_select (.D(VCC_net_1), .CLK(GL0_INST), .EN(
        mss_ready_select4_net_1), .ALn(POWER_ON_RESET_N_clk_base_net_1)
        , .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(mss_ready_select_net_1));
    CLKINT sm0_areset_n_clk_base_RNI4FO6 (.A(sm0_areset_n_clk_base_0), 
        .Y(sm0_areset_n_clk_base_net_1));
    SLE \count_ddr[4]  (.D(\count_ddr_s[4] ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[4]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \count_ddr_cry[7]  (.A(VCC_net_1), .B(
        \count_ddr[7]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \count_ddr_cry[6]_net_1 ), .S(\count_ddr_s[7] ), .Y(), .FCO(
        \count_ddr_cry[7]_net_1 ));
    SLE release_sdif0_core (.D(VCC_net_1), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(VCC_net_1), .ALn(
        sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(release_sdif2_core));
    SLE FDDR_CORE_RESET_N_int (.D(VCC_net_1), .CLK(GL0_INST), .EN(
        \sm0_state[1]_net_1 ), .ALn(sm0_areset_n_clk_base_net_1), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(FDDR_CORE_RESET_N_int_net_1));
    SLE POWER_ON_RESET_N_q1 (.D(VCC_net_1), .CLK(GL0_INST), .EN(
        VCC_net_1), .ALn(POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        POWER_ON_RESET_N_q1_net_1));
    CFG2 #( .INIT(4'h8) )  MSS_HPMS_READY_int_RNI3I2C (.A(
        POWER_ON_RESET_N), .B(MSS_HPMS_READY_int_RNIPJE6), .Y(
        sm0_areset_n_i_0_i));
    CFG2 #( .INIT(4'h8) )  mss_ready_select4 (.A(
        FIC_2_APB_M_PRESET_N_clk_base_net_1), .B(mss_ready_state_net_1)
        , .Y(mss_ready_select4_net_1));
    CFG2 #( .INIT(4'h4) )  MDDR_DDR_AXI_S_CORE_RESET_N (.A(
        CORECONFIGP_0_SOFT_MDDR_DDR_AXI_S_CORE_RESET), .B(
        FDDR_CORE_RESET_N_int_net_1), .Y(
        CORERESETP_0_MDDR_DDR_AXI_S_CORE_RESET_N));
    SLE \count_ddr[12]  (.D(\count_ddr_s[12] ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[12]_net_1 ));
    SLE ddr_settled (.D(VCC_net_1), .CLK(FABOSC_0_RCOSC_25_50MHZ_O2F), 
        .EN(ddr_settled4_net_1), .ALn(sm0_areset_n_rcosc), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(ddr_settled_net_1));
    ARI1 #( .INIT(20'h4AA00) )  \count_ddr_cry[9]  (.A(VCC_net_1), .B(
        \count_ddr[9]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \count_ddr_cry[8]_net_1 ), .S(\count_ddr_s[9] ), .Y(), .FCO(
        \count_ddr_cry[9]_net_1 ));
    SLE \count_ddr[6]  (.D(\count_ddr_s[6] ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[6]_net_1 ));
    SLE CONFIG1_DONE_q1 (.D(CORECONFIGP_0_CONFIG1_DONE), .CLK(GL0_INST)
        , .EN(VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(CONFIG1_DONE_q1_net_1));
    SLE sdif3_spll_lock_q1 (.D(VCC_net_1), .CLK(GL0_INST), .EN(
        VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        sdif3_spll_lock_q1_net_1));
    SLE release_sdif0_core_clk_base (.D(release_sdif3_core_q1), .CLK(
        GL0_INST), .EN(VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(release_sdif3_core_clk_base));
    SLE sdif3_spll_lock_q2 (.D(sdif3_spll_lock_q1_net_1), .CLK(
        GL0_INST), .EN(VCC_net_1), .ALn(sm0_areset_n_clk_base_net_1), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(sdif3_spll_lock_q2_net_1));
    SLE RESET_N_M2F_clk_base (.D(RESET_N_M2F_q1_net_1), .CLK(GL0_INST), 
        .EN(VCC_net_1), .ALn(MDDR_TA_MSS_TMP_0_MSS_RESET_N_M2F), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(RESET_N_M2F_clk_base_net_1));
    CFG4 #( .INIT(16'hF888) )  un1_next_ddr_ready_0_sqmuxa (.A(
        sdif3_spll_lock_q2_net_1), .B(\sm0_state[3]_net_1 ), .C(
        ddr_settled_clk_base_net_1), .D(\sm0_state[4]_net_1 ), .Y(
        un1_next_ddr_ready_0_sqmuxa_net_1));
    SLE \count_ddr[13]  (.D(\count_ddr_s[13]_net_1 ), .CLK(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .EN(count_ddr_enable_rcosc_net_1)
        , .ALn(sm0_areset_n_rcosc), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\count_ddr[13]_net_1 ));
    CFG4 #( .INIT(16'h88F8) )  \sm0_state_ns[5]  (.A(
        \sm0_state[4]_net_1 ), .B(next_sm0_state25_net_1), .C(
        \sm0_state[5]_net_1 ), .D(CONFIG2_DONE_clk_base_net_1), .Y(
        \sm0_state_ns[5]_net_1 ));
    
endmodule


module COREAHBLITE_DEFAULTSLAVESM_0s_0_1_0(
       defSlaveSMCurrentState,
       MSS_HPMS_READY_int_RNIPJE6,
       GL0_INST,
       N_321,
       DEFSLAVEDATASEL_9,
       DEFSLAVEDATASEL_8
    );
output defSlaveSMCurrentState;
input  MSS_HPMS_READY_int_RNIPJE6;
input  GL0_INST;
output N_321;
input  DEFSLAVEDATASEL_9;
input  DEFSLAVEDATASEL_8;

    wire VCC_net_1, GND_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    CFG3 #( .INIT(8'h54) )  defSlaveSMNextState (.A(
        defSlaveSMCurrentState), .B(DEFSLAVEDATASEL_9), .C(
        DEFSLAVEDATASEL_8), .Y(N_321));
    SLE defSlaveSMCurrentState_inst_1 (.D(N_321), .CLK(GL0_INST), .EN(
        VCC_net_1), .ALn(MSS_HPMS_READY_int_RNIPJE6), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        defSlaveSMCurrentState));
    
endmodule


module COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0(
       AHB_IF_0_BIF_1_HTRANS,
       AHB_IF_0_BIF_1_HADDR,
       arbRegSMCurrentState,
       masterDataInProg,
       regHADDR_21,
       regHADDR_22,
       regHADDR_23,
       regHADDR_24,
       regHADDR_25,
       regHADDR_27,
       regHADDR_6,
       regHADDR_7,
       regHADDR_8,
       regHADDR_9,
       regHADDR_10,
       regHADDR_11,
       regHADDR_12,
       regHADDR_13,
       regHADDR_14,
       regHADDR_15,
       regHADDR_16,
       regHADDR_17,
       regHADDR_18,
       regHADDR_19,
       regHADDR_20,
       regHADDR_0,
       regHADDR_1,
       regHADDR_2,
       regHADDR_3,
       regHADDR_4,
       regHADDR_5,
       MSS_HPMS_READY_int_RNIPJE6,
       GL0_INST,
       m0s16DataSel,
       m0s16AddrSel,
       regHTRANS,
       regHWRITE,
       AHB_IF_0_BIF_1_HWRITE,
       masterRegAddrSel,
       N_227,
       masterRegAddrSel_fast,
       masterRegAddrSel_rep1,
       regHTRANS_fast,
       CoreAHBLite_0_AHBmslave16_HREADY,
       HREADY_M_iv,
       N_170,
       N_102_i_0,
       N_100_i_0,
       N_98_i_0,
       N_106_i_0,
       N_209,
       N_321,
       HREADY_M_iv_i_0
    );
input  [1:1] AHB_IF_0_BIF_1_HTRANS;
input  [31:2] AHB_IF_0_BIF_1_HADDR;
input  [0:0] arbRegSMCurrentState;
input  [0:0] masterDataInProg;
output regHADDR_21;
output regHADDR_22;
output regHADDR_23;
output regHADDR_24;
output regHADDR_25;
output regHADDR_27;
output regHADDR_6;
output regHADDR_7;
output regHADDR_8;
output regHADDR_9;
output regHADDR_10;
output regHADDR_11;
output regHADDR_12;
output regHADDR_13;
output regHADDR_14;
output regHADDR_15;
output regHADDR_16;
output regHADDR_17;
output regHADDR_18;
output regHADDR_19;
output regHADDR_20;
output regHADDR_0;
output regHADDR_1;
output regHADDR_2;
output regHADDR_3;
output regHADDR_4;
output regHADDR_5;
input  MSS_HPMS_READY_int_RNIPJE6;
input  GL0_INST;
output m0s16DataSel;
output m0s16AddrSel;
output regHTRANS;
output regHWRITE;
input  AHB_IF_0_BIF_1_HWRITE;
output masterRegAddrSel;
output N_227;
output masterRegAddrSel_fast;
output masterRegAddrSel_rep1;
output regHTRANS_fast;
input  CoreAHBLite_0_AHBmslave16_HREADY;
output HREADY_M_iv;
output N_170;
input  N_102_i_0;
input  N_100_i_0;
input  N_98_i_0;
input  N_106_i_0;
output N_209;
output N_321;
output HREADY_M_iv_i_0;

    wire VCC_net_1, masterAddrClockEnable, GND_net_1, 
        \regHADDR[30]_net_1 , \SDATASELInt[10]_net_1 , \SADDRSEL[10] , 
        N_147_i_0, \SDATASELInt[11]_net_1 , N_30_i_0, 
        \SDATASELInt[12]_net_1 , \SADDRSEL[12] , 
        \SDATASELInt[13]_net_1 , N_148_i_0, \SDATASELInt[14]_net_1 , 
        \SADDRSEL[14] , \SDATASELInt[1]_net_1 , \SADDRSEL[1] , 
        \SDATASELInt[3]_net_1 , \SADDRSEL[3] , \SDATASELInt[5]_net_1 , 
        \SADDRSEL[5] , \SDATASELInt[7]_net_1 , \SADDRSEL[7] , 
        \SDATASELInt[8]_net_1 , \SADDRSEL[8] , \SDATASELInt[9]_net_1 , 
        N_190, d_masterRegAddrSel, N_227_reti, DEFSLAVEDATASEL_1_net_1, 
        DEFSLAVEDATASEL_1_reti, DEFSLAVEDATASEL_7_net_1, 
        DEFSLAVEDATASEL_7_reti, HREADY_M_pre37_0_net_1, 
        HREADY_M_pre37_0_reti, d_masterRegAddrSel_fast, 
        d_masterRegAddrSel_rep1, N_258, d_masterRegAddrSel_0_1_net_1, 
        N_36_i_0, HREADY_M_pre37_8_net_1, HREADY_M_pre37_7_net_1, 
        DEFSLAVEDATASEL_8_net_1, N_228, N_220, N_226, 
        HREADY_M_pre37_9_net_1, DEFSLAVEDATASEL_9_net_1, N_197, 
        d_masterRegAddrSel_0_0_net_1, HREADY_M_pre37_net_1, N_221, 
        defSlaveSMCurrentState;
    
    CFG3 #( .INIT(8'h20) )  \SADDRSEL_0_a2_2[9]  (.A(
        AHB_IF_0_BIF_1_HADDR[28]), .B(masterRegAddrSel), .C(
        AHB_IF_0_BIF_1_HTRANS[1]), .Y(N_220));
    CFG4 #( .INIT(16'hF0F4) )  d_masterRegAddrSel_0_rep1 (.A(
        CoreAHBLite_0_AHBmslave16_HREADY), .B(N_258), .C(
        d_masterRegAddrSel_0_1_net_1), .D(HREADY_M_iv), .Y(
        d_masterRegAddrSel_rep1));
    SLE \regHADDR[21]  (.D(AHB_IF_0_BIF_1_HADDR[21]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_19));
    SLE \regHADDR[15]  (.D(AHB_IF_0_BIF_1_HADDR[15]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_13));
    SLE \regHADDR[30]  (.D(AHB_IF_0_BIF_1_HADDR[30]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\regHADDR[30]_net_1 ));
    SLE \regHADDR[7]  (.D(AHB_IF_0_BIF_1_HADDR[7]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_5));
    CFG4 #( .INIT(16'h0800) )  HREADY_M_pre37_7_RNIRSD9 (.A(
        HREADY_M_pre37_7_net_1), .B(HREADY_M_pre37_9_net_1), .C(
        CoreAHBLite_0_AHBmslave16_HREADY), .D(HREADY_M_pre37_8_net_1), 
        .Y(N_221));
    SLE masterRegAddrSel_rep1_inst_1 (.D(d_masterRegAddrSel_rep1), 
        .CLK(GL0_INST), .EN(VCC_net_1), .ALn(
        MSS_HPMS_READY_int_RNIPJE6), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(masterRegAddrSel_rep1));
    SLE \regHADDR[9]  (.D(AHB_IF_0_BIF_1_HADDR[9]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_7));
    CFG2 #( .INIT(4'h4) )  d_masterRegAddrSel_0_a2_2_0 (.A(
        arbRegSMCurrentState[0]), .B(N_227), .Y(N_209));
    CFG2 #( .INIT(4'hE) )  DEFSLAVEDATASEL_1 (.A(N_36_i_0), .B(
        \SADDRSEL[14] ), .Y(DEFSLAVEDATASEL_1_reti));
    CFG4 #( .INIT(16'h0008) )  \SADDRSEL_0_a2[3]  (.A(
        AHB_IF_0_BIF_1_HADDR[29]), .B(N_220), .C(
        AHB_IF_0_BIF_1_HADDR[31]), .D(N_170), .Y(\SADDRSEL[3] ));
    SLE masterRegAddrSel_inst_1 (.D(d_masterRegAddrSel), .CLK(GL0_INST)
        , .EN(VCC_net_1), .ALn(MSS_HPMS_READY_int_RNIPJE6), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(masterRegAddrSel));
    SLE regHTRANS_inst_1 (.D(VCC_net_1), .CLK(GL0_INST), .EN(
        masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(regHTRANS));
    CFG4 #( .INIT(16'h8000) )  \SADDRSEL_0_a2_2_RNI20161[9]  (.A(
        AHB_IF_0_BIF_1_HADDR[29]), .B(N_220), .C(
        AHB_IF_0_BIF_1_HADDR[31]), .D(N_170), .Y(N_36_i_0));
    VCC VCC (.Y(VCC_net_1));
    CFG3 #( .INIT(8'h40) )  \SADDRSEL_0_a2[12]  (.A(
        AHB_IF_0_BIF_1_HADDR[29]), .B(N_228), .C(N_170), .Y(
        \SADDRSEL[12] ));
    SLE \regHADDR[29]  (.D(AHB_IF_0_BIF_1_HADDR[29]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_27));
    SLE \regHADDR[24]  (.D(AHB_IF_0_BIF_1_HADDR[24]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_22));
    CFG3 #( .INIT(8'h80) )  \SADDRSEL_0_a2[14]  (.A(
        AHB_IF_0_BIF_1_HADDR[29]), .B(N_228), .C(N_170), .Y(
        \SADDRSEL[14] ));
    CFG3 #( .INIT(8'h08) )  \SADDRSEL_0_a2[10]  (.A(
        AHB_IF_0_BIF_1_HADDR[29]), .B(N_228), .C(N_170), .Y(
        \SADDRSEL[10] ));
    SLE regHTRANS_fast_inst_1 (.D(VCC_net_1), .CLK(GL0_INST), .EN(
        masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(regHTRANS_fast));
    SLE masterRegAddrSel_fast_inst_1 (.D(d_masterRegAddrSel_fast), 
        .CLK(GL0_INST), .EN(VCC_net_1), .ALn(
        MSS_HPMS_READY_int_RNIPJE6), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(masterRegAddrSel_fast));
    CFG4 #( .INIT(16'hFFFE) )  DEFSLAVEDATASEL_7 (.A(\SADDRSEL[7] ), 
        .B(\SADDRSEL[5] ), .C(\SADDRSEL[3] ), .D(\SADDRSEL[1] ), .Y(
        DEFSLAVEDATASEL_7_reti));
    SLE \regHADDR[10]  (.D(AHB_IF_0_BIF_1_HADDR[10]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_8));
    CFG2 #( .INIT(4'h8) )  \SADDRSEL_0_a2[8]  (.A(N_226), .B(N_228), 
        .Y(\SADDRSEL[8] ));
    SLE \regHADDR[13]  (.D(AHB_IF_0_BIF_1_HADDR[13]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_11));
    CFG4 #( .INIT(16'h008A) )  masterAddrClockEnable_0 (.A(N_258), .B(
        N_209), .C(CoreAHBLite_0_AHBmslave16_HREADY), .D(HREADY_M_iv), 
        .Y(masterAddrClockEnable));
    CFG4 #( .INIT(16'hF0F4) )  d_masterRegAddrSel_0_fast (.A(
        CoreAHBLite_0_AHBmslave16_HREADY), .B(N_258), .C(
        d_masterRegAddrSel_0_1_net_1), .D(HREADY_M_iv), .Y(
        d_masterRegAddrSel_fast));
    SLE \regHADDR[12]  (.D(AHB_IF_0_BIF_1_HADDR[12]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_10));
    SLE \regHADDR[5]  (.D(AHB_IF_0_BIF_1_HADDR[5]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_3));
    SLE \regHADDR[2]  (.D(AHB_IF_0_BIF_1_HADDR[2]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_0));
    CFG4 #( .INIT(16'h0400) )  \SADDRSEL_0_a2_1[8]  (.A(
        AHB_IF_0_BIF_1_HADDR[28]), .B(AHB_IF_0_BIF_1_HTRANS[1]), .C(
        masterRegAddrSel), .D(AHB_IF_0_BIF_1_HADDR[31]), .Y(N_228));
    SLE \SDATASELInt[14]  (.D(\SADDRSEL[14] ), .CLK(GL0_INST), .EN(
        N_147_i_0), .ALn(MSS_HPMS_READY_int_RNIPJE6), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[14]_net_1 ));
    CFG4 #( .INIT(16'hF0F8) )  d_masterRegAddrSel_0_1 (.A(N_258), .B(
        N_209), .C(d_masterRegAddrSel_0_0_net_1), .D(HREADY_M_iv), .Y(
        d_masterRegAddrSel_0_1_net_1));
    SLE \regHADDR[8]  (.D(AHB_IF_0_BIF_1_HADDR[8]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_6));
    SLE \regHADDR[25]  (.D(AHB_IF_0_BIF_1_HADDR[25]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_23));
    GND GND (.Y(GND_net_1));
    CFG4 #( .INIT(16'h0080) )  \SDATASELInt_RNO[11]  (.A(
        AHB_IF_0_BIF_1_HADDR[29]), .B(N_220), .C(
        AHB_IF_0_BIF_1_HADDR[31]), .D(N_170), .Y(N_30_i_0));
    CFG3 #( .INIT(8'hEC) )  \SADDRSEL_0_o2[16]  (.A(masterRegAddrSel), 
        .B(N_258), .C(regHTRANS), .Y(m0s16AddrSel));
    CFG4 #( .INIT(16'h0100) )  HREADY_M_pre37_7 (.A(
        \SDATASELInt[14]_net_1 ), .B(\SDATASELInt[3]_net_1 ), .C(
        \SDATASELInt[13]_net_1 ), .D(m0s16DataSel), .Y(
        HREADY_M_pre37_7_net_1));
    SLE \regHADDR[17]  (.D(AHB_IF_0_BIF_1_HADDR[17]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_15));
    CFG4 #( .INIT(16'h0002) )  d_masterRegAddrSel_0_a2_5 (.A(
        AHB_IF_0_BIF_1_HTRANS[1]), .B(masterRegAddrSel_fast), .C(
        AHB_IF_0_BIF_1_HADDR[31]), .D(AHB_IF_0_BIF_1_HADDR[28]), .Y(
        N_258));
    CFG4 #( .INIT(16'h0001) )  d_masterRegAddrSel_0_a2_4 (.A(N_102_i_0)
        , .B(N_100_i_0), .C(N_98_i_0), .D(N_106_i_0), .Y(N_227_reti));
    CFG4 #( .INIT(16'h0800) )  \SADDRSEL_0_a2[7]  (.A(
        AHB_IF_0_BIF_1_HADDR[29]), .B(N_220), .C(
        AHB_IF_0_BIF_1_HADDR[31]), .D(N_170), .Y(\SADDRSEL[7] ));
    CFG4 #( .INIT(16'h0B03) )  HREADY_M_pre37_RNITFA91 (.A(
        masterDataInProg[0]), .B(HREADY_M_pre37_net_1), .C(N_321), .D(
        CoreAHBLite_0_AHBmslave16_HREADY), .Y(HREADY_M_iv_i_0));
    CFG4 #( .INIT(16'h3031) )  DEFSLAVEDATASEL_8_RNII3001 (.A(
        DEFSLAVEDATASEL_8_net_1), .B(N_221), .C(defSlaveSMCurrentState)
        , .D(DEFSLAVEDATASEL_9_net_1), .Y(N_147_i_0));
    SLE \regHADDR[6]  (.D(AHB_IF_0_BIF_1_HADDR[6]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_4));
    SLE \regHADDR[16]  (.D(AHB_IF_0_BIF_1_HADDR[16]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_14));
    CFG4 #( .INIT(16'hFFFE) )  DEFSLAVEDATASEL_9 (.A(
        DEFSLAVEDATASEL_7_net_1), .B(DEFSLAVEDATASEL_1_net_1), .C(
        \SDATASELInt[13]_net_1 ), .D(\SDATASELInt[12]_net_1 ), .Y(
        DEFSLAVEDATASEL_9_net_1));
    SLE \SDATASELInt[13]  (.D(N_148_i_0), .CLK(GL0_INST), .EN(
        N_147_i_0), .ALn(MSS_HPMS_READY_int_RNIPJE6), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[13]_net_1 ));
    SLE regHWRITE_inst_1 (.D(AHB_IF_0_BIF_1_HWRITE), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHWRITE));
    SLE \SDATASELInt[9]  (.D(N_190), .CLK(GL0_INST), .EN(N_147_i_0), 
        .ALn(MSS_HPMS_READY_int_RNIPJE6), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[9]_net_1 ));
    SLE \SDATASELInt[1]  (.D(\SADDRSEL[1] ), .CLK(GL0_INST), .EN(
        N_147_i_0), .ALn(MSS_HPMS_READY_int_RNIPJE6), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[1]_net_1 ));
    SLE \SDATASELInt[12]  (.D(\SADDRSEL[12] ), .CLK(GL0_INST), .EN(
        N_147_i_0), .ALn(MSS_HPMS_READY_int_RNIPJE6), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[12]_net_1 ));
    SLE \regHADDR[11]  (.D(AHB_IF_0_BIF_1_HADDR[11]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_9));
    CFG4 #( .INIT(16'hF4FC) )  HREADY_M_iv_inst_1 (.A(
        masterDataInProg[0]), .B(HREADY_M_pre37_net_1), .C(N_321), .D(
        CoreAHBLite_0_AHBmslave16_HREADY), .Y(HREADY_M_iv));
    CFG3 #( .INIT(8'h80) )  \SADDRSEL_0_a2_0[9]  (.A(
        AHB_IF_0_BIF_1_HADDR[31]), .B(N_220), .C(N_226), .Y(N_190));
    SLE \SDATASELInt[5]  (.D(\SADDRSEL[5] ), .CLK(GL0_INST), .EN(
        N_147_i_0), .ALn(MSS_HPMS_READY_int_RNIPJE6), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[5]_net_1 ));
    CFG4 #( .INIT(16'hF0F4) )  d_masterRegAddrSel_0 (.A(
        CoreAHBLite_0_AHBmslave16_HREADY), .B(N_258), .C(
        d_masterRegAddrSel_0_1_net_1), .D(HREADY_M_iv), .Y(
        d_masterRegAddrSel));
    SLE \regHADDR[3]  (.D(AHB_IF_0_BIF_1_HADDR[3]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_1));
    CFG4 #( .INIT(16'h0002) )  HREADY_M_pre37_9 (.A(
        HREADY_M_pre37_0_net_1), .B(\SDATASELInt[8]_net_1 ), .C(
        \SDATASELInt[5]_net_1 ), .D(\SDATASELInt[1]_net_1 ), .Y(
        HREADY_M_pre37_9_net_1));
    CFG4 #( .INIT(16'h0400) )  \SADDRSEL_0_a2[5]  (.A(
        AHB_IF_0_BIF_1_HADDR[29]), .B(N_220), .C(
        AHB_IF_0_BIF_1_HADDR[31]), .D(N_170), .Y(\SADDRSEL[5] ));
    CFG3 #( .INIT(8'h80) )  HREADY_M_pre37 (.A(HREADY_M_pre37_8_net_1), 
        .B(HREADY_M_pre37_9_net_1), .C(HREADY_M_pre37_7_net_1), .Y(
        HREADY_M_pre37_net_1));
    CFG2 #( .INIT(4'h1) )  HREADY_M_pre37_0 (.A(N_36_i_0), .B(
        \SADDRSEL[10] ), .Y(HREADY_M_pre37_0_reti));
    SLE \SDATASELInt[3]  (.D(\SADDRSEL[3] ), .CLK(GL0_INST), .EN(
        N_147_i_0), .ALn(MSS_HPMS_READY_int_RNIPJE6), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[3]_net_1 ));
    CFG4 #( .INIT(16'h0080) )  d_masterRegAddrSel_0_a2_1 (.A(N_227), 
        .B(regHTRANS), .C(masterRegAddrSel), .D(
        arbRegSMCurrentState[0]), .Y(N_197));
    CFG4 #( .INIT(16'h0511) )  \SADDRSEL_0_a2_0[8]  (.A(N_170), .B(
        AHB_IF_0_BIF_1_HADDR[29]), .C(regHADDR_27), .D(
        masterRegAddrSel), .Y(N_226));
    SLE SDATASELInt_ret (.D(DEFSLAVEDATASEL_1_reti), .CLK(GL0_INST), 
        .EN(N_147_i_0), .ALn(MSS_HPMS_READY_int_RNIPJE6), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(DEFSLAVEDATASEL_1_net_1));
    SLE \regHADDR[20]  (.D(AHB_IF_0_BIF_1_HADDR[20]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_18));
    SLE \regHADDR[23]  (.D(AHB_IF_0_BIF_1_HADDR[23]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_21));
    SLE \regHADDR[22]  (.D(AHB_IF_0_BIF_1_HADDR[22]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_20));
    CFG4 #( .INIT(16'h4000) )  \SDATASELInt_RNO[13]  (.A(
        AHB_IF_0_BIF_1_HADDR[29]), .B(N_220), .C(
        AHB_IF_0_BIF_1_HADDR[31]), .D(N_170), .Y(N_148_i_0));
    SLE SDATASELInt_ret_2 (.D(HREADY_M_pre37_0_reti), .CLK(GL0_INST), 
        .EN(N_147_i_0), .ALn(MSS_HPMS_READY_int_RNIPJE6), .ADn(
        GND_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(HREADY_M_pre37_0_net_1));
    SLE \SDATASELInt[7]  (.D(\SADDRSEL[7] ), .CLK(GL0_INST), .EN(
        N_147_i_0), .ALn(MSS_HPMS_READY_int_RNIPJE6), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[7]_net_1 ));
    CFG4 #( .INIT(16'h0001) )  HREADY_M_pre37_8 (.A(
        \SDATASELInt[11]_net_1 ), .B(\SDATASELInt[9]_net_1 ), .C(
        \SDATASELInt[7]_net_1 ), .D(\SDATASELInt[12]_net_1 ), .Y(
        HREADY_M_pre37_8_net_1));
    CFG4 #( .INIT(16'hF0F8) )  d_masterRegAddrSel_0_0 (.A(regHTRANS), 
        .B(masterRegAddrSel), .C(N_197), .D(
        CoreAHBLite_0_AHBmslave16_HREADY), .Y(
        d_masterRegAddrSel_0_0_net_1));
    CFG3 #( .INIT(8'h40) )  \SADDRSEL_0_a2[1]  (.A(
        AHB_IF_0_BIF_1_HADDR[31]), .B(N_220), .C(N_226), .Y(
        \SADDRSEL[1] ));
    CFG4 #( .INIT(16'hFFFE) )  DEFSLAVEDATASEL_8 (.A(
        \SDATASELInt[11]_net_1 ), .B(\SDATASELInt[10]_net_1 ), .C(
        \SDATASELInt[8]_net_1 ), .D(\SDATASELInt[9]_net_1 ), .Y(
        DEFSLAVEDATASEL_8_net_1));
    SLE \regHADDR[19]  (.D(AHB_IF_0_BIF_1_HADDR[19]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_17));
    SLE \regHADDR[14]  (.D(AHB_IF_0_BIF_1_HADDR[14]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_12));
    SLE \regHADDR[27]  (.D(AHB_IF_0_BIF_1_HADDR[27]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_25));
    SLE SDATASELInt_ret_1 (.D(DEFSLAVEDATASEL_7_reti), .CLK(GL0_INST), 
        .EN(N_147_i_0), .ALn(MSS_HPMS_READY_int_RNIPJE6), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(DEFSLAVEDATASEL_7_net_1));
    SLE \SDATASELInt[16]  (.D(m0s16AddrSel), .CLK(GL0_INST), .EN(
        N_147_i_0), .ALn(MSS_HPMS_READY_int_RNIPJE6), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        m0s16DataSel));
    SLE \regHADDR[18]  (.D(AHB_IF_0_BIF_1_HADDR[18]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_16));
    SLE \SDATASELInt[11]  (.D(N_30_i_0), .CLK(GL0_INST), .EN(N_147_i_0)
        , .ALn(MSS_HPMS_READY_int_RNIPJE6), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[11]_net_1 ));
    SLE \SDATASELInt[8]  (.D(\SADDRSEL[8] ), .CLK(GL0_INST), .EN(
        N_147_i_0), .ALn(MSS_HPMS_READY_int_RNIPJE6), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[8]_net_1 ));
    SLE arbRegSMCurrentState_ret (.D(N_227_reti), .CLK(GL0_INST), .EN(
        VCC_net_1), .ALn(MSS_HPMS_READY_int_RNIPJE6), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(N_227));
    SLE \regHADDR[4]  (.D(AHB_IF_0_BIF_1_HADDR[4]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_2));
    SLE \regHADDR[26]  (.D(AHB_IF_0_BIF_1_HADDR[26]), .CLK(GL0_INST), 
        .EN(masterAddrClockEnable), .ALn(MSS_HPMS_READY_int_RNIPJE6), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(regHADDR_24));
    SLE \SDATASELInt[10]  (.D(\SADDRSEL[10] ), .CLK(GL0_INST), .EN(
        N_147_i_0), .ALn(MSS_HPMS_READY_int_RNIPJE6), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[10]_net_1 ));
    CFG3 #( .INIT(8'hD8) )  \PREGATEDHADDR_i_m2[30]  (.A(
        masterRegAddrSel_fast), .B(\regHADDR[30]_net_1 ), .C(
        AHB_IF_0_BIF_1_HADDR[30]), .Y(N_170));
    COREAHBLITE_DEFAULTSLAVESM_0s_0_1_0 default_slave_sm (
        .defSlaveSMCurrentState(defSlaveSMCurrentState), 
        .MSS_HPMS_READY_int_RNIPJE6(MSS_HPMS_READY_int_RNIPJE6), 
        .GL0_INST(GL0_INST), .N_321(N_321), .DEFSLAVEDATASEL_9(
        DEFSLAVEDATASEL_9_net_1), .DEFSLAVEDATASEL_8(
        DEFSLAVEDATASEL_8_net_1));
    
endmodule


module COREAHBLITE_SLAVEARBITER_Z5_1(
       arbRegSMCurrentState_0,
       AHB_IF_0_BIF_1_HADDR_29,
       AHB_IF_0_BIF_1_HADDR_26,
       AHB_IF_0_BIF_1_HADDR_27,
       AHB_IF_0_BIF_1_HADDR_9,
       AHB_IF_0_BIF_1_HADDR_8,
       AHB_IF_0_BIF_1_HADDR_7,
       AHB_IF_0_BIF_1_HADDR_6,
       AHB_IF_0_BIF_1_HADDR_5,
       AHB_IF_0_BIF_1_HADDR_4,
       AHB_IF_0_BIF_1_HADDR_3,
       AHB_IF_0_BIF_1_HADDR_2,
       AHB_IF_0_BIF_1_HADDR_1,
       AHB_IF_0_BIF_1_HADDR_0,
       regHADDR_27,
       regHADDR_9,
       regHADDR_8,
       regHADDR_7,
       regHADDR_6,
       regHADDR_5,
       regHADDR_4,
       regHADDR_3,
       regHADDR_2,
       regHADDR_1,
       regHADDR_0,
       MSS_HPMS_READY_int_RNIPJE6,
       GL0_INST,
       N_106_i_0,
       N_102_i_0,
       N_100_i_0,
       N_98_i_0,
       N_167,
       N_215,
       N_227,
       N_259,
       masterRegAddrSel,
       N_165_i_0,
       N_162_i_0,
       N_209,
       m0s16AddrSel,
       N_259_i_0,
       AHB_IF_0_BIF_1_HWRITE,
       regHWRITE,
       N_150_i_0,
       N_170,
       N_164_i_0,
       N_163_i_0,
       masterRegAddrSel_rep1,
       N_161_i_0,
       N_160_i_0,
       N_159_i_0,
       N_158_i_0,
       N_157_i_0,
       N_156_i_0,
       N_155_i_0,
       N_154_i_0,
       N_153_i_0,
       N_152_i_0,
       CoreAHBLite_0_AHBmslave16_HREADY
    );
output arbRegSMCurrentState_0;
input  AHB_IF_0_BIF_1_HADDR_29;
input  AHB_IF_0_BIF_1_HADDR_26;
input  AHB_IF_0_BIF_1_HADDR_27;
input  AHB_IF_0_BIF_1_HADDR_9;
input  AHB_IF_0_BIF_1_HADDR_8;
input  AHB_IF_0_BIF_1_HADDR_7;
input  AHB_IF_0_BIF_1_HADDR_6;
input  AHB_IF_0_BIF_1_HADDR_5;
input  AHB_IF_0_BIF_1_HADDR_4;
input  AHB_IF_0_BIF_1_HADDR_3;
input  AHB_IF_0_BIF_1_HADDR_2;
input  AHB_IF_0_BIF_1_HADDR_1;
input  AHB_IF_0_BIF_1_HADDR_0;
input  regHADDR_27;
input  regHADDR_9;
input  regHADDR_8;
input  regHADDR_7;
input  regHADDR_6;
input  regHADDR_5;
input  regHADDR_4;
input  regHADDR_3;
input  regHADDR_2;
input  regHADDR_1;
input  regHADDR_0;
input  MSS_HPMS_READY_int_RNIPJE6;
input  GL0_INST;
output N_106_i_0;
output N_102_i_0;
output N_100_i_0;
output N_98_i_0;
input  N_167;
input  N_215;
input  N_227;
output N_259;
input  masterRegAddrSel;
output N_165_i_0;
output N_162_i_0;
input  N_209;
input  m0s16AddrSel;
output N_259_i_0;
input  AHB_IF_0_BIF_1_HWRITE;
input  regHWRITE;
output N_150_i_0;
input  N_170;
output N_164_i_0;
output N_163_i_0;
input  masterRegAddrSel_rep1;
output N_161_i_0;
output N_160_i_0;
output N_159_i_0;
output N_158_i_0;
output N_157_i_0;
output N_156_i_0;
output N_155_i_0;
output N_154_i_0;
output N_153_i_0;
output N_152_i_0;
input  CoreAHBLite_0_AHBmslave16_HREADY;

    wire VCC_net_1, N_104_i_0, GND_net_1, 
        \arbRegSMCurrentState[1]_net_1 , 
        \arbRegSMCurrentState[5]_net_1 , 
        \arbRegSMCurrentState[9]_net_1 , 
        \arbRegSMCurrentState[13]_net_1 , 
        \arbRegSMCurrentState_ns_i_0_0[1]_net_1 ;
    
    CFG4 #( .INIT(16'h3022) )  \arbRegSMCurrentState_RNI1VV72[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_27), .B(N_259), .C(regHADDR_27), .D(
        masterRegAddrSel), .Y(N_163_i_0));
    CFG3 #( .INIT(8'h40) )  \arbRegSMCurrentState_RNI8CMH[0]  (.A(
        masterRegAddrSel), .B(AHB_IF_0_BIF_1_HADDR_29), .C(
        arbRegSMCurrentState_0), .Y(N_165_i_0));
    CFG3 #( .INIT(8'h40) )  \arbRegSMCurrentState_RNIEHLH[0]  (.A(
        masterRegAddrSel), .B(AHB_IF_0_BIF_1_HADDR_26), .C(
        arbRegSMCurrentState_0), .Y(N_162_i_0));
    CFG4 #( .INIT(16'h0C0A) )  \arbRegSMCurrentState_RNI3I852[0]  (.A(
        AHB_IF_0_BIF_1_HWRITE), .B(regHWRITE), .C(N_259), .D(
        masterRegAddrSel), .Y(N_150_i_0));
    CFG4 #( .INIT(16'h3022) )  \arbRegSMCurrentState_RNIGN592[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_5), .B(N_259), .C(regHADDR_5), .D(
        masterRegAddrSel_rep1), .Y(N_157_i_0));
    GND GND (.Y(GND_net_1));
    CFG4 #( .INIT(16'h00FD) )  \arbRegSMCurrentState_RNIC1QG1_0[0]  (
        .A(N_167), .B(N_215), .C(N_227), .D(arbRegSMCurrentState_0), 
        .Y(N_259));
    CFG4 #( .INIT(16'h3022) )  \arbRegSMCurrentState_RNIAH592[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_2), .B(N_259), .C(regHADDR_2), .D(
        masterRegAddrSel_rep1), .Y(N_154_i_0));
    CFG2 #( .INIT(4'h4) )  \arbRegSMCurrentState_RNI60PU1[0]  (.A(
        N_259), .B(N_170), .Y(N_164_i_0));
    SLE \arbRegSMCurrentState[0]  (.D(N_104_i_0), .CLK(GL0_INST), .EN(
        VCC_net_1), .ALn(MSS_HPMS_READY_int_RNIPJE6), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        arbRegSMCurrentState_0));
    CFG2 #( .INIT(4'h1) )  \arbRegSMCurrentState_RNO[0]  (.A(
        CoreAHBLite_0_AHBmslave16_HREADY), .B(N_259), .Y(N_104_i_0));
    SLE \arbRegSMCurrentState[9]  (.D(N_100_i_0), .CLK(GL0_INST), .EN(
        VCC_net_1), .ALn(MSS_HPMS_READY_int_RNIPJE6), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[9]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \arbRegSMCurrentState_RNIUGUL[13]  (.A(
        m0s16AddrSel), .B(\arbRegSMCurrentState[13]_net_1 ), .Y(
        N_98_i_0));
    CFG4 #( .INIT(16'h3022) )  \arbRegSMCurrentState_RNI64TD2[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_9), .B(N_259), .C(regHADDR_9), .D(
        masterRegAddrSel_rep1), .Y(N_161_i_0));
    CFG4 #( .INIT(16'h3022) )  \arbRegSMCurrentState_RNIFJ532[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_0), .B(N_259), .C(regHADDR_0), .D(
        masterRegAddrSel), .Y(N_152_i_0));
    CFG4 #( .INIT(16'h3022) )  \arbRegSMCurrentState_RNICJ592[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_3), .B(N_259), .C(regHADDR_3), .D(
        masterRegAddrSel_rep1), .Y(N_155_i_0));
    SLE \arbRegSMCurrentState[5]  (.D(N_102_i_0), .CLK(GL0_INST), .EN(
        VCC_net_1), .ALn(MSS_HPMS_READY_int_RNIPJE6), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[5]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \arbRegSMCurrentState_RNIFS3D[5]  (.A(
        m0s16AddrSel), .B(\arbRegSMCurrentState[5]_net_1 ), .Y(
        N_102_i_0));
    CFG4 #( .INIT(16'h3022) )  \arbRegSMCurrentState_RNI8F592[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_1), .B(N_259), .C(regHADDR_1), .D(
        masterRegAddrSel_rep1), .Y(N_153_i_0));
    CFG4 #( .INIT(16'h3022) )  \arbRegSMCurrentState_RNI42TD2[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_8), .B(N_259), .C(regHADDR_8), .D(
        masterRegAddrSel_rep1), .Y(N_160_i_0));
    CFG4 #( .INIT(16'h3022) )  \arbRegSMCurrentState_RNIEL592[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_4), .B(N_259), .C(regHADDR_4), .D(
        masterRegAddrSel_rep1), .Y(N_156_i_0));
    CFG4 #( .INIT(16'h3022) )  \arbRegSMCurrentState_RNIKR592[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_7), .B(N_259), .C(regHADDR_7), .D(
        masterRegAddrSel_rep1), .Y(N_159_i_0));
    SLE \arbRegSMCurrentState[1]  (.D(N_106_i_0), .CLK(GL0_INST), .EN(
        VCC_net_1), .ALn(MSS_HPMS_READY_int_RNIPJE6), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[1]_net_1 ));
    CFG2 #( .INIT(4'h4) )  \arbRegSMCurrentState_RNIJ04D[9]  (.A(
        m0s16AddrSel), .B(\arbRegSMCurrentState[9]_net_1 ), .Y(
        N_100_i_0));
    CFG4 #( .INIT(16'hFF02) )  \arbRegSMCurrentState_RNIC1QG1[0]  (.A(
        N_167), .B(N_215), .C(N_227), .D(arbRegSMCurrentState_0), .Y(
        N_259_i_0));
    VCC VCC (.Y(VCC_net_1));
    CFG4 #( .INIT(16'h00F4) )  
        \arbRegSMCurrentState_ns_i_0_0_RNIVPHT[1]  (.A(m0s16AddrSel), 
        .B(\arbRegSMCurrentState[1]_net_1 ), .C(
        CoreAHBLite_0_AHBmslave16_HREADY), .D(
        \arbRegSMCurrentState_ns_i_0_0[1]_net_1 ), .Y(N_106_i_0));
    CFG4 #( .INIT(16'hAAAB) )  \arbRegSMCurrentState_ns_i_0_0[1]  (.A(
        N_209), .B(m0s16AddrSel), .C(\arbRegSMCurrentState[1]_net_1 ), 
        .D(arbRegSMCurrentState_0), .Y(
        \arbRegSMCurrentState_ns_i_0_0[1]_net_1 ));
    CFG4 #( .INIT(16'h3022) )  \arbRegSMCurrentState_RNIIP592[0]  (.A(
        AHB_IF_0_BIF_1_HADDR_6), .B(N_259), .C(regHADDR_6), .D(
        masterRegAddrSel_rep1), .Y(N_158_i_0));
    SLE \arbRegSMCurrentState[13]  (.D(N_98_i_0), .CLK(GL0_INST), .EN(
        VCC_net_1), .ALn(MSS_HPMS_READY_int_RNIPJE6), .ADn(GND_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[13]_net_1 ));
    
endmodule


module COREAHBLITE_SLAVESTAGE_0s_0_0_0(
       masterDataInProg,
       HTRANS_1_fast,
       AHB_IF_0_BIF_1_HWDATA,
       CoreAHBLite_0_AHBmslave16_HWDATA,
       AHB_IF_0_BIF_1_HTRANS,
       arbRegSMCurrentState,
       CoreAHBLite_0_AHBmslave16_HADDR,
       AHB_IF_0_BIF_1_HADDR_29,
       AHB_IF_0_BIF_1_HADDR_26,
       AHB_IF_0_BIF_1_HADDR_25,
       AHB_IF_0_BIF_1_HADDR_24,
       AHB_IF_0_BIF_1_HADDR_23,
       AHB_IF_0_BIF_1_HADDR_22,
       AHB_IF_0_BIF_1_HADDR_21,
       AHB_IF_0_BIF_1_HADDR_20,
       AHB_IF_0_BIF_1_HADDR_19,
       AHB_IF_0_BIF_1_HADDR_18,
       AHB_IF_0_BIF_1_HADDR_17,
       AHB_IF_0_BIF_1_HADDR_16,
       AHB_IF_0_BIF_1_HADDR_15,
       AHB_IF_0_BIF_1_HADDR_14,
       AHB_IF_0_BIF_1_HADDR_13,
       AHB_IF_0_BIF_1_HADDR_12,
       AHB_IF_0_BIF_1_HADDR_11,
       AHB_IF_0_BIF_1_HADDR_10,
       AHB_IF_0_BIF_1_HADDR_27,
       AHB_IF_0_BIF_1_HADDR_9,
       AHB_IF_0_BIF_1_HADDR_8,
       AHB_IF_0_BIF_1_HADDR_7,
       AHB_IF_0_BIF_1_HADDR_6,
       AHB_IF_0_BIF_1_HADDR_5,
       AHB_IF_0_BIF_1_HADDR_4,
       AHB_IF_0_BIF_1_HADDR_3,
       AHB_IF_0_BIF_1_HADDR_2,
       AHB_IF_0_BIF_1_HADDR_1,
       AHB_IF_0_BIF_1_HADDR_0,
       regHADDR_25,
       regHADDR_24,
       regHADDR_23,
       regHADDR_22,
       regHADDR_21,
       regHADDR_20,
       regHADDR_19,
       regHADDR_18,
       regHADDR_17,
       regHADDR_16,
       regHADDR_15,
       regHADDR_14,
       regHADDR_13,
       regHADDR_12,
       regHADDR_11,
       regHADDR_10,
       regHADDR_27,
       regHADDR_9,
       regHADDR_8,
       regHADDR_7,
       regHADDR_6,
       regHADDR_5,
       regHADDR_4,
       regHADDR_3,
       regHADDR_2,
       regHADDR_1,
       regHADDR_0,
       MSS_HPMS_READY_int_RNIPJE6,
       GL0_INST,
       N_259_i_0,
       CoreAHBLite_0_AHBmslave16_HREADY,
       masterRegAddrSel_fast,
       regHTRANS_fast,
       m0s16DataSel,
       N_321,
       N_149_i_0,
       regHTRANS,
       masterRegAddrSel_rep1,
       N_227,
       masterRegAddrSel,
       N_166_i_0,
       N_106_i_0,
       N_102_i_0,
       N_100_i_0,
       N_98_i_0,
       N_165_i_0,
       N_162_i_0,
       N_209,
       m0s16AddrSel,
       AHB_IF_0_BIF_1_HWRITE,
       regHWRITE,
       N_150_i_0,
       N_170,
       N_164_i_0,
       N_163_i_0,
       N_161_i_0,
       N_160_i_0,
       N_159_i_0,
       N_158_i_0,
       N_157_i_0,
       N_156_i_0,
       N_155_i_0,
       N_154_i_0,
       N_153_i_0,
       N_152_i_0
    );
output [0:0] masterDataInProg;
input  [1:1] HTRANS_1_fast;
input  [13:0] AHB_IF_0_BIF_1_HWDATA;
output [13:0] CoreAHBLite_0_AHBmslave16_HWDATA;
input  [1:1] AHB_IF_0_BIF_1_HTRANS;
output [0:0] arbRegSMCurrentState;
output [27:12] CoreAHBLite_0_AHBmslave16_HADDR;
input  AHB_IF_0_BIF_1_HADDR_29;
input  AHB_IF_0_BIF_1_HADDR_26;
input  AHB_IF_0_BIF_1_HADDR_25;
input  AHB_IF_0_BIF_1_HADDR_24;
input  AHB_IF_0_BIF_1_HADDR_23;
input  AHB_IF_0_BIF_1_HADDR_22;
input  AHB_IF_0_BIF_1_HADDR_21;
input  AHB_IF_0_BIF_1_HADDR_20;
input  AHB_IF_0_BIF_1_HADDR_19;
input  AHB_IF_0_BIF_1_HADDR_18;
input  AHB_IF_0_BIF_1_HADDR_17;
input  AHB_IF_0_BIF_1_HADDR_16;
input  AHB_IF_0_BIF_1_HADDR_15;
input  AHB_IF_0_BIF_1_HADDR_14;
input  AHB_IF_0_BIF_1_HADDR_13;
input  AHB_IF_0_BIF_1_HADDR_12;
input  AHB_IF_0_BIF_1_HADDR_11;
input  AHB_IF_0_BIF_1_HADDR_10;
input  AHB_IF_0_BIF_1_HADDR_27;
input  AHB_IF_0_BIF_1_HADDR_9;
input  AHB_IF_0_BIF_1_HADDR_8;
input  AHB_IF_0_BIF_1_HADDR_7;
input  AHB_IF_0_BIF_1_HADDR_6;
input  AHB_IF_0_BIF_1_HADDR_5;
input  AHB_IF_0_BIF_1_HADDR_4;
input  AHB_IF_0_BIF_1_HADDR_3;
input  AHB_IF_0_BIF_1_HADDR_2;
input  AHB_IF_0_BIF_1_HADDR_1;
input  AHB_IF_0_BIF_1_HADDR_0;
input  regHADDR_25;
input  regHADDR_24;
input  regHADDR_23;
input  regHADDR_22;
input  regHADDR_21;
input  regHADDR_20;
input  regHADDR_19;
input  regHADDR_18;
input  regHADDR_17;
input  regHADDR_16;
input  regHADDR_15;
input  regHADDR_14;
input  regHADDR_13;
input  regHADDR_12;
input  regHADDR_11;
input  regHADDR_10;
input  regHADDR_27;
input  regHADDR_9;
input  regHADDR_8;
input  regHADDR_7;
input  regHADDR_6;
input  regHADDR_5;
input  regHADDR_4;
input  regHADDR_3;
input  regHADDR_2;
input  regHADDR_1;
input  regHADDR_0;
input  MSS_HPMS_READY_int_RNIPJE6;
input  GL0_INST;
output N_259_i_0;
input  CoreAHBLite_0_AHBmslave16_HREADY;
input  masterRegAddrSel_fast;
input  regHTRANS_fast;
input  m0s16DataSel;
input  N_321;
output N_149_i_0;
input  regHTRANS;
input  masterRegAddrSel_rep1;
input  N_227;
input  masterRegAddrSel;
output N_166_i_0;
output N_106_i_0;
output N_102_i_0;
output N_100_i_0;
output N_98_i_0;
output N_165_i_0;
output N_162_i_0;
input  N_209;
input  m0s16AddrSel;
input  AHB_IF_0_BIF_1_HWRITE;
input  regHWRITE;
output N_150_i_0;
input  N_170;
output N_164_i_0;
output N_163_i_0;
output N_161_i_0;
output N_160_i_0;
output N_159_i_0;
output N_158_i_0;
output N_157_i_0;
output N_156_i_0;
output N_155_i_0;
output N_154_i_0;
output N_153_i_0;
output N_152_i_0;

    wire VCC_net_1, GND_net_1, N_167, N_215, HTRANS_i_0_net_1, 
        \HSIZE_i_0[1]_net_1 , N_259;
    
    CFG4 #( .INIT(16'h55FD) )  HTRANS_i_0 (.A(N_167), .B(N_215), .C(
        N_227), .D(arbRegSMCurrentState[0]), .Y(HTRANS_i_0_net_1));
    CFG4 #( .INIT(16'h00CD) )  \HSIZE_i_0_RNIE4F71[1]  (.A(N_227), .B(
        arbRegSMCurrentState[0]), .C(N_215), .D(\HSIZE_i_0[1]_net_1 ), 
        .Y(N_166_i_0));
    CFG3 #( .INIT(8'h32) )  g0_1 (.A(AHB_IF_0_BIF_1_HADDR_29), .B(
        masterRegAddrSel_fast), .C(AHB_IF_0_BIF_1_HADDR_26), .Y(N_215));
    CFG2 #( .INIT(4'h8) )  \HWDATA[12]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[12]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[12]));
    VCC VCC (.Y(VCC_net_1));
    CFG2 #( .INIT(4'h8) )  \HWDATA[10]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[10]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[10]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[13]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[13]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[13]));
    CFG4 #( .INIT(16'h3022) )  \HADDR[14]  (.A(AHB_IF_0_BIF_1_HADDR_12)
        , .B(N_259), .C(regHADDR_12), .D(masterRegAddrSel_rep1), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR[14]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[0]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[0]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[0]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[4]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[4]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[4]));
    CFG4 #( .INIT(16'h3022) )  \HADDR[19]  (.A(AHB_IF_0_BIF_1_HADDR_17)
        , .B(N_259), .C(regHADDR_17), .D(masterRegAddrSel), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR[19]));
    CFG4 #( .INIT(16'h3022) )  \HADDR[15]  (.A(AHB_IF_0_BIF_1_HADDR_13)
        , .B(N_259), .C(regHADDR_13), .D(masterRegAddrSel_rep1), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR[15]));
    CFG4 #( .INIT(16'h3022) )  \HADDR[17]  (.A(AHB_IF_0_BIF_1_HADDR_15)
        , .B(N_259), .C(regHADDR_15), .D(masterRegAddrSel_rep1), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR[17]));
    CFG4 #( .INIT(16'h3022) )  \HADDR[16]  (.A(AHB_IF_0_BIF_1_HADDR_14)
        , .B(N_259), .C(regHADDR_14), .D(masterRegAddrSel_rep1), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR[16]));
    CFG4 #( .INIT(16'h3022) )  \HADDR[18]  (.A(AHB_IF_0_BIF_1_HADDR_16)
        , .B(N_259), .C(regHADDR_16), .D(masterRegAddrSel_rep1), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR[18]));
    CFG4 #( .INIT(16'h3022) )  \HADDR[20]  (.A(AHB_IF_0_BIF_1_HADDR_18)
        , .B(N_259), .C(regHADDR_18), .D(masterRegAddrSel), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR[20]));
    GND GND (.Y(GND_net_1));
    SLE \masterDataInProg[0]  (.D(N_259_i_0), .CLK(GL0_INST), .EN(
        CoreAHBLite_0_AHBmslave16_HREADY), .ALn(
        MSS_HPMS_READY_int_RNIPJE6), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(masterDataInProg[0]));
    CFG4 #( .INIT(16'h3022) )  \HADDR[24]  (.A(AHB_IF_0_BIF_1_HADDR_22)
        , .B(N_259), .C(regHADDR_22), .D(masterRegAddrSel), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR[24]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[8]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[8]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[8]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[3]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[3]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[3]));
    CFG4 #( .INIT(16'h3022) )  \HADDR[25]  (.A(AHB_IF_0_BIF_1_HADDR_23)
        , .B(N_259), .C(regHADDR_23), .D(masterRegAddrSel), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR[25]));
    CFG3 #( .INIT(8'h23) )  HTRANS_i_0_RNISM401 (.A(m0s16DataSel), .B(
        HTRANS_i_0_net_1), .C(N_321), .Y(N_149_i_0));
    CFG4 #( .INIT(16'h3022) )  \HADDR[21]  (.A(AHB_IF_0_BIF_1_HADDR_19)
        , .B(N_259), .C(regHADDR_19), .D(masterRegAddrSel), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR[21]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[5]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[5]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[5]));
    CFG4 #( .INIT(16'h3022) )  \HADDR[27]  (.A(AHB_IF_0_BIF_1_HADDR_25)
        , .B(N_259), .C(regHADDR_25), .D(masterRegAddrSel), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR[27]));
    CFG4 #( .INIT(16'h5053) )  \HSIZE_i_0[1]  (.A(regHTRANS), .B(
        AHB_IF_0_BIF_1_HTRANS[1]), .C(masterRegAddrSel_rep1), .D(
        arbRegSMCurrentState[0]), .Y(\HSIZE_i_0[1]_net_1 ));
    CFG4 #( .INIT(16'h3022) )  \HADDR[26]  (.A(AHB_IF_0_BIF_1_HADDR_24)
        , .B(N_259), .C(regHADDR_24), .D(masterRegAddrSel), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR[26]));
    CFG4 #( .INIT(16'h3022) )  \HADDR[12]  (.A(AHB_IF_0_BIF_1_HADDR_10)
        , .B(N_259), .C(regHADDR_10), .D(masterRegAddrSel_rep1), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR[12]));
    CFG4 #( .INIT(16'h3022) )  \HADDR[13]  (.A(AHB_IF_0_BIF_1_HADDR_11)
        , .B(N_259), .C(regHADDR_11), .D(masterRegAddrSel), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR[13]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[9]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[9]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[9]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[7]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[7]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[7]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[1]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[1]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[1]));
    CFG2 #( .INIT(4'h8) )  \HWDATA[6]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[6]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[6]));
    COREAHBLITE_SLAVEARBITER_Z5_1 slave_arbiter (
        .arbRegSMCurrentState_0(arbRegSMCurrentState[0]), 
        .AHB_IF_0_BIF_1_HADDR_29(AHB_IF_0_BIF_1_HADDR_29), 
        .AHB_IF_0_BIF_1_HADDR_26(AHB_IF_0_BIF_1_HADDR_26), 
        .AHB_IF_0_BIF_1_HADDR_27(AHB_IF_0_BIF_1_HADDR_27), 
        .AHB_IF_0_BIF_1_HADDR_9(AHB_IF_0_BIF_1_HADDR_9), 
        .AHB_IF_0_BIF_1_HADDR_8(AHB_IF_0_BIF_1_HADDR_8), 
        .AHB_IF_0_BIF_1_HADDR_7(AHB_IF_0_BIF_1_HADDR_7), 
        .AHB_IF_0_BIF_1_HADDR_6(AHB_IF_0_BIF_1_HADDR_6), 
        .AHB_IF_0_BIF_1_HADDR_5(AHB_IF_0_BIF_1_HADDR_5), 
        .AHB_IF_0_BIF_1_HADDR_4(AHB_IF_0_BIF_1_HADDR_4), 
        .AHB_IF_0_BIF_1_HADDR_3(AHB_IF_0_BIF_1_HADDR_3), 
        .AHB_IF_0_BIF_1_HADDR_2(AHB_IF_0_BIF_1_HADDR_2), 
        .AHB_IF_0_BIF_1_HADDR_1(AHB_IF_0_BIF_1_HADDR_1), 
        .AHB_IF_0_BIF_1_HADDR_0(AHB_IF_0_BIF_1_HADDR_0), .regHADDR_27(
        regHADDR_27), .regHADDR_9(regHADDR_9), .regHADDR_8(regHADDR_8), 
        .regHADDR_7(regHADDR_7), .regHADDR_6(regHADDR_6), .regHADDR_5(
        regHADDR_5), .regHADDR_4(regHADDR_4), .regHADDR_3(regHADDR_3), 
        .regHADDR_2(regHADDR_2), .regHADDR_1(regHADDR_1), .regHADDR_0(
        regHADDR_0), .MSS_HPMS_READY_int_RNIPJE6(
        MSS_HPMS_READY_int_RNIPJE6), .GL0_INST(GL0_INST), .N_106_i_0(
        N_106_i_0), .N_102_i_0(N_102_i_0), .N_100_i_0(N_100_i_0), 
        .N_98_i_0(N_98_i_0), .N_167(N_167), .N_215(N_215), .N_227(
        N_227), .N_259(N_259), .masterRegAddrSel(masterRegAddrSel), 
        .N_165_i_0(N_165_i_0), .N_162_i_0(N_162_i_0), .N_209(N_209), 
        .m0s16AddrSel(m0s16AddrSel), .N_259_i_0(N_259_i_0), 
        .AHB_IF_0_BIF_1_HWRITE(AHB_IF_0_BIF_1_HWRITE), .regHWRITE(
        regHWRITE), .N_150_i_0(N_150_i_0), .N_170(N_170), .N_164_i_0(
        N_164_i_0), .N_163_i_0(N_163_i_0), .masterRegAddrSel_rep1(
        masterRegAddrSel_rep1), .N_161_i_0(N_161_i_0), .N_160_i_0(
        N_160_i_0), .N_159_i_0(N_159_i_0), .N_158_i_0(N_158_i_0), 
        .N_157_i_0(N_157_i_0), .N_156_i_0(N_156_i_0), .N_155_i_0(
        N_155_i_0), .N_154_i_0(N_154_i_0), .N_153_i_0(N_153_i_0), 
        .N_152_i_0(N_152_i_0), .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY));
    CFG2 #( .INIT(4'h8) )  \HWDATA[2]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[2]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[2]));
    CFG4 #( .INIT(16'h3022) )  \HADDR[22]  (.A(AHB_IF_0_BIF_1_HADDR_20)
        , .B(N_259), .C(regHADDR_20), .D(masterRegAddrSel_rep1), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR[22]));
    CFG4 #( .INIT(16'h3022) )  \HADDR[23]  (.A(AHB_IF_0_BIF_1_HADDR_21)
        , .B(N_259), .C(regHADDR_21), .D(masterRegAddrSel_rep1), .Y(
        CoreAHBLite_0_AHBmslave16_HADDR[23]));
    CFG3 #( .INIT(8'hE4) )  g0_2 (.A(masterRegAddrSel_fast), .B(
        HTRANS_1_fast[1]), .C(regHTRANS_fast), .Y(N_167));
    CFG2 #( .INIT(4'h8) )  \HWDATA[11]  (.A(masterDataInProg[0]), .B(
        AHB_IF_0_BIF_1_HWDATA[11]), .Y(
        CoreAHBLite_0_AHBmslave16_HWDATA[11]));
    
endmodule


module COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s(
       AHB_IF_0_BIF_1_HTRANS,
       AHB_IF_0_BIF_1_HADDR,
       HTRANS_1_fast,
       AHB_IF_0_BIF_1_HWDATA,
       CoreAHBLite_0_AHBmslave16_HWDATA,
       CoreAHBLite_0_AHBmslave16_HADDR,
       MSS_HPMS_READY_int_RNIPJE6,
       GL0_INST,
       AHB_IF_0_BIF_1_HWRITE,
       CoreAHBLite_0_AHBmslave16_HREADY,
       HREADY_M_iv,
       HREADY_M_iv_i_0,
       N_259_i_0,
       N_149_i_0,
       N_166_i_0,
       N_165_i_0,
       N_162_i_0,
       N_150_i_0,
       N_164_i_0,
       N_163_i_0,
       N_161_i_0,
       N_160_i_0,
       N_159_i_0,
       N_158_i_0,
       N_157_i_0,
       N_156_i_0,
       N_155_i_0,
       N_154_i_0,
       N_153_i_0,
       N_152_i_0
    );
input  [1:1] AHB_IF_0_BIF_1_HTRANS;
input  [31:2] AHB_IF_0_BIF_1_HADDR;
input  [1:1] HTRANS_1_fast;
input  [13:0] AHB_IF_0_BIF_1_HWDATA;
output [13:0] CoreAHBLite_0_AHBmslave16_HWDATA;
output [27:12] CoreAHBLite_0_AHBmslave16_HADDR;
input  MSS_HPMS_READY_int_RNIPJE6;
input  GL0_INST;
input  AHB_IF_0_BIF_1_HWRITE;
input  CoreAHBLite_0_AHBmslave16_HREADY;
output HREADY_M_iv;
output HREADY_M_iv_i_0;
output N_259_i_0;
output N_149_i_0;
output N_166_i_0;
output N_165_i_0;
output N_162_i_0;
output N_150_i_0;
output N_164_i_0;
output N_163_i_0;
output N_161_i_0;
output N_160_i_0;
output N_159_i_0;
output N_158_i_0;
output N_157_i_0;
output N_156_i_0;
output N_155_i_0;
output N_154_i_0;
output N_153_i_0;
output N_152_i_0;

    wire \regHADDR[23] , \regHADDR[24] , \regHADDR[25] , 
        \regHADDR[26] , \regHADDR[27] , \regHADDR[29] , \regHADDR[8] , 
        \regHADDR[9] , \regHADDR[10] , \regHADDR[11] , \regHADDR[12] , 
        \regHADDR[13] , \regHADDR[14] , \regHADDR[15] , \regHADDR[16] , 
        \regHADDR[17] , \regHADDR[18] , \regHADDR[19] , \regHADDR[20] , 
        \regHADDR[21] , \regHADDR[22] , \regHADDR[2] , \regHADDR[3] , 
        \regHADDR[4] , \regHADDR[5] , \regHADDR[6] , \regHADDR[7] , 
        \arbRegSMCurrentState[0] , \masterDataInProg[0] , m0s16DataSel, 
        m0s16AddrSel, regHTRANS, regHWRITE, masterRegAddrSel, N_227, 
        masterRegAddrSel_fast, masterRegAddrSel_rep1, regHTRANS_fast, 
        N_170, N_102_i_0, N_100_i_0, N_98_i_0, N_106_i_0, N_209, N_321, 
        GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    COREAHBLITE_MASTERSTAGE_1_1_85_65536_0s_0_1_0 masterstage_0 (
        .AHB_IF_0_BIF_1_HTRANS({AHB_IF_0_BIF_1_HTRANS[1]}), 
        .AHB_IF_0_BIF_1_HADDR({AHB_IF_0_BIF_1_HADDR[31], 
        AHB_IF_0_BIF_1_HADDR[30], AHB_IF_0_BIF_1_HADDR[29], 
        AHB_IF_0_BIF_1_HADDR[28], AHB_IF_0_BIF_1_HADDR[27], 
        AHB_IF_0_BIF_1_HADDR[26], AHB_IF_0_BIF_1_HADDR[25], 
        AHB_IF_0_BIF_1_HADDR[24], AHB_IF_0_BIF_1_HADDR[23], 
        AHB_IF_0_BIF_1_HADDR[22], AHB_IF_0_BIF_1_HADDR[21], 
        AHB_IF_0_BIF_1_HADDR[20], AHB_IF_0_BIF_1_HADDR[19], 
        AHB_IF_0_BIF_1_HADDR[18], AHB_IF_0_BIF_1_HADDR[17], 
        AHB_IF_0_BIF_1_HADDR[16], AHB_IF_0_BIF_1_HADDR[15], 
        AHB_IF_0_BIF_1_HADDR[14], AHB_IF_0_BIF_1_HADDR[13], 
        AHB_IF_0_BIF_1_HADDR[12], AHB_IF_0_BIF_1_HADDR[11], 
        AHB_IF_0_BIF_1_HADDR[10], AHB_IF_0_BIF_1_HADDR[9], 
        AHB_IF_0_BIF_1_HADDR[8], AHB_IF_0_BIF_1_HADDR[7], 
        AHB_IF_0_BIF_1_HADDR[6], AHB_IF_0_BIF_1_HADDR[5], 
        AHB_IF_0_BIF_1_HADDR[4], AHB_IF_0_BIF_1_HADDR[3], 
        AHB_IF_0_BIF_1_HADDR[2]}), .arbRegSMCurrentState({
        \arbRegSMCurrentState[0] }), .masterDataInProg({
        \masterDataInProg[0] }), .regHADDR_21(\regHADDR[23] ), 
        .regHADDR_22(\regHADDR[24] ), .regHADDR_23(\regHADDR[25] ), 
        .regHADDR_24(\regHADDR[26] ), .regHADDR_25(\regHADDR[27] ), 
        .regHADDR_27(\regHADDR[29] ), .regHADDR_6(\regHADDR[8] ), 
        .regHADDR_7(\regHADDR[9] ), .regHADDR_8(\regHADDR[10] ), 
        .regHADDR_9(\regHADDR[11] ), .regHADDR_10(\regHADDR[12] ), 
        .regHADDR_11(\regHADDR[13] ), .regHADDR_12(\regHADDR[14] ), 
        .regHADDR_13(\regHADDR[15] ), .regHADDR_14(\regHADDR[16] ), 
        .regHADDR_15(\regHADDR[17] ), .regHADDR_16(\regHADDR[18] ), 
        .regHADDR_17(\regHADDR[19] ), .regHADDR_18(\regHADDR[20] ), 
        .regHADDR_19(\regHADDR[21] ), .regHADDR_20(\regHADDR[22] ), 
        .regHADDR_0(\regHADDR[2] ), .regHADDR_1(\regHADDR[3] ), 
        .regHADDR_2(\regHADDR[4] ), .regHADDR_3(\regHADDR[5] ), 
        .regHADDR_4(\regHADDR[6] ), .regHADDR_5(\regHADDR[7] ), 
        .MSS_HPMS_READY_int_RNIPJE6(MSS_HPMS_READY_int_RNIPJE6), 
        .GL0_INST(GL0_INST), .m0s16DataSel(m0s16DataSel), 
        .m0s16AddrSel(m0s16AddrSel), .regHTRANS(regHTRANS), .regHWRITE(
        regHWRITE), .AHB_IF_0_BIF_1_HWRITE(AHB_IF_0_BIF_1_HWRITE), 
        .masterRegAddrSel(masterRegAddrSel), .N_227(N_227), 
        .masterRegAddrSel_fast(masterRegAddrSel_fast), 
        .masterRegAddrSel_rep1(masterRegAddrSel_rep1), .regHTRANS_fast(
        regHTRANS_fast), .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY), .HREADY_M_iv(HREADY_M_iv), 
        .N_170(N_170), .N_102_i_0(N_102_i_0), .N_100_i_0(N_100_i_0), 
        .N_98_i_0(N_98_i_0), .N_106_i_0(N_106_i_0), .N_209(N_209), 
        .N_321(N_321), .HREADY_M_iv_i_0(HREADY_M_iv_i_0));
    COREAHBLITE_SLAVESTAGE_0s_0_0_0 slavestage_16 (.masterDataInProg({
        \masterDataInProg[0] }), .HTRANS_1_fast({HTRANS_1_fast[1]}), 
        .AHB_IF_0_BIF_1_HWDATA({AHB_IF_0_BIF_1_HWDATA[13], 
        AHB_IF_0_BIF_1_HWDATA[12], AHB_IF_0_BIF_1_HWDATA[11], 
        AHB_IF_0_BIF_1_HWDATA[10], AHB_IF_0_BIF_1_HWDATA[9], 
        AHB_IF_0_BIF_1_HWDATA[8], AHB_IF_0_BIF_1_HWDATA[7], 
        AHB_IF_0_BIF_1_HWDATA[6], AHB_IF_0_BIF_1_HWDATA[5], 
        AHB_IF_0_BIF_1_HWDATA[4], AHB_IF_0_BIF_1_HWDATA[3], 
        AHB_IF_0_BIF_1_HWDATA[2], AHB_IF_0_BIF_1_HWDATA[1], 
        AHB_IF_0_BIF_1_HWDATA[0]}), .CoreAHBLite_0_AHBmslave16_HWDATA({
        CoreAHBLite_0_AHBmslave16_HWDATA[13], 
        CoreAHBLite_0_AHBmslave16_HWDATA[12], 
        CoreAHBLite_0_AHBmslave16_HWDATA[11], 
        CoreAHBLite_0_AHBmslave16_HWDATA[10], 
        CoreAHBLite_0_AHBmslave16_HWDATA[9], 
        CoreAHBLite_0_AHBmslave16_HWDATA[8], 
        CoreAHBLite_0_AHBmslave16_HWDATA[7], 
        CoreAHBLite_0_AHBmslave16_HWDATA[6], 
        CoreAHBLite_0_AHBmslave16_HWDATA[5], 
        CoreAHBLite_0_AHBmslave16_HWDATA[4], 
        CoreAHBLite_0_AHBmslave16_HWDATA[3], 
        CoreAHBLite_0_AHBmslave16_HWDATA[2], 
        CoreAHBLite_0_AHBmslave16_HWDATA[1], 
        CoreAHBLite_0_AHBmslave16_HWDATA[0]}), .AHB_IF_0_BIF_1_HTRANS({
        AHB_IF_0_BIF_1_HTRANS[1]}), .arbRegSMCurrentState({
        \arbRegSMCurrentState[0] }), .CoreAHBLite_0_AHBmslave16_HADDR({
        CoreAHBLite_0_AHBmslave16_HADDR[27], 
        CoreAHBLite_0_AHBmslave16_HADDR[26], 
        CoreAHBLite_0_AHBmslave16_HADDR[25], 
        CoreAHBLite_0_AHBmslave16_HADDR[24], 
        CoreAHBLite_0_AHBmslave16_HADDR[23], 
        CoreAHBLite_0_AHBmslave16_HADDR[22], 
        CoreAHBLite_0_AHBmslave16_HADDR[21], 
        CoreAHBLite_0_AHBmslave16_HADDR[20], 
        CoreAHBLite_0_AHBmslave16_HADDR[19], 
        CoreAHBLite_0_AHBmslave16_HADDR[18], 
        CoreAHBLite_0_AHBmslave16_HADDR[17], 
        CoreAHBLite_0_AHBmslave16_HADDR[16], 
        CoreAHBLite_0_AHBmslave16_HADDR[15], 
        CoreAHBLite_0_AHBmslave16_HADDR[14], 
        CoreAHBLite_0_AHBmslave16_HADDR[13], 
        CoreAHBLite_0_AHBmslave16_HADDR[12]}), 
        .AHB_IF_0_BIF_1_HADDR_29(AHB_IF_0_BIF_1_HADDR[31]), 
        .AHB_IF_0_BIF_1_HADDR_26(AHB_IF_0_BIF_1_HADDR[28]), 
        .AHB_IF_0_BIF_1_HADDR_25(AHB_IF_0_BIF_1_HADDR[27]), 
        .AHB_IF_0_BIF_1_HADDR_24(AHB_IF_0_BIF_1_HADDR[26]), 
        .AHB_IF_0_BIF_1_HADDR_23(AHB_IF_0_BIF_1_HADDR[25]), 
        .AHB_IF_0_BIF_1_HADDR_22(AHB_IF_0_BIF_1_HADDR[24]), 
        .AHB_IF_0_BIF_1_HADDR_21(AHB_IF_0_BIF_1_HADDR[23]), 
        .AHB_IF_0_BIF_1_HADDR_20(AHB_IF_0_BIF_1_HADDR[22]), 
        .AHB_IF_0_BIF_1_HADDR_19(AHB_IF_0_BIF_1_HADDR[21]), 
        .AHB_IF_0_BIF_1_HADDR_18(AHB_IF_0_BIF_1_HADDR[20]), 
        .AHB_IF_0_BIF_1_HADDR_17(AHB_IF_0_BIF_1_HADDR[19]), 
        .AHB_IF_0_BIF_1_HADDR_16(AHB_IF_0_BIF_1_HADDR[18]), 
        .AHB_IF_0_BIF_1_HADDR_15(AHB_IF_0_BIF_1_HADDR[17]), 
        .AHB_IF_0_BIF_1_HADDR_14(AHB_IF_0_BIF_1_HADDR[16]), 
        .AHB_IF_0_BIF_1_HADDR_13(AHB_IF_0_BIF_1_HADDR[15]), 
        .AHB_IF_0_BIF_1_HADDR_12(AHB_IF_0_BIF_1_HADDR[14]), 
        .AHB_IF_0_BIF_1_HADDR_11(AHB_IF_0_BIF_1_HADDR[13]), 
        .AHB_IF_0_BIF_1_HADDR_10(AHB_IF_0_BIF_1_HADDR[12]), 
        .AHB_IF_0_BIF_1_HADDR_27(AHB_IF_0_BIF_1_HADDR[29]), 
        .AHB_IF_0_BIF_1_HADDR_9(AHB_IF_0_BIF_1_HADDR[11]), 
        .AHB_IF_0_BIF_1_HADDR_8(AHB_IF_0_BIF_1_HADDR[10]), 
        .AHB_IF_0_BIF_1_HADDR_7(AHB_IF_0_BIF_1_HADDR[9]), 
        .AHB_IF_0_BIF_1_HADDR_6(AHB_IF_0_BIF_1_HADDR[8]), 
        .AHB_IF_0_BIF_1_HADDR_5(AHB_IF_0_BIF_1_HADDR[7]), 
        .AHB_IF_0_BIF_1_HADDR_4(AHB_IF_0_BIF_1_HADDR[6]), 
        .AHB_IF_0_BIF_1_HADDR_3(AHB_IF_0_BIF_1_HADDR[5]), 
        .AHB_IF_0_BIF_1_HADDR_2(AHB_IF_0_BIF_1_HADDR[4]), 
        .AHB_IF_0_BIF_1_HADDR_1(AHB_IF_0_BIF_1_HADDR[3]), 
        .AHB_IF_0_BIF_1_HADDR_0(AHB_IF_0_BIF_1_HADDR[2]), .regHADDR_25(
        \regHADDR[27] ), .regHADDR_24(\regHADDR[26] ), .regHADDR_23(
        \regHADDR[25] ), .regHADDR_22(\regHADDR[24] ), .regHADDR_21(
        \regHADDR[23] ), .regHADDR_20(\regHADDR[22] ), .regHADDR_19(
        \regHADDR[21] ), .regHADDR_18(\regHADDR[20] ), .regHADDR_17(
        \regHADDR[19] ), .regHADDR_16(\regHADDR[18] ), .regHADDR_15(
        \regHADDR[17] ), .regHADDR_14(\regHADDR[16] ), .regHADDR_13(
        \regHADDR[15] ), .regHADDR_12(\regHADDR[14] ), .regHADDR_11(
        \regHADDR[13] ), .regHADDR_10(\regHADDR[12] ), .regHADDR_27(
        \regHADDR[29] ), .regHADDR_9(\regHADDR[11] ), .regHADDR_8(
        \regHADDR[10] ), .regHADDR_7(\regHADDR[9] ), .regHADDR_6(
        \regHADDR[8] ), .regHADDR_5(\regHADDR[7] ), .regHADDR_4(
        \regHADDR[6] ), .regHADDR_3(\regHADDR[5] ), .regHADDR_2(
        \regHADDR[4] ), .regHADDR_1(\regHADDR[3] ), .regHADDR_0(
        \regHADDR[2] ), .MSS_HPMS_READY_int_RNIPJE6(
        MSS_HPMS_READY_int_RNIPJE6), .GL0_INST(GL0_INST), .N_259_i_0(
        N_259_i_0), .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY), .masterRegAddrSel_fast(
        masterRegAddrSel_fast), .regHTRANS_fast(regHTRANS_fast), 
        .m0s16DataSel(m0s16DataSel), .N_321(N_321), .N_149_i_0(
        N_149_i_0), .regHTRANS(regHTRANS), .masterRegAddrSel_rep1(
        masterRegAddrSel_rep1), .N_227(N_227), .masterRegAddrSel(
        masterRegAddrSel), .N_166_i_0(N_166_i_0), .N_106_i_0(N_106_i_0)
        , .N_102_i_0(N_102_i_0), .N_100_i_0(N_100_i_0), .N_98_i_0(
        N_98_i_0), .N_165_i_0(N_165_i_0), .N_162_i_0(N_162_i_0), 
        .N_209(N_209), .m0s16AddrSel(m0s16AddrSel), 
        .AHB_IF_0_BIF_1_HWRITE(AHB_IF_0_BIF_1_HWRITE), .regHWRITE(
        regHWRITE), .N_150_i_0(N_150_i_0), .N_170(N_170), .N_164_i_0(
        N_164_i_0), .N_163_i_0(N_163_i_0), .N_161_i_0(N_161_i_0), 
        .N_160_i_0(N_160_i_0), .N_159_i_0(N_159_i_0), .N_158_i_0(
        N_158_i_0), .N_157_i_0(N_157_i_0), .N_156_i_0(N_156_i_0), 
        .N_155_i_0(N_155_i_0), .N_154_i_0(N_154_i_0), .N_153_i_0(
        N_153_i_0), .N_152_i_0(N_152_i_0));
    
endmodule


module CoreAHBLite_Z6(
       AHB_IF_0_BIF_1_HTRANS,
       AHB_IF_0_BIF_1_HADDR,
       HTRANS_1_fast,
       AHB_IF_0_BIF_1_HWDATA,
       CoreAHBLite_0_AHBmslave16_HWDATA,
       CoreAHBLite_0_AHBmslave16_HADDR,
       MSS_HPMS_READY_int_RNIPJE6,
       GL0_INST,
       AHB_IF_0_BIF_1_HWRITE,
       CoreAHBLite_0_AHBmslave16_HREADY,
       HREADY_M_iv,
       HREADY_M_iv_i_0,
       N_259_i_0,
       N_149_i_0,
       N_166_i_0,
       N_165_i_0,
       N_162_i_0,
       N_150_i_0,
       N_164_i_0,
       N_163_i_0,
       N_161_i_0,
       N_160_i_0,
       N_159_i_0,
       N_158_i_0,
       N_157_i_0,
       N_156_i_0,
       N_155_i_0,
       N_154_i_0,
       N_153_i_0,
       N_152_i_0
    );
input  [1:1] AHB_IF_0_BIF_1_HTRANS;
input  [31:2] AHB_IF_0_BIF_1_HADDR;
input  [1:1] HTRANS_1_fast;
input  [13:0] AHB_IF_0_BIF_1_HWDATA;
output [13:0] CoreAHBLite_0_AHBmslave16_HWDATA;
output [27:12] CoreAHBLite_0_AHBmslave16_HADDR;
input  MSS_HPMS_READY_int_RNIPJE6;
input  GL0_INST;
input  AHB_IF_0_BIF_1_HWRITE;
input  CoreAHBLite_0_AHBmslave16_HREADY;
output HREADY_M_iv;
output HREADY_M_iv_i_0;
output N_259_i_0;
output N_149_i_0;
output N_166_i_0;
output N_165_i_0;
output N_162_i_0;
output N_150_i_0;
output N_164_i_0;
output N_163_i_0;
output N_161_i_0;
output N_160_i_0;
output N_159_i_0;
output N_158_i_0;
output N_157_i_0;
output N_156_i_0;
output N_155_i_0;
output N_154_i_0;
output N_153_i_0;
output N_152_i_0;

    wire GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    COREAHBLITE_MATRIX4X16_1_1_85_65536_0_0_0_0s matrix4x16 (
        .AHB_IF_0_BIF_1_HTRANS({AHB_IF_0_BIF_1_HTRANS[1]}), 
        .AHB_IF_0_BIF_1_HADDR({AHB_IF_0_BIF_1_HADDR[31], 
        AHB_IF_0_BIF_1_HADDR[30], AHB_IF_0_BIF_1_HADDR[29], 
        AHB_IF_0_BIF_1_HADDR[28], AHB_IF_0_BIF_1_HADDR[27], 
        AHB_IF_0_BIF_1_HADDR[26], AHB_IF_0_BIF_1_HADDR[25], 
        AHB_IF_0_BIF_1_HADDR[24], AHB_IF_0_BIF_1_HADDR[23], 
        AHB_IF_0_BIF_1_HADDR[22], AHB_IF_0_BIF_1_HADDR[21], 
        AHB_IF_0_BIF_1_HADDR[20], AHB_IF_0_BIF_1_HADDR[19], 
        AHB_IF_0_BIF_1_HADDR[18], AHB_IF_0_BIF_1_HADDR[17], 
        AHB_IF_0_BIF_1_HADDR[16], AHB_IF_0_BIF_1_HADDR[15], 
        AHB_IF_0_BIF_1_HADDR[14], AHB_IF_0_BIF_1_HADDR[13], 
        AHB_IF_0_BIF_1_HADDR[12], AHB_IF_0_BIF_1_HADDR[11], 
        AHB_IF_0_BIF_1_HADDR[10], AHB_IF_0_BIF_1_HADDR[9], 
        AHB_IF_0_BIF_1_HADDR[8], AHB_IF_0_BIF_1_HADDR[7], 
        AHB_IF_0_BIF_1_HADDR[6], AHB_IF_0_BIF_1_HADDR[5], 
        AHB_IF_0_BIF_1_HADDR[4], AHB_IF_0_BIF_1_HADDR[3], 
        AHB_IF_0_BIF_1_HADDR[2]}), .HTRANS_1_fast({HTRANS_1_fast[1]}), 
        .AHB_IF_0_BIF_1_HWDATA({AHB_IF_0_BIF_1_HWDATA[13], 
        AHB_IF_0_BIF_1_HWDATA[12], AHB_IF_0_BIF_1_HWDATA[11], 
        AHB_IF_0_BIF_1_HWDATA[10], AHB_IF_0_BIF_1_HWDATA[9], 
        AHB_IF_0_BIF_1_HWDATA[8], AHB_IF_0_BIF_1_HWDATA[7], 
        AHB_IF_0_BIF_1_HWDATA[6], AHB_IF_0_BIF_1_HWDATA[5], 
        AHB_IF_0_BIF_1_HWDATA[4], AHB_IF_0_BIF_1_HWDATA[3], 
        AHB_IF_0_BIF_1_HWDATA[2], AHB_IF_0_BIF_1_HWDATA[1], 
        AHB_IF_0_BIF_1_HWDATA[0]}), .CoreAHBLite_0_AHBmslave16_HWDATA({
        CoreAHBLite_0_AHBmslave16_HWDATA[13], 
        CoreAHBLite_0_AHBmslave16_HWDATA[12], 
        CoreAHBLite_0_AHBmslave16_HWDATA[11], 
        CoreAHBLite_0_AHBmslave16_HWDATA[10], 
        CoreAHBLite_0_AHBmslave16_HWDATA[9], 
        CoreAHBLite_0_AHBmslave16_HWDATA[8], 
        CoreAHBLite_0_AHBmslave16_HWDATA[7], 
        CoreAHBLite_0_AHBmslave16_HWDATA[6], 
        CoreAHBLite_0_AHBmslave16_HWDATA[5], 
        CoreAHBLite_0_AHBmslave16_HWDATA[4], 
        CoreAHBLite_0_AHBmslave16_HWDATA[3], 
        CoreAHBLite_0_AHBmslave16_HWDATA[2], 
        CoreAHBLite_0_AHBmslave16_HWDATA[1], 
        CoreAHBLite_0_AHBmslave16_HWDATA[0]}), 
        .CoreAHBLite_0_AHBmslave16_HADDR({
        CoreAHBLite_0_AHBmslave16_HADDR[27], 
        CoreAHBLite_0_AHBmslave16_HADDR[26], 
        CoreAHBLite_0_AHBmslave16_HADDR[25], 
        CoreAHBLite_0_AHBmslave16_HADDR[24], 
        CoreAHBLite_0_AHBmslave16_HADDR[23], 
        CoreAHBLite_0_AHBmslave16_HADDR[22], 
        CoreAHBLite_0_AHBmslave16_HADDR[21], 
        CoreAHBLite_0_AHBmslave16_HADDR[20], 
        CoreAHBLite_0_AHBmslave16_HADDR[19], 
        CoreAHBLite_0_AHBmslave16_HADDR[18], 
        CoreAHBLite_0_AHBmslave16_HADDR[17], 
        CoreAHBLite_0_AHBmslave16_HADDR[16], 
        CoreAHBLite_0_AHBmslave16_HADDR[15], 
        CoreAHBLite_0_AHBmslave16_HADDR[14], 
        CoreAHBLite_0_AHBmslave16_HADDR[13], 
        CoreAHBLite_0_AHBmslave16_HADDR[12]}), 
        .MSS_HPMS_READY_int_RNIPJE6(MSS_HPMS_READY_int_RNIPJE6), 
        .GL0_INST(GL0_INST), .AHB_IF_0_BIF_1_HWRITE(
        AHB_IF_0_BIF_1_HWRITE), .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY), .HREADY_M_iv(HREADY_M_iv), 
        .HREADY_M_iv_i_0(HREADY_M_iv_i_0), .N_259_i_0(N_259_i_0), 
        .N_149_i_0(N_149_i_0), .N_166_i_0(N_166_i_0), .N_165_i_0(
        N_165_i_0), .N_162_i_0(N_162_i_0), .N_150_i_0(N_150_i_0), 
        .N_164_i_0(N_164_i_0), .N_163_i_0(N_163_i_0), .N_161_i_0(
        N_161_i_0), .N_160_i_0(N_160_i_0), .N_159_i_0(N_159_i_0), 
        .N_158_i_0(N_158_i_0), .N_157_i_0(N_157_i_0), .N_156_i_0(
        N_156_i_0), .N_155_i_0(N_155_i_0), .N_154_i_0(N_154_i_0), 
        .N_153_i_0(N_153_i_0), .N_152_i_0(N_152_i_0));
    GND GND (.Y(GND_net_1));
    
endmodule


module MDDR_TA_CCC_0_FCCC(
       MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK,
       MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK_i_0,
       GL0_INST,
       LOCK,
       FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
    );
output MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK;
output MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK_i_0;
output GL0_INST;
output LOCK;
input  FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC;

    wire GL0_net, GL2_net, VCC_net_1, GND_net_1;
    
    CFG1 #( .INIT(2'h1) )  GL2_INST_RNI0QN4 (.A(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .Y(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK_i_0));
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    CLKINT GL2_INST (.A(GL2_net), .Y(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK));
    CLKINT GL0_INST_inst_1 (.A(GL0_net), .Y(GL0_INST));
    CCC #( .INIT(210'h0000007F88000044164000718C2318C2318C1DEC0404041434031)
        , .VCOFREQUENCY(833.0) )  CCC_INST (.Y0(), .Y1(), .Y2(), .Y3(), 
        .PRDATA({nc0, nc1, nc2, nc3, nc4, nc5, nc6, nc7}), .LOCK(LOCK), 
        .BUSY(), .CLK0(VCC_net_1), .CLK1(VCC_net_1), .CLK2(VCC_net_1), 
        .CLK3(VCC_net_1), .NGMUX0_SEL(GND_net_1), .NGMUX1_SEL(
        GND_net_1), .NGMUX2_SEL(GND_net_1), .NGMUX3_SEL(GND_net_1), 
        .NGMUX0_HOLD_N(VCC_net_1), .NGMUX1_HOLD_N(VCC_net_1), 
        .NGMUX2_HOLD_N(VCC_net_1), .NGMUX3_HOLD_N(VCC_net_1), 
        .NGMUX0_ARST_N(VCC_net_1), .NGMUX1_ARST_N(VCC_net_1), 
        .NGMUX2_ARST_N(VCC_net_1), .NGMUX3_ARST_N(VCC_net_1), 
        .PLL_BYPASS_N(VCC_net_1), .PLL_ARST_N(VCC_net_1), 
        .PLL_POWERDOWN_N(VCC_net_1), .GPD0_ARST_N(VCC_net_1), 
        .GPD1_ARST_N(VCC_net_1), .GPD2_ARST_N(VCC_net_1), .GPD3_ARST_N(
        VCC_net_1), .PRESET_N(GND_net_1), .PCLK(VCC_net_1), .PSEL(
        VCC_net_1), .PENABLE(VCC_net_1), .PWRITE(VCC_net_1), .PADDR({
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1}), .PWDATA({VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .CLK0_PAD(GND_net_1), .CLK1_PAD(GND_net_1), .CLK2_PAD(
        GND_net_1), .CLK3_PAD(GND_net_1), .GL0(GL0_net), .GL1(), .GL2(
        GL2_net), .GL3(), .RCOSC_25_50MHZ(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC), 
        .RCOSC_1MHZ(GND_net_1), .XTLOSC(GND_net_1));
    
endmodule


module CoreConfigP_Z9(
       CORECONFIGP_0_MDDR_APBmslave_PADDR,
       CORECONFIGP_0_MDDR_APBmslave_PWDATA,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA,
       CORECONFIGP_0_MDDR_APBmslave_PRDATA,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_11,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_13,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_14,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_3,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_4,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_5,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_6,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_7,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_8,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_10,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_4,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_5,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_6,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_7,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_8,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_9,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_10,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_11,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_12,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_13,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_14,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_15,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_16,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_18,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_0,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_1,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_2,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_3,
       CORECONFIGP_0_SOFT_RESET_F2M_i_0,
       CORECONFIGP_0_SOFT_M3_RESET_i_0,
       CORECONFIGP_0_APB_S_PRESET_N,
       CORECONFIGP_0_APB_S_PCLK,
       CORECONFIGP_0_CONFIG1_DONE,
       CORECONFIGP_0_CONFIG2_DONE,
       CORECONFIGP_0_SOFT_MDDR_DDR_AXI_S_CORE_RESET,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PREADY,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSLVERR,
       CORECONFIGP_0_MDDR_APBmslave_PWRITE,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE,
       CORECONFIGP_0_MDDR_APBmslave_PENABLE,
       CORECONFIGP_0_APB_S_PCLK_i_0,
       INIT_DONE,
       CORECONFIGP_0_MDDR_APBmslave_PSELx,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSELx,
       CORECONFIGP_0_MDDR_APBmslave_PSLVERR,
       CORECONFIGP_0_MDDR_APBmslave_PREADY
    );
output [10:2] CORECONFIGP_0_MDDR_APBmslave_PADDR;
output [15:0] CORECONFIGP_0_MDDR_APBmslave_PWDATA;
input  [16:0] MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA;
input  [15:0] CORECONFIGP_0_MDDR_APBmslave_PRDATA;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_11;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_13;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_14;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_3;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_4;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_5;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_6;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_7;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_8;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_10;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_4;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_5;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_6;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_7;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_8;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_9;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_10;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_11;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_12;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_13;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_14;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_15;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_16;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_18;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_0;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_1;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_2;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_3;
output CORECONFIGP_0_SOFT_RESET_F2M_i_0;
output CORECONFIGP_0_SOFT_M3_RESET_i_0;
input  CORECONFIGP_0_APB_S_PRESET_N;
input  CORECONFIGP_0_APB_S_PCLK;
output CORECONFIGP_0_CONFIG1_DONE;
output CORECONFIGP_0_CONFIG2_DONE;
output CORECONFIGP_0_SOFT_MDDR_DDR_AXI_S_CORE_RESET;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PREADY;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSLVERR;
output CORECONFIGP_0_MDDR_APBmslave_PWRITE;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE;
output CORECONFIGP_0_MDDR_APBmslave_PENABLE;
input  CORECONFIGP_0_APB_S_PCLK_i_0;
input  INIT_DONE;
output CORECONFIGP_0_MDDR_APBmslave_PSELx;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSELx;
input  CORECONFIGP_0_MDDR_APBmslave_PSLVERR;
input  CORECONFIGP_0_MDDR_APBmslave_PREADY;

    wire CORECONFIGP_0_SOFT_RESET_F2M, CORECONFIGP_0_SOFT_M3_RESET, 
        \paddr[13]_net_1 , VCC_net_1, state_458_d, GND_net_1, 
        \paddr[15]_net_1 , \paddr[16]_net_1 , \paddr[12]_net_1 , 
        \soft_reset_reg[15]_net_1 , soft_reset_reg6, 
        \soft_reset_reg[16]_net_1 , control_reg_15, 
        \soft_reset_reg[0]_net_1 , \soft_reset_reg[4]_net_1 , 
        \soft_reset_reg[5]_net_1 , \soft_reset_reg[6]_net_1 , 
        \soft_reset_reg[7]_net_1 , \soft_reset_reg[8]_net_1 , 
        \soft_reset_reg[9]_net_1 , \soft_reset_reg[10]_net_1 , 
        \soft_reset_reg[11]_net_1 , \soft_reset_reg[12]_net_1 , 
        \soft_reset_reg[13]_net_1 , \soft_reset_reg[14]_net_1 , 
        \prdata[4] , \state[1]_net_1 , \prdata[5] , \prdata[6] , 
        \prdata[7] , \prdata[8] , \prdata[9] , \prdata[10] , 
        \prdata[11] , \prdata[12] , \prdata[13] , \prdata[14] , 
        \prdata[15] , N_12_i_0, N_7_i_0, \prdata[0] , \prdata[1] , 
        \prdata[2] , \prdata[3] , \state[0]_net_1 , \state_ns[0] , 
        \state_ns[1] , N_28_i_0, pslverr, MDDR_PENABLE_2, psel_net_1, 
        state_458_d_i_0, INIT_DONE_q1_net_1, INIT_DONE_q2_net_1, N_96, 
        N_93, N_90, \prdata_0_iv_0_1[1]_net_1 , control_reg_15_1, N_33, 
        N_42, N_43, control_reg_15_3, N_50, N_47, N_44, N_52, N_48;
    
    SLE \soft_reset_reg[13]  (.D(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[13]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[13]_net_1 ));
    SLE \pwdata[15]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[15])
        , .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[15]));
    CFG4 #( .INIT(16'h3B33) )  \prdata_0_iv_0[1]  (.A(N_90), .B(
        \prdata_0_iv_0_1[1]_net_1 ), .C(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2), .D(
        CORECONFIGP_0_CONFIG2_DONE), .Y(\prdata[1] ));
    SLE \FIC_2_APB_M_PRDATA[13]  (.D(\prdata[13] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_13));
    SLE \pwdata[8]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[8]), 
        .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[8]));
    SLE \pwdata[3]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[3]), 
        .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[3]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_0_iv_0[15]  (.A(
        \soft_reset_reg[15]_net_1 ), .B(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[15]), .C(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .D(N_93), .Y(\prdata[15] )
        );
    SLE \paddr[16]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_14), 
        .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(\paddr[16]_net_1 ));
    SLE \soft_reset_reg[10]  (.D(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[10]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[10]_net_1 ));
    SLE \paddr[8]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_6), 
        .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[8]));
    CFG4 #( .INIT(16'h3020) )  \FIC_2_APB_M_PRDATA_RNO[16]  (.A(
        \soft_reset_reg[16]_net_1 ), .B(N_44), .C(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2), .D(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0), .Y(N_12_i_0));
    SLE \soft_reset_reg[2]  (.D(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[2]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_SOFT_M3_RESET));
    SLE \pwdata[5]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[5]), 
        .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[5]));
    CFG2 #( .INIT(4'h8) )  \prdata_0_iv_0_a2_1[5]  (.A(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .B(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[5]), .Y(N_52));
    CFG3 #( .INIT(8'h20) )  \FIC_2_APB_M_PRDATA_RNO[17]  (.A(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0), .B(N_44), .C(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2), .Y(N_7_i_0));
    CFG4 #( .INIT(16'hAEAA) )  \state_ns_0_0[1]  (.A(\state[0]_net_1 ), 
        .B(\state[1]_net_1 ), .C(CORECONFIGP_0_MDDR_APBmslave_PREADY), 
        .D(CORECONFIGP_0_MDDR_APBmslave_PSELx), .Y(\state_ns[1] ));
    SLE \paddr[5]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_3), 
        .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[5]));
    CFG2 #( .INIT(4'hE) )  int_prdata_5_sqmuxa_i_o2 (.A(N_96), .B(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1), .Y(N_44));
    SLE INIT_DONE_q1 (.D(INIT_DONE), .CLK(CORECONFIGP_0_APB_S_PCLK), 
        .EN(VCC_net_1), .ALn(CORECONFIGP_0_APB_S_PRESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(INIT_DONE_q1_net_1));
    CFG2 #( .INIT(4'h1) )  
        un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_a3_0_a2 (.A(N_43), .B(
        \state[1]_net_1 ), .Y(\state_ns[0] ));
    SLE \paddr[3]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1), 
        .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[3]));
    SLE \FIC_2_APB_M_PRDATA[5]  (.D(\prdata[5] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_5));
    SLE \pwdata[9]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[9]), 
        .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[9]));
    SLE \FIC_2_APB_M_PRDATA[9]  (.D(\prdata[9] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_9));
    SLE \control_reg_1[0]  (.D(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[0]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(control_reg_15), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_CONFIG1_DONE));
    SLE FIC_2_APB_M_PREADY (.D(\state[1]_net_1 ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(N_28_i_0), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(GND_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PREADY));
    CFG4 #( .INIT(16'h8000) )  soft_reset_reg6_0_a2 (.A(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE), .B(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2), .C(
        control_reg_15_3), .D(control_reg_15_1), .Y(soft_reset_reg6));
    SLE \pwdata[7]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[7]), 
        .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[7]));
    SLE \soft_reset_reg[9]  (.D(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[9]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[9]_net_1 ));
    SLE \FIC_2_APB_M_PRDATA[14]  (.D(\prdata[14] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_14));
    VCC VCC (.Y(VCC_net_1));
    SLE \pwdata[1]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[1]), 
        .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[1]));
    SLE \pwdata[13]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[13])
        , .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[13]));
    CFG4 #( .INIT(16'h0100) )  \prdata_0_iv_0_a3[0]  (.A(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1), .B(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0), .C(N_96), .D(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2), .Y(N_93));
    SLE psel (.D(state_458_d_i_0), .CLK(CORECONFIGP_0_APB_S_PCLK_i_0), 
        .EN(VCC_net_1), .ALn(CORECONFIGP_0_APB_S_PRESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(psel_net_1));
    SLE \FIC_2_APB_M_PRDATA[11]  (.D(\prdata[11] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_11));
    SLE pwrite (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWRITE));
    SLE \pwdata[6]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[6]), 
        .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[6]));
    SLE \paddr[12]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_10), 
        .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(\paddr[12]_net_1 ));
    CFG4 #( .INIT(16'hB0BF) )  FIC_2_APB_M_PREADY_RNO (.A(
        CORECONFIGP_0_MDDR_APBmslave_PREADY), .B(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .C(\state[1]_net_1 ), .D(
        N_43), .Y(N_28_i_0));
    CFG1 #( .INIT(2'h1) )  \soft_reset_reg_RNI95NE[2]  (.A(
        CORECONFIGP_0_SOFT_M3_RESET), .Y(
        CORECONFIGP_0_SOFT_M3_RESET_i_0));
    CFG1 #( .INIT(2'h1) )  \soft_reset_reg_RNI84NE[1]  (.A(
        CORECONFIGP_0_SOFT_RESET_F2M), .Y(
        CORECONFIGP_0_SOFT_RESET_F2M_i_0));
    SLE \paddr[13]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_11), 
        .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(\paddr[13]_net_1 ));
    SLE FIC_2_APB_M_PSLVERR (.D(pslverr), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSLVERR));
    SLE \FIC_2_APB_M_PRDATA[17]  (.D(N_7_i_0), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_18));
    CFG2 #( .INIT(4'h8) )  \prdata_0_iv_0_a2_0[0]  (.A(N_93), .B(
        \soft_reset_reg[0]_net_1 ), .Y(N_48));
    SLE \FIC_2_APB_M_PRDATA[7]  (.D(\prdata[7] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_7));
    CFG4 #( .INIT(16'h0200) )  \prdata_0_iv_0_a2[5]  (.A(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0), .B(N_96), .C(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2), .D(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1), .Y(N_50));
    SLE \soft_reset_reg[0]  (.D(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[0]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[0]_net_1 ));
    SLE \pwdata[2]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[2]), 
        .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[2]));
    CFG4 #( .INIT(16'h153F) )  \prdata_0_iv_0_1[1]  (.A(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[1]), .B(N_93), .C(
        CORECONFIGP_0_SOFT_RESET_F2M), .D(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .Y(
        \prdata_0_iv_0_1[1]_net_1 ));
    SLE \FIC_2_APB_M_PRDATA[0]  (.D(\prdata[0] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_0));
    CFG3 #( .INIT(8'hFD) )  
        un1_next_FIC_2_APB_M_PREADY_0_sqmuxa_0_i_o3 (.A(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSELx), .B(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE), .C(
        \state[0]_net_1 ), .Y(N_43));
    SLE \soft_reset_reg[15]  (.D(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[15]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[15]_net_1 ));
    SLE \paddr[7]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_5), 
        .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[7]));
    SLE \FIC_2_APB_M_PRDATA[3]  (.D(\prdata[3] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_3));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_0_iv_0[9]  (.A(
        \soft_reset_reg[9]_net_1 ), .B(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[9]), .C(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .D(N_93), .Y(\prdata[9] ));
    SLE \FIC_2_APB_M_PRDATA[6]  (.D(\prdata[6] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_6));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_0_iv_0[7]  (.A(
        \soft_reset_reg[7]_net_1 ), .B(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[7]), .C(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .D(N_93), .Y(\prdata[7] ));
    CFG2 #( .INIT(4'hE) )  soft_reset_reg6_0_o3_0 (.A(
        \paddr[15]_net_1 ), .B(\paddr[16]_net_1 ), .Y(N_33));
    CFG4 #( .INIT(16'hFFF8) )  \prdata_0_iv_0[0]  (.A(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[0]), .B(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .C(N_47), .D(N_48), .Y(
        \prdata[0] ));
    SLE \paddr[6]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_4), 
        .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[6]));
    SLE \control_reg_1[1]  (.D(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[1]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(control_reg_15), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_CONFIG2_DONE));
    SLE \pwdata[11]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[11])
        , .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[11]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_0_iv_0[13]  (.A(
        \soft_reset_reg[13]_net_1 ), .B(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[13]), .C(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .D(N_93), .Y(\prdata[13] )
        );
    GND GND (.Y(GND_net_1));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_0_iv_0[14]  (.A(
        \soft_reset_reg[14]_net_1 ), .B(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[14]), .C(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .D(N_93), .Y(\prdata[14] )
        );
    SLE \soft_reset_reg[3]  (.D(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[3]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_SOFT_MDDR_DDR_AXI_S_CORE_RESET));
    SLE \soft_reset_reg[12]  (.D(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[12]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[12]_net_1 ));
    CFG2 #( .INIT(4'h8) )  FIC_2_APB_M_PSLVERR_RNO (.A(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .B(
        CORECONFIGP_0_MDDR_APBmslave_PSLVERR), .Y(pslverr));
    SLE \state[0]  (.D(\state_ns[0] ), .CLK(CORECONFIGP_0_APB_S_PCLK), 
        .EN(VCC_net_1), .ALn(CORECONFIGP_0_APB_S_PRESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\state[0]_net_1 ));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_0_iv_0[8]  (.A(
        \soft_reset_reg[8]_net_1 ), .B(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[8]), .C(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .D(N_93), .Y(\prdata[8] ));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_0_iv_0[10]  (.A(
        \soft_reset_reg[10]_net_1 ), .B(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[10]), .C(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .D(N_93), .Y(\prdata[10] )
        );
    CFG2 #( .INIT(4'hE) )  state_s0_0_a2_0_a2_i (.A(\state[1]_net_1 ), 
        .B(\state[0]_net_1 ), .Y(state_458_d_i_0));
    CFG4 #( .INIT(16'h2000) )  control_reg_15_0_a2 (.A(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE), .B(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2), .C(
        control_reg_15_3), .D(control_reg_15_1), .Y(control_reg_15));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_0_iv_0[6]  (.A(
        \soft_reset_reg[6]_net_1 ), .B(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[6]), .C(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .D(N_93), .Y(\prdata[6] ));
    SLE \pwdata[14]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[14])
        , .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[14]));
    CFG4 #( .INIT(16'h0010) )  MDDR_PSEL_0_a3 (.A(\paddr[13]_net_1 ), 
        .B(\paddr[12]_net_1 ), .C(psel_net_1), .D(N_33), .Y(
        CORECONFIGP_0_MDDR_APBmslave_PSELx));
    CFG3 #( .INIT(8'hE2) )  \prdata_0_iv_0_m3[0]  (.A(
        CORECONFIGP_0_CONFIG1_DONE), .B(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0), .C(
        INIT_DONE_q2_net_1), .Y(N_42));
    SLE \soft_reset_reg[4]  (.D(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[4]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[4]_net_1 ));
    SLE \soft_reset_reg[8]  (.D(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[8]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[8]_net_1 ));
    CFG4 #( .INIT(16'h0100) )  \prdata_0_iv_0_a2[0]  (.A(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1), .B(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2), .C(N_96), .D(N_42)
        , .Y(N_47));
    SLE MDDR_PENABLE (.D(MDDR_PENABLE_2), .CLK(
        CORECONFIGP_0_APB_S_PCLK_i_0), .EN(VCC_net_1), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PENABLE));
    SLE \FIC_2_APB_M_PRDATA[12]  (.D(\prdata[12] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_12));
    SLE \FIC_2_APB_M_PRDATA[16]  (.D(N_12_i_0), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_16));
    CFG4 #( .INIT(16'h0010) )  MDDR_PENABLE_2_0_a2 (.A(
        \paddr[13]_net_1 ), .B(\paddr[12]_net_1 ), .C(\state[1]_net_1 )
        , .D(N_33), .Y(MDDR_PENABLE_2));
    CFG4 #( .INIT(16'h0002) )  control_reg_15_0_a2_3 (.A(
        \paddr[13]_net_1 ), .B(N_33), .C(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1), .D(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0), .Y(
        control_reg_15_3));
    SLE \FIC_2_APB_M_PRDATA[2]  (.D(\prdata[2] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_2));
    SLE \pwdata[10]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[10])
        , .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[10]));
    SLE INIT_DONE_q2 (.D(INIT_DONE_q1_net_1), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(VCC_net_1), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(INIT_DONE_q2_net_1));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_0_iv_0[11]  (.A(
        \soft_reset_reg[11]_net_1 ), .B(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[11]), .C(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .D(N_93), .Y(\prdata[11] )
        );
    SLE \state[1]  (.D(\state_ns[1] ), .CLK(CORECONFIGP_0_APB_S_PCLK), 
        .EN(VCC_net_1), .ALn(CORECONFIGP_0_APB_S_PRESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\state[1]_net_1 ));
    SLE \soft_reset_reg[6]  (.D(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[6]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[6]_net_1 ));
    CFG4 #( .INIT(16'hECA0) )  \prdata_0_iv_0[3]  (.A(N_93), .B(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[3]), .C(
        CORECONFIGP_0_SOFT_MDDR_DDR_AXI_S_CORE_RESET), .D(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .Y(\prdata[3] ));
    SLE \FIC_2_APB_M_PRDATA[8]  (.D(\prdata[8] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_8));
    SLE \FIC_2_APB_M_PRDATA[4]  (.D(\prdata[4] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_4));
    CFG2 #( .INIT(4'h8) )  control_reg_15_0_a2_1 (.A(psel_net_1), .B(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE), .Y(
        control_reg_15_1));
    SLE \soft_reset_reg[7]  (.D(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[7]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[7]_net_1 ));
    SLE \soft_reset_reg[11]  (.D(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[11]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[11]_net_1 ));
    SLE \paddr[4]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2), 
        .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[4]));
    SLE \pwdata[12]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[12])
        , .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[12]));
    SLE \paddr[9]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_7), 
        .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[9]));
    SLE \soft_reset_reg[1]  (.D(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[1]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_SOFT_RESET_F2M));
    SLE \soft_reset_reg[16]  (.D(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[16]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[16]_net_1 ));
    SLE \pwdata[0]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[0]), 
        .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[0]));
    SLE \pwdata[4]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[4]), 
        .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[4]));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_0_iv_0[2]  (.A(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[2]), .B(
        CORECONFIGP_0_SOFT_M3_RESET), .C(N_93), .D(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .Y(\prdata[2] ));
    SLE \FIC_2_APB_M_PRDATA[15]  (.D(\prdata[15] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_15));
    CFG4 #( .INIT(16'hEAC0) )  \prdata_0_iv_0[12]  (.A(
        \soft_reset_reg[12]_net_1 ), .B(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[12]), .C(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .D(N_93), .Y(\prdata[12] )
        );
    SLE \paddr[2]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0), 
        .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[2]));
    CFG3 #( .INIT(8'h01) )  \prdata_0_iv_0_a3[1]  (.A(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0), .B(N_96), .C(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1), .Y(N_90));
    SLE \paddr[10]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_8), 
        .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CORECONFIGP_0_MDDR_APBmslave_PADDR[10]));
    SLE \FIC_2_APB_M_PRDATA[1]  (.D(\prdata[1] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_1));
    CFG2 #( .INIT(4'h1) )  state_s0_0_a2_0_a2 (.A(\state[1]_net_1 ), 
        .B(\state[0]_net_1 ), .Y(state_458_d));
    CFG4 #( .INIT(16'hFEFA) )  \prdata_0_iv_0[5]  (.A(N_50), .B(
        \soft_reset_reg[5]_net_1 ), .C(N_52), .D(N_93), .Y(\prdata[5] )
        );
    CFG4 #( .INIT(16'hEAC0) )  \prdata_0_iv_0[4]  (.A(
        \soft_reset_reg[4]_net_1 ), .B(
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[4]), .C(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .D(N_93), .Y(\prdata[4] ));
    SLE \soft_reset_reg[14]  (.D(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[14]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[14]_net_1 ));
    CFG3 #( .INIT(8'hA2) )  int_prdata_5_sqmuxa_i_a3 (.A(psel_net_1), 
        .B(\paddr[13]_net_1 ), .C(N_33), .Y(N_96));
    SLE \paddr[15]  (.D(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_13), 
        .CLK(CORECONFIGP_0_APB_S_PCLK), .EN(state_458_d), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(\paddr[15]_net_1 ));
    SLE \FIC_2_APB_M_PRDATA[10]  (.D(\prdata[10] ), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(\state[1]_net_1 ), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_10));
    SLE \soft_reset_reg[5]  (.D(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[5]), .CLK(
        CORECONFIGP_0_APB_S_PCLK), .EN(soft_reset_reg6), .ALn(
        CORECONFIGP_0_APB_S_PRESET_N), .ADn(VCC_net_1), .SLn(VCC_net_1)
        , .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \soft_reset_reg[5]_net_1 ));
    
endmodule


module MDDR_TA_MSS(
       MDDR_DQ,
       MDDR_DM_RDQS,
       MDDR_BA,
       MDDR_ADDR,
       AXI_IF_0_BIF_1_RDATA,
       CORECONFIGP_0_MDDR_APBmslave_PRDATA,
       CoreAHBLite_0_AHBmslave16_HADDR,
       CoreAHBLite_0_AHBmslave16_HWDATA,
       AXI_IF_0_BIF_1_ARADDR,
       AXI_IF_0_BIF_1_ARSIZE,
       AXI_IF_0_BIF_1_AWADDR,
       AXI_IF_0_BIF_1_AWSIZE,
       AXI_IF_0_BIF_1_WDATA,
       AXI_IF_0_BIF_1_WSTRB,
       CORECONFIGP_0_MDDR_APBmslave_PADDR,
       CORECONFIGP_0_MDDR_APBmslave_PWDATA,
       MDDR_DQS_N,
       MDDR_DQS,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_3,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_4,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_5,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_6,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_7,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_8,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_10,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_11,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_13,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_14,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_0,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_1,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_2,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_3,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_4,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_5,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_6,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_7,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_8,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_9,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_10,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_11,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_12,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_13,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_14,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_15,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_16,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_0,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_1,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_2,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_3,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_4,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_5,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_6,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_7,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_8,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_9,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_10,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_11,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_12,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_13,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_14,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_15,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_16,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_18,
       CORECONFIGP_0_APB_S_PCLK,
       CORECONFIGP_0_APB_S_PRESET_N,
       AXI_IF_0_BIF_1_RVALID,
       AXI_IF_0_BIF_1_RVALID_i_0,
       AXI_IF_0_BIF_1_RLAST,
       AXI_IF_0_BIF_1_RLAST_i_0,
       CORECONFIGP_0_APB_S_PCLK_i_0,
       MMUART_0_TXD,
       MMUART_0_RXD,
       MDDR_WE_N,
       MDDR_RESET_N,
       MDDR_RAS_N,
       MDDR_ODT,
       MDDR_DQS_TMATCH_0_OUT,
       MDDR_DQS_TMATCH_0_IN,
       MDDR_CS_N,
       MDDR_CKE,
       MDDR_CAS_N,
       MDDR_TA_0_GPIO_3_M2F,
       MDDR_TA_0_GPIO_4_M2F,
       MDDR_TA_0_GPIO_2_M2F,
       CoreAHBLite_0_AHBmslave16_HREADY,
       MDDR_TA_MSS_TMP_0_MSS_RESET_N_M2F,
       MDDR_TA_0_GPIO_1_M2F,
       MDDR_TA_0_GPIO_0_M2F,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSELx,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE,
       MDDR_TA_0_GPIO_5_M2F,
       MDDR_TA_0_GPIO_6_M2F,
       MDDR_TA_0_GPIO_7_M2F,
       AXI_IF_0_BIF_1_ARREADY,
       AXI_IF_0_BIF_1_AWREADY,
       AXI_IF_0_BIF_1_WREADY,
       CORECONFIGP_0_MDDR_APBmslave_PREADY,
       CORECONFIGP_0_MDDR_APBmslave_PSLVERR,
       GL0_INST,
       N_152_i_0,
       N_153_i_0,
       N_154_i_0,
       N_155_i_0,
       N_156_i_0,
       N_157_i_0,
       N_158_i_0,
       N_159_i_0,
       N_160_i_0,
       N_161_i_0,
       N_162_i_0,
       N_163_i_0,
       N_164_i_0,
       N_165_i_0,
       N_259_i_0,
       N_166_i_0,
       N_149_i_0,
       N_150_i_0,
       CORECONFIGP_0_SOFT_M3_RESET_i_0,
       LOCK,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PREADY,
       MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSLVERR,
       CORECONFIGP_0_SOFT_RESET_F2M_i_0,
       AXI_IF_0_BIF_1_ARVALID,
       AXI_IF_0_BIF_1_AWVALID,
       AXI_IF_0_BIF_1_RREADY,
       AXI_IF_0_BIF_1_WLAST,
       AXI_IF_0_BIF_1_WVALID,
       CORERESETP_0_MDDR_DDR_AXI_S_CORE_RESET_N,
       CORECONFIGP_0_MDDR_APBmslave_PENABLE,
       CORECONFIGP_0_MDDR_APBmslave_PSELx,
       CORECONFIGP_0_MDDR_APBmslave_PWRITE,
       MDDR_CLK_N,
       MDDR_CLK
    );
inout  [15:0] MDDR_DQ;
inout  [1:0] MDDR_DM_RDQS;
output [2:0] MDDR_BA;
output [15:0] MDDR_ADDR;
output [63:0] AXI_IF_0_BIF_1_RDATA;
output [15:0] CORECONFIGP_0_MDDR_APBmslave_PRDATA;
input  [27:12] CoreAHBLite_0_AHBmslave16_HADDR;
input  [13:0] CoreAHBLite_0_AHBmslave16_HWDATA;
input  [31:7] AXI_IF_0_BIF_1_ARADDR;
input  [1:1] AXI_IF_0_BIF_1_ARSIZE;
input  [31:7] AXI_IF_0_BIF_1_AWADDR;
input  [1:1] AXI_IF_0_BIF_1_AWSIZE;
input  [63:0] AXI_IF_0_BIF_1_WDATA;
input  [1:1] AXI_IF_0_BIF_1_WSTRB;
input  [10:2] CORECONFIGP_0_MDDR_APBmslave_PADDR;
input  [15:0] CORECONFIGP_0_MDDR_APBmslave_PWDATA;
inout  [1:0] MDDR_DQS_N;
inout  [1:0] MDDR_DQS;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_3;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_4;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_5;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_6;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_7;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_8;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_10;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_11;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_13;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_14;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_0;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_1;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_2;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_3;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_4;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_5;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_6;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_7;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_8;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_9;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_10;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_11;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_12;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_13;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_14;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_15;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_16;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_0;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_1;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_2;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_3;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_4;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_5;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_6;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_7;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_8;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_9;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_10;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_11;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_12;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_13;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_14;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_15;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_16;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_18;
output CORECONFIGP_0_APB_S_PCLK;
output CORECONFIGP_0_APB_S_PRESET_N;
inout  AXI_IF_0_BIF_1_RVALID;
output AXI_IF_0_BIF_1_RVALID_i_0;
inout  AXI_IF_0_BIF_1_RLAST;
output AXI_IF_0_BIF_1_RLAST_i_0;
output CORECONFIGP_0_APB_S_PCLK_i_0;
output MMUART_0_TXD;
input  MMUART_0_RXD;
output MDDR_WE_N;
output MDDR_RESET_N;
output MDDR_RAS_N;
output MDDR_ODT;
output MDDR_DQS_TMATCH_0_OUT;
input  MDDR_DQS_TMATCH_0_IN;
output MDDR_CS_N;
output MDDR_CKE;
output MDDR_CAS_N;
output MDDR_TA_0_GPIO_3_M2F;
output MDDR_TA_0_GPIO_4_M2F;
output MDDR_TA_0_GPIO_2_M2F;
inout  CoreAHBLite_0_AHBmslave16_HREADY;
output MDDR_TA_MSS_TMP_0_MSS_RESET_N_M2F;
output MDDR_TA_0_GPIO_1_M2F;
output MDDR_TA_0_GPIO_0_M2F;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSELx;
output MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE;
output MDDR_TA_0_GPIO_5_M2F;
output MDDR_TA_0_GPIO_6_M2F;
output MDDR_TA_0_GPIO_7_M2F;
output AXI_IF_0_BIF_1_ARREADY;
output AXI_IF_0_BIF_1_AWREADY;
output AXI_IF_0_BIF_1_WREADY;
output CORECONFIGP_0_MDDR_APBmslave_PREADY;
output CORECONFIGP_0_MDDR_APBmslave_PSLVERR;
input  GL0_INST;
input  N_152_i_0;
input  N_153_i_0;
input  N_154_i_0;
input  N_155_i_0;
input  N_156_i_0;
input  N_157_i_0;
input  N_158_i_0;
input  N_159_i_0;
input  N_160_i_0;
input  N_161_i_0;
input  N_162_i_0;
input  N_163_i_0;
input  N_164_i_0;
input  N_165_i_0;
input  N_259_i_0;
input  N_166_i_0;
input  N_149_i_0;
input  N_150_i_0;
input  CORECONFIGP_0_SOFT_M3_RESET_i_0;
input  LOCK;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PREADY;
input  MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSLVERR;
input  CORECONFIGP_0_SOFT_RESET_F2M_i_0;
input  AXI_IF_0_BIF_1_ARVALID;
input  AXI_IF_0_BIF_1_AWVALID;
input  AXI_IF_0_BIF_1_RREADY;
input  AXI_IF_0_BIF_1_WLAST;
input  AXI_IF_0_BIF_1_WVALID;
input  CORERESETP_0_MDDR_DDR_AXI_S_CORE_RESET_N;
input  CORECONFIGP_0_MDDR_APBmslave_PENABLE;
input  CORECONFIGP_0_MDDR_APBmslave_PSELx;
input  CORECONFIGP_0_MDDR_APBmslave_PWRITE;
output MDDR_CLK_N;
output MDDR_CLK;

    wire FIC_2_APB_M_PCLK, CONFIG_PRESET_N, 
        MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OUT, 
        MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OE, 
        MMUART_0_RXD_PAD_Y, MSS_ADLIB_INST_DRAM_WEN, 
        MSS_ADLIB_INST_DRAM_RSTN, MSS_ADLIB_INST_DRAM_RASN, 
        MSS_ADLIB_INST_DRAM_ODT, \DRAM_FIFO_WE_OUT_net_0[0] , 
        MDDR_DQS_TMATCH_0_IN_PAD_Y, MDDR_DQ_15_PAD_Y, 
        \DRAM_DQ_OUT_net_0[15] , \DRAM_DQ_OE_net_0[15] , 
        MDDR_DQ_14_PAD_Y, \DRAM_DQ_OUT_net_0[14] , 
        \DRAM_DQ_OE_net_0[14] , MDDR_DQ_13_PAD_Y, 
        \DRAM_DQ_OUT_net_0[13] , \DRAM_DQ_OE_net_0[13] , 
        MDDR_DQ_12_PAD_Y, \DRAM_DQ_OUT_net_0[12] , 
        \DRAM_DQ_OE_net_0[12] , MDDR_DQ_11_PAD_Y, 
        \DRAM_DQ_OUT_net_0[11] , \DRAM_DQ_OE_net_0[11] , 
        MDDR_DQ_10_PAD_Y, \DRAM_DQ_OUT_net_0[10] , 
        \DRAM_DQ_OE_net_0[10] , MDDR_DQ_9_PAD_Y, 
        \DRAM_DQ_OUT_net_0[9] , \DRAM_DQ_OE_net_0[9] , MDDR_DQ_8_PAD_Y, 
        \DRAM_DQ_OUT_net_0[8] , \DRAM_DQ_OE_net_0[8] , MDDR_DQ_7_PAD_Y, 
        \DRAM_DQ_OUT_net_0[7] , \DRAM_DQ_OE_net_0[7] , MDDR_DQ_6_PAD_Y, 
        \DRAM_DQ_OUT_net_0[6] , \DRAM_DQ_OE_net_0[6] , MDDR_DQ_5_PAD_Y, 
        \DRAM_DQ_OUT_net_0[5] , \DRAM_DQ_OE_net_0[5] , MDDR_DQ_4_PAD_Y, 
        \DRAM_DQ_OUT_net_0[4] , \DRAM_DQ_OE_net_0[4] , MDDR_DQ_3_PAD_Y, 
        \DRAM_DQ_OUT_net_0[3] , \DRAM_DQ_OE_net_0[3] , MDDR_DQ_2_PAD_Y, 
        \DRAM_DQ_OUT_net_0[2] , \DRAM_DQ_OE_net_0[2] , MDDR_DQ_1_PAD_Y, 
        \DRAM_DQ_OUT_net_0[1] , \DRAM_DQ_OE_net_0[1] , MDDR_DQ_0_PAD_Y, 
        \DRAM_DQ_OUT_net_0[0] , \DRAM_DQ_OE_net_0[0] , 
        MDDR_DM_RDQS_1_PAD_Y, \DRAM_DM_RDQS_OUT_net_0[1] , 
        \DM_OE_net_0[1] , MDDR_DM_RDQS_0_PAD_Y, 
        \DRAM_DM_RDQS_OUT_net_0[0] , \DM_OE_net_0[0] , 
        MSS_ADLIB_INST_DRAM_CSN, MSS_ADLIB_INST_DRAM_CKE, 
        MSS_ADLIB_INST_DRAM_CASN, \DRAM_BA_net_0[2] , 
        \DRAM_BA_net_0[1] , \DRAM_BA_net_0[0] , \DRAM_ADDR_net_0[15] , 
        \DRAM_ADDR_net_0[14] , \DRAM_ADDR_net_0[13] , 
        \DRAM_ADDR_net_0[12] , \DRAM_ADDR_net_0[11] , 
        \DRAM_ADDR_net_0[10] , \DRAM_ADDR_net_0[9] , 
        \DRAM_ADDR_net_0[8] , \DRAM_ADDR_net_0[7] , 
        \DRAM_ADDR_net_0[6] , \DRAM_ADDR_net_0[5] , 
        \DRAM_ADDR_net_0[4] , \DRAM_ADDR_net_0[3] , 
        \DRAM_ADDR_net_0[2] , \DRAM_ADDR_net_0[1] , 
        \DRAM_ADDR_net_0[0] , VCC_net_1, GND_net_1, MDDR_DQS_0_PAD_Y, 
        MDDR_DQS_1_PAD_Y, MSS_ADLIB_INST_DRAM_CLK, 
        \DRAM_DQS_OUT_net_0[0] , \DRAM_DQS_OUT_net_0[1] , 
        \DRAM_DQS_OE_net_0[0] , \DRAM_DQS_OE_net_0[1] ;
    
    INBUF #( .IOSTD("") )  MMUART_0_RXD_PAD (.PAD(MMUART_0_RXD), .Y(
        MMUART_0_RXD_PAD_Y));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_6_PAD (.D(
        \DRAM_ADDR_net_0[6] ), .PAD(MDDR_ADDR[6]));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_CAS_N_PAD (.D(
        MSS_ADLIB_INST_DRAM_CASN), .PAD(MDDR_CAS_N));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_RESET_N_PAD (.D(
        MSS_ADLIB_INST_DRAM_RSTN), .PAD(MDDR_RESET_N));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ODT_PAD (.D(
        MSS_ADLIB_INST_DRAM_ODT), .PAD(MDDR_ODT));
    CFG1 #( .INIT(2'h1) )  FIC_2_APB_M_PCLK_keep_RNIG3N5_0 (.A(
        CORECONFIGP_0_APB_S_PCLK), .Y(CORECONFIGP_0_APB_S_PCLK_i_0));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_11_PAD (.D(
        \DRAM_ADDR_net_0[11] ), .PAD(MDDR_ADDR[11]));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_10_PAD (.PAD(MDDR_DQ[10]), 
        .D(\DRAM_DQ_OUT_net_0[10] ), .E(\DRAM_DQ_OE_net_0[10] ), .Y(
        MDDR_DQ_10_PAD_Y));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_1_PAD (.PAD(MDDR_DQ[1]), .D(
        \DRAM_DQ_OUT_net_0[1] ), .E(\DRAM_DQ_OE_net_0[1] ), .Y(
        MDDR_DQ_1_PAD_Y));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_7_PAD (.D(
        \DRAM_ADDR_net_0[7] ), .PAD(MDDR_ADDR[7]));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_11_PAD (.PAD(MDDR_DQ[11]), 
        .D(\DRAM_DQ_OUT_net_0[11] ), .E(\DRAM_DQ_OE_net_0[11] ), .Y(
        MDDR_DQ_11_PAD_Y));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_9_PAD (.PAD(MDDR_DQ[9]), .D(
        \DRAM_DQ_OUT_net_0[9] ), .E(\DRAM_DQ_OE_net_0[9] ), .Y(
        MDDR_DQ_9_PAD_Y));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_3_PAD (.PAD(MDDR_DQ[3]), .D(
        \DRAM_DQ_OUT_net_0[3] ), .E(\DRAM_DQ_OE_net_0[3] ), .Y(
        MDDR_DQ_3_PAD_Y));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_0_PAD (.PAD(MDDR_DQ[0]), .D(
        \DRAM_DQ_OUT_net_0[0] ), .E(\DRAM_DQ_OE_net_0[0] ), .Y(
        MDDR_DQ_0_PAD_Y));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_12_PAD (.D(
        \DRAM_ADDR_net_0[12] ), .PAD(MDDR_ADDR[12]));
    CLKINT FIC_2_APB_M_PCLK_keep_RNIG3N5 (.A(FIC_2_APB_M_PCLK), .Y(
        CORECONFIGP_0_APB_S_PCLK));
    VCC VCC (.Y(VCC_net_1));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_2_PAD (.PAD(MDDR_DQ[2]), .D(
        \DRAM_DQ_OUT_net_0[2] ), .E(\DRAM_DQ_OE_net_0[2] ), .Y(
        MDDR_DQ_2_PAD_Y));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_12_PAD (.PAD(MDDR_DQ[12]), 
        .D(\DRAM_DQ_OUT_net_0[12] ), .E(\DRAM_DQ_OE_net_0[12] ), .Y(
        MDDR_DQ_12_PAD_Y));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_CKE_PAD (.D(
        MSS_ADLIB_INST_DRAM_CKE), .PAD(MDDR_CKE));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_2_PAD (.D(
        \DRAM_ADDR_net_0[2] ), .PAD(MDDR_ADDR[2]));
    TRIBUFF MMUART_0_TXD_PAD (.D(
        MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OUT), .E(
        MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OE), .PAD(
        MMUART_0_TXD));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_13_PAD (.D(
        \DRAM_ADDR_net_0[13] ), .PAD(MDDR_ADDR[13]));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_5_PAD (.D(
        \DRAM_ADDR_net_0[5] ), .PAD(MDDR_ADDR[5]));
    CFG1 #( .INIT(2'h1) )  MSS_ADLIB_INST_RNIDR56_1 (.A(
        AXI_IF_0_BIF_1_RVALID), .Y(AXI_IF_0_BIF_1_RVALID_i_0));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DM_RDQS_1_PAD (.PAD(
        MDDR_DM_RDQS[1]), .D(\DRAM_DM_RDQS_OUT_net_0[1] ), .E(
        \DM_OE_net_0[1] ), .Y(MDDR_DM_RDQS_1_PAD_Y));
    BIBUF_DIFF #( .IOSTD("SSTL15I") )  MDDR_DQS_0_PAD (.D(
        \DRAM_DQS_OUT_net_0[0] ), .E(\DRAM_DQS_OE_net_0[0] ), .PADP(
        MDDR_DQS[0]), .PADN(MDDR_DQS_N[0]), .Y(MDDR_DQS_0_PAD_Y));
    CLKINT MSS_ADLIB_INST_RNIDR56 (.A(CONFIG_PRESET_N), .Y(
        CORECONFIGP_0_APB_S_PRESET_N));
    BIBUF_DIFF #( .IOSTD("SSTL15I") )  MDDR_DQS_1_PAD (.D(
        \DRAM_DQS_OUT_net_0[1] ), .E(\DRAM_DQS_OE_net_0[1] ), .PADP(
        MDDR_DQS[1]), .PADN(MDDR_DQS_N[1]), .Y(MDDR_DQS_1_PAD_Y));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_15_PAD (.PAD(MDDR_DQ[15]), 
        .D(\DRAM_DQ_OUT_net_0[15] ), .E(\DRAM_DQ_OE_net_0[15] ), .Y(
        MDDR_DQ_15_PAD_Y));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DM_RDQS_0_PAD (.PAD(
        MDDR_DM_RDQS[0]), .D(\DRAM_DM_RDQS_OUT_net_0[0] ), .E(
        \DM_OE_net_0[0] ), .Y(MDDR_DM_RDQS_0_PAD_Y));
    GND GND (.Y(GND_net_1));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_8_PAD (.PAD(MDDR_DQ[8]), .D(
        \DRAM_DQ_OUT_net_0[8] ), .E(\DRAM_DQ_OE_net_0[8] ), .Y(
        MDDR_DQ_8_PAD_Y));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_9_PAD (.D(
        \DRAM_ADDR_net_0[9] ), .PAD(MDDR_ADDR[9]));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_BA_2_PAD (.D(
        \DRAM_BA_net_0[2] ), .PAD(MDDR_BA[2]));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_14_PAD (.D(
        \DRAM_ADDR_net_0[14] ), .PAD(MDDR_ADDR[14]));
    MSS_120 #( .INIT(1438'h00000000003612000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000F00000000F000000000000000000000000000000007FFFFFFFB000001007C33C00024A0060904030C003FFFFE4000000000000400000000F0F11C00000000DFDC010842108421000001FE34001FF8000000400000000000EF1007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
        , .ACT_UBITS(56'hFFFFFFFFFFFFFF), .MEMORYFILE("ENVM_init.mem")
        , .RTC_MAIN_XTL_FREQ(0.0), .RTC_MAIN_XTL_MODE(""), .DDR_CLK_FREQ(333.2)
         )  MSS_ADLIB_INST (.CAN_RXBUS_MGPIO3A_H2F_A(), 
        .CAN_RXBUS_MGPIO3A_H2F_B(MDDR_TA_0_GPIO_3_M2F), 
        .CAN_TX_EBL_MGPIO4A_H2F_A(), .CAN_TX_EBL_MGPIO4A_H2F_B(
        MDDR_TA_0_GPIO_4_M2F), .CAN_TXBUS_MGPIO2A_H2F_A(), 
        .CAN_TXBUS_MGPIO2A_H2F_B(MDDR_TA_0_GPIO_2_M2F), 
        .CLK_CONFIG_APB(FIC_2_APB_M_PCLK), .COMMS_INT(), 
        .CONFIG_PRESET_N(CONFIG_PRESET_N), .EDAC_ERROR({nc0, nc1, nc2, 
        nc3, nc4, nc5, nc6, nc7}), .F_FM0_RDATA({nc8, nc9, nc10, nc11, 
        nc12, nc13, nc14, nc15, nc16, nc17, nc18, nc19, nc20, nc21, 
        nc22, nc23, nc24, nc25, nc26, nc27, nc28, nc29, nc30, nc31, 
        nc32, nc33, nc34, nc35, nc36, nc37, nc38, nc39}), 
        .F_FM0_READYOUT(CoreAHBLite_0_AHBmslave16_HREADY), .F_FM0_RESP(
        ), .F_FM1_RDATA({nc40, nc41, nc42, nc43, nc44, nc45, nc46, 
        nc47, nc48, nc49, nc50, nc51, nc52, nc53, nc54, nc55, nc56, 
        nc57, nc58, nc59, nc60, nc61, nc62, nc63, nc64, nc65, nc66, 
        nc67, nc68, nc69, nc70, nc71}), .F_FM1_READYOUT(), .F_FM1_RESP(
        ), .F_HM0_ADDR({nc72, nc73, nc74, nc75, nc76, nc77, nc78, nc79, 
        nc80, nc81, nc82, nc83, nc84, nc85, nc86, nc87, nc88, nc89, 
        nc90, nc91, nc92, nc93, nc94, nc95, nc96, nc97, nc98, nc99, 
        nc100, nc101, nc102, nc103}), .F_HM0_ENABLE(), .F_HM0_SEL(), 
        .F_HM0_SIZE({nc104, nc105}), .F_HM0_TRANS1(), .F_HM0_WDATA({
        nc106, nc107, nc108, nc109, nc110, nc111, nc112, nc113, nc114, 
        nc115, nc116, nc117, nc118, nc119, nc120, nc121, nc122, nc123, 
        nc124, nc125, nc126, nc127, nc128, nc129, nc130, nc131, nc132, 
        nc133, nc134, nc135, nc136, nc137}), .F_HM0_WRITE(), 
        .F_HM1_ADDR({nc138, nc139, nc140, nc141, nc142, nc143, nc144, 
        nc145, nc146, nc147, nc148, nc149, nc150, nc151, nc152, nc153, 
        nc154, nc155, nc156, nc157, nc158, nc159, nc160, nc161, nc162, 
        nc163, nc164, nc165, nc166, nc167, nc168, nc169}), 
        .F_HM1_ENABLE(), .F_HM1_SEL(), .F_HM1_SIZE({nc170, nc171}), 
        .F_HM1_TRANS1(), .F_HM1_WDATA({nc172, nc173, nc174, nc175, 
        nc176, nc177, nc178, nc179, nc180, nc181, nc182, nc183, nc184, 
        nc185, nc186, nc187, nc188, nc189, nc190, nc191, nc192, nc193, 
        nc194, nc195, nc196, nc197, nc198, nc199, nc200, nc201, nc202, 
        nc203}), .F_HM1_WRITE(), .FAB_CHRGVBUS(), .FAB_DISCHRGVBUS(), 
        .FAB_DMPULLDOWN(), .FAB_DPPULLDOWN(), .FAB_DRVVBUS(), 
        .FAB_IDPULLUP(), .FAB_OPMODE({nc204, nc205}), .FAB_SUSPENDM(), 
        .FAB_TERMSEL(), .FAB_TXVALID(), .FAB_VCONTROL({nc206, nc207, 
        nc208, nc209}), .FAB_VCONTROLLOADM(), .FAB_XCVRSEL({nc210, 
        nc211}), .FAB_XDATAOUT({nc212, nc213, nc214, nc215, nc216, 
        nc217, nc218, nc219}), .FACC_GLMUX_SEL(), .FIC32_0_MASTER({
        nc220, nc221}), .FIC32_1_MASTER({nc222, nc223}), .FPGA_RESET_N(
        MDDR_TA_MSS_TMP_0_MSS_RESET_N_M2F), .GTX_CLK(), .H2F_INTERRUPT({
        nc224, nc225, nc226, nc227, nc228, nc229, nc230, nc231, nc232, 
        nc233, nc234, nc235, nc236, nc237, nc238, nc239}), .H2F_NMI(), 
        .H2FCALIB(), .I2C0_SCL_MGPIO31B_H2F_A(), 
        .I2C0_SCL_MGPIO31B_H2F_B(), .I2C0_SDA_MGPIO30B_H2F_A(), 
        .I2C0_SDA_MGPIO30B_H2F_B(), .I2C1_SCL_MGPIO1A_H2F_A(), 
        .I2C1_SCL_MGPIO1A_H2F_B(MDDR_TA_0_GPIO_1_M2F), 
        .I2C1_SDA_MGPIO0A_H2F_A(), .I2C1_SDA_MGPIO0A_H2F_B(
        MDDR_TA_0_GPIO_0_M2F), .MDCF(), .MDOENF(), .MDOF(), 
        .MMUART0_CTS_MGPIO19B_H2F_A(), .MMUART0_CTS_MGPIO19B_H2F_B(), 
        .MMUART0_DCD_MGPIO22B_H2F_A(), .MMUART0_DCD_MGPIO22B_H2F_B(), 
        .MMUART0_DSR_MGPIO20B_H2F_A(), .MMUART0_DSR_MGPIO20B_H2F_B(), 
        .MMUART0_DTR_MGPIO18B_H2F_A(), .MMUART0_DTR_MGPIO18B_H2F_B(), 
        .MMUART0_RI_MGPIO21B_H2F_A(), .MMUART0_RI_MGPIO21B_H2F_B(), 
        .MMUART0_RTS_MGPIO17B_H2F_A(), .MMUART0_RTS_MGPIO17B_H2F_B(), 
        .MMUART0_RXD_MGPIO28B_H2F_A(), .MMUART0_RXD_MGPIO28B_H2F_B(), 
        .MMUART0_SCK_MGPIO29B_H2F_A(), .MMUART0_SCK_MGPIO29B_H2F_B(), 
        .MMUART0_TXD_MGPIO27B_H2F_A(), .MMUART0_TXD_MGPIO27B_H2F_B(), 
        .MMUART1_DTR_MGPIO12B_H2F_A(), .MMUART1_RTS_MGPIO11B_H2F_A(), 
        .MMUART1_RTS_MGPIO11B_H2F_B(), .MMUART1_RXD_MGPIO26B_H2F_A(), 
        .MMUART1_RXD_MGPIO26B_H2F_B(), .MMUART1_SCK_MGPIO25B_H2F_A(), 
        .MMUART1_SCK_MGPIO25B_H2F_B(), .MMUART1_TXD_MGPIO24B_H2F_A(), 
        .MMUART1_TXD_MGPIO24B_H2F_B(), .MPLL_LOCK(), 
        .PER2_FABRIC_PADDR({
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_14, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_13, nc240, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_11, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_10, nc241, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_8, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_7, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_6, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_5, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_4, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_3, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0}), 
        .PER2_FABRIC_PENABLE(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE), .PER2_FABRIC_PSEL(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSELx), .PER2_FABRIC_PWDATA({
        nc242, nc243, nc244, nc245, nc246, nc247, nc248, nc249, nc250, 
        nc251, nc252, nc253, nc254, nc255, nc256, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_16, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_15, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_14, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_13, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_12, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_11, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_10, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_9, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_8, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_7, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_6, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_5, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_4, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_3, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_2, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_1, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_0}), 
        .PER2_FABRIC_PWRITE(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE), 
        .RTC_MATCH(), .SLEEPDEEP(), .SLEEPHOLDACK(), .SLEEPING(), 
        .SMBALERT_NO0(), .SMBALERT_NO1(), .SMBSUS_NO0(), .SMBSUS_NO1(), 
        .SPI0_CLK_OUT(), .SPI0_SDI_MGPIO5A_H2F_A(), 
        .SPI0_SDI_MGPIO5A_H2F_B(MDDR_TA_0_GPIO_5_M2F), 
        .SPI0_SDO_MGPIO6A_H2F_A(), .SPI0_SDO_MGPIO6A_H2F_B(
        MDDR_TA_0_GPIO_6_M2F), .SPI0_SS0_MGPIO7A_H2F_A(), 
        .SPI0_SS0_MGPIO7A_H2F_B(MDDR_TA_0_GPIO_7_M2F), 
        .SPI0_SS1_MGPIO8A_H2F_A(), .SPI0_SS1_MGPIO8A_H2F_B(), 
        .SPI0_SS2_MGPIO9A_H2F_A(), .SPI0_SS2_MGPIO9A_H2F_B(), 
        .SPI0_SS3_MGPIO10A_H2F_A(), .SPI0_SS3_MGPIO10A_H2F_B(), 
        .SPI0_SS4_MGPIO19A_H2F_A(), .SPI0_SS5_MGPIO20A_H2F_A(), 
        .SPI0_SS6_MGPIO21A_H2F_A(), .SPI0_SS7_MGPIO22A_H2F_A(), 
        .SPI1_CLK_OUT(), .SPI1_SDI_MGPIO11A_H2F_A(), 
        .SPI1_SDI_MGPIO11A_H2F_B(), .SPI1_SDO_MGPIO12A_H2F_A(), 
        .SPI1_SDO_MGPIO12A_H2F_B(), .SPI1_SS0_MGPIO13A_H2F_A(), 
        .SPI1_SS0_MGPIO13A_H2F_B(), .SPI1_SS1_MGPIO14A_H2F_A(), 
        .SPI1_SS1_MGPIO14A_H2F_B(), .SPI1_SS2_MGPIO15A_H2F_A(), 
        .SPI1_SS2_MGPIO15A_H2F_B(), .SPI1_SS3_MGPIO16A_H2F_A(), 
        .SPI1_SS3_MGPIO16A_H2F_B(), .SPI1_SS4_MGPIO17A_H2F_A(), 
        .SPI1_SS5_MGPIO18A_H2F_A(), .SPI1_SS6_MGPIO23A_H2F_A(), 
        .SPI1_SS7_MGPIO24A_H2F_A(), .TCGF({nc257, nc258, nc259, nc260, 
        nc261, nc262, nc263, nc264, nc265, nc266}), .TRACECLK(), 
        .TRACEDATA({nc267, nc268, nc269, nc270}), .TX_CLK(), .TX_ENF(), 
        .TX_ERRF(), .TXCTL_EN_RIF(), .TXD_RIF({nc271, nc272, nc273, 
        nc274}), .TXDF({nc275, nc276, nc277, nc278, nc279, nc280, 
        nc281, nc282}), .TXEV(), .WDOGTIMEOUT(), .F_ARREADY_HREADYOUT1(
        AXI_IF_0_BIF_1_ARREADY), .F_AWREADY_HREADYOUT0(
        AXI_IF_0_BIF_1_AWREADY), .F_BID({nc283, nc284, nc285, nc286}), 
        .F_BRESP_HRESP0({nc287, nc288}), .F_BVALID(), 
        .F_RDATA_HRDATA01({AXI_IF_0_BIF_1_RDATA[63], 
        AXI_IF_0_BIF_1_RDATA[62], AXI_IF_0_BIF_1_RDATA[61], 
        AXI_IF_0_BIF_1_RDATA[60], AXI_IF_0_BIF_1_RDATA[59], 
        AXI_IF_0_BIF_1_RDATA[58], AXI_IF_0_BIF_1_RDATA[57], 
        AXI_IF_0_BIF_1_RDATA[56], AXI_IF_0_BIF_1_RDATA[55], 
        AXI_IF_0_BIF_1_RDATA[54], AXI_IF_0_BIF_1_RDATA[53], 
        AXI_IF_0_BIF_1_RDATA[52], AXI_IF_0_BIF_1_RDATA[51], 
        AXI_IF_0_BIF_1_RDATA[50], AXI_IF_0_BIF_1_RDATA[49], 
        AXI_IF_0_BIF_1_RDATA[48], AXI_IF_0_BIF_1_RDATA[47], 
        AXI_IF_0_BIF_1_RDATA[46], AXI_IF_0_BIF_1_RDATA[45], 
        AXI_IF_0_BIF_1_RDATA[44], AXI_IF_0_BIF_1_RDATA[43], 
        AXI_IF_0_BIF_1_RDATA[42], AXI_IF_0_BIF_1_RDATA[41], 
        AXI_IF_0_BIF_1_RDATA[40], AXI_IF_0_BIF_1_RDATA[39], 
        AXI_IF_0_BIF_1_RDATA[38], AXI_IF_0_BIF_1_RDATA[37], 
        AXI_IF_0_BIF_1_RDATA[36], AXI_IF_0_BIF_1_RDATA[35], 
        AXI_IF_0_BIF_1_RDATA[34], AXI_IF_0_BIF_1_RDATA[33], 
        AXI_IF_0_BIF_1_RDATA[32], AXI_IF_0_BIF_1_RDATA[31], 
        AXI_IF_0_BIF_1_RDATA[30], AXI_IF_0_BIF_1_RDATA[29], 
        AXI_IF_0_BIF_1_RDATA[28], AXI_IF_0_BIF_1_RDATA[27], 
        AXI_IF_0_BIF_1_RDATA[26], AXI_IF_0_BIF_1_RDATA[25], 
        AXI_IF_0_BIF_1_RDATA[24], AXI_IF_0_BIF_1_RDATA[23], 
        AXI_IF_0_BIF_1_RDATA[22], AXI_IF_0_BIF_1_RDATA[21], 
        AXI_IF_0_BIF_1_RDATA[20], AXI_IF_0_BIF_1_RDATA[19], 
        AXI_IF_0_BIF_1_RDATA[18], AXI_IF_0_BIF_1_RDATA[17], 
        AXI_IF_0_BIF_1_RDATA[16], AXI_IF_0_BIF_1_RDATA[15], 
        AXI_IF_0_BIF_1_RDATA[14], AXI_IF_0_BIF_1_RDATA[13], 
        AXI_IF_0_BIF_1_RDATA[12], AXI_IF_0_BIF_1_RDATA[11], 
        AXI_IF_0_BIF_1_RDATA[10], AXI_IF_0_BIF_1_RDATA[9], 
        AXI_IF_0_BIF_1_RDATA[8], AXI_IF_0_BIF_1_RDATA[7], 
        AXI_IF_0_BIF_1_RDATA[6], AXI_IF_0_BIF_1_RDATA[5], 
        AXI_IF_0_BIF_1_RDATA[4], AXI_IF_0_BIF_1_RDATA[3], 
        AXI_IF_0_BIF_1_RDATA[2], AXI_IF_0_BIF_1_RDATA[1], 
        AXI_IF_0_BIF_1_RDATA[0]}), .F_RID({nc289, nc290, nc291, nc292})
        , .F_RLAST(AXI_IF_0_BIF_1_RLAST), .F_RRESP_HRESP1({nc293, 
        nc294}), .F_RVALID(AXI_IF_0_BIF_1_RVALID), .F_WREADY(
        AXI_IF_0_BIF_1_WREADY), .MDDR_FABRIC_PRDATA({
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[15], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[14], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[13], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[12], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[11], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[10], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[9], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[8], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[7], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[6], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[5], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[4], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[3], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[2], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[1], 
        CORECONFIGP_0_MDDR_APBmslave_PRDATA[0]}), .MDDR_FABRIC_PREADY(
        CORECONFIGP_0_MDDR_APBmslave_PREADY), .MDDR_FABRIC_PSLVERR(
        CORECONFIGP_0_MDDR_APBmslave_PSLVERR), .REV_ARADDR({nc295, 
        nc296, nc297, nc298, nc299, nc300, nc301, nc302, nc303, nc304, 
        nc305, nc306, nc307, nc308, nc309, nc310, nc311, nc312, nc313, 
        nc314, nc315, nc316, nc317, nc318, nc319, nc320, nc321, nc322, 
        nc323, nc324, nc325, nc326}), .REV_ARBURST({nc327, nc328}), 
        .REV_ARID({nc329, nc330, nc331, nc332}), .REV_ARLEN({nc333, 
        nc334, nc335, nc336}), .REV_ARLOCK({nc337, nc338}), 
        .REV_ARSIZE({nc339, nc340}), .REV_AWADDR({nc341, nc342, nc343, 
        nc344, nc345, nc346, nc347, nc348, nc349, nc350, nc351, nc352, 
        nc353, nc354, nc355, nc356, nc357, nc358, nc359, nc360, nc361, 
        nc362, nc363, nc364, nc365, nc366, nc367, nc368, nc369, nc370, 
        nc371, nc372}), .REV_AWLOCK({nc373, nc374}), .REV_AWSIZE({
        nc375, nc376}), .REV_RREADY(), .REV_WID({nc377, nc378, nc379, 
        nc380}), .REV_WSTRB({nc381, nc382, nc383, nc384, nc385, nc386, 
        nc387, nc388}), .CAN_RXBUS_F2H_SCP(VCC_net_1), 
        .CAN_TX_EBL_F2H_SCP(VCC_net_1), .CAN_TXBUS_F2H_SCP(VCC_net_1), 
        .CLK_BASE(GL0_INST), .COLF(VCC_net_1), .CRSF(VCC_net_1), 
        .F2_DMAREADY({VCC_net_1, VCC_net_1}), .F2H_INTERRUPT({
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1}), .F2HCALIB(VCC_net_1), .F_DMAREADY({VCC_net_1, 
        VCC_net_1}), .F_FM0_ADDR({N_165_i_0, N_164_i_0, N_163_i_0, 
        N_162_i_0, CoreAHBLite_0_AHBmslave16_HADDR[27], 
        CoreAHBLite_0_AHBmslave16_HADDR[26], 
        CoreAHBLite_0_AHBmslave16_HADDR[25], 
        CoreAHBLite_0_AHBmslave16_HADDR[24], 
        CoreAHBLite_0_AHBmslave16_HADDR[23], 
        CoreAHBLite_0_AHBmslave16_HADDR[22], 
        CoreAHBLite_0_AHBmslave16_HADDR[21], 
        CoreAHBLite_0_AHBmslave16_HADDR[20], 
        CoreAHBLite_0_AHBmslave16_HADDR[19], 
        CoreAHBLite_0_AHBmslave16_HADDR[18], 
        CoreAHBLite_0_AHBmslave16_HADDR[17], 
        CoreAHBLite_0_AHBmslave16_HADDR[16], 
        CoreAHBLite_0_AHBmslave16_HADDR[15], 
        CoreAHBLite_0_AHBmslave16_HADDR[14], 
        CoreAHBLite_0_AHBmslave16_HADDR[13], 
        CoreAHBLite_0_AHBmslave16_HADDR[12], N_161_i_0, N_160_i_0, 
        N_159_i_0, N_158_i_0, N_157_i_0, N_156_i_0, N_155_i_0, 
        N_154_i_0, N_153_i_0, N_152_i_0, GND_net_1, GND_net_1}), 
        .F_FM0_ENABLE(GND_net_1), .F_FM0_MASTLOCK(GND_net_1), 
        .F_FM0_READY(CoreAHBLite_0_AHBmslave16_HREADY), .F_FM0_SEL(
        N_259_i_0), .F_FM0_SIZE({N_166_i_0, GND_net_1}), .F_FM0_TRANS1(
        N_149_i_0), .F_FM0_WDATA({GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        CoreAHBLite_0_AHBmslave16_HWDATA[13], 
        CoreAHBLite_0_AHBmslave16_HWDATA[12], 
        CoreAHBLite_0_AHBmslave16_HWDATA[11], 
        CoreAHBLite_0_AHBmslave16_HWDATA[10], 
        CoreAHBLite_0_AHBmslave16_HWDATA[9], 
        CoreAHBLite_0_AHBmslave16_HWDATA[8], 
        CoreAHBLite_0_AHBmslave16_HWDATA[7], 
        CoreAHBLite_0_AHBmslave16_HWDATA[6], 
        CoreAHBLite_0_AHBmslave16_HWDATA[5], 
        CoreAHBLite_0_AHBmslave16_HWDATA[4], 
        CoreAHBLite_0_AHBmslave16_HWDATA[3], 
        CoreAHBLite_0_AHBmslave16_HWDATA[2], 
        CoreAHBLite_0_AHBmslave16_HWDATA[1], 
        CoreAHBLite_0_AHBmslave16_HWDATA[0]}), .F_FM0_WRITE(N_150_i_0), 
        .F_FM1_ADDR({GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1}), .F_FM1_ENABLE(GND_net_1), 
        .F_FM1_MASTLOCK(GND_net_1), .F_FM1_READY(VCC_net_1), 
        .F_FM1_SEL(GND_net_1), .F_FM1_SIZE({GND_net_1, GND_net_1}), 
        .F_FM1_TRANS1(GND_net_1), .F_FM1_WDATA({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .F_FM1_WRITE(GND_net_1), .F_HM0_RDATA({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .F_HM0_READY(VCC_net_1), .F_HM0_RESP(GND_net_1), .F_HM1_RDATA({
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1}), .F_HM1_READY(VCC_net_1), .F_HM1_RESP(
        GND_net_1), .FAB_AVALID(VCC_net_1), .FAB_HOSTDISCON(VCC_net_1), 
        .FAB_IDDIG(VCC_net_1), .FAB_LINESTATE({VCC_net_1, VCC_net_1}), 
        .FAB_M3_RESET_N(CORECONFIGP_0_SOFT_M3_RESET_i_0), 
        .FAB_PLL_LOCK(LOCK), .FAB_RXACTIVE(VCC_net_1), .FAB_RXERROR(
        VCC_net_1), .FAB_RXVALID(VCC_net_1), .FAB_RXVALIDH(GND_net_1), 
        .FAB_SESSEND(VCC_net_1), .FAB_TXREADY(VCC_net_1), 
        .FAB_VBUSVALID(VCC_net_1), .FAB_VSTATUS({VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1}), .FAB_XDATAIN({VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .GTX_CLKPF(VCC_net_1), .I2C0_BCLK(VCC_net_1), 
        .I2C0_SCL_F2H_SCP(VCC_net_1), .I2C0_SDA_F2H_SCP(VCC_net_1), 
        .I2C1_BCLK(VCC_net_1), .I2C1_SCL_F2H_SCP(VCC_net_1), 
        .I2C1_SDA_F2H_SCP(VCC_net_1), .MDIF(VCC_net_1), 
        .MGPIO0A_F2H_GPIN(VCC_net_1), .MGPIO10A_F2H_GPIN(VCC_net_1), 
        .MGPIO11A_F2H_GPIN(VCC_net_1), .MGPIO11B_F2H_GPIN(VCC_net_1), 
        .MGPIO12A_F2H_GPIN(VCC_net_1), .MGPIO13A_F2H_GPIN(VCC_net_1), 
        .MGPIO14A_F2H_GPIN(VCC_net_1), .MGPIO15A_F2H_GPIN(VCC_net_1), 
        .MGPIO16A_F2H_GPIN(VCC_net_1), .MGPIO17B_F2H_GPIN(VCC_net_1), 
        .MGPIO18B_F2H_GPIN(VCC_net_1), .MGPIO19B_F2H_GPIN(VCC_net_1), 
        .MGPIO1A_F2H_GPIN(VCC_net_1), .MGPIO20B_F2H_GPIN(VCC_net_1), 
        .MGPIO21B_F2H_GPIN(VCC_net_1), .MGPIO22B_F2H_GPIN(VCC_net_1), 
        .MGPIO24B_F2H_GPIN(VCC_net_1), .MGPIO25B_F2H_GPIN(VCC_net_1), 
        .MGPIO26B_F2H_GPIN(VCC_net_1), .MGPIO27B_F2H_GPIN(VCC_net_1), 
        .MGPIO28B_F2H_GPIN(VCC_net_1), .MGPIO29B_F2H_GPIN(VCC_net_1), 
        .MGPIO2A_F2H_GPIN(VCC_net_1), .MGPIO30B_F2H_GPIN(VCC_net_1), 
        .MGPIO31B_F2H_GPIN(VCC_net_1), .MGPIO3A_F2H_GPIN(VCC_net_1), 
        .MGPIO4A_F2H_GPIN(VCC_net_1), .MGPIO5A_F2H_GPIN(VCC_net_1), 
        .MGPIO6A_F2H_GPIN(VCC_net_1), .MGPIO7A_F2H_GPIN(VCC_net_1), 
        .MGPIO8A_F2H_GPIN(VCC_net_1), .MGPIO9A_F2H_GPIN(VCC_net_1), 
        .MMUART0_CTS_F2H_SCP(VCC_net_1), .MMUART0_DCD_F2H_SCP(
        VCC_net_1), .MMUART0_DSR_F2H_SCP(VCC_net_1), 
        .MMUART0_DTR_F2H_SCP(VCC_net_1), .MMUART0_RI_F2H_SCP(VCC_net_1)
        , .MMUART0_RTS_F2H_SCP(VCC_net_1), .MMUART0_RXD_F2H_SCP(
        VCC_net_1), .MMUART0_SCK_F2H_SCP(VCC_net_1), 
        .MMUART0_TXD_F2H_SCP(VCC_net_1), .MMUART1_CTS_F2H_SCP(
        VCC_net_1), .MMUART1_DCD_F2H_SCP(VCC_net_1), 
        .MMUART1_DSR_F2H_SCP(VCC_net_1), .MMUART1_RI_F2H_SCP(VCC_net_1)
        , .MMUART1_RTS_F2H_SCP(VCC_net_1), .MMUART1_RXD_F2H_SCP(
        VCC_net_1), .MMUART1_SCK_F2H_SCP(VCC_net_1), 
        .MMUART1_TXD_F2H_SCP(VCC_net_1), .PER2_FABRIC_PRDATA({
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_18, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_18, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_16, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_15, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_14, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_13, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_12, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_11, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_10, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_9, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_8, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_7, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_6, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_5, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_4, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_3, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_2, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_1, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_0}), 
        .PER2_FABRIC_PREADY(MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PREADY), 
        .PER2_FABRIC_PSLVERR(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSLVERR), .RCGF({VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), .RX_CLKPF(
        VCC_net_1), .RX_DVF(VCC_net_1), .RX_ERRF(VCC_net_1), .RX_EV(
        VCC_net_1), .RXDF({VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), .SLEEPHOLDREQ(
        GND_net_1), .SMBALERT_NI0(VCC_net_1), .SMBALERT_NI1(VCC_net_1), 
        .SMBSUS_NI0(VCC_net_1), .SMBSUS_NI1(VCC_net_1), .SPI0_CLK_IN(
        VCC_net_1), .SPI0_SDI_F2H_SCP(VCC_net_1), .SPI0_SDO_F2H_SCP(
        VCC_net_1), .SPI0_SS0_F2H_SCP(VCC_net_1), .SPI0_SS1_F2H_SCP(
        VCC_net_1), .SPI0_SS2_F2H_SCP(VCC_net_1), .SPI0_SS3_F2H_SCP(
        VCC_net_1), .SPI1_CLK_IN(VCC_net_1), .SPI1_SDI_F2H_SCP(
        VCC_net_1), .SPI1_SDO_F2H_SCP(VCC_net_1), .SPI1_SS0_F2H_SCP(
        VCC_net_1), .SPI1_SS1_F2H_SCP(VCC_net_1), .SPI1_SS2_F2H_SCP(
        VCC_net_1), .SPI1_SS3_F2H_SCP(VCC_net_1), .TX_CLKPF(VCC_net_1), 
        .USER_MSS_GPIO_RESET_N(VCC_net_1), .USER_MSS_RESET_N(
        CORECONFIGP_0_SOFT_RESET_F2M_i_0), .XCLK_FAB(VCC_net_1), 
        .CLK_MDDR_APB(CORECONFIGP_0_APB_S_PCLK), .F_ARADDR_HADDR1({
        AXI_IF_0_BIF_1_ARADDR[31], AXI_IF_0_BIF_1_ARADDR[30], 
        AXI_IF_0_BIF_1_ARADDR[29], AXI_IF_0_BIF_1_ARADDR[28], 
        AXI_IF_0_BIF_1_ARADDR[27], AXI_IF_0_BIF_1_ARADDR[26], 
        AXI_IF_0_BIF_1_ARADDR[25], AXI_IF_0_BIF_1_ARADDR[24], 
        AXI_IF_0_BIF_1_ARADDR[23], AXI_IF_0_BIF_1_ARADDR[22], 
        AXI_IF_0_BIF_1_ARADDR[21], AXI_IF_0_BIF_1_ARADDR[20], 
        AXI_IF_0_BIF_1_ARADDR[19], AXI_IF_0_BIF_1_ARADDR[18], 
        AXI_IF_0_BIF_1_ARADDR[17], AXI_IF_0_BIF_1_ARADDR[16], 
        AXI_IF_0_BIF_1_ARADDR[15], AXI_IF_0_BIF_1_ARADDR[14], 
        AXI_IF_0_BIF_1_ARADDR[13], AXI_IF_0_BIF_1_ARADDR[12], 
        AXI_IF_0_BIF_1_ARADDR[11], AXI_IF_0_BIF_1_ARADDR[10], 
        AXI_IF_0_BIF_1_ARADDR[9], AXI_IF_0_BIF_1_ARADDR[8], 
        AXI_IF_0_BIF_1_ARADDR[7], GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .F_ARBURST_HTRANS1({GND_net_1, AXI_IF_0_BIF_1_ARSIZE[1]}), 
        .F_ARID_HSEL1({GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .F_ARLEN_HBURST1({VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .F_ARLOCK_HMASTLOCK1({GND_net_1, GND_net_1}), .F_ARSIZE_HSIZE1({
        AXI_IF_0_BIF_1_ARSIZE[1], AXI_IF_0_BIF_1_ARSIZE[1]}), 
        .F_ARVALID_HWRITE1(AXI_IF_0_BIF_1_ARVALID), .F_AWADDR_HADDR0({
        AXI_IF_0_BIF_1_AWADDR[31], AXI_IF_0_BIF_1_AWADDR[30], 
        AXI_IF_0_BIF_1_AWADDR[29], AXI_IF_0_BIF_1_AWADDR[28], 
        AXI_IF_0_BIF_1_AWADDR[27], AXI_IF_0_BIF_1_AWADDR[26], 
        AXI_IF_0_BIF_1_AWADDR[25], AXI_IF_0_BIF_1_AWADDR[24], 
        AXI_IF_0_BIF_1_AWADDR[23], AXI_IF_0_BIF_1_AWADDR[22], 
        AXI_IF_0_BIF_1_AWADDR[21], AXI_IF_0_BIF_1_AWADDR[20], 
        AXI_IF_0_BIF_1_AWADDR[19], AXI_IF_0_BIF_1_AWADDR[18], 
        AXI_IF_0_BIF_1_AWADDR[17], AXI_IF_0_BIF_1_AWADDR[16], 
        AXI_IF_0_BIF_1_AWADDR[15], AXI_IF_0_BIF_1_AWADDR[14], 
        AXI_IF_0_BIF_1_AWADDR[13], AXI_IF_0_BIF_1_AWADDR[12], 
        AXI_IF_0_BIF_1_AWADDR[11], AXI_IF_0_BIF_1_AWADDR[10], 
        AXI_IF_0_BIF_1_AWADDR[9], AXI_IF_0_BIF_1_AWADDR[8], 
        AXI_IF_0_BIF_1_AWADDR[7], GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .F_AWBURST_HTRANS0({GND_net_1, AXI_IF_0_BIF_1_AWSIZE[1]}), 
        .F_AWID_HSEL0({GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .F_AWLEN_HBURST0({VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .F_AWLOCK_HMASTLOCK0({GND_net_1, GND_net_1}), .F_AWSIZE_HSIZE0({
        AXI_IF_0_BIF_1_AWSIZE[1], AXI_IF_0_BIF_1_AWSIZE[1]}), 
        .F_AWVALID_HWRITE0(AXI_IF_0_BIF_1_AWVALID), .F_BREADY(
        VCC_net_1), .F_RMW_AXI(GND_net_1), .F_RREADY(
        AXI_IF_0_BIF_1_RREADY), .F_WDATA_HWDATA01({
        AXI_IF_0_BIF_1_WDATA[63], AXI_IF_0_BIF_1_WDATA[62], 
        AXI_IF_0_BIF_1_WDATA[61], AXI_IF_0_BIF_1_WDATA[60], 
        AXI_IF_0_BIF_1_WDATA[59], AXI_IF_0_BIF_1_WDATA[58], 
        AXI_IF_0_BIF_1_WDATA[57], AXI_IF_0_BIF_1_WDATA[56], 
        AXI_IF_0_BIF_1_WDATA[55], AXI_IF_0_BIF_1_WDATA[54], 
        AXI_IF_0_BIF_1_WDATA[53], AXI_IF_0_BIF_1_WDATA[52], 
        AXI_IF_0_BIF_1_WDATA[51], AXI_IF_0_BIF_1_WDATA[50], 
        AXI_IF_0_BIF_1_WDATA[49], AXI_IF_0_BIF_1_WDATA[48], 
        AXI_IF_0_BIF_1_WDATA[47], AXI_IF_0_BIF_1_WDATA[46], 
        AXI_IF_0_BIF_1_WDATA[45], AXI_IF_0_BIF_1_WDATA[44], 
        AXI_IF_0_BIF_1_WDATA[43], AXI_IF_0_BIF_1_WDATA[42], 
        AXI_IF_0_BIF_1_WDATA[41], AXI_IF_0_BIF_1_WDATA[40], 
        AXI_IF_0_BIF_1_WDATA[39], AXI_IF_0_BIF_1_WDATA[38], 
        AXI_IF_0_BIF_1_WDATA[37], AXI_IF_0_BIF_1_WDATA[36], 
        AXI_IF_0_BIF_1_WDATA[35], AXI_IF_0_BIF_1_WDATA[34], 
        AXI_IF_0_BIF_1_WDATA[33], AXI_IF_0_BIF_1_WDATA[32], 
        AXI_IF_0_BIF_1_WDATA[31], AXI_IF_0_BIF_1_WDATA[30], 
        AXI_IF_0_BIF_1_WDATA[29], AXI_IF_0_BIF_1_WDATA[28], 
        AXI_IF_0_BIF_1_WDATA[27], AXI_IF_0_BIF_1_WDATA[26], 
        AXI_IF_0_BIF_1_WDATA[25], AXI_IF_0_BIF_1_WDATA[24], 
        AXI_IF_0_BIF_1_WDATA[23], AXI_IF_0_BIF_1_WDATA[22], 
        AXI_IF_0_BIF_1_WDATA[21], AXI_IF_0_BIF_1_WDATA[20], 
        AXI_IF_0_BIF_1_WDATA[19], AXI_IF_0_BIF_1_WDATA[18], 
        AXI_IF_0_BIF_1_WDATA[17], AXI_IF_0_BIF_1_WDATA[16], 
        AXI_IF_0_BIF_1_WDATA[15], AXI_IF_0_BIF_1_WDATA[14], 
        AXI_IF_0_BIF_1_WDATA[13], AXI_IF_0_BIF_1_WDATA[12], 
        AXI_IF_0_BIF_1_WDATA[11], AXI_IF_0_BIF_1_WDATA[10], 
        AXI_IF_0_BIF_1_WDATA[9], AXI_IF_0_BIF_1_WDATA[8], 
        AXI_IF_0_BIF_1_WDATA[7], AXI_IF_0_BIF_1_WDATA[6], 
        AXI_IF_0_BIF_1_WDATA[5], AXI_IF_0_BIF_1_WDATA[4], 
        AXI_IF_0_BIF_1_WDATA[3], AXI_IF_0_BIF_1_WDATA[2], 
        AXI_IF_0_BIF_1_WDATA[1], AXI_IF_0_BIF_1_WDATA[0]}), 
        .F_WID_HREADY01({GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .F_WLAST(AXI_IF_0_BIF_1_WLAST), .F_WSTRB({
        AXI_IF_0_BIF_1_WSTRB[1], AXI_IF_0_BIF_1_WSTRB[1], 
        AXI_IF_0_BIF_1_WSTRB[1], AXI_IF_0_BIF_1_WSTRB[1], 
        AXI_IF_0_BIF_1_WSTRB[1], AXI_IF_0_BIF_1_WSTRB[1], 
        AXI_IF_0_BIF_1_WSTRB[1], AXI_IF_0_BIF_1_WSTRB[1]}), .F_WVALID(
        AXI_IF_0_BIF_1_WVALID), .FPGA_MDDR_ARESET_N(
        CORERESETP_0_MDDR_DDR_AXI_S_CORE_RESET_N), .MDDR_FABRIC_PADDR({
        CORECONFIGP_0_MDDR_APBmslave_PADDR[10], 
        CORECONFIGP_0_MDDR_APBmslave_PADDR[9], 
        CORECONFIGP_0_MDDR_APBmslave_PADDR[8], 
        CORECONFIGP_0_MDDR_APBmslave_PADDR[7], 
        CORECONFIGP_0_MDDR_APBmslave_PADDR[6], 
        CORECONFIGP_0_MDDR_APBmslave_PADDR[5], 
        CORECONFIGP_0_MDDR_APBmslave_PADDR[4], 
        CORECONFIGP_0_MDDR_APBmslave_PADDR[3], 
        CORECONFIGP_0_MDDR_APBmslave_PADDR[2]}), .MDDR_FABRIC_PENABLE(
        CORECONFIGP_0_MDDR_APBmslave_PENABLE), .MDDR_FABRIC_PSEL(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), .MDDR_FABRIC_PWDATA({
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[15], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[14], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[13], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[12], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[11], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[10], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[9], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[8], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[7], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[6], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[5], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[4], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[3], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[2], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[1], 
        CORECONFIGP_0_MDDR_APBmslave_PWDATA[0]}), .MDDR_FABRIC_PWRITE(
        CORECONFIGP_0_MDDR_APBmslave_PWRITE), .PRESET_N(
        CORECONFIGP_0_APB_S_PRESET_N), 
        .CAN_RXBUS_USBA_DATA1_MGPIO3A_IN(GND_net_1), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN(GND_net_1), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_IN(GND_net_1), .DM_IN({GND_net_1, 
        GND_net_1, GND_net_1, MDDR_DM_RDQS_1_PAD_Y, 
        MDDR_DM_RDQS_0_PAD_Y}), .DRAM_DQ_IN({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, MDDR_DQ_15_PAD_Y, 
        MDDR_DQ_14_PAD_Y, MDDR_DQ_13_PAD_Y, MDDR_DQ_12_PAD_Y, 
        MDDR_DQ_11_PAD_Y, MDDR_DQ_10_PAD_Y, MDDR_DQ_9_PAD_Y, 
        MDDR_DQ_8_PAD_Y, MDDR_DQ_7_PAD_Y, MDDR_DQ_6_PAD_Y, 
        MDDR_DQ_5_PAD_Y, MDDR_DQ_4_PAD_Y, MDDR_DQ_3_PAD_Y, 
        MDDR_DQ_2_PAD_Y, MDDR_DQ_1_PAD_Y, MDDR_DQ_0_PAD_Y}), 
        .DRAM_DQS_IN({GND_net_1, GND_net_1, GND_net_1, 
        MDDR_DQS_1_PAD_Y, MDDR_DQS_0_PAD_Y}), .DRAM_FIFO_WE_IN({
        GND_net_1, GND_net_1, MDDR_DQS_TMATCH_0_IN_PAD_Y}), 
        .I2C0_SCL_USBC_DATA1_MGPIO31B_IN(GND_net_1), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_IN(GND_net_1), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_IN(GND_net_1), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_IN(GND_net_1), .MGPIO0B_IN(
        GND_net_1), .MGPIO10B_IN(GND_net_1), .MGPIO1B_IN(GND_net_1), 
        .MGPIO25A_IN(GND_net_1), .MGPIO26A_IN(GND_net_1), .MGPIO27A_IN(
        GND_net_1), .MGPIO28A_IN(GND_net_1), .MGPIO29A_IN(GND_net_1), 
        .MGPIO2B_IN(GND_net_1), .MGPIO30A_IN(GND_net_1), .MGPIO31A_IN(
        GND_net_1), .MGPIO3B_IN(GND_net_1), .MGPIO4B_IN(GND_net_1), 
        .MGPIO5B_IN(GND_net_1), .MGPIO6B_IN(GND_net_1), .MGPIO7B_IN(
        GND_net_1), .MGPIO8B_IN(GND_net_1), .MGPIO9B_IN(GND_net_1), 
        .MMUART0_CTS_USBC_DATA7_MGPIO19B_IN(GND_net_1), 
        .MMUART0_DCD_MGPIO22B_IN(GND_net_1), .MMUART0_DSR_MGPIO20B_IN(
        GND_net_1), .MMUART0_DTR_USBC_DATA6_MGPIO18B_IN(GND_net_1), 
        .MMUART0_RI_MGPIO21B_IN(GND_net_1), 
        .MMUART0_RTS_USBC_DATA5_MGPIO17B_IN(GND_net_1), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_IN(MMUART_0_RXD_PAD_Y), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_IN(GND_net_1), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_IN(GND_net_1), 
        .MMUART1_CTS_MGPIO13B_IN(GND_net_1), .MMUART1_DCD_MGPIO16B_IN(
        GND_net_1), .MMUART1_DSR_MGPIO14B_IN(GND_net_1), 
        .MMUART1_DTR_MGPIO12B_IN(GND_net_1), .MMUART1_RI_MGPIO15B_IN(
        GND_net_1), .MMUART1_RTS_MGPIO11B_IN(GND_net_1), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_IN(GND_net_1), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_IN(GND_net_1), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_IN(GND_net_1), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN(GND_net_1), 
        .RGMII_MDC_RMII_MDC_IN(GND_net_1), 
        .RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN(GND_net_1), 
        .RGMII_RX_CLK_IN(GND_net_1), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN(GND_net_1), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN(GND_net_1), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN(GND_net_1), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN(GND_net_1), 
        .RGMII_RXD3_USBB_DATA4_IN(GND_net_1), .RGMII_TX_CLK_IN(
        GND_net_1), .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN(GND_net_1), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_IN(GND_net_1), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_IN(GND_net_1), 
        .RGMII_TXD2_USBB_DATA5_IN(GND_net_1), 
        .RGMII_TXD3_USBB_DATA6_IN(GND_net_1), .SPI0_SCK_USBA_XCLK_IN(
        GND_net_1), .SPI0_SDI_USBA_DIR_MGPIO5A_IN(GND_net_1), 
        .SPI0_SDO_USBA_STP_MGPIO6A_IN(GND_net_1), 
        .SPI0_SS0_USBA_NXT_MGPIO7A_IN(GND_net_1), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_IN(GND_net_1), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_IN(GND_net_1), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_IN(GND_net_1), 
        .SPI0_SS4_MGPIO19A_IN(GND_net_1), .SPI0_SS5_MGPIO20A_IN(
        GND_net_1), .SPI0_SS6_MGPIO21A_IN(GND_net_1), 
        .SPI0_SS7_MGPIO22A_IN(GND_net_1), .SPI1_SCK_IN(GND_net_1), 
        .SPI1_SDI_MGPIO11A_IN(GND_net_1), .SPI1_SDO_MGPIO12A_IN(
        GND_net_1), .SPI1_SS0_MGPIO13A_IN(GND_net_1), 
        .SPI1_SS1_MGPIO14A_IN(GND_net_1), .SPI1_SS2_MGPIO15A_IN(
        GND_net_1), .SPI1_SS3_MGPIO16A_IN(GND_net_1), 
        .SPI1_SS4_MGPIO17A_IN(GND_net_1), .SPI1_SS5_MGPIO18A_IN(
        GND_net_1), .SPI1_SS6_MGPIO23A_IN(GND_net_1), 
        .SPI1_SS7_MGPIO24A_IN(GND_net_1), .USBC_XCLK_IN(GND_net_1), 
        .USBD_DATA0_IN(GND_net_1), .USBD_DATA1_IN(GND_net_1), 
        .USBD_DATA2_IN(GND_net_1), .USBD_DATA3_IN(GND_net_1), 
        .USBD_DATA4_IN(GND_net_1), .USBD_DATA5_IN(GND_net_1), 
        .USBD_DATA6_IN(GND_net_1), .USBD_DATA7_MGPIO23B_IN(GND_net_1), 
        .USBD_DIR_IN(GND_net_1), .USBD_NXT_IN(GND_net_1), .USBD_STP_IN(
        GND_net_1), .USBD_XCLK_IN(GND_net_1), 
        .CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT(), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT(), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT(), .DRAM_ADDR({
        \DRAM_ADDR_net_0[15] , \DRAM_ADDR_net_0[14] , 
        \DRAM_ADDR_net_0[13] , \DRAM_ADDR_net_0[12] , 
        \DRAM_ADDR_net_0[11] , \DRAM_ADDR_net_0[10] , 
        \DRAM_ADDR_net_0[9] , \DRAM_ADDR_net_0[8] , 
        \DRAM_ADDR_net_0[7] , \DRAM_ADDR_net_0[6] , 
        \DRAM_ADDR_net_0[5] , \DRAM_ADDR_net_0[4] , 
        \DRAM_ADDR_net_0[3] , \DRAM_ADDR_net_0[2] , 
        \DRAM_ADDR_net_0[1] , \DRAM_ADDR_net_0[0] }), .DRAM_BA({
        \DRAM_BA_net_0[2] , \DRAM_BA_net_0[1] , \DRAM_BA_net_0[0] }), 
        .DRAM_CASN(MSS_ADLIB_INST_DRAM_CASN), .DRAM_CKE(
        MSS_ADLIB_INST_DRAM_CKE), .DRAM_CLK(MSS_ADLIB_INST_DRAM_CLK), 
        .DRAM_CSN(MSS_ADLIB_INST_DRAM_CSN), .DRAM_DM_RDQS_OUT({nc389, 
        nc390, nc391, \DRAM_DM_RDQS_OUT_net_0[1] , 
        \DRAM_DM_RDQS_OUT_net_0[0] }), .DRAM_DQ_OUT({nc392, nc393, 
        nc394, nc395, nc396, nc397, nc398, nc399, nc400, nc401, nc402, 
        nc403, nc404, nc405, nc406, nc407, nc408, nc409, nc410, nc411, 
        \DRAM_DQ_OUT_net_0[15] , \DRAM_DQ_OUT_net_0[14] , 
        \DRAM_DQ_OUT_net_0[13] , \DRAM_DQ_OUT_net_0[12] , 
        \DRAM_DQ_OUT_net_0[11] , \DRAM_DQ_OUT_net_0[10] , 
        \DRAM_DQ_OUT_net_0[9] , \DRAM_DQ_OUT_net_0[8] , 
        \DRAM_DQ_OUT_net_0[7] , \DRAM_DQ_OUT_net_0[6] , 
        \DRAM_DQ_OUT_net_0[5] , \DRAM_DQ_OUT_net_0[4] , 
        \DRAM_DQ_OUT_net_0[3] , \DRAM_DQ_OUT_net_0[2] , 
        \DRAM_DQ_OUT_net_0[1] , \DRAM_DQ_OUT_net_0[0] }), 
        .DRAM_DQS_OUT({nc412, nc413, nc414, \DRAM_DQS_OUT_net_0[1] , 
        \DRAM_DQS_OUT_net_0[0] }), .DRAM_FIFO_WE_OUT({nc415, nc416, 
        \DRAM_FIFO_WE_OUT_net_0[0] }), .DRAM_ODT(
        MSS_ADLIB_INST_DRAM_ODT), .DRAM_RASN(MSS_ADLIB_INST_DRAM_RASN), 
        .DRAM_RSTN(MSS_ADLIB_INST_DRAM_RSTN), .DRAM_WEN(
        MSS_ADLIB_INST_DRAM_WEN), .I2C0_SCL_USBC_DATA1_MGPIO31B_OUT(), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_OUT(), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_OUT(), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_OUT(), .MGPIO0B_OUT(), 
        .MGPIO10B_OUT(), .MGPIO1B_OUT(), .MGPIO25A_OUT(), 
        .MGPIO26A_OUT(), .MGPIO27A_OUT(), .MGPIO28A_OUT(), 
        .MGPIO29A_OUT(), .MGPIO2B_OUT(), .MGPIO30A_OUT(), 
        .MGPIO31A_OUT(), .MGPIO3B_OUT(), .MGPIO4B_OUT(), .MGPIO5B_OUT()
        , .MGPIO6B_OUT(), .MGPIO7B_OUT(), .MGPIO8B_OUT(), .MGPIO9B_OUT(
        ), .MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT(), 
        .MMUART0_DCD_MGPIO22B_OUT(), .MMUART0_DSR_MGPIO20B_OUT(), 
        .MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT(), 
        .MMUART0_RI_MGPIO21B_OUT(), 
        .MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT(), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_OUT(), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_OUT(), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_OUT(
        MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OUT), 
        .MMUART1_CTS_MGPIO13B_OUT(), .MMUART1_DCD_MGPIO16B_OUT(), 
        .MMUART1_DSR_MGPIO14B_OUT(), .MMUART1_DTR_MGPIO12B_OUT(), 
        .MMUART1_RI_MGPIO15B_OUT(), .MMUART1_RTS_MGPIO11B_OUT(), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT(), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT(), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT(), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT(), 
        .RGMII_MDC_RMII_MDC_OUT(), 
        .RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT(), .RGMII_RX_CLK_OUT(), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT(), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT(), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT(), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT(), 
        .RGMII_RXD3_USBB_DATA4_OUT(), .RGMII_TX_CLK_OUT(), 
        .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT(), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT(), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_OUT(), 
        .RGMII_TXD2_USBB_DATA5_OUT(), .RGMII_TXD3_USBB_DATA6_OUT(), 
        .SPI0_SCK_USBA_XCLK_OUT(), .SPI0_SDI_USBA_DIR_MGPIO5A_OUT(), 
        .SPI0_SDO_USBA_STP_MGPIO6A_OUT(), 
        .SPI0_SS0_USBA_NXT_MGPIO7A_OUT(), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_OUT(), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_OUT(), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_OUT(), .SPI0_SS4_MGPIO19A_OUT(), 
        .SPI0_SS5_MGPIO20A_OUT(), .SPI0_SS6_MGPIO21A_OUT(), 
        .SPI0_SS7_MGPIO22A_OUT(), .SPI1_SCK_OUT(), 
        .SPI1_SDI_MGPIO11A_OUT(), .SPI1_SDO_MGPIO12A_OUT(), 
        .SPI1_SS0_MGPIO13A_OUT(), .SPI1_SS1_MGPIO14A_OUT(), 
        .SPI1_SS2_MGPIO15A_OUT(), .SPI1_SS3_MGPIO16A_OUT(), 
        .SPI1_SS4_MGPIO17A_OUT(), .SPI1_SS5_MGPIO18A_OUT(), 
        .SPI1_SS6_MGPIO23A_OUT(), .SPI1_SS7_MGPIO24A_OUT(), 
        .USBC_XCLK_OUT(), .USBD_DATA0_OUT(), .USBD_DATA1_OUT(), 
        .USBD_DATA2_OUT(), .USBD_DATA3_OUT(), .USBD_DATA4_OUT(), 
        .USBD_DATA5_OUT(), .USBD_DATA6_OUT(), .USBD_DATA7_MGPIO23B_OUT(
        ), .USBD_DIR_OUT(), .USBD_NXT_OUT(), .USBD_STP_OUT(), 
        .USBD_XCLK_OUT(), .CAN_RXBUS_USBA_DATA1_MGPIO3A_OE(), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE(), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_OE(), .DM_OE({nc417, nc418, 
        nc419, \DM_OE_net_0[1] , \DM_OE_net_0[0] }), .DRAM_DQ_OE({
        nc420, nc421, nc422, nc423, nc424, nc425, nc426, nc427, nc428, 
        nc429, nc430, nc431, nc432, nc433, nc434, nc435, nc436, nc437, 
        nc438, nc439, \DRAM_DQ_OE_net_0[15] , \DRAM_DQ_OE_net_0[14] , 
        \DRAM_DQ_OE_net_0[13] , \DRAM_DQ_OE_net_0[12] , 
        \DRAM_DQ_OE_net_0[11] , \DRAM_DQ_OE_net_0[10] , 
        \DRAM_DQ_OE_net_0[9] , \DRAM_DQ_OE_net_0[8] , 
        \DRAM_DQ_OE_net_0[7] , \DRAM_DQ_OE_net_0[6] , 
        \DRAM_DQ_OE_net_0[5] , \DRAM_DQ_OE_net_0[4] , 
        \DRAM_DQ_OE_net_0[3] , \DRAM_DQ_OE_net_0[2] , 
        \DRAM_DQ_OE_net_0[1] , \DRAM_DQ_OE_net_0[0] }), .DRAM_DQS_OE({
        nc440, nc441, nc442, \DRAM_DQS_OE_net_0[1] , 
        \DRAM_DQS_OE_net_0[0] }), .I2C0_SCL_USBC_DATA1_MGPIO31B_OE(), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_OE(), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_OE(), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_OE(), .MGPIO0B_OE(), .MGPIO10B_OE(
        ), .MGPIO1B_OE(), .MGPIO25A_OE(), .MGPIO26A_OE(), .MGPIO27A_OE(
        ), .MGPIO28A_OE(), .MGPIO29A_OE(), .MGPIO2B_OE(), .MGPIO30A_OE(
        ), .MGPIO31A_OE(), .MGPIO3B_OE(), .MGPIO4B_OE(), .MGPIO5B_OE(), 
        .MGPIO6B_OE(), .MGPIO7B_OE(), .MGPIO8B_OE(), .MGPIO9B_OE(), 
        .MMUART0_CTS_USBC_DATA7_MGPIO19B_OE(), 
        .MMUART0_DCD_MGPIO22B_OE(), .MMUART0_DSR_MGPIO20B_OE(), 
        .MMUART0_DTR_USBC_DATA6_MGPIO18B_OE(), .MMUART0_RI_MGPIO21B_OE(
        ), .MMUART0_RTS_USBC_DATA5_MGPIO17B_OE(), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_OE(), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_OE(), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_OE(
        MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OE), 
        .MMUART1_CTS_MGPIO13B_OE(), .MMUART1_DCD_MGPIO16B_OE(), 
        .MMUART1_DSR_MGPIO14B_OE(), .MMUART1_DTR_MGPIO12B_OE(), 
        .MMUART1_RI_MGPIO15B_OE(), .MMUART1_RTS_MGPIO11B_OE(), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_OE(), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_OE(), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_OE(), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE(), .RGMII_MDC_RMII_MDC_OE(
        ), .RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE(), .RGMII_RX_CLK_OE(), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE(), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE(), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE(), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE(), 
        .RGMII_RXD3_USBB_DATA4_OE(), .RGMII_TX_CLK_OE(), 
        .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE(), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_OE(), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_OE(), .RGMII_TXD2_USBB_DATA5_OE(
        ), .RGMII_TXD3_USBB_DATA6_OE(), .SPI0_SCK_USBA_XCLK_OE(), 
        .SPI0_SDI_USBA_DIR_MGPIO5A_OE(), .SPI0_SDO_USBA_STP_MGPIO6A_OE(
        ), .SPI0_SS0_USBA_NXT_MGPIO7A_OE(), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_OE(), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_OE(), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_OE(), .SPI0_SS4_MGPIO19A_OE(), 
        .SPI0_SS5_MGPIO20A_OE(), .SPI0_SS6_MGPIO21A_OE(), 
        .SPI0_SS7_MGPIO22A_OE(), .SPI1_SCK_OE(), .SPI1_SDI_MGPIO11A_OE(
        ), .SPI1_SDO_MGPIO12A_OE(), .SPI1_SS0_MGPIO13A_OE(), 
        .SPI1_SS1_MGPIO14A_OE(), .SPI1_SS2_MGPIO15A_OE(), 
        .SPI1_SS3_MGPIO16A_OE(), .SPI1_SS4_MGPIO17A_OE(), 
        .SPI1_SS5_MGPIO18A_OE(), .SPI1_SS6_MGPIO23A_OE(), 
        .SPI1_SS7_MGPIO24A_OE(), .USBC_XCLK_OE(), .USBD_DATA0_OE(), 
        .USBD_DATA1_OE(), .USBD_DATA2_OE(), .USBD_DATA3_OE(), 
        .USBD_DATA4_OE(), .USBD_DATA5_OE(), .USBD_DATA6_OE(), 
        .USBD_DATA7_MGPIO23B_OE(), .USBD_DIR_OE(), .USBD_NXT_OE(), 
        .USBD_STP_OE(), .USBD_XCLK_OE());
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_RAS_N_PAD (.D(
        MSS_ADLIB_INST_DRAM_RASN), .PAD(MDDR_RAS_N));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_4_PAD (.PAD(MDDR_DQ[4]), .D(
        \DRAM_DQ_OUT_net_0[4] ), .E(\DRAM_DQ_OE_net_0[4] ), .Y(
        MDDR_DQ_4_PAD_Y));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_10_PAD (.D(
        \DRAM_ADDR_net_0[10] ), .PAD(MDDR_ADDR[10]));
    INBUF #( .IOSTD("SSTL15I") )  MDDR_DQS_TMATCH_0_IN_PAD (.PAD(
        MDDR_DQS_TMATCH_0_IN), .Y(MDDR_DQS_TMATCH_0_IN_PAD_Y));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_CS_N_PAD (.D(
        MSS_ADLIB_INST_DRAM_CSN), .PAD(MDDR_CS_N));
    CFG1 #( .INIT(2'h1) )  MSS_ADLIB_INST_RNIDR56_0 (.A(
        AXI_IF_0_BIF_1_RLAST), .Y(AXI_IF_0_BIF_1_RLAST_i_0));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_4_PAD (.D(
        \DRAM_ADDR_net_0[4] ), .PAD(MDDR_ADDR[4]));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_7_PAD (.PAD(MDDR_DQ[7]), .D(
        \DRAM_DQ_OUT_net_0[7] ), .E(\DRAM_DQ_OE_net_0[7] ), .Y(
        MDDR_DQ_7_PAD_Y));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_WE_N_PAD (.D(
        MSS_ADLIB_INST_DRAM_WEN), .PAD(MDDR_WE_N));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_8_PAD (.D(
        \DRAM_ADDR_net_0[8] ), .PAD(MDDR_ADDR[8]));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_15_PAD (.D(
        \DRAM_ADDR_net_0[15] ), .PAD(MDDR_ADDR[15]));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_0_PAD (.D(
        \DRAM_ADDR_net_0[0] ), .PAD(MDDR_ADDR[0]));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_1_PAD (.D(
        \DRAM_ADDR_net_0[1] ), .PAD(MDDR_ADDR[1]));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_13_PAD (.PAD(MDDR_DQ[13]), 
        .D(\DRAM_DQ_OUT_net_0[13] ), .E(\DRAM_DQ_OE_net_0[13] ), .Y(
        MDDR_DQ_13_PAD_Y));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_ADDR_3_PAD (.D(
        \DRAM_ADDR_net_0[3] ), .PAD(MDDR_ADDR[3]));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_BA_0_PAD (.D(
        \DRAM_BA_net_0[0] ), .PAD(MDDR_BA[0]));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_6_PAD (.PAD(MDDR_DQ[6]), .D(
        \DRAM_DQ_OUT_net_0[6] ), .E(\DRAM_DQ_OE_net_0[6] ), .Y(
        MDDR_DQ_6_PAD_Y));
    OUTBUF_DIFF #( .IOSTD("SSTL15I") )  MDDR_CLK_PAD (.D(
        MSS_ADLIB_INST_DRAM_CLK), .PADP(MDDR_CLK), .PADN(MDDR_CLK_N));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_14_PAD (.PAD(MDDR_DQ[14]), 
        .D(\DRAM_DQ_OUT_net_0[14] ), .E(\DRAM_DQ_OE_net_0[14] ), .Y(
        MDDR_DQ_14_PAD_Y));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_DQS_TMATCH_0_OUT_PAD (.D(
        \DRAM_FIFO_WE_OUT_net_0[0] ), .PAD(MDDR_DQS_TMATCH_0_OUT));
    OUTBUF #( .IOSTD("SSTL15I") )  MDDR_BA_1_PAD (.D(
        \DRAM_BA_net_0[1] ), .PAD(MDDR_BA[1]));
    BIBUF #( .IOSTD("SSTL15I") )  MDDR_DQ_5_PAD (.PAD(MDDR_DQ[5]), .D(
        \DRAM_DQ_OUT_net_0[5] ), .E(\DRAM_DQ_OE_net_0[5] ), .Y(
        MDDR_DQ_5_PAD_Y));
    
endmodule


module MDDR_TA(
       AHB_IF_0_BIF_1_HTRANS,
       AHB_IF_0_BIF_1_HADDR,
       HTRANS_1_fast,
       AHB_IF_0_BIF_1_HWDATA,
       MDDR_DQ,
       MDDR_DM_RDQS,
       MDDR_BA,
       MDDR_ADDR,
       AXI_IF_0_BIF_1_RDATA,
       AXI_IF_0_BIF_1_ARADDR,
       AXI_IF_0_BIF_1_ARSIZE,
       AXI_IF_0_BIF_1_AWADDR,
       AXI_IF_0_BIF_1_AWSIZE,
       AXI_IF_0_BIF_1_WDATA,
       AXI_IF_0_BIF_1_WSTRB,
       MDDR_DQS_N,
       MDDR_DQS,
       MDDR_TA_0_INIT_DONE,
       DEVRST_N,
       MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK,
       MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK_i_0,
       AHB_IF_0_BIF_1_HWRITE,
       HREADY_M_iv,
       HREADY_M_iv_i_0,
       AXI_IF_0_BIF_1_RVALID,
       AXI_IF_0_BIF_1_RVALID_i_0,
       AXI_IF_0_BIF_1_RLAST,
       AXI_IF_0_BIF_1_RLAST_i_0,
       MMUART_0_TXD,
       MMUART_0_RXD,
       MDDR_WE_N,
       MDDR_RESET_N,
       MDDR_RAS_N,
       MDDR_ODT,
       MDDR_DQS_TMATCH_0_OUT,
       MDDR_DQS_TMATCH_0_IN,
       MDDR_CS_N,
       MDDR_CKE,
       MDDR_CAS_N,
       MDDR_TA_0_GPIO_3_M2F,
       MDDR_TA_0_GPIO_4_M2F,
       MDDR_TA_0_GPIO_2_M2F,
       MDDR_TA_0_GPIO_1_M2F,
       MDDR_TA_0_GPIO_0_M2F,
       MDDR_TA_0_GPIO_5_M2F,
       MDDR_TA_0_GPIO_6_M2F,
       MDDR_TA_0_GPIO_7_M2F,
       AXI_IF_0_BIF_1_ARREADY,
       AXI_IF_0_BIF_1_AWREADY,
       AXI_IF_0_BIF_1_WREADY,
       AXI_IF_0_BIF_1_ARVALID,
       AXI_IF_0_BIF_1_AWVALID,
       AXI_IF_0_BIF_1_RREADY,
       AXI_IF_0_BIF_1_WLAST,
       AXI_IF_0_BIF_1_WVALID,
       MDDR_CLK_N,
       MDDR_CLK
    );
input  [1:1] AHB_IF_0_BIF_1_HTRANS;
input  [31:2] AHB_IF_0_BIF_1_HADDR;
input  [1:1] HTRANS_1_fast;
input  [13:0] AHB_IF_0_BIF_1_HWDATA;
inout  [15:0] MDDR_DQ;
inout  [1:0] MDDR_DM_RDQS;
output [2:0] MDDR_BA;
output [15:0] MDDR_ADDR;
output [63:0] AXI_IF_0_BIF_1_RDATA;
input  [31:7] AXI_IF_0_BIF_1_ARADDR;
input  [1:1] AXI_IF_0_BIF_1_ARSIZE;
input  [31:7] AXI_IF_0_BIF_1_AWADDR;
input  [1:1] AXI_IF_0_BIF_1_AWSIZE;
input  [63:0] AXI_IF_0_BIF_1_WDATA;
input  [1:1] AXI_IF_0_BIF_1_WSTRB;
inout  [1:0] MDDR_DQS_N;
inout  [1:0] MDDR_DQS;
output MDDR_TA_0_INIT_DONE;
input  DEVRST_N;
output MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK;
output MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK_i_0;
input  AHB_IF_0_BIF_1_HWRITE;
output HREADY_M_iv;
output HREADY_M_iv_i_0;
inout  AXI_IF_0_BIF_1_RVALID;
output AXI_IF_0_BIF_1_RVALID_i_0;
inout  AXI_IF_0_BIF_1_RLAST;
output AXI_IF_0_BIF_1_RLAST_i_0;
output MMUART_0_TXD;
input  MMUART_0_RXD;
output MDDR_WE_N;
output MDDR_RESET_N;
output MDDR_RAS_N;
output MDDR_ODT;
output MDDR_DQS_TMATCH_0_OUT;
input  MDDR_DQS_TMATCH_0_IN;
output MDDR_CS_N;
output MDDR_CKE;
output MDDR_CAS_N;
output MDDR_TA_0_GPIO_3_M2F;
output MDDR_TA_0_GPIO_4_M2F;
output MDDR_TA_0_GPIO_2_M2F;
output MDDR_TA_0_GPIO_1_M2F;
output MDDR_TA_0_GPIO_0_M2F;
output MDDR_TA_0_GPIO_5_M2F;
output MDDR_TA_0_GPIO_6_M2F;
output MDDR_TA_0_GPIO_7_M2F;
output AXI_IF_0_BIF_1_ARREADY;
output AXI_IF_0_BIF_1_AWREADY;
output AXI_IF_0_BIF_1_WREADY;
input  AXI_IF_0_BIF_1_ARVALID;
input  AXI_IF_0_BIF_1_AWVALID;
input  AXI_IF_0_BIF_1_RREADY;
input  AXI_IF_0_BIF_1_WLAST;
input  AXI_IF_0_BIF_1_WVALID;
output MDDR_CLK_N;
output MDDR_CLK;

    wire INIT_DONE, POWER_ON_RESET_N, GL0_INST, LOCK, 
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC, 
        \CoreAHBLite_0_AHBmslave16_HWDATA[0] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[1] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[2] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[3] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[4] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[5] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[6] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[7] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[8] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[9] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[10] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[11] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[12] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[13] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[12] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[13] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[14] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[15] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[16] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[17] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[18] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[19] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[20] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[21] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[22] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[23] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[24] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[25] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[26] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[27] , 
        MSS_HPMS_READY_int_RNIPJE6, CoreAHBLite_0_AHBmslave16_HREADY, 
        N_259_i_0, N_149_i_0, N_166_i_0, N_165_i_0, N_162_i_0, 
        N_150_i_0, N_164_i_0, N_163_i_0, N_161_i_0, N_160_i_0, 
        N_159_i_0, N_158_i_0, N_157_i_0, N_156_i_0, N_155_i_0, 
        N_154_i_0, N_153_i_0, N_152_i_0, 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[2] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[3] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[4] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[5] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[6] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[7] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[8] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[9] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[10] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[13] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[15] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[16] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[2] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[3] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[4] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[5] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[6] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[7] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[8] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[9] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[10] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[12] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[0] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[1] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[2] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[3] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[4] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[5] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[6] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[7] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[8] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[9] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[10] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[11] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[12] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[13] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[14] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[15] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[0] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[1] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[2] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[3] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[4] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[5] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[6] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[7] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[8] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[9] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[10] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[11] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[12] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[13] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[14] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[15] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[16] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[4] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[5] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[6] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[7] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[8] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[9] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[10] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[11] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[12] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[13] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[14] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[15] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[16] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[18] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[0] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[1] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[2] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[3] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[0] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[1] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[2] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[3] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[4] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[5] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[6] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[7] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[8] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[9] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[10] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[11] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[12] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[13] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[14] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[15] , 
        CORECONFIGP_0_SOFT_RESET_F2M_i_0, 
        CORECONFIGP_0_SOFT_M3_RESET_i_0, CORECONFIGP_0_APB_S_PRESET_N, 
        CORECONFIGP_0_APB_S_PCLK, CORECONFIGP_0_CONFIG1_DONE, 
        CORECONFIGP_0_CONFIG2_DONE, 
        CORECONFIGP_0_SOFT_MDDR_DDR_AXI_S_CORE_RESET, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PREADY, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSLVERR, 
        CORECONFIGP_0_MDDR_APBmslave_PWRITE, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE, 
        CORECONFIGP_0_MDDR_APBmslave_PENABLE, 
        CORECONFIGP_0_APB_S_PCLK_i_0, 
        CORECONFIGP_0_MDDR_APBmslave_PSELx, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE, 
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSELx, 
        CORECONFIGP_0_MDDR_APBmslave_PSLVERR, 
        CORECONFIGP_0_MDDR_APBmslave_PREADY, 
        FABOSC_0_RCOSC_25_50MHZ_O2F, MDDR_TA_MSS_TMP_0_MSS_RESET_N_M2F, 
        CORERESETP_0_MDDR_DDR_AXI_S_CORE_RESET_N, GND_net_1, VCC_net_1;
    
    MDDR_TA_FABOSC_0_OSC FABOSC_0 (.FABOSC_0_RCOSC_25_50MHZ_O2F(
        FABOSC_0_RCOSC_25_50MHZ_O2F), 
        .FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC));
    CoreResetP_Z10 CORERESETP_0 (.MSS_HPMS_READY_int_RNIPJE6(
        MSS_HPMS_READY_int_RNIPJE6), .FABOSC_0_RCOSC_25_50MHZ_O2F(
        FABOSC_0_RCOSC_25_50MHZ_O2F), .GL0_INST(GL0_INST), .INIT_DONE(
        INIT_DONE), .POWER_ON_RESET_N(POWER_ON_RESET_N), 
        .MDDR_TA_MSS_TMP_0_MSS_RESET_N_M2F(
        MDDR_TA_MSS_TMP_0_MSS_RESET_N_M2F), 
        .CORECONFIGP_0_APB_S_PRESET_N(CORECONFIGP_0_APB_S_PRESET_N), 
        .CORECONFIGP_0_CONFIG1_DONE(CORECONFIGP_0_CONFIG1_DONE), 
        .CORECONFIGP_0_CONFIG2_DONE(CORECONFIGP_0_CONFIG2_DONE), 
        .CORECONFIGP_0_SOFT_MDDR_DDR_AXI_S_CORE_RESET(
        CORECONFIGP_0_SOFT_MDDR_DDR_AXI_S_CORE_RESET), 
        .CORERESETP_0_MDDR_DDR_AXI_S_CORE_RESET_N(
        CORERESETP_0_MDDR_DDR_AXI_S_CORE_RESET_N));
    CoreAHBLite_Z6 CoreAHBLite_0 (.AHB_IF_0_BIF_1_HTRANS({
        AHB_IF_0_BIF_1_HTRANS[1]}), .AHB_IF_0_BIF_1_HADDR({
        AHB_IF_0_BIF_1_HADDR[31], AHB_IF_0_BIF_1_HADDR[30], 
        AHB_IF_0_BIF_1_HADDR[29], AHB_IF_0_BIF_1_HADDR[28], 
        AHB_IF_0_BIF_1_HADDR[27], AHB_IF_0_BIF_1_HADDR[26], 
        AHB_IF_0_BIF_1_HADDR[25], AHB_IF_0_BIF_1_HADDR[24], 
        AHB_IF_0_BIF_1_HADDR[23], AHB_IF_0_BIF_1_HADDR[22], 
        AHB_IF_0_BIF_1_HADDR[21], AHB_IF_0_BIF_1_HADDR[20], 
        AHB_IF_0_BIF_1_HADDR[19], AHB_IF_0_BIF_1_HADDR[18], 
        AHB_IF_0_BIF_1_HADDR[17], AHB_IF_0_BIF_1_HADDR[16], 
        AHB_IF_0_BIF_1_HADDR[15], AHB_IF_0_BIF_1_HADDR[14], 
        AHB_IF_0_BIF_1_HADDR[13], AHB_IF_0_BIF_1_HADDR[12], 
        AHB_IF_0_BIF_1_HADDR[11], AHB_IF_0_BIF_1_HADDR[10], 
        AHB_IF_0_BIF_1_HADDR[9], AHB_IF_0_BIF_1_HADDR[8], 
        AHB_IF_0_BIF_1_HADDR[7], AHB_IF_0_BIF_1_HADDR[6], 
        AHB_IF_0_BIF_1_HADDR[5], AHB_IF_0_BIF_1_HADDR[4], 
        AHB_IF_0_BIF_1_HADDR[3], AHB_IF_0_BIF_1_HADDR[2]}), 
        .HTRANS_1_fast({HTRANS_1_fast[1]}), .AHB_IF_0_BIF_1_HWDATA({
        AHB_IF_0_BIF_1_HWDATA[13], AHB_IF_0_BIF_1_HWDATA[12], 
        AHB_IF_0_BIF_1_HWDATA[11], AHB_IF_0_BIF_1_HWDATA[10], 
        AHB_IF_0_BIF_1_HWDATA[9], AHB_IF_0_BIF_1_HWDATA[8], 
        AHB_IF_0_BIF_1_HWDATA[7], AHB_IF_0_BIF_1_HWDATA[6], 
        AHB_IF_0_BIF_1_HWDATA[5], AHB_IF_0_BIF_1_HWDATA[4], 
        AHB_IF_0_BIF_1_HWDATA[3], AHB_IF_0_BIF_1_HWDATA[2], 
        AHB_IF_0_BIF_1_HWDATA[1], AHB_IF_0_BIF_1_HWDATA[0]}), 
        .CoreAHBLite_0_AHBmslave16_HWDATA({
        \CoreAHBLite_0_AHBmslave16_HWDATA[13] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[12] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[11] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[10] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[9] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[8] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[7] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[6] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[5] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[4] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[3] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[2] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[1] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[0] }), 
        .CoreAHBLite_0_AHBmslave16_HADDR({
        \CoreAHBLite_0_AHBmslave16_HADDR[27] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[26] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[25] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[24] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[23] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[22] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[21] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[20] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[19] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[18] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[17] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[16] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[15] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[14] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[13] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[12] }), 
        .MSS_HPMS_READY_int_RNIPJE6(MSS_HPMS_READY_int_RNIPJE6), 
        .GL0_INST(GL0_INST), .AHB_IF_0_BIF_1_HWRITE(
        AHB_IF_0_BIF_1_HWRITE), .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY), .HREADY_M_iv(HREADY_M_iv), 
        .HREADY_M_iv_i_0(HREADY_M_iv_i_0), .N_259_i_0(N_259_i_0), 
        .N_149_i_0(N_149_i_0), .N_166_i_0(N_166_i_0), .N_165_i_0(
        N_165_i_0), .N_162_i_0(N_162_i_0), .N_150_i_0(N_150_i_0), 
        .N_164_i_0(N_164_i_0), .N_163_i_0(N_163_i_0), .N_161_i_0(
        N_161_i_0), .N_160_i_0(N_160_i_0), .N_159_i_0(N_159_i_0), 
        .N_158_i_0(N_158_i_0), .N_157_i_0(N_157_i_0), .N_156_i_0(
        N_156_i_0), .N_155_i_0(N_155_i_0), .N_154_i_0(N_154_i_0), 
        .N_153_i_0(N_153_i_0), .N_152_i_0(N_152_i_0));
    VCC VCC (.Y(VCC_net_1));
    CLKINT INIT_DONE_keep_RNIL648 (.A(INIT_DONE), .Y(
        MDDR_TA_0_INIT_DONE));
    MDDR_TA_CCC_0_FCCC CCC_0 (.MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), 
        .MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK_i_0(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK_i_0), .GL0_INST(GL0_INST), 
        .LOCK(LOCK), 
        .FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC));
    GND GND (.Y(GND_net_1));
    CoreConfigP_Z9 CORECONFIGP_0 (.CORECONFIGP_0_MDDR_APBmslave_PADDR({
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[10] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[9] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[8] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[7] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[6] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[5] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[4] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[3] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[2] }), 
        .CORECONFIGP_0_MDDR_APBmslave_PWDATA({
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[15] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[14] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[13] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[12] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[11] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[10] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[9] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[8] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[7] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[6] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[5] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[4] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[3] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[2] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[1] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[0] }), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA({
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[16] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[15] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[14] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[13] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[12] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[11] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[10] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[9] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[8] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[7] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[6] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[5] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[4] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[3] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[2] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[1] , 
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[0] }), 
        .CORECONFIGP_0_MDDR_APBmslave_PRDATA({
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[15] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[14] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[13] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[12] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[11] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[10] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[9] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[8] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[7] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[6] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[5] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[4] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[3] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[2] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[1] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[0] }), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_11(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[13] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_13(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[15] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_14(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[16] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[2] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[3] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[4] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_3(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[5] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_4(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[6] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_5(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[7] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_6(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[8] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_7(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[9] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_8(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[10] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_10(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[12] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_4(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[4] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_5(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[5] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_6(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[6] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_7(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[7] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_8(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[8] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_9(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[9] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_10(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[10] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_11(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[11] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_12(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[12] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_13(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[13] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_14(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[14] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_15(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[15] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_16(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[16] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_18(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[18] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_0(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[0] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_1(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[1] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_2(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[2] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_3(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[3] ), 
        .CORECONFIGP_0_SOFT_RESET_F2M_i_0(
        CORECONFIGP_0_SOFT_RESET_F2M_i_0), 
        .CORECONFIGP_0_SOFT_M3_RESET_i_0(
        CORECONFIGP_0_SOFT_M3_RESET_i_0), 
        .CORECONFIGP_0_APB_S_PRESET_N(CORECONFIGP_0_APB_S_PRESET_N), 
        .CORECONFIGP_0_APB_S_PCLK(CORECONFIGP_0_APB_S_PCLK), 
        .CORECONFIGP_0_CONFIG1_DONE(CORECONFIGP_0_CONFIG1_DONE), 
        .CORECONFIGP_0_CONFIG2_DONE(CORECONFIGP_0_CONFIG2_DONE), 
        .CORECONFIGP_0_SOFT_MDDR_DDR_AXI_S_CORE_RESET(
        CORECONFIGP_0_SOFT_MDDR_DDR_AXI_S_CORE_RESET), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PREADY(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PREADY), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSLVERR(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSLVERR), 
        .CORECONFIGP_0_MDDR_APBmslave_PWRITE(
        CORECONFIGP_0_MDDR_APBmslave_PWRITE), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE), 
        .CORECONFIGP_0_MDDR_APBmslave_PENABLE(
        CORECONFIGP_0_MDDR_APBmslave_PENABLE), 
        .CORECONFIGP_0_APB_S_PCLK_i_0(CORECONFIGP_0_APB_S_PCLK_i_0), 
        .INIT_DONE(INIT_DONE), .CORECONFIGP_0_MDDR_APBmslave_PSELx(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSELx(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSELx), 
        .CORECONFIGP_0_MDDR_APBmslave_PSLVERR(
        CORECONFIGP_0_MDDR_APBmslave_PSLVERR), 
        .CORECONFIGP_0_MDDR_APBmslave_PREADY(
        CORECONFIGP_0_MDDR_APBmslave_PREADY));
    MDDR_TA_MSS MDDR_TA_MSS_0 (.MDDR_DQ({MDDR_DQ[15], MDDR_DQ[14], 
        MDDR_DQ[13], MDDR_DQ[12], MDDR_DQ[11], MDDR_DQ[10], MDDR_DQ[9], 
        MDDR_DQ[8], MDDR_DQ[7], MDDR_DQ[6], MDDR_DQ[5], MDDR_DQ[4], 
        MDDR_DQ[3], MDDR_DQ[2], MDDR_DQ[1], MDDR_DQ[0]}), 
        .MDDR_DM_RDQS({MDDR_DM_RDQS[1], MDDR_DM_RDQS[0]}), .MDDR_BA({
        MDDR_BA[2], MDDR_BA[1], MDDR_BA[0]}), .MDDR_ADDR({
        MDDR_ADDR[15], MDDR_ADDR[14], MDDR_ADDR[13], MDDR_ADDR[12], 
        MDDR_ADDR[11], MDDR_ADDR[10], MDDR_ADDR[9], MDDR_ADDR[8], 
        MDDR_ADDR[7], MDDR_ADDR[6], MDDR_ADDR[5], MDDR_ADDR[4], 
        MDDR_ADDR[3], MDDR_ADDR[2], MDDR_ADDR[1], MDDR_ADDR[0]}), 
        .AXI_IF_0_BIF_1_RDATA({AXI_IF_0_BIF_1_RDATA[63], 
        AXI_IF_0_BIF_1_RDATA[62], AXI_IF_0_BIF_1_RDATA[61], 
        AXI_IF_0_BIF_1_RDATA[60], AXI_IF_0_BIF_1_RDATA[59], 
        AXI_IF_0_BIF_1_RDATA[58], AXI_IF_0_BIF_1_RDATA[57], 
        AXI_IF_0_BIF_1_RDATA[56], AXI_IF_0_BIF_1_RDATA[55], 
        AXI_IF_0_BIF_1_RDATA[54], AXI_IF_0_BIF_1_RDATA[53], 
        AXI_IF_0_BIF_1_RDATA[52], AXI_IF_0_BIF_1_RDATA[51], 
        AXI_IF_0_BIF_1_RDATA[50], AXI_IF_0_BIF_1_RDATA[49], 
        AXI_IF_0_BIF_1_RDATA[48], AXI_IF_0_BIF_1_RDATA[47], 
        AXI_IF_0_BIF_1_RDATA[46], AXI_IF_0_BIF_1_RDATA[45], 
        AXI_IF_0_BIF_1_RDATA[44], AXI_IF_0_BIF_1_RDATA[43], 
        AXI_IF_0_BIF_1_RDATA[42], AXI_IF_0_BIF_1_RDATA[41], 
        AXI_IF_0_BIF_1_RDATA[40], AXI_IF_0_BIF_1_RDATA[39], 
        AXI_IF_0_BIF_1_RDATA[38], AXI_IF_0_BIF_1_RDATA[37], 
        AXI_IF_0_BIF_1_RDATA[36], AXI_IF_0_BIF_1_RDATA[35], 
        AXI_IF_0_BIF_1_RDATA[34], AXI_IF_0_BIF_1_RDATA[33], 
        AXI_IF_0_BIF_1_RDATA[32], AXI_IF_0_BIF_1_RDATA[31], 
        AXI_IF_0_BIF_1_RDATA[30], AXI_IF_0_BIF_1_RDATA[29], 
        AXI_IF_0_BIF_1_RDATA[28], AXI_IF_0_BIF_1_RDATA[27], 
        AXI_IF_0_BIF_1_RDATA[26], AXI_IF_0_BIF_1_RDATA[25], 
        AXI_IF_0_BIF_1_RDATA[24], AXI_IF_0_BIF_1_RDATA[23], 
        AXI_IF_0_BIF_1_RDATA[22], AXI_IF_0_BIF_1_RDATA[21], 
        AXI_IF_0_BIF_1_RDATA[20], AXI_IF_0_BIF_1_RDATA[19], 
        AXI_IF_0_BIF_1_RDATA[18], AXI_IF_0_BIF_1_RDATA[17], 
        AXI_IF_0_BIF_1_RDATA[16], AXI_IF_0_BIF_1_RDATA[15], 
        AXI_IF_0_BIF_1_RDATA[14], AXI_IF_0_BIF_1_RDATA[13], 
        AXI_IF_0_BIF_1_RDATA[12], AXI_IF_0_BIF_1_RDATA[11], 
        AXI_IF_0_BIF_1_RDATA[10], AXI_IF_0_BIF_1_RDATA[9], 
        AXI_IF_0_BIF_1_RDATA[8], AXI_IF_0_BIF_1_RDATA[7], 
        AXI_IF_0_BIF_1_RDATA[6], AXI_IF_0_BIF_1_RDATA[5], 
        AXI_IF_0_BIF_1_RDATA[4], AXI_IF_0_BIF_1_RDATA[3], 
        AXI_IF_0_BIF_1_RDATA[2], AXI_IF_0_BIF_1_RDATA[1], 
        AXI_IF_0_BIF_1_RDATA[0]}), 
        .CORECONFIGP_0_MDDR_APBmslave_PRDATA({
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[15] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[14] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[13] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[12] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[11] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[10] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[9] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[8] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[7] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[6] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[5] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[4] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[3] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[2] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[1] , 
        \CORECONFIGP_0_MDDR_APBmslave_PRDATA[0] }), 
        .CoreAHBLite_0_AHBmslave16_HADDR({
        \CoreAHBLite_0_AHBmslave16_HADDR[27] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[26] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[25] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[24] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[23] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[22] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[21] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[20] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[19] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[18] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[17] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[16] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[15] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[14] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[13] , 
        \CoreAHBLite_0_AHBmslave16_HADDR[12] }), 
        .CoreAHBLite_0_AHBmslave16_HWDATA({
        \CoreAHBLite_0_AHBmslave16_HWDATA[13] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[12] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[11] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[10] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[9] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[8] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[7] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[6] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[5] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[4] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[3] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[2] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[1] , 
        \CoreAHBLite_0_AHBmslave16_HWDATA[0] }), 
        .AXI_IF_0_BIF_1_ARADDR({AXI_IF_0_BIF_1_ARADDR[31], 
        AXI_IF_0_BIF_1_ARADDR[30], AXI_IF_0_BIF_1_ARADDR[29], 
        AXI_IF_0_BIF_1_ARADDR[28], AXI_IF_0_BIF_1_ARADDR[27], 
        AXI_IF_0_BIF_1_ARADDR[26], AXI_IF_0_BIF_1_ARADDR[25], 
        AXI_IF_0_BIF_1_ARADDR[24], AXI_IF_0_BIF_1_ARADDR[23], 
        AXI_IF_0_BIF_1_ARADDR[22], AXI_IF_0_BIF_1_ARADDR[21], 
        AXI_IF_0_BIF_1_ARADDR[20], AXI_IF_0_BIF_1_ARADDR[19], 
        AXI_IF_0_BIF_1_ARADDR[18], AXI_IF_0_BIF_1_ARADDR[17], 
        AXI_IF_0_BIF_1_ARADDR[16], AXI_IF_0_BIF_1_ARADDR[15], 
        AXI_IF_0_BIF_1_ARADDR[14], AXI_IF_0_BIF_1_ARADDR[13], 
        AXI_IF_0_BIF_1_ARADDR[12], AXI_IF_0_BIF_1_ARADDR[11], 
        AXI_IF_0_BIF_1_ARADDR[10], AXI_IF_0_BIF_1_ARADDR[9], 
        AXI_IF_0_BIF_1_ARADDR[8], AXI_IF_0_BIF_1_ARADDR[7]}), 
        .AXI_IF_0_BIF_1_ARSIZE({AXI_IF_0_BIF_1_ARSIZE[1]}), 
        .AXI_IF_0_BIF_1_AWADDR({AXI_IF_0_BIF_1_AWADDR[31], 
        AXI_IF_0_BIF_1_AWADDR[30], AXI_IF_0_BIF_1_AWADDR[29], 
        AXI_IF_0_BIF_1_AWADDR[28], AXI_IF_0_BIF_1_AWADDR[27], 
        AXI_IF_0_BIF_1_AWADDR[26], AXI_IF_0_BIF_1_AWADDR[25], 
        AXI_IF_0_BIF_1_AWADDR[24], AXI_IF_0_BIF_1_AWADDR[23], 
        AXI_IF_0_BIF_1_AWADDR[22], AXI_IF_0_BIF_1_AWADDR[21], 
        AXI_IF_0_BIF_1_AWADDR[20], AXI_IF_0_BIF_1_AWADDR[19], 
        AXI_IF_0_BIF_1_AWADDR[18], AXI_IF_0_BIF_1_AWADDR[17], 
        AXI_IF_0_BIF_1_AWADDR[16], AXI_IF_0_BIF_1_AWADDR[15], 
        AXI_IF_0_BIF_1_AWADDR[14], AXI_IF_0_BIF_1_AWADDR[13], 
        AXI_IF_0_BIF_1_AWADDR[12], AXI_IF_0_BIF_1_AWADDR[11], 
        AXI_IF_0_BIF_1_AWADDR[10], AXI_IF_0_BIF_1_AWADDR[9], 
        AXI_IF_0_BIF_1_AWADDR[8], AXI_IF_0_BIF_1_AWADDR[7]}), 
        .AXI_IF_0_BIF_1_AWSIZE({AXI_IF_0_BIF_1_AWSIZE[1]}), 
        .AXI_IF_0_BIF_1_WDATA({AXI_IF_0_BIF_1_WDATA[63], 
        AXI_IF_0_BIF_1_WDATA[62], AXI_IF_0_BIF_1_WDATA[61], 
        AXI_IF_0_BIF_1_WDATA[60], AXI_IF_0_BIF_1_WDATA[59], 
        AXI_IF_0_BIF_1_WDATA[58], AXI_IF_0_BIF_1_WDATA[57], 
        AXI_IF_0_BIF_1_WDATA[56], AXI_IF_0_BIF_1_WDATA[55], 
        AXI_IF_0_BIF_1_WDATA[54], AXI_IF_0_BIF_1_WDATA[53], 
        AXI_IF_0_BIF_1_WDATA[52], AXI_IF_0_BIF_1_WDATA[51], 
        AXI_IF_0_BIF_1_WDATA[50], AXI_IF_0_BIF_1_WDATA[49], 
        AXI_IF_0_BIF_1_WDATA[48], AXI_IF_0_BIF_1_WDATA[47], 
        AXI_IF_0_BIF_1_WDATA[46], AXI_IF_0_BIF_1_WDATA[45], 
        AXI_IF_0_BIF_1_WDATA[44], AXI_IF_0_BIF_1_WDATA[43], 
        AXI_IF_0_BIF_1_WDATA[42], AXI_IF_0_BIF_1_WDATA[41], 
        AXI_IF_0_BIF_1_WDATA[40], AXI_IF_0_BIF_1_WDATA[39], 
        AXI_IF_0_BIF_1_WDATA[38], AXI_IF_0_BIF_1_WDATA[37], 
        AXI_IF_0_BIF_1_WDATA[36], AXI_IF_0_BIF_1_WDATA[35], 
        AXI_IF_0_BIF_1_WDATA[34], AXI_IF_0_BIF_1_WDATA[33], 
        AXI_IF_0_BIF_1_WDATA[32], AXI_IF_0_BIF_1_WDATA[31], 
        AXI_IF_0_BIF_1_WDATA[30], AXI_IF_0_BIF_1_WDATA[29], 
        AXI_IF_0_BIF_1_WDATA[28], AXI_IF_0_BIF_1_WDATA[27], 
        AXI_IF_0_BIF_1_WDATA[26], AXI_IF_0_BIF_1_WDATA[25], 
        AXI_IF_0_BIF_1_WDATA[24], AXI_IF_0_BIF_1_WDATA[23], 
        AXI_IF_0_BIF_1_WDATA[22], AXI_IF_0_BIF_1_WDATA[21], 
        AXI_IF_0_BIF_1_WDATA[20], AXI_IF_0_BIF_1_WDATA[19], 
        AXI_IF_0_BIF_1_WDATA[18], AXI_IF_0_BIF_1_WDATA[17], 
        AXI_IF_0_BIF_1_WDATA[16], AXI_IF_0_BIF_1_WDATA[15], 
        AXI_IF_0_BIF_1_WDATA[14], AXI_IF_0_BIF_1_WDATA[13], 
        AXI_IF_0_BIF_1_WDATA[12], AXI_IF_0_BIF_1_WDATA[11], 
        AXI_IF_0_BIF_1_WDATA[10], AXI_IF_0_BIF_1_WDATA[9], 
        AXI_IF_0_BIF_1_WDATA[8], AXI_IF_0_BIF_1_WDATA[7], 
        AXI_IF_0_BIF_1_WDATA[6], AXI_IF_0_BIF_1_WDATA[5], 
        AXI_IF_0_BIF_1_WDATA[4], AXI_IF_0_BIF_1_WDATA[3], 
        AXI_IF_0_BIF_1_WDATA[2], AXI_IF_0_BIF_1_WDATA[1], 
        AXI_IF_0_BIF_1_WDATA[0]}), .AXI_IF_0_BIF_1_WSTRB({
        AXI_IF_0_BIF_1_WSTRB[1]}), .CORECONFIGP_0_MDDR_APBmslave_PADDR({
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[10] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[9] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[8] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[7] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[6] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[5] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[4] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[3] , 
        \CORECONFIGP_0_MDDR_APBmslave_PADDR[2] }), 
        .CORECONFIGP_0_MDDR_APBmslave_PWDATA({
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[15] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[14] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[13] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[12] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[11] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[10] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[9] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[8] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[7] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[6] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[5] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[4] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[3] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[2] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[1] , 
        \CORECONFIGP_0_MDDR_APBmslave_PWDATA[0] }), .MDDR_DQS_N({
        MDDR_DQS_N[1], MDDR_DQS_N[0]}), .MDDR_DQS({MDDR_DQS[1], 
        MDDR_DQS[0]}), .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_0(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[2] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_1(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[3] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_2(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[4] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_3(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[5] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_4(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[6] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_5(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[7] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_6(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[8] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_7(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[9] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_8(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[10] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_10(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[12] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_11(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[13] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_13(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[15] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR_14(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR[16] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_0(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[0] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_1(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[1] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_2(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[2] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_3(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[3] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_4(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[4] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_5(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[5] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_6(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[6] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_7(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[7] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_8(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[8] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_9(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[9] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_10(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[10] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_11(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[11] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_12(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[12] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_13(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[13] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_14(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[14] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_15(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[15] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA_16(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA[16] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_0(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[0] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_1(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[1] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_2(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[2] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_3(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[3] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_4(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[4] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_5(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[5] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_6(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[6] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_7(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[7] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_8(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[8] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_9(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[9] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_10(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[10] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_11(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[11] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_12(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[12] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_13(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[13] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_14(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[14] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_15(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[15] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_16(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[16] ), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA_18(
        \MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA[18] ), 
        .CORECONFIGP_0_APB_S_PCLK(CORECONFIGP_0_APB_S_PCLK), 
        .CORECONFIGP_0_APB_S_PRESET_N(CORECONFIGP_0_APB_S_PRESET_N), 
        .AXI_IF_0_BIF_1_RVALID(AXI_IF_0_BIF_1_RVALID), 
        .AXI_IF_0_BIF_1_RVALID_i_0(AXI_IF_0_BIF_1_RVALID_i_0), 
        .AXI_IF_0_BIF_1_RLAST(AXI_IF_0_BIF_1_RLAST), 
        .AXI_IF_0_BIF_1_RLAST_i_0(AXI_IF_0_BIF_1_RLAST_i_0), 
        .CORECONFIGP_0_APB_S_PCLK_i_0(CORECONFIGP_0_APB_S_PCLK_i_0), 
        .MMUART_0_TXD(MMUART_0_TXD), .MMUART_0_RXD(MMUART_0_RXD), 
        .MDDR_WE_N(MDDR_WE_N), .MDDR_RESET_N(MDDR_RESET_N), 
        .MDDR_RAS_N(MDDR_RAS_N), .MDDR_ODT(MDDR_ODT), 
        .MDDR_DQS_TMATCH_0_OUT(MDDR_DQS_TMATCH_0_OUT), 
        .MDDR_DQS_TMATCH_0_IN(MDDR_DQS_TMATCH_0_IN), .MDDR_CS_N(
        MDDR_CS_N), .MDDR_CKE(MDDR_CKE), .MDDR_CAS_N(MDDR_CAS_N), 
        .MDDR_TA_0_GPIO_3_M2F(MDDR_TA_0_GPIO_3_M2F), 
        .MDDR_TA_0_GPIO_4_M2F(MDDR_TA_0_GPIO_4_M2F), 
        .MDDR_TA_0_GPIO_2_M2F(MDDR_TA_0_GPIO_2_M2F), 
        .CoreAHBLite_0_AHBmslave16_HREADY(
        CoreAHBLite_0_AHBmslave16_HREADY), 
        .MDDR_TA_MSS_TMP_0_MSS_RESET_N_M2F(
        MDDR_TA_MSS_TMP_0_MSS_RESET_N_M2F), .MDDR_TA_0_GPIO_1_M2F(
        MDDR_TA_0_GPIO_1_M2F), .MDDR_TA_0_GPIO_0_M2F(
        MDDR_TA_0_GPIO_0_M2F), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSELx(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSELx), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE), 
        .MDDR_TA_0_GPIO_5_M2F(MDDR_TA_0_GPIO_5_M2F), 
        .MDDR_TA_0_GPIO_6_M2F(MDDR_TA_0_GPIO_6_M2F), 
        .MDDR_TA_0_GPIO_7_M2F(MDDR_TA_0_GPIO_7_M2F), 
        .AXI_IF_0_BIF_1_ARREADY(AXI_IF_0_BIF_1_ARREADY), 
        .AXI_IF_0_BIF_1_AWREADY(AXI_IF_0_BIF_1_AWREADY), 
        .AXI_IF_0_BIF_1_WREADY(AXI_IF_0_BIF_1_WREADY), 
        .CORECONFIGP_0_MDDR_APBmslave_PREADY(
        CORECONFIGP_0_MDDR_APBmslave_PREADY), 
        .CORECONFIGP_0_MDDR_APBmslave_PSLVERR(
        CORECONFIGP_0_MDDR_APBmslave_PSLVERR), .GL0_INST(GL0_INST), 
        .N_152_i_0(N_152_i_0), .N_153_i_0(N_153_i_0), .N_154_i_0(
        N_154_i_0), .N_155_i_0(N_155_i_0), .N_156_i_0(N_156_i_0), 
        .N_157_i_0(N_157_i_0), .N_158_i_0(N_158_i_0), .N_159_i_0(
        N_159_i_0), .N_160_i_0(N_160_i_0), .N_161_i_0(N_161_i_0), 
        .N_162_i_0(N_162_i_0), .N_163_i_0(N_163_i_0), .N_164_i_0(
        N_164_i_0), .N_165_i_0(N_165_i_0), .N_259_i_0(N_259_i_0), 
        .N_166_i_0(N_166_i_0), .N_149_i_0(N_149_i_0), .N_150_i_0(
        N_150_i_0), .CORECONFIGP_0_SOFT_M3_RESET_i_0(
        CORECONFIGP_0_SOFT_M3_RESET_i_0), .LOCK(LOCK), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PREADY(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PREADY), 
        .MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSLVERR(
        MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSLVERR), 
        .CORECONFIGP_0_SOFT_RESET_F2M_i_0(
        CORECONFIGP_0_SOFT_RESET_F2M_i_0), .AXI_IF_0_BIF_1_ARVALID(
        AXI_IF_0_BIF_1_ARVALID), .AXI_IF_0_BIF_1_AWVALID(
        AXI_IF_0_BIF_1_AWVALID), .AXI_IF_0_BIF_1_RREADY(
        AXI_IF_0_BIF_1_RREADY), .AXI_IF_0_BIF_1_WLAST(
        AXI_IF_0_BIF_1_WLAST), .AXI_IF_0_BIF_1_WVALID(
        AXI_IF_0_BIF_1_WVALID), 
        .CORERESETP_0_MDDR_DDR_AXI_S_CORE_RESET_N(
        CORERESETP_0_MDDR_DDR_AXI_S_CORE_RESET_N), 
        .CORECONFIGP_0_MDDR_APBmslave_PENABLE(
        CORECONFIGP_0_MDDR_APBmslave_PENABLE), 
        .CORECONFIGP_0_MDDR_APBmslave_PSELx(
        CORECONFIGP_0_MDDR_APBmslave_PSELx), 
        .CORECONFIGP_0_MDDR_APBmslave_PWRITE(
        CORECONFIGP_0_MDDR_APBmslave_PWRITE), .MDDR_CLK_N(MDDR_CLK_N), 
        .MDDR_CLK(MDDR_CLK));
    SYSRESET SYSRESET_POR (.POWER_ON_RESET_N(POWER_ON_RESET_N), 
        .DEVRST_N(DEVRST_N));
    
endmodule


module AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z2(
        
       AXI_IF_0_BIF_1_AWADDR,
       AXI_IF_0_AHB_DATA,
       AXI_IF_0_BIF_1_ARADDR,
       AXI_IF_0_BIF_1_WSTRB,
       AXI_IF_0_BIF_1_AWSIZE,
       AXI_IF_0_BIF_1_ARSIZE,
       AXI_IF_0_AHB_ADDR,
       CMD_Decode_0_r_xfer_size,
       CMD_Decode_0_r_xfer_size_i_0,
       CMD_Decode_0_w_xfer_size,
       AXI_IF_0_BIF_1_RDATA,
       WS_d1,
       CMD_Decode_0_w_xfer_sizeoi,
       AXI_IF_0_BIF_1_WDATA,
       CMD_Decode_0_r_xfer_sizeoi,
       AXI_IF_0_AHB_ADDR_reto_0_11,
       AXI_IF_0_AHB_ADDR_reto_0_23,
       AXI_IF_0_AHB_ADDR_reto_0_17,
       AXI_IF_0_AHB_ADDR_reto_0_24,
       AXI_IF_0_AHB_ADDR_reto_0_19,
       AXI_IF_0_AHB_ADDR_reto_0_25,
       AXI_IF_0_AHB_ADDR_reto_0_18,
       AXI_IF_0_AHB_ADDR_reto_0_0,
       AXI_IF_0_AHB_ADDR_reto_0_22,
       AXI_IF_0_AHB_ADDR_reto_0_5,
       AXI_IF_0_AHB_ADDR_reto_0_4,
       MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK,
       AXI_IF_0_BIF_1_RVALID_i_0,
       MDDR_TA_0_INIT_DONE,
       AXI_IF_0_BIF_1_RREADY,
       AXI_IF_0_BIF_1_RLAST_i_0,
       AXI_IF_0_BIF_1_WLAST,
       AXI_IF_0_WRITE_AHB,
       AHB_ADDR_6_cry_2_0_Y,
       N_178_i_0,
       MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK_i_0,
       AXI_IF_0_BIF_1_AWREADY,
       AXI_IF_0_BIF_1_WREADY,
       AXI_IF_0_BIF_1_ARVALID,
       AXI_IF_0_BIF_1_RVALID,
       AXI_IF_0_BIF_1_ARREADY,
       AXI_IF_0_BIF_1_WVALID,
       AXI_IF_0_BIF_1_AWVALID,
       AHB_IF_0_AHB_BUSY,
       AXI_IF_0_BIF_1_RLAST,
       read_start_c,
       write_start_c
    );
output [31:7] AXI_IF_0_BIF_1_AWADDR;
output [13:0] AXI_IF_0_AHB_DATA;
output [31:7] AXI_IF_0_BIF_1_ARADDR;
output [1:1] AXI_IF_0_BIF_1_WSTRB;
output [1:1] AXI_IF_0_BIF_1_AWSIZE;
output [1:1] AXI_IF_0_BIF_1_ARSIZE;
output [31:3] AXI_IF_0_AHB_ADDR;
input  [8:4] CMD_Decode_0_r_xfer_size;
input  [4:4] CMD_Decode_0_r_xfer_size_i_0;
input  [8:4] CMD_Decode_0_w_xfer_size;
input  [63:0] AXI_IF_0_BIF_1_RDATA;
input  [2:0] WS_d1;
input  [4:4] CMD_Decode_0_w_xfer_sizeoi;
output [63:0] AXI_IF_0_BIF_1_WDATA;
input  [8:4] CMD_Decode_0_r_xfer_sizeoi;
output AXI_IF_0_AHB_ADDR_reto_0_11;
output AXI_IF_0_AHB_ADDR_reto_0_23;
output AXI_IF_0_AHB_ADDR_reto_0_17;
output AXI_IF_0_AHB_ADDR_reto_0_24;
output AXI_IF_0_AHB_ADDR_reto_0_19;
output AXI_IF_0_AHB_ADDR_reto_0_25;
output AXI_IF_0_AHB_ADDR_reto_0_18;
output AXI_IF_0_AHB_ADDR_reto_0_0;
output AXI_IF_0_AHB_ADDR_reto_0_22;
output AXI_IF_0_AHB_ADDR_reto_0_5;
output AXI_IF_0_AHB_ADDR_reto_0_4;
input  MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK;
input  AXI_IF_0_BIF_1_RVALID_i_0;
input  MDDR_TA_0_INIT_DONE;
output AXI_IF_0_BIF_1_RREADY;
input  AXI_IF_0_BIF_1_RLAST_i_0;
output AXI_IF_0_BIF_1_WLAST;
output AXI_IF_0_WRITE_AHB;
output AHB_ADDR_6_cry_2_0_Y;
input  N_178_i_0;
input  MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK_i_0;
input  AXI_IF_0_BIF_1_AWREADY;
input  AXI_IF_0_BIF_1_WREADY;
output AXI_IF_0_BIF_1_ARVALID;
input  AXI_IF_0_BIF_1_RVALID;
input  AXI_IF_0_BIF_1_ARREADY;
output AXI_IF_0_BIF_1_WVALID;
output AXI_IF_0_BIF_1_AWVALID;
input  AHB_IF_0_AHB_BUSY;
input  AXI_IF_0_BIF_1_RLAST;
input  read_start_c;
input  write_start_c;

    wire \wburst_cnt[4]_net_1 , \wburst_cnt_i[4] , 
        \wburst_cnt[5]_net_1 , \wburst_cnt_i[5] , 
        \wburst_cnt[6]_net_1 , \wburst_cnt_i[6] , \rdata_cnt[0]_net_1 , 
        \rdata_cnt_s[0] , \ahb_state[0]_net_1 , \ahb_state_i_0[0] , 
        wburst_cnt, \axi_fsm_current_state_i_0[1] , 
        \axi_fsm_read_state[0]_net_1 , \axi_fsm_read_state_i_0[0] , 
        \axi_fsm_current_state[0]_net_1 , 
        \axi_fsm_current_state_i_0[0] , RVALID_li_reto, VCC_net_1, 
        GND_net_1, \w_loop[0]_net_1 , \w_loop_5[0]_net_1 , 
        \w_loop[1]_net_1 , \w_loop_5[1]_net_1 , \w_loop[2]_net_1 , 
        \w_loop_5[2]_net_1 , \w_loop[3]_net_1 , \w_loop_5[3]_net_1 , 
        \AWADDR_int[27]_net_1 , N_1249_i_0, 
        un1_WVALID_0_sqmuxa_1_0_net_1, \AWADDR_int[28]_net_1 , 
        N_1238_i_0, \AWADDR_int[29]_net_1 , N_1227_i_0, 
        \AWADDR_int[30]_net_1 , N_1216_i_0, \AWADDR_int[31]_net_1 , 
        N_1205_i_0, \AWADDR_int[12]_net_1 , N_1194_i_0, 
        \AWADDR_int[13]_net_1 , N_1183_i_0, \AWADDR_int[14]_net_1 , 
        N_1172_i_0, \AWADDR_int[15]_net_1 , N_1161_i_0, 
        \AWADDR_int[16]_net_1 , N_1150_i_0, \AWADDR_int[17]_net_1 , 
        N_1139_i_0, \AWADDR_int[18]_net_1 , N_1128_i_0, 
        \AWADDR_int[19]_net_1 , N_1117_i_0, \AWADDR_int[20]_net_1 , 
        N_1106_i_0, \AWADDR_int[21]_net_1 , N_1095_i_0, 
        \AWADDR_int[22]_net_1 , N_1084_i_0, \AWADDR_int[23]_net_1 , 
        N_1073_i_0, \AWADDR_int[24]_net_1 , N_1062_i_0, 
        \AWADDR_int[25]_net_1 , N_1051_i_0, \AWADDR_int[26]_net_1 , 
        N_1040_i_0, burst_cnt_0_sqmuxa_1, \AWADDR_int[7]_net_1 , 
        N_1029, \AWADDR_int[8]_net_1 , N_1018_i_0, 
        \AWADDR_int[9]_net_1 , N_1007_i_0, \AWADDR_int[10]_net_1 , 
        N_996_i_0, \AWADDR_int[11]_net_1 , N_985_i_0, 
        \AHB_DATA_5[0]_net_1 , N_452_i_0, \AHB_DATA_5[1]_net_1 , 
        \AHB_DATA_5[2]_net_1 , \AHB_DATA_5[3]_net_1 , 
        \AHB_DATA_5[4]_net_1 , \AHB_DATA_5[5]_net_1 , 
        \AHB_DATA_5[6]_net_1 , \AHB_DATA_5[7]_net_1 , 
        \AHB_DATA_5[8]_net_1 , \AHB_DATA_5[9]_net_1 , 
        \AHB_DATA_5[10]_net_1 , \AHB_DATA_5[11]_net_1 , 
        \AHB_DATA_5[12]_net_1 , \AHB_DATA_5[13]_net_1 , 
        \WDATA_reto[52] , \Rdata_mem_reto[52] , \WDATA_reto[53] , 
        \Rdata_mem_reto[53] , \WDATA_reto[54] , \Rdata_mem_reto[54] , 
        \WDATA_reto[55] , \Rdata_mem_reto[55] , \WDATA_reto[56] , 
        \Rdata_mem_reto[56] , \WDATA_reto[57] , \Rdata_mem_reto[57] , 
        \WDATA_reto[58] , \Rdata_mem_reto[58] , \WDATA_reto[59] , 
        \Rdata_mem_reto[59] , \WDATA_reto[60] , \Rdata_mem_reto[60] , 
        \WDATA_reto[61] , \Rdata_mem_reto[61] , \WDATA_reto[62] , 
        \Rdata_mem_reto[62] , \WDATA_reto[63] , \Rdata_mem_reto[63] , 
        \WDATA_reto[37] , \Rdata_mem_reto[37] , \WDATA_reto[38] , 
        \Rdata_mem_reto[38] , \WDATA_reto[39] , \Rdata_mem_reto[39] , 
        \WDATA_reto[40] , \Rdata_mem_reto[40] , \WDATA_reto[41] , 
        \Rdata_mem_reto[41] , \WDATA_reto[42] , \Rdata_mem_reto[42] , 
        \WDATA_reto[43] , \Rdata_mem_reto[43] , \WDATA_reto[44] , 
        \Rdata_mem_reto[44] , \WDATA_reto[45] , \Rdata_mem_reto[45] , 
        \WDATA_reto[46] , \Rdata_mem_reto[46] , \WDATA_reto[47] , 
        \Rdata_mem_reto[47] , \WDATA_reto[48] , \Rdata_mem_reto[48] , 
        \WDATA_reto[49] , \Rdata_mem_reto[49] , \WDATA_reto[50] , 
        \Rdata_mem_reto[50] , \WDATA_reto[51] , \Rdata_mem_reto[51] , 
        \WDATA_reto[22] , \Rdata_mem_reto[22] , \WDATA_reto[23] , 
        \Rdata_mem_reto[23] , \WDATA_reto[24] , \Rdata_mem_reto[24] , 
        \WDATA_reto[25] , \Rdata_mem_reto[25] , \WDATA_reto[26] , 
        \Rdata_mem_reto[26] , \WDATA_reto[27] , \Rdata_mem_reto[27] , 
        \WDATA_reto[28] , \Rdata_mem_reto[28] , \WDATA_reto[29] , 
        \Rdata_mem_reto[29] , \WDATA_reto[30] , \Rdata_mem_reto[30] , 
        \WDATA_reto[31] , \Rdata_mem_reto[31] , \WDATA_reto[32] , 
        \Rdata_mem_reto[32] , \WDATA_reto[33] , \Rdata_mem_reto[33] , 
        \WDATA_reto[34] , \Rdata_mem_reto[34] , \WDATA_reto[35] , 
        \Rdata_mem_reto[35] , \WDATA_reto[36] , \Rdata_mem_reto[36] , 
        \WDATA_reto[7] , \Rdata_mem_reto[7] , \WDATA_reto[8] , 
        \Rdata_mem_reto[8] , \WDATA_reto[9] , \Rdata_mem_reto[9] , 
        \WDATA_reto[10] , \Rdata_mem_reto[10] , \WDATA_reto[11] , 
        \Rdata_mem_reto[11] , \WDATA_reto[12] , \Rdata_mem_reto[12] , 
        \WDATA_reto[13] , \Rdata_mem_reto[13] , \WDATA_reto[14] , 
        \Rdata_mem_reto[14] , \WDATA_reto[15] , \Rdata_mem_reto[15] , 
        \WDATA_reto[16] , \Rdata_mem_reto[16] , \WDATA_reto[17] , 
        \Rdata_mem_reto[17] , \WDATA_reto[18] , \Rdata_mem_reto[18] , 
        \WDATA_reto[19] , \Rdata_mem_reto[19] , \WDATA_reto[20] , 
        \Rdata_mem_reto[20] , \WDATA_reto[21] , \Rdata_mem_reto[21] , 
        \WDATA_reto[0] , \Rdata_mem_reto[0] , \WDATA_reto[1] , 
        \Rdata_mem_reto[1] , \WDATA_reto[2] , \Rdata_mem_reto[2] , 
        \WDATA_reto[3] , \Rdata_mem_reto[3] , \WDATA_reto[4] , 
        \Rdata_mem_reto[4] , \WDATA_reto[5] , \Rdata_mem_reto[5] , 
        \WDATA_reto[6] , \Rdata_mem_reto[6] , \ARADDR_6[20] , 
        \ARADDR_6[21] , \ARADDR_6[22] , \ARADDR_6[23] , \ARADDR_6[24] , 
        \ARADDR_6[25] , \ARADDR_6[26] , \ARADDR_6[27] , \ARADDR_6[28] , 
        \ARADDR_6[29] , \ARADDR_6[30] , \ARADDR_6[31] , 
        ARADDR_6_cry_7_0_Y, \ARADDR_6[8] , \ARADDR_6[9] , 
        \ARADDR_6[10] , \ARADDR_6[11] , \ARADDR_6[12] , \ARADDR_6[13] , 
        \ARADDR_6[14] , \ARADDR_6[15] , \ARADDR_6[16] , \ARADDR_6[17] , 
        \ARADDR_6[18] , \ARADDR_6[19] , N_192, \burst_cnt[0]_net_1 , 
        \burst_cnt_0_0[0]_net_1 , \burst_cnt[1]_net_1 , N_21_i_0, 
        \burst_cnt[2]_net_1 , N_19_i_0, \burst_cnt[3]_net_1 , N_17_i_0, 
        un1_RREADY_0_sqmuxa_0_net_1, ARVALID_net_1, 
        un1_ARBURST_0_sqmuxa, un1_WVALID_0_sqmuxa_i_i_net_1, 
        AWVALID_net_1, N_24, N_458_i_0, AWBURST_0_sqmuxa, 
        ARBURST_0_sqmuxa, WVALID_net_1, 
        un1_WSTRB_0_sqmuxa_i_i_a3_net_1, \axi_fsm_current_state_ns[0] , 
        \axi_fsm_current_state_ns[1] , \axi_fsm_read1_state[0]_net_1 , 
        \axi_fsm_read1_state_ns[0] , rburst_cnt, 
        \axi_fsm_read1_state_ns[1] , \rt_state[1]_net_1 , 
        \rt_state_ns[1] , \wt_state[0]_net_1 , \wt_state_ns[0] , 
        \wt_state[1]_net_1 , \wt_state_ns[1] , r_start, N_808_i_0, 
        w_start, N_235_i_0, \rt_state[0]_net_1 , N_794_i_0, 
        \axi_fsm_read_state_ns[0] , \r_clk_cnt[0]_net_1 , 
        \r_clk_cnt_lm[0] , N_314_i_0, \r_clk_cnt[1]_net_1 , 
        \r_clk_cnt_lm[1] , \r_clk_cnt[2]_net_1 , \r_clk_cnt_lm[2] , 
        \r_clk_cnt[3]_net_1 , \r_clk_cnt_lm[3] , \r_clk_cnt[4]_net_1 , 
        \r_clk_cnt_lm[4] , \r_clk_cnt[5]_net_1 , \r_clk_cnt_lm[5] , 
        \r_clk_cnt[6]_net_1 , \r_clk_cnt_lm[6] , \r_clk_cnt[7]_net_1 , 
        \r_clk_cnt_lm[7] , \r_clk_cnt[8]_net_1 , \r_clk_cnt_lm[8] , 
        \r_clk_cnt[9]_net_1 , \r_clk_cnt_lm[9] , \r_clk_cnt[10]_net_1 , 
        \r_clk_cnt_lm[10] , \r_clk_cnt[11]_net_1 , \r_clk_cnt_lm[11] , 
        \r_clk_cnt[12]_net_1 , \r_clk_cnt_lm[12] , 
        \r_clk_cnt[13]_net_1 , \r_clk_cnt_lm[13] , 
        \WDATA_int[0]_net_1 , \WDATA_int_lm[0] , N_15_i_0, 
        \WDATA_int[1]_net_1 , \WDATA_int_lm[1] , \WDATA_int[2]_net_1 , 
        \WDATA_int_lm[2] , \WDATA_int[3]_net_1 , \WDATA_int_lm[3] , 
        \WDATA_int[4]_net_1 , \WDATA_int_lm[4] , \WDATA_int[5]_net_1 , 
        \WDATA_int_lm[5] , \WDATA_int[6]_net_1 , \WDATA_int_lm[6] , 
        \WDATA_int[7]_net_1 , \WDATA_int_lm[7] , \WDATA_int[8]_net_1 , 
        \WDATA_int_lm[8] , \w_clk_cnt[0]_net_1 , \w_clk_cnt_s[0] , 
        w_clk_cnte, \w_clk_cnt[1]_net_1 , \w_clk_cnt_s[1] , 
        \w_clk_cnt[2]_net_1 , \w_clk_cnt_s[2] , \w_clk_cnt[3]_net_1 , 
        \w_clk_cnt_s[3] , \w_clk_cnt[4]_net_1 , \w_clk_cnt_s[4] , 
        \w_clk_cnt[5]_net_1 , \w_clk_cnt_s[5] , \w_clk_cnt[6]_net_1 , 
        \w_clk_cnt_s[6] , \w_clk_cnt[7]_net_1 , \w_clk_cnt_s[7] , 
        \w_clk_cnt[8]_net_1 , \w_clk_cnt_s[8] , \w_clk_cnt[9]_net_1 , 
        \w_clk_cnt_s[9] , \w_clk_cnt[10]_net_1 , \w_clk_cnt_s[10] , 
        \w_clk_cnt[11]_net_1 , \w_clk_cnt_s[11] , 
        \w_clk_cnt[12]_net_1 , \w_clk_cnt_s[12] , 
        \w_clk_cnt[13]_net_1 , \w_clk_cnt_s[13]_net_1 , 
        \rburst_cnt[0]_net_1 , \rburst_cntoi[0] , rburst_cnte, 
        \rburst_cnt[1]_net_1 , \rburst_cntoi[1] , 
        \rburst_cnt[2]_net_1 , \rburst_cntoi[2] , 
        \rburst_cnt[3]_net_1 , \rburst_cntoi[3] , 
        \wburst_cnt[0]_net_1 , \wburst_cntoi[0] , wburst_cnte, 
        \wburst_cnt[1]_net_1 , \wburst_cntoi[1] , 
        \wburst_cnt[2]_net_1 , \wburst_cntoi[2] , 
        \wburst_cnt[3]_net_1 , \wburst_cntoi[3] , \wburst_cnt_s[4] , 
        \wburst_cnt_s[5] , \wburst_cnt_s[6] , \wburst_cnt[7]_net_1 , 
        \wburst_cnt_s[7] , \wburst_cnt[8]_net_1 , 
        \wburst_cnt_s[8]_net_1 , N_368_i_0, \rdata_cnt[1]_net_1 , 
        \rdata_cnt_s[1] , \rdata_cnt[2]_net_1 , \rdata_cnt_s[2] , 
        \rdata_cnt[3]_net_1 , \rdata_cnt_s[3] , \rdata_cnt[4]_net_1 , 
        \rdata_cnt_s[4] , \rdata_cnt[5]_net_1 , \rdata_cnt_s[5] , 
        \rdata_cnt[6]_net_1 , \rdata_cnt_s[6] , \rdata_cnt[7]_net_1 , 
        \rdata_cnt_s[7] , \rdata_cnt[8]_net_1 , \rdata_cnt_s[8]_net_1 , 
        un1_rt_1_c4_i, un1_rt_1_c4_ioi, un4_rt_1_5, un4_rt_1_5_reti, 
        un4_rt_1_6, un4_rt_1_6_reti, un4_rt_1_7, un4_rt_1_7_reti, 
        un4_rt_1_8, un4_rt_1_8_reti, N_771_reto, N_771, 
        \ahb_state_reto[0] , w_loop_0_sqmuxa_reto, 
        w_loop_0_sqmuxa_net_1, \AXI_IF_0_AHB_ADDR_reto[2] , 
        \AXI_IF_0_AHB_ADDR_reto[3] , \AXI_IF_0_AHB_ADDR_reto[4] , 
        \AXI_IF_0_AHB_ADDR_reto[5] , \AXI_IF_0_AHB_ADDR_reto[6] , 
        \AXI_IF_0_AHB_ADDR_reto[7] , \AXI_IF_0_AHB_ADDR_reto[8] , 
        \AXI_IF_0_AHB_ADDR_reto[9] , \AXI_IF_0_AHB_ADDR_reto[10] , 
        \AXI_IF_0_AHB_ADDR_reto[11] , \AXI_IF_0_AHB_ADDR_reto[12] , 
        \AXI_IF_0_AHB_ADDR_reto[13] , \AXI_IF_0_AHB_ADDR_reto[14] , 
        \AXI_IF_0_AHB_ADDR_reto[15] , \AXI_IF_0_AHB_ADDR_reto[16] , 
        \AXI_IF_0_AHB_ADDR_reto[17] , \AXI_IF_0_AHB_ADDR_reto[18] , 
        \AXI_IF_0_AHB_ADDR_reto[19] , \AXI_IF_0_AHB_ADDR_reto[20] , 
        \AXI_IF_0_AHB_ADDR_reto[21] , \AXI_IF_0_AHB_ADDR_reto[22] , 
        \AXI_IF_0_AHB_ADDR_reto[23] , \AXI_IF_0_AHB_ADDR_reto[24] , 
        \AXI_IF_0_AHB_ADDR_reto[25] , \AXI_IF_0_AHB_ADDR_reto[26] , 
        \AXI_IF_0_AHB_ADDR_reto[27] , \AXI_IF_0_AHB_ADDR_reto[28] , 
        \AXI_IF_0_AHB_ADDR_reto[29] , \AXI_IF_0_AHB_ADDR_reto[30] , 
        \AXI_IF_0_AHB_ADDR_reto[31] , un5_write_idle2_NE_2_net_1, 
        un5_write_idle2_NE_2_reti, un2_wt_1_c2_net_1, un2_wt_1_c2_reti, 
        un4_rt_1_9, un4_rt_1_9_reti, \r_loop[3]_net_1 , 
        \r_loop_5[3]_net_1 , \r_loop[2]_net_1 , \r_loop_5[2]_net_1 , 
        \r_loop[1]_net_1 , \r_loop_5[1]_net_1 , \r_loop[0]_net_1 , 
        \r_loop_5[0]_net_1 , g0_0_2, g0_0_2_reti, AWVALID_reto, 
        AXI_IF_0_BIF_1_AWREADY_reto, WVALID_reto, 
        AXI_IF_0_BIF_1_WREADY_reto, \rburst_cnt[6]_net_1 , 
        \rburst_cnt_s[6] , \rburst_cnt[8]_net_1 , 
        \rburst_cnt_s[8]_net_1 , \rburst_cnt[7]_net_1 , 
        \rburst_cnt_s[7] , \rburst_cnt[4]_net_1 , \rburst_cnt_s[4] , 
        un3_ahb1_NE_2_net_1, un3_ahb1_NE_2_reti, \rburst_cnt[5]_net_1 , 
        \rburst_cnt_s[5] , ARVALID_ext_2_net_1, un3_rt_0_cry_4_net_1, 
        un3_rt_0_cry_5_net_1, un3_rt_0_cry_6_net_1, 
        un3_rt_0_cry_7_net_1, un3_rt_0, w_clk_cnt_cry_cy, 
        \w_clk_cnt_cry_cy_Y[0] , wt_0, \w_clk_cnt_cry[0]_net_1 , 
        \w_clk_cnt_cry[1]_net_1 , \w_clk_cnt_cry[2]_net_1 , 
        \w_clk_cnt_cry[3]_net_1 , \w_clk_cnt_cry[4]_net_1 , 
        \w_clk_cnt_cry[5]_net_1 , \w_clk_cnt_cry[6]_net_1 , 
        \w_clk_cnt_cry[7]_net_1 , \w_clk_cnt_cry[8]_net_1 , 
        \w_clk_cnt_cry[9]_net_1 , \w_clk_cnt_cry[10]_net_1 , 
        \w_clk_cnt_cry[11]_net_1 , \w_clk_cnt_cry[12]_net_1 , 
        AHB_ADDR_6_cry_2, AHB_ADDR_6_cry_3_net_1, 
        AHB_ADDR_6_cry_4_net_1, AHB_ADDR_6_cry_5_net_1, 
        AHB_ADDR_6_cry_6_net_1, AHB_ADDR_6_cry_7_net_1, 
        AHB_ADDR_6_cry_8_net_1, AHB_ADDR_6_cry_9_net_1, 
        AHB_ADDR_6_cry_10_net_1, AHB_ADDR_6_cry_11_net_1, 
        AHB_ADDR_6_cry_12_net_1, AHB_ADDR_6_cry_13_net_1, 
        AHB_ADDR_6_cry_14_net_1, AHB_ADDR_6_cry_15_net_1, 
        AHB_ADDR_6_cry_16_net_1, AHB_ADDR_6_cry_17_net_1, 
        AHB_ADDR_6_cry_18_net_1, AHB_ADDR_6_cry_19_net_1, 
        AHB_ADDR_6_cry_20_net_1, AHB_ADDR_6_cry_21_net_1, 
        AHB_ADDR_6_cry_22_net_1, AHB_ADDR_6_cry_23_net_1, 
        AHB_ADDR_6_cry_24_net_1, AHB_ADDR_6_cry_25_net_1, 
        AHB_ADDR_6_cry_26_net_1, AHB_ADDR_6_cry_27_net_1, 
        AHB_ADDR_6_cry_28_net_1, AHB_ADDR_6_cry_29_net_1, 
        AHB_ADDR_6_cry_30_net_1, ARADDR_6_cry_7, 
        axi_fsm_read_state_1_sqmuxa, ARADDR_6_cry_8_net_1, 
        ARADDR_6_cry_9_net_1, ARADDR_6_cry_10_net_1, 
        ARADDR_6_cry_11_net_1, ARADDR_6_cry_12_net_1, 
        ARADDR_6_cry_13_net_1, ARADDR_6_cry_14_net_1, 
        ARADDR_6_cry_15_net_1, ARADDR_6_cry_16_net_1, 
        ARADDR_6_cry_17_net_1, ARADDR_6_cry_18_net_1, 
        ARADDR_6_cry_19_net_1, ARADDR_6_cry_20_net_1, 
        ARADDR_6_cry_21_net_1, ARADDR_6_cry_22_net_1, 
        ARADDR_6_cry_23_net_1, ARADDR_6_cry_24_net_1, 
        ARADDR_6_cry_25_net_1, ARADDR_6_cry_26_net_1, 
        ARADDR_6_cry_27_net_1, ARADDR_6_cry_28_net_1, 
        ARADDR_6_cry_29_net_1, ARADDR_6_cry_30_net_1, 
        read_read1_cry_7_net_1, read_read1_cry_8_net_1, 
        read_read1_cry_9_net_1, read_read1_cry_10_net_1, 
        read_read1_cry_11_net_1, read_read1_cry_12_net_1, 
        read_read1_cry_13_net_1, read_read1_cry_14_net_1, 
        read_read1_cry_15_net_1, read_read1_cry_16_net_1, 
        read_read1_cry_17_net_1, read_read1_cry_18_net_1, 
        read_read1_cry_19_net_1, read_read1_cry_20_net_1, 
        read_read1_cry_21_net_1, read_read1_cry_22_net_1, 
        read_read1_cry_23_net_1, read_read1_cry_24_net_1, 
        read_read1_cry_25_net_1, read_read1_cry_26_net_1, 
        read_read1_cry_27_net_1, read_read1_cry_28_net_1, 
        read_read1_cry_29_net_1, read_read1_cry_30_net_1, read_read1, 
        un4_write_idle1_cry_4_net_1, un4_write_idle1_cry_5_net_1, 
        un4_write_idle1_cry_6_net_1, un4_write_idle1_cry_7_net_1, 
        un4_write_idle1, un7_wt_1_cry_0_net_1, un7_wt_1_cry_1_net_1, 
        un7_wt_1_cry_2_net_1, un7_wt_1_cry_3_net_1, 
        un7_wt_1_cry_4_net_1, un7_wt_1_cry_5_net_1, 
        un7_wt_1_cry_6_net_1, un7_wt_1_cry_7_net_1, un7_wt_1_7_0, 
        un7_wt_1_axb_7_i_0, un7_wt_1_cry_8_net_1, un7_wt_1_8_0, 
        un7_wt_1_axb_8_i_0, un7_wt_1_cry_9_net_1, 
        un7_wt_1_cry_10_net_1, un4_rt_1_cry_0_net_1, 
        un4_rt_1_cry_1_net_1, un4_rt_1_cry_2_net_1, 
        un4_rt_1_cry_3_net_1, un4_rt_1_cry_4_net_1, 
        un4_rt_1_cry_5_net_1, un4_rt_1_cry_6_net_1, 
        un4_rt_1_cry_7_net_1, un4_rt_1_cry_8_net_1, 
        un4_rt_1_cry_9_net_1, un4_rt_1_cry_10_net_1, 
        rdata_cnt_s_551_FCO, \rdata_cnt_cry[1]_net_1 , 
        \rdata_cnt_cry[2]_net_1 , \rdata_cnt_cry[3]_net_1 , 
        \rdata_cnt_cry[4]_net_1 , \rdata_cnt_cry[5]_net_1 , 
        \rdata_cnt_cry[6]_net_1 , \rdata_cnt_cry[7]_net_1 , 
        wburst_cnt_s_552_FCO, \wburst_cnt_cry[0]_net_1 , 
        \wburst_cnt_cry[1]_net_1 , \wburst_cnt_cry[2]_net_1 , 
        \wburst_cnt_cry[3]_net_1 , \wburst_cnt_cry[4]_net_1 , 
        \wburst_cnt_cry[5]_net_1 , \wburst_cnt_cry[6]_net_1 , 
        \wburst_cnt_cry[7]_net_1 , rburst_cnt_s_553_FCO, 
        \rburst_cnt_cry[0]_net_1 , \rburst_cnt_cry[1]_net_1 , 
        \rburst_cnt_cry[2]_net_1 , \rburst_cnt_cry[3]_net_1 , 
        \rburst_cnt_cry[4]_net_1 , \rburst_cnt_cry[5]_net_1 , 
        \rburst_cnt_cry[6]_net_1 , \rburst_cnt_cry[7]_net_1 , 
        WDATA_int_s_554_FCO, \WDATA_int_cry[1]_net_1 , 
        \WDATA_int_s[1] , \WDATA_int_cry[2]_net_1 , \WDATA_int_s[2] , 
        \WDATA_int_cry[3]_net_1 , \WDATA_int_s[3] , 
        \WDATA_int_cry[4]_net_1 , \WDATA_int_s[4] , 
        \WDATA_int_cry[5]_net_1 , \WDATA_int_s[5] , 
        \WDATA_int_cry[6]_net_1 , \WDATA_int_s[6] , 
        \WDATA_int_s[8]_net_1 , \WDATA_int_cry[7]_net_1 , 
        \WDATA_int_s[7] , r_clk_cnt_s_555_FCO, 
        \r_clk_cnt_cry[1]_net_1 , \r_clk_cnt_s[1] , 
        \r_clk_cnt_cry[2]_net_1 , \r_clk_cnt_s[2] , 
        \r_clk_cnt_cry[3]_net_1 , \r_clk_cnt_s[3] , 
        \r_clk_cnt_cry[4]_net_1 , \r_clk_cnt_s[4] , 
        \r_clk_cnt_cry[5]_net_1 , \r_clk_cnt_s[5] , 
        \r_clk_cnt_cry[6]_net_1 , \r_clk_cnt_s[6] , 
        \r_clk_cnt_cry[7]_net_1 , \r_clk_cnt_s[7] , 
        \r_clk_cnt_cry[8]_net_1 , \r_clk_cnt_s[8] , 
        \r_clk_cnt_cry[9]_net_1 , \r_clk_cnt_s[9] , 
        \r_clk_cnt_cry[10]_net_1 , \r_clk_cnt_s[10] , 
        \r_clk_cnt_cry[11]_net_1 , \r_clk_cnt_s[11] , 
        \r_clk_cnt_s[13]_net_1 , \r_clk_cnt_cry[12]_net_1 , 
        \r_clk_cnt_s[12] , un8_AWADDR_int_1_s_1_556_FCO, 
        un8_AWADDR_int_1_cry_1_net_1, un8_AWADDR_int_1_cry_1_S, 
        un8_AWADDR_int_1_cry_2_net_1, un8_AWADDR_int_1_cry_2_S, 
        un8_AWADDR_int_1_cry_3_net_1, un8_AWADDR_int_1_cry_3_S, 
        un8_AWADDR_int_1_cry_4_net_1, un8_AWADDR_int_1_cry_4_S, 
        un8_AWADDR_int_1_cry_5_net_1, un8_AWADDR_int_1_cry_5_S, 
        un8_AWADDR_int_1_cry_6_net_1, un8_AWADDR_int_1_cry_6_S, 
        un8_AWADDR_int_1_cry_7_net_1, un8_AWADDR_int_1_cry_7_S, 
        un8_AWADDR_int_1_cry_8_net_1, un8_AWADDR_int_1_cry_8_S, 
        un8_AWADDR_int_1_cry_9_net_1, un8_AWADDR_int_1_cry_9_S, 
        un8_AWADDR_int_1_cry_10_net_1, un8_AWADDR_int_1_cry_10_S, 
        un8_AWADDR_int_1_cry_11_net_1, un8_AWADDR_int_1_cry_11_S, 
        un8_AWADDR_int_1_cry_12_net_1, un8_AWADDR_int_1_cry_12_S, 
        un8_AWADDR_int_1_cry_13_net_1, un8_AWADDR_int_1_cry_13_S, 
        un8_AWADDR_int_1_cry_14_net_1, un8_AWADDR_int_1_cry_14_S, 
        un8_AWADDR_int_1_cry_15_net_1, un8_AWADDR_int_1_cry_15_S, 
        un8_AWADDR_int_1_cry_16_net_1, un8_AWADDR_int_1_cry_16_S, 
        un8_AWADDR_int_1_cry_17_net_1, un8_AWADDR_int_1_cry_17_S, 
        un8_AWADDR_int_1_cry_18_net_1, un8_AWADDR_int_1_cry_18_S, 
        un8_AWADDR_int_1_cry_19_net_1, un8_AWADDR_int_1_cry_19_S, 
        un8_AWADDR_int_1_cry_20_net_1, un8_AWADDR_int_1_cry_20_S, 
        un8_AWADDR_int_1_cry_21_net_1, un8_AWADDR_int_1_cry_21_S, 
        un8_AWADDR_int_1_cry_22_net_1, un8_AWADDR_int_1_cry_22_S, 
        un8_AWADDR_int_1_s_24_S, un8_AWADDR_int_1_cry_23_net_1, 
        un8_AWADDR_int_1_cry_23_S, axi_fsm_read1_state_1_sqmuxa, 
        g0_1_0, g0_1_1, g0_1_2, un3_ahb1_NE, N_222, ahb0_0_net_1, 
        wt_state13_net_1, rt_state13_net_1, read1_idle_net_1, N_38, 
        WDATA_intlde_i_o2_2, un5_write_idle2_NE_4_net_1, 
        un5_write_idle2_NE_3_net_1, w_clk_cnt_1_sqmuxa_1_5_net_1, 
        w_clk_cnt_1_sqmuxa_1_4_net_1, un5_ahb2_net_1, un3_ahb2_net_1, 
        N_254, rt_0_net_1, N_31, un7_wt_1_8, un7_wt_1_7, 
        un1_wt_state_0_sqmuxa_i_0_net_1, WDATA_intlde_i_0, 
        un5_write_idle2_NE_5_net_1, w_clk_cnt_1_sqmuxa_1_8_net_1, 
        N_231, N_241, w_clk_cnt_1_sqmuxa_1_net_1, un1_rt_1_c5_net_1, 
        N_34, N_236, ahb0_net_1, un1_ARBURST_0_sqmuxa_0_a3_0_0, 
        r_loop_1_sqmuxa_0_a2_0_net_1, N_244, un2_wt_1_c5_net_1, N_825, 
        CO1, N_831, CO1_0;
    
    SLE \WDATA_ret[21]  (.D(\Rdata_mem_reto[21] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[21] ));
    SLE HADDR_ret_6 (.D(AXI_IF_0_AHB_ADDR[20]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_AHB_ADDR_reto_0_18));
    SLE \AHB_DATA_1[1]  (.D(\AHB_DATA_5[1]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_452_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_AHB_DATA[1]));
    CFG4 #( .INIT(16'h04AE) )  \wt_state_ns_0[1]  (.A(
        \wt_state[0]_net_1 ), .B(\wt_state[1]_net_1 ), .C(
        wt_state13_net_1), .D(un7_wt_1_cry_10_net_1), .Y(
        \wt_state_ns[1] ));
    SLE \WDATA_ret[40]  (.D(\Rdata_mem_reto[40] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[40] ));
    SLE \rburst_cnt[3]  (.D(\rburst_cntoi[3] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(rburst_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rburst_cnt[3]_net_1 ));
    SLE AHB_ADDR_ret_21 (.D(AXI_IF_0_AHB_ADDR[20]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[20] ));
    SLE AWVALID_ext_ret (.D(AWVALID_net_1), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK_i_0), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AWVALID_reto));
    ARI1 #( .INIT(20'h5AA55) )  read_read1_cry_19 (.A(un4_rt_1_9), .B(
        AXI_IF_0_BIF_1_ARADDR[19]), .C(GND_net_1), .D(GND_net_1), .FCI(
        read_read1_cry_18_net_1), .S(), .Y(), .FCO(
        read_read1_cry_19_net_1));
    CFG4 #( .INIT(16'hFE01) )  un2_wt_1_axbxc4 (.A(
        CMD_Decode_0_w_xfer_size[7]), .B(CMD_Decode_0_w_xfer_size[6]), 
        .C(un2_wt_1_c2_net_1), .D(CMD_Decode_0_w_xfer_size[8]), .Y(
        un7_wt_1_8));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNIMQQD[6]  (.A(
        \Rdata_mem_reto[6] ), .B(\WDATA_reto[6] ), .C(RVALID_li_reto), 
        .Y(AXI_IF_0_BIF_1_WDATA[6]));
    CFG4 #( .INIT(16'h9180) )  \axi_fsm_current_state_RNIFBOP1[0]  (.A(
        wburst_cnt), .B(\axi_fsm_current_state[0]_net_1 ), .C(
        AXI_IF_0_BIF_1_WREADY), .D(N_38), .Y(wburst_cnte));
    SLE \rburst_cnt[7]  (.D(\rburst_cnt_s[7] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(rburst_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rburst_cnt[7]_net_1 ));
    CFG4 #( .INIT(16'hDFFF) )  \burst_cnt_0_i_o2_1[2]  (.A(wburst_cnt), 
        .B(\axi_fsm_current_state[0]_net_1 ), .C(AXI_IF_0_BIF_1_WREADY)
        , .D(MDDR_TA_0_INIT_DONE), .Y(N_231));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNIJNQD[3]  (.A(
        \Rdata_mem_reto[3] ), .B(\WDATA_reto[3] ), .C(RVALID_li_reto), 
        .Y(AXI_IF_0_BIF_1_WDATA[3]));
    SLE \ARADDR[31]  (.D(\ARADDR_6[31] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARADDR[31]));
    CFG2 #( .INIT(4'h8) )  \AWADDR_int_RNO[19]  (.A(
        un8_AWADDR_int_1_cry_12_S), .B(wburst_cnt), .Y(N_1117_i_0));
    ARI1 #( .INIT(20'h6AA00) )  read_read1_cry_9 (.A(VCC_net_1), .B(
        AXI_IF_0_BIF_1_ARADDR[9]), .C(GND_net_1), .D(GND_net_1), .FCI(
        read_read1_cry_8_net_1), .S(), .Y(), .FCO(
        read_read1_cry_9_net_1));
    ARI1 #( .INIT(20'h5AA55) )  read_read1_cry_16 (.A(un4_rt_1_6), .B(
        AXI_IF_0_BIF_1_ARADDR[16]), .C(GND_net_1), .D(GND_net_1), .FCI(
        read_read1_cry_15_net_1), .S(), .Y(), .FCO(
        read_read1_cry_16_net_1));
    SLE \r_clk_cnt[11]  (.D(\r_clk_cnt_lm[11] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_314_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\r_clk_cnt[11]_net_1 ));
    ARI1 #( .INIT(20'h45500) )  read_read1_cry_22 (.A(VCC_net_1), .B(
        AXI_IF_0_BIF_1_ARADDR[22]), .C(GND_net_1), .D(GND_net_1), .FCI(
        read_read1_cry_21_net_1), .S(), .Y(), .FCO(
        read_read1_cry_22_net_1));
    CFG4 #( .INIT(16'hFFDC) )  \axi_fsm_current_state_ns_1_0_.m6_0  (
        .A(N_31), .B(N_241), .C(N_254), .D(AWBURST_0_sqmuxa), .Y(
        \axi_fsm_current_state_ns[0] ));
    ARI1 #( .INIT(20'h48800) )  AHB_ADDR_6_cry_4 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[4] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_3_net_1), .S(
        AXI_IF_0_AHB_ADDR[4]), .Y(), .FCO(AHB_ADDR_6_cry_4_net_1));
    ARI1 #( .INIT(20'h4AA00) )  \r_clk_cnt_cry[12]  (.A(VCC_net_1), .B(
        \r_clk_cnt[12]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \r_clk_cnt_cry[11]_net_1 ), .S(\r_clk_cnt_s[12] ), .Y(), .FCO(
        \r_clk_cnt_cry[12]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI51IC[40]  (.A(
        \Rdata_mem_reto[40] ), .B(\WDATA_reto[40] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[40]));
    SLE \WDATA_ret[53]  (.D(\Rdata_mem_reto[53] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[53] ));
    CFG4 #( .INIT(16'h2130) )  \burst_cnt_RNO[1]  (.A(N_231), .B(
        burst_cnt_0_sqmuxa_1), .C(\burst_cnt[1]_net_1 ), .D(
        \burst_cnt[0]_net_1 ), .Y(N_21_i_0));
    SLE AWVALID_ext_ret_1 (.D(AXI_IF_0_BIF_1_AWREADY), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK_i_0), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWREADY_reto));
    SLE \WDATA_ret[47]  (.D(\Rdata_mem_reto[47] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[47] ));
    SLE \r_clk_cnt[1]  (.D(\r_clk_cnt_lm[1] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_314_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\r_clk_cnt[1]_net_1 ));
    SLE AHB_ADDR_ret_1 (.D(\ahb_state[0]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ahb_state_reto[0] ));
    ARI1 #( .INIT(20'h48800) )  \rburst_cnt_cry[5]  (.A(VCC_net_1), .B(
        rburst_cnt), .C(\rburst_cnt[5]_net_1 ), .D(GND_net_1), .FCI(
        \rburst_cnt_cry[4]_net_1 ), .S(\rburst_cnt_s[5] ), .Y(), .FCO(
        \rburst_cnt_cry[5]_net_1 ));
    CFG4 #( .INIT(16'hA028) )  \w_loop_5[0]  (.A(w_loop_0_sqmuxa_net_1)
        , .B(ahb0_net_1), .C(\w_loop[0]_net_1 ), .D(
        \ahb_state[0]_net_1 ), .Y(\w_loop_5[0]_net_1 ));
    SLE AHB_ADDR_ret_22 (.D(AXI_IF_0_AHB_ADDR[21]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[21] ));
    CFG4 #( .INIT(16'hFE00) )  \r_clk_cnt_lm_0[2]  (.A(
        \rt_state[0]_net_1 ), .B(\rt_state[1]_net_1 ), .C(rt_0_net_1), 
        .D(\r_clk_cnt_s[2] ), .Y(\r_clk_cnt_lm[2] ));
    SLE \ahb_state[0]  (.D(N_452_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\ahb_state[0]_net_1 ));
    SLE \WDATA_ret[31]  (.D(\Rdata_mem_reto[31] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[31] ));
    SLE \WDATA_int[3]  (.D(\WDATA_int_lm[3] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_15_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[3]_net_1 ));
    CFG4 #( .INIT(16'hF0E1) )  un2_wt_1_axbxc3 (.A(
        CMD_Decode_0_w_xfer_size[5]), .B(CMD_Decode_0_w_xfer_size[4]), 
        .C(CMD_Decode_0_w_xfer_size[7]), .D(
        CMD_Decode_0_w_xfer_size[6]), .Y(un7_wt_1_7));
    ARI1 #( .INIT(20'h4DD00) )  AHB_ADDR_6_cry_29 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[29] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_28_net_1), .S(
        AXI_IF_0_AHB_ADDR[29]), .Y(), .FCO(AHB_ADDR_6_cry_29_net_1));
    ARI1 #( .INIT(20'h5AA55) )  un4_write_idle1_cry_4 (.A(
        CMD_Decode_0_w_xfer_size[4]), .B(\wburst_cnt[4]_net_1 ), .C(
        GND_net_1), .D(GND_net_1), .FCI(GND_net_1), .S(), .Y(), .FCO(
        un4_write_idle1_cry_4_net_1));
    CFG2 #( .INIT(4'h8) )  wt_state13 (.A(AXI_IF_0_BIF_1_WREADY), .B(
        AXI_IF_0_BIF_1_WLAST), .Y(wt_state13_net_1));
    SLE w_xfer_size_1_ret (.D(un2_wt_1_c2_reti), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(un2_wt_1_c2_net_1));
    SLE \r_clk_cnt[0]  (.D(\r_clk_cnt_lm[0] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_314_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\r_clk_cnt[0]_net_1 ));
    SLE \WDATA_ret[44]  (.D(\Rdata_mem_reto[44] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[44] ));
    SLE \r_loop[1]  (.D(\r_loop_5[1]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\r_loop[1]_net_1 ));
    SLE \r_clk_cnt[8]  (.D(\r_clk_cnt_lm[8] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_314_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\r_clk_cnt[8]_net_1 ));
    SLE \rdata_cnt[7]  (.D(\rdata_cnt_s[7] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_368_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rdata_cnt[7]_net_1 ));
    SLE \WDATA_ret[7]  (.D(\Rdata_mem_reto[7] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[7] ));
    CFG4 #( .INIT(16'hA080) )  un1_WVALID_0_sqmuxa_i_i (.A(wburst_cnt), 
        .B(\axi_fsm_current_state[0]_net_1 ), .C(AXI_IF_0_BIF_1_WREADY)
        , .D(N_254), .Y(un1_WVALID_0_sqmuxa_i_i_net_1));
    SLE \WDATA_ret[1]  (.D(\Rdata_mem_reto[1] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[1] ));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI73IC[42]  (.A(
        \Rdata_mem_reto[42] ), .B(\WDATA_reto[42] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[42]));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI5VEC[14]  (.A(
        \Rdata_mem_reto[14] ), .B(\WDATA_reto[14] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[14]));
    SLE \AWADDR_1[30]  (.D(\AWADDR_int[30]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(burst_cnt_0_sqmuxa_1)
        , .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWADDR[30]));
    ARI1 #( .INIT(20'h4AA00) )  un8_AWADDR_int_1_cry_10 (.A(VCC_net_1), 
        .B(\AWADDR_int[17]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un8_AWADDR_int_1_cry_9_net_1), .S(un8_AWADDR_int_1_cry_10_S), 
        .Y(), .FCO(un8_AWADDR_int_1_cry_10_net_1));
    CFG4 #( .INIT(16'h0EAE) )  \axi_fsm_read1_state_ns_0[1]  (.A(
        rburst_cnt), .B(\axi_fsm_read1_state[0]_net_1 ), .C(
        AXI_IF_0_BIF_1_RLAST), .D(AXI_IF_0_BIF_1_RVALID), .Y(
        \axi_fsm_read1_state_ns[1] ));
    SLE AHB_ADDR_ret_13 (.D(AXI_IF_0_AHB_ADDR[12]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[12] ));
    SLE \w_clk_cnt[8]  (.D(\w_clk_cnt_s[8] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(w_clk_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\w_clk_cnt[8]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  AHB_ADDR_6_cry_5 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[5] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_4_net_1), .S(
        AXI_IF_0_AHB_ADDR[5]), .Y(), .FCO(AHB_ADDR_6_cry_5_net_1));
    ARI1 #( .INIT(20'h4AA00) )  rdata_cnt_s_551 (.A(VCC_net_1), .B(
        \rdata_cnt[0]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        VCC_net_1), .S(), .Y(), .FCO(rdata_cnt_s_551_FCO));
    ARI1 #( .INIT(20'h4AA00) )  \rdata_cnt_cry[7]  (.A(VCC_net_1), .B(
        \rdata_cnt[7]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \rdata_cnt_cry[6]_net_1 ), .S(\rdata_cnt_s[7] ), .Y(), .FCO(
        \rdata_cnt_cry[7]_net_1 ));
    SLE \AWADDR_1[21]  (.D(\AWADDR_int[21]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(burst_cnt_0_sqmuxa_1)
        , .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWADDR[21]));
    CFG4 #( .INIT(16'h4000) )  \un1_r_loop_1.CO1  (.A(ahb0_net_1), .B(
        r_loop_1_sqmuxa_0_a2_0_net_1), .C(\r_loop[1]_net_1 ), .D(
        \r_loop[0]_net_1 ), .Y(CO1_0));
    SLE \AWADDR_1[9]  (.D(\AWADDR_int[9]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(burst_cnt_0_sqmuxa_1)
        , .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWADDR[9]));
    CFG1 #( .INIT(2'h1) )  WVALID_RNO (.A(wburst_cnt), .Y(
        \axi_fsm_current_state_i_0[1] ));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNIA5HC[36]  (.A(
        \Rdata_mem_reto[36] ), .B(\WDATA_reto[36] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[36]));
    SLE \r_clk_cnt[6]  (.D(\r_clk_cnt_lm[6] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_314_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\r_clk_cnt[6]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI4VFC[22]  (.A(
        \Rdata_mem_reto[22] ), .B(\WDATA_reto[22] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[22]));
    CFG4 #( .INIT(16'hFFFE) )  un2_wt_1_c5 (.A(
        CMD_Decode_0_w_xfer_size[7]), .B(CMD_Decode_0_w_xfer_size[6]), 
        .C(un2_wt_1_c2_net_1), .D(CMD_Decode_0_w_xfer_size[8]), .Y(
        un2_wt_1_c5_net_1));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNIC9JC[56]  (.A(
        \Rdata_mem_reto[56] ), .B(\WDATA_reto[56] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[56]));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI61GC[24]  (.A(
        \Rdata_mem_reto[24] ), .B(\WDATA_reto[24] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[24]));
    SLE \ARADDR[16]  (.D(\ARADDR_6[16] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARADDR[16]));
    ARI1 #( .INIT(20'h48800) )  ARADDR_6_cry_21 (.A(VCC_net_1), .B(
        \axi_fsm_read_state_ns[0] ), .C(AXI_IF_0_BIF_1_ARADDR[21]), .D(
        GND_net_1), .FCI(ARADDR_6_cry_20_net_1), .S(\ARADDR_6[21] ), 
        .Y(), .FCO(ARADDR_6_cry_21_net_1));
    SLE \WDATA_ret[13]  (.D(\Rdata_mem_reto[13] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[13] ));
    SLE \wburst_cnt[0]  (.D(\wburst_cntoi[0] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(wburst_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\wburst_cnt[0]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI93FC[18]  (.A(
        \Rdata_mem_reto[18] ), .B(\WDATA_reto[18] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[18]));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNIA4FC[19]  (.A(
        \Rdata_mem_reto[19] ), .B(\WDATA_reto[19] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[19]));
    ARI1 #( .INIT(20'h48800) )  ARADDR_6_cry_19 (.A(VCC_net_1), .B(
        \axi_fsm_read_state_ns[0] ), .C(AXI_IF_0_BIF_1_ARADDR[19]), .D(
        GND_net_1), .FCI(ARADDR_6_cry_18_net_1), .S(\ARADDR_6[19] ), 
        .Y(), .FCO(ARADDR_6_cry_19_net_1));
    ARI1 #( .INIT(20'h48800) )  \w_clk_cnt_cry[6]  (.A(VCC_net_1), .B(
        \w_clk_cnt_cry_cy_Y[0] ), .C(\w_clk_cnt[6]_net_1 ), .D(
        GND_net_1), .FCI(\w_clk_cnt_cry[5]_net_1 ), .S(
        \w_clk_cnt_s[6] ), .Y(), .FCO(\w_clk_cnt_cry[6]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \AWADDR_int_RNO[18]  (.A(
        un8_AWADDR_int_1_cry_11_S), .B(wburst_cnt), .Y(N_1128_i_0));
    CFG2 #( .INIT(4'h9) )  un7_wt_1_axb_7_i (.A(un7_wt_1_7), .B(
        \wburst_cnt[7]_net_1 ), .Y(un7_wt_1_axb_7_i_0));
    SLE \AWADDR_1[12]  (.D(\AWADDR_int[12]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(burst_cnt_0_sqmuxa_1)
        , .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWADDR[12]));
    CFG3 #( .INIT(8'hAC) )  \AHB_DATA_5[2]  (.A(\w_clk_cnt[2]_net_1 ), 
        .B(\r_clk_cnt[2]_net_1 ), .C(ahb0_net_1), .Y(
        \AHB_DATA_5[2]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un8_AWADDR_int_1_cry_16 (.A(VCC_net_1), 
        .B(\AWADDR_int[23]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un8_AWADDR_int_1_cry_15_net_1), .S(un8_AWADDR_int_1_cry_16_S), 
        .Y(), .FCO(un8_AWADDR_int_1_cry_16_net_1));
    SLE \AHB_DATA_1[10]  (.D(\AHB_DATA_5[10]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_452_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_AHB_DATA[10]));
    CFG4 #( .INIT(16'h28A0) )  \w_loop_5[3]  (.A(w_loop_0_sqmuxa_net_1)
        , .B(CO1), .C(\w_loop[3]_net_1 ), .D(\w_loop[2]_net_1 ), .Y(
        \w_loop_5[3]_net_1 ));
    SLE AHB_ADDR_ret_11 (.D(AXI_IF_0_AHB_ADDR[10]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[10] ));
    CFG4 #( .INIT(16'hAAA8) )  \WDATA_int_lm_0[1]  (.A(
        \WDATA_int_s[1] ), .B(N_236), .C(
        \axi_fsm_current_state[0]_net_1 ), .D(wburst_cnt), .Y(
        \WDATA_int_lm[1] ));
    SLE AHB_ADDR_ret_24 (.D(AXI_IF_0_AHB_ADDR[23]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[23] ));
    SLE \WDATA_int[6]  (.D(\WDATA_int_lm[6] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_15_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[6]_net_1 ));
    SLE \AWADDR_1[24]  (.D(\AWADDR_int[24]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(burst_cnt_0_sqmuxa_1)
        , .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWADDR[24]));
    CFG4 #( .INIT(16'h0105) )  axi_fsm_read1_state_1_sqmuxa_0_a3 (.A(
        \axi_fsm_read1_state[0]_net_1 ), .B(r_start), .C(rburst_cnt), 
        .D(un3_rt_0), .Y(axi_fsm_read1_state_1_sqmuxa));
    CFG3 #( .INIT(8'hAC) )  \AHB_DATA_5[12]  (.A(\w_clk_cnt[12]_net_1 )
        , .B(\r_clk_cnt[12]_net_1 ), .C(ahb0_net_1), .Y(
        \AHB_DATA_5[12]_net_1 ));
    SLE \AWADDR_1[27]  (.D(\AWADDR_int[27]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(burst_cnt_0_sqmuxa_1)
        , .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWADDR[27]));
    SLE \ARADDR[28]  (.D(\ARADDR_6[28] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARADDR[28]));
    SLE \WDATA_ret[46]  (.D(\Rdata_mem_reto[46] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[46] ));
    ARI1 #( .INIT(20'h4AA00) )  \WDATA_int_cry[3]  (.A(VCC_net_1), .B(
        \WDATA_int[3]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \WDATA_int_cry[2]_net_1 ), .S(\WDATA_int_s[3] ), .Y(), .FCO(
        \WDATA_int_cry[3]_net_1 ));
    SLE \AWADDR_int[26]  (.D(N_1040_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WVALID_0_sqmuxa_1_0_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\AWADDR_int[26]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \r_clk_cnt_cry[9]  (.A(VCC_net_1), .B(
        \r_clk_cnt[9]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \r_clk_cnt_cry[8]_net_1 ), .S(\r_clk_cnt_s[9] ), .Y(), .FCO(
        \r_clk_cnt_cry[9]_net_1 ));
    CFG4 #( .INIT(16'hDFCC) )  \axi_fsm_current_state_ns_1_0_.m8_0  (
        .A(AXI_IF_0_BIF_1_WREADY), .B(N_192), .C(
        \axi_fsm_current_state[0]_net_1 ), .D(wburst_cnt), .Y(
        \axi_fsm_current_state_ns[1] ));
    SLE \r_clk_cnt[2]  (.D(\r_clk_cnt_lm[2] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_314_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\r_clk_cnt[2]_net_1 ));
    SLE \AHB_DATA_1[8]  (.D(\AHB_DATA_5[8]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_452_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_AHB_DATA[8]));
    SLE AHB_ADDR_ret_4 (.D(AXI_IF_0_AHB_ADDR[3]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[3] ));
    ARI1 #( .INIT(20'h54488) )  ARADDR_6_cry_7_0 (.A(
        AXI_IF_0_BIF_1_ARADDR[7]), .B(axi_fsm_read_state_1_sqmuxa), .C(
        \axi_fsm_read_state_ns[0] ), .D(GND_net_1), .FCI(GND_net_1), 
        .S(), .Y(ARADDR_6_cry_7_0_Y), .FCO(ARADDR_6_cry_7));
    SLE AHB_ADDR_ret_12 (.D(AXI_IF_0_AHB_ADDR[11]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[11] ));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI62IC[41]  (.A(
        \Rdata_mem_reto[41] ), .B(\WDATA_reto[41] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[41]));
    SLE \AWADDR_int[11]  (.D(N_985_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WVALID_0_sqmuxa_1_0_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\AWADDR_int[11]_net_1 ));
    SLE \w_loop[2]  (.D(\w_loop_5[2]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\w_loop[2]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI82FC[17]  (.A(
        \Rdata_mem_reto[17] ), .B(\WDATA_reto[17] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[17]));
    CFG3 #( .INIT(8'hAC) )  \AHB_DATA_5[3]  (.A(\w_clk_cnt[3]_net_1 ), 
        .B(\r_clk_cnt[3]_net_1 ), .C(ahb0_net_1), .Y(
        \AHB_DATA_5[3]_net_1 ));
    SLE \ARSIZE_1[0]  (.D(VCC_net_1), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(ARBURST_0_sqmuxa), 
        .ALn(MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARSIZE[1]));
    CFG4 #( .INIT(16'hAAA8) )  \WDATA_int_lm_0[7]  (.A(
        \WDATA_int_s[7] ), .B(N_236), .C(
        \axi_fsm_current_state[0]_net_1 ), .D(wburst_cnt), .Y(
        \WDATA_int_lm[7] ));
    CFG2 #( .INIT(4'h8) )  \AWADDR_int_RNO[29]  (.A(
        un8_AWADDR_int_1_cry_22_S), .B(wburst_cnt), .Y(N_1227_i_0));
    SLE \AWADDR_int[29]  (.D(N_1227_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WVALID_0_sqmuxa_1_0_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\AWADDR_int[29]_net_1 ));
    CFG2 #( .INIT(4'h8) )  AWVALID_RNIQKEH (.A(w_start), .B(
        AWVALID_net_1), .Y(wt_0));
    GND GND (.Y(GND_net_1));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI86KC[61]  (.A(
        \Rdata_mem_reto[61] ), .B(\WDATA_reto[61] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[61]));
    SLE ARVALID_ext (.D(ARVALID_ext_2_net_1), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK_i_0), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARVALID));
    ARI1 #( .INIT(20'h48800) )  \wburst_cnt_cry[3]  (.A(VCC_net_1), .B(
        wburst_cnt), .C(\wburst_cnt[3]_net_1 ), .D(GND_net_1), .FCI(
        \wburst_cnt_cry[2]_net_1 ), .S(\wburst_cntoi[3] ), .Y(), .FCO(
        \wburst_cnt_cry[3]_net_1 ));
    SLE \rburst_cnt[2]  (.D(\rburst_cntoi[2] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(rburst_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rburst_cnt[2]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI50GC[23]  (.A(
        \Rdata_mem_reto[23] ), .B(\WDATA_reto[23] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[23]));
    SLE \AWADDR_int[15]  (.D(N_1161_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WVALID_0_sqmuxa_1_0_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\AWADDR_int[15]_net_1 ));
    SLE \r_clk_cnt[12]  (.D(\r_clk_cnt_lm[12] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_314_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\r_clk_cnt[12]_net_1 ));
    SLE \rdata_cnt[8]  (.D(\rdata_cnt_s[8]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_368_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rdata_cnt[8]_net_1 ));
    CFG2 #( .INIT(4'h6) )  un1_rt_1_axbxc4 (.A(un1_rt_1_c4_ioi), .B(
        CMD_Decode_0_r_xfer_sizeoi[8]), .Y(un4_rt_1_8_reti));
    SLE \ARADDR[29]  (.D(\ARADDR_6[29] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARADDR[29]));
    SLE \AHB_DATA_1[4]  (.D(\AHB_DATA_5[4]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_452_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_AHB_DATA[4]));
    ARI1 #( .INIT(20'h48800) )  AHB_ADDR_6_cry_20 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[20] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_19_net_1), .S(
        AXI_IF_0_AHB_ADDR[20]), .Y(), .FCO(AHB_ADDR_6_cry_20_net_1));
    CFG2 #( .INIT(4'h8) )  WVALID_ext_2 (.A(WVALID_reto), .B(
        AXI_IF_0_BIF_1_WREADY_reto), .Y(AXI_IF_0_BIF_1_WVALID));
    SLE AHB_ADDR_ret_3 (.D(AHB_ADDR_6_cry_2_0_Y), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[2] ));
    SLE \WDATA_ret[28]  (.D(\Rdata_mem_reto[28] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[28] ));
    SLE \AWADDR_int[10]  (.D(N_996_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WVALID_0_sqmuxa_1_0_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\AWADDR_int[10]_net_1 ));
    ARI1 #( .INIT(20'h5AA55) )  un4_write_idle1_cry_7 (.A(
        CMD_Decode_0_w_xfer_size[7]), .B(\wburst_cnt[7]_net_1 ), .C(
        GND_net_1), .D(GND_net_1), .FCI(un4_write_idle1_cry_6_net_1), 
        .S(), .Y(), .FCO(un4_write_idle1_cry_7_net_1));
    ARI1 #( .INIT(20'h45500) )  read_read1_cry_25 (.A(VCC_net_1), .B(
        AXI_IF_0_BIF_1_ARADDR[25]), .C(GND_net_1), .D(GND_net_1), .FCI(
        read_read1_cry_24_net_1), .S(), .Y(), .FCO(
        read_read1_cry_25_net_1));
    SLE \w_clk_cnt[13]  (.D(\w_clk_cnt_s[13]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(w_clk_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\w_clk_cnt[13]_net_1 ));
    SLE AHB_ADDR_ret_5 (.D(AXI_IF_0_AHB_ADDR[4]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[4] ));
    SLE HADDR_ret (.D(AXI_IF_0_AHB_ADDR[13]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_AHB_ADDR_reto_0_11));
    CFG4 #( .INIT(16'h0001) )  w_clk_cnt_1_sqmuxa_1_5 (.A(
        \wburst_cnt[1]_net_1 ), .B(\wburst_cnt[0]_net_1 ), .C(
        \wburst_cnt[8]_net_1 ), .D(\wburst_cnt[5]_net_1 ), .Y(
        w_clk_cnt_1_sqmuxa_1_5_net_1));
    SLE \wburst_cnt[1]  (.D(\wburst_cntoi[1] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(wburst_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\wburst_cnt[1]_net_1 ));
    CFG4 #( .INIT(16'h0F88) )  \w_loop_state_RNO[0]  (.A(write_start_c)
        , .B(un2_wt_1_c5_net_1), .C(\w_loop[3]_net_1 ), .D(w_start), 
        .Y(N_235_i_0));
    SLE \wburst_cnt[4]  (.D(\wburst_cnt_s[4] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(wburst_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\wburst_cnt[4]_net_1 ));
    CFG3 #( .INIT(8'hC9) )  un1_rt_1_axbxc2 (.A(
        CMD_Decode_0_r_xfer_sizeoi[5]), .B(
        CMD_Decode_0_r_xfer_sizeoi[6]), .C(
        CMD_Decode_0_r_xfer_sizeoi[4]), .Y(un4_rt_1_6_reti));
    ARI1 #( .INIT(20'h48800) )  \rburst_cnt_s[8]  (.A(VCC_net_1), .B(
        rburst_cnt), .C(\rburst_cnt[8]_net_1 ), .D(GND_net_1), .FCI(
        \rburst_cnt_cry[7]_net_1 ), .S(\rburst_cnt_s[8]_net_1 ), .Y(), 
        .FCO());
    ARI1 #( .INIT(20'h48800) )  \w_clk_cnt_cry[11]  (.A(VCC_net_1), .B(
        \w_clk_cnt_cry_cy_Y[0] ), .C(\w_clk_cnt[11]_net_1 ), .D(
        GND_net_1), .FCI(\w_clk_cnt_cry[10]_net_1 ), .S(
        \w_clk_cnt_s[11] ), .Y(), .FCO(\w_clk_cnt_cry[11]_net_1 ));
    CFG4 #( .INIT(16'h0A0C) )  \rt_state_RNO[0]  (.A(
        un4_rt_1_cry_10_net_1), .B(rt_0_net_1), .C(\rt_state[1]_net_1 )
        , .D(\rt_state[0]_net_1 ), .Y(N_794_i_0));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNIEAIC[49]  (.A(
        \Rdata_mem_reto[49] ), .B(\WDATA_reto[49] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[49]));
    ARI1 #( .INIT(20'h5A802) )  AHB_ADDR_6_cry_2_0 (.A(
        \AXI_IF_0_AHB_ADDR_reto[2] ), .B(w_loop_0_sqmuxa_reto), .C(
        N_771_reto), .D(\ahb_state_reto[0] ), .FCI(GND_net_1), .S(), 
        .Y(AHB_ADDR_6_cry_2_0_Y), .FCO(AHB_ADDR_6_cry_2));
    CFG4 #( .INIT(16'hFE00) )  \r_clk_cnt_lm_0[1]  (.A(
        \rt_state[0]_net_1 ), .B(\rt_state[1]_net_1 ), .C(rt_0_net_1), 
        .D(\r_clk_cnt_s[1] ), .Y(\r_clk_cnt_lm[1] ));
    ARI1 #( .INIT(20'h4AA00) )  un8_AWADDR_int_1_cry_23 (.A(VCC_net_1), 
        .B(\AWADDR_int[30]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un8_AWADDR_int_1_cry_22_net_1), .S(un8_AWADDR_int_1_cry_23_S), 
        .Y(), .FCO(un8_AWADDR_int_1_cry_23_net_1));
    ARI1 #( .INIT(20'h48800) )  AHB_ADDR_6_cry_11 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[11] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_10_net_1), .S(
        AXI_IF_0_AHB_ADDR[11]), .Y(), .FCO(AHB_ADDR_6_cry_11_net_1));
    SLE \WDATA_ret[49]  (.D(\Rdata_mem_reto[49] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[49] ));
    SLE \AWADDR_1[7]  (.D(\AWADDR_int[7]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(burst_cnt_0_sqmuxa_1)
        , .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWADDR[7]));
    SLE \AWADDR_1[16]  (.D(\AWADDR_int[16]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(burst_cnt_0_sqmuxa_1)
        , .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWADDR[16]));
    CFG4 #( .INIT(16'h4051) )  un1_WSTRB_0_sqmuxa_2_i_i (.A(wburst_cnt)
        , .B(\axi_fsm_current_state[0]_net_1 ), .C(
        AXI_IF_0_BIF_1_AWREADY), .D(N_38), .Y(N_24));
    SLE HADDR_ret_3 (.D(AXI_IF_0_AHB_ADDR[26]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_AHB_ADDR_reto_0_24));
    CFG4 #( .INIT(16'h8091) )  un1_WVALID_0_sqmuxa_1_0 (.A(wburst_cnt), 
        .B(\axi_fsm_current_state[0]_net_1 ), .C(AXI_IF_0_BIF_1_WREADY)
        , .D(N_236), .Y(un1_WVALID_0_sqmuxa_1_0_net_1));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNIA6IC[45]  (.A(
        \Rdata_mem_reto[45] ), .B(\WDATA_reto[45] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[45]));
    SLE \AHB_DATA_1[9]  (.D(\AHB_DATA_5[9]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_452_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_AHB_DATA[9]));
    ARI1 #( .INIT(20'h4AA00) )  un8_AWADDR_int_1_cry_9 (.A(VCC_net_1), 
        .B(\AWADDR_int[16]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un8_AWADDR_int_1_cry_8_net_1), .S(un8_AWADDR_int_1_cry_9_S), 
        .Y(), .FCO(un8_AWADDR_int_1_cry_9_net_1));
    SLE \WDATA_ret[38]  (.D(\Rdata_mem_reto[38] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[38] ));
    SLE \WSTRB_1[0]  (.D(VCC_net_1), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_192), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_WSTRB[1]));
    SLE AHB_ADDR_ret_14 (.D(AXI_IF_0_AHB_ADDR[13]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[13] ));
    SLE \WDATA_ret[52]  (.D(\Rdata_mem_reto[52] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[52] ));
    CFG2 #( .INIT(4'h8) )  AWVALID_ext_2 (.A(AWVALID_reto), .B(
        AXI_IF_0_BIF_1_AWREADY_reto), .Y(AXI_IF_0_BIF_1_AWVALID));
    ARI1 #( .INIT(20'h48800) )  AHB_ADDR_6_cry_30 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[30] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_29_net_1), .S(
        AXI_IF_0_AHB_ADDR[30]), .Y(), .FCO(AHB_ADDR_6_cry_30_net_1));
    ARI1 #( .INIT(20'h48800) )  \wburst_cnt_cry[0]  (.A(VCC_net_1), .B(
        wburst_cnt), .C(\wburst_cnt[0]_net_1 ), .D(GND_net_1), .FCI(
        wburst_cnt_s_552_FCO), .S(\wburst_cntoi[0] ), .Y(), .FCO(
        \wburst_cnt_cry[0]_net_1 ));
    CFG2 #( .INIT(4'h1) )  \ahb_state_ns_i_a3_RNIRMEM[0]  (.A(N_771), 
        .B(\ahb_state[0]_net_1 ), .Y(N_452_i_0));
    ARI1 #( .INIT(20'h48800) )  AHB_ADDR_6_cry_25 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[25] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_24_net_1), .S(
        AXI_IF_0_AHB_ADDR[25]), .Y(), .FCO(AHB_ADDR_6_cry_25_net_1));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNIA5GC[28]  (.A(
        \Rdata_mem_reto[28] ), .B(\WDATA_reto[28] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[28]));
    SLE \r_loop[2]  (.D(\r_loop_5[2]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\r_loop[2]_net_1 ));
    ARI1 #( .INIT(20'h5AA55) )  read_read1_cry_17 (.A(un4_rt_1_7), .B(
        AXI_IF_0_BIF_1_ARADDR[17]), .C(GND_net_1), .D(GND_net_1), .FCI(
        read_read1_cry_16_net_1), .S(), .Y(), .FCO(
        read_read1_cry_17_net_1));
    CFG2 #( .INIT(4'h8) )  \AWADDR_int_RNO[28]  (.A(
        un8_AWADDR_int_1_cry_21_S), .B(wburst_cnt), .Y(N_1238_i_0));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI83GC[26]  (.A(
        \Rdata_mem_reto[26] ), .B(\WDATA_reto[26] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[26]));
    SLE \w_clk_cnt[5]  (.D(\w_clk_cnt_s[5] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(w_clk_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\w_clk_cnt[5]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  ARADDR_6_cry_11 (.A(VCC_net_1), .B(
        \axi_fsm_read_state_ns[0] ), .C(AXI_IF_0_BIF_1_ARADDR[11]), .D(
        GND_net_1), .FCI(ARADDR_6_cry_10_net_1), .S(\ARADDR_6[11] ), 
        .Y(), .FCO(ARADDR_6_cry_11_net_1));
    CFG3 #( .INIT(8'h41) )  \burst_cnt_RNO[2]  (.A(
        burst_cnt_0_sqmuxa_1), .B(N_34), .C(\burst_cnt[2]_net_1 ), .Y(
        N_19_i_0));
    SLE \AHB_DATA_1[6]  (.D(\AHB_DATA_5[6]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_452_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_AHB_DATA[6]));
    SLE ARVALID (.D(\axi_fsm_read_state_i_0[0] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(un1_ARBURST_0_sqmuxa)
        , .ALn(MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(ARVALID_net_1));
    SLE \WDATA_ret[8]  (.D(\Rdata_mem_reto[8] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[8] ));
    ARI1 #( .INIT(20'h48800) )  ARADDR_6_cry_22 (.A(VCC_net_1), .B(
        \axi_fsm_read_state_ns[0] ), .C(AXI_IF_0_BIF_1_ARADDR[22]), .D(
        GND_net_1), .FCI(ARADDR_6_cry_21_net_1), .S(\ARADDR_6[22] ), 
        .Y(), .FCO(ARADDR_6_cry_22_net_1));
    SLE \ARADDR[9]  (.D(\ARADDR_6[9] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARADDR[9]));
    SLE AHB_ADDR_ret_31 (.D(AXI_IF_0_AHB_ADDR[30]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[30] ));
    ARI1 #( .INIT(20'h4AA00) )  \rdata_cnt_cry[5]  (.A(VCC_net_1), .B(
        \rdata_cnt[5]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \rdata_cnt_cry[4]_net_1 ), .S(\rdata_cnt_s[5] ), .Y(), .FCO(
        \rdata_cnt_cry[5]_net_1 ));
    SLE \WDATA_ret[5]  (.D(\Rdata_mem_reto[5] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[5] ));
    ARI1 #( .INIT(20'h48800) )  AHB_ADDR_6_cry_17 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[17] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_16_net_1), .S(
        AXI_IF_0_AHB_ADDR[17]), .Y(), .FCO(AHB_ADDR_6_cry_17_net_1));
    CFG3 #( .INIT(8'h37) )  w_loop_0_sqmuxa (.A(un3_ahb2_net_1), .B(
        \ahb_state[0]_net_1 ), .C(un5_ahb2_net_1), .Y(
        w_loop_0_sqmuxa_net_1));
    SLE \WDATA_ret[45]  (.D(\Rdata_mem_reto[45] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[45] ));
    CFG3 #( .INIT(8'hAC) )  \AHB_DATA_5[0]  (.A(\w_clk_cnt[0]_net_1 ), 
        .B(\r_clk_cnt[0]_net_1 ), .C(ahb0_net_1), .Y(
        \AHB_DATA_5[0]_net_1 ));
    CFG2 #( .INIT(4'h9) )  un7_wt_1_axb_8_i (.A(un7_wt_1_8), .B(
        \wburst_cnt[8]_net_1 ), .Y(un7_wt_1_axb_8_i_0));
    SLE HADDR_ret_2 (.D(AXI_IF_0_AHB_ADDR[19]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_AHB_ADDR_reto_0_17));
    SLE \WDATA_ret[6]  (.D(\Rdata_mem_reto[6] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[6] ));
    CFG4 #( .INIT(16'hFE00) )  \r_clk_cnt_lm_0[13]  (.A(
        \rt_state[0]_net_1 ), .B(\rt_state[1]_net_1 ), .C(rt_0_net_1), 
        .D(\r_clk_cnt_s[13]_net_1 ), .Y(\r_clk_cnt_lm[13] ));
    CFG4 #( .INIT(16'h0004) )  un5_ahb2 (.A(\r_loop[0]_net_1 ), .B(
        \r_loop[3]_net_1 ), .C(\r_loop[2]_net_1 ), .D(
        \r_loop[1]_net_1 ), .Y(un5_ahb2_net_1));
    ARI1 #( .INIT(20'h4AA00) )  \r_clk_cnt_cry[11]  (.A(VCC_net_1), .B(
        \r_clk_cnt[11]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \r_clk_cnt_cry[10]_net_1 ), .S(\r_clk_cnt_s[11] ), .Y(), .FCO(
        \r_clk_cnt_cry[11]_net_1 ));
    CFG4 #( .INIT(16'hFFFE) )  un5_write_idle2_NE_2 (.A(
        \wburst_cntoi[0] ), .B(\wburst_cntoi[3] ), .C(
        \wburst_cntoi[2] ), .D(\wburst_cntoi[1] ), .Y(
        un5_write_idle2_NE_2_reti));
    SLE \AHB_DATA_1[12]  (.D(\AHB_DATA_5[12]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_452_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_AHB_DATA[12]));
    ARI1 #( .INIT(20'h48800) )  ARADDR_6_cry_28 (.A(VCC_net_1), .B(
        \axi_fsm_read_state_ns[0] ), .C(AXI_IF_0_BIF_1_ARADDR[28]), .D(
        GND_net_1), .FCI(ARADDR_6_cry_27_net_1), .S(\ARADDR_6[28] ), 
        .Y(), .FCO(ARADDR_6_cry_28_net_1));
    SLE \ARADDR[18]  (.D(\ARADDR_6[18] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARADDR[18]));
    SLE \WDATA_ret[50]  (.D(\Rdata_mem_reto[50] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[50] ));
    ARI1 #( .INIT(20'h48800) )  ARADDR_6_cry_23 (.A(VCC_net_1), .B(
        \axi_fsm_read_state_ns[0] ), .C(AXI_IF_0_BIF_1_ARADDR[23]), .D(
        GND_net_1), .FCI(ARADDR_6_cry_22_net_1), .S(\ARADDR_6[23] ), 
        .Y(), .FCO(ARADDR_6_cry_23_net_1));
    SLE \w_clk_cnt[2]  (.D(\w_clk_cnt_s[2] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(w_clk_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\w_clk_cnt[2]_net_1 ));
    SLE \wburst_cnt[6]  (.D(\wburst_cnt_s[6] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(wburst_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\wburst_cnt[6]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \rdata_cnt_cry[4]  (.A(VCC_net_1), .B(
        \rdata_cnt[4]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \rdata_cnt_cry[3]_net_1 ), .S(\rdata_cnt_s[4] ), .Y(), .FCO(
        \rdata_cnt_cry[4]_net_1 ));
    ARI1 #( .INIT(20'h6AA00) )  read_read1_cry_10 (.A(VCC_net_1), .B(
        AXI_IF_0_BIF_1_ARADDR[10]), .C(GND_net_1), .D(GND_net_1), .FCI(
        read_read1_cry_9_net_1), .S(), .Y(), .FCO(
        read_read1_cry_10_net_1));
    ARI1 #( .INIT(20'h48800) )  \rburst_cnt_cry[3]  (.A(VCC_net_1), .B(
        rburst_cnt), .C(\rburst_cnt[3]_net_1 ), .D(GND_net_1), .FCI(
        \rburst_cnt_cry[2]_net_1 ), .S(\rburst_cntoi[3] ), .Y(), .FCO(
        \rburst_cnt_cry[3]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI3TEC[12]  (.A(
        \Rdata_mem_reto[12] ), .B(\WDATA_reto[12] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[12]));
    SLE \axi_fsm_read1_state[1]  (.D(\axi_fsm_read1_state_ns[1] ), 
        .CLK(MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), 
        .ALn(MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(rburst_cnt));
    CFG1 #( .INIT(2'h1) )  WRITE_AHB_RNO (.A(\ahb_state[0]_net_1 ), .Y(
        \ahb_state_i_0[0] ));
    SLE \AWADDR_1[15]  (.D(\AWADDR_int[15]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(burst_cnt_0_sqmuxa_1)
        , .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWADDR[15]));
    SLE AHB_ADDR_ret_32 (.D(AXI_IF_0_AHB_ADDR[31]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[31] ));
    SLE \WDATA_ret[12]  (.D(\Rdata_mem_reto[12] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[12] ));
    CFG4 #( .INIT(16'hFFFE) )  un5_write_idle2_NE_3_RNI38P82 (.A(
        un5_write_idle2_NE_3_net_1), .B(un5_write_idle2_NE_4_net_1), 
        .C(WDATA_intlde_i_o2_2), .D(un5_write_idle2_NE_5_net_1), .Y(
        N_236));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI60FC[15]  (.A(
        \Rdata_mem_reto[15] ), .B(\WDATA_reto[15] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[15]));
    SLE \w_loop[3]  (.D(\w_loop_5[3]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\w_loop[3]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \axi_fsm_read1_state_RNIM12K[1]  (.A(
        AXI_IF_0_BIF_1_RVALID), .B(rburst_cnt), .Y(N_368_i_0));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNIB8JC[55]  (.A(
        \Rdata_mem_reto[55] ), .B(\WDATA_reto[55] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[55]));
    CFG3 #( .INIT(8'hAC) )  \AHB_DATA_5[13]  (.A(\w_clk_cnt[13]_net_1 )
        , .B(\r_clk_cnt[13]_net_1 ), .C(ahb0_net_1), .Y(
        \AHB_DATA_5[13]_net_1 ));
    CFG4 #( .INIT(16'h8000) )  un1_WVALID_0_sqmuxa_i_i_a2_0 (.A(
        \burst_cnt[3]_net_1 ), .B(\burst_cnt[2]_net_1 ), .C(
        \burst_cnt[1]_net_1 ), .D(\burst_cnt[0]_net_1 ), .Y(N_254));
    ARI1 #( .INIT(20'h4AA00) )  un8_AWADDR_int_1_cry_21 (.A(VCC_net_1), 
        .B(\AWADDR_int[28]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un8_AWADDR_int_1_cry_20_net_1), .S(un8_AWADDR_int_1_cry_21_S), 
        .Y(), .FCO(un8_AWADDR_int_1_cry_21_net_1));
    SLE \WDATA_ret[57]  (.D(\Rdata_mem_reto[57] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[57] ));
    SLE \WDATA_ret[23]  (.D(\Rdata_mem_reto[23] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[23] ));
    CFG2 #( .INIT(4'h8) )  \AWADDR_int_RNO[9]  (.A(
        un8_AWADDR_int_1_cry_2_S), .B(wburst_cnt), .Y(N_1007_i_0));
    ARI1 #( .INIT(20'h6AA00) )  un7_wt_1_cry_1 (.A(VCC_net_1), .B(
        \wburst_cnt[1]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un7_wt_1_cry_0_net_1), .S(), .Y(), .FCO(un7_wt_1_cry_1_net_1));
    ARI1 #( .INIT(20'h5AA55) )  read_read1_cry_14 (.A(
        CMD_Decode_0_r_xfer_size_i_0[4]), .B(AXI_IF_0_BIF_1_ARADDR[14])
        , .C(GND_net_1), .D(GND_net_1), .FCI(read_read1_cry_13_net_1), 
        .S(), .Y(), .FCO(read_read1_cry_14_net_1));
    SLE \ARADDR[24]  (.D(\ARADDR_6[24] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(GND_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARADDR[24]));
    CFG1 #( .INIT(2'h1) )  un7_wt_1_cry_6_RNO (.A(
        \wburst_cnt[6]_net_1 ), .Y(\wburst_cnt_i[6] ));
    SLE \ARADDR[19]  (.D(\ARADDR_6[19] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARADDR[19]));
    CFG4 #( .INIT(16'hFE00) )  \r_clk_cnt_lm_0[12]  (.A(
        \rt_state[0]_net_1 ), .B(\rt_state[1]_net_1 ), .C(rt_0_net_1), 
        .D(\r_clk_cnt_s[12] ), .Y(\r_clk_cnt_lm[12] ));
    SLE \rdata_cnt[1]  (.D(\rdata_cnt_s[1] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_368_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rdata_cnt[1]_net_1 ));
    SLE \ARADDR[30]  (.D(\ARADDR_6[30] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARADDR[30]));
    ARI1 #( .INIT(20'h48800) )  AHB_ADDR_6_cry_28 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[28] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_27_net_1), .S(
        AXI_IF_0_AHB_ADDR[28]), .Y(), .FCO(AHB_ADDR_6_cry_28_net_1));
    SLE \r_clk_cnt[5]  (.D(\r_clk_cnt_lm[5] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_314_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\r_clk_cnt[5]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI72GC[25]  (.A(
        \Rdata_mem_reto[25] ), .B(\WDATA_reto[25] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[25]));
    CFG4 #( .INIT(16'h0080) )  r_loop_ret_RNO (.A(\r_loop_5[0]_net_1 ), 
        .B(\r_loop_5[1]_net_1 ), .C(\r_loop_5[2]_net_1 ), .D(
        \r_loop_5[3]_net_1 ), .Y(g0_0_2_reti));
    SLE \WDATA_ret[54]  (.D(\Rdata_mem_reto[54] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[54] ));
    ARI1 #( .INIT(20'h45500) )  read_read1_cry_31 (.A(VCC_net_1), .B(
        AXI_IF_0_BIF_1_ARADDR[31]), .C(GND_net_1), .D(GND_net_1), .FCI(
        read_read1_cry_30_net_1), .S(), .Y(), .FCO(read_read1));
    SLE \AWADDR_int[16]  (.D(N_1150_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WVALID_0_sqmuxa_1_0_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\AWADDR_int[16]_net_1 ));
    SLE \ARADDR[22]  (.D(\ARADDR_6[22] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARADDR[22]));
    CFG4 #( .INIT(16'h5554) )  \WDATA_int_lm_0[0]  (.A(
        \WDATA_int[0]_net_1 ), .B(\axi_fsm_current_state[0]_net_1 ), 
        .C(N_236), .D(wburst_cnt), .Y(\WDATA_int_lm[0] ));
    ARI1 #( .INIT(20'h5AA55) )  read_read1_cry_18 (.A(un4_rt_1_8), .B(
        AXI_IF_0_BIF_1_ARADDR[18]), .C(GND_net_1), .D(GND_net_1), .FCI(
        read_read1_cry_17_net_1), .S(), .Y(), .FCO(
        read_read1_cry_18_net_1));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNIPTQD[9]  (.A(
        \Rdata_mem_reto[9] ), .B(\WDATA_reto[9] ), .C(RVALID_li_reto), 
        .Y(AXI_IF_0_BIF_1_WDATA[9]));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNIB6GC[29]  (.A(
        \Rdata_mem_reto[29] ), .B(\WDATA_reto[29] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[29]));
    ARI1 #( .INIT(20'h4AA00) )  \WDATA_int_s[8]  (.A(VCC_net_1), .B(
        \WDATA_int[8]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \WDATA_int_cry[7]_net_1 ), .S(\WDATA_int_s[8]_net_1 ), .Y(), 
        .FCO());
    SLE \rt_state[1]  (.D(\rt_state_ns[1] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rt_state[1]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un8_AWADDR_int_1_cry_18 (.A(VCC_net_1), 
        .B(\AWADDR_int[25]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un8_AWADDR_int_1_cry_17_net_1), .S(un8_AWADDR_int_1_cry_18_S), 
        .Y(), .FCO(un8_AWADDR_int_1_cry_18_net_1));
    CFG4 #( .INIT(16'hAAA8) )  \WDATA_int_lm_0[2]  (.A(
        \WDATA_int_s[2] ), .B(N_236), .C(
        \axi_fsm_current_state[0]_net_1 ), .D(wburst_cnt), .Y(
        \WDATA_int_lm[2] ));
    SLE \WDATA_ret[10]  (.D(\Rdata_mem_reto[10] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[10] ));
    SLE \wburst_cnt[3]  (.D(\wburst_cntoi[3] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(wburst_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\wburst_cnt[3]_net_1 ));
    SLE \AWADDR_int[19]  (.D(N_1117_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WVALID_0_sqmuxa_1_0_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\AWADDR_int[19]_net_1 ));
    SLE AHB_ADDR_ret_28 (.D(AXI_IF_0_AHB_ADDR[27]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[27] ));
    ARI1 #( .INIT(20'h48800) )  AHB_ADDR_6_cry_26 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[26] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_25_net_1), .S(
        AXI_IF_0_AHB_ADDR[26]), .Y(), .FCO(AHB_ADDR_6_cry_26_net_1));
    ARI1 #( .INIT(20'h6AA00) )  read_read1_cry_7 (.A(VCC_net_1), .B(
        AXI_IF_0_BIF_1_ARADDR[7]), .C(GND_net_1), .D(GND_net_1), .FCI(
        GND_net_1), .S(), .Y(), .FCO(read_read1_cry_7_net_1));
    SLE \AWADDR_int[23]  (.D(N_1073_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WVALID_0_sqmuxa_1_0_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\AWADDR_int[23]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI4UEC[13]  (.A(
        \Rdata_mem_reto[13] ), .B(\WDATA_reto[13] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[13]));
    SLE \WDATA_ret[33]  (.D(\Rdata_mem_reto[33] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[33] ));
    ARI1 #( .INIT(20'h48800) )  \wburst_cnt_cry[7]  (.A(VCC_net_1), .B(
        wburst_cnt), .C(\wburst_cnt[7]_net_1 ), .D(GND_net_1), .FCI(
        \wburst_cnt_cry[6]_net_1 ), .S(\wburst_cnt_s[7] ), .Y(), .FCO(
        \wburst_cnt_cry[7]_net_1 ));
    CFG3 #( .INIT(8'hBF) )  \axi_fsm_current_state_ns_1_0_.m6_0_o2  (
        .A(\axi_fsm_current_state[0]_net_1 ), .B(wburst_cnt), .C(
        AXI_IF_0_BIF_1_WREADY), .Y(N_31));
    SLE \r_clk_cnt[3]  (.D(\r_clk_cnt_lm[3] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_314_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\r_clk_cnt[3]_net_1 ));
    CFG4 #( .INIT(16'h4150) )  \burst_cnt_RNO[3]  (.A(
        burst_cnt_0_sqmuxa_1), .B(N_34), .C(\burst_cnt[3]_net_1 ), .D(
        \burst_cnt[2]_net_1 ), .Y(N_17_i_0));
    CFG3 #( .INIT(8'hAC) )  \AHB_DATA_5[1]  (.A(\w_clk_cnt[1]_net_1 ), 
        .B(\r_clk_cnt[1]_net_1 ), .C(ahb0_net_1), .Y(
        \AHB_DATA_5[1]_net_1 ));
    SLE \wburst_cnt[7]  (.D(\wburst_cnt_s[7] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(wburst_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\wburst_cnt[7]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \AHB_DATA_5[5]  (.A(\w_clk_cnt[5]_net_1 ), 
        .B(\r_clk_cnt[5]_net_1 ), .C(ahb0_net_1), .Y(
        \AHB_DATA_5[5]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  \rburst_cnt_cry[0]  (.A(VCC_net_1), .B(
        rburst_cnt), .C(\rburst_cnt[0]_net_1 ), .D(GND_net_1), .FCI(
        rburst_cnt_s_553_FCO), .S(\rburst_cntoi[0] ), .Y(), .FCO(
        \rburst_cnt_cry[0]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI96JC[53]  (.A(
        \Rdata_mem_reto[53] ), .B(\WDATA_reto[53] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[53]));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI3VGC[30]  (.A(
        \Rdata_mem_reto[30] ), .B(\WDATA_reto[30] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[30]));
    SLE \rdata_cnt[0]  (.D(\rdata_cnt_s[0] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_368_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rdata_cnt[0]_net_1 ));
    CFG4 #( .INIT(16'hDC10) )  \wt_state_ns_0[0]  (.A(
        \wt_state[1]_net_1 ), .B(\wt_state[0]_net_1 ), .C(wt_0), .D(
        un7_wt_1_cry_10_net_1), .Y(\wt_state_ns[0] ));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNIC8IC[47]  (.A(
        \Rdata_mem_reto[47] ), .B(\WDATA_reto[47] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[47]));
    SLE \burst_cnt[0]  (.D(\burst_cnt_0_0[0]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\burst_cnt[0]_net_1 ));
    SLE \WDATA_ret[61]  (.D(\Rdata_mem_reto[61] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[61] ));
    CFG1 #( .INIT(2'h1) )  ARVALID_RNO (.A(
        \axi_fsm_read_state[0]_net_1 ), .Y(\axi_fsm_read_state_i_0[0] )
        );
    SLE \axi_fsm_current_state[1]  (.D(\axi_fsm_current_state_ns[1] ), 
        .CLK(MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), 
        .ALn(MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(wburst_cnt));
    ARI1 #( .INIT(20'h4AA00) )  \WDATA_int_cry[5]  (.A(VCC_net_1), .B(
        \WDATA_int[5]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \WDATA_int_cry[4]_net_1 ), .S(\WDATA_int_s[5] ), .Y(), .FCO(
        \WDATA_int_cry[5]_net_1 ));
    CFG3 #( .INIT(8'hFE) )  rburst_cnt_ret_RNISP903 (.A(g0_1_1), .B(
        g0_1_0), .C(g0_1_2), .Y(un3_ahb1_NE));
    ARI1 #( .INIT(20'h48800) )  AHB_ADDR_6_cry_23 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[23] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_22_net_1), .S(
        AXI_IF_0_AHB_ADDR[23]), .Y(), .FCO(AHB_ADDR_6_cry_23_net_1));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI3UFC[21]  (.A(
        \Rdata_mem_reto[21] ), .B(\WDATA_reto[21] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[21]));
    SLE \WDATA_ret[17]  (.D(\Rdata_mem_reto[17] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[17] ));
    ARI1 #( .INIT(20'h4AA00) )  r_clk_cnt_s_555 (.A(VCC_net_1), .B(
        \r_clk_cnt[0]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        VCC_net_1), .S(), .Y(), .FCO(r_clk_cnt_s_555_FCO));
    ARI1 #( .INIT(20'h6AA00) )  un4_rt_1_cry_1 (.A(VCC_net_1), .B(
        \rburst_cnt[1]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un4_rt_1_cry_0_net_1), .S(), .Y(), .FCO(un4_rt_1_cry_1_net_1));
    ARI1 #( .INIT(20'h5AA55) )  un4_write_idle1_cry_6 (.A(
        CMD_Decode_0_w_xfer_size[6]), .B(\wburst_cnt[6]_net_1 ), .C(
        GND_net_1), .D(GND_net_1), .FCI(un4_write_idle1_cry_5_net_1), 
        .S(), .Y(), .FCO(un4_write_idle1_cry_6_net_1));
    SLE \AWADDR_1[11]  (.D(\AWADDR_int[11]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(burst_cnt_0_sqmuxa_1)
        , .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWADDR[11]));
    ARI1 #( .INIT(20'h48800) )  \w_clk_cnt_s[13]  (.A(VCC_net_1), .B(
        \w_clk_cnt_cry_cy_Y[0] ), .C(\w_clk_cnt[13]_net_1 ), .D(
        GND_net_1), .FCI(\w_clk_cnt_cry[12]_net_1 ), .S(
        \w_clk_cnt_s[13]_net_1 ), .Y(), .FCO());
    CFG2 #( .INIT(4'h8) )  \AWADDR_int_RNO[31]  (.A(
        un8_AWADDR_int_1_s_24_S), .B(wburst_cnt), .Y(N_1205_i_0));
    ARI1 #( .INIT(20'h6FFFE) )  un7_wt_1_cry_10 (.A(
        CMD_Decode_0_w_xfer_size[8]), .B(un2_wt_1_c2_net_1), .C(
        CMD_Decode_0_w_xfer_size[6]), .D(CMD_Decode_0_w_xfer_size[7]), 
        .FCI(un7_wt_1_cry_9_net_1), .S(), .Y(), .FCO(
        un7_wt_1_cry_10_net_1));
    SLE \burst_cnt[1]  (.D(N_21_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\burst_cnt[1]_net_1 ));
    SLE \r_loop[3]  (.D(\r_loop_5[3]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\r_loop[3]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \AWADDR_int_RNO[13]  (.A(
        un8_AWADDR_int_1_cry_6_S), .B(wburst_cnt), .Y(N_1183_i_0));
    ARI1 #( .INIT(20'h6AA00) )  read_read1_cry_12 (.A(VCC_net_1), .B(
        AXI_IF_0_BIF_1_ARADDR[12]), .C(GND_net_1), .D(GND_net_1), .FCI(
        read_read1_cry_11_net_1), .S(), .Y(), .FCO(
        read_read1_cry_12_net_1));
    SLE \WDATA_ret[14]  (.D(\Rdata_mem_reto[14] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[14] ));
    ARI1 #( .INIT(20'h48800) )  \wburst_cnt_cry[4]  (.A(VCC_net_1), .B(
        wburst_cnt), .C(\wburst_cnt[4]_net_1 ), .D(GND_net_1), .FCI(
        \wburst_cnt_cry[3]_net_1 ), .S(\wburst_cnt_s[4] ), .Y(), .FCO(
        \wburst_cnt_cry[4]_net_1 ));
    SLE \w_clk_cnt[7]  (.D(\w_clk_cnt_s[7] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(w_clk_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\w_clk_cnt[7]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  AHB_ADDR_6_cry_22 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[22] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_21_net_1), .S(
        AXI_IF_0_AHB_ADDR[22]), .Y(), .FCO(AHB_ADDR_6_cry_22_net_1));
    ARI1 #( .INIT(20'h48800) )  AHB_ADDR_6_cry_19 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[19] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_18_net_1), .S(
        AXI_IF_0_AHB_ADDR[19]), .Y(), .FCO(AHB_ADDR_6_cry_19_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un8_AWADDR_int_1_cry_13 (.A(VCC_net_1), 
        .B(\AWADDR_int[20]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un8_AWADDR_int_1_cry_12_net_1), .S(un8_AWADDR_int_1_cry_13_S), 
        .Y(), .FCO(un8_AWADDR_int_1_cry_13_net_1));
    SLE \burst_cnt[3]  (.D(N_17_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\burst_cnt[3]_net_1 ));
    CFG4 #( .INIT(16'hECCC) )  
        axi_fsm_read1_state_1_sqmuxa_0_a3_RNIJ3KV (.A(rburst_cnt), .B(
        axi_fsm_read1_state_1_sqmuxa), .C(AXI_IF_0_BIF_1_RVALID), .D(
        AXI_IF_0_BIF_1_RLAST), .Y(rburst_cnte));
    CFG4 #( .INIT(16'h7222) )  \r_loop_state_RNO[0]  (.A(r_start), .B(
        \r_loop[3]_net_1 ), .C(un1_rt_1_c5_net_1), .D(read_start_c), 
        .Y(N_808_i_0));
    ARI1 #( .INIT(20'h48800) )  ARADDR_6_cry_12 (.A(VCC_net_1), .B(
        \axi_fsm_read_state_ns[0] ), .C(AXI_IF_0_BIF_1_ARADDR[12]), .D(
        GND_net_1), .FCI(ARADDR_6_cry_11_net_1), .S(\ARADDR_6[12] ), 
        .Y(), .FCO(ARADDR_6_cry_12_net_1));
    ARI1 #( .INIT(20'h48800) )  \wburst_cnt_cry[1]  (.A(VCC_net_1), .B(
        wburst_cnt), .C(\wburst_cnt[1]_net_1 ), .D(GND_net_1), .FCI(
        \wburst_cnt_cry[0]_net_1 ), .S(\wburst_cntoi[1] ), .Y(), .FCO(
        \wburst_cnt_cry[1]_net_1 ));
    SLE \w_clk_cnt[10]  (.D(\w_clk_cnt_s[10] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(w_clk_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\w_clk_cnt[10]_net_1 ));
    SLE \WDATA_ret[56]  (.D(\Rdata_mem_reto[56] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[56] ));
    ARI1 #( .INIT(20'h48800) )  ARADDR_6_cry_20 (.A(VCC_net_1), .B(
        \axi_fsm_read_state_ns[0] ), .C(AXI_IF_0_BIF_1_ARADDR[20]), .D(
        GND_net_1), .FCI(ARADDR_6_cry_19_net_1), .S(\ARADDR_6[20] ), 
        .Y(), .FCO(ARADDR_6_cry_20_net_1));
    CFG4 #( .INIT(16'hAAA8) )  \WDATA_int_lm_0[8]  (.A(
        \WDATA_int_s[8]_net_1 ), .B(N_236), .C(
        \axi_fsm_current_state[0]_net_1 ), .D(wburst_cnt), .Y(
        \WDATA_int_lm[8] ));
    ARI1 #( .INIT(20'h51EE1) )  un7_wt_1_cry_6 (.A(\wburst_cnt_i[6] ), 
        .B(CMD_Decode_0_w_xfer_size[4]), .C(
        CMD_Decode_0_w_xfer_size[5]), .D(CMD_Decode_0_w_xfer_size[6]), 
        .FCI(un7_wt_1_cry_5_net_1), .S(), .Y(), .FCO(
        un7_wt_1_cry_6_net_1));
    CFG4 #( .INIT(16'h0004) )  r_loop_ret_RNIUF6A3 (.A(g0_1_0), .B(
        g0_0_2), .C(g0_1_1), .D(g0_1_2), .Y(N_222));
    ARI1 #( .INIT(20'h48800) )  \wburst_cnt_cry[6]  (.A(VCC_net_1), .B(
        wburst_cnt), .C(\wburst_cnt[6]_net_1 ), .D(GND_net_1), .FCI(
        \wburst_cnt_cry[5]_net_1 ), .S(\wburst_cnt_s[6] ), .Y(), .FCO(
        \wburst_cnt_cry[6]_net_1 ));
    SLE \AHB_DATA_1[7]  (.D(\AHB_DATA_5[7]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_452_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_AHB_DATA[7]));
    ARI1 #( .INIT(20'h48800) )  ARADDR_6_cry_30 (.A(VCC_net_1), .B(
        \axi_fsm_read_state_ns[0] ), .C(AXI_IF_0_BIF_1_ARADDR[30]), .D(
        GND_net_1), .FCI(ARADDR_6_cry_29_net_1), .S(\ARADDR_6[30] ), 
        .Y(), .FCO(ARADDR_6_cry_30_net_1));
    ARI1 #( .INIT(20'h4DD00) )  AHB_ADDR_6_cry_8 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[8] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_7_net_1), .S(
        AXI_IF_0_AHB_ADDR[8]), .Y(), .FCO(AHB_ADDR_6_cry_8_net_1));
    ARI1 #( .INIT(20'h4DD00) )  ARADDR_6_cry_24 (.A(VCC_net_1), .B(
        \axi_fsm_read_state_ns[0] ), .C(AXI_IF_0_BIF_1_ARADDR[24]), .D(
        GND_net_1), .FCI(ARADDR_6_cry_23_net_1), .S(\ARADDR_6[24] ), 
        .Y(), .FCO(ARADDR_6_cry_24_net_1));
    SLE WDATA_ret_128 (.D(AXI_IF_0_BIF_1_RVALID_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(RVALID_li_reto));
    SLE \AWADDR_int[31]  (.D(N_1205_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WVALID_0_sqmuxa_1_0_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\AWADDR_int[31]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI75KC[60]  (.A(
        \Rdata_mem_reto[60] ), .B(\WDATA_reto[60] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[60]));
    SLE \AWADDR_1[14]  (.D(\AWADDR_int[14]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(burst_cnt_0_sqmuxa_1)
        , .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWADDR[14]));
    CFG1 #( .INIT(2'h1) )  \rdata_cnt_RNO[0]  (.A(\rdata_cnt[0]_net_1 )
        , .Y(\rdata_cnt_s[0] ));
    ARI1 #( .INIT(20'h48800) )  ARADDR_6_cry_18 (.A(VCC_net_1), .B(
        \axi_fsm_read_state_ns[0] ), .C(AXI_IF_0_BIF_1_ARADDR[18]), .D(
        GND_net_1), .FCI(ARADDR_6_cry_17_net_1), .S(\ARADDR_6[18] ), 
        .Y(), .FCO(ARADDR_6_cry_18_net_1));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNINRQD[7]  (.A(
        \Rdata_mem_reto[7] ), .B(\WDATA_reto[7] ), .C(RVALID_li_reto), 
        .Y(AXI_IF_0_BIF_1_WDATA[7]));
    SLE \WDATA_ret[41]  (.D(\Rdata_mem_reto[41] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[41] ));
    ARI1 #( .INIT(20'h4AA00) )  un8_AWADDR_int_1_cry_4 (.A(VCC_net_1), 
        .B(\AWADDR_int[11]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un8_AWADDR_int_1_cry_3_net_1), .S(un8_AWADDR_int_1_cry_4_S), 
        .Y(), .FCO(un8_AWADDR_int_1_cry_4_net_1));
    CFG3 #( .INIT(8'hBE) )  un5_write_idle2_NE_5 (.A(
        un5_write_idle2_NE_2_net_1), .B(\wburst_cnt[4]_net_1 ), .C(
        CMD_Decode_0_w_xfer_size[4]), .Y(un5_write_idle2_NE_5_net_1));
    ARI1 #( .INIT(20'h48800) )  ARADDR_6_cry_13 (.A(VCC_net_1), .B(
        \axi_fsm_read_state_ns[0] ), .C(AXI_IF_0_BIF_1_ARADDR[13]), .D(
        GND_net_1), .FCI(ARADDR_6_cry_12_net_1), .S(\ARADDR_6[13] ), 
        .Y(), .FCO(ARADDR_6_cry_13_net_1));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNIEBJC[58]  (.A(
        \Rdata_mem_reto[58] ), .B(\WDATA_reto[58] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[58]));
    SLE \AWADDR_1[17]  (.D(\AWADDR_int[17]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(burst_cnt_0_sqmuxa_1)
        , .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWADDR[17]));
    ARI1 #( .INIT(20'h45500) )  read_read1_cry_21 (.A(VCC_net_1), .B(
        AXI_IF_0_BIF_1_ARADDR[21]), .C(GND_net_1), .D(GND_net_1), .FCI(
        read_read1_cry_20_net_1), .S(), .Y(), .FCO(
        read_read1_cry_21_net_1));
    SLE HADDR_ret_8 (.D(AXI_IF_0_AHB_ADDR[24]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_AHB_ADDR_reto_0_22));
    SLE \ARADDR[23]  (.D(\ARADDR_6[23] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARADDR[23]));
    CFG4 #( .INIT(16'h0F0E) )  \r_clk_cnt_lm_0[0]  (.A(
        \rt_state[0]_net_1 ), .B(rt_0_net_1), .C(\r_clk_cnt[0]_net_1 ), 
        .D(\rt_state[1]_net_1 ), .Y(\r_clk_cnt_lm[0] ));
    CFG3 #( .INIT(8'h80) )  axi_fsm_read_state_1_sqmuxa_0_a3 (.A(
        \axi_fsm_read_state[0]_net_1 ), .B(read_read1), .C(
        AXI_IF_0_BIF_1_ARREADY), .Y(axi_fsm_read_state_1_sqmuxa));
    CFG4 #( .INIT(16'h3530) )  \rt_state_ns_0[1]  (.A(
        un4_rt_1_cry_10_net_1), .B(rt_state13_net_1), .C(
        \rt_state[1]_net_1 ), .D(\rt_state[0]_net_1 ), .Y(
        \rt_state_ns[1] ));
    CFG3 #( .INIT(8'h40) )  rt_0 (.A(\r_loop[3]_net_1 ), .B(r_start), 
        .C(un3_rt_0), .Y(rt_0_net_1));
    RAM1K18 Rdata_mem_Rdata_mem_0_0 (.A_DOUT({nc0, nc1, nc2, nc3, 
        \Rdata_mem_reto[31] , \Rdata_mem_reto[30] , 
        \Rdata_mem_reto[29] , \Rdata_mem_reto[28] , 
        \Rdata_mem_reto[27] , \Rdata_mem_reto[26] , 
        \Rdata_mem_reto[25] , \Rdata_mem_reto[24] , 
        \Rdata_mem_reto[23] , \Rdata_mem_reto[22] , 
        \Rdata_mem_reto[21] , \Rdata_mem_reto[20] , 
        \Rdata_mem_reto[19] , \Rdata_mem_reto[18] }), .B_DOUT({
        \Rdata_mem_reto[17] , \Rdata_mem_reto[16] , 
        \Rdata_mem_reto[15] , \Rdata_mem_reto[14] , 
        \Rdata_mem_reto[13] , \Rdata_mem_reto[12] , 
        \Rdata_mem_reto[11] , \Rdata_mem_reto[10] , 
        \Rdata_mem_reto[9] , \Rdata_mem_reto[8] , \Rdata_mem_reto[7] , 
        \Rdata_mem_reto[6] , \Rdata_mem_reto[5] , \Rdata_mem_reto[4] , 
        \Rdata_mem_reto[3] , \Rdata_mem_reto[2] , \Rdata_mem_reto[1] , 
        \Rdata_mem_reto[0] }), .BUSY(), .A_CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .A_DOUT_CLK(VCC_net_1), 
        .A_ARST_N(VCC_net_1), .A_DOUT_EN(VCC_net_1), .A_BLK({VCC_net_1, 
        VCC_net_1, VCC_net_1}), .A_DOUT_ARST_N(VCC_net_1), 
        .A_DOUT_SRST_N(VCC_net_1), .A_DIN({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, AXI_IF_0_BIF_1_RDATA[31], 
        AXI_IF_0_BIF_1_RDATA[30], AXI_IF_0_BIF_1_RDATA[29], 
        AXI_IF_0_BIF_1_RDATA[28], AXI_IF_0_BIF_1_RDATA[27], 
        AXI_IF_0_BIF_1_RDATA[26], AXI_IF_0_BIF_1_RDATA[25], 
        AXI_IF_0_BIF_1_RDATA[24], AXI_IF_0_BIF_1_RDATA[23], 
        AXI_IF_0_BIF_1_RDATA[22], AXI_IF_0_BIF_1_RDATA[21], 
        AXI_IF_0_BIF_1_RDATA[20], AXI_IF_0_BIF_1_RDATA[19], 
        AXI_IF_0_BIF_1_RDATA[18]}), .A_ADDR({\WDATA_int[8]_net_1 , 
        \WDATA_int[7]_net_1 , \WDATA_int[6]_net_1 , 
        \WDATA_int[5]_net_1 , \WDATA_int[4]_net_1 , 
        \WDATA_int[3]_net_1 , \WDATA_int[2]_net_1 , 
        \WDATA_int[1]_net_1 , \WDATA_int[0]_net_1 , GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1}), .A_WEN({
        VCC_net_1, VCC_net_1}), .B_CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .B_DOUT_CLK(VCC_net_1), 
        .B_ARST_N(VCC_net_1), .B_DOUT_EN(VCC_net_1), .B_BLK({
        AXI_IF_0_BIF_1_RVALID, AXI_IF_0_BIF_1_RVALID, 
        AXI_IF_0_BIF_1_RVALID}), .B_DOUT_ARST_N(VCC_net_1), 
        .B_DOUT_SRST_N(VCC_net_1), .B_DIN({AXI_IF_0_BIF_1_RDATA[17], 
        AXI_IF_0_BIF_1_RDATA[16], AXI_IF_0_BIF_1_RDATA[15], 
        AXI_IF_0_BIF_1_RDATA[14], AXI_IF_0_BIF_1_RDATA[13], 
        AXI_IF_0_BIF_1_RDATA[12], AXI_IF_0_BIF_1_RDATA[11], 
        AXI_IF_0_BIF_1_RDATA[10], AXI_IF_0_BIF_1_RDATA[9], 
        AXI_IF_0_BIF_1_RDATA[8], AXI_IF_0_BIF_1_RDATA[7], 
        AXI_IF_0_BIF_1_RDATA[6], AXI_IF_0_BIF_1_RDATA[5], 
        AXI_IF_0_BIF_1_RDATA[4], AXI_IF_0_BIF_1_RDATA[3], 
        AXI_IF_0_BIF_1_RDATA[2], AXI_IF_0_BIF_1_RDATA[1], 
        AXI_IF_0_BIF_1_RDATA[0]}), .B_ADDR({\rdata_cnt[8]_net_1 , 
        \rdata_cnt[7]_net_1 , \rdata_cnt[6]_net_1 , 
        \rdata_cnt[5]_net_1 , \rdata_cnt[4]_net_1 , 
        \rdata_cnt[3]_net_1 , \rdata_cnt[2]_net_1 , 
        \rdata_cnt[1]_net_1 , \rdata_cnt[0]_net_1 , GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1}), .B_WEN({
        VCC_net_1, VCC_net_1}), .A_EN(VCC_net_1), .A_DOUT_LAT(
        VCC_net_1), .A_WIDTH({VCC_net_1, VCC_net_1, GND_net_1}), 
        .A_WMODE(GND_net_1), .B_EN(VCC_net_1), .B_DOUT_LAT(VCC_net_1), 
        .B_WIDTH({VCC_net_1, VCC_net_1, GND_net_1}), .B_WMODE(
        GND_net_1), .SII_LOCK(GND_net_1));
    SLE \AHB_DATA_1[13]  (.D(\AHB_DATA_5[13]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_452_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_AHB_DATA[13]));
    SLE \w_clk_cnt[4]  (.D(\w_clk_cnt_s[4] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(w_clk_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\w_clk_cnt[4]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI63JC[50]  (.A(
        \Rdata_mem_reto[50] ), .B(\WDATA_reto[50] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[50]));
    CFG2 #( .INIT(4'h8) )  \r_loop_5[1]  (.A(N_831), .B(
        w_loop_0_sqmuxa_net_1), .Y(\r_loop_5[1]_net_1 ));
    SLE AHB_ADDR_ret_18 (.D(AXI_IF_0_AHB_ADDR[17]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[17] ));
    SLE \AWADDR_int[24]  (.D(N_1062_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WVALID_0_sqmuxa_1_0_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\AWADDR_int[24]_net_1 ));
    SLE \AWADDR_int[30]  (.D(N_1216_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WVALID_0_sqmuxa_1_0_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\AWADDR_int[30]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \AHB_DATA_5[9]  (.A(\w_clk_cnt[9]_net_1 ), 
        .B(\r_clk_cnt[9]_net_1 ), .C(ahb0_net_1), .Y(
        \AHB_DATA_5[9]_net_1 ));
    SLE \ARADDR[14]  (.D(\ARADDR_6[14] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARADDR[14]));
    SLE \w_clk_cnt[11]  (.D(\w_clk_cnt_s[11] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(w_clk_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\w_clk_cnt[11]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \AWADDR_int_RNO[8]  (.A(
        un8_AWADDR_int_1_cry_1_S), .B(wburst_cnt), .Y(N_1018_i_0));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNIB6HC[37]  (.A(
        \Rdata_mem_reto[37] ), .B(\WDATA_reto[37] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[37]));
    ARI1 #( .INIT(20'h4AA00) )  \WDATA_int_cry[1]  (.A(VCC_net_1), .B(
        \WDATA_int[1]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        WDATA_int_s_554_FCO), .S(\WDATA_int_s[1] ), .Y(), .FCO(
        \WDATA_int_cry[1]_net_1 ));
    SLE AHB_ADDR_ret_26 (.D(AXI_IF_0_AHB_ADDR[25]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[25] ));
    CFG4 #( .INIT(16'hFE01) )  un7_wt_1_cry_0_557 (.A(
        CMD_Decode_0_w_xfer_size[7]), .B(CMD_Decode_0_w_xfer_size[6]), 
        .C(un2_wt_1_c2_net_1), .D(CMD_Decode_0_w_xfer_size[8]), .Y(
        un7_wt_1_8_0));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI83HC[34]  (.A(
        \Rdata_mem_reto[34] ), .B(\WDATA_reto[34] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[34]));
    SLE \w_clk_cnt[9]  (.D(\w_clk_cnt_s[9] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(w_clk_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\w_clk_cnt[9]_net_1 ));
    SLE \ARADDR[12]  (.D(\ARADDR_6[12] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARADDR[12]));
    SLE \WDATA_ret[16]  (.D(\Rdata_mem_reto[16] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[16] ));
    SLE \rt_state[0]  (.D(N_794_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rt_state[0]_net_1 ));
    ARI1 #( .INIT(20'h5AA55) )  un4_rt_1_cry_6 (.A(un4_rt_1_6), .B(
        \rburst_cnt[6]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un4_rt_1_cry_5_net_1), .S(), .Y(), .FCO(un4_rt_1_cry_6_net_1));
    ARI1 #( .INIT(20'h4AA00) )  \r_clk_cnt_cry[5]  (.A(VCC_net_1), .B(
        \r_clk_cnt[5]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \r_clk_cnt_cry[4]_net_1 ), .S(\r_clk_cnt_s[5] ), .Y(), .FCO(
        \r_clk_cnt_cry[5]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  \rburst_cnt_cry[7]  (.A(VCC_net_1), .B(
        rburst_cnt), .C(\rburst_cnt[7]_net_1 ), .D(GND_net_1), .FCI(
        \rburst_cnt_cry[6]_net_1 ), .S(\rburst_cnt_s[7] ), .Y(), .FCO(
        \rburst_cnt_cry[7]_net_1 ));
    SLE \WDATA_ret[59]  (.D(\Rdata_mem_reto[59] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[59] ));
    ARI1 #( .INIT(20'h5CCAA) )  un7_wt_1_cry_8 (.A(VCC_net_1), .B(
        un7_wt_1_8_0), .C(un7_wt_1_axb_8_i_0), .D(GND_net_1), .FCI(
        un7_wt_1_cry_7_net_1), .S(), .Y(), .FCO(un7_wt_1_cry_8_net_1));
    ARI1 #( .INIT(20'h48800) )  AHB_ADDR_6_cry_6 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[6] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_5_net_1), .S(
        AXI_IF_0_AHB_ADDR[6]), .Y(), .FCO(AHB_ADDR_6_cry_6_net_1));
    SLE \rburst_cnt[8]  (.D(\rburst_cnt_s[8]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(rburst_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rburst_cnt[8]_net_1 ));
    CFG2 #( .INIT(4'h2) )  AWADDR_int_6_19_344_a2 (.A(wburst_cnt), .B(
        \AWADDR_int[7]_net_1 ), .Y(N_1029));
    SLE \AWADDR_int[9]  (.D(N_1007_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WVALID_0_sqmuxa_1_0_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\AWADDR_int[9]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un8_AWADDR_int_1_cry_22 (.A(VCC_net_1), 
        .B(\AWADDR_int[29]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un8_AWADDR_int_1_cry_21_net_1), .S(un8_AWADDR_int_1_cry_22_S), 
        .Y(), .FCO(un8_AWADDR_int_1_cry_22_net_1));
    SLE \AHB_DATA_1[0]  (.D(\AHB_DATA_5[0]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_452_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_AHB_DATA[0]));
    CFG4 #( .INIT(16'h0800) )  \un1_w_loop_1.CO1  (.A(
        \w_loop[1]_net_1 ), .B(\w_loop[0]_net_1 ), .C(
        \ahb_state[0]_net_1 ), .D(ahb0_net_1), .Y(CO1));
    SLE \AWADDR_1[31]  (.D(\AWADDR_int[31]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(burst_cnt_0_sqmuxa_1)
        , .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWADDR[31]));
    CFG4 #( .INIT(16'h0200) )  \axi_fsm_current_state_ns_1_0_.m6_0_a2  
        (.A(w_start), .B(\axi_fsm_current_state[0]_net_1 ), .C(
        wburst_cnt), .D(un4_write_idle1), .Y(AWBURST_0_sqmuxa));
    SLE WVALID_ext_ret_1 (.D(AXI_IF_0_BIF_1_WREADY), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK_i_0), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_WREADY_reto));
    SLE \wburst_cnt[2]  (.D(\wburst_cntoi[2] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(wburst_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\wburst_cnt[2]_net_1 ));
    ARI1 #( .INIT(20'h5AA55) )  un3_rt_0_cry_5 (.A(
        CMD_Decode_0_r_xfer_size[5]), .B(\rburst_cnt[5]_net_1 ), .C(
        GND_net_1), .D(GND_net_1), .FCI(un3_rt_0_cry_4_net_1), .S(), 
        .Y(), .FCO(un3_rt_0_cry_5_net_1));
    CFG2 #( .INIT(4'h2) )  r_xfer_size_1_ret_4_RNO (.A(un1_rt_1_c4_ioi)
        , .B(CMD_Decode_0_r_xfer_sizeoi[8]), .Y(un4_rt_1_9_reti));
    ARI1 #( .INIT(20'h4AA00) )  un8_AWADDR_int_1_cry_11 (.A(VCC_net_1), 
        .B(\AWADDR_int[18]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un8_AWADDR_int_1_cry_10_net_1), .S(un8_AWADDR_int_1_cry_11_S), 
        .Y(), .FCO(un8_AWADDR_int_1_cry_11_net_1));
    CFG4 #( .INIT(16'hFE00) )  \r_clk_cnt_lm_0[4]  (.A(
        \rt_state[0]_net_1 ), .B(\rt_state[1]_net_1 ), .C(rt_0_net_1), 
        .D(\r_clk_cnt_s[4] ), .Y(\r_clk_cnt_lm[4] ));
    SLE RREADY (.D(AXI_IF_0_BIF_1_RLAST_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_RREADY_0_sqmuxa_0_net_1), .ALn(MDDR_TA_0_INIT_DONE), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(AXI_IF_0_BIF_1_RREADY));
    SLE \WDATA_ret[22]  (.D(\Rdata_mem_reto[22] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[22] ));
    SLE \r_clk_cnt[7]  (.D(\r_clk_cnt_lm[7] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_314_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\r_clk_cnt[7]_net_1 ));
    CFG4 #( .INIT(16'hB4F0) )  \un1_r_loop_1.SUM[1]  (.A(ahb0_net_1), 
        .B(r_loop_1_sqmuxa_0_a2_0_net_1), .C(\r_loop[1]_net_1 ), .D(
        \r_loop[0]_net_1 ), .Y(N_831));
    ARI1 #( .INIT(20'h48800) )  \rburst_cnt_cry[4]  (.A(VCC_net_1), .B(
        rburst_cnt), .C(\rburst_cnt[4]_net_1 ), .D(GND_net_1), .FCI(
        \rburst_cnt_cry[3]_net_1 ), .S(\rburst_cnt_s[4] ), .Y(), .FCO(
        \rburst_cnt_cry[4]_net_1 ));
    SLE AWVALID (.D(\axi_fsm_current_state_i_0[0] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_24), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AWVALID_net_1));
    CFG2 #( .INIT(4'h8) )  \AWADDR_int_RNO[23]  (.A(
        un8_AWADDR_int_1_cry_16_S), .B(wburst_cnt), .Y(N_1073_i_0));
    ARI1 #( .INIT(20'h6DD00) )  un4_rt_1_cry_10 (.A(VCC_net_1), .B(
        un1_rt_1_c4_i), .C(CMD_Decode_0_r_xfer_size[8]), .D(GND_net_1), 
        .FCI(un4_rt_1_cry_9_net_1), .S(), .Y(), .FCO(
        un4_rt_1_cry_10_net_1));
    ARI1 #( .INIT(20'h4FE00) )  \w_clk_cnt_cry_cy[0]  (.A(VCC_net_1), 
        .B(wt_0), .C(\wt_state[0]_net_1 ), .D(\wt_state[1]_net_1 ), 
        .FCI(VCC_net_1), .S(), .Y(\w_clk_cnt_cry_cy_Y[0] ), .FCO(
        w_clk_cnt_cry_cy));
    CFG4 #( .INIT(16'h7BDE) )  un5_write_idle2_NE_4 (.A(
        \wburst_cnt[8]_net_1 ), .B(\wburst_cnt[6]_net_1 ), .C(
        CMD_Decode_0_w_xfer_size[8]), .D(CMD_Decode_0_w_xfer_size[6]), 
        .Y(un5_write_idle2_NE_4_net_1));
    SLE r_xfer_size_1_ret (.D(un1_rt_1_c4_ioi), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(GND_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(un1_rt_1_c4_i));
    ARI1 #( .INIT(20'h48800) )  ARADDR_6_cry_27 (.A(VCC_net_1), .B(
        \axi_fsm_read_state_ns[0] ), .C(AXI_IF_0_BIF_1_ARADDR[27]), .D(
        GND_net_1), .FCI(ARADDR_6_cry_26_net_1), .S(\ARADDR_6[27] ), 
        .Y(), .FCO(ARADDR_6_cry_27_net_1));
    ARI1 #( .INIT(20'h48800) )  ARADDR_6_cry_8 (.A(VCC_net_1), .B(
        \axi_fsm_read_state_ns[0] ), .C(AXI_IF_0_BIF_1_ARADDR[8]), .D(
        GND_net_1), .FCI(ARADDR_6_cry_7), .S(\ARADDR_6[8] ), .Y(), 
        .FCO(ARADDR_6_cry_8_net_1));
    ARI1 #( .INIT(20'h48800) )  \rburst_cnt_cry[1]  (.A(VCC_net_1), .B(
        rburst_cnt), .C(\rburst_cnt[1]_net_1 ), .D(GND_net_1), .FCI(
        \rburst_cnt_cry[0]_net_1 ), .S(\rburst_cntoi[1] ), .Y(), .FCO(
        \rburst_cnt_cry[1]_net_1 ));
    SLE \AWSIZE_1[0]  (.D(VCC_net_1), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(AWBURST_0_sqmuxa), 
        .ALn(MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWSIZE[1]));
    SLE \ARADDR[21]  (.D(\ARADDR_6[21] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARADDR[21]));
    SLE AHB_ADDR_ret (.D(N_771), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(N_771_reto));
    ARI1 #( .INIT(20'h48800) )  AHB_ADDR_6_cry_10 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[10] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_9_net_1), .S(
        AXI_IF_0_AHB_ADDR[10]), .Y(), .FCO(AHB_ADDR_6_cry_10_net_1));
    CFG4 #( .INIT(16'hFE00) )  \r_clk_cnt_lm_0[10]  (.A(
        \rt_state[0]_net_1 ), .B(\rt_state[1]_net_1 ), .C(rt_0_net_1), 
        .D(\r_clk_cnt_s[10] ), .Y(\r_clk_cnt_lm[10] ));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNIB7IC[46]  (.A(
        \Rdata_mem_reto[46] ), .B(\WDATA_reto[46] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[46]));
    ARI1 #( .INIT(20'h5AA55) )  un3_rt_0_cry_7 (.A(
        CMD_Decode_0_r_xfer_size[7]), .B(\rburst_cnt[7]_net_1 ), .C(
        GND_net_1), .D(GND_net_1), .FCI(un3_rt_0_cry_6_net_1), .S(), 
        .Y(), .FCO(un3_rt_0_cry_7_net_1));
    SLE \WDATA_int[8]  (.D(\WDATA_int_lm[8] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_15_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[8]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  AHB_ADDR_6_cry_24 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[24] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_23_net_1), .S(
        AXI_IF_0_AHB_ADDR[24]), .Y(), .FCO(AHB_ADDR_6_cry_24_net_1));
    SLE \WDATA_ret[55]  (.D(\Rdata_mem_reto[55] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[55] ));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNIOSQD[8]  (.A(
        \Rdata_mem_reto[8] ), .B(\WDATA_reto[8] ), .C(RVALID_li_reto), 
        .Y(AXI_IF_0_BIF_1_WDATA[8]));
    ARI1 #( .INIT(20'h48800) )  \rburst_cnt_cry[6]  (.A(VCC_net_1), .B(
        rburst_cnt), .C(\rburst_cnt[6]_net_1 ), .D(GND_net_1), .FCI(
        \rburst_cnt_cry[5]_net_1 ), .S(\rburst_cnt_s[6] ), .Y(), .FCO(
        \rburst_cnt_cry[6]_net_1 ));
    SLE \AWADDR_int[13]  (.D(N_1183_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WVALID_0_sqmuxa_1_0_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\AWADDR_int[13]_net_1 ));
    SLE r_loop_ret (.D(g0_0_2_reti), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(g0_0_2));
    ARI1 #( .INIT(20'h48800) )  AHB_ADDR_6_cry_3 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[3] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_2), .S(AXI_IF_0_AHB_ADDR[3]), 
        .Y(), .FCO(AHB_ADDR_6_cry_3_net_1));
    ARI1 #( .INIT(20'h5AA55) )  un4_rt_1_cry_8 (.A(un4_rt_1_8), .B(
        \rburst_cnt[8]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un4_rt_1_cry_7_net_1), .S(), .Y(), .FCO(un4_rt_1_cry_8_net_1));
    CFG2 #( .INIT(4'h8) )  \AWADDR_int_RNO[30]  (.A(
        un8_AWADDR_int_1_cry_23_S), .B(wburst_cnt), .Y(N_1216_i_0));
    SLE \WDATA_ret[19]  (.D(\Rdata_mem_reto[19] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[19] ));
    ARI1 #( .INIT(20'h4AA00) )  un8_AWADDR_int_1_cry_7 (.A(VCC_net_1), 
        .B(\AWADDR_int[14]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un8_AWADDR_int_1_cry_6_net_1), .S(un8_AWADDR_int_1_cry_7_S), 
        .Y(), .FCO(un8_AWADDR_int_1_cry_7_net_1));
    SLE \WDATA_ret[32]  (.D(\Rdata_mem_reto[32] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[32] ));
    SLE \ARADDR[7]  (.D(ARADDR_6_cry_7_0_Y), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARADDR[7]));
    ARI1 #( .INIT(20'h5AA55) )  read_read1_cry_15 (.A(un4_rt_1_5), .B(
        AXI_IF_0_BIF_1_ARADDR[15]), .C(GND_net_1), .D(GND_net_1), .FCI(
        read_read1_cry_14_net_1), .S(), .Y(), .FCO(
        read_read1_cry_15_net_1));
    ARI1 #( .INIT(20'h48800) )  ARADDR_6_cry_25 (.A(VCC_net_1), .B(
        \axi_fsm_read_state_ns[0] ), .C(AXI_IF_0_BIF_1_ARADDR[25]), .D(
        GND_net_1), .FCI(ARADDR_6_cry_24_net_1), .S(\ARADDR_6[25] ), 
        .Y(), .FCO(ARADDR_6_cry_25_net_1));
    CFG3 #( .INIT(8'h01) )  w_clk_cnt_1_sqmuxa_1_4 (.A(
        \wburst_cnt[2]_net_1 ), .B(\wburst_cnt[6]_net_1 ), .C(
        \wburst_cnt[3]_net_1 ), .Y(w_clk_cnt_1_sqmuxa_1_4_net_1));
    ARI1 #( .INIT(20'h4AA00) )  \WDATA_int_cry[7]  (.A(VCC_net_1), .B(
        \WDATA_int[7]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \WDATA_int_cry[6]_net_1 ), .S(\WDATA_int_s[7] ), .Y(), .FCO(
        \WDATA_int_cry[7]_net_1 ));
    SLE \WDATA_ret[20]  (.D(\Rdata_mem_reto[20] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[20] ));
    SLE \AWADDR_1[29]  (.D(\AWADDR_int[29]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(burst_cnt_0_sqmuxa_1)
        , .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWADDR[29]));
    ARI1 #( .INIT(20'h48800) )  ARADDR_6_cry_10 (.A(VCC_net_1), .B(
        \axi_fsm_read_state_ns[0] ), .C(AXI_IF_0_BIF_1_ARADDR[10]), .D(
        GND_net_1), .FCI(ARADDR_6_cry_9_net_1), .S(\ARADDR_6[10] ), .Y(
        ), .FCO(ARADDR_6_cry_10_net_1));
    SLE \AHB_DATA_1[3]  (.D(\AHB_DATA_5[3]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_452_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_AHB_DATA[3]));
    ARI1 #( .INIT(20'h4AA00) )  un8_AWADDR_int_1_cry_15 (.A(VCC_net_1), 
        .B(\AWADDR_int[22]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un8_AWADDR_int_1_cry_14_net_1), .S(un8_AWADDR_int_1_cry_15_S), 
        .Y(), .FCO(un8_AWADDR_int_1_cry_15_net_1));
    SLE \ARADDR[25]  (.D(\ARADDR_6[25] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARADDR[25]));
    ARI1 #( .INIT(20'h48800) )  ARADDR_6_s_31 (.A(VCC_net_1), .B(
        \axi_fsm_read_state_ns[0] ), .C(AXI_IF_0_BIF_1_ARADDR[31]), .D(
        GND_net_1), .FCI(ARADDR_6_cry_30_net_1), .S(\ARADDR_6[31] ), 
        .Y(), .FCO());
    CFG4 #( .INIT(16'h0001) )  un1_rt_1_c4_a0 (.A(
        CMD_Decode_0_r_xfer_sizeoi[6]), .B(
        CMD_Decode_0_r_xfer_sizeoi[7]), .C(
        CMD_Decode_0_r_xfer_sizeoi[5]), .D(
        CMD_Decode_0_r_xfer_sizeoi[4]), .Y(un1_rt_1_c4_ioi));
    ARI1 #( .INIT(20'h48800) )  \wburst_cnt_s[8]  (.A(VCC_net_1), .B(
        wburst_cnt), .C(\wburst_cnt[8]_net_1 ), .D(GND_net_1), .FCI(
        \wburst_cnt_cry[7]_net_1 ), .S(\wburst_cnt_s[8]_net_1 ), .Y(), 
        .FCO());
    CFG4 #( .INIT(16'hAEEE) )  \axi_fsm_read_state_RNISI8B4[0]  (.A(
        ARBURST_0_sqmuxa), .B(\axi_fsm_read_state[0]_net_1 ), .C(
        AXI_IF_0_BIF_1_ARREADY), .D(N_222), .Y(
        \axi_fsm_read_state_ns[0] ));
    CFG2 #( .INIT(4'h8) )  \AWADDR_int_RNO[17]  (.A(
        un8_AWADDR_int_1_cry_10_S), .B(wburst_cnt), .Y(N_1139_i_0));
    CFG2 #( .INIT(4'h8) )  \AWADDR_int_RNO[16]  (.A(
        un8_AWADDR_int_1_cry_9_S), .B(wburst_cnt), .Y(N_1150_i_0));
    ARI1 #( .INIT(20'h48800) )  ARADDR_6_cry_14 (.A(VCC_net_1), .B(
        \axi_fsm_read_state_ns[0] ), .C(AXI_IF_0_BIF_1_ARADDR[14]), .D(
        GND_net_1), .FCI(ARADDR_6_cry_13_net_1), .S(\ARADDR_6[14] ), 
        .Y(), .FCO(ARADDR_6_cry_14_net_1));
    CFG3 #( .INIT(8'h04) )  \r_loop_RNIQBJG[3]  (.A(
        \axi_fsm_read_state[0]_net_1 ), .B(r_start), .C(
        \r_loop[3]_net_1 ), .Y(ARBURST_0_sqmuxa));
    CFG3 #( .INIT(8'h60) )  \r_loop_5[2]  (.A(CO1_0), .B(
        \r_loop[2]_net_1 ), .C(w_loop_0_sqmuxa_net_1), .Y(
        \r_loop_5[2]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \r_clk_cnt_s[13]  (.A(VCC_net_1), .B(
        \r_clk_cnt[13]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \r_clk_cnt_cry[12]_net_1 ), .S(\r_clk_cnt_s[13]_net_1 ), .Y(), 
        .FCO());
    CFG3 #( .INIT(8'hAC) )  \AHB_DATA_5[6]  (.A(\w_clk_cnt[6]_net_1 ), 
        .B(\r_clk_cnt[6]_net_1 ), .C(ahb0_net_1), .Y(
        \AHB_DATA_5[6]_net_1 ));
    CFG3 #( .INIT(8'hBA) )  un1_ARBURST_0_sqmuxa_0 (.A(
        ARBURST_0_sqmuxa), .B(read_read1), .C(
        un1_ARBURST_0_sqmuxa_0_a3_0_0), .Y(un1_ARBURST_0_sqmuxa));
    SLE AHB_ADDR_ret_16 (.D(AXI_IF_0_AHB_ADDR[15]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[15] ));
    ARI1 #( .INIT(20'h48800) )  \w_clk_cnt_cry[10]  (.A(VCC_net_1), .B(
        \w_clk_cnt_cry_cy_Y[0] ), .C(\w_clk_cnt[10]_net_1 ), .D(
        GND_net_1), .FCI(\w_clk_cnt_cry[9]_net_1 ), .S(
        \w_clk_cnt_s[10] ), .Y(), .FCO(\w_clk_cnt_cry[10]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un8_AWADDR_int_1_cry_5 (.A(VCC_net_1), 
        .B(\AWADDR_int[12]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un8_AWADDR_int_1_cry_4_net_1), .S(un8_AWADDR_int_1_cry_5_S), 
        .Y(), .FCO(un8_AWADDR_int_1_cry_5_net_1));
    SLE \AWADDR_int[28]  (.D(N_1238_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WVALID_0_sqmuxa_1_0_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\AWADDR_int[28]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNID8HC[39]  (.A(
        \Rdata_mem_reto[39] ), .B(\WDATA_reto[39] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[39]));
    ARI1 #( .INIT(20'h4AA00) )  un8_AWADDR_int_1_cry_3 (.A(VCC_net_1), 
        .B(\AWADDR_int[10]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un8_AWADDR_int_1_cry_2_net_1), .S(un8_AWADDR_int_1_cry_3_S), 
        .Y(), .FCO(un8_AWADDR_int_1_cry_3_net_1));
    SLE \ARADDR[13]  (.D(\ARADDR_6[13] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARADDR[13]));
    ARI1 #( .INIT(20'h4AA00) )  un8_AWADDR_int_1_cry_19 (.A(VCC_net_1), 
        .B(\AWADDR_int[26]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un8_AWADDR_int_1_cry_18_net_1), .S(un8_AWADDR_int_1_cry_19_S), 
        .Y(), .FCO(un8_AWADDR_int_1_cry_19_net_1));
    ARI1 #( .INIT(20'h4DD00) )  AHB_ADDR_6_cry_15 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[15] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_14_net_1), .S(
        AXI_IF_0_AHB_ADDR[15]), .Y(), .FCO(AHB_ADDR_6_cry_15_net_1));
    SLE \WDATA_ret[27]  (.D(\Rdata_mem_reto[27] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[27] ));
    SLE \w_clk_cnt[3]  (.D(\w_clk_cnt_s[3] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(w_clk_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\w_clk_cnt[3]_net_1 ));
    ARI1 #( .INIT(20'h5AA55) )  un3_rt_0_cry_4 (.A(
        CMD_Decode_0_r_xfer_size[4]), .B(\rburst_cnt[4]_net_1 ), .C(
        GND_net_1), .D(GND_net_1), .FCI(GND_net_1), .S(), .Y(), .FCO(
        un3_rt_0_cry_4_net_1));
    SLE \WDATA_ret[30]  (.D(\Rdata_mem_reto[30] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[30] ));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI95IC[44]  (.A(
        \Rdata_mem_reto[44] ), .B(\WDATA_reto[44] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[44]));
    ARI1 #( .INIT(20'h4AA00) )  \r_clk_cnt_cry[8]  (.A(VCC_net_1), .B(
        \r_clk_cnt[8]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \r_clk_cnt_cry[7]_net_1 ), .S(\r_clk_cnt_s[8] ), .Y(), .FCO(
        \r_clk_cnt_cry[8]_net_1 ));
    SLE \WDATA_ret[15]  (.D(\Rdata_mem_reto[15] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[15] ));
    ARI1 #( .INIT(20'h4AA00) )  un8_AWADDR_int_1_s_1_556 (.A(VCC_net_1)
        , .B(\AWADDR_int[7]_net_1 ), .C(GND_net_1), .D(GND_net_1), 
        .FCI(VCC_net_1), .S(), .Y(), .FCO(un8_AWADDR_int_1_s_1_556_FCO)
        );
    CFG3 #( .INIT(8'hAC) )  \AHB_DATA_5[11]  (.A(\w_clk_cnt[11]_net_1 )
        , .B(\r_clk_cnt[11]_net_1 ), .C(ahb0_net_1), .Y(
        \AHB_DATA_5[11]_net_1 ));
    SLE \w_clk_cnt[12]  (.D(\w_clk_cnt_s[12] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(w_clk_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\w_clk_cnt[12]_net_1 ));
    CFG2 #( .INIT(4'hD) )  WRITE_AHB_RNO_0 (.A(N_771), .B(
        \ahb_state[0]_net_1 ), .Y(N_458_i_0));
    SLE \WDATA_ret[24]  (.D(\Rdata_mem_reto[24] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[24] ));
    CFG4 #( .INIT(16'hFE00) )  \r_clk_cnt_lm_0[6]  (.A(
        \rt_state[0]_net_1 ), .B(\rt_state[1]_net_1 ), .C(rt_0_net_1), 
        .D(\r_clk_cnt_s[6] ), .Y(\r_clk_cnt_lm[6] ));
    ARI1 #( .INIT(20'h45500) )  read_read1_cry_23 (.A(VCC_net_1), .B(
        AXI_IF_0_BIF_1_ARADDR[23]), .C(GND_net_1), .D(GND_net_1), .FCI(
        read_read1_cry_22_net_1), .S(), .Y(), .FCO(
        read_read1_cry_23_net_1));
    SLE \AWADDR_int[7]  (.D(N_1029), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WVALID_0_sqmuxa_1_0_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\AWADDR_int[7]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un8_AWADDR_int_1_s_24 (.A(VCC_net_1), 
        .B(\AWADDR_int[31]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un8_AWADDR_int_1_cry_23_net_1), .S(un8_AWADDR_int_1_s_24_S), 
        .Y(), .FCO());
    SLE \WDATA_ret[48]  (.D(\Rdata_mem_reto[48] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[48] ));
    SLE \rburst_cnt[5]  (.D(\rburst_cnt_s[5] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(rburst_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rburst_cnt[5]_net_1 ));
    SLE \w_loop[0]  (.D(\w_loop_5[0]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\w_loop[0]_net_1 ));
    SLE WRITE_AHB (.D(\ahb_state_i_0[0] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_458_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_WRITE_AHB));
    CFG4 #( .INIT(16'hFE00) )  \r_clk_cnt_lm_0[8]  (.A(
        \rt_state[0]_net_1 ), .B(\rt_state[1]_net_1 ), .C(rt_0_net_1), 
        .D(\r_clk_cnt_s[8] ), .Y(\r_clk_cnt_lm[8] ));
    CFG2 #( .INIT(4'h8) )  \w_loop_5[1]  (.A(N_825), .B(
        w_loop_0_sqmuxa_net_1), .Y(\w_loop_5[1]_net_1 ));
    CFG4 #( .INIT(16'h1000) )  w_clk_cnt_1_sqmuxa_1 (.A(
        \wt_state[0]_net_1 ), .B(\wt_state[1]_net_1 ), .C(
        w_clk_cnt_1_sqmuxa_1_8_net_1), .D(w_clk_cnt_1_sqmuxa_1_4_net_1)
        , .Y(w_clk_cnt_1_sqmuxa_1_net_1));
    ARI1 #( .INIT(20'h48800) )  AHB_ADDR_6_cry_9 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[9] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_8_net_1), .S(
        AXI_IF_0_AHB_ADDR[9]), .Y(), .FCO(AHB_ADDR_6_cry_9_net_1));
    SLE \AWADDR_1[28]  (.D(\AWADDR_int[28]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(burst_cnt_0_sqmuxa_1)
        , .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWADDR[28]));
    CFG4 #( .INIT(16'h2A3F) )  rt_state13_RNIKKMI (.A(
        un4_rt_1_cry_10_net_1), .B(rt_state13_net_1), .C(
        \rt_state[1]_net_1 ), .D(\rt_state[0]_net_1 ), .Y(N_314_i_0));
    ARI1 #( .INIT(20'h4AA00) )  WDATA_int_s_554 (.A(VCC_net_1), .B(
        \WDATA_int[0]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        VCC_net_1), .S(), .Y(), .FCO(WDATA_int_s_554_FCO));
    CFG2 #( .INIT(4'h9) )  un1_rt_1_axbxc1 (.A(
        CMD_Decode_0_r_xfer_sizeoi[5]), .B(
        CMD_Decode_0_r_xfer_sizeoi[4]), .Y(un4_rt_1_5_reti));
    SLE \WDATA_ret[37]  (.D(\Rdata_mem_reto[37] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[37] ));
    ARI1 #( .INIT(20'h45500) )  read_read1_cry_29 (.A(VCC_net_1), .B(
        AXI_IF_0_BIF_1_ARADDR[29]), .C(GND_net_1), .D(GND_net_1), .FCI(
        read_read1_cry_28_net_1), .S(), .Y(), .FCO(
        read_read1_cry_29_net_1));
    ARI1 #( .INIT(20'h48800) )  ARADDR_6_cry_9 (.A(VCC_net_1), .B(
        \axi_fsm_read_state_ns[0] ), .C(AXI_IF_0_BIF_1_ARADDR[9]), .D(
        GND_net_1), .FCI(ARADDR_6_cry_8_net_1), .S(\ARADDR_6[9] ), .Y()
        , .FCO(ARADDR_6_cry_9_net_1));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI72HC[33]  (.A(
        \Rdata_mem_reto[33] ), .B(\WDATA_reto[33] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[33]));
    SLE \AWADDR_1[20]  (.D(\AWADDR_int[20]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(burst_cnt_0_sqmuxa_1)
        , .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWADDR[20]));
    SLE AHB_ADDR_ret_20 (.D(AXI_IF_0_AHB_ADDR[19]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[19] ));
    SLE \WDATA_int[4]  (.D(\WDATA_int_lm[4] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_15_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[4]_net_1 ));
    ARI1 #( .INIT(20'h5CCAA) )  un7_wt_1_cry_7 (.A(VCC_net_1), .B(
        un7_wt_1_7_0), .C(un7_wt_1_axb_7_i_0), .D(GND_net_1), .FCI(
        un7_wt_1_cry_6_net_1), .S(), .Y(), .FCO(un7_wt_1_cry_7_net_1));
    SLE HADDR_ret_5 (.D(AXI_IF_0_AHB_ADDR[27]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_AHB_ADDR_reto_0_25));
    CFG1 #( .INIT(2'h1) )  \axi_fsm_current_state_RNIUEOC[0]  (.A(
        \axi_fsm_current_state[0]_net_1 ), .Y(
        \axi_fsm_current_state_i_0[0] ));
    ARI1 #( .INIT(20'h4AA00) )  \rdata_cnt_s[8]  (.A(VCC_net_1), .B(
        \rdata_cnt[8]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \rdata_cnt_cry[7]_net_1 ), .S(\rdata_cnt_s[8]_net_1 ), .Y(), 
        .FCO());
    ARI1 #( .INIT(20'h45500) )  read_read1_cry_26 (.A(VCC_net_1), .B(
        AXI_IF_0_BIF_1_ARADDR[26]), .C(GND_net_1), .D(GND_net_1), .FCI(
        read_read1_cry_25_net_1), .S(), .Y(), .FCO(
        read_read1_cry_26_net_1));
    CFG2 #( .INIT(4'h2) )  ahb0_0 (.A(w_start), .B(AHB_IF_0_AHB_BUSY), 
        .Y(ahb0_0_net_1));
    SLE \AWADDR_int[14]  (.D(N_1172_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WVALID_0_sqmuxa_1_0_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\AWADDR_int[14]_net_1 ));
    SLE \WDATA_ret[34]  (.D(\Rdata_mem_reto[34] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[34] ));
    SLE r_xfer_size_1_ret_3 (.D(un4_rt_1_8_reti), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(GND_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(un4_rt_1_8));
    ARI1 #( .INIT(20'h4AA00) )  \WDATA_int_cry[4]  (.A(VCC_net_1), .B(
        \WDATA_int[4]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \WDATA_int_cry[3]_net_1 ), .S(\WDATA_int_s[4] ), .Y(), .FCO(
        \WDATA_int_cry[4]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \r_clk_cnt_cry[10]  (.A(VCC_net_1), .B(
        \r_clk_cnt[10]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \r_clk_cnt_cry[9]_net_1 ), .S(\r_clk_cnt_s[10] ), .Y(), .FCO(
        \r_clk_cnt_cry[10]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  ARADDR_6_cry_26 (.A(VCC_net_1), .B(
        \axi_fsm_read_state_ns[0] ), .C(AXI_IF_0_BIF_1_ARADDR[26]), .D(
        GND_net_1), .FCI(ARADDR_6_cry_25_net_1), .S(\ARADDR_6[26] ), 
        .Y(), .FCO(ARADDR_6_cry_26_net_1));
    CFG3 #( .INIT(8'h10) )  \axi_fsm_current_state_RNI07A23[0]  (.A(
        \axi_fsm_current_state[0]_net_1 ), .B(wburst_cnt), .C(N_236), 
        .Y(N_244));
    ARI1 #( .INIT(20'h4AA00) )  \rdata_cnt_cry[3]  (.A(VCC_net_1), .B(
        \rdata_cnt[3]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \rdata_cnt_cry[2]_net_1 ), .S(\rdata_cnt_s[3] ), .Y(), .FCO(
        \rdata_cnt_cry[3]_net_1 ));
    SLE \w_clk_cnt[1]  (.D(\w_clk_cnt_s[1] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(w_clk_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\w_clk_cnt[1]_net_1 ));
    SLE \WDATA_ret[0]  (.D(\Rdata_mem_reto[0] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[0] ));
    CFG4 #( .INIT(16'hBFFF) )  \w_loop_RNIQ6SN1[1]  (.A(
        \w_loop[3]_net_1 ), .B(\w_loop[2]_net_1 ), .C(
        \w_loop[1]_net_1 ), .D(\w_loop[0]_net_1 ), .Y(
        WDATA_intlde_i_o2_2));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI97KC[62]  (.A(
        \Rdata_mem_reto[62] ), .B(\WDATA_reto[62] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[62]));
    CFG4 #( .INIT(16'h0002) )  w_clk_cnt_1_sqmuxa_1_8 (.A(
        w_clk_cnt_1_sqmuxa_1_5_net_1), .B(wt_0), .C(
        \wburst_cnt[7]_net_1 ), .D(\wburst_cnt[4]_net_1 ), .Y(
        w_clk_cnt_1_sqmuxa_1_8_net_1));
    CFG3 #( .INIT(8'hED) )  \burst_cnt_0_0[0]  (.A(N_231), .B(
        burst_cnt_0_sqmuxa_1), .C(\burst_cnt[0]_net_1 ), .Y(
        \burst_cnt_0_0[0]_net_1 ));
    SLE \AWADDR_1[23]  (.D(\AWADDR_int[23]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(burst_cnt_0_sqmuxa_1)
        , .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWADDR[23]));
    SLE \WDATA_ret[4]  (.D(\Rdata_mem_reto[4] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[4] ));
    ARI1 #( .INIT(20'h6AA00) )  read_read1_cry_8 (.A(VCC_net_1), .B(
        AXI_IF_0_BIF_1_ARADDR[8]), .C(GND_net_1), .D(GND_net_1), .FCI(
        read_read1_cry_7_net_1), .S(), .Y(), .FCO(
        read_read1_cry_8_net_1));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI2SEC[11]  (.A(
        \Rdata_mem_reto[11] ), .B(\WDATA_reto[11] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[11]));
    ARI1 #( .INIT(20'h48800) )  \w_clk_cnt_cry[7]  (.A(VCC_net_1), .B(
        \w_clk_cnt_cry_cy_Y[0] ), .C(\w_clk_cnt[7]_net_1 ), .D(
        GND_net_1), .FCI(\w_clk_cnt_cry[6]_net_1 ), .S(
        \w_clk_cnt_s[7] ), .Y(), .FCO(\w_clk_cnt_cry[7]_net_1 ));
    SLE \ARADDR[11]  (.D(\ARADDR_6[11] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARADDR[11]));
    CFG2 #( .INIT(4'h8) )  \AWADDR_int_RNO[11]  (.A(
        un8_AWADDR_int_1_cry_4_S), .B(wburst_cnt), .Y(N_985_i_0));
    ARI1 #( .INIT(20'h48800) )  AHB_ADDR_6_cry_18 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[18] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_17_net_1), .S(
        AXI_IF_0_AHB_ADDR[18]), .Y(), .FCO(AHB_ADDR_6_cry_18_net_1));
    ARI1 #( .INIT(20'h48800) )  ARADDR_6_cry_17 (.A(VCC_net_1), .B(
        \axi_fsm_read_state_ns[0] ), .C(AXI_IF_0_BIF_1_ARADDR[17]), .D(
        GND_net_1), .FCI(ARADDR_6_cry_16_net_1), .S(\ARADDR_6[17] ), 
        .Y(), .FCO(ARADDR_6_cry_17_net_1));
    SLE \WDATA_ret[63]  (.D(\Rdata_mem_reto[63] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[63] ));
    CFG4 #( .INIT(16'hAAA8) )  \WDATA_int_lm_0[4]  (.A(
        \WDATA_int_s[4] ), .B(N_236), .C(
        \axi_fsm_current_state[0]_net_1 ), .D(wburst_cnt), .Y(
        \WDATA_int_lm[4] ));
    CFG4 #( .INIT(16'hC840) )  un1_WSTRB_0_sqmuxa_i_i_a3 (.A(
        wburst_cnt), .B(\axi_fsm_current_state[0]_net_1 ), .C(
        AXI_IF_0_BIF_1_AWREADY), .D(AXI_IF_0_BIF_1_WREADY), .Y(
        un1_WSTRB_0_sqmuxa_i_i_a3_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un8_AWADDR_int_1_cry_12 (.A(VCC_net_1), 
        .B(\AWADDR_int[19]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un8_AWADDR_int_1_cry_11_net_1), .S(un8_AWADDR_int_1_cry_12_S), 
        .Y(), .FCO(un8_AWADDR_int_1_cry_12_net_1));
    SLE rburst_cnt_ret (.D(un3_ahb1_NE_2_reti), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(rburst_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(un3_ahb1_NE_2_net_1));
    ARI1 #( .INIT(20'h6AA00) )  un7_wt_1_cry_3 (.A(VCC_net_1), .B(
        \wburst_cnt[3]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un7_wt_1_cry_2_net_1), .S(), .Y(), .FCO(un7_wt_1_cry_3_net_1));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNID9IC[48]  (.A(
        \Rdata_mem_reto[48] ), .B(\WDATA_reto[48] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[48]));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNIIMQD[2]  (.A(
        \Rdata_mem_reto[2] ), .B(\WDATA_reto[2] ), .C(RVALID_li_reto), 
        .Y(AXI_IF_0_BIF_1_WDATA[2]));
    SLE AHB_ADDR_ret_29 (.D(AXI_IF_0_AHB_ADDR[28]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[28] ));
    SLE \WDATA_ret[3]  (.D(\Rdata_mem_reto[3] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[3] ));
    CFG3 #( .INIT(8'hAC) )  \AHB_DATA_5[8]  (.A(\w_clk_cnt[8]_net_1 ), 
        .B(\r_clk_cnt[8]_net_1 ), .C(ahb0_net_1), .Y(
        \AHB_DATA_5[8]_net_1 ));
    ARI1 #( .INIT(20'h5AA55) )  un3_rt_0_cry_8 (.A(
        CMD_Decode_0_r_xfer_size[8]), .B(\rburst_cnt[8]_net_1 ), .C(
        GND_net_1), .D(GND_net_1), .FCI(un3_rt_0_cry_7_net_1), .S(), 
        .Y(), .FCO(un3_rt_0));
    SLE \WDATA_ret[26]  (.D(\Rdata_mem_reto[26] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[26] ));
    CFG2 #( .INIT(4'h8) )  \AWADDR_int_RNO[15]  (.A(
        un8_AWADDR_int_1_cry_8_S), .B(wburst_cnt), .Y(N_1161_i_0));
    SLE \AWADDR_int[27]  (.D(N_1249_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WVALID_0_sqmuxa_1_0_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\AWADDR_int[27]_net_1 ));
    CFG4 #( .INIT(16'h04AE) )  \axi_fsm_current_state_RNINLS51[0]  (.A(
        wburst_cnt), .B(\axi_fsm_current_state[0]_net_1 ), .C(
        AXI_IF_0_BIF_1_AWREADY), .D(AXI_IF_0_BIF_1_WREADY), .Y(
        WDATA_intlde_i_0));
    CFG2 #( .INIT(4'h8) )  ARVALID_ext_2 (.A(AXI_IF_0_BIF_1_ARREADY), 
        .B(ARVALID_net_1), .Y(ARVALID_ext_2_net_1));
    SLE \rdata_cnt[5]  (.D(\rdata_cnt_s[5] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_368_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rdata_cnt[5]_net_1 ));
    SLE AHB_ADDR_ret_9 (.D(AXI_IF_0_AHB_ADDR[8]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[8] ));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI1REC[10]  (.A(
        \Rdata_mem_reto[10] ), .B(\WDATA_reto[10] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[10]));
    SLE \WDATA_int[2]  (.D(\WDATA_int_lm[2] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_15_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[2]_net_1 ));
    SLE \AWADDR_int[22]  (.D(N_1084_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WVALID_0_sqmuxa_1_0_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\AWADDR_int[22]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \AWADDR_int_RNO[27]  (.A(
        un8_AWADDR_int_1_cry_20_S), .B(wburst_cnt), .Y(N_1249_i_0));
    ARI1 #( .INIT(20'h48800) )  AHB_ADDR_6_cry_16 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[16] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_15_net_1), .S(
        AXI_IF_0_AHB_ADDR[16]), .Y(), .FCO(AHB_ADDR_6_cry_16_net_1));
    ARI1 #( .INIT(20'h5AA55) )  un4_rt_1_cry_7 (.A(un4_rt_1_7), .B(
        \rburst_cnt[7]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un4_rt_1_cry_6_net_1), .S(), .Y(), .FCO(un4_rt_1_cry_7_net_1));
    CFG2 #( .INIT(4'h8) )  \AWADDR_int_RNO[26]  (.A(
        un8_AWADDR_int_1_cry_19_S), .B(wburst_cnt), .Y(N_1040_i_0));
    CFG4 #( .INIT(16'h048C) )  \axi_fsm_current_state_ns_1_0_.m6_0_a3  
        (.A(wburst_cnt), .B(\axi_fsm_current_state[0]_net_1 ), .C(
        AXI_IF_0_BIF_1_AWREADY), .D(AXI_IF_0_BIF_1_WREADY), .Y(N_241));
    SLE \AWADDR_1[8]  (.D(\AWADDR_int[8]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(burst_cnt_0_sqmuxa_1)
        , .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWADDR[8]));
    SLE \WDATA_ret[51]  (.D(\Rdata_mem_reto[51] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[51] ));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNIDAJC[57]  (.A(
        \Rdata_mem_reto[57] ), .B(\WDATA_reto[57] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[57]));
    SLE \r_loop[0]  (.D(\r_loop_5[0]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\r_loop[0]_net_1 ));
    SLE \axi_fsm_read_state[0]  (.D(\axi_fsm_read_state_ns[0] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\axi_fsm_read_state[0]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  ARADDR_6_cry_15 (.A(VCC_net_1), .B(
        \axi_fsm_read_state_ns[0] ), .C(AXI_IF_0_BIF_1_ARADDR[15]), .D(
        GND_net_1), .FCI(ARADDR_6_cry_14_net_1), .S(\ARADDR_6[15] ), 
        .Y(), .FCO(ARADDR_6_cry_15_net_1));
    SLE \ARADDR[15]  (.D(\ARADDR_6[15] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARADDR[15]));
    CFG4 #( .INIT(16'h7BDE) )  \rburst_cnt_RNI49H21[4]  (.A(
        CMD_Decode_0_r_xfer_size[7]), .B(CMD_Decode_0_r_xfer_size[4]), 
        .C(\rburst_cnt[7]_net_1 ), .D(\rburst_cnt[4]_net_1 ), .Y(
        g0_1_1));
    ARI1 #( .INIT(20'h4AA00) )  \rdata_cnt_cry[1]  (.A(VCC_net_1), .B(
        \rdata_cnt[1]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        rdata_cnt_s_551_FCO), .S(\rdata_cnt_s[1] ), .Y(), .FCO(
        \rdata_cnt_cry[1]_net_1 ));
    CFG4 #( .INIT(16'hFE00) )  \r_clk_cnt_lm_0[11]  (.A(
        \rt_state[0]_net_1 ), .B(\rt_state[1]_net_1 ), .C(rt_0_net_1), 
        .D(\r_clk_cnt_s[11] ), .Y(\r_clk_cnt_lm[11] ));
    ARI1 #( .INIT(20'h48800) )  \w_clk_cnt_cry[9]  (.A(VCC_net_1), .B(
        \w_clk_cnt_cry_cy_Y[0] ), .C(\w_clk_cnt[9]_net_1 ), .D(
        GND_net_1), .FCI(\w_clk_cnt_cry[8]_net_1 ), .S(
        \w_clk_cnt_s[9] ), .Y(), .FCO(\w_clk_cnt_cry[9]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNIHLQD[1]  (.A(
        \Rdata_mem_reto[1] ), .B(\WDATA_reto[1] ), .C(RVALID_li_reto), 
        .Y(AXI_IF_0_BIF_1_WDATA[1]));
    ARI1 #( .INIT(20'h4AA00) )  un8_AWADDR_int_1_cry_14 (.A(VCC_net_1), 
        .B(\AWADDR_int[21]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un8_AWADDR_int_1_cry_13_net_1), .S(un8_AWADDR_int_1_cry_14_S), 
        .Y(), .FCO(un8_AWADDR_int_1_cry_14_net_1));
    SLE HADDR_ret_10 (.D(AXI_IF_0_AHB_ADDR[6]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_AHB_ADDR_reto_0_4));
    ARI1 #( .INIT(20'h4AA00) )  \rdata_cnt_cry[6]  (.A(VCC_net_1), .B(
        \rdata_cnt[6]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \rdata_cnt_cry[5]_net_1 ), .S(\rdata_cnt_s[6] ), .Y(), .FCO(
        \rdata_cnt_cry[6]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  \w_clk_cnt_cry[2]  (.A(VCC_net_1), .B(
        \w_clk_cnt_cry_cy_Y[0] ), .C(\w_clk_cnt[2]_net_1 ), .D(
        GND_net_1), .FCI(\w_clk_cnt_cry[1]_net_1 ), .S(
        \w_clk_cnt_s[2] ), .Y(), .FCO(\w_clk_cnt_cry[2]_net_1 ));
    ARI1 #( .INIT(20'h5AA55) )  un7_wt_1_cry_4 (.A(\wburst_cnt_i[4] ), 
        .B(CMD_Decode_0_w_xfer_size[4]), .C(GND_net_1), .D(GND_net_1), 
        .FCI(un7_wt_1_cry_3_net_1), .S(), .Y(), .FCO(
        un7_wt_1_cry_4_net_1));
    SLE AHB_ADDR_ret_27 (.D(AXI_IF_0_AHB_ADDR[26]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[26] ));
    CFG4 #( .INIT(16'hF0E1) )  un7_wt_1_cry_0_558 (.A(
        CMD_Decode_0_w_xfer_size[5]), .B(CMD_Decode_0_w_xfer_size[4]), 
        .C(CMD_Decode_0_w_xfer_size[7]), .D(
        CMD_Decode_0_w_xfer_size[6]), .Y(un7_wt_1_7_0));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI2TFC[20]  (.A(
        \Rdata_mem_reto[20] ), .B(\WDATA_reto[20] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[20]));
    CFG3 #( .INIT(8'hF6) )  rburst_cnt_ret_RNIE17R (.A(
        CMD_Decode_0_r_xfer_size[5]), .B(\rburst_cnt[5]_net_1 ), .C(
        un3_ahb1_NE_2_net_1), .Y(g0_1_0));
    SLE \AHB_DATA_1[5]  (.D(\AHB_DATA_5[5]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_452_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_AHB_DATA[5]));
    CFG4 #( .INIT(16'h0031) )  un1_WVALID_0_sqmuxa_i_i_a2_0_RNI6FUI5 (
        .A(N_254), .B(N_244), .C(N_31), .D(WDATA_intlde_i_0), .Y(
        N_15_i_0));
    ARI1 #( .INIT(20'h48800) )  AHB_ADDR_6_cry_13 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[13] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_12_net_1), .S(
        AXI_IF_0_AHB_ADDR[13]), .Y(), .FCO(AHB_ADDR_6_cry_13_net_1));
    CFG4 #( .INIT(16'hAAA8) )  \WDATA_int_lm_0[5]  (.A(
        \WDATA_int_s[5] ), .B(N_236), .C(
        \axi_fsm_current_state[0]_net_1 ), .D(wburst_cnt), .Y(
        \WDATA_int_lm[5] ));
    SLE \burst_cnt[2]  (.D(N_19_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), 
        .LAT(GND_net_1), .Q(\burst_cnt[2]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \AHB_DATA_5[4]  (.A(\w_clk_cnt[4]_net_1 ), 
        .B(\r_clk_cnt[4]_net_1 ), .C(ahb0_net_1), .Y(
        \AHB_DATA_5[4]_net_1 ));
    SLE \WDATA_ret[36]  (.D(\Rdata_mem_reto[36] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[36] ));
    SLE \r_clk_cnt[13]  (.D(\r_clk_cnt_lm[13] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_314_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\r_clk_cnt[13]_net_1 ));
    SLE \WDATA_int[0]  (.D(\WDATA_int_lm[0] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_15_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[0]_net_1 ));
    VCC VCC (.Y(VCC_net_1));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI94HC[35]  (.A(
        \Rdata_mem_reto[35] ), .B(\WDATA_reto[35] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[35]));
    CFG4 #( .INIT(16'hAAA8) )  \WDATA_int_lm_0[3]  (.A(
        \WDATA_int_s[3] ), .B(N_236), .C(
        \axi_fsm_current_state[0]_net_1 ), .D(wburst_cnt), .Y(
        \WDATA_int_lm[3] ));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNIA7JC[54]  (.A(
        \Rdata_mem_reto[54] ), .B(\WDATA_reto[54] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[54]));
    SLE \rburst_cnt[0]  (.D(\rburst_cntoi[0] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(rburst_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rburst_cnt[0]_net_1 ));
    CFG3 #( .INIT(8'h28) )  \w_loop_5[2]  (.A(w_loop_0_sqmuxa_net_1), 
        .B(CO1), .C(\w_loop[2]_net_1 ), .Y(\w_loop_5[2]_net_1 ));
    SLE AHB_ADDR_ret_10 (.D(AXI_IF_0_AHB_ADDR[9]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[9] ));
    SLE \WDATA_ret[43]  (.D(\Rdata_mem_reto[43] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[43] ));
    CFG2 #( .INIT(4'h8) )  \AWADDR_int_RNO[14]  (.A(
        un8_AWADDR_int_1_cry_7_S), .B(wburst_cnt), .Y(N_1172_i_0));
    SLE \WDATA_int[5]  (.D(\WDATA_int_lm[5] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_15_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[5]_net_1 ));
    SLE \rdata_cnt[3]  (.D(\rdata_cnt_s[3] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_368_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rdata_cnt[3]_net_1 ));
    ARI1 #( .INIT(20'h6AA00) )  un4_rt_1_cry_3 (.A(VCC_net_1), .B(
        \rburst_cnt[3]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un4_rt_1_cry_2_net_1), .S(), .Y(), .FCO(un4_rt_1_cry_3_net_1));
    SLE \wt_state[1]  (.D(\wt_state_ns[1] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\wt_state[1]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  AHB_ADDR_6_cry_12 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[12] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_11_net_1), .S(
        AXI_IF_0_AHB_ADDR[12]), .Y(), .FCO(AHB_ADDR_6_cry_12_net_1));
    SLE \WDATA_int[7]  (.D(\WDATA_int_lm[7] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_15_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[7]_net_1 ));
    CFG2 #( .INIT(4'h7) )  un4_write_idle1_cry_8_RNI5H1Q (.A(
        un4_write_idle1), .B(w_start), .Y(N_38));
    CFG4 #( .INIT(16'hFF04) )  un2_wt_1_c2 (.A(WS_d1[0]), .B(WS_d1[1]), 
        .C(WS_d1[2]), .D(CMD_Decode_0_w_xfer_sizeoi[4]), .Y(
        un2_wt_1_c2_reti));
    SLE \AHB_DATA_1[11]  (.D(\AHB_DATA_5[11]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_452_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_AHB_DATA[11]));
    ARI1 #( .INIT(20'h48800) )  AHB_ADDR_6_s_31 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[31] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_30_net_1), .S(
        AXI_IF_0_AHB_ADDR[31]), .Y(), .FCO());
    SLE \w_clk_cnt[6]  (.D(\w_clk_cnt_s[6] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(w_clk_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\w_clk_cnt[6]_net_1 ));
    ARI1 #( .INIT(20'h6AA00) )  un7_wt_1_cry_0 (.A(VCC_net_1), .B(
        \wburst_cnt[0]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        GND_net_1), .S(), .Y(), .FCO(un7_wt_1_cry_0_net_1));
    SLE AHB_ADDR_ret_7 (.D(AXI_IF_0_AHB_ADDR[6]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[6] ));
    SLE HADDR_ret_4 (.D(AXI_IF_0_AHB_ADDR[21]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_AHB_ADDR_reto_0_19));
    SLE \WDATA_ret[29]  (.D(\Rdata_mem_reto[29] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[29] ));
    ARI1 #( .INIT(20'h48800) )  AHB_ADDR_6_cry_7 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[7] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_6_net_1), .S(
        AXI_IF_0_AHB_ADDR[7]), .Y(), .FCO(AHB_ADDR_6_cry_7_net_1));
    SLE \AWADDR_int[8]  (.D(N_1018_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WVALID_0_sqmuxa_1_0_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\AWADDR_int[8]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un8_AWADDR_int_1_cry_6 (.A(VCC_net_1), 
        .B(\AWADDR_int[13]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un8_AWADDR_int_1_cry_5_net_1), .S(un8_AWADDR_int_1_cry_6_S), 
        .Y(), .FCO(un8_AWADDR_int_1_cry_6_net_1));
    SLE \WDATA_ret[11]  (.D(\Rdata_mem_reto[11] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[11] ));
    SLE WVALID (.D(\axi_fsm_current_state_i_0[1] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WSTRB_0_sqmuxa_i_i_a3_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(WVALID_net_1));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI71FC[16]  (.A(
        \Rdata_mem_reto[16] ), .B(\WDATA_reto[16] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[16]));
    CFG1 #( .INIT(2'h1) )  un7_wt_1_cry_5_RNO (.A(
        \wburst_cnt[5]_net_1 ), .Y(\wburst_cnt_i[5] ));
    SLE \AWADDR_int[18]  (.D(N_1128_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WVALID_0_sqmuxa_1_0_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\AWADDR_int[18]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un8_AWADDR_int_1_cry_2 (.A(VCC_net_1), 
        .B(\AWADDR_int[9]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un8_AWADDR_int_1_cry_1_net_1), .S(un8_AWADDR_int_1_cry_2_S), 
        .Y(), .FCO(un8_AWADDR_int_1_cry_2_net_1));
    ARI1 #( .INIT(20'h4AAA8) )  \w_clk_cnt_cry[0]  (.A(wt_0), .B(
        \w_clk_cnt[0]_net_1 ), .C(\wt_state[1]_net_1 ), .D(
        \wt_state[0]_net_1 ), .FCI(w_clk_cnt_cry_cy), .S(
        \w_clk_cnt_s[0] ), .Y(), .FCO(\w_clk_cnt_cry[0]_net_1 ));
    SLE AHB_ADDR_ret_25 (.D(AXI_IF_0_AHB_ADDR[24]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[24] ));
    ARI1 #( .INIT(20'h5AA55) )  un4_rt_1_cry_4 (.A(
        CMD_Decode_0_r_xfer_size_i_0[4]), .B(\rburst_cnt[4]_net_1 ), 
        .C(GND_net_1), .D(GND_net_1), .FCI(un4_rt_1_cry_3_net_1), .S(), 
        .Y(), .FCO(un4_rt_1_cry_4_net_1));
    CFG2 #( .INIT(4'h8) )  read1_idle (.A(un3_rt_0), .B(r_start), .Y(
        read1_idle_net_1));
    ARI1 #( .INIT(20'h4AA00) )  un8_AWADDR_int_1_cry_8 (.A(VCC_net_1), 
        .B(\AWADDR_int[15]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un8_AWADDR_int_1_cry_7_net_1), .S(un8_AWADDR_int_1_cry_8_S), 
        .Y(), .FCO(un8_AWADDR_int_1_cry_8_net_1));
    ARI1 #( .INIT(20'h45500) )  read_read1_cry_30 (.A(VCC_net_1), .B(
        AXI_IF_0_BIF_1_ARADDR[30]), .C(GND_net_1), .D(GND_net_1), .FCI(
        read_read1_cry_29_net_1), .S(), .Y(), .FCO(
        read_read1_cry_30_net_1));
    CFG3 #( .INIT(8'h40) )  un1_ARBURST_0_sqmuxa_0_a3_0 (.A(N_222), .B(
        AXI_IF_0_BIF_1_ARREADY), .C(\axi_fsm_read_state[0]_net_1 ), .Y(
        un1_ARBURST_0_sqmuxa_0_a3_0_0));
    ARI1 #( .INIT(20'h4AA00) )  \WDATA_int_cry[6]  (.A(VCC_net_1), .B(
        \WDATA_int[6]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \WDATA_int_cry[5]_net_1 ), .S(\WDATA_int_s[6] ), .Y(), .FCO(
        \WDATA_int_cry[6]_net_1 ));
    ARI1 #( .INIT(20'h56699) )  un7_wt_1_cry_5 (.A(\wburst_cnt_i[5] ), 
        .B(CMD_Decode_0_w_xfer_size[4]), .C(
        CMD_Decode_0_w_xfer_size[5]), .D(GND_net_1), .FCI(
        un7_wt_1_cry_4_net_1), .S(), .Y(), .FCO(un7_wt_1_cry_5_net_1));
    SLE r_xfer_size_1_ret_2 (.D(un4_rt_1_7_reti), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(GND_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(un4_rt_1_7));
    SLE \AWADDR_1[22]  (.D(\AWADDR_int[22]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(burst_cnt_0_sqmuxa_1)
        , .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWADDR[22]));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI94GC[27]  (.A(
        \Rdata_mem_reto[27] ), .B(\WDATA_reto[27] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[27]));
    SLE AHB_ADDR_ret_19 (.D(AXI_IF_0_AHB_ADDR[18]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[18] ));
    ARI1 #( .INIT(20'h48800) )  \w_clk_cnt_cry[1]  (.A(VCC_net_1), .B(
        \w_clk_cnt_cry_cy_Y[0] ), .C(\w_clk_cnt[1]_net_1 ), .D(
        GND_net_1), .FCI(\w_clk_cnt_cry[0]_net_1 ), .S(
        \w_clk_cnt_s[1] ), .Y(), .FCO(\w_clk_cnt_cry[1]_net_1 ));
    SLE \rdata_cnt[6]  (.D(\rdata_cnt_s[6] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_368_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rdata_cnt[6]_net_1 ));
    SLE \WDATA_ret[39]  (.D(\Rdata_mem_reto[39] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[39] ));
    CFG4 #( .INIT(16'hC0D1) )  un1_wt_state_0_sqmuxa_i_0 (.A(
        \wt_state[0]_net_1 ), .B(\wt_state[1]_net_1 ), .C(
        wt_state13_net_1), .D(wt_0), .Y(
        un1_wt_state_0_sqmuxa_i_0_net_1));
    CFG4 #( .INIT(16'h0010) )  ahb0 (.A(un5_write_idle2_NE_3_net_1), 
        .B(un5_write_idle2_NE_4_net_1), .C(ahb0_0_net_1), .D(
        un5_write_idle2_NE_5_net_1), .Y(ahb0_net_1));
    ARI1 #( .INIT(20'h48800) )  \w_clk_cnt_cry[8]  (.A(VCC_net_1), .B(
        \w_clk_cnt_cry_cy_Y[0] ), .C(\w_clk_cnt[8]_net_1 ), .D(
        GND_net_1), .FCI(\w_clk_cnt_cry[7]_net_1 ), .S(
        \w_clk_cnt_s[8] ), .Y(), .FCO(\w_clk_cnt_cry[8]_net_1 ));
    SLE \r_loop_state[0]  (.D(N_808_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(r_start));
    CFG2 #( .INIT(4'h8) )  \AWADDR_int_RNO[21]  (.A(
        un8_AWADDR_int_1_cry_14_S), .B(wburst_cnt), .Y(N_1095_i_0));
    ARI1 #( .INIT(20'h48800) )  ARADDR_6_cry_16 (.A(VCC_net_1), .B(
        \axi_fsm_read_state_ns[0] ), .C(AXI_IF_0_BIF_1_ARADDR[16]), .D(
        GND_net_1), .FCI(ARADDR_6_cry_15_net_1), .S(\ARADDR_6[16] ), 
        .Y(), .FCO(ARADDR_6_cry_16_net_1));
    SLE \ARADDR[27]  (.D(\ARADDR_6[27] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARADDR[27]));
    SLE \rdata_cnt[4]  (.D(\rdata_cnt_s[4] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_368_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rdata_cnt[4]_net_1 ));
    CFG4 #( .INIT(16'h7DBE) )  un5_write_idle2_NE_3 (.A(
        \wburst_cnt[5]_net_1 ), .B(\wburst_cnt[7]_net_1 ), .C(
        CMD_Decode_0_w_xfer_size[7]), .D(CMD_Decode_0_w_xfer_size[5]), 
        .Y(un5_write_idle2_NE_3_net_1));
    ARI1 #( .INIT(20'h6AA00) )  read_read1_cry_11 (.A(VCC_net_1), .B(
        AXI_IF_0_BIF_1_ARADDR[11]), .C(GND_net_1), .D(GND_net_1), .FCI(
        read_read1_cry_10_net_1), .S(), .Y(), .FCO(
        read_read1_cry_11_net_1));
    CFG4 #( .INIT(16'hFE00) )  \r_clk_cnt_lm_0[5]  (.A(
        \rt_state[0]_net_1 ), .B(\rt_state[1]_net_1 ), .C(rt_0_net_1), 
        .D(\r_clk_cnt_s[5] ), .Y(\r_clk_cnt_lm[5] ));
    ARI1 #( .INIT(20'h48800) )  \w_clk_cnt_cry[5]  (.A(VCC_net_1), .B(
        \w_clk_cnt_cry_cy_Y[0] ), .C(\w_clk_cnt[5]_net_1 ), .D(
        GND_net_1), .FCI(\w_clk_cnt_cry[4]_net_1 ), .S(
        \w_clk_cnt_s[5] ), .Y(), .FCO(\w_clk_cnt_cry[5]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI40HC[31]  (.A(
        \Rdata_mem_reto[31] ), .B(\WDATA_reto[31] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[31]));
    CFG4 #( .INIT(16'hCCC9) )  un1_rt_1_axbxc3 (.A(
        CMD_Decode_0_r_xfer_sizeoi[6]), .B(
        CMD_Decode_0_r_xfer_sizeoi[7]), .C(
        CMD_Decode_0_r_xfer_sizeoi[5]), .D(
        CMD_Decode_0_r_xfer_sizeoi[4]), .Y(un4_rt_1_7_reti));
    ARI1 #( .INIT(20'h48800) )  \w_clk_cnt_cry[4]  (.A(VCC_net_1), .B(
        \w_clk_cnt_cry_cy_Y[0] ), .C(\w_clk_cnt[4]_net_1 ), .D(
        GND_net_1), .FCI(\w_clk_cnt_cry[3]_net_1 ), .S(
        \w_clk_cnt_s[4] ), .Y(), .FCO(\w_clk_cnt_cry[4]_net_1 ));
    ARI1 #( .INIT(20'h6AA00) )  un4_rt_1_cry_0 (.A(VCC_net_1), .B(
        \rburst_cnt[0]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        GND_net_1), .S(), .Y(), .FCO(un4_rt_1_cry_0_net_1));
    ARI1 #( .INIT(20'h4AA00) )  \r_clk_cnt_cry[2]  (.A(VCC_net_1), .B(
        \r_clk_cnt[2]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \r_clk_cnt_cry[1]_net_1 ), .S(\r_clk_cnt_s[2] ), .Y(), .FCO(
        \r_clk_cnt_cry[2]_net_1 ));
    SLE \WDATA_ret[25]  (.D(\Rdata_mem_reto[25] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[25] ));
    ARI1 #( .INIT(20'h4AA00) )  wburst_cnt_s_552 (.A(VCC_net_1), .B(
        wburst_cnt), .C(GND_net_1), .D(GND_net_1), .FCI(VCC_net_1), .S(
        ), .Y(), .FCO(wburst_cnt_s_552_FCO));
    CFG4 #( .INIT(16'hAC0C) )  un1_RREADY_0_sqmuxa_0 (.A(rburst_cnt), 
        .B(\axi_fsm_read1_state[0]_net_1 ), .C(AXI_IF_0_BIF_1_RLAST), 
        .D(AXI_IF_0_BIF_1_RVALID), .Y(un1_RREADY_0_sqmuxa_0_net_1));
    CFG2 #( .INIT(4'h8) )  \AWADDR_int_RNO[12]  (.A(
        un8_AWADDR_int_1_cry_5_S), .B(wburst_cnt), .Y(N_1194_i_0));
    SLE \WDATA_ret[9]  (.D(\Rdata_mem_reto[9] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[9] ));
    CFG2 #( .INIT(4'h8) )  \AWADDR_int_RNO[25]  (.A(
        un8_AWADDR_int_1_cry_18_S), .B(wburst_cnt), .Y(N_1051_i_0));
    ARI1 #( .INIT(20'h6AA00) )  un7_wt_1_cry_2 (.A(VCC_net_1), .B(
        \wburst_cnt[2]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un7_wt_1_cry_1_net_1), .S(), .Y(), .FCO(un7_wt_1_cry_2_net_1));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI84IC[43]  (.A(
        \Rdata_mem_reto[43] ), .B(\WDATA_reto[43] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[43]));
    SLE \wburst_cnt[8]  (.D(\wburst_cnt_s[8]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(wburst_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\wburst_cnt[8]_net_1 ));
    CFG4 #( .INIT(16'hFE00) )  \r_clk_cnt_lm_0[9]  (.A(
        \rt_state[0]_net_1 ), .B(\rt_state[1]_net_1 ), .C(rt_0_net_1), 
        .D(\r_clk_cnt_s[9] ), .Y(\r_clk_cnt_lm[9] ));
    SLE \r_clk_cnt[9]  (.D(\r_clk_cnt_lm[9] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_314_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\r_clk_cnt[9]_net_1 ));
    SLE \ARADDR[20]  (.D(\ARADDR_6[20] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARADDR[20]));
    SLE AHB_ADDR_ret_17 (.D(AXI_IF_0_AHB_ADDR[16]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[16] ));
    CFG4 #( .INIT(16'hBA10) )  \axi_fsm_read1_state_ns_0[0]  (.A(
        \axi_fsm_read1_state[0]_net_1 ), .B(rburst_cnt), .C(
        read1_idle_net_1), .D(AXI_IF_0_BIF_1_RLAST), .Y(
        \axi_fsm_read1_state_ns[0] ));
    SLE \w_clk_cnt[0]  (.D(\w_clk_cnt_s[0] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(w_clk_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\w_clk_cnt[0]_net_1 ));
    ARI1 #( .INIT(20'h5AA55) )  un4_write_idle1_cry_8 (.A(
        CMD_Decode_0_w_xfer_size[8]), .B(\wburst_cnt[8]_net_1 ), .C(
        GND_net_1), .D(GND_net_1), .FCI(un4_write_idle1_cry_7_net_1), 
        .S(), .Y(), .FCO(un4_write_idle1));
    ARI1 #( .INIT(20'h5AA55) )  un3_rt_0_cry_6 (.A(
        CMD_Decode_0_r_xfer_size[6]), .B(\rburst_cnt[6]_net_1 ), .C(
        GND_net_1), .D(GND_net_1), .FCI(un3_rt_0_cry_5_net_1), .S(), 
        .Y(), .FCO(un3_rt_0_cry_6_net_1));
    CFG2 #( .INIT(4'h8) )  \AWADDR_int_RNO[10]  (.A(
        un8_AWADDR_int_1_cry_3_S), .B(wburst_cnt), .Y(N_996_i_0));
    SLE \rburst_cnt[1]  (.D(\rburst_cntoi[1] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(rburst_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rburst_cnt[1]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  AHB_ADDR_6_cry_21 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[21] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_20_net_1), .S(
        AXI_IF_0_AHB_ADDR[21]), .Y(), .FCO(AHB_ADDR_6_cry_21_net_1));
    SLE \rburst_cnt[4]  (.D(\rburst_cnt_s[4] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(rburst_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rburst_cnt[4]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \r_clk_cnt_cry[3]  (.A(VCC_net_1), .B(
        \r_clk_cnt[3]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \r_clk_cnt_cry[2]_net_1 ), .S(\r_clk_cnt_s[3] ), .Y(), .FCO(
        \r_clk_cnt_cry[3]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  \wburst_cnt_cry[2]  (.A(VCC_net_1), .B(
        wburst_cnt), .C(\wburst_cnt[2]_net_1 ), .D(GND_net_1), .FCI(
        \wburst_cnt_cry[1]_net_1 ), .S(\wburst_cntoi[2] ), .Y(), .FCO(
        \wburst_cnt_cry[2]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \rdata_cnt_cry[2]  (.A(VCC_net_1), .B(
        \rdata_cnt[2]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \rdata_cnt_cry[1]_net_1 ), .S(\rdata_cnt_s[2] ), .Y(), .FCO(
        \rdata_cnt_cry[2]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \r_clk_cnt_cry[7]  (.A(VCC_net_1), .B(
        \r_clk_cnt[7]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \r_clk_cnt_cry[6]_net_1 ), .S(\r_clk_cnt_s[7] ), .Y(), .FCO(
        \r_clk_cnt_cry[7]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \r_clk_cnt_cry[4]  (.A(VCC_net_1), .B(
        \r_clk_cnt[4]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \r_clk_cnt_cry[3]_net_1 ), .S(\r_clk_cnt_s[4] ), .Y(), .FCO(
        \r_clk_cnt_cry[4]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  un8_AWADDR_int_1_cry_20 (.A(VCC_net_1), 
        .B(\AWADDR_int[27]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un8_AWADDR_int_1_cry_19_net_1), .S(un8_AWADDR_int_1_cry_20_S), 
        .Y(), .FCO(un8_AWADDR_int_1_cry_20_net_1));
    CFG4 #( .INIT(16'h8488) )  \r_loop_5[0]  (.A(\r_loop[0]_net_1 ), 
        .B(w_loop_0_sqmuxa_net_1), .C(ahb0_net_1), .D(
        r_loop_1_sqmuxa_0_a2_0_net_1), .Y(\r_loop_5[0]_net_1 ));
    CFG1 #( .INIT(2'h1) )  un7_wt_1_cry_4_RNO (.A(
        \wburst_cnt[4]_net_1 ), .Y(\wburst_cnt_i[4] ));
    ARI1 #( .INIT(20'h5AA55) )  un4_rt_1_cry_5 (.A(un4_rt_1_5), .B(
        \rburst_cnt[5]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un4_rt_1_cry_4_net_1), .S(), .Y(), .FCO(un4_rt_1_cry_5_net_1));
    SLE \w_loop_state[0]  (.D(N_235_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(w_start));
    ARI1 #( .INIT(20'h45500) )  read_read1_cry_27 (.A(VCC_net_1), .B(
        AXI_IF_0_BIF_1_ARADDR[27]), .C(GND_net_1), .D(GND_net_1), .FCI(
        read_read1_cry_26_net_1), .S(), .Y(), .FCO(
        read_read1_cry_27_net_1));
    SLE \WDATA_ret[35]  (.D(\Rdata_mem_reto[35] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[35] ));
    CFG4 #( .INIT(16'hFE00) )  \r_clk_cnt_lm_0[7]  (.A(
        \rt_state[0]_net_1 ), .B(\rt_state[1]_net_1 ), .C(rt_0_net_1), 
        .D(\r_clk_cnt_s[7] ), .Y(\r_clk_cnt_lm[7] ));
    ARI1 #( .INIT(20'h4AA00) )  \r_clk_cnt_cry[1]  (.A(VCC_net_1), .B(
        \r_clk_cnt[1]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        r_clk_cnt_s_555_FCO), .S(\r_clk_cnt_s[1] ), .Y(), .FCO(
        \r_clk_cnt_cry[1]_net_1 ));
    SLE \AWADDR_1[19]  (.D(\AWADDR_int[19]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(burst_cnt_0_sqmuxa_1)
        , .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWADDR[19]));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNIA8KC[63]  (.A(
        \Rdata_mem_reto[63] ), .B(\WDATA_reto[63] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[63]));
    SLE \AHB_DATA_1[2]  (.D(\AHB_DATA_5[2]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_452_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_AHB_DATA[2]));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI85JC[52]  (.A(
        \Rdata_mem_reto[52] ), .B(\WDATA_reto[52] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[52]));
    CFG4 #( .INIT(16'hCCFD) )  w_clk_cnt_1_sqmuxa_1_RNIS0QO (.A(
        \wt_state[0]_net_1 ), .B(w_clk_cnt_1_sqmuxa_1_net_1), .C(
        un7_wt_1_cry_10_net_1), .D(un1_wt_state_0_sqmuxa_i_0_net_1), 
        .Y(w_clk_cnte));
    ARI1 #( .INIT(20'h48800) )  \w_clk_cnt_cry[3]  (.A(VCC_net_1), .B(
        \w_clk_cnt_cry_cy_Y[0] ), .C(\w_clk_cnt[3]_net_1 ), .D(
        GND_net_1), .FCI(\w_clk_cnt_cry[2]_net_1 ), .S(
        \w_clk_cnt_s[3] ), .Y(), .FCO(\w_clk_cnt_cry[3]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \AWADDR_int_RNO[24]  (.A(
        un8_AWADDR_int_1_cry_17_S), .B(wburst_cnt), .Y(N_1062_i_0));
    SLE \WDATA_ret[2]  (.D(\Rdata_mem_reto[2] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[2] ));
    ARI1 #( .INIT(20'h4AA00) )  un8_AWADDR_int_1_cry_17 (.A(VCC_net_1), 
        .B(\AWADDR_int[24]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un8_AWADDR_int_1_cry_16_net_1), .S(un8_AWADDR_int_1_cry_17_S), 
        .Y(), .FCO(un8_AWADDR_int_1_cry_17_net_1));
    CFG4 #( .INIT(16'h0004) )  burst_cnt_0_sqmuxa_1_1_a3 (.A(
        \axi_fsm_current_state[0]_net_1 ), .B(MDDR_TA_0_INIT_DONE), .C(
        N_38), .D(wburst_cnt), .Y(burst_cnt_0_sqmuxa_1));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNIFCJC[59]  (.A(
        \Rdata_mem_reto[59] ), .B(\WDATA_reto[59] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[59]));
    SLE \WDATA_ret[62]  (.D(\Rdata_mem_reto[62] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[62] ));
    SLE \axi_fsm_current_state[0]  (.D(\axi_fsm_current_state_ns[0] ), 
        .CLK(MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), 
        .ALn(MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \axi_fsm_current_state[0]_net_1 ));
    SLE \AWADDR_int[17]  (.D(N_1139_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WVALID_0_sqmuxa_1_0_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\AWADDR_int[17]_net_1 ));
    ARI1 #( .INIT(20'h6AA00) )  un4_rt_1_cry_2 (.A(VCC_net_1), .B(
        \rburst_cnt[2]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un4_rt_1_cry_1_net_1), .S(), .Y(), .FCO(un4_rt_1_cry_2_net_1));
    ARI1 #( .INIT(20'h6FFFE) )  un7_wt_1_cry_9 (.A(
        CMD_Decode_0_w_xfer_size[8]), .B(un2_wt_1_c2_net_1), .C(
        CMD_Decode_0_w_xfer_size[6]), .D(CMD_Decode_0_w_xfer_size[7]), 
        .FCI(un7_wt_1_cry_8_net_1), .S(), .Y(), .FCO(
        un7_wt_1_cry_9_net_1));
    SLE \wt_state[0]  (.D(\wt_state_ns[0] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\wt_state[0]_net_1 ));
    SLE \WDATA_ret[58]  (.D(\Rdata_mem_reto[58] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[58] ));
    SLE \AWADDR_int[12]  (.D(N_1194_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WVALID_0_sqmuxa_1_0_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\AWADDR_int[12]_net_1 ));
    SLE AHB_ADDR_ret_30 (.D(AXI_IF_0_AHB_ADDR[29]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[29] ));
    ARI1 #( .INIT(20'h48800) )  AHB_ADDR_6_cry_14 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[14] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_13_net_1), .S(
        AXI_IF_0_AHB_ADDR[14]), .Y(), .FCO(AHB_ADDR_6_cry_14_net_1));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI61HC[32]  (.A(
        \Rdata_mem_reto[32] ), .B(\WDATA_reto[32] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[32]));
    SLE \ARADDR[8]  (.D(\ARADDR_6[8] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARADDR[8]));
    SLE AHB_ADDR_ret_15 (.D(AXI_IF_0_AHB_ADDR[14]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[14] ));
    SLE \AWADDR_1[26]  (.D(\AWADDR_int[26]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(burst_cnt_0_sqmuxa_1)
        , .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWADDR[26]));
    ARI1 #( .INIT(20'h48800) )  AHB_ADDR_6_cry_27 (.A(VCC_net_1), .B(
        w_loop_0_sqmuxa_reto), .C(\AXI_IF_0_AHB_ADDR_reto[27] ), .D(
        GND_net_1), .FCI(AHB_ADDR_6_cry_26_net_1), .S(
        AXI_IF_0_AHB_ADDR[27]), .Y(), .FCO(AHB_ADDR_6_cry_27_net_1));
    CFG4 #( .INIT(16'h0002) )  un3_ahb2 (.A(\w_loop[3]_net_1 ), .B(
        \w_loop[2]_net_1 ), .C(\w_loop[1]_net_1 ), .D(
        \w_loop[0]_net_1 ), .Y(un3_ahb2_net_1));
    ARI1 #( .INIT(20'h48800) )  \wburst_cnt_cry[5]  (.A(VCC_net_1), .B(
        wburst_cnt), .C(\wburst_cnt[5]_net_1 ), .D(GND_net_1), .FCI(
        \wburst_cnt_cry[4]_net_1 ), .S(\wburst_cnt_s[5] ), .Y(), .FCO(
        \wburst_cnt_cry[5]_net_1 ));
    CFG4 #( .INIT(16'hAAA8) )  \WDATA_int_lm_0[6]  (.A(
        \WDATA_int_s[6] ), .B(N_236), .C(
        \axi_fsm_current_state[0]_net_1 ), .D(wburst_cnt), .Y(
        \WDATA_int_lm[6] ));
    SLE \WDATA_int[1]  (.D(\WDATA_int_lm[1] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_15_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_int[1]_net_1 ));
    SLE AHB_ADDR_ret_6 (.D(AXI_IF_0_AHB_ADDR[5]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[5] ));
    ARI1 #( .INIT(20'h45500) )  read_read1_cry_20 (.A(VCC_net_1), .B(
        AXI_IF_0_BIF_1_ARADDR[20]), .C(GND_net_1), .D(GND_net_1), .FCI(
        read_read1_cry_19_net_1), .S(), .Y(), .FCO(
        read_read1_cry_20_net_1));
    CFG2 #( .INIT(4'h8) )  rt_state13 (.A(AXI_IF_0_BIF_1_RLAST), .B(
        AXI_IF_0_BIF_1_RREADY), .Y(rt_state13_net_1));
    SLE AHB_ADDR_ret_8 (.D(AXI_IF_0_AHB_ADDR[7]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[7] ));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNI74JC[51]  (.A(
        \Rdata_mem_reto[51] ), .B(\WDATA_reto[51] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[51]));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNILPQD[5]  (.A(
        \Rdata_mem_reto[5] ), .B(\WDATA_reto[5] ), .C(RVALID_li_reto), 
        .Y(AXI_IF_0_BIF_1_WDATA[5]));
    SLE AHB_ADDR_ret_2 (.D(w_loop_0_sqmuxa_net_1), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(w_loop_0_sqmuxa_reto));
    CFG2 #( .INIT(4'hB) )  un1_rt_1_c5 (.A(CMD_Decode_0_r_xfer_size[8])
        , .B(un1_rt_1_c4_i), .Y(un1_rt_1_c5_net_1));
    SLE WVALID_ext_ret (.D(WVALID_net_1), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK_i_0), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(WVALID_reto));
    CFG4 #( .INIT(16'hA6AA) )  \un1_w_loop_1.SUM[1]  (.A(
        \w_loop[1]_net_1 ), .B(\w_loop[0]_net_1 ), .C(
        \ahb_state[0]_net_1 ), .D(ahb0_net_1), .Y(N_825));
    SLE \axi_fsm_read1_state[0]  (.D(\axi_fsm_read1_state_ns[0] ), 
        .CLK(MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), 
        .ALn(MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \axi_fsm_read1_state[0]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \AHB_DATA_5[7]  (.A(\w_clk_cnt[7]_net_1 ), 
        .B(\r_clk_cnt[7]_net_1 ), .C(ahb0_net_1), .Y(
        \AHB_DATA_5[7]_net_1 ));
    SLE r_xfer_size_1_ret_0 (.D(un4_rt_1_5_reti), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(GND_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(un4_rt_1_5));
    RAM1K18 Rdata_mem_Rdata_mem_0_1 (.A_DOUT({nc4, nc5, nc6, nc7, 
        \Rdata_mem_reto[63] , \Rdata_mem_reto[62] , 
        \Rdata_mem_reto[61] , \Rdata_mem_reto[60] , 
        \Rdata_mem_reto[59] , \Rdata_mem_reto[58] , 
        \Rdata_mem_reto[57] , \Rdata_mem_reto[56] , 
        \Rdata_mem_reto[55] , \Rdata_mem_reto[54] , 
        \Rdata_mem_reto[53] , \Rdata_mem_reto[52] , 
        \Rdata_mem_reto[51] , \Rdata_mem_reto[50] }), .B_DOUT({
        \Rdata_mem_reto[49] , \Rdata_mem_reto[48] , 
        \Rdata_mem_reto[47] , \Rdata_mem_reto[46] , 
        \Rdata_mem_reto[45] , \Rdata_mem_reto[44] , 
        \Rdata_mem_reto[43] , \Rdata_mem_reto[42] , 
        \Rdata_mem_reto[41] , \Rdata_mem_reto[40] , 
        \Rdata_mem_reto[39] , \Rdata_mem_reto[38] , 
        \Rdata_mem_reto[37] , \Rdata_mem_reto[36] , 
        \Rdata_mem_reto[35] , \Rdata_mem_reto[34] , 
        \Rdata_mem_reto[33] , \Rdata_mem_reto[32] }), .BUSY(), .A_CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .A_DOUT_CLK(VCC_net_1), 
        .A_ARST_N(VCC_net_1), .A_DOUT_EN(VCC_net_1), .A_BLK({VCC_net_1, 
        VCC_net_1, VCC_net_1}), .A_DOUT_ARST_N(VCC_net_1), 
        .A_DOUT_SRST_N(VCC_net_1), .A_DIN({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, AXI_IF_0_BIF_1_RDATA[63], 
        AXI_IF_0_BIF_1_RDATA[62], AXI_IF_0_BIF_1_RDATA[61], 
        AXI_IF_0_BIF_1_RDATA[60], AXI_IF_0_BIF_1_RDATA[59], 
        AXI_IF_0_BIF_1_RDATA[58], AXI_IF_0_BIF_1_RDATA[57], 
        AXI_IF_0_BIF_1_RDATA[56], AXI_IF_0_BIF_1_RDATA[55], 
        AXI_IF_0_BIF_1_RDATA[54], AXI_IF_0_BIF_1_RDATA[53], 
        AXI_IF_0_BIF_1_RDATA[52], AXI_IF_0_BIF_1_RDATA[51], 
        AXI_IF_0_BIF_1_RDATA[50]}), .A_ADDR({\WDATA_int[8]_net_1 , 
        \WDATA_int[7]_net_1 , \WDATA_int[6]_net_1 , 
        \WDATA_int[5]_net_1 , \WDATA_int[4]_net_1 , 
        \WDATA_int[3]_net_1 , \WDATA_int[2]_net_1 , 
        \WDATA_int[1]_net_1 , \WDATA_int[0]_net_1 , GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1}), .A_WEN({
        VCC_net_1, VCC_net_1}), .B_CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .B_DOUT_CLK(VCC_net_1), 
        .B_ARST_N(VCC_net_1), .B_DOUT_EN(VCC_net_1), .B_BLK({
        AXI_IF_0_BIF_1_RVALID, AXI_IF_0_BIF_1_RVALID, 
        AXI_IF_0_BIF_1_RVALID}), .B_DOUT_ARST_N(VCC_net_1), 
        .B_DOUT_SRST_N(VCC_net_1), .B_DIN({AXI_IF_0_BIF_1_RDATA[49], 
        AXI_IF_0_BIF_1_RDATA[48], AXI_IF_0_BIF_1_RDATA[47], 
        AXI_IF_0_BIF_1_RDATA[46], AXI_IF_0_BIF_1_RDATA[45], 
        AXI_IF_0_BIF_1_RDATA[44], AXI_IF_0_BIF_1_RDATA[43], 
        AXI_IF_0_BIF_1_RDATA[42], AXI_IF_0_BIF_1_RDATA[41], 
        AXI_IF_0_BIF_1_RDATA[40], AXI_IF_0_BIF_1_RDATA[39], 
        AXI_IF_0_BIF_1_RDATA[38], AXI_IF_0_BIF_1_RDATA[37], 
        AXI_IF_0_BIF_1_RDATA[36], AXI_IF_0_BIF_1_RDATA[35], 
        AXI_IF_0_BIF_1_RDATA[34], AXI_IF_0_BIF_1_RDATA[33], 
        AXI_IF_0_BIF_1_RDATA[32]}), .B_ADDR({\rdata_cnt[8]_net_1 , 
        \rdata_cnt[7]_net_1 , \rdata_cnt[6]_net_1 , 
        \rdata_cnt[5]_net_1 , \rdata_cnt[4]_net_1 , 
        \rdata_cnt[3]_net_1 , \rdata_cnt[2]_net_1 , 
        \rdata_cnt[1]_net_1 , \rdata_cnt[0]_net_1 , GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1}), .B_WEN({
        VCC_net_1, VCC_net_1}), .A_EN(VCC_net_1), .A_DOUT_LAT(
        VCC_net_1), .A_WIDTH({VCC_net_1, VCC_net_1, GND_net_1}), 
        .A_WMODE(GND_net_1), .B_EN(VCC_net_1), .B_DOUT_LAT(VCC_net_1), 
        .B_WIDTH({VCC_net_1, VCC_net_1, GND_net_1}), .B_WMODE(
        GND_net_1), .SII_LOCK(GND_net_1));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNIKOQD[4]  (.A(
        \Rdata_mem_reto[4] ), .B(\WDATA_reto[4] ), .C(RVALID_li_reto), 
        .Y(AXI_IF_0_BIF_1_WDATA[4]));
    ARI1 #( .INIT(20'h4AA00) )  \r_clk_cnt_cry[6]  (.A(VCC_net_1), .B(
        \r_clk_cnt[6]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \r_clk_cnt_cry[5]_net_1 ), .S(\r_clk_cnt_s[6] ), .Y(), .FCO(
        \r_clk_cnt_cry[6]_net_1 ));
    CFG4 #( .INIT(16'hF7FF) )  \burst_cnt_0_i_o2[2]  (.A(
        \burst_cnt[0]_net_1 ), .B(\burst_cnt[1]_net_1 ), .C(N_31), .D(
        MDDR_TA_0_INIT_DONE), .Y(N_34));
    SLE HADDR_ret_7 (.D(AHB_ADDR_6_cry_2_0_Y), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_AHB_ADDR_reto_0_0));
    SLE r_xfer_size_1_ret_1 (.D(un4_rt_1_6_reti), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(GND_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(un4_rt_1_6));
    SLE r_xfer_size_1_ret_4 (.D(un4_rt_1_9_reti), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(GND_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(un4_rt_1_9));
    SLE \WDATA_ret[60]  (.D(\Rdata_mem_reto[60] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[60] ));
    SLE \rburst_cnt[6]  (.D(\rburst_cnt_s[6] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(rburst_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rburst_cnt[6]_net_1 ));
    SLE \AWADDR_1[18]  (.D(\AWADDR_int[18]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(burst_cnt_0_sqmuxa_1)
        , .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWADDR[18]));
    SLE \ARADDR[26]  (.D(\ARADDR_6[26] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARADDR[26]));
    ARI1 #( .INIT(20'h6AA00) )  read_read1_cry_24 (.A(VCC_net_1), .B(
        AXI_IF_0_BIF_1_ARADDR[24]), .C(GND_net_1), .D(GND_net_1), .FCI(
        read_read1_cry_23_net_1), .S(), .Y(), .FCO(
        read_read1_cry_24_net_1));
    CFG4 #( .INIT(16'h6A00) )  \r_loop_5[3]  (.A(\r_loop[3]_net_1 ), 
        .B(\r_loop[2]_net_1 ), .C(CO1_0), .D(w_loop_0_sqmuxa_net_1), 
        .Y(\r_loop_5[3]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  ARADDR_6_cry_29 (.A(VCC_net_1), .B(
        \axi_fsm_read_state_ns[0] ), .C(AXI_IF_0_BIF_1_ARADDR[29]), .D(
        GND_net_1), .FCI(ARADDR_6_cry_28_net_1), .S(\ARADDR_6[29] ), 
        .Y(), .FCO(ARADDR_6_cry_29_net_1));
    SLE \AWADDR_1[10]  (.D(\AWADDR_int[10]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(burst_cnt_0_sqmuxa_1)
        , .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWADDR[10]));
    CFG3 #( .INIT(8'h20) )  \axi_fsm_current_state_ns_1_0_.m8_0_a3_0  
        (.A(\axi_fsm_current_state[0]_net_1 ), .B(wburst_cnt), .C(
        AXI_IF_0_BIF_1_AWREADY), .Y(N_192));
    ARI1 #( .INIT(20'h48800) )  \w_clk_cnt_cry[12]  (.A(VCC_net_1), .B(
        \w_clk_cnt_cry_cy_Y[0] ), .C(\w_clk_cnt[12]_net_1 ), .D(
        GND_net_1), .FCI(\w_clk_cnt_cry[11]_net_1 ), .S(
        \w_clk_cnt_s[12] ), .Y(), .FCO(\w_clk_cnt_cry[12]_net_1 ));
    SLE \WDATA_ret[42]  (.D(\Rdata_mem_reto[42] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[42] ));
    SLE \AWADDR_int[21]  (.D(N_1095_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WVALID_0_sqmuxa_1_0_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\AWADDR_int[21]_net_1 ));
    ARI1 #( .INIT(20'h6DD00) )  un4_rt_1_cry_9 (.A(VCC_net_1), .B(
        un1_rt_1_c4_i), .C(CMD_Decode_0_r_xfer_size[8]), .D(GND_net_1), 
        .FCI(un4_rt_1_cry_8_net_1), .S(), .Y(), .FCO(
        un4_rt_1_cry_9_net_1));
    SLE AHB_ADDR_ret_23 (.D(AXI_IF_0_AHB_ADDR[22]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\AXI_IF_0_AHB_ADDR_reto[22] ));
    SLE \w_loop[1]  (.D(\w_loop_5[1]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\w_loop[1]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \AWADDR_int_RNO[22]  (.A(
        un8_AWADDR_int_1_cry_15_S), .B(wburst_cnt), .Y(N_1084_i_0));
    SLE \ARADDR[17]  (.D(\ARADDR_6[17] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARADDR[17]));
    SLE \WDATA_ret[18]  (.D(\Rdata_mem_reto[18] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(RVALID_li_reto), 
        .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\WDATA_reto[18] ));
    SLE \r_clk_cnt[10]  (.D(\r_clk_cnt_lm[10] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_314_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\r_clk_cnt[10]_net_1 ));
    ARI1 #( .INIT(20'h45500) )  read_read1_cry_28 (.A(VCC_net_1), .B(
        AXI_IF_0_BIF_1_ARADDR[28]), .C(GND_net_1), .D(GND_net_1), .FCI(
        read_read1_cry_27_net_1), .S(), .Y(), .FCO(
        read_read1_cry_28_net_1));
    CFG3 #( .INIT(8'hAC) )  \AHB_DATA_5[10]  (.A(\w_clk_cnt[10]_net_1 )
        , .B(\r_clk_cnt[10]_net_1 ), .C(ahb0_net_1), .Y(
        \AHB_DATA_5[10]_net_1 ));
    SLE \wburst_cnt[5]  (.D(\wburst_cnt_s[5] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(wburst_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\wburst_cnt[5]_net_1 ));
    SLE \r_clk_cnt[4]  (.D(\r_clk_cnt_lm[4] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_314_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\r_clk_cnt[4]_net_1 ));
    SLE wburst_cnt_ret (.D(un5_write_idle2_NE_2_reti), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(wburst_cnte), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(un5_write_idle2_NE_2_net_1));
    SLE \AWADDR_int[25]  (.D(N_1051_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WVALID_0_sqmuxa_1_0_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\AWADDR_int[25]_net_1 ));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNIC7HC[38]  (.A(
        \Rdata_mem_reto[38] ), .B(\WDATA_reto[38] ), .C(RVALID_li_reto)
        , .Y(AXI_IF_0_BIF_1_WDATA[38]));
    CFG4 #( .INIT(16'h7BDE) )  \rburst_cnt_RNIAFH21[6]  (.A(
        \rburst_cnt[6]_net_1 ), .B(CMD_Decode_0_r_xfer_size[8]), .C(
        CMD_Decode_0_r_xfer_size[6]), .D(\rburst_cnt[8]_net_1 ), .Y(
        g0_1_2));
    SLE WLAST (.D(\axi_fsm_current_state_i_0[0] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WVALID_0_sqmuxa_i_i_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(AXI_IF_0_BIF_1_WLAST));
    SLE HADDR_ret_9 (.D(AXI_IF_0_AHB_ADDR[7]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_AHB_ADDR_reto_0_5));
    SLE HADDR_ret_1 (.D(AXI_IF_0_AHB_ADDR[25]), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_178_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_AHB_ADDR_reto_0_23));
    CFG2 #( .INIT(4'h8) )  \AWADDR_int_RNO[20]  (.A(
        un8_AWADDR_int_1_cry_13_S), .B(wburst_cnt), .Y(N_1106_i_0));
    ARI1 #( .INIT(20'h5AA55) )  un4_write_idle1_cry_5 (.A(
        CMD_Decode_0_w_xfer_size[5]), .B(\wburst_cnt[5]_net_1 ), .C(
        GND_net_1), .D(GND_net_1), .FCI(un4_write_idle1_cry_4_net_1), 
        .S(), .Y(), .FCO(un4_write_idle1_cry_5_net_1));
    CFG4 #( .INIT(16'hFFFE) )  un3_ahb1_NE_2 (.A(\rburst_cntoi[0] ), 
        .B(\rburst_cntoi[3] ), .C(\rburst_cntoi[2] ), .D(
        \rburst_cntoi[1] ), .Y(un3_ahb1_NE_2_reti));
    ARI1 #( .INIT(20'h4AA00) )  \WDATA_int_cry[2]  (.A(VCC_net_1), .B(
        \WDATA_int[2]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \WDATA_int_cry[1]_net_1 ), .S(\WDATA_int_s[2] ), .Y(), .FCO(
        \WDATA_int_cry[2]_net_1 ));
    ARI1 #( .INIT(20'h48800) )  \rburst_cnt_cry[2]  (.A(VCC_net_1), .B(
        rburst_cnt), .C(\rburst_cnt[2]_net_1 ), .D(GND_net_1), .FCI(
        \rburst_cnt_cry[1]_net_1 ), .S(\rburst_cntoi[2] ), .Y(), .FCO(
        \rburst_cnt_cry[2]_net_1 ));
    SLE \AWADDR_1[13]  (.D(\AWADDR_int[13]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(burst_cnt_0_sqmuxa_1)
        , .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWADDR[13]));
    CFG4 #( .INIT(16'h0004) )  r_loop_1_sqmuxa_0_a2_0 (.A(
        AHB_IF_0_AHB_BUSY), .B(r_start), .C(\ahb_state[0]_net_1 ), .D(
        un3_ahb1_NE), .Y(r_loop_1_sqmuxa_0_a2_0_net_1));
    SLE \AWADDR_1[25]  (.D(\AWADDR_int[25]_net_1 ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(burst_cnt_0_sqmuxa_1)
        , .ALn(VCC_net_1), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_AWADDR[25]));
    CFG4 #( .INIT(16'hFE00) )  \r_clk_cnt_lm_0[3]  (.A(
        \rt_state[0]_net_1 ), .B(\rt_state[1]_net_1 ), .C(rt_0_net_1), 
        .D(\r_clk_cnt_s[3] ), .Y(\r_clk_cnt_lm[3] ));
    SLE \ARADDR[10]  (.D(\ARADDR_6[10] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(VCC_net_1), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(AXI_IF_0_BIF_1_ARADDR[10]));
    SLE \rdata_cnt[2]  (.D(\rdata_cnt_s[2] ), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(N_368_i_0), .ALn(
        MDDR_TA_0_INIT_DONE), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(\rdata_cnt[2]_net_1 ));
    SLE \AWADDR_int[20]  (.D(N_1106_i_0), .CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .EN(
        un1_WVALID_0_sqmuxa_1_0_net_1), .ALn(MDDR_TA_0_INIT_DONE), 
        .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(
        GND_net_1), .Q(\AWADDR_int[20]_net_1 ));
    ARI1 #( .INIT(20'h6AA00) )  read_read1_cry_13 (.A(VCC_net_1), .B(
        AXI_IF_0_BIF_1_ARADDR[13]), .C(GND_net_1), .D(GND_net_1), .FCI(
        read_read1_cry_12_net_1), .S(), .Y(), .FCO(
        read_read1_cry_13_net_1));
    ARI1 #( .INIT(20'h4AA00) )  rburst_cnt_s_553 (.A(VCC_net_1), .B(
        rburst_cnt), .C(GND_net_1), .D(GND_net_1), .FCI(VCC_net_1), .S(
        ), .Y(), .FCO(rburst_cnt_s_553_FCO));
    ARI1 #( .INIT(20'h4AA00) )  un8_AWADDR_int_1_cry_1 (.A(VCC_net_1), 
        .B(\AWADDR_int[8]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        un8_AWADDR_int_1_s_1_556_FCO), .S(un8_AWADDR_int_1_cry_1_S), 
        .Y(), .FCO(un8_AWADDR_int_1_cry_1_net_1));
    CFG3 #( .INIT(8'hAC) )  \WDATA_ret_RNIGKQD[0]  (.A(
        \Rdata_mem_reto[0] ), .B(\WDATA_reto[0] ), .C(RVALID_li_reto), 
        .Y(AXI_IF_0_BIF_1_WDATA[0]));
    CFG4 #( .INIT(16'h0F0D) )  \ahb_state_ns_i_a3[0]  (.A(r_start), .B(
        AHB_IF_0_AHB_BUSY), .C(ahb0_net_1), .D(un3_ahb1_NE), .Y(N_771));
    
endmodule


module MDDR_TA_top(
       MDDR_ADDR,
       MDDR_BA,
       MDDR_DM_RDQS,
       MDDR_DQ,
       MDDR_DQS,
       MDDR_DQS_N,
       DEVRST_N,
       MDDR_DQS_TMATCH_0_IN,
       MMUART_0_RXD,
       MDDR_CAS_N,
       MDDR_CKE,
       MDDR_CLK,
       MDDR_CLK_N,
       MDDR_CS_N,
       MDDR_DQS_TMATCH_0_OUT,
       MDDR_ODT,
       MDDR_RAS_N,
       MDDR_RESET_N,
       MDDR_WE_N,
       MMUART_0_TXD,
       read_start,
       write_start
    );
output [15:0] MDDR_ADDR;
output [2:0] MDDR_BA;
inout  [1:0] MDDR_DM_RDQS;
inout  [15:0] MDDR_DQ;
inout  [1:0] MDDR_DQS;
inout  [1:0] MDDR_DQS_N;
input  DEVRST_N;
input  MDDR_DQS_TMATCH_0_IN;
input  MMUART_0_RXD;
output MDDR_CAS_N;
output MDDR_CKE;
output MDDR_CLK;
output MDDR_CLK_N;
output MDDR_CS_N;
output MDDR_DQS_TMATCH_0_OUT;
output MDDR_ODT;
output MDDR_RAS_N;
output MDDR_RESET_N;
output MDDR_WE_N;
output MMUART_0_TXD;
output read_start;
output write_start;

    wire MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK, MDDR_TA_0_INIT_DONE, 
        AXI_IF_0_WRITE_AHB, \AXI_IF_0_AHB_DATA[0] , 
        \AXI_IF_0_AHB_DATA[1] , \AXI_IF_0_AHB_DATA[2] , 
        \AXI_IF_0_AHB_DATA[3] , \AXI_IF_0_AHB_DATA[4] , 
        \AXI_IF_0_AHB_DATA[5] , \AXI_IF_0_AHB_DATA[6] , 
        \AXI_IF_0_AHB_DATA[7] , \AXI_IF_0_AHB_DATA[8] , 
        \AXI_IF_0_AHB_DATA[9] , \AXI_IF_0_AHB_DATA[10] , 
        \AXI_IF_0_AHB_DATA[11] , \AXI_IF_0_AHB_DATA[12] , 
        \AXI_IF_0_AHB_DATA[13] , \AHB_IF_0_BIF_1_HADDR[3] , 
        \AHB_IF_0_BIF_1_HADDR[4] , \AHB_IF_0_BIF_1_HADDR[5] , 
        \AHB_IF_0_BIF_1_HADDR[8] , \AHB_IF_0_BIF_1_HADDR[9] , 
        \AHB_IF_0_BIF_1_HADDR[10] , \AHB_IF_0_BIF_1_HADDR[11] , 
        \AHB_IF_0_BIF_1_HADDR[12] , \AHB_IF_0_BIF_1_HADDR[14] , 
        \AHB_IF_0_BIF_1_HADDR[15] , \AHB_IF_0_BIF_1_HADDR[16] , 
        \AHB_IF_0_BIF_1_HADDR[17] , \AHB_IF_0_BIF_1_HADDR[18] , 
        \AHB_IF_0_BIF_1_HADDR[22] , \AHB_IF_0_BIF_1_HADDR[23] , 
        \AHB_IF_0_BIF_1_HADDR[28] , \AHB_IF_0_BIF_1_HADDR[29] , 
        \AHB_IF_0_BIF_1_HADDR[30] , \AHB_IF_0_BIF_1_HADDR[31] , 
        \AHB_IF_0_BIF_1_HTRANS[1] , AHB_IF_0_BIF_1_HWRITE, 
        \AHB_IF_0_BIF_1_HWDATA[0] , \AHB_IF_0_BIF_1_HWDATA[1] , 
        \AHB_IF_0_BIF_1_HWDATA[2] , \AHB_IF_0_BIF_1_HWDATA[3] , 
        \AHB_IF_0_BIF_1_HWDATA[4] , \AHB_IF_0_BIF_1_HWDATA[5] , 
        \AHB_IF_0_BIF_1_HWDATA[6] , \AHB_IF_0_BIF_1_HWDATA[7] , 
        \AHB_IF_0_BIF_1_HWDATA[8] , \AHB_IF_0_BIF_1_HWDATA[9] , 
        \AHB_IF_0_BIF_1_HWDATA[10] , \AHB_IF_0_BIF_1_HWDATA[11] , 
        \AHB_IF_0_BIF_1_HWDATA[12] , \AHB_IF_0_BIF_1_HWDATA[13] , 
        AHB_IF_0_AHB_BUSY, \CMD_Decode_0_w_xfer_size[4] , 
        \CMD_Decode_0_w_xfer_size[5] , \CMD_Decode_0_w_xfer_size[6] , 
        \CMD_Decode_0_w_xfer_size[7] , \CMD_Decode_0_w_xfer_size[8] , 
        \CMD_Decode_0_r_xfer_size[4] , \CMD_Decode_0_r_xfer_size[5] , 
        \CMD_Decode_0_r_xfer_size[6] , \CMD_Decode_0_r_xfer_size[7] , 
        \CMD_Decode_0_r_xfer_size[8] , VCC_net_1, 
        \AXI_IF_0_BIF_1_AWADDR[7] , \AXI_IF_0_BIF_1_AWADDR[8] , 
        \AXI_IF_0_BIF_1_AWADDR[9] , \AXI_IF_0_BIF_1_AWADDR[10] , 
        \AXI_IF_0_BIF_1_AWADDR[11] , \AXI_IF_0_BIF_1_AWADDR[12] , 
        \AXI_IF_0_BIF_1_AWADDR[13] , \AXI_IF_0_BIF_1_AWADDR[14] , 
        \AXI_IF_0_BIF_1_AWADDR[15] , \AXI_IF_0_BIF_1_AWADDR[16] , 
        \AXI_IF_0_BIF_1_AWADDR[17] , \AXI_IF_0_BIF_1_AWADDR[18] , 
        \AXI_IF_0_BIF_1_AWADDR[19] , \AXI_IF_0_BIF_1_AWADDR[20] , 
        \AXI_IF_0_BIF_1_AWADDR[21] , \AXI_IF_0_BIF_1_AWADDR[22] , 
        \AXI_IF_0_BIF_1_AWADDR[23] , \AXI_IF_0_BIF_1_AWADDR[24] , 
        \AXI_IF_0_BIF_1_AWADDR[25] , \AXI_IF_0_BIF_1_AWADDR[26] , 
        \AXI_IF_0_BIF_1_AWADDR[27] , \AXI_IF_0_BIF_1_AWADDR[28] , 
        \AXI_IF_0_BIF_1_AWADDR[29] , \AXI_IF_0_BIF_1_AWADDR[30] , 
        \AXI_IF_0_BIF_1_AWADDR[31] , \AXI_IF_0_BIF_1_AWSIZE[1] , 
        AXI_IF_0_BIF_1_AWVALID, AXI_IF_0_BIF_1_AWREADY, 
        \AXI_IF_0_BIF_1_WSTRB[1] , AXI_IF_0_BIF_1_WLAST, 
        AXI_IF_0_BIF_1_WVALID, \AXI_IF_0_BIF_1_WDATA[0] , 
        \AXI_IF_0_BIF_1_WDATA[1] , \AXI_IF_0_BIF_1_WDATA[2] , 
        \AXI_IF_0_BIF_1_WDATA[3] , \AXI_IF_0_BIF_1_WDATA[4] , 
        \AXI_IF_0_BIF_1_WDATA[5] , \AXI_IF_0_BIF_1_WDATA[6] , 
        \AXI_IF_0_BIF_1_WDATA[7] , \AXI_IF_0_BIF_1_WDATA[8] , 
        \AXI_IF_0_BIF_1_WDATA[9] , \AXI_IF_0_BIF_1_WDATA[10] , 
        \AXI_IF_0_BIF_1_WDATA[11] , \AXI_IF_0_BIF_1_WDATA[12] , 
        \AXI_IF_0_BIF_1_WDATA[13] , \AXI_IF_0_BIF_1_WDATA[14] , 
        \AXI_IF_0_BIF_1_WDATA[15] , \AXI_IF_0_BIF_1_WDATA[16] , 
        \AXI_IF_0_BIF_1_WDATA[17] , \AXI_IF_0_BIF_1_WDATA[18] , 
        \AXI_IF_0_BIF_1_WDATA[19] , \AXI_IF_0_BIF_1_WDATA[20] , 
        \AXI_IF_0_BIF_1_WDATA[21] , \AXI_IF_0_BIF_1_WDATA[22] , 
        \AXI_IF_0_BIF_1_WDATA[23] , \AXI_IF_0_BIF_1_WDATA[24] , 
        \AXI_IF_0_BIF_1_WDATA[25] , \AXI_IF_0_BIF_1_WDATA[26] , 
        \AXI_IF_0_BIF_1_WDATA[27] , \AXI_IF_0_BIF_1_WDATA[28] , 
        \AXI_IF_0_BIF_1_WDATA[29] , \AXI_IF_0_BIF_1_WDATA[30] , 
        \AXI_IF_0_BIF_1_WDATA[31] , \AXI_IF_0_BIF_1_WDATA[32] , 
        \AXI_IF_0_BIF_1_WDATA[33] , \AXI_IF_0_BIF_1_WDATA[34] , 
        \AXI_IF_0_BIF_1_WDATA[35] , \AXI_IF_0_BIF_1_WDATA[36] , 
        \AXI_IF_0_BIF_1_WDATA[37] , \AXI_IF_0_BIF_1_WDATA[38] , 
        \AXI_IF_0_BIF_1_WDATA[39] , \AXI_IF_0_BIF_1_WDATA[40] , 
        \AXI_IF_0_BIF_1_WDATA[41] , \AXI_IF_0_BIF_1_WDATA[42] , 
        \AXI_IF_0_BIF_1_WDATA[43] , \AXI_IF_0_BIF_1_WDATA[44] , 
        \AXI_IF_0_BIF_1_WDATA[45] , \AXI_IF_0_BIF_1_WDATA[46] , 
        \AXI_IF_0_BIF_1_WDATA[47] , \AXI_IF_0_BIF_1_WDATA[48] , 
        \AXI_IF_0_BIF_1_WDATA[49] , \AXI_IF_0_BIF_1_WDATA[50] , 
        \AXI_IF_0_BIF_1_WDATA[51] , \AXI_IF_0_BIF_1_WDATA[52] , 
        \AXI_IF_0_BIF_1_WDATA[53] , \AXI_IF_0_BIF_1_WDATA[54] , 
        \AXI_IF_0_BIF_1_WDATA[55] , \AXI_IF_0_BIF_1_WDATA[56] , 
        \AXI_IF_0_BIF_1_WDATA[57] , \AXI_IF_0_BIF_1_WDATA[58] , 
        \AXI_IF_0_BIF_1_WDATA[59] , \AXI_IF_0_BIF_1_WDATA[60] , 
        \AXI_IF_0_BIF_1_WDATA[61] , \AXI_IF_0_BIF_1_WDATA[62] , 
        \AXI_IF_0_BIF_1_WDATA[63] , AXI_IF_0_BIF_1_WREADY, 
        \AXI_IF_0_BIF_1_ARADDR[14] , \AXI_IF_0_BIF_1_ARADDR[15] , 
        \AXI_IF_0_BIF_1_ARADDR[16] , \AXI_IF_0_BIF_1_ARADDR[17] , 
        \AXI_IF_0_BIF_1_ARADDR[18] , \AXI_IF_0_BIF_1_ARADDR[19] , 
        \AXI_IF_0_BIF_1_ARADDR[20] , \AXI_IF_0_BIF_1_ARADDR[21] , 
        \AXI_IF_0_BIF_1_ARADDR[22] , \AXI_IF_0_BIF_1_ARADDR[23] , 
        \AXI_IF_0_BIF_1_ARADDR[25] , \AXI_IF_0_BIF_1_ARADDR[26] , 
        \AXI_IF_0_BIF_1_ARADDR[27] , \AXI_IF_0_BIF_1_ARADDR[28] , 
        \AXI_IF_0_BIF_1_ARADDR[29] , \AXI_IF_0_BIF_1_ARADDR[30] , 
        \AXI_IF_0_BIF_1_ARADDR[31] , \AXI_IF_0_BIF_1_ARSIZE[1] , 
        AXI_IF_0_BIF_1_ARVALID, AXI_IF_0_BIF_1_ARREADY, 
        \AXI_IF_0_BIF_1_RDATA[0] , \AXI_IF_0_BIF_1_RDATA[1] , 
        \AXI_IF_0_BIF_1_RDATA[2] , \AXI_IF_0_BIF_1_RDATA[3] , 
        \AXI_IF_0_BIF_1_RDATA[4] , \AXI_IF_0_BIF_1_RDATA[5] , 
        \AXI_IF_0_BIF_1_RDATA[6] , \AXI_IF_0_BIF_1_RDATA[7] , 
        \AXI_IF_0_BIF_1_RDATA[8] , \AXI_IF_0_BIF_1_RDATA[9] , 
        \AXI_IF_0_BIF_1_RDATA[10] , \AXI_IF_0_BIF_1_RDATA[11] , 
        \AXI_IF_0_BIF_1_RDATA[12] , \AXI_IF_0_BIF_1_RDATA[13] , 
        \AXI_IF_0_BIF_1_RDATA[14] , \AXI_IF_0_BIF_1_RDATA[15] , 
        \AXI_IF_0_BIF_1_RDATA[16] , \AXI_IF_0_BIF_1_RDATA[17] , 
        \AXI_IF_0_BIF_1_RDATA[18] , \AXI_IF_0_BIF_1_RDATA[19] , 
        \AXI_IF_0_BIF_1_RDATA[20] , \AXI_IF_0_BIF_1_RDATA[21] , 
        \AXI_IF_0_BIF_1_RDATA[22] , \AXI_IF_0_BIF_1_RDATA[23] , 
        \AXI_IF_0_BIF_1_RDATA[24] , \AXI_IF_0_BIF_1_RDATA[25] , 
        \AXI_IF_0_BIF_1_RDATA[26] , \AXI_IF_0_BIF_1_RDATA[27] , 
        \AXI_IF_0_BIF_1_RDATA[28] , \AXI_IF_0_BIF_1_RDATA[29] , 
        \AXI_IF_0_BIF_1_RDATA[30] , \AXI_IF_0_BIF_1_RDATA[31] , 
        \AXI_IF_0_BIF_1_RDATA[32] , \AXI_IF_0_BIF_1_RDATA[33] , 
        \AXI_IF_0_BIF_1_RDATA[34] , \AXI_IF_0_BIF_1_RDATA[35] , 
        \AXI_IF_0_BIF_1_RDATA[36] , \AXI_IF_0_BIF_1_RDATA[37] , 
        \AXI_IF_0_BIF_1_RDATA[38] , \AXI_IF_0_BIF_1_RDATA[39] , 
        \AXI_IF_0_BIF_1_RDATA[40] , \AXI_IF_0_BIF_1_RDATA[41] , 
        \AXI_IF_0_BIF_1_RDATA[42] , \AXI_IF_0_BIF_1_RDATA[43] , 
        \AXI_IF_0_BIF_1_RDATA[44] , \AXI_IF_0_BIF_1_RDATA[45] , 
        \AXI_IF_0_BIF_1_RDATA[46] , \AXI_IF_0_BIF_1_RDATA[47] , 
        \AXI_IF_0_BIF_1_RDATA[48] , \AXI_IF_0_BIF_1_RDATA[49] , 
        \AXI_IF_0_BIF_1_RDATA[50] , \AXI_IF_0_BIF_1_RDATA[51] , 
        \AXI_IF_0_BIF_1_RDATA[52] , \AXI_IF_0_BIF_1_RDATA[53] , 
        \AXI_IF_0_BIF_1_RDATA[54] , \AXI_IF_0_BIF_1_RDATA[55] , 
        \AXI_IF_0_BIF_1_RDATA[56] , \AXI_IF_0_BIF_1_RDATA[57] , 
        \AXI_IF_0_BIF_1_RDATA[58] , \AXI_IF_0_BIF_1_RDATA[59] , 
        \AXI_IF_0_BIF_1_RDATA[60] , \AXI_IF_0_BIF_1_RDATA[61] , 
        \AXI_IF_0_BIF_1_RDATA[62] , \AXI_IF_0_BIF_1_RDATA[63] , 
        AXI_IF_0_BIF_1_RLAST, AXI_IF_0_BIF_1_RREADY, 
        MDDR_TA_0_GPIO_0_M2F, MDDR_TA_0_GPIO_1_M2F, 
        MDDR_TA_0_GPIO_2_M2F, MDDR_TA_0_GPIO_3_M2F, 
        MDDR_TA_0_GPIO_4_M2F, MDDR_TA_0_GPIO_5_M2F, 
        MDDR_TA_0_GPIO_6_M2F, MDDR_TA_0_GPIO_7_M2F, GND_net_1, 
        \CMD_Decode_0_r_xfer_sizeoi[4] , 
        \CMD_Decode_0_r_xfer_sizeoi[5] , 
        \CMD_Decode_0_r_xfer_sizeoi[6] , 
        \CMD_Decode_0_r_xfer_sizeoi[7] , 
        \CMD_Decode_0_r_xfer_sizeoi[8] , 
        \CMD_Decode_0_w_xfer_sizeoi[4] , \CMD_Decode_0.WS_d1[0] , 
        \CMD_Decode_0.WS_d1[1] , \CMD_Decode_0.WS_d1[2] , 
        \AXI_IF_0_AHB_ADDR[3] , \AXI_IF_0_AHB_ADDR[4] , 
        \AXI_IF_0_AHB_ADDR[5] , \AXI_IF_0_AHB_ADDR[8] , 
        \AXI_IF_0_AHB_ADDR[9] , \AXI_IF_0_AHB_ADDR[10] , 
        \AXI_IF_0_AHB_ADDR[11] , \AXI_IF_0_AHB_ADDR[12] , 
        \AXI_IF_0_AHB_ADDR[14] , \AXI_IF_0_AHB_ADDR[15] , 
        \AXI_IF_0_AHB_ADDR[16] , \AXI_IF_0_AHB_ADDR[17] , 
        \AXI_IF_0_AHB_ADDR[18] , \AXI_IF_0_AHB_ADDR[22] , 
        \AXI_IF_0_AHB_ADDR[23] , \AXI_IF_0_AHB_ADDR[28] , 
        \AXI_IF_0_AHB_ADDR[29] , \AXI_IF_0_AHB_ADDR[30] , 
        \AXI_IF_0_AHB_ADDR[31] , \AHB_IF_0_BIF_1_HADDR[2] , 
        \AHB_IF_0_BIF_1_HADDR[6] , \AHB_IF_0_BIF_1_HADDR[7] , 
        \AHB_IF_0_BIF_1_HADDR[13] , \AHB_IF_0_BIF_1_HADDR[25] , 
        \AHB_IF_0_BIF_1_HADDR[26] , \AHB_IF_0_BIF_1_HADDR[27] , 
        \MDDR_TA_0.CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_iv , 
        read_start_c, write_start_c, \AHB_IF_0_BIF_1_HADDR[24] , 
        \AHB_IF_0_BIF_1_HADDR[21] , \AHB_IF_0_BIF_1_HADDR[20] , 
        \AHB_IF_0_BIF_1_HADDR[19] , 
        \MDDR_TA_0.CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_iv_i_0 , 
        AXI_IF_0_BIF_1_RVALID_i_0, AXI_IF_0_BIF_1_RLAST_i_0, 
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK_i_0, \AHB_IF_0.N_178_i_0 , 
        \AXI_IF_0_BIF_1_ARADDR[24] , \AXI_IF_0_BIF_1_ARADDR[13] , 
        \AXI_IF_0_BIF_1_ARADDR[12] , \AXI_IF_0_BIF_1_ARADDR[11] , 
        \AXI_IF_0_BIF_1_ARADDR[10] , \AXI_IF_0_BIF_1_ARADDR[9] , 
        \AXI_IF_0_BIF_1_ARADDR[8] , \AXI_IF_0_BIF_1_ARADDR[7] , 
        \AXI_IF_0_AHB_ADDR[13] , \AXI_IF_0_AHB_ADDR_reto_0[13] , 
        \AXI_IF_0_AHB_ADDR[25] , \AXI_IF_0_AHB_ADDR_reto_0[25] , 
        \AXI_IF_0_AHB_ADDR[19] , \AXI_IF_0_AHB_ADDR_reto_0[19] , 
        \AXI_IF_0_AHB_ADDR[26] , \AXI_IF_0_AHB_ADDR_reto_0[26] , 
        \AXI_IF_0_AHB_ADDR[21] , \AXI_IF_0_AHB_ADDR_reto_0[21] , 
        \AXI_IF_0_AHB_ADDR[27] , \AXI_IF_0_AHB_ADDR_reto_0[27] , 
        \AXI_IF_0_AHB_ADDR[20] , \AXI_IF_0_AHB_ADDR_reto_0[20] , 
        \AXI_IF_0_AHB_ADDR_reto_0[2] , \AXI_IF_0_AHB_ADDR[24] , 
        \AXI_IF_0_AHB_ADDR_reto_0[24] , \AXI_IF_0_AHB_ADDR[7] , 
        \AXI_IF_0_AHB_ADDR_reto_0[7] , \AXI_IF_0_AHB_ADDR[6] , 
        \AXI_IF_0_AHB_ADDR_reto_0[6] , 
        \CMD_Decode_0_r_xfer_size_i_0[4] , \AHB_IF_0.HTRANS_1_fast[1] , 
        AXI_IF_0_BIF_1_RVALID, AHB_ADDR_6_cry_2_0_Y;
    
    OUTBUF write_start_obuf (.D(write_start_c), .PAD(write_start));
    VCC VCC (.Y(VCC_net_1));
    OUTBUF read_start_obuf (.D(read_start_c), .PAD(read_start));
    CMD_Decode CMD_Decode_0 (.CMD_Decode_0_w_xfer_size({
        \CMD_Decode_0_w_xfer_size[8] , \CMD_Decode_0_w_xfer_size[7] , 
        \CMD_Decode_0_w_xfer_size[6] , \CMD_Decode_0_w_xfer_size[5] , 
        \CMD_Decode_0_w_xfer_size[4] }), .WS_d1({
        \CMD_Decode_0.WS_d1[2] , \CMD_Decode_0.WS_d1[1] , 
        \CMD_Decode_0.WS_d1[0] }), .CMD_Decode_0_r_xfer_size_i_0({
        \CMD_Decode_0_r_xfer_size_i_0[4] }), .CMD_Decode_0_r_xfer_size({
        \CMD_Decode_0_r_xfer_size[8] , \CMD_Decode_0_r_xfer_size[7] , 
        \CMD_Decode_0_r_xfer_size[6] , \CMD_Decode_0_r_xfer_size[5] , 
        \CMD_Decode_0_r_xfer_size[4] }), .CMD_Decode_0_r_xfer_sizeoi({
        \CMD_Decode_0_r_xfer_sizeoi[8] , 
        \CMD_Decode_0_r_xfer_sizeoi[7] , 
        \CMD_Decode_0_r_xfer_sizeoi[6] , 
        \CMD_Decode_0_r_xfer_sizeoi[5] , 
        \CMD_Decode_0_r_xfer_sizeoi[4] }), 
        .CMD_Decode_0_w_xfer_sizeoi_0(\CMD_Decode_0_w_xfer_sizeoi[4] ), 
        .MDDR_TA_0_INIT_DONE(MDDR_TA_0_INIT_DONE), 
        .MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .MDDR_TA_0_GPIO_7_M2F(
        MDDR_TA_0_GPIO_7_M2F), .MDDR_TA_0_GPIO_2_M2F(
        MDDR_TA_0_GPIO_2_M2F), .MDDR_TA_0_GPIO_3_M2F(
        MDDR_TA_0_GPIO_3_M2F), .MDDR_TA_0_GPIO_4_M2F(
        MDDR_TA_0_GPIO_4_M2F), .MDDR_TA_0_GPIO_0_M2F(
        MDDR_TA_0_GPIO_0_M2F), .MDDR_TA_0_GPIO_1_M2F(
        MDDR_TA_0_GPIO_1_M2F), .MDDR_TA_0_GPIO_5_M2F(
        MDDR_TA_0_GPIO_5_M2F), .MDDR_TA_0_GPIO_6_M2F(
        MDDR_TA_0_GPIO_6_M2F), .read_start_c(read_start_c), 
        .write_start_c(write_start_c));
    AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z1 
        AHB_IF_0 (.AHB_IF_0_BIF_1_HWDATA({\AHB_IF_0_BIF_1_HWDATA[13] , 
        \AHB_IF_0_BIF_1_HWDATA[12] , \AHB_IF_0_BIF_1_HWDATA[11] , 
        \AHB_IF_0_BIF_1_HWDATA[10] , \AHB_IF_0_BIF_1_HWDATA[9] , 
        \AHB_IF_0_BIF_1_HWDATA[8] , \AHB_IF_0_BIF_1_HWDATA[7] , 
        \AHB_IF_0_BIF_1_HWDATA[6] , \AHB_IF_0_BIF_1_HWDATA[5] , 
        \AHB_IF_0_BIF_1_HWDATA[4] , \AHB_IF_0_BIF_1_HWDATA[3] , 
        \AHB_IF_0_BIF_1_HWDATA[2] , \AHB_IF_0_BIF_1_HWDATA[1] , 
        \AHB_IF_0_BIF_1_HWDATA[0] }), .AXI_IF_0_AHB_DATA({
        \AXI_IF_0_AHB_DATA[13] , \AXI_IF_0_AHB_DATA[12] , 
        \AXI_IF_0_AHB_DATA[11] , \AXI_IF_0_AHB_DATA[10] , 
        \AXI_IF_0_AHB_DATA[9] , \AXI_IF_0_AHB_DATA[8] , 
        \AXI_IF_0_AHB_DATA[7] , \AXI_IF_0_AHB_DATA[6] , 
        \AXI_IF_0_AHB_DATA[5] , \AXI_IF_0_AHB_DATA[4] , 
        \AXI_IF_0_AHB_DATA[3] , \AXI_IF_0_AHB_DATA[2] , 
        \AXI_IF_0_AHB_DATA[1] , \AXI_IF_0_AHB_DATA[0] }), 
        .AXI_IF_0_AHB_ADDR({\AXI_IF_0_AHB_ADDR[31] , 
        \AXI_IF_0_AHB_ADDR[30] , \AXI_IF_0_AHB_ADDR[29] , 
        \AXI_IF_0_AHB_ADDR[28] , \AXI_IF_0_AHB_ADDR[27] , 
        \AXI_IF_0_AHB_ADDR[26] , \AXI_IF_0_AHB_ADDR[25] , 
        \AXI_IF_0_AHB_ADDR[24] , \AXI_IF_0_AHB_ADDR[23] , 
        \AXI_IF_0_AHB_ADDR[22] , \AXI_IF_0_AHB_ADDR[21] , 
        \AXI_IF_0_AHB_ADDR[20] , \AXI_IF_0_AHB_ADDR[19] , 
        \AXI_IF_0_AHB_ADDR[18] , \AXI_IF_0_AHB_ADDR[17] , 
        \AXI_IF_0_AHB_ADDR[16] , \AXI_IF_0_AHB_ADDR[15] , 
        \AXI_IF_0_AHB_ADDR[14] , \AXI_IF_0_AHB_ADDR[13] , 
        \AXI_IF_0_AHB_ADDR[12] , \AXI_IF_0_AHB_ADDR[11] , 
        \AXI_IF_0_AHB_ADDR[10] , \AXI_IF_0_AHB_ADDR[9] , 
        \AXI_IF_0_AHB_ADDR[8] , \AXI_IF_0_AHB_ADDR[7] , 
        \AXI_IF_0_AHB_ADDR[6] , \AXI_IF_0_AHB_ADDR[5] , 
        \AXI_IF_0_AHB_ADDR[4] , \AXI_IF_0_AHB_ADDR[3] }), 
        .AHB_IF_0_BIF_1_HTRANS({\AHB_IF_0_BIF_1_HTRANS[1] }), 
        .HTRANS_1_fast({\AHB_IF_0.HTRANS_1_fast[1] }), 
        .AHB_IF_0_BIF_1_HADDR({\AHB_IF_0_BIF_1_HADDR[31] , 
        \AHB_IF_0_BIF_1_HADDR[30] , \AHB_IF_0_BIF_1_HADDR[29] , 
        \AHB_IF_0_BIF_1_HADDR[28] , \AHB_IF_0_BIF_1_HADDR[27] , 
        \AHB_IF_0_BIF_1_HADDR[26] , \AHB_IF_0_BIF_1_HADDR[25] , 
        \AHB_IF_0_BIF_1_HADDR[24] , \AHB_IF_0_BIF_1_HADDR[23] , 
        \AHB_IF_0_BIF_1_HADDR[22] , \AHB_IF_0_BIF_1_HADDR[21] , 
        \AHB_IF_0_BIF_1_HADDR[20] , \AHB_IF_0_BIF_1_HADDR[19] , 
        \AHB_IF_0_BIF_1_HADDR[18] , \AHB_IF_0_BIF_1_HADDR[17] , 
        \AHB_IF_0_BIF_1_HADDR[16] , \AHB_IF_0_BIF_1_HADDR[15] , 
        \AHB_IF_0_BIF_1_HADDR[14] , \AHB_IF_0_BIF_1_HADDR[13] , 
        \AHB_IF_0_BIF_1_HADDR[12] , \AHB_IF_0_BIF_1_HADDR[11] , 
        \AHB_IF_0_BIF_1_HADDR[10] , \AHB_IF_0_BIF_1_HADDR[9] , 
        \AHB_IF_0_BIF_1_HADDR[8] , \AHB_IF_0_BIF_1_HADDR[7] , 
        \AHB_IF_0_BIF_1_HADDR[6] , \AHB_IF_0_BIF_1_HADDR[5] , 
        \AHB_IF_0_BIF_1_HADDR[4] , \AHB_IF_0_BIF_1_HADDR[3] , 
        \AHB_IF_0_BIF_1_HADDR[2] }), .AXI_IF_0_AHB_ADDR_reto_0_0(
        \AXI_IF_0_AHB_ADDR_reto_0[2] ), .AXI_IF_0_AHB_ADDR_reto_0_4(
        \AXI_IF_0_AHB_ADDR_reto_0[6] ), .AXI_IF_0_AHB_ADDR_reto_0_5(
        \AXI_IF_0_AHB_ADDR_reto_0[7] ), .AXI_IF_0_AHB_ADDR_reto_0_11(
        \AXI_IF_0_AHB_ADDR_reto_0[13] ), .AXI_IF_0_AHB_ADDR_reto_0_23(
        \AXI_IF_0_AHB_ADDR_reto_0[25] ), .AXI_IF_0_AHB_ADDR_reto_0_24(
        \AXI_IF_0_AHB_ADDR_reto_0[26] ), .AXI_IF_0_AHB_ADDR_reto_0_25(
        \AXI_IF_0_AHB_ADDR_reto_0[27] ), .AXI_IF_0_AHB_ADDR_reto_0_22(
        \AXI_IF_0_AHB_ADDR_reto_0[24] ), .AXI_IF_0_AHB_ADDR_reto_0_19(
        \AXI_IF_0_AHB_ADDR_reto_0[21] ), .AXI_IF_0_AHB_ADDR_reto_0_18(
        \AXI_IF_0_AHB_ADDR_reto_0[20] ), .AXI_IF_0_AHB_ADDR_reto_0_17(
        \AXI_IF_0_AHB_ADDR_reto_0[19] ), 
        .MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), .MDDR_TA_0_INIT_DONE(
        MDDR_TA_0_INIT_DONE), .N_178_i_0(\AHB_IF_0.N_178_i_0 ), 
        .AHB_ADDR_6_cry_2_0_Y(AHB_ADDR_6_cry_2_0_Y), 
        .AHB_IF_0_BIF_1_HWRITE(AHB_IF_0_BIF_1_HWRITE), 
        .AHB_IF_0_AHB_BUSY(AHB_IF_0_AHB_BUSY), .HREADY_M_iv_i_0(
        \MDDR_TA_0.CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_iv_i_0 )
        , .AXI_IF_0_WRITE_AHB(AXI_IF_0_WRITE_AHB), .HREADY_M_iv(
        \MDDR_TA_0.CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_iv )
        );
    GND GND (.Y(GND_net_1));
    MDDR_TA MDDR_TA_0 (.AHB_IF_0_BIF_1_HTRANS({
        \AHB_IF_0_BIF_1_HTRANS[1] }), .AHB_IF_0_BIF_1_HADDR({
        \AHB_IF_0_BIF_1_HADDR[31] , \AHB_IF_0_BIF_1_HADDR[30] , 
        \AHB_IF_0_BIF_1_HADDR[29] , \AHB_IF_0_BIF_1_HADDR[28] , 
        \AHB_IF_0_BIF_1_HADDR[27] , \AHB_IF_0_BIF_1_HADDR[26] , 
        \AHB_IF_0_BIF_1_HADDR[25] , \AHB_IF_0_BIF_1_HADDR[24] , 
        \AHB_IF_0_BIF_1_HADDR[23] , \AHB_IF_0_BIF_1_HADDR[22] , 
        \AHB_IF_0_BIF_1_HADDR[21] , \AHB_IF_0_BIF_1_HADDR[20] , 
        \AHB_IF_0_BIF_1_HADDR[19] , \AHB_IF_0_BIF_1_HADDR[18] , 
        \AHB_IF_0_BIF_1_HADDR[17] , \AHB_IF_0_BIF_1_HADDR[16] , 
        \AHB_IF_0_BIF_1_HADDR[15] , \AHB_IF_0_BIF_1_HADDR[14] , 
        \AHB_IF_0_BIF_1_HADDR[13] , \AHB_IF_0_BIF_1_HADDR[12] , 
        \AHB_IF_0_BIF_1_HADDR[11] , \AHB_IF_0_BIF_1_HADDR[10] , 
        \AHB_IF_0_BIF_1_HADDR[9] , \AHB_IF_0_BIF_1_HADDR[8] , 
        \AHB_IF_0_BIF_1_HADDR[7] , \AHB_IF_0_BIF_1_HADDR[6] , 
        \AHB_IF_0_BIF_1_HADDR[5] , \AHB_IF_0_BIF_1_HADDR[4] , 
        \AHB_IF_0_BIF_1_HADDR[3] , \AHB_IF_0_BIF_1_HADDR[2] }), 
        .HTRANS_1_fast({\AHB_IF_0.HTRANS_1_fast[1] }), 
        .AHB_IF_0_BIF_1_HWDATA({\AHB_IF_0_BIF_1_HWDATA[13] , 
        \AHB_IF_0_BIF_1_HWDATA[12] , \AHB_IF_0_BIF_1_HWDATA[11] , 
        \AHB_IF_0_BIF_1_HWDATA[10] , \AHB_IF_0_BIF_1_HWDATA[9] , 
        \AHB_IF_0_BIF_1_HWDATA[8] , \AHB_IF_0_BIF_1_HWDATA[7] , 
        \AHB_IF_0_BIF_1_HWDATA[6] , \AHB_IF_0_BIF_1_HWDATA[5] , 
        \AHB_IF_0_BIF_1_HWDATA[4] , \AHB_IF_0_BIF_1_HWDATA[3] , 
        \AHB_IF_0_BIF_1_HWDATA[2] , \AHB_IF_0_BIF_1_HWDATA[1] , 
        \AHB_IF_0_BIF_1_HWDATA[0] }), .MDDR_DQ({MDDR_DQ[15], 
        MDDR_DQ[14], MDDR_DQ[13], MDDR_DQ[12], MDDR_DQ[11], 
        MDDR_DQ[10], MDDR_DQ[9], MDDR_DQ[8], MDDR_DQ[7], MDDR_DQ[6], 
        MDDR_DQ[5], MDDR_DQ[4], MDDR_DQ[3], MDDR_DQ[2], MDDR_DQ[1], 
        MDDR_DQ[0]}), .MDDR_DM_RDQS({MDDR_DM_RDQS[1], MDDR_DM_RDQS[0]})
        , .MDDR_BA({MDDR_BA[2], MDDR_BA[1], MDDR_BA[0]}), .MDDR_ADDR({
        MDDR_ADDR[15], MDDR_ADDR[14], MDDR_ADDR[13], MDDR_ADDR[12], 
        MDDR_ADDR[11], MDDR_ADDR[10], MDDR_ADDR[9], MDDR_ADDR[8], 
        MDDR_ADDR[7], MDDR_ADDR[6], MDDR_ADDR[5], MDDR_ADDR[4], 
        MDDR_ADDR[3], MDDR_ADDR[2], MDDR_ADDR[1], MDDR_ADDR[0]}), 
        .AXI_IF_0_BIF_1_RDATA({\AXI_IF_0_BIF_1_RDATA[63] , 
        \AXI_IF_0_BIF_1_RDATA[62] , \AXI_IF_0_BIF_1_RDATA[61] , 
        \AXI_IF_0_BIF_1_RDATA[60] , \AXI_IF_0_BIF_1_RDATA[59] , 
        \AXI_IF_0_BIF_1_RDATA[58] , \AXI_IF_0_BIF_1_RDATA[57] , 
        \AXI_IF_0_BIF_1_RDATA[56] , \AXI_IF_0_BIF_1_RDATA[55] , 
        \AXI_IF_0_BIF_1_RDATA[54] , \AXI_IF_0_BIF_1_RDATA[53] , 
        \AXI_IF_0_BIF_1_RDATA[52] , \AXI_IF_0_BIF_1_RDATA[51] , 
        \AXI_IF_0_BIF_1_RDATA[50] , \AXI_IF_0_BIF_1_RDATA[49] , 
        \AXI_IF_0_BIF_1_RDATA[48] , \AXI_IF_0_BIF_1_RDATA[47] , 
        \AXI_IF_0_BIF_1_RDATA[46] , \AXI_IF_0_BIF_1_RDATA[45] , 
        \AXI_IF_0_BIF_1_RDATA[44] , \AXI_IF_0_BIF_1_RDATA[43] , 
        \AXI_IF_0_BIF_1_RDATA[42] , \AXI_IF_0_BIF_1_RDATA[41] , 
        \AXI_IF_0_BIF_1_RDATA[40] , \AXI_IF_0_BIF_1_RDATA[39] , 
        \AXI_IF_0_BIF_1_RDATA[38] , \AXI_IF_0_BIF_1_RDATA[37] , 
        \AXI_IF_0_BIF_1_RDATA[36] , \AXI_IF_0_BIF_1_RDATA[35] , 
        \AXI_IF_0_BIF_1_RDATA[34] , \AXI_IF_0_BIF_1_RDATA[33] , 
        \AXI_IF_0_BIF_1_RDATA[32] , \AXI_IF_0_BIF_1_RDATA[31] , 
        \AXI_IF_0_BIF_1_RDATA[30] , \AXI_IF_0_BIF_1_RDATA[29] , 
        \AXI_IF_0_BIF_1_RDATA[28] , \AXI_IF_0_BIF_1_RDATA[27] , 
        \AXI_IF_0_BIF_1_RDATA[26] , \AXI_IF_0_BIF_1_RDATA[25] , 
        \AXI_IF_0_BIF_1_RDATA[24] , \AXI_IF_0_BIF_1_RDATA[23] , 
        \AXI_IF_0_BIF_1_RDATA[22] , \AXI_IF_0_BIF_1_RDATA[21] , 
        \AXI_IF_0_BIF_1_RDATA[20] , \AXI_IF_0_BIF_1_RDATA[19] , 
        \AXI_IF_0_BIF_1_RDATA[18] , \AXI_IF_0_BIF_1_RDATA[17] , 
        \AXI_IF_0_BIF_1_RDATA[16] , \AXI_IF_0_BIF_1_RDATA[15] , 
        \AXI_IF_0_BIF_1_RDATA[14] , \AXI_IF_0_BIF_1_RDATA[13] , 
        \AXI_IF_0_BIF_1_RDATA[12] , \AXI_IF_0_BIF_1_RDATA[11] , 
        \AXI_IF_0_BIF_1_RDATA[10] , \AXI_IF_0_BIF_1_RDATA[9] , 
        \AXI_IF_0_BIF_1_RDATA[8] , \AXI_IF_0_BIF_1_RDATA[7] , 
        \AXI_IF_0_BIF_1_RDATA[6] , \AXI_IF_0_BIF_1_RDATA[5] , 
        \AXI_IF_0_BIF_1_RDATA[4] , \AXI_IF_0_BIF_1_RDATA[3] , 
        \AXI_IF_0_BIF_1_RDATA[2] , \AXI_IF_0_BIF_1_RDATA[1] , 
        \AXI_IF_0_BIF_1_RDATA[0] }), .AXI_IF_0_BIF_1_ARADDR({
        \AXI_IF_0_BIF_1_ARADDR[31] , \AXI_IF_0_BIF_1_ARADDR[30] , 
        \AXI_IF_0_BIF_1_ARADDR[29] , \AXI_IF_0_BIF_1_ARADDR[28] , 
        \AXI_IF_0_BIF_1_ARADDR[27] , \AXI_IF_0_BIF_1_ARADDR[26] , 
        \AXI_IF_0_BIF_1_ARADDR[25] , \AXI_IF_0_BIF_1_ARADDR[24] , 
        \AXI_IF_0_BIF_1_ARADDR[23] , \AXI_IF_0_BIF_1_ARADDR[22] , 
        \AXI_IF_0_BIF_1_ARADDR[21] , \AXI_IF_0_BIF_1_ARADDR[20] , 
        \AXI_IF_0_BIF_1_ARADDR[19] , \AXI_IF_0_BIF_1_ARADDR[18] , 
        \AXI_IF_0_BIF_1_ARADDR[17] , \AXI_IF_0_BIF_1_ARADDR[16] , 
        \AXI_IF_0_BIF_1_ARADDR[15] , \AXI_IF_0_BIF_1_ARADDR[14] , 
        \AXI_IF_0_BIF_1_ARADDR[13] , \AXI_IF_0_BIF_1_ARADDR[12] , 
        \AXI_IF_0_BIF_1_ARADDR[11] , \AXI_IF_0_BIF_1_ARADDR[10] , 
        \AXI_IF_0_BIF_1_ARADDR[9] , \AXI_IF_0_BIF_1_ARADDR[8] , 
        \AXI_IF_0_BIF_1_ARADDR[7] }), .AXI_IF_0_BIF_1_ARSIZE({
        \AXI_IF_0_BIF_1_ARSIZE[1] }), .AXI_IF_0_BIF_1_AWADDR({
        \AXI_IF_0_BIF_1_AWADDR[31] , \AXI_IF_0_BIF_1_AWADDR[30] , 
        \AXI_IF_0_BIF_1_AWADDR[29] , \AXI_IF_0_BIF_1_AWADDR[28] , 
        \AXI_IF_0_BIF_1_AWADDR[27] , \AXI_IF_0_BIF_1_AWADDR[26] , 
        \AXI_IF_0_BIF_1_AWADDR[25] , \AXI_IF_0_BIF_1_AWADDR[24] , 
        \AXI_IF_0_BIF_1_AWADDR[23] , \AXI_IF_0_BIF_1_AWADDR[22] , 
        \AXI_IF_0_BIF_1_AWADDR[21] , \AXI_IF_0_BIF_1_AWADDR[20] , 
        \AXI_IF_0_BIF_1_AWADDR[19] , \AXI_IF_0_BIF_1_AWADDR[18] , 
        \AXI_IF_0_BIF_1_AWADDR[17] , \AXI_IF_0_BIF_1_AWADDR[16] , 
        \AXI_IF_0_BIF_1_AWADDR[15] , \AXI_IF_0_BIF_1_AWADDR[14] , 
        \AXI_IF_0_BIF_1_AWADDR[13] , \AXI_IF_0_BIF_1_AWADDR[12] , 
        \AXI_IF_0_BIF_1_AWADDR[11] , \AXI_IF_0_BIF_1_AWADDR[10] , 
        \AXI_IF_0_BIF_1_AWADDR[9] , \AXI_IF_0_BIF_1_AWADDR[8] , 
        \AXI_IF_0_BIF_1_AWADDR[7] }), .AXI_IF_0_BIF_1_AWSIZE({
        \AXI_IF_0_BIF_1_AWSIZE[1] }), .AXI_IF_0_BIF_1_WDATA({
        \AXI_IF_0_BIF_1_WDATA[63] , \AXI_IF_0_BIF_1_WDATA[62] , 
        \AXI_IF_0_BIF_1_WDATA[61] , \AXI_IF_0_BIF_1_WDATA[60] , 
        \AXI_IF_0_BIF_1_WDATA[59] , \AXI_IF_0_BIF_1_WDATA[58] , 
        \AXI_IF_0_BIF_1_WDATA[57] , \AXI_IF_0_BIF_1_WDATA[56] , 
        \AXI_IF_0_BIF_1_WDATA[55] , \AXI_IF_0_BIF_1_WDATA[54] , 
        \AXI_IF_0_BIF_1_WDATA[53] , \AXI_IF_0_BIF_1_WDATA[52] , 
        \AXI_IF_0_BIF_1_WDATA[51] , \AXI_IF_0_BIF_1_WDATA[50] , 
        \AXI_IF_0_BIF_1_WDATA[49] , \AXI_IF_0_BIF_1_WDATA[48] , 
        \AXI_IF_0_BIF_1_WDATA[47] , \AXI_IF_0_BIF_1_WDATA[46] , 
        \AXI_IF_0_BIF_1_WDATA[45] , \AXI_IF_0_BIF_1_WDATA[44] , 
        \AXI_IF_0_BIF_1_WDATA[43] , \AXI_IF_0_BIF_1_WDATA[42] , 
        \AXI_IF_0_BIF_1_WDATA[41] , \AXI_IF_0_BIF_1_WDATA[40] , 
        \AXI_IF_0_BIF_1_WDATA[39] , \AXI_IF_0_BIF_1_WDATA[38] , 
        \AXI_IF_0_BIF_1_WDATA[37] , \AXI_IF_0_BIF_1_WDATA[36] , 
        \AXI_IF_0_BIF_1_WDATA[35] , \AXI_IF_0_BIF_1_WDATA[34] , 
        \AXI_IF_0_BIF_1_WDATA[33] , \AXI_IF_0_BIF_1_WDATA[32] , 
        \AXI_IF_0_BIF_1_WDATA[31] , \AXI_IF_0_BIF_1_WDATA[30] , 
        \AXI_IF_0_BIF_1_WDATA[29] , \AXI_IF_0_BIF_1_WDATA[28] , 
        \AXI_IF_0_BIF_1_WDATA[27] , \AXI_IF_0_BIF_1_WDATA[26] , 
        \AXI_IF_0_BIF_1_WDATA[25] , \AXI_IF_0_BIF_1_WDATA[24] , 
        \AXI_IF_0_BIF_1_WDATA[23] , \AXI_IF_0_BIF_1_WDATA[22] , 
        \AXI_IF_0_BIF_1_WDATA[21] , \AXI_IF_0_BIF_1_WDATA[20] , 
        \AXI_IF_0_BIF_1_WDATA[19] , \AXI_IF_0_BIF_1_WDATA[18] , 
        \AXI_IF_0_BIF_1_WDATA[17] , \AXI_IF_0_BIF_1_WDATA[16] , 
        \AXI_IF_0_BIF_1_WDATA[15] , \AXI_IF_0_BIF_1_WDATA[14] , 
        \AXI_IF_0_BIF_1_WDATA[13] , \AXI_IF_0_BIF_1_WDATA[12] , 
        \AXI_IF_0_BIF_1_WDATA[11] , \AXI_IF_0_BIF_1_WDATA[10] , 
        \AXI_IF_0_BIF_1_WDATA[9] , \AXI_IF_0_BIF_1_WDATA[8] , 
        \AXI_IF_0_BIF_1_WDATA[7] , \AXI_IF_0_BIF_1_WDATA[6] , 
        \AXI_IF_0_BIF_1_WDATA[5] , \AXI_IF_0_BIF_1_WDATA[4] , 
        \AXI_IF_0_BIF_1_WDATA[3] , \AXI_IF_0_BIF_1_WDATA[2] , 
        \AXI_IF_0_BIF_1_WDATA[1] , \AXI_IF_0_BIF_1_WDATA[0] }), 
        .AXI_IF_0_BIF_1_WSTRB({\AXI_IF_0_BIF_1_WSTRB[1] }), 
        .MDDR_DQS_N({MDDR_DQS_N[1], MDDR_DQS_N[0]}), .MDDR_DQS({
        MDDR_DQS[1], MDDR_DQS[0]}), .MDDR_TA_0_INIT_DONE(
        MDDR_TA_0_INIT_DONE), .DEVRST_N(DEVRST_N), 
        .MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), 
        .MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK_i_0(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK_i_0), 
        .AHB_IF_0_BIF_1_HWRITE(AHB_IF_0_BIF_1_HWRITE), .HREADY_M_iv(
        \MDDR_TA_0.CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_iv )
        , .HREADY_M_iv_i_0(
        \MDDR_TA_0.CoreAHBLite_0.matrix4x16.masterstage_0.HREADY_M_iv_i_0 )
        , .AXI_IF_0_BIF_1_RVALID(AXI_IF_0_BIF_1_RVALID), 
        .AXI_IF_0_BIF_1_RVALID_i_0(AXI_IF_0_BIF_1_RVALID_i_0), 
        .AXI_IF_0_BIF_1_RLAST(AXI_IF_0_BIF_1_RLAST), 
        .AXI_IF_0_BIF_1_RLAST_i_0(AXI_IF_0_BIF_1_RLAST_i_0), 
        .MMUART_0_TXD(MMUART_0_TXD), .MMUART_0_RXD(MMUART_0_RXD), 
        .MDDR_WE_N(MDDR_WE_N), .MDDR_RESET_N(MDDR_RESET_N), 
        .MDDR_RAS_N(MDDR_RAS_N), .MDDR_ODT(MDDR_ODT), 
        .MDDR_DQS_TMATCH_0_OUT(MDDR_DQS_TMATCH_0_OUT), 
        .MDDR_DQS_TMATCH_0_IN(MDDR_DQS_TMATCH_0_IN), .MDDR_CS_N(
        MDDR_CS_N), .MDDR_CKE(MDDR_CKE), .MDDR_CAS_N(MDDR_CAS_N), 
        .MDDR_TA_0_GPIO_3_M2F(MDDR_TA_0_GPIO_3_M2F), 
        .MDDR_TA_0_GPIO_4_M2F(MDDR_TA_0_GPIO_4_M2F), 
        .MDDR_TA_0_GPIO_2_M2F(MDDR_TA_0_GPIO_2_M2F), 
        .MDDR_TA_0_GPIO_1_M2F(MDDR_TA_0_GPIO_1_M2F), 
        .MDDR_TA_0_GPIO_0_M2F(MDDR_TA_0_GPIO_0_M2F), 
        .MDDR_TA_0_GPIO_5_M2F(MDDR_TA_0_GPIO_5_M2F), 
        .MDDR_TA_0_GPIO_6_M2F(MDDR_TA_0_GPIO_6_M2F), 
        .MDDR_TA_0_GPIO_7_M2F(MDDR_TA_0_GPIO_7_M2F), 
        .AXI_IF_0_BIF_1_ARREADY(AXI_IF_0_BIF_1_ARREADY), 
        .AXI_IF_0_BIF_1_AWREADY(AXI_IF_0_BIF_1_AWREADY), 
        .AXI_IF_0_BIF_1_WREADY(AXI_IF_0_BIF_1_WREADY), 
        .AXI_IF_0_BIF_1_ARVALID(AXI_IF_0_BIF_1_ARVALID), 
        .AXI_IF_0_BIF_1_AWVALID(AXI_IF_0_BIF_1_AWVALID), 
        .AXI_IF_0_BIF_1_RREADY(AXI_IF_0_BIF_1_RREADY), 
        .AXI_IF_0_BIF_1_WLAST(AXI_IF_0_BIF_1_WLAST), 
        .AXI_IF_0_BIF_1_WVALID(AXI_IF_0_BIF_1_WVALID), .MDDR_CLK_N(
        MDDR_CLK_N), .MDDR_CLK(MDDR_CLK));
    AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z2 
        AXI_IF_0 (.AXI_IF_0_BIF_1_AWADDR({\AXI_IF_0_BIF_1_AWADDR[31] , 
        \AXI_IF_0_BIF_1_AWADDR[30] , \AXI_IF_0_BIF_1_AWADDR[29] , 
        \AXI_IF_0_BIF_1_AWADDR[28] , \AXI_IF_0_BIF_1_AWADDR[27] , 
        \AXI_IF_0_BIF_1_AWADDR[26] , \AXI_IF_0_BIF_1_AWADDR[25] , 
        \AXI_IF_0_BIF_1_AWADDR[24] , \AXI_IF_0_BIF_1_AWADDR[23] , 
        \AXI_IF_0_BIF_1_AWADDR[22] , \AXI_IF_0_BIF_1_AWADDR[21] , 
        \AXI_IF_0_BIF_1_AWADDR[20] , \AXI_IF_0_BIF_1_AWADDR[19] , 
        \AXI_IF_0_BIF_1_AWADDR[18] , \AXI_IF_0_BIF_1_AWADDR[17] , 
        \AXI_IF_0_BIF_1_AWADDR[16] , \AXI_IF_0_BIF_1_AWADDR[15] , 
        \AXI_IF_0_BIF_1_AWADDR[14] , \AXI_IF_0_BIF_1_AWADDR[13] , 
        \AXI_IF_0_BIF_1_AWADDR[12] , \AXI_IF_0_BIF_1_AWADDR[11] , 
        \AXI_IF_0_BIF_1_AWADDR[10] , \AXI_IF_0_BIF_1_AWADDR[9] , 
        \AXI_IF_0_BIF_1_AWADDR[8] , \AXI_IF_0_BIF_1_AWADDR[7] }), 
        .AXI_IF_0_AHB_DATA({\AXI_IF_0_AHB_DATA[13] , 
        \AXI_IF_0_AHB_DATA[12] , \AXI_IF_0_AHB_DATA[11] , 
        \AXI_IF_0_AHB_DATA[10] , \AXI_IF_0_AHB_DATA[9] , 
        \AXI_IF_0_AHB_DATA[8] , \AXI_IF_0_AHB_DATA[7] , 
        \AXI_IF_0_AHB_DATA[6] , \AXI_IF_0_AHB_DATA[5] , 
        \AXI_IF_0_AHB_DATA[4] , \AXI_IF_0_AHB_DATA[3] , 
        \AXI_IF_0_AHB_DATA[2] , \AXI_IF_0_AHB_DATA[1] , 
        \AXI_IF_0_AHB_DATA[0] }), .AXI_IF_0_BIF_1_ARADDR({
        \AXI_IF_0_BIF_1_ARADDR[31] , \AXI_IF_0_BIF_1_ARADDR[30] , 
        \AXI_IF_0_BIF_1_ARADDR[29] , \AXI_IF_0_BIF_1_ARADDR[28] , 
        \AXI_IF_0_BIF_1_ARADDR[27] , \AXI_IF_0_BIF_1_ARADDR[26] , 
        \AXI_IF_0_BIF_1_ARADDR[25] , \AXI_IF_0_BIF_1_ARADDR[24] , 
        \AXI_IF_0_BIF_1_ARADDR[23] , \AXI_IF_0_BIF_1_ARADDR[22] , 
        \AXI_IF_0_BIF_1_ARADDR[21] , \AXI_IF_0_BIF_1_ARADDR[20] , 
        \AXI_IF_0_BIF_1_ARADDR[19] , \AXI_IF_0_BIF_1_ARADDR[18] , 
        \AXI_IF_0_BIF_1_ARADDR[17] , \AXI_IF_0_BIF_1_ARADDR[16] , 
        \AXI_IF_0_BIF_1_ARADDR[15] , \AXI_IF_0_BIF_1_ARADDR[14] , 
        \AXI_IF_0_BIF_1_ARADDR[13] , \AXI_IF_0_BIF_1_ARADDR[12] , 
        \AXI_IF_0_BIF_1_ARADDR[11] , \AXI_IF_0_BIF_1_ARADDR[10] , 
        \AXI_IF_0_BIF_1_ARADDR[9] , \AXI_IF_0_BIF_1_ARADDR[8] , 
        \AXI_IF_0_BIF_1_ARADDR[7] }), .AXI_IF_0_BIF_1_WSTRB({
        \AXI_IF_0_BIF_1_WSTRB[1] }), .AXI_IF_0_BIF_1_AWSIZE({
        \AXI_IF_0_BIF_1_AWSIZE[1] }), .AXI_IF_0_BIF_1_ARSIZE({
        \AXI_IF_0_BIF_1_ARSIZE[1] }), .AXI_IF_0_AHB_ADDR({
        \AXI_IF_0_AHB_ADDR[31] , \AXI_IF_0_AHB_ADDR[30] , 
        \AXI_IF_0_AHB_ADDR[29] , \AXI_IF_0_AHB_ADDR[28] , 
        \AXI_IF_0_AHB_ADDR[27] , \AXI_IF_0_AHB_ADDR[26] , 
        \AXI_IF_0_AHB_ADDR[25] , \AXI_IF_0_AHB_ADDR[24] , 
        \AXI_IF_0_AHB_ADDR[23] , \AXI_IF_0_AHB_ADDR[22] , 
        \AXI_IF_0_AHB_ADDR[21] , \AXI_IF_0_AHB_ADDR[20] , 
        \AXI_IF_0_AHB_ADDR[19] , \AXI_IF_0_AHB_ADDR[18] , 
        \AXI_IF_0_AHB_ADDR[17] , \AXI_IF_0_AHB_ADDR[16] , 
        \AXI_IF_0_AHB_ADDR[15] , \AXI_IF_0_AHB_ADDR[14] , 
        \AXI_IF_0_AHB_ADDR[13] , \AXI_IF_0_AHB_ADDR[12] , 
        \AXI_IF_0_AHB_ADDR[11] , \AXI_IF_0_AHB_ADDR[10] , 
        \AXI_IF_0_AHB_ADDR[9] , \AXI_IF_0_AHB_ADDR[8] , 
        \AXI_IF_0_AHB_ADDR[7] , \AXI_IF_0_AHB_ADDR[6] , 
        \AXI_IF_0_AHB_ADDR[5] , \AXI_IF_0_AHB_ADDR[4] , 
        \AXI_IF_0_AHB_ADDR[3] }), .CMD_Decode_0_r_xfer_size({
        \CMD_Decode_0_r_xfer_size[8] , \CMD_Decode_0_r_xfer_size[7] , 
        \CMD_Decode_0_r_xfer_size[6] , \CMD_Decode_0_r_xfer_size[5] , 
        \CMD_Decode_0_r_xfer_size[4] }), .CMD_Decode_0_r_xfer_size_i_0({
        \CMD_Decode_0_r_xfer_size_i_0[4] }), .CMD_Decode_0_w_xfer_size({
        \CMD_Decode_0_w_xfer_size[8] , \CMD_Decode_0_w_xfer_size[7] , 
        \CMD_Decode_0_w_xfer_size[6] , \CMD_Decode_0_w_xfer_size[5] , 
        \CMD_Decode_0_w_xfer_size[4] }), .AXI_IF_0_BIF_1_RDATA({
        \AXI_IF_0_BIF_1_RDATA[63] , \AXI_IF_0_BIF_1_RDATA[62] , 
        \AXI_IF_0_BIF_1_RDATA[61] , \AXI_IF_0_BIF_1_RDATA[60] , 
        \AXI_IF_0_BIF_1_RDATA[59] , \AXI_IF_0_BIF_1_RDATA[58] , 
        \AXI_IF_0_BIF_1_RDATA[57] , \AXI_IF_0_BIF_1_RDATA[56] , 
        \AXI_IF_0_BIF_1_RDATA[55] , \AXI_IF_0_BIF_1_RDATA[54] , 
        \AXI_IF_0_BIF_1_RDATA[53] , \AXI_IF_0_BIF_1_RDATA[52] , 
        \AXI_IF_0_BIF_1_RDATA[51] , \AXI_IF_0_BIF_1_RDATA[50] , 
        \AXI_IF_0_BIF_1_RDATA[49] , \AXI_IF_0_BIF_1_RDATA[48] , 
        \AXI_IF_0_BIF_1_RDATA[47] , \AXI_IF_0_BIF_1_RDATA[46] , 
        \AXI_IF_0_BIF_1_RDATA[45] , \AXI_IF_0_BIF_1_RDATA[44] , 
        \AXI_IF_0_BIF_1_RDATA[43] , \AXI_IF_0_BIF_1_RDATA[42] , 
        \AXI_IF_0_BIF_1_RDATA[41] , \AXI_IF_0_BIF_1_RDATA[40] , 
        \AXI_IF_0_BIF_1_RDATA[39] , \AXI_IF_0_BIF_1_RDATA[38] , 
        \AXI_IF_0_BIF_1_RDATA[37] , \AXI_IF_0_BIF_1_RDATA[36] , 
        \AXI_IF_0_BIF_1_RDATA[35] , \AXI_IF_0_BIF_1_RDATA[34] , 
        \AXI_IF_0_BIF_1_RDATA[33] , \AXI_IF_0_BIF_1_RDATA[32] , 
        \AXI_IF_0_BIF_1_RDATA[31] , \AXI_IF_0_BIF_1_RDATA[30] , 
        \AXI_IF_0_BIF_1_RDATA[29] , \AXI_IF_0_BIF_1_RDATA[28] , 
        \AXI_IF_0_BIF_1_RDATA[27] , \AXI_IF_0_BIF_1_RDATA[26] , 
        \AXI_IF_0_BIF_1_RDATA[25] , \AXI_IF_0_BIF_1_RDATA[24] , 
        \AXI_IF_0_BIF_1_RDATA[23] , \AXI_IF_0_BIF_1_RDATA[22] , 
        \AXI_IF_0_BIF_1_RDATA[21] , \AXI_IF_0_BIF_1_RDATA[20] , 
        \AXI_IF_0_BIF_1_RDATA[19] , \AXI_IF_0_BIF_1_RDATA[18] , 
        \AXI_IF_0_BIF_1_RDATA[17] , \AXI_IF_0_BIF_1_RDATA[16] , 
        \AXI_IF_0_BIF_1_RDATA[15] , \AXI_IF_0_BIF_1_RDATA[14] , 
        \AXI_IF_0_BIF_1_RDATA[13] , \AXI_IF_0_BIF_1_RDATA[12] , 
        \AXI_IF_0_BIF_1_RDATA[11] , \AXI_IF_0_BIF_1_RDATA[10] , 
        \AXI_IF_0_BIF_1_RDATA[9] , \AXI_IF_0_BIF_1_RDATA[8] , 
        \AXI_IF_0_BIF_1_RDATA[7] , \AXI_IF_0_BIF_1_RDATA[6] , 
        \AXI_IF_0_BIF_1_RDATA[5] , \AXI_IF_0_BIF_1_RDATA[4] , 
        \AXI_IF_0_BIF_1_RDATA[3] , \AXI_IF_0_BIF_1_RDATA[2] , 
        \AXI_IF_0_BIF_1_RDATA[1] , \AXI_IF_0_BIF_1_RDATA[0] }), .WS_d1({
        \CMD_Decode_0.WS_d1[2] , \CMD_Decode_0.WS_d1[1] , 
        \CMD_Decode_0.WS_d1[0] }), .CMD_Decode_0_w_xfer_sizeoi({
        \CMD_Decode_0_w_xfer_sizeoi[4] }), .AXI_IF_0_BIF_1_WDATA({
        \AXI_IF_0_BIF_1_WDATA[63] , \AXI_IF_0_BIF_1_WDATA[62] , 
        \AXI_IF_0_BIF_1_WDATA[61] , \AXI_IF_0_BIF_1_WDATA[60] , 
        \AXI_IF_0_BIF_1_WDATA[59] , \AXI_IF_0_BIF_1_WDATA[58] , 
        \AXI_IF_0_BIF_1_WDATA[57] , \AXI_IF_0_BIF_1_WDATA[56] , 
        \AXI_IF_0_BIF_1_WDATA[55] , \AXI_IF_0_BIF_1_WDATA[54] , 
        \AXI_IF_0_BIF_1_WDATA[53] , \AXI_IF_0_BIF_1_WDATA[52] , 
        \AXI_IF_0_BIF_1_WDATA[51] , \AXI_IF_0_BIF_1_WDATA[50] , 
        \AXI_IF_0_BIF_1_WDATA[49] , \AXI_IF_0_BIF_1_WDATA[48] , 
        \AXI_IF_0_BIF_1_WDATA[47] , \AXI_IF_0_BIF_1_WDATA[46] , 
        \AXI_IF_0_BIF_1_WDATA[45] , \AXI_IF_0_BIF_1_WDATA[44] , 
        \AXI_IF_0_BIF_1_WDATA[43] , \AXI_IF_0_BIF_1_WDATA[42] , 
        \AXI_IF_0_BIF_1_WDATA[41] , \AXI_IF_0_BIF_1_WDATA[40] , 
        \AXI_IF_0_BIF_1_WDATA[39] , \AXI_IF_0_BIF_1_WDATA[38] , 
        \AXI_IF_0_BIF_1_WDATA[37] , \AXI_IF_0_BIF_1_WDATA[36] , 
        \AXI_IF_0_BIF_1_WDATA[35] , \AXI_IF_0_BIF_1_WDATA[34] , 
        \AXI_IF_0_BIF_1_WDATA[33] , \AXI_IF_0_BIF_1_WDATA[32] , 
        \AXI_IF_0_BIF_1_WDATA[31] , \AXI_IF_0_BIF_1_WDATA[30] , 
        \AXI_IF_0_BIF_1_WDATA[29] , \AXI_IF_0_BIF_1_WDATA[28] , 
        \AXI_IF_0_BIF_1_WDATA[27] , \AXI_IF_0_BIF_1_WDATA[26] , 
        \AXI_IF_0_BIF_1_WDATA[25] , \AXI_IF_0_BIF_1_WDATA[24] , 
        \AXI_IF_0_BIF_1_WDATA[23] , \AXI_IF_0_BIF_1_WDATA[22] , 
        \AXI_IF_0_BIF_1_WDATA[21] , \AXI_IF_0_BIF_1_WDATA[20] , 
        \AXI_IF_0_BIF_1_WDATA[19] , \AXI_IF_0_BIF_1_WDATA[18] , 
        \AXI_IF_0_BIF_1_WDATA[17] , \AXI_IF_0_BIF_1_WDATA[16] , 
        \AXI_IF_0_BIF_1_WDATA[15] , \AXI_IF_0_BIF_1_WDATA[14] , 
        \AXI_IF_0_BIF_1_WDATA[13] , \AXI_IF_0_BIF_1_WDATA[12] , 
        \AXI_IF_0_BIF_1_WDATA[11] , \AXI_IF_0_BIF_1_WDATA[10] , 
        \AXI_IF_0_BIF_1_WDATA[9] , \AXI_IF_0_BIF_1_WDATA[8] , 
        \AXI_IF_0_BIF_1_WDATA[7] , \AXI_IF_0_BIF_1_WDATA[6] , 
        \AXI_IF_0_BIF_1_WDATA[5] , \AXI_IF_0_BIF_1_WDATA[4] , 
        \AXI_IF_0_BIF_1_WDATA[3] , \AXI_IF_0_BIF_1_WDATA[2] , 
        \AXI_IF_0_BIF_1_WDATA[1] , \AXI_IF_0_BIF_1_WDATA[0] }), 
        .CMD_Decode_0_r_xfer_sizeoi({\CMD_Decode_0_r_xfer_sizeoi[8] , 
        \CMD_Decode_0_r_xfer_sizeoi[7] , 
        \CMD_Decode_0_r_xfer_sizeoi[6] , 
        \CMD_Decode_0_r_xfer_sizeoi[5] , 
        \CMD_Decode_0_r_xfer_sizeoi[4] }), 
        .AXI_IF_0_AHB_ADDR_reto_0_11(\AXI_IF_0_AHB_ADDR_reto_0[13] ), 
        .AXI_IF_0_AHB_ADDR_reto_0_23(\AXI_IF_0_AHB_ADDR_reto_0[25] ), 
        .AXI_IF_0_AHB_ADDR_reto_0_17(\AXI_IF_0_AHB_ADDR_reto_0[19] ), 
        .AXI_IF_0_AHB_ADDR_reto_0_24(\AXI_IF_0_AHB_ADDR_reto_0[26] ), 
        .AXI_IF_0_AHB_ADDR_reto_0_19(\AXI_IF_0_AHB_ADDR_reto_0[21] ), 
        .AXI_IF_0_AHB_ADDR_reto_0_25(\AXI_IF_0_AHB_ADDR_reto_0[27] ), 
        .AXI_IF_0_AHB_ADDR_reto_0_18(\AXI_IF_0_AHB_ADDR_reto_0[20] ), 
        .AXI_IF_0_AHB_ADDR_reto_0_0(\AXI_IF_0_AHB_ADDR_reto_0[2] ), 
        .AXI_IF_0_AHB_ADDR_reto_0_22(\AXI_IF_0_AHB_ADDR_reto_0[24] ), 
        .AXI_IF_0_AHB_ADDR_reto_0_5(\AXI_IF_0_AHB_ADDR_reto_0[7] ), 
        .AXI_IF_0_AHB_ADDR_reto_0_4(\AXI_IF_0_AHB_ADDR_reto_0[6] ), 
        .MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK), 
        .AXI_IF_0_BIF_1_RVALID_i_0(AXI_IF_0_BIF_1_RVALID_i_0), 
        .MDDR_TA_0_INIT_DONE(MDDR_TA_0_INIT_DONE), 
        .AXI_IF_0_BIF_1_RREADY(AXI_IF_0_BIF_1_RREADY), 
        .AXI_IF_0_BIF_1_RLAST_i_0(AXI_IF_0_BIF_1_RLAST_i_0), 
        .AXI_IF_0_BIF_1_WLAST(AXI_IF_0_BIF_1_WLAST), 
        .AXI_IF_0_WRITE_AHB(AXI_IF_0_WRITE_AHB), .AHB_ADDR_6_cry_2_0_Y(
        AHB_ADDR_6_cry_2_0_Y), .N_178_i_0(\AHB_IF_0.N_178_i_0 ), 
        .MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK_i_0(
        MDDR_TA_0_MSS_DDR_FIC_SUBSYSTEM_CLK_i_0), 
        .AXI_IF_0_BIF_1_AWREADY(AXI_IF_0_BIF_1_AWREADY), 
        .AXI_IF_0_BIF_1_WREADY(AXI_IF_0_BIF_1_WREADY), 
        .AXI_IF_0_BIF_1_ARVALID(AXI_IF_0_BIF_1_ARVALID), 
        .AXI_IF_0_BIF_1_RVALID(AXI_IF_0_BIF_1_RVALID), 
        .AXI_IF_0_BIF_1_ARREADY(AXI_IF_0_BIF_1_ARREADY), 
        .AXI_IF_0_BIF_1_WVALID(AXI_IF_0_BIF_1_WVALID), 
        .AXI_IF_0_BIF_1_AWVALID(AXI_IF_0_BIF_1_AWVALID), 
        .AHB_IF_0_AHB_BUSY(AHB_IF_0_AHB_BUSY), .AXI_IF_0_BIF_1_RLAST(
        AXI_IF_0_BIF_1_RLAST), .read_start_c(read_start_c), 
        .write_start_c(write_start_c));
    
endmodule
