/*-----------------------------------------------------------------------------
 Title      : Testbench 
-------------------------------------------------------------------------------
 File       : testbench.v
 Author     : Corporate Applications Engineering
 Company    : Microsemi Corporation
 Device     : SmartFusion2
 Standard   : Verilog
-------------------------------------------------------------------------------
Description: This testbench performs the following steps:
1 : Initialize LSRAM with incremental pattern
2 : Initiate the write operation
3 : Disable the write operation
4 : Initiate the read operation
5 : Disable the read operation.
-------------------------------------------------------------------------------
 Copyright (c) 2014   Microsemi Corporation
                      All rights reserved.
-------------------------------------------------------------------------------
 Revisions  : V1.0
-------------------------------------------------------------------------------*/

`timescale 1ps /1ps

`include "ddr3.v"

module testbench;

parameter SYSCLK_PERIOD = 10000; // 10MHz

reg SYSCLK;
reg NSYSRESET;

wire MDDR_CAS_N;
wire MDDR_CKE;
wire MDDR_CLK;
wire MDDR_CLK_N;
wire MDDR_CS_N;
wire MDDR_ODT;
wire MDDR_RAS_N;
wire MDDR_RESET_N;
wire MDDR_WE_N;	
wire [15:0] MDDR_ADDR;
wire [2:0]  MDDR_BA;
wire [1:0]  MDDR_DM_RDQS;
wire [1:0]  MDDR_DQS;
wire [1:0]  MDDR_DQS_N;
wire [15:0] MDDR_DQ;

wire MDDR_DQS_TMATCH_0_IN;
wire MDDR_DQS_TMATCH_0_OUT;
wire mddr_dqs_tmatch_0_out;
wire [2:0] COMMAND;

assign mddr_dqs_tmatch_0_out = MDDR_DQS_TMATCH_0_OUT;
assign COMMAND = {MDDR_RAS_N,MDDR_CAS_N,MDDR_WE_N};

initial
begin
    SYSCLK    = 1'b0;
    NSYSRESET = 1'b0;

    $display ("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++");
    $display ("Loading LSRAM from lsram.mem file");
    $display ("");
    $readmemh("lsram_512x64.mem",testbench.MDDR_TA_top_0.AXI_IF_0.Rdata_mem);
    $display (" Completed Loading LSRAM"); 
    $display ("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++");

    @(posedge testbench.MDDR_TA_top_0.AXI_IF_0.RESETn);

    /* 2KB write   */
    repeat(9500) @(posedge testbench.MDDR_TA_top_0.AXI_IF_0.CLK);
    force testbench.MDDR_TA_top_0.CMD_Decoder_0.command   = 8'b001_001_01; 

    /* Disable Write   */
    repeat(15) @(posedge testbench.MDDR_TA_top_0.AXI_IF_0.CLK);
    force testbench.MDDR_TA_top_0.CMD_Decoder_0.command   = 8'b000_000_00;
  
    /* 2KB Read   */
    repeat(5000) @(posedge testbench.MDDR_TA_top_0.AXI_IF_0.CLK);
    force testbench.MDDR_TA_top_0.CMD_Decoder_0. command   = 8'b001_001_10; 

    /* Disable Read   */
    repeat(15) @(posedge testbench.MDDR_TA_top_0.AXI_IF_0.CLK);
    force testbench.MDDR_TA_top_0.CMD_Decoder_0. command   = 8'b000_000_00;

end


/* DEVRST_N Signal gneration */

initial
begin
    #(SYSCLK_PERIOD * 10 )
        NSYSRESET = 1'b1;
end

/* 10MHz Clock Driver */

always @(SYSCLK)
    #(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;


/* Instantiate Unit Under Test:  MDDR_TA_top */

MDDR_TA_top MDDR_TA_top_0 (
    // Inputs
    .MDDR_DQS_TMATCH_0_IN(mddr_dqs_tmatch_0_out),
    .DEVRST_N(NSYSRESET),
	.MMUART_0_RXD_F2M({1{1'b0}}),
    // Outputs
    .MDDR_DQS_TMATCH_0_OUT(MDDR_DQS_TMATCH_0_OUT),
    .MDDR_CAS_N(MDDR_CAS_N ),
	.MDDR_CLK(MDDR_CLK ),
	.MDDR_CLK_N(MDDR_CLK_N ),
	.MDDR_CKE(MDDR_CKE ),
	.MDDR_CS_N(MDDR_CS_N ),
	.MDDR_ODT( MDDR_ODT),
	.MDDR_RAS_N( MDDR_RAS_N ),
	.MDDR_RESET_N(MDDR_RESET_N),
	.MDDR_WE_N(MDDR_WE_N),
	.MDDR_ADDR(MDDR_ADDR[15:0]),
	.MDDR_BA(MDDR_BA),
    .MMUART_0_TXD_M2F( ),

    // Inouts
	.MDDR_DM_RDQS(MDDR_DM_RDQS),
	.MDDR_DQS(MDDR_DQS),
	.MDDR_DQS_N(MDDR_DQS_N),
	.MDDR_DQ(MDDR_DQ)

    
);


/* ------------------------------------------------------------------------
Instantiate and connect DDR3 memory model. The design uses two instance of
ddr3 model with device width 8. 
---------------------------------------------------------------------------*/

ddr3 DDR3_0 (
	.rst_n(MDDR_RESET_N),
	.ck(MDDR_CLK),
	.ck_n(MDDR_CLK_N),
	
	.cke(MDDR_CKE),
	.cs_n(MDDR_CS_N),
	.ras_n(MDDR_RAS_N ),
	.cas_n(MDDR_CAS_N),
	.we_n(MDDR_WE_N),
	.addr(MDDR_ADDR[14:0]),
	.ba(MDDR_BA),
	.dm_tdqs(MDDR_DM_RDQS[0]),
	.dq(MDDR_DQ[7:0]),
	
	.dqs(MDDR_DQS[0]),
	.dqs_n(MDDR_DQS_N[0]),

	.odt(MDDR_ODT),
	.tdqs_n()
);

ddr3 DDR3_1 (
	.rst_n(MDDR_RESET_N),
	.ck(MDDR_CLK),
	.ck_n(MDDR_CLK_N),
	
	.cke(MDDR_CKE),
	.cs_n(MDDR_CS_N),
	.ras_n(MDDR_RAS_N ),
	.cas_n(MDDR_CAS_N),
	.we_n(MDDR_WE_N),
	.addr(MDDR_ADDR[14:0]),
	.ba(MDDR_BA),
	.dm_tdqs(MDDR_DM_RDQS[1]),
	.dq(MDDR_DQ[15:8]),
	
	.dqs(MDDR_DQS[1]),
	.dqs_n(MDDR_DQS_N[1]),

	.odt(MDDR_ODT),
	.tdqs_n()
);

endmodule