++++++++++++++++++++++++++++++++++
   Libero SoC 11.7 
++++++++++++++++++++++++++++++++++

Simulation :- This folder consists of Libero SoC design file and DDR Configuration file for Simulation. The design operates at 166 MHz.
Board_Test :- This folder consists of Libero SoC design file and DDR Configuration file for BOARD TEST. The design operates at 166.6 MHz



If you regenerates the SmartDesign testbench of Microsemi DDR3 SDRAM VIP Model,add the following code above “endmodule” in the generated SmartDesign testbench file, MDDR_VIP_Simulation.v.
MDDR_VIP_Simulation.v file is available at "MDDR_TA\component\work\MDDR_VIP_Simulation".


wire   [1:0]  MDDR_DM_RDQS;
wire   [15:0] MDDR_DQ;
wire   [1:0]  MDDR_DQS;
wire   [2:0]  COMMAND;

assign COMMAND = {MDDR_TA_top_0_MDDR_RAS_N,MDDR_TA_top_0_MDDR_CAS_N,MDDR_TA_top_0_MDDR_WE_N};

assign MDDR_DM_RDQS = MDDR_DM_RDQS_net_0;
assign MDDR_DQ      = MDDR_DQ_net_0;
assign MDDR_DQS     = MDDR_DQS_net_0;

initial
begin

    $display ("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++");
    $display ("Loading LSRAM from lsram.mem file");
    $display ("");
    $readmemh("lsram_512x64.mem",MDDR_VIP_Simulation.MDDR_TA_top_0.AXI_IF_0.Rdata_mem);
    $display (" Completed Loading LSRAM"); 
    $display ("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++");

    @(posedge MDDR_VIP_Simulation.MDDR_TA_top_0.AXI_IF_0.RESETn);

    /* 2KB write   */
    repeat(9500) @(posedge MDDR_VIP_Simulation.MDDR_TA_top_0.AXI_IF_0.CLK);
    force MDDR_VIP_Simulation.MDDR_TA_top_0.CMD_Decoder_0.command   = 8'b001_001_01; 

    /* Disable Write   */
    repeat(15) @(posedge MDDR_VIP_Simulation.MDDR_TA_top_0.AXI_IF_0.CLK);
    force MDDR_VIP_Simulation.MDDR_TA_top_0.CMD_Decoder_0.command   = 8'b000_000_00;
  
    /* 2KB Read   */
    repeat(5000) @(posedge MDDR_VIP_Simulation.MDDR_TA_top_0.AXI_IF_0.CLK);
    force MDDR_VIP_Simulation.MDDR_TA_top_0.CMD_Decoder_0.command   = 8'b001_001_10; 

    /* Disable Read   */
    repeat(15) @(posedge MDDR_VIP_Simulation.MDDR_TA_top_0.AXI_IF_0.CLK);
    force MDDR_VIP_Simulation.MDDR_TA_top_0.CMD_Decoder_0.command   = 8'b000_000_00;

end

