data DESIGN MDDR_TA_top
data HPATH 'D:/422_debug/designer/MDDR_TA_top'
data CPATH 'D:/422_debug/constraint/io'
data IOCPATH 'D:/422_debug/constraint/io'
data FPCPATH 'D:/422_debug/constraint/fp'
data FAM SmartFusion2
data DIE PA4M12000
data PACKAGE fc1152
data IO_DEFT_STD LVCMOS25
data RESTRICTPROBEPINS 1
data HYDRA_EXPORT_DATA 1
data HYDRA_PRESERVE_DATA_FILES 1
data ENABLE_AUTO_VERCHK 2
data ALICUTIL_BD 42
data RECORD_QUALIFIED_PATHS 0
data VCCI_1.2_VOLTR COM
data VCCI_1.5_VOLTR COM
data VCCI_1.8_VOLTR COM
data VCCI_2.5_VOLTR COM
data VCCI_3.3_VOLTR COM
data AFL 'D:/422_debug/designer/MDDR_TA_top/MDDR_TA_top.afl'
data ADL 'D:/422_debug/designer/MDDR_TA_top/MDDR_TA_top.adl'
data LOC 'D:/422_debug/designer/MDDR_TA_top/MDDR_TA_top.loc'
data SEG 'D:/422_debug/designer/MDDR_TA_top/MDDR_TA_top.seg'

