@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":461:4:461:9|Removing sequential instance FDDR_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":461:4:461:9|Removing sequential instance SDIF0_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":461:4:461:9|Removing sequential instance SDIF1_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":461:4:461:9|Removing sequential instance SDIF2_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreconfigp\7.0.105\rtl\vlog\core\coreconfigp.v":461:4:461:9|Removing sequential instance SDIF3_PENABLE of view:PrimLib.dffr(prim) in hierarchy view:work.CoreConfigP_Z9(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance SDIF_READY_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1089:4:1089:9|Removing sequential instance SDIF_RELEASED_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\hdl\ahb_if.v":71:0:71:5|Removing sequential instance DATAOUT[31:0] of view:PrimLib.dffre(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\hdl\ahb_if.v":71:0:71:5|Removing sequential instance HSEL of view:PrimLib.dffre(prim) in hierarchy view:work.AHB_IF_0s_1s_2s_3s_4294967292s_4294967293s_4294967294s_0s_Z1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\hdl\axi_if.v":258:0:258:5|Removing sequential instance AXI_BUSY of view:PrimLib.dffse(prim) in hierarchy view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z2(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\hdl\axi_if.v":501:0:501:5|Removing sequential instance done of view:PrimLib.dffre(prim) in hierarchy view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z2(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\hdl\axi_if.v":558:0:558:5|Removing sequential instance read_done of view:PrimLib.dffre(prim) in hierarchy view:work.AXI_IF_0s_1s_2s_3s_2s_3s_4294967292s_4294967292s_4294967293s_Z2(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHMASTLOCK of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHSIZE[2:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":163:0:163:5|Removing sequential instance regHWRITE of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because there are no references to its outputs 
@N: BN115 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":2703:2:2703:14|Removing instance masterstage_1 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_2(verilog) because there are no references to its outputs 
@N: BN115 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":2767:2:2767:14|Removing instance masterstage_2 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_1(verilog) because there are no references to its outputs 
@N: BN115 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":2831:2:2831:14|Removing instance masterstage_3 of view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_1_1_85_0s_0_1_0_0(verilog) because there are no references to its outputs 
@N: BN115 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v":2890:1:2890:12|Removing instance slavestage_0 of view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Removing sequential instance SDIF0_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Removing sequential instance SDIF0_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Removing sequential instance SDIF1_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Removing sequential instance SDIF1_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Removing sequential instance SDIF2_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Removing sequential instance SDIF2_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Removing sequential instance SDIF3_PHY_RESET_N_int of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Removing sequential instance SDIF3_CORE_RESET_N_0 of view:PrimLib.dffre(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1170:4:1170:9|Removing sequential instance sdif0_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1235:4:1235:9|Removing sequential instance sdif1_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1300:4:1300:9|Removing sequential instance sdif2_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":1365:4:1365:9|Removing sequential instance sdif3_state[3:0] of view:PrimLib.statemachine(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":79:4:79:9|Removing sequential instance masterDataInProg[3:0] of view:PrimLib.dffre(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":797:4:797:9|Removing sequential instance sdif0_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":811:4:811:9|Removing sequential instance sdif1_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":825:4:825:9|Removing sequential instance sdif2_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":839:4:839:9|Removing sequential instance sdif3_areset_n_clk_base of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":797:4:797:9|Removing sequential instance sdif0_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":811:4:811:9|Removing sequential instance sdif1_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":825:4:825:9|Removing sequential instance sdif2_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreresetp\7.0.104\rtl\vlog\core\coreresetp.v":839:4:839:9|Removing sequential instance sdif3_areset_n_q1 of view:PrimLib.dffr(prim) in hierarchy view:work.CoreResetP_Z10(verilog) because there are no references to its outputs 
@N: BN115 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v":87:56:87:68|Removing instance slave_arbiter of view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z5_0(verilog) because there are no references to its outputs 
@N: BN362 :"d:\libero_11_7_publish\m2s_ac422_liberov11p6_df\board_test\mddr_ta\component\actel\directcore\coreahblite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance arbRegSMCurrentState[15:0] of view:PrimLib.statemachine(prim) in hierarchy view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z5_0(verilog) because there are no references to its outputs 
@N: BN225 |Writing default property annotation file D:\Libero_11_7_publish\m2s_ac422_liberov11p6_df\Board_test\MDDR_TA\synthesis\MDDR_TA_top.sap.
