#--  Synopsys, Inc.
#--  Version J-2015.03M-SP1-2
#--  Project file D:\Libero_11_7_publish\m2s_ac422_liberov11p6_df\Board_test\MDDR_TA\synthesis\run_options.txt
#--  Written on Wed Mar 23 17:44:11 2016


#project files
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/hdl/AHB_IF.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/hdl/AXI_IF.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/hdl/CMD_Decode.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/CoreConfigP/7.0.105/rtl/vlog/core/coreconfigp.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp_pcie_hotreset.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/work/MDDR_TA/CCC_0/MDDR_TA_CCC_0_FCCC.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_feedthrough.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_16Sto1M.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rd_channel.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wresp_channel.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_matrix_m.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_ra_arbiter.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S_hgs_high.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S_hgs_low.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_ra_channel.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wa_arbiter.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S_hgs_high.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S_hgs_low.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wa_channel.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wd_channel.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_matrix_s.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_interconnect_ntom.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_master_stage.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_slave_stage.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/work/MDDR_TA/COREAXI_0/rtl/vlog/core/coreaxi.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/SgCore/OSC/2.0.101/osc_comps.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/work/MDDR_TA/FABOSC_0/MDDR_TA_FABOSC_0_OSC.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/work/MDDR_TA_MSS/MDDR_TA_MSS_syn.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/work/MDDR_TA_MSS/MDDR_TA_MSS.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_addrdec.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_defaultslavesm.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_masterstage.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavearbiter.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavestage.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_matrix4x16.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/work/MDDR_TA/MDDR_TA.v"
add_file -verilog "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/component/work/MDDR_TA_top/MDDR_TA_top.v"
add_file -constraint "D:/Libero_11_7_publish/m2s_ac422_liberov11p6_df/Board_test/MDDR_TA/constraint/ddr3_sdc.sdc"
add_file -fpga_constraint "MDDR_TA_top_syn.fdc"



#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std v2001

#device options
set_option -technology SmartFusion2
set_option -part M2S150T
set_option -package FC1152
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "MDDR_TA_top"

# mapper_options
set_option -frequency 166
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -srs_instrumentation 1

# actel_options
set_option -rw_check_on_ram 0

# Microsemi G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 12
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -disable_io_insertion 0
set_option -opcond COMTC
set_option -retiming 1
set_option -report_path 0
set_option -update_models_cp 0
set_option -preserve_registers 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 0

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./MDDR_TA_top.edn"
impl -active "synthesis"
