// available hyper connections - for debug and ip models
// timestamp: 1438680827


`ifndef SYN_HYPER_CONNECT
`define SYN_HYPER_CONNECT 1
module syn_hyper_connect(out) /* synthesis syn_black_box=1 syn_noprune=1 */;
parameter w = 1;
parameter tag = "xxx";
parameter dflt = 0;
parameter mustconnect = 1'b1;
output [w-1:0] out;
endmodule
`endif

module MDDR_TA_top_hyper_debug(dummy);
input dummy; /* avoid compiler error for no ports */

wire CLK_0;
syn_hyper_connect CLK_connect_0(CLK_0);
defparam CLK_connect_0.tag = "AXI_IF_0.CLK";


wire write_start_0;
syn_hyper_connect write_start_connect_0(write_start_0);
defparam write_start_connect_0.tag = "AXI_IF_0.write_start";


wire read_start_0;
syn_hyper_connect read_start_connect_0(read_start_0);
defparam read_start_connect_0.tag = "AXI_IF_0.read_start";


wire [31:0] AWADDR_0;
syn_hyper_connect AWADDR_connect_0(AWADDR_0);
defparam AWADDR_connect_0.w = 32;
defparam AWADDR_connect_0.tag = "AXI_IF_0.AWADDR";


wire AWVALID_ext_0;
syn_hyper_connect AWVALID_ext_connect_0(AWVALID_ext_0);
defparam AWVALID_ext_connect_0.tag = "AXI_IF_0.AWVALID_ext";


wire AWREADY_0;
syn_hyper_connect AWREADY_connect_0(AWREADY_0);
defparam AWREADY_connect_0.tag = "AXI_IF_0.AWREADY";


wire WLAST_0;
syn_hyper_connect WLAST_connect_0(WLAST_0);
defparam WLAST_connect_0.tag = "AXI_IF_0.WLAST";


wire WVALID_ext_0;
syn_hyper_connect WVALID_ext_connect_0(WVALID_ext_0);
defparam WVALID_ext_connect_0.tag = "AXI_IF_0.WVALID_ext";


wire [63:0] WDATA_0;
syn_hyper_connect WDATA_connect_0(WDATA_0);
defparam WDATA_connect_0.w = 64;
defparam WDATA_connect_0.tag = "AXI_IF_0.WDATA";


wire WREADY_0;
syn_hyper_connect WREADY_connect_0(WREADY_0);
defparam WREADY_connect_0.tag = "AXI_IF_0.WREADY";


wire [31:0] ARADDR_0;
syn_hyper_connect ARADDR_connect_0(ARADDR_0);
defparam ARADDR_connect_0.w = 32;
defparam ARADDR_connect_0.tag = "AXI_IF_0.ARADDR";


wire ARVALID_ext_0;
syn_hyper_connect ARVALID_ext_connect_0(ARVALID_ext_0);
defparam ARVALID_ext_connect_0.tag = "AXI_IF_0.ARVALID_ext";


wire ARREADY_0;
syn_hyper_connect ARREADY_connect_0(ARREADY_0);
defparam ARREADY_connect_0.tag = "AXI_IF_0.ARREADY";


wire [63:0] RDATA_0;
syn_hyper_connect RDATA_connect_0(RDATA_0);
defparam RDATA_connect_0.w = 64;
defparam RDATA_connect_0.tag = "AXI_IF_0.RDATA";


wire RLAST_0;
syn_hyper_connect RLAST_connect_0(RLAST_0);
defparam RLAST_connect_0.tag = "AXI_IF_0.RLAST";


wire RVALID_0;
syn_hyper_connect RVALID_connect_0(RVALID_0);
defparam RVALID_connect_0.tag = "AXI_IF_0.RVALID";


wire RREADY_0;
syn_hyper_connect RREADY_connect_0(RREADY_0);
defparam RREADY_connect_0.tag = "AXI_IF_0.RREADY";


wire w_start_0;
syn_hyper_connect w_start_connect_0(w_start_0);
defparam w_start_connect_0.tag = "AXI_IF_0.w_start";


wire r_start_0;
syn_hyper_connect r_start_connect_0(r_start_0);
defparam r_start_connect_0.tag = "AXI_IF_0.r_start";


wire read_idle_0;
syn_hyper_connect read_idle_connect_0(read_idle_0);
defparam read_idle_connect_0.tag = "AXI_IF_0.read_idle";


wire read_read0_0;
syn_hyper_connect read_read0_connect_0(read_read0_0);
defparam read_read0_connect_0.tag = "AXI_IF_0.read_read0";


wire read_read1_0;
syn_hyper_connect read_read1_connect_0(read_read1_0);
defparam read_read1_connect_0.tag = "AXI_IF_0.read_read1";


wire read1_idle_0;
syn_hyper_connect read1_idle_connect_0(read1_idle_0);
defparam read1_idle_connect_0.tag = "AXI_IF_0.read1_idle";


wire [7:0] ujtag_wrapper_uireg_0;
syn_hyper_connect ujtag_wrapper_uireg_connect_0(ujtag_wrapper_uireg_0);
defparam ujtag_wrapper_uireg_connect_0.w = 8;
defparam ujtag_wrapper_uireg_connect_0.tag = "ident_coreinst.comm_block_INST.jtagi.ujtag_wrapper_uireg";


wire ujtag_wrapper_urstb_0;
syn_hyper_connect ujtag_wrapper_urstb_connect_0(ujtag_wrapper_urstb_0);
defparam ujtag_wrapper_urstb_connect_0.tag = "ident_coreinst.comm_block_INST.jtagi.ujtag_wrapper_urstb";


wire ujtag_wrapper_udrupd_0;
syn_hyper_connect ujtag_wrapper_udrupd_connect_0(ujtag_wrapper_udrupd_0);
defparam ujtag_wrapper_udrupd_connect_0.tag = "ident_coreinst.comm_block_INST.jtagi.ujtag_wrapper_udrupd";


wire ujtag_wrapper_udrck_0;
syn_hyper_connect ujtag_wrapper_udrck_connect_0(ujtag_wrapper_udrck_0);
defparam ujtag_wrapper_udrck_connect_0.tag = "ident_coreinst.comm_block_INST.jtagi.ujtag_wrapper_udrck";


wire ujtag_wrapper_udrcap_0;
syn_hyper_connect ujtag_wrapper_udrcap_connect_0(ujtag_wrapper_udrcap_0);
defparam ujtag_wrapper_udrcap_connect_0.tag = "ident_coreinst.comm_block_INST.jtagi.ujtag_wrapper_udrcap";


wire ujtag_wrapper_udrsh_0;
syn_hyper_connect ujtag_wrapper_udrsh_connect_0(ujtag_wrapper_udrsh_0);
defparam ujtag_wrapper_udrsh_connect_0.tag = "ident_coreinst.comm_block_INST.jtagi.ujtag_wrapper_udrsh";


wire ujtag_wrapper_utdi_0;
syn_hyper_connect ujtag_wrapper_utdi_connect_0(ujtag_wrapper_utdi_0);
defparam ujtag_wrapper_utdi_connect_0.tag = "ident_coreinst.comm_block_INST.jtagi.ujtag_wrapper_utdi";

endmodule
