module SimDRAM(
    // Inputs
    DRAM_ADDR,
    DRAM_BA,
    DRAM_CAS_N,
    DRAM_CKE,
    DRAM_CLK,
    DRAM_CLK_N,
    DRAM_CS_N,
    DRAM_ODT,
    DRAM_RAS_N,
    DRAM_RESET_N,
    DRAM_WE_N,
    DRAM_DM,
    // Outputs
    DRAM_RDQS_N,
    // Inouts
    DRAM_DQ,
    DRAM_DQS,
    DRAM_DQS_N,
    DRAM_DM_RDQS
);

  parameter MEMORY            = 0;              // DRAM Memory Type
  parameter DQ_BITS           = 16;             // Data bus width
  parameter ADDR_BITS         = 16;             // Address bus width
  parameter BA_BITS           = 3;              // Bank address bits

  

  //--------------------------------------------------------------------
  // Input
  //--------------------------------------------------------------------
  input  [ADDR_BITS-1 : 0]    DRAM_ADDR;
  input  [BA_BITS-1 : 0]      DRAM_BA;
  input                       DRAM_CAS_N;
  input                       DRAM_CKE;
  input                       DRAM_CLK;
  input                       DRAM_CLK_N;
  input                       DRAM_CS_N;
  input                       DRAM_ODT;
  input                       DRAM_RAS_N;
  input                       DRAM_RESET_N;
  input                       DRAM_WE_N;
  input  [DQ_BITS/8-1 : 0]    DRAM_DM;
  
  output [DQ_BITS/8-1 : 0]    DRAM_RDQS_N;
  //--------------------------------------------------------------------
  // Inout
  //--------------------------------------------------------------------
  inout  [DQ_BITS-1 : 0]      DRAM_DQ;
  inout  [DQ_BITS/8-1 : 0]    DRAM_DQS;
  inout  [DQ_BITS/8-1 : 0]    DRAM_DQS_N;
  inout  [DQ_BITS/8-1 : 0]    DRAM_DM_RDQS;
endmodule
