Detailed Resource Usage
Module Name,Fabric 4LUT,Fabric DFF,Interface 4LUT,Interface DFF,Single-Ended I/O,Differential I/O Pairs,LSRAM 18K,PLLs and CCCs,Chip Globals,MSS,Multi-Mode UART,MDDR Controller,RCOSC_50MHZ
AXI_IF_0/Primitives,447,310,72,72,0,0,2,0,0,0,0,0,0
MDDR_TA_0/CORERESETP_0/Primitives,32,51,0,0,0,0,0,0,3,0,0,0,0
MDDR_TA_0/CORECONFIGP_0/Primitives,44,75,0,0,0,0,0,0,0,0,0,0,0
MDDR_TA_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/Primitives,23,5,0,0,0,0,0,0,0,0,0,0,0
MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/Primitives,40,50,0,0,0,0,0,0,0,0,0,0,0
AHB_IF_0/Primitives,41,118,0,0,0,0,0,0,0,0,0,0,0
Primitives/Primitives,1,0,0,0,2,0,0,0,0,0,0,0,0
MDDR_TA_0/MDDR_TA_MSS_0/Primitives,2,0,0,0,48,3,0,0,2,1,1,1,0
CMD_Decode_0/Primitives,13,21,0,0,0,0,0,0,0,0,0,0,0
MDDR_TA_0/CoreAHBLite_0/matrix4x16/slavestage_16/Primitives,36,1,0,0,0,0,0,0,0,0,0,0,0
MDDR_TA_0/Primitives,0,0,0,0,0,0,0,0,1,0,0,0,0
MDDR_TA_0/FABOSC_0/Primitives,0,0,0,0,0,0,0,0,1,0,0,0,1
MDDR_TA_0/CCC_0/Primitives,0,0,0,0,0,0,0,1,2,0,0,0,0
MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/default_slave_sm/Primitives,1,1,0,0,0,0,0,0,0,0,0,0,0
