<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
<doc>
<title>Timing Report Min Delay Analysis
</title>
<text>SmartTime Version 11.7.0.119</text>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.7 (Version 11.7.0.119)</text>
<text>Date: Wed Mar 23 17:54:18 2016
</text>
<table>
<header>
</header>
<row>
 <cell>Design</cell>
 <cell>MDDR_TA_top</cell>
</row>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Die</cell>
 <cell>M2S150T</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>1152 FC</cell>
</row>
<row>
 <cell>Temperature Range</cell>
 <cell>0 - 85 C</cell>
</row>
<row>
 <cell>Voltage Range</cell>
 <cell>1.14 - 1.26 V</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
<row>
 <cell>Design State</cell>
 <cell>Post-Layout</cell>
</row>
<row>
 <cell>Data source</cell>
 <cell>Production</cell>
</row>
<row>
 <cell>Min Operating Conditions</cell>
 <cell>BEST - 1.26 V - 0 C</cell>
</row>
<row>
 <cell>Max Operating Conditions</cell>
 <cell>WORST - 1.14 V - 85 C</cell>
</row>
<row>
 <cell>Scenario for Timing Analysis</cell>
 <cell>Primary</cell>
</row>
</table>
<text></text>
<section>
<name>Summary</name>
<table>
<header>
 <cell>Clock Domain</cell>
 <cell>Period (ns)</cell>
 <cell>Frequency (MHz)</cell>
 <cell>Required Period (ns)</cell>
 <cell>Required Frequency (MHz)</cell>
 <cell>External Setup (ns)</cell>
 <cell>External Hold (ns)</cell>
 <cell>Min Clock-To-Out (ns)</cell>
 <cell>Max Clock-To-Out (ns)</cell>
</header>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>4.899</cell>
 <cell>204.123</cell>
 <cell>6.002</cell>
 <cell>166.611</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>5.351</cell>
 <cell>9.356</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>5.100</cell>
 <cell>196.078</cell>
 <cell>6.002</cell>
 <cell>166.611</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>6.983</cell>
 <cell>11.847</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>6.312</cell>
 <cell>158.428</cell>
 <cell>20.000</cell>
 <cell>50.000</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
<row>
 <cell>FIC2_APB_CLK</cell>
 <cell>8.818</cell>
 <cell>113.404</cell>
 <cell>24.000</cell>
 <cell>41.667</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
<text></text>
<table>
<header>
 <cell></cell>
 <cell>Min Delay (ns)</cell>
 <cell>Max Delay (ns)</cell>
</header>
<row>
 <cell>Input to Output</cell>
 <cell>N/A</cell>
 <cell>N/A</cell>
</row>
</table>
</section>
<section>
<name>Clock Domain MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MDDR_TA_0/CORERESETP_0/release_sdif0_core_q1:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/release_sdif0_core_clk_base:D</cell>
 <cell>0.293</cell>
 <cell>0.246</cell>
 <cell>3.599</cell>
 <cell>3.353</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>MDDR_TA_0/CORERESETP_0/RESET_N_M2F_q1:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/RESET_N_M2F_clk_base:D</cell>
 <cell>0.293</cell>
 <cell>0.248</cell>
 <cell>3.592</cell>
 <cell>3.344</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>MDDR_TA_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_q1:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_clk_base:D</cell>
 <cell>0.291</cell>
 <cell>0.253</cell>
 <cell>3.597</cell>
 <cell>3.344</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sm0_state[0]:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sm0_state[1]:D</cell>
 <cell>0.297</cell>
 <cell>0.256</cell>
 <cell>3.618</cell>
 <cell>3.362</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>MDDR_TA_0/CORERESETP_0/CONFIG2_DONE_q1:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/CONFIG2_DONE_clk_base:D</cell>
 <cell>0.290</cell>
 <cell>0.258</cell>
 <cell>3.611</cell>
 <cell>3.353</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MDDR_TA_0/CORERESETP_0/release_sdif0_core_q1:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MDDR_TA_0/CORERESETP_0/release_sdif0_core_clk_base:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.599</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.353</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.246</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.131</cell>
 <cell>2.131</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>2.309</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.088</cell>
 <cell>2.397</cell>
 <cell>9</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.365</cell>
 <cell>2.762</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>2.958</cell>
 <cell>8</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/release_sdif0_core_q1:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.348</cell>
 <cell>3.306</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/release_sdif0_core_q1:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.054</cell>
 <cell>3.360</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/release_sdif0_core_clk_base:D</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CORERESETP_0/release_sdif3_core_q1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.239</cell>
 <cell>3.599</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.599</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.131</cell>
 <cell>2.131</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>2.309</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.088</cell>
 <cell>2.397</cell>
 <cell>9</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.365</cell>
 <cell>2.762</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>2.958</cell>
 <cell>8</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/release_sdif0_core_clk_base:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.395</cell>
 <cell>3.353</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/release_sdif0_core_clk_base:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>3.353</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.353</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Clock to Out (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell>MMUART_0_TXD</cell>
 <cell>1.896</cell>
 <cell></cell>
 <cell>5.351</cell>
 <cell></cell>
 <cell>5.351</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MMUART_0_TXD</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.351</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.131</cell>
 <cell>2.131</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>2.309</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.088</cell>
 <cell>2.397</cell>
 <cell>9</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.365</cell>
 <cell>2.762</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>2.958</cell>
 <cell>8</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.289</cell>
 <cell>3.247</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.130</cell>
 <cell>3.377</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.078</cell>
 <cell>3.455</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MMUART0_TXD_USBC_DIR_MGPIO27B_OUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MSS_120_IP</cell>
 <cell>+</cell>
 <cell>0.412</cell>
 <cell>3.867</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MMUART_0_TXD_PAD/U_IOPAD:D</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST_MMUART0_TXD_USBC_DIR_MGPIO27B_OUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>3.867</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MMUART_0_TXD_PAD/U_IOPAD:PAD</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_TRI</cell>
 <cell>+</cell>
 <cell>1.484</cell>
 <cell>5.351</cell>
 <cell>0</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MMUART_0_TXD</cell>
 <cell>net</cell>
 <cell>MMUART_0_TXD</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>5.351</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.351</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.131</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MMUART_0_TXD</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MDDR_TA_0/CORERESETP_0/FDDR_CORE_RESET_N_int:CLK</cell>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:FPGA_MDDR_ARESET_N</cell>
 <cell>0.683</cell>
 <cell>2.364</cell>
 <cell>3.976</cell>
 <cell>1.612</cell>
 <cell>-1.852</cell>
 <cell>-0.171</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MDDR_TA_0/CORERESETP_0/FDDR_CORE_RESET_N_int:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:FPGA_MDDR_ARESET_N</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.976</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>1.612</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>2.364</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.131</cell>
 <cell>2.131</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>2.309</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.088</cell>
 <cell>2.397</cell>
 <cell>9</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.368</cell>
 <cell>2.765</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>2.961</cell>
 <cell>5</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/FDDR_CORE_RESET_N_int:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.332</cell>
 <cell>3.293</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/FDDR_CORE_RESET_N_int:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.054</cell>
 <cell>3.347</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/MDDR_DDR_AXI_S_CORE_RESET_N:B</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CORERESETP_0/FDDR_CORE_RESET_N_int</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.216</cell>
 <cell>3.563</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/MDDR_DDR_AXI_S_CORE_RESET_N:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2</cell>
 <cell>+</cell>
 <cell>0.046</cell>
 <cell>3.609</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_284:A</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CORERESETP_0_MDDR_DDR_AXI_S_CORE_RESET_N</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.205</cell>
 <cell>3.814</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_284:IPA</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.121</cell>
 <cell>3.935</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:FPGA_MDDR_ARESET_N</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/FPGA_MDDR_ARESET_N_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.041</cell>
 <cell>3.976</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.976</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.131</cell>
 <cell>2.131</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>2.309</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.088</cell>
 <cell>2.397</cell>
 <cell>9</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.365</cell>
 <cell>2.762</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>2.958</cell>
 <cell>8</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.289</cell>
 <cell>3.247</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.130</cell>
 <cell>3.377</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.087</cell>
 <cell>3.464</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:FPGA_MDDR_ARESET_N</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:MSS_120_IP</cell>
 <cell>+</cell>
 <cell>-1.852</cell>
 <cell>1.612</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>1.612</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT to MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<text>No Path</text>
</section>
<section>
<name>SET MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2 to MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>AHB_IF_0/HWRITE:CLK</cell>
 <cell>MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHWRITE:D</cell>
 <cell>0.498</cell>
 <cell>0.450</cell>
 <cell>3.795</cell>
 <cell>3.345</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>AHB_IF_0/HADDR[30]:CLK</cell>
 <cell>MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[30]:D</cell>
 <cell>0.525</cell>
 <cell>0.512</cell>
 <cell>3.845</cell>
 <cell>3.333</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>AHB_IF_0/HADDR_ret_24:CLK</cell>
 <cell>MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[24]:D</cell>
 <cell>0.590</cell>
 <cell>0.561</cell>
 <cell>3.898</cell>
 <cell>3.337</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>AHB_IF_0/HADDR_ret_15:CLK</cell>
 <cell>MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHADDR[27]:D</cell>
 <cell>0.613</cell>
 <cell>0.581</cell>
 <cell>3.926</cell>
 <cell>3.345</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>AHB_IF_0/HADDR[31]:CLK</cell>
 <cell>MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/SDATASELInt[9]:D</cell>
 <cell>0.687</cell>
 <cell>0.659</cell>
 <cell>4.000</cell>
 <cell>3.341</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: AHB_IF_0/HWRITE:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHWRITE:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.795</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.345</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.450</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.128</cell>
 <cell>2.128</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.179</cell>
 <cell>2.307</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.088</cell>
 <cell>2.395</cell>
 <cell>16</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB12:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.364</cell>
 <cell>2.759</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB12:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>2.955</cell>
 <cell>39</cell>
 <cell>r</cell>
</row>
<row>
 <cell>AHB_IF_0/HWRITE:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB12_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.342</cell>
 <cell>3.297</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>AHB_IF_0/HWRITE:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.067</cell>
 <cell>3.364</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHWRITE:D</cell>
 <cell>net</cell>
 <cell>AHB_IF_0_BIF_1_HWRITE</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.431</cell>
 <cell>3.795</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.795</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.131</cell>
 <cell>2.131</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>2.309</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.088</cell>
 <cell>2.397</cell>
 <cell>9</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB5:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.358</cell>
 <cell>2.755</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB5:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>2.951</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHWRITE:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB5_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.394</cell>
 <cell>3.345</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CoreAHBLite_0/matrix4x16/masterstage_0/regHWRITE:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>3.345</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.345</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET FIC2_APB_CLK to MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/control_reg_1[1]:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/CONFIG2_DONE_q1:D</cell>
 <cell>0.536</cell>
 <cell>25.312</cell>
 <cell>4.674</cell>
 <cell>-20.638</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/control_reg_1[0]:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/CONFIG1_DONE_q1:D</cell>
 <cell>0.545</cell>
 <cell>25.323</cell>
 <cell>4.676</cell>
 <cell>-20.647</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MDDR_TA_0/CORECONFIGP_0/control_reg_1[1]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MDDR_TA_0/CORERESETP_0/CONFIG2_DONE_q1:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.674</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>-20.638</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>25.312</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_APB_CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.999</cell>
 <cell>2.999</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.221</cell>
 <cell>3.220</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.371</cell>
 <cell>3.591</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>3.787</cell>
 <cell>17</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORECONFIGP_0/control_reg_1[1]:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.351</cell>
 <cell>4.138</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORECONFIGP_0/control_reg_1[1]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.067</cell>
 <cell>4.205</cell>
 <cell>2</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/CONFIG2_DONE_q1:D</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0_CONFIG2_DONE</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.469</cell>
 <cell>4.674</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.674</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Min Delay Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-24.000</cell>
 <cell>-24.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>-24.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.131</cell>
 <cell>-21.869</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>-21.691</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.088</cell>
 <cell>-21.603</cell>
 <cell>9</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.366</cell>
 <cell>-21.237</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>-21.041</cell>
 <cell>12</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/CONFIG2_DONE_q1:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.403</cell>
 <cell>-20.638</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/CONFIG2_DONE_q1:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>-20.638</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-20.638</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Clock Domain MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>AHB_IF_0/HADDR_int[4]:CLK</cell>
 <cell>AHB_IF_0/HADDR_ret_44:D</cell>
 <cell>0.282</cell>
 <cell>0.240</cell>
 <cell>3.603</cell>
 <cell>3.363</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>AHB_IF_0/HADDR_int[13]:CLK</cell>
 <cell>AHB_IF_0/HADDR_ret:D</cell>
 <cell>0.298</cell>
 <cell>0.250</cell>
 <cell>3.610</cell>
 <cell>3.360</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>AHB_IF_0/HADDR_int[25]:CLK</cell>
 <cell>AHB_IF_0/HADDR_ret_3:D</cell>
 <cell>0.298</cell>
 <cell>0.250</cell>
 <cell>3.611</cell>
 <cell>3.361</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>AHB_IF_0/HADDR_int[5]:CLK</cell>
 <cell>AHB_IF_0/HADDR_ret_40:D</cell>
 <cell>0.298</cell>
 <cell>0.250</cell>
 <cell>3.611</cell>
 <cell>3.361</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>AHB_IF_0/HADDR_int[17]:CLK</cell>
 <cell>AHB_IF_0/HADDR_ret_36:D</cell>
 <cell>0.291</cell>
 <cell>0.251</cell>
 <cell>3.605</cell>
 <cell>3.354</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: AHB_IF_0/HADDR_int[4]:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: AHB_IF_0/HADDR_ret_44:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.603</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.363</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.240</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.128</cell>
 <cell>2.128</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.179</cell>
 <cell>2.307</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.088</cell>
 <cell>2.395</cell>
 <cell>16</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB14:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.359</cell>
 <cell>2.754</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB14:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>2.950</cell>
 <cell>12</cell>
 <cell>r</cell>
</row>
<row>
 <cell>AHB_IF_0/HADDR_int[4]:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB14_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.371</cell>
 <cell>3.321</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>AHB_IF_0/HADDR_int[4]:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.057</cell>
 <cell>3.378</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>AHB_IF_0/HADDR_ret_44:D</cell>
 <cell>net</cell>
 <cell>AHB_IF_0/HADDR_int[4]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.225</cell>
 <cell>3.603</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.603</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.128</cell>
 <cell>2.128</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.179</cell>
 <cell>2.307</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.088</cell>
 <cell>2.395</cell>
 <cell>16</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB14:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.359</cell>
 <cell>2.754</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB14:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>2.950</cell>
 <cell>12</cell>
 <cell>r</cell>
</row>
<row>
 <cell>AHB_IF_0/HADDR_ret_44:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB14_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.413</cell>
 <cell>3.363</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>AHB_IF_0/HADDR_ret_44:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>3.363</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.363</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Clock to Out (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>CMD_Decode_0/read_start:CLK</cell>
 <cell>read_start</cell>
 <cell>3.666</cell>
 <cell></cell>
 <cell>6.983</cell>
 <cell></cell>
 <cell>6.983</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>CMD_Decode_0/write_start:CLK</cell>
 <cell>write_start</cell>
 <cell>3.842</cell>
 <cell></cell>
 <cell>7.154</cell>
 <cell></cell>
 <cell>7.154</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: CMD_Decode_0/read_start:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: read_start</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.983</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.128</cell>
 <cell>2.128</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.179</cell>
 <cell>2.307</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.088</cell>
 <cell>2.395</cell>
 <cell>16</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.370</cell>
 <cell>2.765</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>2.961</cell>
 <cell>34</cell>
 <cell>r</cell>
</row>
<row>
 <cell>CMD_Decode_0/read_start:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.356</cell>
 <cell>3.317</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>CMD_Decode_0/read_start:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.054</cell>
 <cell>3.371</cell>
 <cell>2</cell>
 <cell>r</cell>
</row>
<row>
 <cell>read_start_obuf/U0/U_IOOUTFF:A</cell>
 <cell>net</cell>
 <cell>read_start_c</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>1.889</cell>
 <cell>5.260</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>read_start_obuf/U0/U_IOOUTFF:Y</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOOUTFF_BYPASS</cell>
 <cell>+</cell>
 <cell>0.219</cell>
 <cell>5.479</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>read_start_obuf/U0/U_IOPAD:D</cell>
 <cell>net</cell>
 <cell>read_start_obuf/U0/DOUT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>5.479</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>read_start_obuf/U0/U_IOPAD:PAD</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IOPAD_TRI</cell>
 <cell>+</cell>
 <cell>1.504</cell>
 <cell>6.983</cell>
 <cell>0</cell>
 <cell>r</cell>
</row>
<row>
 <cell>read_start</cell>
 <cell>net</cell>
 <cell>read_start</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>6.983</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>6.983</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.128</cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>read_start</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>N/C</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/INST_RAM1K18_IP:B_DIN[7]</cell>
 <cell>0.634</cell>
 <cell>0.664</cell>
 <cell>4.089</cell>
 <cell>3.425</cell>
 <cell>0.047</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/INST_RAM1K18_IP:B_DIN[15]</cell>
 <cell>0.656</cell>
 <cell>0.679</cell>
 <cell>4.111</cell>
 <cell>3.432</cell>
 <cell>0.054</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_1/INST_RAM1K18_IP:B_DIN[5]</cell>
 <cell>0.661</cell>
 <cell>0.683</cell>
 <cell>4.116</cell>
 <cell>3.433</cell>
 <cell>0.054</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/INST_RAM1K18_IP:B_DIN[17]</cell>
 <cell>0.656</cell>
 <cell>0.690</cell>
 <cell>4.111</cell>
 <cell>3.421</cell>
 <cell>0.043</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/INST_RAM1K18_IP:B_DIN[16]</cell>
 <cell>0.674</cell>
 <cell>0.694</cell>
 <cell>4.129</cell>
 <cell>3.435</cell>
 <cell>0.057</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: AXI_IF_0/Rdata_mem_Rdata_mem_0_0/INST_RAM1K18_IP:B_DIN[7]</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.089</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>3.425</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.664</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.131</cell>
 <cell>2.131</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.178</cell>
 <cell>2.309</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.088</cell>
 <cell>2.397</cell>
 <cell>9</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.365</cell>
 <cell>2.762</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>2.958</cell>
 <cell>8</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:B</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL0_INST/U0_RGB1_RGB1_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.289</cell>
 <cell>3.247</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_198:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.130</cell>
 <cell>3.377</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_BASE</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/CLK_BASE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.078</cell>
 <cell>3.455</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:F_RDATA_HRDATA01[7]</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:MSS_120_IP</cell>
 <cell>+</cell>
 <cell>0.020</cell>
 <cell>3.475</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/CFG_29:B</cell>
 <cell>net</cell>
 <cell>AXI_IF_0_BIF_1_RDATA[7]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.459</cell>
 <cell>3.934</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/CFG_29:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:CFG2_IP_BC</cell>
 <cell>+</cell>
 <cell>0.124</cell>
 <cell>4.058</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/INST_RAM1K18_IP:B_DIN[7]</cell>
 <cell>net</cell>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/B_DIN_net[7]</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.031</cell>
 <cell>4.089</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>4.089</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL2</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell></cell>
 <cell>Clock generation</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.128</cell>
 <cell>2.128</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.179</cell>
 <cell>2.307</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.088</cell>
 <cell>2.395</cell>
 <cell>16</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB2:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.369</cell>
 <cell>2.764</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB2:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>2.960</cell>
 <cell>28</cell>
 <cell>r</cell>
</row>
<row>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/FF_24:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CCC_0/GL2_INST/U0_RGB1_RGB2_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.326</cell>
 <cell>3.286</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/FF_24:IPCLKn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE_IP_CLK</cell>
 <cell>+</cell>
 <cell>0.037</cell>
 <cell>3.323</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/INST_RAM1K18_IP:B_CLK</cell>
 <cell>net</cell>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/B_CLK_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.055</cell>
 <cell>3.378</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>AXI_IF_0/Rdata_mem_Rdata_mem_0_0/INST_RAM1K18_IP:B_DIN[7]</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:RAM1K18_IP</cell>
 <cell>+</cell>
 <cell>0.047</cell>
 <cell>3.425</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.425</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
</section>
<section>
<name>Clock Domain MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr_enable_q1:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr_enable_rcosc:D</cell>
 <cell>0.369</cell>
 <cell>0.322</cell>
 <cell>5.534</cell>
 <cell>5.212</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[0]:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[0]:D</cell>
 <cell>0.393</cell>
 <cell>0.354</cell>
 <cell>5.558</cell>
 <cell>5.204</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[4]:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[4]:D</cell>
 <cell>0.402</cell>
 <cell>0.362</cell>
 <cell>5.572</cell>
 <cell>5.210</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[10]:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[10]:D</cell>
 <cell>0.402</cell>
 <cell>0.362</cell>
 <cell>5.574</cell>
 <cell>5.212</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[2]:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[2]:D</cell>
 <cell>0.402</cell>
 <cell>0.362</cell>
 <cell>5.573</cell>
 <cell>5.211</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MDDR_TA_0/CORERESETP_0/count_ddr_enable_q1:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MDDR_TA_0/CORERESETP_0/count_ddr_enable_rcosc:D</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.534</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>5.212</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.322</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.866</cell>
 <cell>0.866</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.095</cell>
 <cell>0.961</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.066</cell>
 <cell>4.027</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.221</cell>
 <cell>4.248</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.370</cell>
 <cell>4.618</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>4.814</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr_enable_q1:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.351</cell>
 <cell>5.165</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr_enable_q1:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.067</cell>
 <cell>5.232</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr_enable_rcosc:D</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr_enable_q1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.302</cell>
 <cell>5.534</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.534</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.866</cell>
 <cell>0.866</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.095</cell>
 <cell>0.961</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.066</cell>
 <cell>4.027</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.221</cell>
 <cell>4.248</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.370</cell>
 <cell>4.618</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>4.814</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr_enable_rcosc:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.398</cell>
 <cell>5.212</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr_enable_rcosc:D</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>5.212</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.212</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Removal (ns)</cell>
 <cell>Skew (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr_enable_rcosc:ALn</cell>
 <cell>3.658</cell>
 <cell>3.618</cell>
 <cell>8.830</cell>
 <cell>5.212</cell>
 <cell>0.000</cell>
 <cell>-0.040</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/ddr_settled:ALn</cell>
 <cell>3.658</cell>
 <cell>3.618</cell>
 <cell>8.830</cell>
 <cell>5.212</cell>
 <cell>0.000</cell>
 <cell>-0.040</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[10]:ALn</cell>
 <cell>3.658</cell>
 <cell>3.618</cell>
 <cell>8.830</cell>
 <cell>5.212</cell>
 <cell>0.000</cell>
 <cell>-0.040</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[12]:ALn</cell>
 <cell>3.658</cell>
 <cell>3.618</cell>
 <cell>8.830</cell>
 <cell>5.212</cell>
 <cell>0.000</cell>
 <cell>-0.040</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr[2]:ALn</cell>
 <cell>3.658</cell>
 <cell>3.619</cell>
 <cell>8.830</cell>
 <cell>5.211</cell>
 <cell>0.000</cell>
 <cell>-0.039</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MDDR_TA_0/CORERESETP_0/count_ddr_enable_rcosc:ALn</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>8.830</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>5.212</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>3.618</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.866</cell>
 <cell>0.866</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.095</cell>
 <cell>0.961</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.066</cell>
 <cell>4.027</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.221</cell>
 <cell>4.248</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.370</cell>
 <cell>4.618</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>4.814</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.358</cell>
 <cell>5.172</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.054</cell>
 <cell>5.226</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIGC0B:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.461</cell>
 <cell>7.687</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIGC0B:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.221</cell>
 <cell>7.908</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIGC0B/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIGC0B/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.366</cell>
 <cell>8.274</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIGC0B/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>8.470</cell>
 <cell>18</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr_enable_rcosc:ALn</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CORERESETP_0/sdif0_areset_n_rcosc_RNIGC0B/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.360</cell>
 <cell>8.830</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>8.830</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:A</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.866</cell>
 <cell>0.866</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB:CLKOUT</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RCOSC_25_50MHZ_FAB</cell>
 <cell>+</cell>
 <cell>0.095</cell>
 <cell>0.961</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/N_RCOSC_25_50MHZ_CLKINT</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.066</cell>
 <cell>4.027</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.221</cell>
 <cell>4.248</cell>
 <cell>1</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.370</cell>
 <cell>4.618</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>4.814</cell>
 <cell>20</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr_enable_rcosc:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ_FAB_CLKINT/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.398</cell>
 <cell>5.212</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORERESETP_0/count_ddr_enable_rcosc:ALn</cell>
 <cell>Library removal time</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>5.212</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.212</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to MDDR_TA_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Clock Domain FIC2_APB_CLK</name>
<text></text>
<section>
<name>SET Register to Register</name>
<table>
<header>
 <cell/>
 <cell>From</cell>
 <cell>To</cell>
 <cell>Delay (ns)</cell>
 <cell>Slack (ns)</cell>
 <cell>Arrival (ns)</cell>
 <cell>Required (ns)</cell>
 <cell>Hold (ns)</cell>
</header>
<row>
 <cell>Path 1</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/MDDR_PENABLE:CLK</cell>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PENABLE</cell>
 <cell>0.787</cell>
 <cell>12.578</cell>
 <cell>5.092</cell>
 <cell>-7.486</cell>
 <cell>0.297</cell>
</row>
<row>
 <cell>Path 2</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[14]:D</cell>
 <cell>0.541</cell>
 <cell>12.657</cell>
 <cell>4.846</cell>
 <cell>-7.811</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 3</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PSEL</cell>
 <cell>1.159</cell>
 <cell>12.660</cell>
 <cell>5.464</cell>
 <cell>-7.196</cell>
 <cell>0.587</cell>
</row>
<row>
 <cell>Path 4</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[8]:D</cell>
 <cell>0.542</cell>
 <cell>12.667</cell>
 <cell>4.847</cell>
 <cell>-7.820</cell>
 <cell>0.000</cell>
</row>
<row>
 <cell>Path 5</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/psel:CLK</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[9]:D</cell>
 <cell>0.678</cell>
 <cell>12.802</cell>
 <cell>4.983</cell>
 <cell>-7.819</cell>
 <cell>0.000</cell>
</row>
</table>
<text></text>
<section><name>Expanded Path 1</name></section>
<table>
<header>
 <cell>Pin Name</cell>
 <cell>Type</cell>
 <cell>Net Name</cell>
 <cell>Cell Name</cell>
 <cell>Op</cell>
 <cell>Delay (ns)</cell>
 <cell>Total (ns)</cell>
 <cell>Fanout</cell>
 <cell>Edge</cell>
</header>
<row>
 <cell>From: MDDR_TA_0/CORECONFIGP_0/MDDR_PENABLE:CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>To: MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PENABLE</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.092</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-</cell>
 <cell></cell>
 <cell>-7.486</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>slack</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>12.578</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data arrival time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_APB_CLK</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>0.000</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>3.210</cell>
 <cell>3.210</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.228</cell>
 <cell>3.438</cell>
 <cell>3</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5/U0_RGB1_RGB0:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.355</cell>
 <cell>3.793</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5/U0_RGB1_RGB0:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.153</cell>
 <cell>3.946</cell>
 <cell>58</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORECONFIGP_0/MDDR_PENABLE:CLK</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5/U0_RGB1_RGB0_rgbr_net_1</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.359</cell>
 <cell>4.305</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/CORECONFIGP_0/MDDR_PENABLE:Q</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:SLE</cell>
 <cell>+</cell>
 <cell>0.054</cell>
 <cell>4.359</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_365:A</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/CORECONFIGP_0_MDDR_APBmslave_PENABLE</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.591</cell>
 <cell>4.950</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_365:IPA</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.121</cell>
 <cell>5.071</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PENABLE</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/MDDR_FABRIC_PENABLE_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.021</cell>
 <cell>5.092</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>data arrival time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>5.092</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
<row>
 <cell>Data required time calculation</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>FIC2_APB_CLK</cell>
 <cell>Clock Constraint</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-12.000</cell>
 <cell>-12.000</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB</cell>
 <cell>Clock source</cell>
 <cell></cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.000</cell>
 <cell>-12.000</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>2.999</cell>
 <cell>-9.001</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5:YEn</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:GBM</cell>
 <cell>+</cell>
 <cell>0.221</cell>
 <cell>-8.780</cell>
 <cell>3</cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5/U0_RGB1:An</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5/U0_YWn_GEast</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.373</cell>
 <cell>-8.407</cell>
 <cell></cell>
 <cell>f</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5/U0_RGB1:YR</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:RGB</cell>
 <cell>+</cell>
 <cell>0.196</cell>
 <cell>-8.211</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_361:B</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/FIC_2_APB_M_PCLK_keep_RNIG3N5/U0_RGB1_YR</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.275</cell>
 <cell>-7.936</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/IP_INTERFACE_361:IPB</cell>
 <cell>cell</cell>
 <cell></cell>
 <cell>ADLIB:IP_INTERFACE</cell>
 <cell>+</cell>
 <cell>0.130</cell>
 <cell>-7.806</cell>
 <cell>1</cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_MDDR_APB</cell>
 <cell>net</cell>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/CLK_MDDR_APB_net</cell>
 <cell></cell>
 <cell>+</cell>
 <cell>0.023</cell>
 <cell>-7.783</cell>
 <cell></cell>
 <cell>r</cell>
</row>
<row>
 <cell>MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:MDDR_FABRIC_PENABLE</cell>
 <cell>Library hold time</cell>
 <cell></cell>
 <cell>ADLIB:MSS_120_IP</cell>
 <cell>+</cell>
 <cell>0.297</cell>
 <cell>-7.486</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
 <cell>data required time</cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell></cell>
 <cell>-7.486</cell>
 <cell></cell>
 <cell></cell>
</row>
<row>
</row>
</table>
</section>
<section>
<name>SET External Hold</name>
<text>No Path</text>
</section>
<section>
<name>SET Clock to Output</name>
<text>No Path</text>
</section>
<section>
<name>SET Register to Asynchronous</name>
<text>No Path</text>
</section>
<section>
<name>SET External Removal</name>
<text>No Path</text>
</section>
<section>
<name>SET Asynchronous to Register</name>
<text>No Path</text>
</section>
<section>
<name>SET MDDR_TA_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 to FIC2_APB_CLK</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set Pin to Pin</name>
<section>
<name>SET Input to Output</name>
<text>No Path</text>
</section>
</section>
<section>
<name>Path Set User Sets</name>
</section>
</doc>
