Timing Violation Report Min Delay Analysis

SmartTime Version 
Microsemi Corporation - Microsemi Libero Software Release  (Version 11.6.0.34)
Date: Thu Sep 10 18:58:35 2015


Design: MDDR_TA_top
Family: SmartFusion2
Die: M2S150T
Package: 1152 FC
Temperature Range: 0 - 85 C
Voltage Range: 1.14 - 1.26 V
Speed Grade: -1
Design State: Post-Layout
Data source: Production
Min Operating Conditions: BEST - 1.26 V - 0 C
Max Operating Conditions: WORST - 1.14 V - 85 C
Scenario for Timing Analysis: Primary


Path 1
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/soft_reset_reg[3]:D
  Delay (ns):                  4.267                                                                           
  Slack (ns):                  0.004                                                                           
  Arrival (ns):                4.267                                                                           
  Required (ns):               4.263                                                                           

Path 2
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/pwdata[3]:D
  Delay (ns):                  4.267                                                                           
  Slack (ns):                  0.004                                                                           
  Arrival (ns):                4.267                                                                           
  Required (ns):               4.263                                                                           

Path 3
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/soft_reset_reg[16]:D
  Delay (ns):                  4.279                                                                           
  Slack (ns):                  0.015                                                                           
  Arrival (ns):                4.279                                                                           
  Required (ns):               4.264                                                                           

Path 4
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/paddr[8]:D
  Delay (ns):                  4.262                                                                           
  Slack (ns):                  0.021                                                                           
  Arrival (ns):                4.262                                                                           
  Required (ns):               4.241                                                                           

Path 5
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/paddr[12]:D
  Delay (ns):                  4.268                                                                           
  Slack (ns):                  0.021                                                                           
  Arrival (ns):                4.268                                                                           
  Required (ns):               4.247                                                                           

Path 6
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/paddr[9]:D
  Delay (ns):                  4.283                                                                           
  Slack (ns):                  0.021                                                                           
  Arrival (ns):                4.283                                                                           
  Required (ns):               4.262                                                                           

Path 7
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/paddr[6]:D
  Delay (ns):                  4.317                                                                           
  Slack (ns):                  0.076                                                                           
  Arrival (ns):                4.317                                                                           
  Required (ns):               4.241                                                                           

Path 8
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/state[0]:D
  Delay (ns):                  4.325                                                                           
  Slack (ns):                  0.078                                                                           
  Arrival (ns):                4.325                                                                           
  Required (ns):               4.247                                                                           

Path 9
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/paddr[7]:D
  Delay (ns):                  4.329                                                                           
  Slack (ns):                  0.088                                                                           
  Arrival (ns):                4.329                                                                           
  Required (ns):               4.241                                                                           

Path 10
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/paddr[4]:D
  Delay (ns):                  4.324                                                                           
  Slack (ns):                  0.090                                                                           
  Arrival (ns):                4.324                                                                           
  Required (ns):               4.234                                                                           

Path 11
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/pwdata[7]:D
  Delay (ns):                  4.345                                                                           
  Slack (ns):                  0.091                                                                           
  Arrival (ns):                4.345                                                                           
  Required (ns):               4.254                                                                           

Path 12
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/soft_reset_reg[7]:D
  Delay (ns):                  4.345                                                                           
  Slack (ns):                  0.091                                                                           
  Arrival (ns):                4.345                                                                           
  Required (ns):               4.254                                                                           

Path 13
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/soft_reset_reg[15]:D
  Delay (ns):                  4.357                                                                           
  Slack (ns):                  0.103                                                                           
  Arrival (ns):                4.357                                                                           
  Required (ns):               4.254                                                                           

Path 14
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/pwdata[15]:D
  Delay (ns):                  4.357                                                                           
  Slack (ns):                  0.103                                                                           
  Arrival (ns):                4.357                                                                           
  Required (ns):               4.254                                                                           

Path 15
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/paddr[13]:D
  Delay (ns):                  4.352                                                                           
  Slack (ns):                  0.105                                                                           
  Arrival (ns):                4.352                                                                           
  Required (ns):               4.247                                                                           

Path 16
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/pwdata[14]:D
  Delay (ns):                  4.370                                                                           
  Slack (ns):                  0.107                                                                           
  Arrival (ns):                4.370                                                                           
  Required (ns):               4.263                                                                           

Path 17
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/soft_reset_reg[14]:D
  Delay (ns):                  4.370                                                                           
  Slack (ns):                  0.116                                                                           
  Arrival (ns):                4.370                                                                           
  Required (ns):               4.254                                                                           

Path 18
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/pwdata[8]:D
  Delay (ns):                  4.382                                                                           
  Slack (ns):                  0.120                                                                           
  Arrival (ns):                4.382                                                                           
  Required (ns):               4.262                                                                           

Path 19
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/soft_reset_reg[6]:D
  Delay (ns):                  4.391                                                                           
  Slack (ns):                  0.128                                                                           
  Arrival (ns):                4.391                                                                           
  Required (ns):               4.263                                                                           

Path 20
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/pwdata[6]:D
  Delay (ns):                  4.391                                                                           
  Slack (ns):                  0.137                                                                           
  Arrival (ns):                4.391                                                                           
  Required (ns):               4.254                                                                           

Path 21
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/soft_reset_reg[11]:D
  Delay (ns):                  4.402                                                                           
  Slack (ns):                  0.148                                                                           
  Arrival (ns):                4.402                                                                           
  Required (ns):               4.254                                                                           

Path 22
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/paddr[15]:D
  Delay (ns):                  4.407                                                                           
  Slack (ns):                  0.160                                                                           
  Arrival (ns):                4.407                                                                           
  Required (ns):               4.247                                                                           

Path 23
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/paddr[3]:D
  Delay (ns):                  4.416                                                                           
  Slack (ns):                  0.163                                                                           
  Arrival (ns):                4.416                                                                           
  Required (ns):               4.253                                                                           

Path 24
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/paddr[5]:D
  Delay (ns):                  4.415                                                                           
  Slack (ns):                  0.166                                                                           
  Arrival (ns):                4.415                                                                           
  Required (ns):               4.249                                                                           

Path 25
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/pwdata[12]:D
  Delay (ns):                  4.451                                                                           
  Slack (ns):                  0.189                                                                           
  Arrival (ns):                4.451                                                                           
  Required (ns):               4.262                                                                           

Path 26
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/soft_reset_reg[10]:D
  Delay (ns):                  4.454                                                                           
  Slack (ns):                  0.191                                                                           
  Arrival (ns):                4.454                                                                           
  Required (ns):               4.263                                                                           

Path 27
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/pwdata[10]:D
  Delay (ns):                  4.454                                                                           
  Slack (ns):                  0.191                                                                           
  Arrival (ns):                4.454                                                                           
  Required (ns):               4.263                                                                           

Path 28
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/soft_reset_reg[9]:D
  Delay (ns):                  4.455                                                                           
  Slack (ns):                  0.192                                                                           
  Arrival (ns):                4.455                                                                           
  Required (ns):               4.263                                                                           

Path 29
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/pwdata[9]:D
  Delay (ns):                  4.455                                                                           
  Slack (ns):                  0.193                                                                           
  Arrival (ns):                4.455                                                                           
  Required (ns):               4.262                                                                           

Path 30
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/control_reg_1[0]:EN
  Delay (ns):                  4.459                                                                           
  Slack (ns):                  0.195                                                                           
  Arrival (ns):                4.459                                                                           
  Required (ns):               4.264                                                                           

Path 31
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/soft_reset_reg[8]:D
  Delay (ns):                  4.454                                                                           
  Slack (ns):                  0.200                                                                           
  Arrival (ns):                4.454                                                                           
  Required (ns):               4.254                                                                           

Path 32
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/control_reg_1[1]:EN
  Delay (ns):                  4.459                                                                           
  Slack (ns):                  0.204                                                                           
  Arrival (ns):                4.459                                                                           
  Required (ns):               4.255                                                                           

Path 33
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_ret_54:D
  Delay (ns):                  4.471                                                                           
  Slack (ns):                  0.212                                                                           
  Arrival (ns):                4.471                                                                           
  Required (ns):               4.259                                                                           

Path 34
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/pwdata[13]:D
  Delay (ns):                  4.471                                                                           
  Slack (ns):                  0.217                                                                           
  Arrival (ns):                4.471                                                                           
  Required (ns):               4.254                                                                           

Path 35
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/soft_reset_reg[13]:D
  Delay (ns):                  4.471                                                                           
  Slack (ns):                  0.217                                                                           
  Arrival (ns):                4.471                                                                           
  Required (ns):               4.254                                                                           

Path 36
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/soft_reset_reg[5]:D
  Delay (ns):                  4.486                                                                           
  Slack (ns):                  0.223                                                                           
  Arrival (ns):                4.486                                                                           
  Required (ns):               4.263                                                                           

Path 37
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA[17]:D
  Delay (ns):                  4.496                                                                           
  Slack (ns):                  0.237                                                                           
  Arrival (ns):                4.496                                                                           
  Required (ns):               4.259                                                                           

Path 38
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/paddr[16]:D
  Delay (ns):                  4.493                                                                           
  Slack (ns):                  0.240                                                                           
  Arrival (ns):                4.493                                                                           
  Required (ns):               4.253                                                                           

Path 39
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_ret_0:D
  Delay (ns):                  4.497                                                                           
  Slack (ns):                  0.246                                                                           
  Arrival (ns):                4.497                                                                           
  Required (ns):               4.251                                                                           

Path 40
  From:                        AHB_IF_0/HADDR_int[9]:CLK
  To:                          AHB_IF_0/HADDR_ret_95:D
  Delay (ns):                  0.293                                                                           
  Slack (ns):                  0.247                                                                           
  Arrival (ns):                3.590                                                                           
  Required (ns):               3.343                                                                           

Path 41
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_ret_55:D
  Delay (ns):                  4.498                                                                           
  Slack (ns):                  0.247                                                                           
  Arrival (ns):                4.498                                                                           
  Required (ns):               4.251                                                                           

Path 42
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/pwdata[2]:D
  Delay (ns):                  4.512                                                                           
  Slack (ns):                  0.249                                                                           
  Arrival (ns):                4.512                                                                           
  Required (ns):               4.263                                                                           

Path 43
  From:                        AHB_IF_0/HADDR_int[7]:CLK
  To:                          AHB_IF_0/HADDR_ret_35:D
  Delay (ns):                  0.297                                                                           
  Slack (ns):                  0.249                                                                           
  Arrival (ns):                3.613                                                                           
  Required (ns):               3.364                                                                           

Path 44
  From:                        AHB_IF_0/HADDR_int[5]:CLK
  To:                          AHB_IF_0/HADDR_ret_51:D
  Delay (ns):                  0.298                                                                           
  Slack (ns):                  0.250                                                                           
  Arrival (ns):                3.614                                                                           
  Required (ns):               3.364                                                                           

Path 45
  From:                        AHB_IF_0/HADDR_int[6]:CLK
  To:                          AHB_IF_0/HADDR_ret_39:D
  Delay (ns):                  0.290                                                                           
  Slack (ns):                  0.250                                                                           
  Arrival (ns):                3.614                                                                           
  Required (ns):               3.364                                                                           

Path 46
  From:                        AHB_IF_0/HADDR_int[8]:CLK
  To:                          AHB_IF_0/HADDR_ret_63:D
  Delay (ns):                  0.293                                                                           
  Slack (ns):                  0.251                                                                           
  Arrival (ns):                3.592                                                                           
  Required (ns):               3.341                                                                           

Path 47
  From:                        AHB_IF_0/HADDR_int[27]:CLK
  To:                          AHB_IF_0/HADDR_ret_23:D
  Delay (ns):                  0.300                                                                           
  Slack (ns):                  0.252                                                                           
  Arrival (ns):                3.618                                                                           
  Required (ns):               3.366                                                                           

Path 48
  From:                        AHB_IF_0/HADDR_int[30]:CLK
  To:                          AHB_IF_0/HADDR_ret_103:D
  Delay (ns):                  0.300                                                                           
  Slack (ns):                  0.253                                                                           
  Arrival (ns):                3.615                                                                           
  Required (ns):               3.362                                                                           

Path 49
  From:                        AHB_IF_0/HADDR_int[20]:CLK
  To:                          AHB_IF_0/HADDR_ret_7:D
  Delay (ns):                  0.301                                                                           
  Slack (ns):                  0.254                                                                           
  Arrival (ns):                3.619                                                                           
  Required (ns):               3.365                                                                           

Path 50
  From:                        AHB_IF_0/HWDATA_int[8]:CLK
  To:                          AHB_IF_0/HWDATA[8]:D
  Delay (ns):                  0.300                                                                           
  Slack (ns):                  0.254                                                                           
  Arrival (ns):                3.616                                                                           
  Required (ns):               3.362                                                                           

Path 51
  From:                        AHB_IF_0/HADDR_int[18]:CLK
  To:                          AHB_IF_0/HADDR_ret_43:D
  Delay (ns):                  0.300                                                                           
  Slack (ns):                  0.254                                                                           
  Arrival (ns):                3.608                                                                           
  Required (ns):               3.354                                                                           

Path 52
  From:                        AHB_IF_0/HADDR_int[15]:CLK
  To:                          AHB_IF_0/HADDR_ret_83:D
  Delay (ns):                  0.295                                                                           
  Slack (ns):                  0.255                                                                           
  Arrival (ns):                3.619                                                                           
  Required (ns):               3.364                                                                           

Path 53
  From:                        MDDR_TA_0/CORERESETP_0/release_sdif0_core_q1:CLK
  To:                          MDDR_TA_0/CORERESETP_0/release_sdif0_core_clk_base:D
  Delay (ns):                  0.295                                                                           
  Slack (ns):                  0.255                                                                           
  Arrival (ns):                3.627                                                                           
  Required (ns):               3.372                                                                           

Path 54
  From:                        MDDR_TA_0/CORERESETP_0/POWER_ON_RESET_N_q1:CLK
  To:                          MDDR_TA_0/CORERESETP_0/POWER_ON_RESET_N_clk_base:D
  Delay (ns):                  0.297                                                                           
  Slack (ns):                  0.255                                                                           
  Arrival (ns):                3.573                                                                           
  Required (ns):               3.318                                                                           

Path 55
  From:                        MDDR_TA_0/CORERESETP_0/sm0_areset_n_q1:CLK
  To:                          MDDR_TA_0/CORERESETP_0/sm0_areset_n_clk_base:D
  Delay (ns):                  0.297                                                                           
  Slack (ns):                  0.256                                                                           
  Arrival (ns):                3.596                                                                           
  Required (ns):               3.340                                                                           

Path 56
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/soft_reset_reg[12]:D
  Delay (ns):                  4.511                                                                           
  Slack (ns):                  0.257                                                                           
  Arrival (ns):                4.511                                                                           
  Required (ns):               4.254                                                                           

Path 57
  From:                        MDDR_TA_0/CORERESETP_0/count_ddr_enable_q1:CLK
  To:                          MDDR_TA_0/CORERESETP_0/count_ddr_enable_rcosc:D
  Delay (ns):                  0.297                                                                           
  Slack (ns):                  0.258                                                                           
  Arrival (ns):                5.504                                                                           
  Required (ns):               5.246                                                                           

Path 58
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/soft_reset_reg[2]:D
  Delay (ns):                  4.512                                                                           
  Slack (ns):                  0.258                                                                           
  Arrival (ns):                4.512                                                                           
  Required (ns):               4.254                                                                           

Path 59
  From:                        AXI_IF_0/AHB_DATA_1[3]:CLK
  To:                          AHB_IF_0/HWDATA_int[3]:D
  Delay (ns):                  0.290                                                                           
  Slack (ns):                  0.258                                                                           
  Arrival (ns):                3.613                                                                           
  Required (ns):               3.355                                                                           

Path 60
  From:                        AXI_IF_0/AHB_DATA_1[1]:CLK
  To:                          AHB_IF_0/HWDATA_int[1]:D
  Delay (ns):                  0.297                                                                           
  Slack (ns):                  0.258                                                                           
  Arrival (ns):                3.613                                                                           
  Required (ns):               3.355                                                                           

Path 61
  From:                        AHB_IF_0/HADDR_int[13]:CLK
  To:                          AHB_IF_0/HADDR_ret_31:D
  Delay (ns):                  0.298                                                                           
  Slack (ns):                  0.259                                                                           
  Arrival (ns):                3.616                                                                           
  Required (ns):               3.357                                                                           

Path 62
  From:                        AHB_IF_0/HADDR_int[25]:CLK
  To:                          AHB_IF_0/HADDR_ret_0:D
  Delay (ns):                  0.298                                                                           
  Slack (ns):                  0.259                                                                           
  Arrival (ns):                3.616                                                                           
  Required (ns):               3.357                                                                           

Path 63
  From:                        MDDR_TA_0/CORECONFIGP_0/soft_reset_reg[10]:CLK
  To:                          MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_ret_31:D
  Delay (ns):                  0.299                                                                           
  Slack (ns):                  0.259                                                                           
  Arrival (ns):                4.521                                                                           
  Required (ns):               4.262                                                                           

Path 64
  From:                        MDDR_TA_0/CORERESETP_0/ddr_settled_q1:CLK
  To:                          MDDR_TA_0/CORERESETP_0/ddr_settled_clk_base:D
  Delay (ns):                  0.298                                                                           
  Slack (ns):                  0.259                                                                           
  Arrival (ns):                3.622                                                                           
  Required (ns):               3.363                                                                           

Path 65
  From:                        AHB_IF_0/HADDR_int[24]:CLK
  To:                          AHB_IF_0/HADDR_ret_11:D
  Delay (ns):                  0.301                                                                           
  Slack (ns):                  0.260                                                                           
  Arrival (ns):                3.626                                                                           
  Required (ns):               3.366                                                                           

Path 66
  From:                        AHB_IF_0/HADDR_int[14]:CLK
  To:                          AHB_IF_0/HADDR_ret_79:D
  Delay (ns):                  0.300                                                                           
  Slack (ns):                  0.260                                                                           
  Arrival (ns):                3.616                                                                           
  Required (ns):               3.356                                                                           

Path 67
  From:                        MDDR_TA_0/CORERESETP_0/CONFIG1_DONE_q1:CLK
  To:                          MDDR_TA_0/CORERESETP_0/CONFIG1_DONE_clk_base:D
  Delay (ns):                  0.298                                                                           
  Slack (ns):                  0.260                                                                           
  Arrival (ns):                3.614                                                                           
  Required (ns):               3.354                                                                           

Path 68
  From:                        MDDR_TA_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[1]:CLK
  To:                          MDDR_TA_0/CoreAHBLite_0/matrix4x16/slavestage_16/slave_arbiter/arbRegSMCurrentState[1]:D
  Delay (ns):                  0.299                                                                           
  Slack (ns):                  0.260                                                                           
  Arrival (ns):                3.608                                                                           
  Required (ns):               3.348                                                                           

Path 69
  From:                        AHB_IF_0/HADDR_int[21]:CLK
  To:                          AHB_IF_0/HADDR_ret_27:D
  Delay (ns):                  0.301                                                                           
  Slack (ns):                  0.261                                                                           
  Arrival (ns):                3.626                                                                           
  Required (ns):               3.365                                                                           

Path 70
  From:                        AHB_IF_0/HADDR_int[12]:CLK
  To:                          AHB_IF_0/HADDR_ret_75:D
  Delay (ns):                  0.301                                                                           
  Slack (ns):                  0.262                                                                           
  Arrival (ns):                3.626                                                                           
  Required (ns):               3.364                                                                           

Path 71
  From:                        MDDR_TA_0/CORERESETP_0/RESET_N_M2F_q1:CLK
  To:                          MDDR_TA_0/CORERESETP_0/RESET_N_M2F_clk_base:D
  Delay (ns):                  0.301                                                                           
  Slack (ns):                  0.262                                                                           
  Arrival (ns):                3.623                                                                           
  Required (ns):               3.361                                                                           

Path 72
  From:                        AHB_IF_0/HADDR_int[2]:CLK
  To:                          AHB_IF_0/HADDR_ret:D
  Delay (ns):                  0.295                                                                           
  Slack (ns):                  0.263                                                                           
  Arrival (ns):                3.620                                                                           
  Required (ns):               3.357                                                                           

Path 73
  From:                        AHB_IF_0/HADDR_int[19]:CLK
  To:                          AHB_IF_0/HADDR_ret_15:D
  Delay (ns):                  0.295                                                                           
  Slack (ns):                  0.263                                                                           
  Arrival (ns):                3.620                                                                           
  Required (ns):               3.357                                                                           

Path 74
  From:                        AHB_IF_0/HWDATA_int[0]:CLK
  To:                          AHB_IF_0/HWDATA[0]:D
  Delay (ns):                  0.297                                                                           
  Slack (ns):                  0.265                                                                           
  Arrival (ns):                3.624                                                                           
  Required (ns):               3.359                                                                           

Path 75
  From:                        MDDR_TA_0/CORECONFIGP_0/INIT_DONE_q1:CLK
  To:                          MDDR_TA_0/CORECONFIGP_0/INIT_DONE_q2:D
  Delay (ns):                  0.297                                                                           
  Slack (ns):                  0.265                                                                           
  Arrival (ns):                4.520                                                                           
  Required (ns):               4.255                                                                           

Path 76
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/control_reg_1[0]:D
  Delay (ns):                  4.530                                                                           
  Slack (ns):                  0.266                                                                           
  Arrival (ns):                4.530                                                                           
  Required (ns):               4.264                                                                           

Path 77
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/pwdata[0]:D
  Delay (ns):                  4.530                                                                           
  Slack (ns):                  0.266                                                                           
  Arrival (ns):                4.530                                                                           
  Required (ns):               4.264                                                                           

Path 78
  From:                        AHB_IF_0/HADDR_int[3]:CLK
  To:                          AHB_IF_0/HADDR_ret_87:D
  Delay (ns):                  0.299                                                                           
  Slack (ns):                  0.267                                                                           
  Arrival (ns):                3.621                                                                           
  Required (ns):               3.354                                                                           

Path 79
  From:                        MDDR_TA_0/CORECONFIGP_0/soft_reset_reg[1]:CLK
  To:                          MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_ret_53:D
  Delay (ns):                  0.308                                                                           
  Slack (ns):                  0.267                                                                           
  Arrival (ns):                4.531                                                                           
  Required (ns):               4.264                                                                           

Path 80
  From:                        MDDR_TA_0/CORECONFIGP_0/control_reg_1[1]:CLK
  To:                          MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_ret_5:D
  Delay (ns):                  0.308                                                                           
  Slack (ns):                  0.269                                                                           
  Arrival (ns):                4.524                                                                           
  Required (ns):               4.255                                                                           

Path 81
  From:                        AHB_IF_0/HADDR_int[11]:CLK
  To:                          AHB_IF_0/HADDR_ret_99:D
  Delay (ns):                  0.301                                                                           
  Slack (ns):                  0.269                                                                           
  Arrival (ns):                3.623                                                                           
  Required (ns):               3.354                                                                           

Path 82
  From:                        AHB_IF_0/HADDR_int[16]:CLK
  To:                          AHB_IF_0/HADDR_ret_59:D
  Delay (ns):                  0.301                                                                           
  Slack (ns):                  0.269                                                                           
  Arrival (ns):                3.616                                                                           
  Required (ns):               3.347                                                                           

Path 83
  From:                        AXI_IF_0/rt_state[0]:CLK
  To:                          AXI_IF_0/rt_state[0]:D
  Delay (ns):                  0.309                                                                           
  Slack (ns):                  0.270                                                                           
  Arrival (ns):                3.625                                                                           
  Required (ns):               3.355                                                                           

Path 84
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/paddr[2]:D
  Delay (ns):                  4.527                                                                           
  Slack (ns):                  0.272                                                                           
  Arrival (ns):                4.527                                                                           
  Required (ns):               4.255                                                                           

Path 85
  From:                        AXI_IF_0/wt_state[1]:CLK
  To:                          AXI_IF_0/wt_state[1]:D
  Delay (ns):                  0.311                                                                           
  Slack (ns):                  0.273                                                                           
  Arrival (ns):                3.623                                                                           
  Required (ns):               3.350                                                                           

Path 86
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/soft_reset_reg[0]:D
  Delay (ns):                  4.530                                                                           
  Slack (ns):                  0.275                                                                           
  Arrival (ns):                4.530                                                                           
  Required (ns):               4.255                                                                           

Path 87
  From:                        AXI_IF_0/rt_state[1]:CLK
  To:                          AXI_IF_0/rt_state[1]:D
  Delay (ns):                  0.317                                                                           
  Slack (ns):                  0.277                                                                           
  Arrival (ns):                3.642                                                                           
  Required (ns):               3.365                                                                           

Path 88
  From:                        AXI_IF_0/burst_cnt[1]:CLK
  To:                          AXI_IF_0/burst_cnt[1]:D
  Delay (ns):                  0.315                                                                           
  Slack (ns):                  0.278                                                                           
  Arrival (ns):                3.622                                                                           
  Required (ns):               3.344                                                                           

Path 89
  From:                        AXI_IF_0/burst_cnt[3]:CLK
  To:                          AXI_IF_0/burst_cnt[3]:D
  Delay (ns):                  0.316                                                                           
  Slack (ns):                  0.279                                                                           
  Arrival (ns):                3.623                                                                           
  Required (ns):               3.344                                                                           

Path 90
  From:                        MDDR_TA_0/CORERESETP_0/sm0_state[5]:CLK
  To:                          MDDR_TA_0/CORERESETP_0/sm0_state[5]:D
  Delay (ns):                  0.318                                                                           
  Slack (ns):                  0.279                                                                           
  Arrival (ns):                3.642                                                                           
  Required (ns):               3.363                                                                           

Path 91
  From:                        AXI_IF_0/w_loop[3]:CLK
  To:                          AXI_IF_0/w_loop[3]:D
  Delay (ns):                  0.318                                                                           
  Slack (ns):                  0.280                                                                           
  Arrival (ns):                3.622                                                                           
  Required (ns):               3.342                                                                           

Path 92
  From:                        AXI_IF_0/w_loop[0]:CLK
  To:                          AXI_IF_0/w_loop[0]:D
  Delay (ns):                  0.320                                                                           
  Slack (ns):                  0.282                                                                           
  Arrival (ns):                3.624                                                                           
  Required (ns):               3.342                                                                           

Path 93
  From:                        MDDR_TA_0/CORECONFIGP_0/soft_reset_reg[2]:CLK
  To:                          MDDR_TA_0/CORECONFIGP_0/FIC_2_APB_M_PRDATA_ret_8:D
  Delay (ns):                  0.321                                                                           
  Slack (ns):                  0.282                                                                           
  Arrival (ns):                4.536                                                                           
  Required (ns):               4.254                                                                           

Path 94
  From:                        AXI_IF_0/axi_fsm_read1_state[0]:CLK
  To:                          AXI_IF_0/axi_fsm_read1_state[0]:D
  Delay (ns):                  0.319                                                                           
  Slack (ns):                  0.282                                                                           
  Arrival (ns):                3.620                                                                           
  Required (ns):               3.338                                                                           

Path 95
  From:                        AXI_IF_0/w_loop_state[0]:CLK
  To:                          AXI_IF_0/w_loop_state[0]:D
  Delay (ns):                  0.323                                                                           
  Slack (ns):                  0.285                                                                           
  Arrival (ns):                3.633                                                                           
  Required (ns):               3.348                                                                           

Path 96
  From:                        AXI_IF_0/r_loop[3]:CLK
  To:                          AXI_IF_0/r_loop[3]:D
  Delay (ns):                  0.324                                                                           
  Slack (ns):                  0.286                                                                           
  Arrival (ns):                3.636                                                                           
  Required (ns):               3.350                                                                           

Path 97
  From:                        AXI_IF_0/r_loop[0]:CLK
  To:                          AXI_IF_0/r_loop[0]:D
  Delay (ns):                  0.324                                                                           
  Slack (ns):                  0.286                                                                           
  Arrival (ns):                3.636                                                                           
  Required (ns):               3.350                                                                           

Path 98
  From:                        AXI_IF_0/axi_fsm_read_state[0]:CLK
  To:                          AXI_IF_0/axi_fsm_read_state[0]:D
  Delay (ns):                  0.326                                                                           
  Slack (ns):                  0.288                                                                           
  Arrival (ns):                3.630                                                                           
  Required (ns):               3.342                                                                           

Path 99
  From:                        AXI_IF_0/AWADDR_int[31]:CLK
  To:                          AXI_IF_0/AWADDR_1[31]:D
  Delay (ns):                  0.323                                                                           
  Slack (ns):                  0.291                                                                           
  Arrival (ns):                3.637                                                                           
  Required (ns):               3.346                                                                           

Path 100
  From:                        MDDR_TA_0/MDDR_TA_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB
  To:                          MDDR_TA_0/CORECONFIGP_0/soft_reset_reg[1]:D
  Delay (ns):                  4.558                                                                           
  Slack (ns):                  0.294                                                                           
  Arrival (ns):                4.558                                                                           
  Required (ns):               4.264                                                                           

