//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Thu Jul 30 16:30:56 2015
// Version: v11.6 11.6.0.28
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

// MDDR_TA
module MDDR_TA(
    // Inputs
    AMBA_MASTER_0_ARADDR_M0,
    AMBA_MASTER_0_ARBURST_M0,
    AMBA_MASTER_0_ARCACHE_M0,
    AMBA_MASTER_0_ARID_M0,
    AMBA_MASTER_0_ARLEN_M0,
    AMBA_MASTER_0_ARLOCK_M0,
    AMBA_MASTER_0_ARPROT_M0,
    AMBA_MASTER_0_ARSIZE_M0,
    AMBA_MASTER_0_ARVALID_M0,
    AMBA_MASTER_0_AWADDR_M0,
    AMBA_MASTER_0_AWBURST_M0,
    AMBA_MASTER_0_AWCACHE_M0,
    AMBA_MASTER_0_AWID_M0,
    AMBA_MASTER_0_AWLEN_M0,
    AMBA_MASTER_0_AWLOCK_M0,
    AMBA_MASTER_0_AWPROT_M0,
    AMBA_MASTER_0_AWSIZE_M0,
    AMBA_MASTER_0_AWVALID_M0,
    AMBA_MASTER_0_BREADY_M0,
    AMBA_MASTER_0_RREADY_M0,
    AMBA_MASTER_0_WDATA_M0,
    AMBA_MASTER_0_WID_M0,
    AMBA_MASTER_0_WLAST_M0,
    AMBA_MASTER_0_WSTRB_M0,
    AMBA_MASTER_0_WVALID_M0,
    AMBA_MASTER_1_HADDR_M0,
    AMBA_MASTER_1_HBURST_M0,
    AMBA_MASTER_1_HMASTLOCK_M0,
    AMBA_MASTER_1_HPROT_M0,
    AMBA_MASTER_1_HSIZE_M0,
    AMBA_MASTER_1_HTRANS_M0,
    AMBA_MASTER_1_HWDATA_M0,
    AMBA_MASTER_1_HWRITE_M0,
    DEVRST_N,
    FAB_RESET_N,
    MDDR_AXI_S_RMW,
    MDDR_DQS_TMATCH_0_IN,
    MMUART_0_RXD,
    // Outputs
    AMBA_MASTER_0_ARREADY_M0,
    AMBA_MASTER_0_AWREADY_M0,
    AMBA_MASTER_0_BID_M0,
    AMBA_MASTER_0_BRESP_M0,
    AMBA_MASTER_0_BVALID_M0,
    AMBA_MASTER_0_RDATA_M0,
    AMBA_MASTER_0_RID_M0,
    AMBA_MASTER_0_RLAST_M0,
    AMBA_MASTER_0_RRESP_M0,
    AMBA_MASTER_0_RVALID_M0,
    AMBA_MASTER_0_WREADY_M0,
    AMBA_MASTER_1_HRDATA_M0,
    AMBA_MASTER_1_HREADY_M0,
    AMBA_MASTER_1_HRESP_M0,
    DDR_READY,
    FIC_0_CLK,
    FIC_0_LOCK,
    GPIO_0_M2F,
    GPIO_1_M2F,
    GPIO_2_M2F,
    GPIO_3_M2F,
    GPIO_4_M2F,
    GPIO_5_M2F,
    GPIO_6_M2F,
    GPIO_7_M2F,
    INIT_DONE,
    MDDR_ADDR,
    MDDR_BA,
    MDDR_CAS_N,
    MDDR_CKE,
    MDDR_CLK,
    MDDR_CLK_N,
    MDDR_CS_N,
    MDDR_DQS_TMATCH_0_OUT,
    MDDR_ODT,
    MDDR_RAS_N,
    MDDR_RESET_N,
    MDDR_WE_N,
    MMUART_0_TXD,
    MSS_DDR_FIC_SUBSYSTEM_CLK,
    MSS_DDR_FIC_SUBSYSTEM_LOCK,
    MSS_READY,
    POWER_ON_RESET_N,
    // Inouts
    MDDR_DM_RDQS,
    MDDR_DQ,
    MDDR_DQS,
    MDDR_DQS_N
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input  [31:0] AMBA_MASTER_0_ARADDR_M0;
input  [1:0]  AMBA_MASTER_0_ARBURST_M0;
input  [3:0]  AMBA_MASTER_0_ARCACHE_M0;
input  [3:0]  AMBA_MASTER_0_ARID_M0;
input  [3:0]  AMBA_MASTER_0_ARLEN_M0;
input  [1:0]  AMBA_MASTER_0_ARLOCK_M0;
input  [2:0]  AMBA_MASTER_0_ARPROT_M0;
input  [2:0]  AMBA_MASTER_0_ARSIZE_M0;
input         AMBA_MASTER_0_ARVALID_M0;
input  [31:0] AMBA_MASTER_0_AWADDR_M0;
input  [1:0]  AMBA_MASTER_0_AWBURST_M0;
input  [3:0]  AMBA_MASTER_0_AWCACHE_M0;
input  [3:0]  AMBA_MASTER_0_AWID_M0;
input  [3:0]  AMBA_MASTER_0_AWLEN_M0;
input  [1:0]  AMBA_MASTER_0_AWLOCK_M0;
input  [2:0]  AMBA_MASTER_0_AWPROT_M0;
input  [2:0]  AMBA_MASTER_0_AWSIZE_M0;
input         AMBA_MASTER_0_AWVALID_M0;
input         AMBA_MASTER_0_BREADY_M0;
input         AMBA_MASTER_0_RREADY_M0;
input  [63:0] AMBA_MASTER_0_WDATA_M0;
input  [3:0]  AMBA_MASTER_0_WID_M0;
input         AMBA_MASTER_0_WLAST_M0;
input  [7:0]  AMBA_MASTER_0_WSTRB_M0;
input         AMBA_MASTER_0_WVALID_M0;
input  [31:0] AMBA_MASTER_1_HADDR_M0;
input  [2:0]  AMBA_MASTER_1_HBURST_M0;
input         AMBA_MASTER_1_HMASTLOCK_M0;
input  [3:0]  AMBA_MASTER_1_HPROT_M0;
input  [2:0]  AMBA_MASTER_1_HSIZE_M0;
input  [1:0]  AMBA_MASTER_1_HTRANS_M0;
input  [31:0] AMBA_MASTER_1_HWDATA_M0;
input         AMBA_MASTER_1_HWRITE_M0;
input         DEVRST_N;
input         FAB_RESET_N;
input         MDDR_AXI_S_RMW;
input         MDDR_DQS_TMATCH_0_IN;
input         MMUART_0_RXD;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output        AMBA_MASTER_0_ARREADY_M0;
output        AMBA_MASTER_0_AWREADY_M0;
output [3:0]  AMBA_MASTER_0_BID_M0;
output [1:0]  AMBA_MASTER_0_BRESP_M0;
output        AMBA_MASTER_0_BVALID_M0;
output [63:0] AMBA_MASTER_0_RDATA_M0;
output [3:0]  AMBA_MASTER_0_RID_M0;
output        AMBA_MASTER_0_RLAST_M0;
output [1:0]  AMBA_MASTER_0_RRESP_M0;
output        AMBA_MASTER_0_RVALID_M0;
output        AMBA_MASTER_0_WREADY_M0;
output [31:0] AMBA_MASTER_1_HRDATA_M0;
output        AMBA_MASTER_1_HREADY_M0;
output [1:0]  AMBA_MASTER_1_HRESP_M0;
output        DDR_READY;
output        FIC_0_CLK;
output        FIC_0_LOCK;
output        GPIO_0_M2F;
output        GPIO_1_M2F;
output        GPIO_2_M2F;
output        GPIO_3_M2F;
output        GPIO_4_M2F;
output        GPIO_5_M2F;
output        GPIO_6_M2F;
output        GPIO_7_M2F;
output        INIT_DONE;
output [15:0] MDDR_ADDR;
output [2:0]  MDDR_BA;
output        MDDR_CAS_N;
output        MDDR_CKE;
output        MDDR_CLK;
output        MDDR_CLK_N;
output        MDDR_CS_N;
output        MDDR_DQS_TMATCH_0_OUT;
output        MDDR_ODT;
output        MDDR_RAS_N;
output        MDDR_RESET_N;
output        MDDR_WE_N;
output        MMUART_0_TXD;
output        MSS_DDR_FIC_SUBSYSTEM_CLK;
output        MSS_DDR_FIC_SUBSYSTEM_LOCK;
output        MSS_READY;
output        POWER_ON_RESET_N;
//--------------------------------------------------------------------
// Inout
//--------------------------------------------------------------------
inout  [1:0]  MDDR_DM_RDQS;
inout  [15:0] MDDR_DQ;
inout  [1:0]  MDDR_DQS;
inout  [1:0]  MDDR_DQS_N;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire   [31:0] AMBA_MASTER_0_ARADDR_M0;
wire   [1:0]  AMBA_MASTER_0_ARBURST_M0;
wire   [3:0]  AMBA_MASTER_0_ARCACHE_M0;
wire   [3:0]  AMBA_MASTER_0_ARID_M0;
wire   [3:0]  AMBA_MASTER_0_ARLEN_M0;
wire   [1:0]  AMBA_MASTER_0_ARLOCK_M0;
wire   [2:0]  AMBA_MASTER_0_ARPROT_M0;
wire          AMBA_MASTER_0_ARREADY;
wire   [2:0]  AMBA_MASTER_0_ARSIZE_M0;
wire          AMBA_MASTER_0_ARVALID_M0;
wire   [31:0] AMBA_MASTER_0_AWADDR_M0;
wire   [1:0]  AMBA_MASTER_0_AWBURST_M0;
wire   [3:0]  AMBA_MASTER_0_AWCACHE_M0;
wire   [3:0]  AMBA_MASTER_0_AWID_M0;
wire   [3:0]  AMBA_MASTER_0_AWLEN_M0;
wire   [1:0]  AMBA_MASTER_0_AWLOCK_M0;
wire   [2:0]  AMBA_MASTER_0_AWPROT_M0;
wire          AMBA_MASTER_0_AWREADY;
wire   [2:0]  AMBA_MASTER_0_AWSIZE_M0;
wire          AMBA_MASTER_0_AWVALID_M0;
wire   [3:0]  AMBA_MASTER_0_BID;
wire          AMBA_MASTER_0_BREADY_M0;
wire   [1:0]  AMBA_MASTER_0_BRESP;
wire          AMBA_MASTER_0_BVALID;
wire   [63:0] AMBA_MASTER_0_RDATA;
wire   [3:0]  AMBA_MASTER_0_RID;
wire          AMBA_MASTER_0_RLAST;
wire          AMBA_MASTER_0_RREADY_M0;
wire   [1:0]  AMBA_MASTER_0_RRESP;
wire          AMBA_MASTER_0_RVALID;
wire   [63:0] AMBA_MASTER_0_WDATA_M0;
wire   [3:0]  AMBA_MASTER_0_WID_M0;
wire          AMBA_MASTER_0_WLAST_M0;
wire          AMBA_MASTER_0_WREADY;
wire   [7:0]  AMBA_MASTER_0_WSTRB_M0;
wire          AMBA_MASTER_0_WVALID_M0;
wire   [31:0] AMBA_MASTER_1_HADDR_M0;
wire   [2:0]  AMBA_MASTER_1_HBURST_M0;
wire          AMBA_MASTER_1_HMASTLOCK_M0;
wire   [3:0]  AMBA_MASTER_1_HPROT_M0;
wire   [31:0] AMBA_MASTER_1_HRDATA;
wire          AMBA_MASTER_1_HREADY;
wire   [1:0]  AMBA_MASTER_1_HRESP;
wire   [2:0]  AMBA_MASTER_1_HSIZE_M0;
wire   [1:0]  AMBA_MASTER_1_HTRANS_M0;
wire   [31:0] AMBA_MASTER_1_HWDATA_M0;
wire          AMBA_MASTER_1_HWRITE_M0;
wire   [31:0] CoreAHBLite_0_AHBmslave16_HADDR;
wire   [2:0]  CoreAHBLite_0_AHBmslave16_HBURST;
wire          CoreAHBLite_0_AHBmslave16_HMASTLOCK;
wire   [3:0]  CoreAHBLite_0_AHBmslave16_HPROT;
wire   [31:0] CoreAHBLite_0_AHBmslave16_HRDATA;
wire          CoreAHBLite_0_AHBmslave16_HREADY;
wire          CoreAHBLite_0_AHBmslave16_HREADYOUT;
wire          CoreAHBLite_0_AHBmslave16_HSELx;
wire   [1:0]  CoreAHBLite_0_AHBmslave16_HTRANS;
wire   [31:0] CoreAHBLite_0_AHBmslave16_HWDATA;
wire          CoreAHBLite_0_AHBmslave16_HWRITE;
wire   [31:0] COREAXI_0_AXImslave0_ARADDR;
wire   [1:0]  COREAXI_0_AXImslave0_ARBURST;
wire   [3:0]  COREAXI_0_AXImslave0_ARCACHE;
wire   [3:0]  COREAXI_0_AXImslave0_ARLEN;
wire   [1:0]  COREAXI_0_AXImslave0_ARLOCK;
wire   [2:0]  COREAXI_0_AXImslave0_ARPROT;
wire          COREAXI_0_AXImslave0_ARREADY;
wire          COREAXI_0_AXImslave0_ARVALID;
wire   [31:0] COREAXI_0_AXImslave0_AWADDR;
wire   [1:0]  COREAXI_0_AXImslave0_AWBURST;
wire   [3:0]  COREAXI_0_AXImslave0_AWCACHE;
wire   [3:0]  COREAXI_0_AXImslave0_AWLEN;
wire   [1:0]  COREAXI_0_AXImslave0_AWLOCK;
wire   [2:0]  COREAXI_0_AXImslave0_AWPROT;
wire          COREAXI_0_AXImslave0_AWREADY;
wire          COREAXI_0_AXImslave0_AWVALID;
wire          COREAXI_0_AXImslave0_BREADY;
wire   [1:0]  COREAXI_0_AXImslave0_BRESP;
wire          COREAXI_0_AXImslave0_BVALID;
wire   [63:0] COREAXI_0_AXImslave0_RDATA;
wire          COREAXI_0_AXImslave0_RLAST;
wire          COREAXI_0_AXImslave0_RREADY;
wire   [1:0]  COREAXI_0_AXImslave0_RRESP;
wire          COREAXI_0_AXImslave0_RVALID;
wire   [63:0] COREAXI_0_AXImslave0_WDATA;
wire          COREAXI_0_AXImslave0_WLAST;
wire          COREAXI_0_AXImslave0_WREADY;
wire   [7:0]  COREAXI_0_AXImslave0_WSTRB;
wire          COREAXI_0_AXImslave0_WVALID;
wire          CORECONFIGP_0_APB_S_PCLK;
wire          CORECONFIGP_0_APB_S_PRESET_N;
wire          CORECONFIGP_0_CONFIG1_DONE;
wire          CORECONFIGP_0_CONFIG2_DONE;
wire          CORECONFIGP_0_MDDR_APBmslave_PENABLE;
wire          CORECONFIGP_0_MDDR_APBmslave_PREADY;
wire          CORECONFIGP_0_MDDR_APBmslave_PSELx;
wire          CORECONFIGP_0_MDDR_APBmslave_PSLVERR;
wire          CORECONFIGP_0_MDDR_APBmslave_PWRITE;
wire          CORECONFIGP_0_SOFT_EXT_RESET_OUT;
wire          CORECONFIGP_0_SOFT_M3_RESET;
wire          CORECONFIGP_0_SOFT_MDDR_DDR_AXI_S_CORE_RESET;
wire          CORECONFIGP_0_SOFT_RESET_F2M;
wire          CORERESETP_0_M3_RESET_N;
wire          CORERESETP_0_MDDR_DDR_AXI_S_CORE_RESET_N;
wire          CORERESETP_0_RESET_N_F2M;
wire          DDR_READY_net_0;
wire          DEVRST_N;
wire          FAB_RESET_N;
wire          FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC;
wire          FABOSC_0_RCOSC_25_50MHZ_O2F;
wire          FIC_0_CLK_net_0;
wire          GPIO_0_M2F_net_0;
wire          GPIO_1_M2F_net_0;
wire          GPIO_2_M2F_net_0;
wire          GPIO_3_M2F_net_0;
wire          GPIO_4_M2F_net_0;
wire          GPIO_5_M2F_net_0;
wire          GPIO_6_M2F_net_0;
wire          GPIO_7_M2F_net_0;
wire          INIT_DONE_net_0;
wire   [15:0] MDDR_ADDR_net_0;
wire          MDDR_AXI_S_RMW;
wire   [2:0]  MDDR_BA_net_0;
wire          MDDR_CAS_N_net_0;
wire          MDDR_CKE_net_0;
wire          MDDR_CLK_net_0;
wire          MDDR_CLK_N_net_0;
wire          MDDR_CS_N_net_0;
wire   [1:0]  MDDR_DM_RDQS;
wire   [15:0] MDDR_DQ;
wire   [1:0]  MDDR_DQS;
wire   [1:0]  MDDR_DQS_N;
wire          MDDR_DQS_TMATCH_0_IN;
wire          MDDR_DQS_TMATCH_0_OUT_net_0;
wire          MDDR_ODT_net_0;
wire          MDDR_RAS_N_net_0;
wire          MDDR_RESET_N_net_0;
wire          MDDR_TA_MSS_TMP_0_FIC_2_APB_M_PCLK;
wire          MDDR_TA_MSS_TMP_0_FIC_2_APB_M_PRESET_N;
wire   [16:2] MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR;
wire          MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE;
wire   [31:0] MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA;
wire          MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PREADY;
wire          MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSELx;
wire          MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSLVERR;
wire   [31:0] MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA;
wire          MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE;
wire          MDDR_TA_MSS_TMP_0_MSS_RESET_N_M2F;
wire          MDDR_WE_N_net_0;
wire          MMUART_0_RXD;
wire          MMUART_0_TXD_net_0;
wire          MSS_DDR_FIC_SUBSYSTEM_CLK_net_0;
wire          MSS_DDR_FIC_SUBSYSTEM_LOCK_net_0;
wire          MSS_READY_net_0;
wire          POWER_ON_RESET_N_net_0;
wire          MMUART_0_TXD_net_1;
wire          MDDR_DQS_TMATCH_0_OUT_net_1;
wire          MDDR_CAS_N_net_1;
wire          MDDR_CLK_net_1;
wire          MDDR_CLK_N_net_1;
wire          MDDR_CKE_net_1;
wire          MDDR_CS_N_net_1;
wire          MDDR_ODT_net_1;
wire          MDDR_RAS_N_net_1;
wire          MDDR_RESET_N_net_1;
wire          MDDR_WE_N_net_1;
wire   [15:0] MDDR_ADDR_net_1;
wire   [2:0]  MDDR_BA_net_1;
wire          POWER_ON_RESET_N_net_1;
wire          INIT_DONE_net_1;
wire          AMBA_MASTER_0_AWREADY_net_0;
wire          AMBA_MASTER_0_WREADY_net_0;
wire   [3:0]  AMBA_MASTER_0_BID_net_0;
wire   [1:0]  AMBA_MASTER_0_BRESP_net_0;
wire          AMBA_MASTER_0_BVALID_net_0;
wire          AMBA_MASTER_0_ARREADY_net_0;
wire   [3:0]  AMBA_MASTER_0_RID_net_0;
wire   [63:0] AMBA_MASTER_0_RDATA_net_0;
wire   [1:0]  AMBA_MASTER_0_RRESP_net_0;
wire          AMBA_MASTER_0_RLAST_net_0;
wire          AMBA_MASTER_0_RVALID_net_0;
wire          MSS_DDR_FIC_SUBSYSTEM_CLK_net_1;
wire          MSS_DDR_FIC_SUBSYSTEM_LOCK_net_1;
wire   [31:0] AMBA_MASTER_1_HRDATA_net_0;
wire          AMBA_MASTER_1_HREADY_net_0;
wire   [1:0]  AMBA_MASTER_1_HRESP_net_0;
wire          FIC_0_CLK_net_1;
wire          MSS_DDR_FIC_SUBSYSTEM_LOCK_net_2;
wire          DDR_READY_net_1;
wire          MSS_READY_net_1;
wire          GPIO_0_M2F_net_1;
wire          GPIO_1_M2F_net_1;
wire          GPIO_2_M2F_net_1;
wire          GPIO_3_M2F_net_1;
wire          GPIO_4_M2F_net_1;
wire          GPIO_5_M2F_net_1;
wire          GPIO_6_M2F_net_1;
wire          GPIO_7_M2F_net_1;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire          GND_net;
wire   [7:2]  PADDR_const_net_0;
wire   [7:0]  PWDATA_const_net_0;
wire   [31:0] FDDR_PRDATA_const_net_0;
wire          VCC_net;
wire   [31:0] SDIF0_PRDATA_const_net_0;
wire   [31:0] SDIF1_PRDATA_const_net_0;
wire   [31:0] SDIF2_PRDATA_const_net_0;
wire   [31:0] SDIF3_PRDATA_const_net_0;
wire   [31:0] SDIF0_PRDATA_const_net_1;
wire   [31:0] SDIF1_PRDATA_const_net_1;
wire   [31:0] SDIF2_PRDATA_const_net_1;
wire   [31:0] SDIF3_PRDATA_const_net_1;
wire   [31:0] HADDR_M1_const_net_0;
wire   [1:0]  HTRANS_M1_const_net_0;
wire   [2:0]  HSIZE_M1_const_net_0;
wire   [2:0]  HBURST_M1_const_net_0;
wire   [3:0]  HPROT_M1_const_net_0;
wire   [31:0] HWDATA_M1_const_net_0;
wire   [31:0] HADDR_M2_const_net_0;
wire   [1:0]  HTRANS_M2_const_net_0;
wire   [2:0]  HSIZE_M2_const_net_0;
wire   [2:0]  HBURST_M2_const_net_0;
wire   [3:0]  HPROT_M2_const_net_0;
wire   [31:0] HWDATA_M2_const_net_0;
wire   [31:0] HADDR_M3_const_net_0;
wire   [1:0]  HTRANS_M3_const_net_0;
wire   [2:0]  HSIZE_M3_const_net_0;
wire   [2:0]  HBURST_M3_const_net_0;
wire   [3:0]  HPROT_M3_const_net_0;
wire   [31:0] HWDATA_M3_const_net_0;
wire   [31:0] HRDATA_S0_const_net_0;
wire   [1:0]  HRESP_S0_const_net_0;
wire   [31:0] HRDATA_S1_const_net_0;
wire   [1:0]  HRESP_S1_const_net_0;
wire   [31:0] HRDATA_S2_const_net_0;
wire   [1:0]  HRESP_S2_const_net_0;
wire   [31:0] HRDATA_S3_const_net_0;
wire   [1:0]  HRESP_S3_const_net_0;
wire   [31:0] HRDATA_S4_const_net_0;
wire   [1:0]  HRESP_S4_const_net_0;
wire   [31:0] HRDATA_S5_const_net_0;
wire   [1:0]  HRESP_S5_const_net_0;
wire   [31:0] HRDATA_S6_const_net_0;
wire   [1:0]  HRESP_S6_const_net_0;
wire   [31:0] HRDATA_S7_const_net_0;
wire   [1:0]  HRESP_S7_const_net_0;
wire   [31:0] HRDATA_S8_const_net_0;
wire   [1:0]  HRESP_S8_const_net_0;
wire   [31:0] HRDATA_S9_const_net_0;
wire   [1:0]  HRESP_S9_const_net_0;
wire   [31:0] HRDATA_S10_const_net_0;
wire   [1:0]  HRESP_S10_const_net_0;
wire   [31:0] HRDATA_S11_const_net_0;
wire   [1:0]  HRESP_S11_const_net_0;
wire   [31:0] HRDATA_S12_const_net_0;
wire   [1:0]  HRESP_S12_const_net_0;
wire   [31:0] HRDATA_S13_const_net_0;
wire   [1:0]  HRESP_S13_const_net_0;
wire   [31:0] HRDATA_S14_const_net_0;
wire   [1:0]  HRESP_S14_const_net_0;
wire   [31:0] HRDATA_S15_const_net_0;
wire   [1:0]  HRESP_S15_const_net_0;
wire   [5:0]  BID_S1_const_net_0;
wire   [1:0]  BRESP_S1_const_net_0;
wire   [5:0]  RID_S1_const_net_0;
wire   [63:0] RDATA_S1_const_net_0;
wire   [1:0]  RRESP_S1_const_net_0;
wire   [5:0]  BID_S2_const_net_0;
wire   [1:0]  BRESP_S2_const_net_0;
wire   [5:0]  RID_S2_const_net_0;
wire   [63:0] RDATA_S2_const_net_0;
wire   [1:0]  RRESP_S2_const_net_0;
wire   [5:0]  BID_S3_const_net_0;
wire   [1:0]  BRESP_S3_const_net_0;
wire   [5:0]  RID_S3_const_net_0;
wire   [63:0] RDATA_S3_const_net_0;
wire   [1:0]  RRESP_S3_const_net_0;
wire   [5:0]  BID_S4_const_net_0;
wire   [1:0]  BRESP_S4_const_net_0;
wire   [5:0]  RID_S4_const_net_0;
wire   [63:0] RDATA_S4_const_net_0;
wire   [1:0]  RRESP_S4_const_net_0;
wire   [5:0]  BID_S5_const_net_0;
wire   [1:0]  BRESP_S5_const_net_0;
wire   [5:0]  RID_S5_const_net_0;
wire   [63:0] RDATA_S5_const_net_0;
wire   [1:0]  RRESP_S5_const_net_0;
wire   [5:0]  BID_S6_const_net_0;
wire   [1:0]  BRESP_S6_const_net_0;
wire   [5:0]  RID_S6_const_net_0;
wire   [63:0] RDATA_S6_const_net_0;
wire   [1:0]  RRESP_S6_const_net_0;
wire   [5:0]  BID_S7_const_net_0;
wire   [1:0]  BRESP_S7_const_net_0;
wire   [5:0]  RID_S7_const_net_0;
wire   [63:0] RDATA_S7_const_net_0;
wire   [1:0]  RRESP_S7_const_net_0;
wire   [5:0]  BID_S8_const_net_0;
wire   [1:0]  BRESP_S8_const_net_0;
wire   [5:0]  RID_S8_const_net_0;
wire   [63:0] RDATA_S8_const_net_0;
wire   [1:0]  RRESP_S8_const_net_0;
wire   [5:0]  BID_S9_const_net_0;
wire   [1:0]  BRESP_S9_const_net_0;
wire   [5:0]  RID_S9_const_net_0;
wire   [63:0] RDATA_S9_const_net_0;
wire   [1:0]  RRESP_S9_const_net_0;
wire   [5:0]  BID_S10_const_net_0;
wire   [1:0]  BRESP_S10_const_net_0;
wire   [5:0]  RID_S10_const_net_0;
wire   [63:0] RDATA_S10_const_net_0;
wire   [1:0]  RRESP_S10_const_net_0;
wire   [5:0]  BID_S11_const_net_0;
wire   [1:0]  BRESP_S11_const_net_0;
wire   [5:0]  RID_S11_const_net_0;
wire   [63:0] RDATA_S11_const_net_0;
wire   [1:0]  RRESP_S11_const_net_0;
wire   [5:0]  BID_S12_const_net_0;
wire   [1:0]  BRESP_S12_const_net_0;
wire   [5:0]  RID_S12_const_net_0;
wire   [63:0] RDATA_S12_const_net_0;
wire   [1:0]  RRESP_S12_const_net_0;
wire   [5:0]  BID_S13_const_net_0;
wire   [1:0]  BRESP_S13_const_net_0;
wire   [5:0]  RID_S13_const_net_0;
wire   [63:0] RDATA_S13_const_net_0;
wire   [1:0]  RRESP_S13_const_net_0;
wire   [5:0]  BID_S14_const_net_0;
wire   [1:0]  BRESP_S14_const_net_0;
wire   [5:0]  RID_S14_const_net_0;
wire   [63:0] RDATA_S14_const_net_0;
wire   [1:0]  RRESP_S14_const_net_0;
wire   [5:0]  BID_S15_const_net_0;
wire   [1:0]  BRESP_S15_const_net_0;
wire   [5:0]  RID_S15_const_net_0;
wire   [63:0] RDATA_S15_const_net_0;
wire   [1:0]  RRESP_S15_const_net_0;
wire   [5:0]  BID_S16_const_net_0;
wire   [1:0]  BRESP_S16_const_net_0;
wire   [5:0]  RID_S16_const_net_0;
wire   [63:0] RDATA_S16_const_net_0;
wire   [1:0]  RRESP_S16_const_net_0;
wire   [3:0]  AWID_M1_const_net_0;
wire   [31:0] AWADDR_M1_const_net_0;
wire   [3:0]  AWLEN_M1_const_net_0;
wire   [2:0]  AWSIZE_M1_const_net_0;
wire   [1:0]  AWBURST_M1_const_net_0;
wire   [1:0]  AWLOCK_M1_const_net_0;
wire   [3:0]  AWCACHE_M1_const_net_0;
wire   [2:0]  AWPROT_M1_const_net_0;
wire   [63:0] WDATA_M1_const_net_0;
wire   [3:0]  WID_M1_const_net_0;
wire   [7:0]  WSTRB_M1_const_net_0;
wire   [3:0]  ARID_M1_const_net_0;
wire   [31:0] ARADDR_M1_const_net_0;
wire   [3:0]  ARLEN_M1_const_net_0;
wire   [2:0]  ARSIZE_M1_const_net_0;
wire   [1:0]  ARBURST_M1_const_net_0;
wire   [1:0]  ARLOCK_M1_const_net_0;
wire   [3:0]  ARCACHE_M1_const_net_0;
wire   [2:0]  ARPROT_M1_const_net_0;
wire   [3:0]  AWID_M2_const_net_0;
wire   [31:0] AWADDR_M2_const_net_0;
wire   [3:0]  AWLEN_M2_const_net_0;
wire   [2:0]  AWSIZE_M2_const_net_0;
wire   [1:0]  AWBURST_M2_const_net_0;
wire   [1:0]  AWLOCK_M2_const_net_0;
wire   [3:0]  AWCACHE_M2_const_net_0;
wire   [2:0]  AWPROT_M2_const_net_0;
wire   [63:0] WDATA_M2_const_net_0;
wire   [3:0]  WID_M2_const_net_0;
wire   [7:0]  WSTRB_M2_const_net_0;
wire   [3:0]  ARID_M2_const_net_0;
wire   [31:0] ARADDR_M2_const_net_0;
wire   [3:0]  ARLEN_M2_const_net_0;
wire   [2:0]  ARSIZE_M2_const_net_0;
wire   [1:0]  ARBURST_M2_const_net_0;
wire   [1:0]  ARLOCK_M2_const_net_0;
wire   [3:0]  ARCACHE_M2_const_net_0;
wire   [2:0]  ARPROT_M2_const_net_0;
wire   [3:0]  AWID_M3_const_net_0;
wire   [31:0] AWADDR_M3_const_net_0;
wire   [3:0]  AWLEN_M3_const_net_0;
wire   [2:0]  AWSIZE_M3_const_net_0;
wire   [1:0]  AWBURST_M3_const_net_0;
wire   [1:0]  AWLOCK_M3_const_net_0;
wire   [3:0]  AWCACHE_M3_const_net_0;
wire   [2:0]  AWPROT_M3_const_net_0;
wire   [63:0] WDATA_M3_const_net_0;
wire   [3:0]  WID_M3_const_net_0;
wire   [7:0]  WSTRB_M3_const_net_0;
wire   [3:0]  ARID_M3_const_net_0;
wire   [31:0] ARADDR_M3_const_net_0;
wire   [3:0]  ARLEN_M3_const_net_0;
wire   [2:0]  ARSIZE_M3_const_net_0;
wire   [1:0]  ARBURST_M3_const_net_0;
wire   [1:0]  ARLOCK_M3_const_net_0;
wire   [3:0]  ARCACHE_M3_const_net_0;
wire   [2:0]  ARPROT_M3_const_net_0;
//--------------------------------------------------------------------
// Bus Interface Nets Declarations - Unequal Pin Widths
//--------------------------------------------------------------------
wire          CoreAHBLite_0_AHBmslave16_HRESP;
wire   [1:1]  CoreAHBLite_0_AHBmslave16_HRESP_0_1to1;
wire   [0:0]  CoreAHBLite_0_AHBmslave16_HRESP_0_0to0;
wire   [1:0]  CoreAHBLite_0_AHBmslave16_HRESP_0;
wire   [1:0]  CoreAHBLite_0_AHBmslave16_HSIZE_0_1to0;
wire   [1:0]  CoreAHBLite_0_AHBmslave16_HSIZE_0;
wire   [2:0]  CoreAHBLite_0_AHBmslave16_HSIZE;
wire   [3:0]  COREAXI_0_AXImslave0_ARID_0_3to0;
wire   [3:0]  COREAXI_0_AXImslave0_ARID_0;
wire   [5:0]  COREAXI_0_AXImslave0_ARID;
wire   [1:0]  COREAXI_0_AXImslave0_ARSIZE_0_1to0;
wire   [1:0]  COREAXI_0_AXImslave0_ARSIZE_0;
wire   [2:0]  COREAXI_0_AXImslave0_ARSIZE;
wire   [3:0]  COREAXI_0_AXImslave0_AWID_0_3to0;
wire   [3:0]  COREAXI_0_AXImslave0_AWID_0;
wire   [5:0]  COREAXI_0_AXImslave0_AWID;
wire   [1:0]  COREAXI_0_AXImslave0_AWSIZE_0_1to0;
wire   [1:0]  COREAXI_0_AXImslave0_AWSIZE_0;
wire   [2:0]  COREAXI_0_AXImslave0_AWSIZE;
wire   [3:0]  COREAXI_0_AXImslave0_BID;
wire   [5:4]  COREAXI_0_AXImslave0_BID_0_5to4;
wire   [3:0]  COREAXI_0_AXImslave0_BID_0_3to0;
wire   [5:0]  COREAXI_0_AXImslave0_BID_0;
wire   [3:0]  COREAXI_0_AXImslave0_RID;
wire   [5:4]  COREAXI_0_AXImslave0_RID_0_5to4;
wire   [3:0]  COREAXI_0_AXImslave0_RID_0_3to0;
wire   [5:0]  COREAXI_0_AXImslave0_RID_0;
wire   [3:0]  COREAXI_0_AXImslave0_WID_0_3to0;
wire   [3:0]  COREAXI_0_AXImslave0_WID_0;
wire   [5:0]  COREAXI_0_AXImslave0_WID;
wire   [10:2] CORECONFIGP_0_MDDR_APBmslave_PADDR_0_10to2;
wire   [10:2] CORECONFIGP_0_MDDR_APBmslave_PADDR_0;
wire   [15:2] CORECONFIGP_0_MDDR_APBmslave_PADDR;
wire   [15:0] CORECONFIGP_0_MDDR_APBmslave_PRDATA;
wire   [31:16]CORECONFIGP_0_MDDR_APBmslave_PRDATA_0_31to16;
wire   [15:0] CORECONFIGP_0_MDDR_APBmslave_PRDATA_0_15to0;
wire   [31:0] CORECONFIGP_0_MDDR_APBmslave_PRDATA_0;
wire   [15:0] CORECONFIGP_0_MDDR_APBmslave_PWDATA_0_15to0;
wire   [15:0] CORECONFIGP_0_MDDR_APBmslave_PWDATA_0;
wire   [31:0] CORECONFIGP_0_MDDR_APBmslave_PWDATA;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign GND_net                  = 1'b0;
assign PADDR_const_net_0        = 6'h00;
assign PWDATA_const_net_0       = 8'h00;
assign FDDR_PRDATA_const_net_0  = 32'h00000000;
assign VCC_net                  = 1'b1;
assign SDIF0_PRDATA_const_net_0 = 32'h00000000;
assign SDIF1_PRDATA_const_net_0 = 32'h00000000;
assign SDIF2_PRDATA_const_net_0 = 32'h00000000;
assign SDIF3_PRDATA_const_net_0 = 32'h00000000;
assign SDIF0_PRDATA_const_net_1 = 32'h00000000;
assign SDIF1_PRDATA_const_net_1 = 32'h00000000;
assign SDIF2_PRDATA_const_net_1 = 32'h00000000;
assign SDIF3_PRDATA_const_net_1 = 32'h00000000;
assign HADDR_M1_const_net_0     = 32'h00000000;
assign HTRANS_M1_const_net_0    = 2'h0;
assign HSIZE_M1_const_net_0     = 3'h0;
assign HBURST_M1_const_net_0    = 3'h0;
assign HPROT_M1_const_net_0     = 4'h0;
assign HWDATA_M1_const_net_0    = 32'h00000000;
assign HADDR_M2_const_net_0     = 32'h00000000;
assign HTRANS_M2_const_net_0    = 2'h0;
assign HSIZE_M2_const_net_0     = 3'h0;
assign HBURST_M2_const_net_0    = 3'h0;
assign HPROT_M2_const_net_0     = 4'h0;
assign HWDATA_M2_const_net_0    = 32'h00000000;
assign HADDR_M3_const_net_0     = 32'h00000000;
assign HTRANS_M3_const_net_0    = 2'h0;
assign HSIZE_M3_const_net_0     = 3'h0;
assign HBURST_M3_const_net_0    = 3'h0;
assign HPROT_M3_const_net_0     = 4'h0;
assign HWDATA_M3_const_net_0    = 32'h00000000;
assign HRDATA_S0_const_net_0    = 32'h00000000;
assign HRESP_S0_const_net_0     = 2'h0;
assign HRDATA_S1_const_net_0    = 32'h00000000;
assign HRESP_S1_const_net_0     = 2'h0;
assign HRDATA_S2_const_net_0    = 32'h00000000;
assign HRESP_S2_const_net_0     = 2'h0;
assign HRDATA_S3_const_net_0    = 32'h00000000;
assign HRESP_S3_const_net_0     = 2'h0;
assign HRDATA_S4_const_net_0    = 32'h00000000;
assign HRESP_S4_const_net_0     = 2'h0;
assign HRDATA_S5_const_net_0    = 32'h00000000;
assign HRESP_S5_const_net_0     = 2'h0;
assign HRDATA_S6_const_net_0    = 32'h00000000;
assign HRESP_S6_const_net_0     = 2'h0;
assign HRDATA_S7_const_net_0    = 32'h00000000;
assign HRESP_S7_const_net_0     = 2'h0;
assign HRDATA_S8_const_net_0    = 32'h00000000;
assign HRESP_S8_const_net_0     = 2'h0;
assign HRDATA_S9_const_net_0    = 32'h00000000;
assign HRESP_S9_const_net_0     = 2'h0;
assign HRDATA_S10_const_net_0   = 32'h00000000;
assign HRESP_S10_const_net_0    = 2'h0;
assign HRDATA_S11_const_net_0   = 32'h00000000;
assign HRESP_S11_const_net_0    = 2'h0;
assign HRDATA_S12_const_net_0   = 32'h00000000;
assign HRESP_S12_const_net_0    = 2'h0;
assign HRDATA_S13_const_net_0   = 32'h00000000;
assign HRESP_S13_const_net_0    = 2'h0;
assign HRDATA_S14_const_net_0   = 32'h00000000;
assign HRESP_S14_const_net_0    = 2'h0;
assign HRDATA_S15_const_net_0   = 32'h00000000;
assign HRESP_S15_const_net_0    = 2'h0;
assign BID_S1_const_net_0       = 6'h00;
assign BRESP_S1_const_net_0     = 2'h0;
assign RID_S1_const_net_0       = 6'h00;
assign RDATA_S1_const_net_0     = 64'h0000000000000000;
assign RRESP_S1_const_net_0     = 2'h0;
assign BID_S2_const_net_0       = 6'h00;
assign BRESP_S2_const_net_0     = 2'h0;
assign RID_S2_const_net_0       = 6'h00;
assign RDATA_S2_const_net_0     = 64'h0000000000000000;
assign RRESP_S2_const_net_0     = 2'h0;
assign BID_S3_const_net_0       = 6'h00;
assign BRESP_S3_const_net_0     = 2'h0;
assign RID_S3_const_net_0       = 6'h00;
assign RDATA_S3_const_net_0     = 64'h0000000000000000;
assign RRESP_S3_const_net_0     = 2'h0;
assign BID_S4_const_net_0       = 6'h00;
assign BRESP_S4_const_net_0     = 2'h0;
assign RID_S4_const_net_0       = 6'h00;
assign RDATA_S4_const_net_0     = 64'h0000000000000000;
assign RRESP_S4_const_net_0     = 2'h0;
assign BID_S5_const_net_0       = 6'h00;
assign BRESP_S5_const_net_0     = 2'h0;
assign RID_S5_const_net_0       = 6'h00;
assign RDATA_S5_const_net_0     = 64'h0000000000000000;
assign RRESP_S5_const_net_0     = 2'h0;
assign BID_S6_const_net_0       = 6'h00;
assign BRESP_S6_const_net_0     = 2'h0;
assign RID_S6_const_net_0       = 6'h00;
assign RDATA_S6_const_net_0     = 64'h0000000000000000;
assign RRESP_S6_const_net_0     = 2'h0;
assign BID_S7_const_net_0       = 6'h00;
assign BRESP_S7_const_net_0     = 2'h0;
assign RID_S7_const_net_0       = 6'h00;
assign RDATA_S7_const_net_0     = 64'h0000000000000000;
assign RRESP_S7_const_net_0     = 2'h0;
assign BID_S8_const_net_0       = 6'h00;
assign BRESP_S8_const_net_0     = 2'h0;
assign RID_S8_const_net_0       = 6'h00;
assign RDATA_S8_const_net_0     = 64'h0000000000000000;
assign RRESP_S8_const_net_0     = 2'h0;
assign BID_S9_const_net_0       = 6'h00;
assign BRESP_S9_const_net_0     = 2'h0;
assign RID_S9_const_net_0       = 6'h00;
assign RDATA_S9_const_net_0     = 64'h0000000000000000;
assign RRESP_S9_const_net_0     = 2'h0;
assign BID_S10_const_net_0      = 6'h00;
assign BRESP_S10_const_net_0    = 2'h0;
assign RID_S10_const_net_0      = 6'h00;
assign RDATA_S10_const_net_0    = 64'h0000000000000000;
assign RRESP_S10_const_net_0    = 2'h0;
assign BID_S11_const_net_0      = 6'h00;
assign BRESP_S11_const_net_0    = 2'h0;
assign RID_S11_const_net_0      = 6'h00;
assign RDATA_S11_const_net_0    = 64'h0000000000000000;
assign RRESP_S11_const_net_0    = 2'h0;
assign BID_S12_const_net_0      = 6'h00;
assign BRESP_S12_const_net_0    = 2'h0;
assign RID_S12_const_net_0      = 6'h00;
assign RDATA_S12_const_net_0    = 64'h0000000000000000;
assign RRESP_S12_const_net_0    = 2'h0;
assign BID_S13_const_net_0      = 6'h00;
assign BRESP_S13_const_net_0    = 2'h0;
assign RID_S13_const_net_0      = 6'h00;
assign RDATA_S13_const_net_0    = 64'h0000000000000000;
assign RRESP_S13_const_net_0    = 2'h0;
assign BID_S14_const_net_0      = 6'h00;
assign BRESP_S14_const_net_0    = 2'h0;
assign RID_S14_const_net_0      = 6'h00;
assign RDATA_S14_const_net_0    = 64'h0000000000000000;
assign RRESP_S14_const_net_0    = 2'h0;
assign BID_S15_const_net_0      = 6'h00;
assign BRESP_S15_const_net_0    = 2'h0;
assign RID_S15_const_net_0      = 6'h00;
assign RDATA_S15_const_net_0    = 64'h0000000000000000;
assign RRESP_S15_const_net_0    = 2'h0;
assign BID_S16_const_net_0      = 6'h00;
assign BRESP_S16_const_net_0    = 2'h0;
assign RID_S16_const_net_0      = 6'h00;
assign RDATA_S16_const_net_0    = 64'h0000000000000000;
assign RRESP_S16_const_net_0    = 2'h0;
assign AWID_M1_const_net_0      = 4'h0;
assign AWADDR_M1_const_net_0    = 32'h00000000;
assign AWLEN_M1_const_net_0     = 4'h0;
assign AWSIZE_M1_const_net_0    = 3'h0;
assign AWBURST_M1_const_net_0   = 2'h0;
assign AWLOCK_M1_const_net_0    = 2'h0;
assign AWCACHE_M1_const_net_0   = 4'h0;
assign AWPROT_M1_const_net_0    = 3'h0;
assign WDATA_M1_const_net_0     = 64'h0000000000000000;
assign WID_M1_const_net_0       = 4'h0;
assign WSTRB_M1_const_net_0     = 8'h00;
assign ARID_M1_const_net_0      = 4'h0;
assign ARADDR_M1_const_net_0    = 32'h00000000;
assign ARLEN_M1_const_net_0     = 4'h0;
assign ARSIZE_M1_const_net_0    = 3'h0;
assign ARBURST_M1_const_net_0   = 2'h0;
assign ARLOCK_M1_const_net_0    = 2'h0;
assign ARCACHE_M1_const_net_0   = 4'h0;
assign ARPROT_M1_const_net_0    = 3'h0;
assign AWID_M2_const_net_0      = 4'h0;
assign AWADDR_M2_const_net_0    = 32'h00000000;
assign AWLEN_M2_const_net_0     = 4'h0;
assign AWSIZE_M2_const_net_0    = 3'h0;
assign AWBURST_M2_const_net_0   = 2'h0;
assign AWLOCK_M2_const_net_0    = 2'h0;
assign AWCACHE_M2_const_net_0   = 4'h0;
assign AWPROT_M2_const_net_0    = 3'h0;
assign WDATA_M2_const_net_0     = 64'h0000000000000000;
assign WID_M2_const_net_0       = 4'h0;
assign WSTRB_M2_const_net_0     = 8'h00;
assign ARID_M2_const_net_0      = 4'h0;
assign ARADDR_M2_const_net_0    = 32'h00000000;
assign ARLEN_M2_const_net_0     = 4'h0;
assign ARSIZE_M2_const_net_0    = 3'h0;
assign ARBURST_M2_const_net_0   = 2'h0;
assign ARLOCK_M2_const_net_0    = 2'h0;
assign ARCACHE_M2_const_net_0   = 4'h0;
assign ARPROT_M2_const_net_0    = 3'h0;
assign AWID_M3_const_net_0      = 4'h0;
assign AWADDR_M3_const_net_0    = 32'h00000000;
assign AWLEN_M3_const_net_0     = 4'h0;
assign AWSIZE_M3_const_net_0    = 3'h0;
assign AWBURST_M3_const_net_0   = 2'h0;
assign AWLOCK_M3_const_net_0    = 2'h0;
assign AWCACHE_M3_const_net_0   = 4'h0;
assign AWPROT_M3_const_net_0    = 3'h0;
assign WDATA_M3_const_net_0     = 64'h0000000000000000;
assign WID_M3_const_net_0       = 4'h0;
assign WSTRB_M3_const_net_0     = 8'h00;
assign ARID_M3_const_net_0      = 4'h0;
assign ARADDR_M3_const_net_0    = 32'h00000000;
assign ARLEN_M3_const_net_0     = 4'h0;
assign ARSIZE_M3_const_net_0    = 3'h0;
assign ARBURST_M3_const_net_0   = 2'h0;
assign ARLOCK_M3_const_net_0    = 2'h0;
assign ARCACHE_M3_const_net_0   = 4'h0;
assign ARPROT_M3_const_net_0    = 3'h0;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign MMUART_0_TXD_net_1               = MMUART_0_TXD_net_0;
assign MMUART_0_TXD                     = MMUART_0_TXD_net_1;
assign MDDR_DQS_TMATCH_0_OUT_net_1      = MDDR_DQS_TMATCH_0_OUT_net_0;
assign MDDR_DQS_TMATCH_0_OUT            = MDDR_DQS_TMATCH_0_OUT_net_1;
assign MDDR_CAS_N_net_1                 = MDDR_CAS_N_net_0;
assign MDDR_CAS_N                       = MDDR_CAS_N_net_1;
assign MDDR_CLK_net_1                   = MDDR_CLK_net_0;
assign MDDR_CLK                         = MDDR_CLK_net_1;
assign MDDR_CLK_N_net_1                 = MDDR_CLK_N_net_0;
assign MDDR_CLK_N                       = MDDR_CLK_N_net_1;
assign MDDR_CKE_net_1                   = MDDR_CKE_net_0;
assign MDDR_CKE                         = MDDR_CKE_net_1;
assign MDDR_CS_N_net_1                  = MDDR_CS_N_net_0;
assign MDDR_CS_N                        = MDDR_CS_N_net_1;
assign MDDR_ODT_net_1                   = MDDR_ODT_net_0;
assign MDDR_ODT                         = MDDR_ODT_net_1;
assign MDDR_RAS_N_net_1                 = MDDR_RAS_N_net_0;
assign MDDR_RAS_N                       = MDDR_RAS_N_net_1;
assign MDDR_RESET_N_net_1               = MDDR_RESET_N_net_0;
assign MDDR_RESET_N                     = MDDR_RESET_N_net_1;
assign MDDR_WE_N_net_1                  = MDDR_WE_N_net_0;
assign MDDR_WE_N                        = MDDR_WE_N_net_1;
assign MDDR_ADDR_net_1                  = MDDR_ADDR_net_0;
assign MDDR_ADDR[15:0]                  = MDDR_ADDR_net_1;
assign MDDR_BA_net_1                    = MDDR_BA_net_0;
assign MDDR_BA[2:0]                     = MDDR_BA_net_1;
assign POWER_ON_RESET_N_net_1           = POWER_ON_RESET_N_net_0;
assign POWER_ON_RESET_N                 = POWER_ON_RESET_N_net_1;
assign INIT_DONE_net_1                  = INIT_DONE_net_0;
assign INIT_DONE                        = INIT_DONE_net_1;
assign AMBA_MASTER_0_AWREADY_net_0      = AMBA_MASTER_0_AWREADY;
assign AMBA_MASTER_0_AWREADY_M0         = AMBA_MASTER_0_AWREADY_net_0;
assign AMBA_MASTER_0_WREADY_net_0       = AMBA_MASTER_0_WREADY;
assign AMBA_MASTER_0_WREADY_M0          = AMBA_MASTER_0_WREADY_net_0;
assign AMBA_MASTER_0_BID_net_0          = AMBA_MASTER_0_BID;
assign AMBA_MASTER_0_BID_M0[3:0]        = AMBA_MASTER_0_BID_net_0;
assign AMBA_MASTER_0_BRESP_net_0        = AMBA_MASTER_0_BRESP;
assign AMBA_MASTER_0_BRESP_M0[1:0]      = AMBA_MASTER_0_BRESP_net_0;
assign AMBA_MASTER_0_BVALID_net_0       = AMBA_MASTER_0_BVALID;
assign AMBA_MASTER_0_BVALID_M0          = AMBA_MASTER_0_BVALID_net_0;
assign AMBA_MASTER_0_ARREADY_net_0      = AMBA_MASTER_0_ARREADY;
assign AMBA_MASTER_0_ARREADY_M0         = AMBA_MASTER_0_ARREADY_net_0;
assign AMBA_MASTER_0_RID_net_0          = AMBA_MASTER_0_RID;
assign AMBA_MASTER_0_RID_M0[3:0]        = AMBA_MASTER_0_RID_net_0;
assign AMBA_MASTER_0_RDATA_net_0        = AMBA_MASTER_0_RDATA;
assign AMBA_MASTER_0_RDATA_M0[63:0]     = AMBA_MASTER_0_RDATA_net_0;
assign AMBA_MASTER_0_RRESP_net_0        = AMBA_MASTER_0_RRESP;
assign AMBA_MASTER_0_RRESP_M0[1:0]      = AMBA_MASTER_0_RRESP_net_0;
assign AMBA_MASTER_0_RLAST_net_0        = AMBA_MASTER_0_RLAST;
assign AMBA_MASTER_0_RLAST_M0           = AMBA_MASTER_0_RLAST_net_0;
assign AMBA_MASTER_0_RVALID_net_0       = AMBA_MASTER_0_RVALID;
assign AMBA_MASTER_0_RVALID_M0          = AMBA_MASTER_0_RVALID_net_0;
assign MSS_DDR_FIC_SUBSYSTEM_CLK_net_1  = MSS_DDR_FIC_SUBSYSTEM_CLK_net_0;
assign MSS_DDR_FIC_SUBSYSTEM_CLK        = MSS_DDR_FIC_SUBSYSTEM_CLK_net_1;
assign MSS_DDR_FIC_SUBSYSTEM_LOCK_net_1 = MSS_DDR_FIC_SUBSYSTEM_LOCK_net_0;
assign MSS_DDR_FIC_SUBSYSTEM_LOCK       = MSS_DDR_FIC_SUBSYSTEM_LOCK_net_1;
assign AMBA_MASTER_1_HRDATA_net_0       = AMBA_MASTER_1_HRDATA;
assign AMBA_MASTER_1_HRDATA_M0[31:0]    = AMBA_MASTER_1_HRDATA_net_0;
assign AMBA_MASTER_1_HREADY_net_0       = AMBA_MASTER_1_HREADY;
assign AMBA_MASTER_1_HREADY_M0          = AMBA_MASTER_1_HREADY_net_0;
assign AMBA_MASTER_1_HRESP_net_0        = AMBA_MASTER_1_HRESP;
assign AMBA_MASTER_1_HRESP_M0[1:0]      = AMBA_MASTER_1_HRESP_net_0;
assign FIC_0_CLK_net_1                  = FIC_0_CLK_net_0;
assign FIC_0_CLK                        = FIC_0_CLK_net_1;
assign MSS_DDR_FIC_SUBSYSTEM_LOCK_net_2 = MSS_DDR_FIC_SUBSYSTEM_LOCK_net_0;
assign FIC_0_LOCK                       = MSS_DDR_FIC_SUBSYSTEM_LOCK_net_2;
assign DDR_READY_net_1                  = DDR_READY_net_0;
assign DDR_READY                        = DDR_READY_net_1;
assign MSS_READY_net_1                  = MSS_READY_net_0;
assign MSS_READY                        = MSS_READY_net_1;
assign GPIO_0_M2F_net_1                 = GPIO_0_M2F_net_0;
assign GPIO_0_M2F                       = GPIO_0_M2F_net_1;
assign GPIO_1_M2F_net_1                 = GPIO_1_M2F_net_0;
assign GPIO_1_M2F                       = GPIO_1_M2F_net_1;
assign GPIO_2_M2F_net_1                 = GPIO_2_M2F_net_0;
assign GPIO_2_M2F                       = GPIO_2_M2F_net_1;
assign GPIO_3_M2F_net_1                 = GPIO_3_M2F_net_0;
assign GPIO_3_M2F                       = GPIO_3_M2F_net_1;
assign GPIO_4_M2F_net_1                 = GPIO_4_M2F_net_0;
assign GPIO_4_M2F                       = GPIO_4_M2F_net_1;
assign GPIO_5_M2F_net_1                 = GPIO_5_M2F_net_0;
assign GPIO_5_M2F                       = GPIO_5_M2F_net_1;
assign GPIO_6_M2F_net_1                 = GPIO_6_M2F_net_0;
assign GPIO_6_M2F                       = GPIO_6_M2F_net_1;
assign GPIO_7_M2F_net_1                 = GPIO_7_M2F_net_0;
assign GPIO_7_M2F                       = GPIO_7_M2F_net_1;
//--------------------------------------------------------------------
// Bus Interface Nets Assignments - Unequal Pin Widths
//--------------------------------------------------------------------
assign CoreAHBLite_0_AHBmslave16_HRESP_0_1to1 = 1'b0;
assign CoreAHBLite_0_AHBmslave16_HRESP_0_0to0 = CoreAHBLite_0_AHBmslave16_HRESP;
assign CoreAHBLite_0_AHBmslave16_HRESP_0 = { CoreAHBLite_0_AHBmslave16_HRESP_0_1to1, CoreAHBLite_0_AHBmslave16_HRESP_0_0to0 };

assign CoreAHBLite_0_AHBmslave16_HSIZE_0_1to0 = CoreAHBLite_0_AHBmslave16_HSIZE[1:0];
assign CoreAHBLite_0_AHBmslave16_HSIZE_0 = { CoreAHBLite_0_AHBmslave16_HSIZE_0_1to0 };

assign COREAXI_0_AXImslave0_ARID_0_3to0 = COREAXI_0_AXImslave0_ARID[3:0];
assign COREAXI_0_AXImslave0_ARID_0 = { COREAXI_0_AXImslave0_ARID_0_3to0 };

assign COREAXI_0_AXImslave0_ARSIZE_0_1to0 = COREAXI_0_AXImslave0_ARSIZE[1:0];
assign COREAXI_0_AXImslave0_ARSIZE_0 = { COREAXI_0_AXImslave0_ARSIZE_0_1to0 };

assign COREAXI_0_AXImslave0_AWID_0_3to0 = COREAXI_0_AXImslave0_AWID[3:0];
assign COREAXI_0_AXImslave0_AWID_0 = { COREAXI_0_AXImslave0_AWID_0_3to0 };

assign COREAXI_0_AXImslave0_AWSIZE_0_1to0 = COREAXI_0_AXImslave0_AWSIZE[1:0];
assign COREAXI_0_AXImslave0_AWSIZE_0 = { COREAXI_0_AXImslave0_AWSIZE_0_1to0 };

assign COREAXI_0_AXImslave0_BID_0_5to4 = 2'h0;
assign COREAXI_0_AXImslave0_BID_0_3to0 = COREAXI_0_AXImslave0_BID[3:0];
assign COREAXI_0_AXImslave0_BID_0 = { COREAXI_0_AXImslave0_BID_0_5to4, COREAXI_0_AXImslave0_BID_0_3to0 };

assign COREAXI_0_AXImslave0_RID_0_5to4 = 2'h0;
assign COREAXI_0_AXImslave0_RID_0_3to0 = COREAXI_0_AXImslave0_RID[3:0];
assign COREAXI_0_AXImslave0_RID_0 = { COREAXI_0_AXImslave0_RID_0_5to4, COREAXI_0_AXImslave0_RID_0_3to0 };

assign COREAXI_0_AXImslave0_WID_0_3to0 = COREAXI_0_AXImslave0_WID[3:0];
assign COREAXI_0_AXImslave0_WID_0 = { COREAXI_0_AXImslave0_WID_0_3to0 };

assign CORECONFIGP_0_MDDR_APBmslave_PADDR_0_10to2 = CORECONFIGP_0_MDDR_APBmslave_PADDR[10:2];
assign CORECONFIGP_0_MDDR_APBmslave_PADDR_0 = { CORECONFIGP_0_MDDR_APBmslave_PADDR_0_10to2 };

assign CORECONFIGP_0_MDDR_APBmslave_PRDATA_0_31to16 = 16'h0;
assign CORECONFIGP_0_MDDR_APBmslave_PRDATA_0_15to0 = CORECONFIGP_0_MDDR_APBmslave_PRDATA[15:0];
assign CORECONFIGP_0_MDDR_APBmslave_PRDATA_0 = { CORECONFIGP_0_MDDR_APBmslave_PRDATA_0_31to16, CORECONFIGP_0_MDDR_APBmslave_PRDATA_0_15to0 };

assign CORECONFIGP_0_MDDR_APBmslave_PWDATA_0_15to0 = CORECONFIGP_0_MDDR_APBmslave_PWDATA[15:0];
assign CORECONFIGP_0_MDDR_APBmslave_PWDATA_0 = { CORECONFIGP_0_MDDR_APBmslave_PWDATA_0_15to0 };

//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------MDDR_TA_CCC_0_FCCC   -   Actel:SgCore:FCCC:2.0.200
MDDR_TA_CCC_0_FCCC CCC_0(
        // Inputs
        .RCOSC_25_50MHZ ( FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC ),
        // Outputs
        .GL0            ( FIC_0_CLK_net_0 ),
        .GL2            ( MSS_DDR_FIC_SUBSYSTEM_CLK_net_0 ),
        .LOCK           ( MSS_DDR_FIC_SUBSYSTEM_LOCK_net_0 ) 
        );

//--------CoreAHBLite   -   Actel:DirectCore:CoreAHBLite:5.2.100
CoreAHBLite #( 
        .FAMILY             ( 19 ),
        .HADDR_SHG_CFG      ( 1 ),
        .M0_AHBSLOT0ENABLE  ( 0 ),
        .M0_AHBSLOT1ENABLE  ( 0 ),
        .M0_AHBSLOT2ENABLE  ( 0 ),
        .M0_AHBSLOT3ENABLE  ( 0 ),
        .M0_AHBSLOT4ENABLE  ( 0 ),
        .M0_AHBSLOT5ENABLE  ( 0 ),
        .M0_AHBSLOT6ENABLE  ( 0 ),
        .M0_AHBSLOT7ENABLE  ( 0 ),
        .M0_AHBSLOT8ENABLE  ( 0 ),
        .M0_AHBSLOT9ENABLE  ( 0 ),
        .M0_AHBSLOT10ENABLE ( 0 ),
        .M0_AHBSLOT11ENABLE ( 0 ),
        .M0_AHBSLOT12ENABLE ( 0 ),
        .M0_AHBSLOT13ENABLE ( 0 ),
        .M0_AHBSLOT14ENABLE ( 0 ),
        .M0_AHBSLOT15ENABLE ( 0 ),
        .M0_AHBSLOT16ENABLE ( 1 ),
        .M1_AHBSLOT0ENABLE  ( 0 ),
        .M1_AHBSLOT1ENABLE  ( 0 ),
        .M1_AHBSLOT2ENABLE  ( 0 ),
        .M1_AHBSLOT3ENABLE  ( 0 ),
        .M1_AHBSLOT4ENABLE  ( 0 ),
        .M1_AHBSLOT5ENABLE  ( 0 ),
        .M1_AHBSLOT6ENABLE  ( 0 ),
        .M1_AHBSLOT7ENABLE  ( 0 ),
        .M1_AHBSLOT8ENABLE  ( 0 ),
        .M1_AHBSLOT9ENABLE  ( 0 ),
        .M1_AHBSLOT10ENABLE ( 0 ),
        .M1_AHBSLOT11ENABLE ( 0 ),
        .M1_AHBSLOT12ENABLE ( 0 ),
        .M1_AHBSLOT13ENABLE ( 0 ),
        .M1_AHBSLOT14ENABLE ( 0 ),
        .M1_AHBSLOT15ENABLE ( 0 ),
        .M1_AHBSLOT16ENABLE ( 0 ),
        .M2_AHBSLOT0ENABLE  ( 0 ),
        .M2_AHBSLOT1ENABLE  ( 0 ),
        .M2_AHBSLOT2ENABLE  ( 0 ),
        .M2_AHBSLOT3ENABLE  ( 0 ),
        .M2_AHBSLOT4ENABLE  ( 0 ),
        .M2_AHBSLOT5ENABLE  ( 0 ),
        .M2_AHBSLOT6ENABLE  ( 0 ),
        .M2_AHBSLOT7ENABLE  ( 0 ),
        .M2_AHBSLOT8ENABLE  ( 0 ),
        .M2_AHBSLOT9ENABLE  ( 0 ),
        .M2_AHBSLOT10ENABLE ( 0 ),
        .M2_AHBSLOT11ENABLE ( 0 ),
        .M2_AHBSLOT12ENABLE ( 0 ),
        .M2_AHBSLOT13ENABLE ( 0 ),
        .M2_AHBSLOT14ENABLE ( 0 ),
        .M2_AHBSLOT15ENABLE ( 0 ),
        .M2_AHBSLOT16ENABLE ( 0 ),
        .M3_AHBSLOT0ENABLE  ( 0 ),
        .M3_AHBSLOT1ENABLE  ( 0 ),
        .M3_AHBSLOT2ENABLE  ( 0 ),
        .M3_AHBSLOT3ENABLE  ( 0 ),
        .M3_AHBSLOT4ENABLE  ( 0 ),
        .M3_AHBSLOT5ENABLE  ( 0 ),
        .M3_AHBSLOT6ENABLE  ( 0 ),
        .M3_AHBSLOT7ENABLE  ( 0 ),
        .M3_AHBSLOT8ENABLE  ( 0 ),
        .M3_AHBSLOT9ENABLE  ( 0 ),
        .M3_AHBSLOT10ENABLE ( 0 ),
        .M3_AHBSLOT11ENABLE ( 0 ),
        .M3_AHBSLOT12ENABLE ( 0 ),
        .M3_AHBSLOT13ENABLE ( 0 ),
        .M3_AHBSLOT14ENABLE ( 0 ),
        .M3_AHBSLOT15ENABLE ( 0 ),
        .M3_AHBSLOT16ENABLE ( 0 ),
        .MEMSPACE           ( 1 ),
        .SC_0               ( 1 ),
        .SC_1               ( 0 ),
        .SC_2               ( 1 ),
        .SC_3               ( 0 ),
        .SC_4               ( 1 ),
        .SC_5               ( 0 ),
        .SC_6               ( 1 ),
        .SC_7               ( 0 ),
        .SC_8               ( 0 ),
        .SC_9               ( 0 ),
        .SC_10              ( 0 ),
        .SC_11              ( 0 ),
        .SC_12              ( 0 ),
        .SC_13              ( 0 ),
        .SC_14              ( 0 ),
        .SC_15              ( 0 ) )
CoreAHBLite_0(
        // Inputs
        .HCLK          ( FIC_0_CLK_net_0 ),
        .HRESETN       ( MSS_READY_net_0 ),
        .REMAP_M0      ( GND_net ),
        .HADDR_M0      ( AMBA_MASTER_1_HADDR_M0 ),
        .HMASTLOCK_M0  ( AMBA_MASTER_1_HMASTLOCK_M0 ),
        .HSIZE_M0      ( AMBA_MASTER_1_HSIZE_M0 ),
        .HTRANS_M0     ( AMBA_MASTER_1_HTRANS_M0 ),
        .HWRITE_M0     ( AMBA_MASTER_1_HWRITE_M0 ),
        .HWDATA_M0     ( AMBA_MASTER_1_HWDATA_M0 ),
        .HBURST_M0     ( AMBA_MASTER_1_HBURST_M0 ),
        .HPROT_M0      ( AMBA_MASTER_1_HPROT_M0 ),
        .HADDR_M1      ( HADDR_M1_const_net_0 ), // tied to 32'h00000000 from definition
        .HMASTLOCK_M1  ( GND_net ), // tied to 1'b0 from definition
        .HSIZE_M1      ( HSIZE_M1_const_net_0 ), // tied to 3'h0 from definition
        .HTRANS_M1     ( HTRANS_M1_const_net_0 ), // tied to 2'h0 from definition
        .HWRITE_M1     ( GND_net ), // tied to 1'b0 from definition
        .HWDATA_M1     ( HWDATA_M1_const_net_0 ), // tied to 32'h00000000 from definition
        .HBURST_M1     ( HBURST_M1_const_net_0 ), // tied to 3'h0 from definition
        .HPROT_M1      ( HPROT_M1_const_net_0 ), // tied to 4'h0 from definition
        .HADDR_M2      ( HADDR_M2_const_net_0 ), // tied to 32'h00000000 from definition
        .HMASTLOCK_M2  ( GND_net ), // tied to 1'b0 from definition
        .HSIZE_M2      ( HSIZE_M2_const_net_0 ), // tied to 3'h0 from definition
        .HTRANS_M2     ( HTRANS_M2_const_net_0 ), // tied to 2'h0 from definition
        .HWRITE_M2     ( GND_net ), // tied to 1'b0 from definition
        .HWDATA_M2     ( HWDATA_M2_const_net_0 ), // tied to 32'h00000000 from definition
        .HBURST_M2     ( HBURST_M2_const_net_0 ), // tied to 3'h0 from definition
        .HPROT_M2      ( HPROT_M2_const_net_0 ), // tied to 4'h0 from definition
        .HADDR_M3      ( HADDR_M3_const_net_0 ), // tied to 32'h00000000 from definition
        .HMASTLOCK_M3  ( GND_net ), // tied to 1'b0 from definition
        .HSIZE_M3      ( HSIZE_M3_const_net_0 ), // tied to 3'h0 from definition
        .HTRANS_M3     ( HTRANS_M3_const_net_0 ), // tied to 2'h0 from definition
        .HWRITE_M3     ( GND_net ), // tied to 1'b0 from definition
        .HWDATA_M3     ( HWDATA_M3_const_net_0 ), // tied to 32'h00000000 from definition
        .HBURST_M3     ( HBURST_M3_const_net_0 ), // tied to 3'h0 from definition
        .HPROT_M3      ( HPROT_M3_const_net_0 ), // tied to 4'h0 from definition
        .HRDATA_S0     ( HRDATA_S0_const_net_0 ), // tied to 32'h00000000 from definition
        .HREADYOUT_S0  ( VCC_net ), // tied to 1'b1 from definition
        .HRESP_S0      ( HRESP_S0_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S1     ( HRDATA_S1_const_net_0 ), // tied to 32'h00000000 from definition
        .HREADYOUT_S1  ( VCC_net ), // tied to 1'b1 from definition
        .HRESP_S1      ( HRESP_S1_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S2     ( HRDATA_S2_const_net_0 ), // tied to 32'h00000000 from definition
        .HREADYOUT_S2  ( VCC_net ), // tied to 1'b1 from definition
        .HRESP_S2      ( HRESP_S2_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S3     ( HRDATA_S3_const_net_0 ), // tied to 32'h00000000 from definition
        .HREADYOUT_S3  ( VCC_net ), // tied to 1'b1 from definition
        .HRESP_S3      ( HRESP_S3_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S4     ( HRDATA_S4_const_net_0 ), // tied to 32'h00000000 from definition
        .HREADYOUT_S4  ( VCC_net ), // tied to 1'b1 from definition
        .HRESP_S4      ( HRESP_S4_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S5     ( HRDATA_S5_const_net_0 ), // tied to 32'h00000000 from definition
        .HREADYOUT_S5  ( VCC_net ), // tied to 1'b1 from definition
        .HRESP_S5      ( HRESP_S5_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S6     ( HRDATA_S6_const_net_0 ), // tied to 32'h00000000 from definition
        .HREADYOUT_S6  ( VCC_net ), // tied to 1'b1 from definition
        .HRESP_S6      ( HRESP_S6_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S7     ( HRDATA_S7_const_net_0 ), // tied to 32'h00000000 from definition
        .HREADYOUT_S7  ( VCC_net ), // tied to 1'b1 from definition
        .HRESP_S7      ( HRESP_S7_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S8     ( HRDATA_S8_const_net_0 ), // tied to 32'h00000000 from definition
        .HREADYOUT_S8  ( VCC_net ), // tied to 1'b1 from definition
        .HRESP_S8      ( HRESP_S8_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S9     ( HRDATA_S9_const_net_0 ), // tied to 32'h00000000 from definition
        .HREADYOUT_S9  ( VCC_net ), // tied to 1'b1 from definition
        .HRESP_S9      ( HRESP_S9_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S10    ( HRDATA_S10_const_net_0 ), // tied to 32'h00000000 from definition
        .HREADYOUT_S10 ( VCC_net ), // tied to 1'b1 from definition
        .HRESP_S10     ( HRESP_S10_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S11    ( HRDATA_S11_const_net_0 ), // tied to 32'h00000000 from definition
        .HREADYOUT_S11 ( VCC_net ), // tied to 1'b1 from definition
        .HRESP_S11     ( HRESP_S11_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S12    ( HRDATA_S12_const_net_0 ), // tied to 32'h00000000 from definition
        .HREADYOUT_S12 ( VCC_net ), // tied to 1'b1 from definition
        .HRESP_S12     ( HRESP_S12_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S13    ( HRDATA_S13_const_net_0 ), // tied to 32'h00000000 from definition
        .HREADYOUT_S13 ( VCC_net ), // tied to 1'b1 from definition
        .HRESP_S13     ( HRESP_S13_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S14    ( HRDATA_S14_const_net_0 ), // tied to 32'h00000000 from definition
        .HREADYOUT_S14 ( VCC_net ), // tied to 1'b1 from definition
        .HRESP_S14     ( HRESP_S14_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S15    ( HRDATA_S15_const_net_0 ), // tied to 32'h00000000 from definition
        .HREADYOUT_S15 ( VCC_net ), // tied to 1'b1 from definition
        .HRESP_S15     ( HRESP_S15_const_net_0 ), // tied to 2'h0 from definition
        .HRDATA_S16    ( CoreAHBLite_0_AHBmslave16_HRDATA ),
        .HREADYOUT_S16 ( CoreAHBLite_0_AHBmslave16_HREADYOUT ),
        .HRESP_S16     ( CoreAHBLite_0_AHBmslave16_HRESP_0 ),
        // Outputs
        .HRESP_M0      ( AMBA_MASTER_1_HRESP ),
        .HRDATA_M0     ( AMBA_MASTER_1_HRDATA ),
        .HREADY_M0     ( AMBA_MASTER_1_HREADY ),
        .HRESP_M1      (  ),
        .HRDATA_M1     (  ),
        .HREADY_M1     (  ),
        .HRESP_M2      (  ),
        .HRDATA_M2     (  ),
        .HREADY_M2     (  ),
        .HRESP_M3      (  ),
        .HRDATA_M3     (  ),
        .HREADY_M3     (  ),
        .HSEL_S0       (  ),
        .HADDR_S0      (  ),
        .HSIZE_S0      (  ),
        .HTRANS_S0     (  ),
        .HWRITE_S0     (  ),
        .HWDATA_S0     (  ),
        .HREADY_S0     (  ),
        .HMASTLOCK_S0  (  ),
        .HBURST_S0     (  ),
        .HPROT_S0      (  ),
        .HSEL_S1       (  ),
        .HADDR_S1      (  ),
        .HSIZE_S1      (  ),
        .HTRANS_S1     (  ),
        .HWRITE_S1     (  ),
        .HWDATA_S1     (  ),
        .HREADY_S1     (  ),
        .HMASTLOCK_S1  (  ),
        .HBURST_S1     (  ),
        .HPROT_S1      (  ),
        .HSEL_S2       (  ),
        .HADDR_S2      (  ),
        .HSIZE_S2      (  ),
        .HTRANS_S2     (  ),
        .HWRITE_S2     (  ),
        .HWDATA_S2     (  ),
        .HREADY_S2     (  ),
        .HMASTLOCK_S2  (  ),
        .HBURST_S2     (  ),
        .HPROT_S2      (  ),
        .HSEL_S3       (  ),
        .HADDR_S3      (  ),
        .HSIZE_S3      (  ),
        .HTRANS_S3     (  ),
        .HWRITE_S3     (  ),
        .HWDATA_S3     (  ),
        .HREADY_S3     (  ),
        .HMASTLOCK_S3  (  ),
        .HBURST_S3     (  ),
        .HPROT_S3      (  ),
        .HSEL_S4       (  ),
        .HADDR_S4      (  ),
        .HSIZE_S4      (  ),
        .HTRANS_S4     (  ),
        .HWRITE_S4     (  ),
        .HWDATA_S4     (  ),
        .HREADY_S4     (  ),
        .HMASTLOCK_S4  (  ),
        .HBURST_S4     (  ),
        .HPROT_S4      (  ),
        .HSEL_S5       (  ),
        .HADDR_S5      (  ),
        .HSIZE_S5      (  ),
        .HTRANS_S5     (  ),
        .HWRITE_S5     (  ),
        .HWDATA_S5     (  ),
        .HREADY_S5     (  ),
        .HMASTLOCK_S5  (  ),
        .HBURST_S5     (  ),
        .HPROT_S5      (  ),
        .HSEL_S6       (  ),
        .HADDR_S6      (  ),
        .HSIZE_S6      (  ),
        .HTRANS_S6     (  ),
        .HWRITE_S6     (  ),
        .HWDATA_S6     (  ),
        .HREADY_S6     (  ),
        .HMASTLOCK_S6  (  ),
        .HBURST_S6     (  ),
        .HPROT_S6      (  ),
        .HSEL_S7       (  ),
        .HADDR_S7      (  ),
        .HSIZE_S7      (  ),
        .HTRANS_S7     (  ),
        .HWRITE_S7     (  ),
        .HWDATA_S7     (  ),
        .HREADY_S7     (  ),
        .HMASTLOCK_S7  (  ),
        .HBURST_S7     (  ),
        .HPROT_S7      (  ),
        .HSEL_S8       (  ),
        .HADDR_S8      (  ),
        .HSIZE_S8      (  ),
        .HTRANS_S8     (  ),
        .HWRITE_S8     (  ),
        .HWDATA_S8     (  ),
        .HREADY_S8     (  ),
        .HMASTLOCK_S8  (  ),
        .HBURST_S8     (  ),
        .HPROT_S8      (  ),
        .HSEL_S9       (  ),
        .HADDR_S9      (  ),
        .HSIZE_S9      (  ),
        .HTRANS_S9     (  ),
        .HWRITE_S9     (  ),
        .HWDATA_S9     (  ),
        .HREADY_S9     (  ),
        .HMASTLOCK_S9  (  ),
        .HBURST_S9     (  ),
        .HPROT_S9      (  ),
        .HSEL_S10      (  ),
        .HADDR_S10     (  ),
        .HSIZE_S10     (  ),
        .HTRANS_S10    (  ),
        .HWRITE_S10    (  ),
        .HWDATA_S10    (  ),
        .HREADY_S10    (  ),
        .HMASTLOCK_S10 (  ),
        .HBURST_S10    (  ),
        .HPROT_S10     (  ),
        .HSEL_S11      (  ),
        .HADDR_S11     (  ),
        .HSIZE_S11     (  ),
        .HTRANS_S11    (  ),
        .HWRITE_S11    (  ),
        .HWDATA_S11    (  ),
        .HREADY_S11    (  ),
        .HMASTLOCK_S11 (  ),
        .HBURST_S11    (  ),
        .HPROT_S11     (  ),
        .HSEL_S12      (  ),
        .HADDR_S12     (  ),
        .HSIZE_S12     (  ),
        .HTRANS_S12    (  ),
        .HWRITE_S12    (  ),
        .HWDATA_S12    (  ),
        .HREADY_S12    (  ),
        .HMASTLOCK_S12 (  ),
        .HBURST_S12    (  ),
        .HPROT_S12     (  ),
        .HSEL_S13      (  ),
        .HADDR_S13     (  ),
        .HSIZE_S13     (  ),
        .HTRANS_S13    (  ),
        .HWRITE_S13    (  ),
        .HWDATA_S13    (  ),
        .HREADY_S13    (  ),
        .HMASTLOCK_S13 (  ),
        .HBURST_S13    (  ),
        .HPROT_S13     (  ),
        .HSEL_S14      (  ),
        .HADDR_S14     (  ),
        .HSIZE_S14     (  ),
        .HTRANS_S14    (  ),
        .HWRITE_S14    (  ),
        .HWDATA_S14    (  ),
        .HREADY_S14    (  ),
        .HMASTLOCK_S14 (  ),
        .HBURST_S14    (  ),
        .HPROT_S14     (  ),
        .HSEL_S15      (  ),
        .HADDR_S15     (  ),
        .HSIZE_S15     (  ),
        .HTRANS_S15    (  ),
        .HWRITE_S15    (  ),
        .HWDATA_S15    (  ),
        .HREADY_S15    (  ),
        .HMASTLOCK_S15 (  ),
        .HBURST_S15    (  ),
        .HPROT_S15     (  ),
        .HSEL_S16      ( CoreAHBLite_0_AHBmslave16_HSELx ),
        .HADDR_S16     ( CoreAHBLite_0_AHBmslave16_HADDR ),
        .HSIZE_S16     ( CoreAHBLite_0_AHBmslave16_HSIZE ),
        .HTRANS_S16    ( CoreAHBLite_0_AHBmslave16_HTRANS ),
        .HWRITE_S16    ( CoreAHBLite_0_AHBmslave16_HWRITE ),
        .HWDATA_S16    ( CoreAHBLite_0_AHBmslave16_HWDATA ),
        .HREADY_S16    ( CoreAHBLite_0_AHBmslave16_HREADY ),
        .HMASTLOCK_S16 ( CoreAHBLite_0_AHBmslave16_HMASTLOCK ),
        .HBURST_S16    ( CoreAHBLite_0_AHBmslave16_HBURST ),
        .HPROT_S16     ( CoreAHBLite_0_AHBmslave16_HPROT ) 
        );

//--------MDDR_TA_COREAXI_0_COREAXI   -   Actel:DirectCore:COREAXI:3.1.100
MDDR_TA_COREAXI_0_COREAXI #( 
        .ADDR_HGS_CFG     ( 1 ),
        .AXI_DWIDTH       ( 64 ),
        .FAMILY           ( 19 ),
        .FEED_THROUGH     ( 1 ),
        .HGS_CFG          ( 1 ),
        .ID_WIDTH         ( 4 ),
        .INP_REG_BUF      ( 1 ),
        .M0_SLAVE0ENABLE  ( 1 ),
        .M0_SLAVE1ENABLE  ( 0 ),
        .M0_SLAVE2ENABLE  ( 0 ),
        .M0_SLAVE3ENABLE  ( 0 ),
        .M0_SLAVE4ENABLE  ( 0 ),
        .M0_SLAVE5ENABLE  ( 0 ),
        .M0_SLAVE6ENABLE  ( 0 ),
        .M0_SLAVE7ENABLE  ( 0 ),
        .M0_SLAVE8ENABLE  ( 0 ),
        .M0_SLAVE9ENABLE  ( 0 ),
        .M0_SLAVE10ENABLE ( 0 ),
        .M0_SLAVE11ENABLE ( 0 ),
        .M0_SLAVE12ENABLE ( 0 ),
        .M0_SLAVE13ENABLE ( 0 ),
        .M0_SLAVE14ENABLE ( 0 ),
        .M0_SLAVE15ENABLE ( 0 ),
        .M0_SLAVE16ENABLE ( 0 ),
        .M1_SLAVE0ENABLE  ( 0 ),
        .M1_SLAVE1ENABLE  ( 0 ),
        .M1_SLAVE2ENABLE  ( 0 ),
        .M1_SLAVE3ENABLE  ( 0 ),
        .M1_SLAVE4ENABLE  ( 0 ),
        .M1_SLAVE5ENABLE  ( 0 ),
        .M1_SLAVE6ENABLE  ( 0 ),
        .M1_SLAVE7ENABLE  ( 0 ),
        .M1_SLAVE8ENABLE  ( 0 ),
        .M1_SLAVE9ENABLE  ( 0 ),
        .M1_SLAVE10ENABLE ( 0 ),
        .M1_SLAVE11ENABLE ( 0 ),
        .M1_SLAVE12ENABLE ( 0 ),
        .M1_SLAVE13ENABLE ( 0 ),
        .M1_SLAVE14ENABLE ( 0 ),
        .M1_SLAVE15ENABLE ( 0 ),
        .M1_SLAVE16ENABLE ( 0 ),
        .M2_SLAVE0ENABLE  ( 0 ),
        .M2_SLAVE1ENABLE  ( 0 ),
        .M2_SLAVE2ENABLE  ( 0 ),
        .M2_SLAVE3ENABLE  ( 0 ),
        .M2_SLAVE4ENABLE  ( 0 ),
        .M2_SLAVE5ENABLE  ( 0 ),
        .M2_SLAVE6ENABLE  ( 0 ),
        .M2_SLAVE7ENABLE  ( 0 ),
        .M2_SLAVE8ENABLE  ( 0 ),
        .M2_SLAVE9ENABLE  ( 0 ),
        .M2_SLAVE10ENABLE ( 0 ),
        .M2_SLAVE11ENABLE ( 0 ),
        .M2_SLAVE12ENABLE ( 0 ),
        .M2_SLAVE13ENABLE ( 0 ),
        .M2_SLAVE14ENABLE ( 0 ),
        .M2_SLAVE15ENABLE ( 0 ),
        .M2_SLAVE16ENABLE ( 0 ),
        .M3_SLAVE0ENABLE  ( 0 ),
        .M3_SLAVE1ENABLE  ( 0 ),
        .M3_SLAVE2ENABLE  ( 0 ),
        .M3_SLAVE3ENABLE  ( 0 ),
        .M3_SLAVE4ENABLE  ( 0 ),
        .M3_SLAVE5ENABLE  ( 0 ),
        .M3_SLAVE6ENABLE  ( 0 ),
        .M3_SLAVE7ENABLE  ( 0 ),
        .M3_SLAVE8ENABLE  ( 0 ),
        .M3_SLAVE9ENABLE  ( 0 ),
        .M3_SLAVE10ENABLE ( 0 ),
        .M3_SLAVE11ENABLE ( 0 ),
        .M3_SLAVE12ENABLE ( 0 ),
        .M3_SLAVE13ENABLE ( 0 ),
        .M3_SLAVE14ENABLE ( 0 ),
        .M3_SLAVE15ENABLE ( 0 ),
        .M3_SLAVE16ENABLE ( 0 ),
        .MEMSPACE         ( 3 ),
        .NUM_MASTER_SLOT  ( 1 ),
        .OUT_REG_BUF      ( 1 ),
        .RD_ACCEPTANCE    ( 4 ),
        .SC_0             ( 0 ),
        .SC_1             ( 0 ),
        .SC_2             ( 0 ),
        .SC_3             ( 0 ),
        .SC_4             ( 0 ),
        .SC_5             ( 0 ),
        .SC_6             ( 0 ),
        .SC_7             ( 0 ),
        .SC_8             ( 0 ),
        .SC_9             ( 0 ),
        .SC_10            ( 0 ),
        .SC_11            ( 0 ),
        .SC_12            ( 0 ),
        .SC_13            ( 0 ),
        .SC_14            ( 0 ),
        .SC_15            ( 0 ) )
COREAXI_0(
        // Inputs
        .ACLK        ( MSS_DDR_FIC_SUBSYSTEM_CLK_net_0 ),
        .ARESETN     ( MSS_READY_net_0 ),
        .AWID_M0     ( AMBA_MASTER_0_AWID_M0 ),
        .AWADDR_M0   ( AMBA_MASTER_0_AWADDR_M0 ),
        .AWLEN_M0    ( AMBA_MASTER_0_AWLEN_M0 ),
        .AWSIZE_M0   ( AMBA_MASTER_0_AWSIZE_M0 ),
        .AWBURST_M0  ( AMBA_MASTER_0_AWBURST_M0 ),
        .AWLOCK_M0   ( AMBA_MASTER_0_AWLOCK_M0 ),
        .AWCACHE_M0  ( AMBA_MASTER_0_AWCACHE_M0 ),
        .AWPROT_M0   ( AMBA_MASTER_0_AWPROT_M0 ),
        .AWVALID_M0  ( AMBA_MASTER_0_AWVALID_M0 ),
        .WID_M0      ( AMBA_MASTER_0_WID_M0 ),
        .WDATA_M0    ( AMBA_MASTER_0_WDATA_M0 ),
        .WSTRB_M0    ( AMBA_MASTER_0_WSTRB_M0 ),
        .WLAST_M0    ( AMBA_MASTER_0_WLAST_M0 ),
        .WVALID_M0   ( AMBA_MASTER_0_WVALID_M0 ),
        .BREADY_M0   ( AMBA_MASTER_0_BREADY_M0 ),
        .ARID_M0     ( AMBA_MASTER_0_ARID_M0 ),
        .ARADDR_M0   ( AMBA_MASTER_0_ARADDR_M0 ),
        .ARLEN_M0    ( AMBA_MASTER_0_ARLEN_M0 ),
        .ARSIZE_M0   ( AMBA_MASTER_0_ARSIZE_M0 ),
        .ARBURST_M0  ( AMBA_MASTER_0_ARBURST_M0 ),
        .ARLOCK_M0   ( AMBA_MASTER_0_ARLOCK_M0 ),
        .ARCACHE_M0  ( AMBA_MASTER_0_ARCACHE_M0 ),
        .ARPROT_M0   ( AMBA_MASTER_0_ARPROT_M0 ),
        .ARVALID_M0  ( AMBA_MASTER_0_ARVALID_M0 ),
        .RREADY_M0   ( AMBA_MASTER_0_RREADY_M0 ),
        .AWID_M1     ( AWID_M1_const_net_0 ), // tied to 4'h0 from definition
        .AWADDR_M1   ( AWADDR_M1_const_net_0 ), // tied to 32'h00000000 from definition
        .AWLEN_M1    ( AWLEN_M1_const_net_0 ), // tied to 4'h0 from definition
        .AWSIZE_M1   ( AWSIZE_M1_const_net_0 ), // tied to 3'h0 from definition
        .AWBURST_M1  ( AWBURST_M1_const_net_0 ), // tied to 2'h0 from definition
        .AWLOCK_M1   ( AWLOCK_M1_const_net_0 ), // tied to 2'h0 from definition
        .AWCACHE_M1  ( AWCACHE_M1_const_net_0 ), // tied to 4'h0 from definition
        .AWPROT_M1   ( AWPROT_M1_const_net_0 ), // tied to 3'h0 from definition
        .AWVALID_M1  ( GND_net ), // tied to 1'b0 from definition
        .WID_M1      ( WID_M1_const_net_0 ), // tied to 4'h0 from definition
        .WDATA_M1    ( WDATA_M1_const_net_0 ), // tied to 64'h0000000000000000 from definition
        .WSTRB_M1    ( WSTRB_M1_const_net_0 ), // tied to 8'h00 from definition
        .WLAST_M1    ( GND_net ), // tied to 1'b0 from definition
        .WVALID_M1   ( GND_net ), // tied to 1'b0 from definition
        .BREADY_M1   ( GND_net ), // tied to 1'b0 from definition
        .ARID_M1     ( ARID_M1_const_net_0 ), // tied to 4'h0 from definition
        .ARADDR_M1   ( ARADDR_M1_const_net_0 ), // tied to 32'h00000000 from definition
        .ARLEN_M1    ( ARLEN_M1_const_net_0 ), // tied to 4'h0 from definition
        .ARSIZE_M1   ( ARSIZE_M1_const_net_0 ), // tied to 3'h0 from definition
        .ARBURST_M1  ( ARBURST_M1_const_net_0 ), // tied to 2'h0 from definition
        .ARLOCK_M1   ( ARLOCK_M1_const_net_0 ), // tied to 2'h0 from definition
        .ARCACHE_M1  ( ARCACHE_M1_const_net_0 ), // tied to 4'h0 from definition
        .ARPROT_M1   ( ARPROT_M1_const_net_0 ), // tied to 3'h0 from definition
        .ARVALID_M1  ( GND_net ), // tied to 1'b0 from definition
        .RREADY_M1   ( GND_net ), // tied to 1'b0 from definition
        .AWID_M2     ( AWID_M2_const_net_0 ), // tied to 4'h0 from definition
        .AWADDR_M2   ( AWADDR_M2_const_net_0 ), // tied to 32'h00000000 from definition
        .AWLEN_M2    ( AWLEN_M2_const_net_0 ), // tied to 4'h0 from definition
        .AWSIZE_M2   ( AWSIZE_M2_const_net_0 ), // tied to 3'h0 from definition
        .AWBURST_M2  ( AWBURST_M2_const_net_0 ), // tied to 2'h0 from definition
        .AWLOCK_M2   ( AWLOCK_M2_const_net_0 ), // tied to 2'h0 from definition
        .AWCACHE_M2  ( AWCACHE_M2_const_net_0 ), // tied to 4'h0 from definition
        .AWPROT_M2   ( AWPROT_M2_const_net_0 ), // tied to 3'h0 from definition
        .AWVALID_M2  ( GND_net ), // tied to 1'b0 from definition
        .WID_M2      ( WID_M2_const_net_0 ), // tied to 4'h0 from definition
        .WDATA_M2    ( WDATA_M2_const_net_0 ), // tied to 64'h0000000000000000 from definition
        .WSTRB_M2    ( WSTRB_M2_const_net_0 ), // tied to 8'h00 from definition
        .WLAST_M2    ( GND_net ), // tied to 1'b0 from definition
        .WVALID_M2   ( GND_net ), // tied to 1'b0 from definition
        .BREADY_M2   ( GND_net ), // tied to 1'b0 from definition
        .ARID_M2     ( ARID_M2_const_net_0 ), // tied to 4'h0 from definition
        .ARADDR_M2   ( ARADDR_M2_const_net_0 ), // tied to 32'h00000000 from definition
        .ARLEN_M2    ( ARLEN_M2_const_net_0 ), // tied to 4'h0 from definition
        .ARSIZE_M2   ( ARSIZE_M2_const_net_0 ), // tied to 3'h0 from definition
        .ARBURST_M2  ( ARBURST_M2_const_net_0 ), // tied to 2'h0 from definition
        .ARLOCK_M2   ( ARLOCK_M2_const_net_0 ), // tied to 2'h0 from definition
        .ARCACHE_M2  ( ARCACHE_M2_const_net_0 ), // tied to 4'h0 from definition
        .ARPROT_M2   ( ARPROT_M2_const_net_0 ), // tied to 3'h0 from definition
        .ARVALID_M2  ( GND_net ), // tied to 1'b0 from definition
        .RREADY_M2   ( GND_net ), // tied to 1'b0 from definition
        .AWID_M3     ( AWID_M3_const_net_0 ), // tied to 4'h0 from definition
        .AWADDR_M3   ( AWADDR_M3_const_net_0 ), // tied to 32'h00000000 from definition
        .AWLEN_M3    ( AWLEN_M3_const_net_0 ), // tied to 4'h0 from definition
        .AWSIZE_M3   ( AWSIZE_M3_const_net_0 ), // tied to 3'h0 from definition
        .AWBURST_M3  ( AWBURST_M3_const_net_0 ), // tied to 2'h0 from definition
        .AWLOCK_M3   ( AWLOCK_M3_const_net_0 ), // tied to 2'h0 from definition
        .AWCACHE_M3  ( AWCACHE_M3_const_net_0 ), // tied to 4'h0 from definition
        .AWPROT_M3   ( AWPROT_M3_const_net_0 ), // tied to 3'h0 from definition
        .AWVALID_M3  ( GND_net ), // tied to 1'b0 from definition
        .WID_M3      ( WID_M3_const_net_0 ), // tied to 4'h0 from definition
        .WDATA_M3    ( WDATA_M3_const_net_0 ), // tied to 64'h0000000000000000 from definition
        .WSTRB_M3    ( WSTRB_M3_const_net_0 ), // tied to 8'h00 from definition
        .WLAST_M3    ( GND_net ), // tied to 1'b0 from definition
        .WVALID_M3   ( GND_net ), // tied to 1'b0 from definition
        .BREADY_M3   ( GND_net ), // tied to 1'b0 from definition
        .ARID_M3     ( ARID_M3_const_net_0 ), // tied to 4'h0 from definition
        .ARADDR_M3   ( ARADDR_M3_const_net_0 ), // tied to 32'h00000000 from definition
        .ARLEN_M3    ( ARLEN_M3_const_net_0 ), // tied to 4'h0 from definition
        .ARSIZE_M3   ( ARSIZE_M3_const_net_0 ), // tied to 3'h0 from definition
        .ARBURST_M3  ( ARBURST_M3_const_net_0 ), // tied to 2'h0 from definition
        .ARLOCK_M3   ( ARLOCK_M3_const_net_0 ), // tied to 2'h0 from definition
        .ARCACHE_M3  ( ARCACHE_M3_const_net_0 ), // tied to 4'h0 from definition
        .ARPROT_M3   ( ARPROT_M3_const_net_0 ), // tied to 3'h0 from definition
        .ARVALID_M3  ( GND_net ), // tied to 1'b0 from definition
        .RREADY_M3   ( GND_net ), // tied to 1'b0 from definition
        .AWREADY_S0  ( COREAXI_0_AXImslave0_AWREADY ),
        .WREADY_S0   ( COREAXI_0_AXImslave0_WREADY ),
        .BID_S0      ( COREAXI_0_AXImslave0_BID_0 ),
        .BRESP_S0    ( COREAXI_0_AXImslave0_BRESP ),
        .BVALID_S0   ( COREAXI_0_AXImslave0_BVALID ),
        .ARREADY_S0  ( COREAXI_0_AXImslave0_ARREADY ),
        .RID_S0      ( COREAXI_0_AXImslave0_RID_0 ),
        .RDATA_S0    ( COREAXI_0_AXImslave0_RDATA ),
        .RRESP_S0    ( COREAXI_0_AXImslave0_RRESP ),
        .RLAST_S0    ( COREAXI_0_AXImslave0_RLAST ),
        .RVALID_S0   ( COREAXI_0_AXImslave0_RVALID ),
        .AWREADY_S1  ( GND_net ), // tied to 1'b0 from definition
        .WREADY_S1   ( GND_net ), // tied to 1'b0 from definition
        .BID_S1      ( BID_S1_const_net_0 ), // tied to 6'h00 from definition
        .BRESP_S1    ( BRESP_S1_const_net_0 ), // tied to 2'h0 from definition
        .BVALID_S1   ( GND_net ), // tied to 1'b0 from definition
        .ARREADY_S1  ( GND_net ), // tied to 1'b0 from definition
        .RID_S1      ( RID_S1_const_net_0 ), // tied to 6'h00 from definition
        .RDATA_S1    ( RDATA_S1_const_net_0 ), // tied to 64'h0000000000000000 from definition
        .RRESP_S1    ( RRESP_S1_const_net_0 ), // tied to 2'h0 from definition
        .RLAST_S1    ( GND_net ), // tied to 1'b0 from definition
        .RVALID_S1   ( GND_net ), // tied to 1'b0 from definition
        .AWREADY_S2  ( GND_net ), // tied to 1'b0 from definition
        .WREADY_S2   ( GND_net ), // tied to 1'b0 from definition
        .BID_S2      ( BID_S2_const_net_0 ), // tied to 6'h00 from definition
        .BRESP_S2    ( BRESP_S2_const_net_0 ), // tied to 2'h0 from definition
        .BVALID_S2   ( GND_net ), // tied to 1'b0 from definition
        .ARREADY_S2  ( GND_net ), // tied to 1'b0 from definition
        .RID_S2      ( RID_S2_const_net_0 ), // tied to 6'h00 from definition
        .RDATA_S2    ( RDATA_S2_const_net_0 ), // tied to 64'h0000000000000000 from definition
        .RRESP_S2    ( RRESP_S2_const_net_0 ), // tied to 2'h0 from definition
        .RLAST_S2    ( GND_net ), // tied to 1'b0 from definition
        .RVALID_S2   ( GND_net ), // tied to 1'b0 from definition
        .AWREADY_S3  ( GND_net ), // tied to 1'b0 from definition
        .WREADY_S3   ( GND_net ), // tied to 1'b0 from definition
        .BID_S3      ( BID_S3_const_net_0 ), // tied to 6'h00 from definition
        .BRESP_S3    ( BRESP_S3_const_net_0 ), // tied to 2'h0 from definition
        .BVALID_S3   ( GND_net ), // tied to 1'b0 from definition
        .ARREADY_S3  ( GND_net ), // tied to 1'b0 from definition
        .RID_S3      ( RID_S3_const_net_0 ), // tied to 6'h00 from definition
        .RDATA_S3    ( RDATA_S3_const_net_0 ), // tied to 64'h0000000000000000 from definition
        .RRESP_S3    ( RRESP_S3_const_net_0 ), // tied to 2'h0 from definition
        .RLAST_S3    ( GND_net ), // tied to 1'b0 from definition
        .RVALID_S3   ( GND_net ), // tied to 1'b0 from definition
        .AWREADY_S4  ( GND_net ), // tied to 1'b0 from definition
        .WREADY_S4   ( GND_net ), // tied to 1'b0 from definition
        .BID_S4      ( BID_S4_const_net_0 ), // tied to 6'h00 from definition
        .BRESP_S4    ( BRESP_S4_const_net_0 ), // tied to 2'h0 from definition
        .BVALID_S4   ( GND_net ), // tied to 1'b0 from definition
        .ARREADY_S4  ( GND_net ), // tied to 1'b0 from definition
        .RID_S4      ( RID_S4_const_net_0 ), // tied to 6'h00 from definition
        .RDATA_S4    ( RDATA_S4_const_net_0 ), // tied to 64'h0000000000000000 from definition
        .RRESP_S4    ( RRESP_S4_const_net_0 ), // tied to 2'h0 from definition
        .RLAST_S4    ( GND_net ), // tied to 1'b0 from definition
        .RVALID_S4   ( GND_net ), // tied to 1'b0 from definition
        .AWREADY_S5  ( GND_net ), // tied to 1'b0 from definition
        .WREADY_S5   ( GND_net ), // tied to 1'b0 from definition
        .BID_S5      ( BID_S5_const_net_0 ), // tied to 6'h00 from definition
        .BRESP_S5    ( BRESP_S5_const_net_0 ), // tied to 2'h0 from definition
        .BVALID_S5   ( GND_net ), // tied to 1'b0 from definition
        .ARREADY_S5  ( GND_net ), // tied to 1'b0 from definition
        .RID_S5      ( RID_S5_const_net_0 ), // tied to 6'h00 from definition
        .RDATA_S5    ( RDATA_S5_const_net_0 ), // tied to 64'h0000000000000000 from definition
        .RRESP_S5    ( RRESP_S5_const_net_0 ), // tied to 2'h0 from definition
        .RLAST_S5    ( GND_net ), // tied to 1'b0 from definition
        .RVALID_S5   ( GND_net ), // tied to 1'b0 from definition
        .AWREADY_S6  ( GND_net ), // tied to 1'b0 from definition
        .WREADY_S6   ( GND_net ), // tied to 1'b0 from definition
        .BID_S6      ( BID_S6_const_net_0 ), // tied to 6'h00 from definition
        .BRESP_S6    ( BRESP_S6_const_net_0 ), // tied to 2'h0 from definition
        .BVALID_S6   ( GND_net ), // tied to 1'b0 from definition
        .ARREADY_S6  ( GND_net ), // tied to 1'b0 from definition
        .RID_S6      ( RID_S6_const_net_0 ), // tied to 6'h00 from definition
        .RDATA_S6    ( RDATA_S6_const_net_0 ), // tied to 64'h0000000000000000 from definition
        .RRESP_S6    ( RRESP_S6_const_net_0 ), // tied to 2'h0 from definition
        .RLAST_S6    ( GND_net ), // tied to 1'b0 from definition
        .RVALID_S6   ( GND_net ), // tied to 1'b0 from definition
        .AWREADY_S7  ( GND_net ), // tied to 1'b0 from definition
        .WREADY_S7   ( GND_net ), // tied to 1'b0 from definition
        .BID_S7      ( BID_S7_const_net_0 ), // tied to 6'h00 from definition
        .BRESP_S7    ( BRESP_S7_const_net_0 ), // tied to 2'h0 from definition
        .BVALID_S7   ( GND_net ), // tied to 1'b0 from definition
        .ARREADY_S7  ( GND_net ), // tied to 1'b0 from definition
        .RID_S7      ( RID_S7_const_net_0 ), // tied to 6'h00 from definition
        .RDATA_S7    ( RDATA_S7_const_net_0 ), // tied to 64'h0000000000000000 from definition
        .RRESP_S7    ( RRESP_S7_const_net_0 ), // tied to 2'h0 from definition
        .RLAST_S7    ( GND_net ), // tied to 1'b0 from definition
        .RVALID_S7   ( GND_net ), // tied to 1'b0 from definition
        .AWREADY_S8  ( GND_net ), // tied to 1'b0 from definition
        .WREADY_S8   ( GND_net ), // tied to 1'b0 from definition
        .BID_S8      ( BID_S8_const_net_0 ), // tied to 6'h00 from definition
        .BRESP_S8    ( BRESP_S8_const_net_0 ), // tied to 2'h0 from definition
        .BVALID_S8   ( GND_net ), // tied to 1'b0 from definition
        .ARREADY_S8  ( GND_net ), // tied to 1'b0 from definition
        .RID_S8      ( RID_S8_const_net_0 ), // tied to 6'h00 from definition
        .RDATA_S8    ( RDATA_S8_const_net_0 ), // tied to 64'h0000000000000000 from definition
        .RRESP_S8    ( RRESP_S8_const_net_0 ), // tied to 2'h0 from definition
        .RLAST_S8    ( GND_net ), // tied to 1'b0 from definition
        .RVALID_S8   ( GND_net ), // tied to 1'b0 from definition
        .AWREADY_S9  ( GND_net ), // tied to 1'b0 from definition
        .WREADY_S9   ( GND_net ), // tied to 1'b0 from definition
        .BID_S9      ( BID_S9_const_net_0 ), // tied to 6'h00 from definition
        .BRESP_S9    ( BRESP_S9_const_net_0 ), // tied to 2'h0 from definition
        .BVALID_S9   ( GND_net ), // tied to 1'b0 from definition
        .ARREADY_S9  ( GND_net ), // tied to 1'b0 from definition
        .RID_S9      ( RID_S9_const_net_0 ), // tied to 6'h00 from definition
        .RDATA_S9    ( RDATA_S9_const_net_0 ), // tied to 64'h0000000000000000 from definition
        .RRESP_S9    ( RRESP_S9_const_net_0 ), // tied to 2'h0 from definition
        .RLAST_S9    ( GND_net ), // tied to 1'b0 from definition
        .RVALID_S9   ( GND_net ), // tied to 1'b0 from definition
        .AWREADY_S10 ( GND_net ), // tied to 1'b0 from definition
        .WREADY_S10  ( GND_net ), // tied to 1'b0 from definition
        .BID_S10     ( BID_S10_const_net_0 ), // tied to 6'h00 from definition
        .BRESP_S10   ( BRESP_S10_const_net_0 ), // tied to 2'h0 from definition
        .BVALID_S10  ( GND_net ), // tied to 1'b0 from definition
        .ARREADY_S10 ( GND_net ), // tied to 1'b0 from definition
        .RID_S10     ( RID_S10_const_net_0 ), // tied to 6'h00 from definition
        .RDATA_S10   ( RDATA_S10_const_net_0 ), // tied to 64'h0000000000000000 from definition
        .RRESP_S10   ( RRESP_S10_const_net_0 ), // tied to 2'h0 from definition
        .RLAST_S10   ( GND_net ), // tied to 1'b0 from definition
        .RVALID_S10  ( GND_net ), // tied to 1'b0 from definition
        .AWREADY_S11 ( GND_net ), // tied to 1'b0 from definition
        .WREADY_S11  ( GND_net ), // tied to 1'b0 from definition
        .BID_S11     ( BID_S11_const_net_0 ), // tied to 6'h00 from definition
        .BRESP_S11   ( BRESP_S11_const_net_0 ), // tied to 2'h0 from definition
        .BVALID_S11  ( GND_net ), // tied to 1'b0 from definition
        .ARREADY_S11 ( GND_net ), // tied to 1'b0 from definition
        .RID_S11     ( RID_S11_const_net_0 ), // tied to 6'h00 from definition
        .RDATA_S11   ( RDATA_S11_const_net_0 ), // tied to 64'h0000000000000000 from definition
        .RRESP_S11   ( RRESP_S11_const_net_0 ), // tied to 2'h0 from definition
        .RLAST_S11   ( GND_net ), // tied to 1'b0 from definition
        .RVALID_S11  ( GND_net ), // tied to 1'b0 from definition
        .AWREADY_S12 ( GND_net ), // tied to 1'b0 from definition
        .WREADY_S12  ( GND_net ), // tied to 1'b0 from definition
        .BID_S12     ( BID_S12_const_net_0 ), // tied to 6'h00 from definition
        .BRESP_S12   ( BRESP_S12_const_net_0 ), // tied to 2'h0 from definition
        .BVALID_S12  ( GND_net ), // tied to 1'b0 from definition
        .ARREADY_S12 ( GND_net ), // tied to 1'b0 from definition
        .RID_S12     ( RID_S12_const_net_0 ), // tied to 6'h00 from definition
        .RDATA_S12   ( RDATA_S12_const_net_0 ), // tied to 64'h0000000000000000 from definition
        .RRESP_S12   ( RRESP_S12_const_net_0 ), // tied to 2'h0 from definition
        .RLAST_S12   ( GND_net ), // tied to 1'b0 from definition
        .RVALID_S12  ( GND_net ), // tied to 1'b0 from definition
        .AWREADY_S13 ( GND_net ), // tied to 1'b0 from definition
        .WREADY_S13  ( GND_net ), // tied to 1'b0 from definition
        .BID_S13     ( BID_S13_const_net_0 ), // tied to 6'h00 from definition
        .BRESP_S13   ( BRESP_S13_const_net_0 ), // tied to 2'h0 from definition
        .BVALID_S13  ( GND_net ), // tied to 1'b0 from definition
        .ARREADY_S13 ( GND_net ), // tied to 1'b0 from definition
        .RID_S13     ( RID_S13_const_net_0 ), // tied to 6'h00 from definition
        .RDATA_S13   ( RDATA_S13_const_net_0 ), // tied to 64'h0000000000000000 from definition
        .RRESP_S13   ( RRESP_S13_const_net_0 ), // tied to 2'h0 from definition
        .RLAST_S13   ( GND_net ), // tied to 1'b0 from definition
        .RVALID_S13  ( GND_net ), // tied to 1'b0 from definition
        .AWREADY_S14 ( GND_net ), // tied to 1'b0 from definition
        .WREADY_S14  ( GND_net ), // tied to 1'b0 from definition
        .BID_S14     ( BID_S14_const_net_0 ), // tied to 6'h00 from definition
        .BRESP_S14   ( BRESP_S14_const_net_0 ), // tied to 2'h0 from definition
        .BVALID_S14  ( GND_net ), // tied to 1'b0 from definition
        .ARREADY_S14 ( GND_net ), // tied to 1'b0 from definition
        .RID_S14     ( RID_S14_const_net_0 ), // tied to 6'h00 from definition
        .RDATA_S14   ( RDATA_S14_const_net_0 ), // tied to 64'h0000000000000000 from definition
        .RRESP_S14   ( RRESP_S14_const_net_0 ), // tied to 2'h0 from definition
        .RLAST_S14   ( GND_net ), // tied to 1'b0 from definition
        .RVALID_S14  ( GND_net ), // tied to 1'b0 from definition
        .AWREADY_S15 ( GND_net ), // tied to 1'b0 from definition
        .WREADY_S15  ( GND_net ), // tied to 1'b0 from definition
        .BID_S15     ( BID_S15_const_net_0 ), // tied to 6'h00 from definition
        .BRESP_S15   ( BRESP_S15_const_net_0 ), // tied to 2'h0 from definition
        .BVALID_S15  ( GND_net ), // tied to 1'b0 from definition
        .ARREADY_S15 ( GND_net ), // tied to 1'b0 from definition
        .RID_S15     ( RID_S15_const_net_0 ), // tied to 6'h00 from definition
        .RDATA_S15   ( RDATA_S15_const_net_0 ), // tied to 64'h0000000000000000 from definition
        .RRESP_S15   ( RRESP_S15_const_net_0 ), // tied to 2'h0 from definition
        .RLAST_S15   ( GND_net ), // tied to 1'b0 from definition
        .RVALID_S15  ( GND_net ), // tied to 1'b0 from definition
        .AWREADY_S16 ( GND_net ), // tied to 1'b0 from definition
        .WREADY_S16  ( GND_net ), // tied to 1'b0 from definition
        .BID_S16     ( BID_S16_const_net_0 ), // tied to 6'h00 from definition
        .BRESP_S16   ( BRESP_S16_const_net_0 ), // tied to 2'h0 from definition
        .BVALID_S16  ( GND_net ), // tied to 1'b0 from definition
        .ARREADY_S16 ( GND_net ), // tied to 1'b0 from definition
        .RID_S16     ( RID_S16_const_net_0 ), // tied to 6'h00 from definition
        .RDATA_S16   ( RDATA_S16_const_net_0 ), // tied to 64'h0000000000000000 from definition
        .RRESP_S16   ( RRESP_S16_const_net_0 ), // tied to 2'h0 from definition
        .RLAST_S16   ( GND_net ), // tied to 1'b0 from definition
        .RVALID_S16  ( GND_net ), // tied to 1'b0 from definition
        // Outputs
        .AWREADY_M0  ( AMBA_MASTER_0_AWREADY ),
        .WREADY_M0   ( AMBA_MASTER_0_WREADY ),
        .BID_M0      ( AMBA_MASTER_0_BID ),
        .BRESP_M0    ( AMBA_MASTER_0_BRESP ),
        .BVALID_M0   ( AMBA_MASTER_0_BVALID ),
        .ARREADY_M0  ( AMBA_MASTER_0_ARREADY ),
        .RID_M0      ( AMBA_MASTER_0_RID ),
        .RDATA_M0    ( AMBA_MASTER_0_RDATA ),
        .RRESP_M0    ( AMBA_MASTER_0_RRESP ),
        .RLAST_M0    ( AMBA_MASTER_0_RLAST ),
        .RVALID_M0   ( AMBA_MASTER_0_RVALID ),
        .AWREADY_M1  (  ),
        .WREADY_M1   (  ),
        .BID_M1      (  ),
        .BRESP_M1    (  ),
        .BVALID_M1   (  ),
        .ARREADY_M1  (  ),
        .RID_M1      (  ),
        .RDATA_M1    (  ),
        .RRESP_M1    (  ),
        .RLAST_M1    (  ),
        .RVALID_M1   (  ),
        .AWREADY_M2  (  ),
        .WREADY_M2   (  ),
        .BID_M2      (  ),
        .BRESP_M2    (  ),
        .BVALID_M2   (  ),
        .ARREADY_M2  (  ),
        .RID_M2      (  ),
        .RDATA_M2    (  ),
        .RRESP_M2    (  ),
        .RLAST_M2    (  ),
        .RVALID_M2   (  ),
        .AWREADY_M3  (  ),
        .WREADY_M3   (  ),
        .BID_M3      (  ),
        .BRESP_M3    (  ),
        .BVALID_M3   (  ),
        .ARREADY_M3  (  ),
        .RID_M3      (  ),
        .RDATA_M3    (  ),
        .RRESP_M3    (  ),
        .RLAST_M3    (  ),
        .RVALID_M3   (  ),
        .AWID_S0     ( COREAXI_0_AXImslave0_AWID ),
        .AWADDR_S0   ( COREAXI_0_AXImslave0_AWADDR ),
        .AWLEN_S0    ( COREAXI_0_AXImslave0_AWLEN ),
        .AWSIZE_S0   ( COREAXI_0_AXImslave0_AWSIZE ),
        .AWBURST_S0  ( COREAXI_0_AXImslave0_AWBURST ),
        .AWLOCK_S0   ( COREAXI_0_AXImslave0_AWLOCK ),
        .AWCACHE_S0  ( COREAXI_0_AXImslave0_AWCACHE ),
        .AWPROT_S0   ( COREAXI_0_AXImslave0_AWPROT ),
        .AWVALID_S0  ( COREAXI_0_AXImslave0_AWVALID ),
        .WID_S0      ( COREAXI_0_AXImslave0_WID ),
        .WDATA_S0    ( COREAXI_0_AXImslave0_WDATA ),
        .WSTRB_S0    ( COREAXI_0_AXImslave0_WSTRB ),
        .WLAST_S0    ( COREAXI_0_AXImslave0_WLAST ),
        .WVALID_S0   ( COREAXI_0_AXImslave0_WVALID ),
        .BREADY_S0   ( COREAXI_0_AXImslave0_BREADY ),
        .ARID_S0     ( COREAXI_0_AXImslave0_ARID ),
        .ARADDR_S0   ( COREAXI_0_AXImslave0_ARADDR ),
        .ARLEN_S0    ( COREAXI_0_AXImslave0_ARLEN ),
        .ARSIZE_S0   ( COREAXI_0_AXImslave0_ARSIZE ),
        .ARBURST_S0  ( COREAXI_0_AXImslave0_ARBURST ),
        .ARLOCK_S0   ( COREAXI_0_AXImslave0_ARLOCK ),
        .ARCACHE_S0  ( COREAXI_0_AXImslave0_ARCACHE ),
        .ARPROT_S0   ( COREAXI_0_AXImslave0_ARPROT ),
        .ARVALID_S0  ( COREAXI_0_AXImslave0_ARVALID ),
        .RREADY_S0   ( COREAXI_0_AXImslave0_RREADY ),
        .AWID_S1     (  ),
        .AWADDR_S1   (  ),
        .AWLEN_S1    (  ),
        .AWSIZE_S1   (  ),
        .AWBURST_S1  (  ),
        .AWLOCK_S1   (  ),
        .AWCACHE_S1  (  ),
        .AWPROT_S1   (  ),
        .AWVALID_S1  (  ),
        .WID_S1      (  ),
        .WDATA_S1    (  ),
        .WSTRB_S1    (  ),
        .WLAST_S1    (  ),
        .WVALID_S1   (  ),
        .BREADY_S1   (  ),
        .ARID_S1     (  ),
        .ARADDR_S1   (  ),
        .ARLEN_S1    (  ),
        .ARSIZE_S1   (  ),
        .ARBURST_S1  (  ),
        .ARLOCK_S1   (  ),
        .ARCACHE_S1  (  ),
        .ARPROT_S1   (  ),
        .ARVALID_S1  (  ),
        .RREADY_S1   (  ),
        .AWID_S2     (  ),
        .AWADDR_S2   (  ),
        .AWLEN_S2    (  ),
        .AWSIZE_S2   (  ),
        .AWBURST_S2  (  ),
        .AWLOCK_S2   (  ),
        .AWCACHE_S2  (  ),
        .AWPROT_S2   (  ),
        .AWVALID_S2  (  ),
        .WID_S2      (  ),
        .WDATA_S2    (  ),
        .WSTRB_S2    (  ),
        .WLAST_S2    (  ),
        .WVALID_S2   (  ),
        .BREADY_S2   (  ),
        .ARID_S2     (  ),
        .ARADDR_S2   (  ),
        .ARLEN_S2    (  ),
        .ARSIZE_S2   (  ),
        .ARBURST_S2  (  ),
        .ARLOCK_S2   (  ),
        .ARCACHE_S2  (  ),
        .ARPROT_S2   (  ),
        .ARVALID_S2  (  ),
        .RREADY_S2   (  ),
        .AWID_S3     (  ),
        .AWADDR_S3   (  ),
        .AWLEN_S3    (  ),
        .AWSIZE_S3   (  ),
        .AWBURST_S3  (  ),
        .AWLOCK_S3   (  ),
        .AWCACHE_S3  (  ),
        .AWPROT_S3   (  ),
        .AWVALID_S3  (  ),
        .WID_S3      (  ),
        .WDATA_S3    (  ),
        .WSTRB_S3    (  ),
        .WLAST_S3    (  ),
        .WVALID_S3   (  ),
        .BREADY_S3   (  ),
        .ARID_S3     (  ),
        .ARADDR_S3   (  ),
        .ARLEN_S3    (  ),
        .ARSIZE_S3   (  ),
        .ARBURST_S3  (  ),
        .ARLOCK_S3   (  ),
        .ARCACHE_S3  (  ),
        .ARPROT_S3   (  ),
        .ARVALID_S3  (  ),
        .RREADY_S3   (  ),
        .AWID_S4     (  ),
        .AWADDR_S4   (  ),
        .AWLEN_S4    (  ),
        .AWSIZE_S4   (  ),
        .AWBURST_S4  (  ),
        .AWLOCK_S4   (  ),
        .AWCACHE_S4  (  ),
        .AWPROT_S4   (  ),
        .AWVALID_S4  (  ),
        .WID_S4      (  ),
        .WDATA_S4    (  ),
        .WSTRB_S4    (  ),
        .WLAST_S4    (  ),
        .WVALID_S4   (  ),
        .BREADY_S4   (  ),
        .ARID_S4     (  ),
        .ARADDR_S4   (  ),
        .ARLEN_S4    (  ),
        .ARSIZE_S4   (  ),
        .ARBURST_S4  (  ),
        .ARLOCK_S4   (  ),
        .ARCACHE_S4  (  ),
        .ARPROT_S4   (  ),
        .ARVALID_S4  (  ),
        .RREADY_S4   (  ),
        .AWID_S5     (  ),
        .AWADDR_S5   (  ),
        .AWLEN_S5    (  ),
        .AWSIZE_S5   (  ),
        .AWBURST_S5  (  ),
        .AWLOCK_S5   (  ),
        .AWCACHE_S5  (  ),
        .AWPROT_S5   (  ),
        .AWVALID_S5  (  ),
        .WID_S5      (  ),
        .WDATA_S5    (  ),
        .WSTRB_S5    (  ),
        .WLAST_S5    (  ),
        .WVALID_S5   (  ),
        .BREADY_S5   (  ),
        .ARID_S5     (  ),
        .ARADDR_S5   (  ),
        .ARLEN_S5    (  ),
        .ARSIZE_S5   (  ),
        .ARBURST_S5  (  ),
        .ARLOCK_S5   (  ),
        .ARCACHE_S5  (  ),
        .ARPROT_S5   (  ),
        .ARVALID_S5  (  ),
        .RREADY_S5   (  ),
        .AWID_S6     (  ),
        .AWADDR_S6   (  ),
        .AWLEN_S6    (  ),
        .AWSIZE_S6   (  ),
        .AWBURST_S6  (  ),
        .AWLOCK_S6   (  ),
        .AWCACHE_S6  (  ),
        .AWPROT_S6   (  ),
        .AWVALID_S6  (  ),
        .WID_S6      (  ),
        .WDATA_S6    (  ),
        .WSTRB_S6    (  ),
        .WLAST_S6    (  ),
        .WVALID_S6   (  ),
        .BREADY_S6   (  ),
        .ARID_S6     (  ),
        .ARADDR_S6   (  ),
        .ARLEN_S6    (  ),
        .ARSIZE_S6   (  ),
        .ARBURST_S6  (  ),
        .ARLOCK_S6   (  ),
        .ARCACHE_S6  (  ),
        .ARPROT_S6   (  ),
        .ARVALID_S6  (  ),
        .RREADY_S6   (  ),
        .AWID_S7     (  ),
        .AWADDR_S7   (  ),
        .AWLEN_S7    (  ),
        .AWSIZE_S7   (  ),
        .AWBURST_S7  (  ),
        .AWLOCK_S7   (  ),
        .AWCACHE_S7  (  ),
        .AWPROT_S7   (  ),
        .AWVALID_S7  (  ),
        .WID_S7      (  ),
        .WDATA_S7    (  ),
        .WSTRB_S7    (  ),
        .WLAST_S7    (  ),
        .WVALID_S7   (  ),
        .BREADY_S7   (  ),
        .ARID_S7     (  ),
        .ARADDR_S7   (  ),
        .ARLEN_S7    (  ),
        .ARSIZE_S7   (  ),
        .ARBURST_S7  (  ),
        .ARLOCK_S7   (  ),
        .ARCACHE_S7  (  ),
        .ARPROT_S7   (  ),
        .ARVALID_S7  (  ),
        .RREADY_S7   (  ),
        .AWID_S8     (  ),
        .AWADDR_S8   (  ),
        .AWLEN_S8    (  ),
        .AWSIZE_S8   (  ),
        .AWBURST_S8  (  ),
        .AWLOCK_S8   (  ),
        .AWCACHE_S8  (  ),
        .AWPROT_S8   (  ),
        .AWVALID_S8  (  ),
        .WID_S8      (  ),
        .WDATA_S8    (  ),
        .WSTRB_S8    (  ),
        .WLAST_S8    (  ),
        .WVALID_S8   (  ),
        .BREADY_S8   (  ),
        .ARID_S8     (  ),
        .ARADDR_S8   (  ),
        .ARLEN_S8    (  ),
        .ARSIZE_S8   (  ),
        .ARBURST_S8  (  ),
        .ARLOCK_S8   (  ),
        .ARCACHE_S8  (  ),
        .ARPROT_S8   (  ),
        .ARVALID_S8  (  ),
        .RREADY_S8   (  ),
        .AWID_S9     (  ),
        .AWADDR_S9   (  ),
        .AWLEN_S9    (  ),
        .AWSIZE_S9   (  ),
        .AWBURST_S9  (  ),
        .AWLOCK_S9   (  ),
        .AWCACHE_S9  (  ),
        .AWPROT_S9   (  ),
        .AWVALID_S9  (  ),
        .WID_S9      (  ),
        .WDATA_S9    (  ),
        .WSTRB_S9    (  ),
        .WLAST_S9    (  ),
        .WVALID_S9   (  ),
        .BREADY_S9   (  ),
        .ARID_S9     (  ),
        .ARADDR_S9   (  ),
        .ARLEN_S9    (  ),
        .ARSIZE_S9   (  ),
        .ARBURST_S9  (  ),
        .ARLOCK_S9   (  ),
        .ARCACHE_S9  (  ),
        .ARPROT_S9   (  ),
        .ARVALID_S9  (  ),
        .RREADY_S9   (  ),
        .AWID_S10    (  ),
        .AWADDR_S10  (  ),
        .AWLEN_S10   (  ),
        .AWSIZE_S10  (  ),
        .AWBURST_S10 (  ),
        .AWLOCK_S10  (  ),
        .AWCACHE_S10 (  ),
        .AWPROT_S10  (  ),
        .AWVALID_S10 (  ),
        .WID_S10     (  ),
        .WDATA_S10   (  ),
        .WSTRB_S10   (  ),
        .WLAST_S10   (  ),
        .WVALID_S10  (  ),
        .BREADY_S10  (  ),
        .ARID_S10    (  ),
        .ARADDR_S10  (  ),
        .ARLEN_S10   (  ),
        .ARSIZE_S10  (  ),
        .ARBURST_S10 (  ),
        .ARLOCK_S10  (  ),
        .ARCACHE_S10 (  ),
        .ARPROT_S10  (  ),
        .ARVALID_S10 (  ),
        .RREADY_S10  (  ),
        .AWID_S11    (  ),
        .AWADDR_S11  (  ),
        .AWLEN_S11   (  ),
        .AWSIZE_S11  (  ),
        .AWBURST_S11 (  ),
        .AWLOCK_S11  (  ),
        .AWCACHE_S11 (  ),
        .AWPROT_S11  (  ),
        .AWVALID_S11 (  ),
        .WID_S11     (  ),
        .WDATA_S11   (  ),
        .WSTRB_S11   (  ),
        .WLAST_S11   (  ),
        .WVALID_S11  (  ),
        .BREADY_S11  (  ),
        .ARID_S11    (  ),
        .ARADDR_S11  (  ),
        .ARLEN_S11   (  ),
        .ARSIZE_S11  (  ),
        .ARBURST_S11 (  ),
        .ARLOCK_S11  (  ),
        .ARCACHE_S11 (  ),
        .ARPROT_S11  (  ),
        .ARVALID_S11 (  ),
        .RREADY_S11  (  ),
        .AWID_S12    (  ),
        .AWADDR_S12  (  ),
        .AWLEN_S12   (  ),
        .AWSIZE_S12  (  ),
        .AWBURST_S12 (  ),
        .AWLOCK_S12  (  ),
        .AWCACHE_S12 (  ),
        .AWPROT_S12  (  ),
        .AWVALID_S12 (  ),
        .WID_S12     (  ),
        .WDATA_S12   (  ),
        .WSTRB_S12   (  ),
        .WLAST_S12   (  ),
        .WVALID_S12  (  ),
        .BREADY_S12  (  ),
        .ARID_S12    (  ),
        .ARADDR_S12  (  ),
        .ARLEN_S12   (  ),
        .ARSIZE_S12  (  ),
        .ARBURST_S12 (  ),
        .ARLOCK_S12  (  ),
        .ARCACHE_S12 (  ),
        .ARPROT_S12  (  ),
        .ARVALID_S12 (  ),
        .RREADY_S12  (  ),
        .AWID_S13    (  ),
        .AWADDR_S13  (  ),
        .AWLEN_S13   (  ),
        .AWSIZE_S13  (  ),
        .AWBURST_S13 (  ),
        .AWLOCK_S13  (  ),
        .AWCACHE_S13 (  ),
        .AWPROT_S13  (  ),
        .AWVALID_S13 (  ),
        .WID_S13     (  ),
        .WDATA_S13   (  ),
        .WSTRB_S13   (  ),
        .WLAST_S13   (  ),
        .WVALID_S13  (  ),
        .BREADY_S13  (  ),
        .ARID_S13    (  ),
        .ARADDR_S13  (  ),
        .ARLEN_S13   (  ),
        .ARSIZE_S13  (  ),
        .ARBURST_S13 (  ),
        .ARLOCK_S13  (  ),
        .ARCACHE_S13 (  ),
        .ARPROT_S13  (  ),
        .ARVALID_S13 (  ),
        .RREADY_S13  (  ),
        .AWID_S14    (  ),
        .AWADDR_S14  (  ),
        .AWLEN_S14   (  ),
        .AWSIZE_S14  (  ),
        .AWBURST_S14 (  ),
        .AWLOCK_S14  (  ),
        .AWCACHE_S14 (  ),
        .AWPROT_S14  (  ),
        .AWVALID_S14 (  ),
        .WID_S14     (  ),
        .WDATA_S14   (  ),
        .WSTRB_S14   (  ),
        .WLAST_S14   (  ),
        .WVALID_S14  (  ),
        .BREADY_S14  (  ),
        .ARID_S14    (  ),
        .ARADDR_S14  (  ),
        .ARLEN_S14   (  ),
        .ARSIZE_S14  (  ),
        .ARBURST_S14 (  ),
        .ARLOCK_S14  (  ),
        .ARCACHE_S14 (  ),
        .ARPROT_S14  (  ),
        .ARVALID_S14 (  ),
        .RREADY_S14  (  ),
        .AWID_S15    (  ),
        .AWADDR_S15  (  ),
        .AWLEN_S15   (  ),
        .AWSIZE_S15  (  ),
        .AWBURST_S15 (  ),
        .AWLOCK_S15  (  ),
        .AWCACHE_S15 (  ),
        .AWPROT_S15  (  ),
        .AWVALID_S15 (  ),
        .WID_S15     (  ),
        .WDATA_S15   (  ),
        .WSTRB_S15   (  ),
        .WLAST_S15   (  ),
        .WVALID_S15  (  ),
        .BREADY_S15  (  ),
        .ARID_S15    (  ),
        .ARADDR_S15  (  ),
        .ARLEN_S15   (  ),
        .ARSIZE_S15  (  ),
        .ARBURST_S15 (  ),
        .ARLOCK_S15  (  ),
        .ARCACHE_S15 (  ),
        .ARPROT_S15  (  ),
        .ARVALID_S15 (  ),
        .RREADY_S15  (  ),
        .AWID_S16    (  ),
        .AWADDR_S16  (  ),
        .AWLEN_S16   (  ),
        .AWSIZE_S16  (  ),
        .AWBURST_S16 (  ),
        .AWLOCK_S16  (  ),
        .AWCACHE_S16 (  ),
        .AWPROT_S16  (  ),
        .AWVALID_S16 (  ),
        .WID_S16     (  ),
        .WDATA_S16   (  ),
        .WSTRB_S16   (  ),
        .WLAST_S16   (  ),
        .WVALID_S16  (  ),
        .BREADY_S16  (  ),
        .ARID_S16    (  ),
        .ARADDR_S16  (  ),
        .ARLEN_S16   (  ),
        .ARSIZE_S16  (  ),
        .ARBURST_S16 (  ),
        .ARLOCK_S16  (  ),
        .ARCACHE_S16 (  ),
        .ARPROT_S16  (  ),
        .ARVALID_S16 (  ),
        .RREADY_S16  (  ) 
        );

//--------CoreConfigP   -   Actel:DirectCore:CoreConfigP:7.0.105
CoreConfigP #( 
        .DEVICE_090         ( 0 ),
        .ENABLE_SOFT_RESETS ( 1 ),
        .FDDR_IN_USE        ( 0 ),
        .MDDR_IN_USE        ( 1 ),
        .SDIF0_IN_USE       ( 0 ),
        .SDIF0_PCIE         ( 0 ),
        .SDIF1_IN_USE       ( 0 ),
        .SDIF1_PCIE         ( 0 ),
        .SDIF2_IN_USE       ( 0 ),
        .SDIF2_PCIE         ( 0 ),
        .SDIF3_IN_USE       ( 0 ),
        .SDIF3_PCIE         ( 0 ) )
CORECONFIGP_0(
        // Inputs
        .FIC_2_APB_M_PRESET_N           ( MDDR_TA_MSS_TMP_0_FIC_2_APB_M_PRESET_N ),
        .FIC_2_APB_M_PCLK               ( MDDR_TA_MSS_TMP_0_FIC_2_APB_M_PCLK ),
        .SDIF_RELEASED                  ( GND_net ), // tied to 1'b0 from definition
        .INIT_DONE                      ( INIT_DONE_net_0 ),
        .FIC_2_APB_M_PSEL               ( MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSELx ),
        .FIC_2_APB_M_PENABLE            ( MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE ),
        .FIC_2_APB_M_PWRITE             ( MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE ),
        .FIC_2_APB_M_PADDR              ( MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR ),
        .FIC_2_APB_M_PWDATA             ( MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA ),
        .MDDR_PRDATA                    ( CORECONFIGP_0_MDDR_APBmslave_PRDATA_0 ),
        .MDDR_PREADY                    ( CORECONFIGP_0_MDDR_APBmslave_PREADY ),
        .MDDR_PSLVERR                   ( CORECONFIGP_0_MDDR_APBmslave_PSLVERR ),
        .FDDR_PRDATA                    ( FDDR_PRDATA_const_net_0 ), // tied to 32'h00000000 from definition
        .FDDR_PREADY                    ( VCC_net ), // tied to 1'b1 from definition
        .FDDR_PSLVERR                   ( GND_net ), // tied to 1'b0 from definition
        .SDIF0_PRDATA                   ( SDIF0_PRDATA_const_net_0 ), // tied to 32'h00000000 from definition
        .SDIF0_PREADY                   ( VCC_net ), // tied to 1'b1 from definition
        .SDIF0_PSLVERR                  ( GND_net ), // tied to 1'b0 from definition
        .SDIF1_PRDATA                   ( SDIF1_PRDATA_const_net_0 ), // tied to 32'h00000000 from definition
        .SDIF1_PREADY                   ( VCC_net ), // tied to 1'b1 from definition
        .SDIF1_PSLVERR                  ( GND_net ), // tied to 1'b0 from definition
        .SDIF2_PRDATA                   ( SDIF2_PRDATA_const_net_0 ), // tied to 32'h00000000 from definition
        .SDIF2_PREADY                   ( VCC_net ), // tied to 1'b1 from definition
        .SDIF2_PSLVERR                  ( GND_net ), // tied to 1'b0 from definition
        .SDIF3_PRDATA                   ( SDIF3_PRDATA_const_net_0 ), // tied to 32'h00000000 from definition
        .SDIF3_PREADY                   ( VCC_net ), // tied to 1'b1 from definition
        .SDIF3_PSLVERR                  ( GND_net ), // tied to 1'b0 from definition
        // Outputs
        .APB_S_PCLK                     ( CORECONFIGP_0_APB_S_PCLK ),
        .APB_S_PRESET_N                 ( CORECONFIGP_0_APB_S_PRESET_N ),
        .CONFIG1_DONE                   ( CORECONFIGP_0_CONFIG1_DONE ),
        .CONFIG2_DONE                   ( CORECONFIGP_0_CONFIG2_DONE ),
        .FIC_2_APB_M_PRDATA             ( MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA ),
        .FIC_2_APB_M_PREADY             ( MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PREADY ),
        .FIC_2_APB_M_PSLVERR            ( MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSLVERR ),
        .MDDR_PSEL                      ( CORECONFIGP_0_MDDR_APBmslave_PSELx ),
        .MDDR_PENABLE                   ( CORECONFIGP_0_MDDR_APBmslave_PENABLE ),
        .MDDR_PWRITE                    ( CORECONFIGP_0_MDDR_APBmslave_PWRITE ),
        .MDDR_PADDR                     ( CORECONFIGP_0_MDDR_APBmslave_PADDR ),
        .MDDR_PWDATA                    ( CORECONFIGP_0_MDDR_APBmslave_PWDATA ),
        .FDDR_PSEL                      (  ),
        .FDDR_PENABLE                   (  ),
        .FDDR_PWRITE                    (  ),
        .FDDR_PADDR                     (  ),
        .FDDR_PWDATA                    (  ),
        .SDIF0_PSEL                     (  ),
        .SDIF0_PENABLE                  (  ),
        .SDIF0_PWRITE                   (  ),
        .SDIF0_PADDR                    (  ),
        .SDIF0_PWDATA                   (  ),
        .SDIF1_PSEL                     (  ),
        .SDIF1_PENABLE                  (  ),
        .SDIF1_PWRITE                   (  ),
        .SDIF1_PADDR                    (  ),
        .SDIF1_PWDATA                   (  ),
        .SDIF2_PSEL                     (  ),
        .SDIF2_PENABLE                  (  ),
        .SDIF2_PWRITE                   (  ),
        .SDIF2_PADDR                    (  ),
        .SDIF2_PWDATA                   (  ),
        .SDIF3_PSEL                     (  ),
        .SDIF3_PENABLE                  (  ),
        .SDIF3_PWRITE                   (  ),
        .SDIF3_PADDR                    (  ),
        .SDIF3_PWDATA                   (  ),
        .SOFT_EXT_RESET_OUT             ( CORECONFIGP_0_SOFT_EXT_RESET_OUT ),
        .SOFT_RESET_F2M                 ( CORECONFIGP_0_SOFT_RESET_F2M ),
        .SOFT_M3_RESET                  ( CORECONFIGP_0_SOFT_M3_RESET ),
        .SOFT_MDDR_DDR_AXI_S_CORE_RESET ( CORECONFIGP_0_SOFT_MDDR_DDR_AXI_S_CORE_RESET ),
        .SOFT_FDDR_CORE_RESET           (  ),
        .SOFT_SDIF0_PHY_RESET           (  ),
        .SOFT_SDIF0_CORE_RESET          (  ),
        .SOFT_SDIF0_0_CORE_RESET        (  ),
        .SOFT_SDIF0_1_CORE_RESET        (  ),
        .SOFT_SDIF1_PHY_RESET           (  ),
        .SOFT_SDIF1_CORE_RESET          (  ),
        .SOFT_SDIF2_PHY_RESET           (  ),
        .SOFT_SDIF2_CORE_RESET          (  ),
        .SOFT_SDIF3_PHY_RESET           (  ),
        .SOFT_SDIF3_CORE_RESET          (  ),
        .R_SDIF0_PSEL                   (  ),
        .R_SDIF0_PWRITE                 (  ),
        .R_SDIF0_PRDATA                 (  ),
        .R_SDIF1_PSEL                   (  ),
        .R_SDIF1_PWRITE                 (  ),
        .R_SDIF1_PRDATA                 (  ),
        .R_SDIF2_PSEL                   (  ),
        .R_SDIF2_PWRITE                 (  ),
        .R_SDIF2_PRDATA                 (  ),
        .R_SDIF3_PSEL                   (  ),
        .R_SDIF3_PWRITE                 (  ),
        .R_SDIF3_PRDATA                 (  ) 
        );

//--------CoreResetP   -   Actel:DirectCore:CoreResetP:7.0.104
CoreResetP #( 
        .DDR_WAIT            ( 200 ),
        .DEVICE_090          ( 0 ),
        .DEVICE_VOLTAGE      ( 2 ),
        .ENABLE_SOFT_RESETS  ( 1 ),
        .EXT_RESET_CFG       ( 0 ),
        .FDDR_IN_USE         ( 0 ),
        .MDDR_IN_USE         ( 1 ),
        .SDIF0_IN_USE        ( 0 ),
        .SDIF0_PCIE          ( 0 ),
        .SDIF0_PCIE_HOTRESET ( 1 ),
        .SDIF0_PCIE_L2P2     ( 1 ),
        .SDIF1_IN_USE        ( 0 ),
        .SDIF1_PCIE          ( 0 ),
        .SDIF1_PCIE_HOTRESET ( 1 ),
        .SDIF1_PCIE_L2P2     ( 1 ),
        .SDIF2_IN_USE        ( 0 ),
        .SDIF2_PCIE          ( 0 ),
        .SDIF2_PCIE_HOTRESET ( 1 ),
        .SDIF2_PCIE_L2P2     ( 1 ),
        .SDIF3_IN_USE        ( 0 ),
        .SDIF3_PCIE          ( 0 ),
        .SDIF3_PCIE_HOTRESET ( 1 ),
        .SDIF3_PCIE_L2P2     ( 1 ) )
CORERESETP_0(
        // Inputs
        .RESET_N_M2F                    ( MDDR_TA_MSS_TMP_0_MSS_RESET_N_M2F ),
        .FIC_2_APB_M_PRESET_N           ( MDDR_TA_MSS_TMP_0_FIC_2_APB_M_PRESET_N ),
        .POWER_ON_RESET_N               ( POWER_ON_RESET_N_net_0 ),
        .FAB_RESET_N                    ( FAB_RESET_N ),
        .RCOSC_25_50MHZ                 ( FABOSC_0_RCOSC_25_50MHZ_O2F ),
        .CLK_BASE                       ( FIC_0_CLK_net_0 ),
        .CLK_LTSSM                      ( GND_net ), // tied to 1'b0 from definition
        .FPLL_LOCK                      ( VCC_net ), // tied to 1'b1 from definition
        .SDIF0_SPLL_LOCK                ( VCC_net ), // tied to 1'b1 from definition
        .SDIF1_SPLL_LOCK                ( VCC_net ), // tied to 1'b1 from definition
        .SDIF2_SPLL_LOCK                ( VCC_net ), // tied to 1'b1 from definition
        .SDIF3_SPLL_LOCK                ( VCC_net ), // tied to 1'b1 from definition
        .CONFIG1_DONE                   ( CORECONFIGP_0_CONFIG1_DONE ),
        .CONFIG2_DONE                   ( CORECONFIGP_0_CONFIG2_DONE ),
        .SDIF0_PERST_N                  ( VCC_net ), // tied to 1'b1 from definition
        .SDIF1_PERST_N                  ( VCC_net ), // tied to 1'b1 from definition
        .SDIF2_PERST_N                  ( VCC_net ), // tied to 1'b1 from definition
        .SDIF3_PERST_N                  ( VCC_net ), // tied to 1'b1 from definition
        .SDIF0_PSEL                     ( GND_net ), // tied to 1'b0 from definition
        .SDIF0_PWRITE                   ( VCC_net ), // tied to 1'b1 from definition
        .SDIF0_PRDATA                   ( SDIF0_PRDATA_const_net_1 ), // tied to 32'h00000000 from definition
        .SDIF1_PSEL                     ( GND_net ), // tied to 1'b0 from definition
        .SDIF1_PWRITE                   ( VCC_net ), // tied to 1'b1 from definition
        .SDIF1_PRDATA                   ( SDIF1_PRDATA_const_net_1 ), // tied to 32'h00000000 from definition
        .SDIF2_PSEL                     ( GND_net ), // tied to 1'b0 from definition
        .SDIF2_PWRITE                   ( VCC_net ), // tied to 1'b1 from definition
        .SDIF2_PRDATA                   ( SDIF2_PRDATA_const_net_1 ), // tied to 32'h00000000 from definition
        .SDIF3_PSEL                     ( GND_net ), // tied to 1'b0 from definition
        .SDIF3_PWRITE                   ( VCC_net ), // tied to 1'b1 from definition
        .SDIF3_PRDATA                   ( SDIF3_PRDATA_const_net_1 ), // tied to 32'h00000000 from definition
        .SOFT_EXT_RESET_OUT             ( CORECONFIGP_0_SOFT_EXT_RESET_OUT ),
        .SOFT_RESET_F2M                 ( CORECONFIGP_0_SOFT_RESET_F2M ),
        .SOFT_M3_RESET                  ( CORECONFIGP_0_SOFT_M3_RESET ),
        .SOFT_MDDR_DDR_AXI_S_CORE_RESET ( CORECONFIGP_0_SOFT_MDDR_DDR_AXI_S_CORE_RESET ),
        .SOFT_FDDR_CORE_RESET           ( GND_net ), // tied to 1'b0 from definition
        .SOFT_SDIF0_PHY_RESET           ( GND_net ), // tied to 1'b0 from definition
        .SOFT_SDIF0_CORE_RESET          ( GND_net ), // tied to 1'b0 from definition
        .SOFT_SDIF0_0_CORE_RESET        ( GND_net ), // tied to 1'b0 from definition
        .SOFT_SDIF0_1_CORE_RESET        ( GND_net ), // tied to 1'b0 from definition
        .SOFT_SDIF1_PHY_RESET           ( GND_net ), // tied to 1'b0 from definition
        .SOFT_SDIF1_CORE_RESET          ( GND_net ), // tied to 1'b0 from definition
        .SOFT_SDIF2_PHY_RESET           ( GND_net ), // tied to 1'b0 from definition
        .SOFT_SDIF2_CORE_RESET          ( GND_net ), // tied to 1'b0 from definition
        .SOFT_SDIF3_PHY_RESET           ( GND_net ), // tied to 1'b0 from definition
        .SOFT_SDIF3_CORE_RESET          ( GND_net ), // tied to 1'b0 from definition
        // Outputs
        .MSS_HPMS_READY                 ( MSS_READY_net_0 ),
        .DDR_READY                      ( DDR_READY_net_0 ),
        .SDIF_READY                     (  ),
        .RESET_N_F2M                    ( CORERESETP_0_RESET_N_F2M ),
        .M3_RESET_N                     ( CORERESETP_0_M3_RESET_N ),
        .EXT_RESET_OUT                  (  ),
        .MDDR_DDR_AXI_S_CORE_RESET_N    ( CORERESETP_0_MDDR_DDR_AXI_S_CORE_RESET_N ),
        .FDDR_CORE_RESET_N              (  ),
        .SDIF0_CORE_RESET_N             (  ),
        .SDIF0_0_CORE_RESET_N           (  ),
        .SDIF0_1_CORE_RESET_N           (  ),
        .SDIF0_PHY_RESET_N              (  ),
        .SDIF1_CORE_RESET_N             (  ),
        .SDIF1_PHY_RESET_N              (  ),
        .SDIF2_CORE_RESET_N             (  ),
        .SDIF2_PHY_RESET_N              (  ),
        .SDIF3_CORE_RESET_N             (  ),
        .SDIF3_PHY_RESET_N              (  ),
        .SDIF_RELEASED                  (  ),
        .INIT_DONE                      ( INIT_DONE_net_0 ) 
        );

//--------MDDR_TA_FABOSC_0_OSC   -   Actel:SgCore:OSC:1.0.105
MDDR_TA_FABOSC_0_OSC FABOSC_0(
        // Inputs
        .XTL                ( GND_net ), // tied to 1'b0 from definition
        // Outputs
        .RCOSC_25_50MHZ_CCC ( FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC ),
        .RCOSC_25_50MHZ_O2F ( FABOSC_0_RCOSC_25_50MHZ_O2F ),
        .RCOSC_1MHZ_CCC     (  ),
        .RCOSC_1MHZ_O2F     (  ),
        .XTLOSC_CCC         (  ),
        .XTLOSC_O2F         (  ) 
        );

//--------MDDR_TA_MSS
MDDR_TA_MSS MDDR_TA_MSS_0(
        // Inputs
        .MCCC_CLK_BASE          ( FIC_0_CLK_net_0 ),
        .MMUART_0_RXD           ( MMUART_0_RXD ),
        .MDDR_DQS_TMATCH_0_IN   ( MDDR_DQS_TMATCH_0_IN ),
        .MCCC_CLK_BASE_PLL_LOCK ( MSS_DDR_FIC_SUBSYSTEM_LOCK_net_0 ),
        .MSS_RESET_N_F2M        ( CORERESETP_0_RESET_N_F2M ),
        .MDDR_DDR_CORE_RESET_N  ( CORERESETP_0_MDDR_DDR_AXI_S_CORE_RESET_N ),
        .MDDR_DDR_AXI_S_RMW     ( MDDR_AXI_S_RMW ),
        .MDDR_DDR_AXI_S_AWVALID ( COREAXI_0_AXImslave0_AWVALID ),
        .MDDR_DDR_AXI_S_WLAST   ( COREAXI_0_AXImslave0_WLAST ),
        .MDDR_DDR_AXI_S_WVALID  ( COREAXI_0_AXImslave0_WVALID ),
        .MDDR_DDR_AXI_S_BREADY  ( COREAXI_0_AXImslave0_BREADY ),
        .MDDR_DDR_AXI_S_ARVALID ( COREAXI_0_AXImslave0_ARVALID ),
        .MDDR_DDR_AXI_S_RREADY  ( COREAXI_0_AXImslave0_RREADY ),
        .FIC_0_AHB_S_HREADY     ( CoreAHBLite_0_AHBmslave16_HREADY ),
        .FIC_0_AHB_S_HWRITE     ( CoreAHBLite_0_AHBmslave16_HWRITE ),
        .FIC_0_AHB_S_HMASTLOCK  ( CoreAHBLite_0_AHBmslave16_HMASTLOCK ),
        .FIC_0_AHB_S_HSEL       ( CoreAHBLite_0_AHBmslave16_HSELx ),
        .M3_RESET_N             ( CORERESETP_0_M3_RESET_N ),
        .MDDR_APB_S_PRESET_N    ( CORECONFIGP_0_APB_S_PRESET_N ),
        .MDDR_APB_S_PCLK        ( CORECONFIGP_0_APB_S_PCLK ),
        .FIC_2_APB_M_PREADY     ( MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PREADY ),
        .FIC_2_APB_M_PSLVERR    ( MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSLVERR ),
        .MDDR_APB_S_PWRITE      ( CORECONFIGP_0_MDDR_APBmslave_PWRITE ),
        .MDDR_APB_S_PENABLE     ( CORECONFIGP_0_MDDR_APBmslave_PENABLE ),
        .MDDR_APB_S_PSEL        ( CORECONFIGP_0_MDDR_APBmslave_PSELx ),
        .MDDR_DDR_AXI_S_AWID    ( COREAXI_0_AXImslave0_AWID_0 ),
        .MDDR_DDR_AXI_S_AWADDR  ( COREAXI_0_AXImslave0_AWADDR ),
        .MDDR_DDR_AXI_S_AWLEN   ( COREAXI_0_AXImslave0_AWLEN ),
        .MDDR_DDR_AXI_S_AWSIZE  ( COREAXI_0_AXImslave0_AWSIZE_0 ),
        .MDDR_DDR_AXI_S_AWBURST ( COREAXI_0_AXImslave0_AWBURST ),
        .MDDR_DDR_AXI_S_AWLOCK  ( COREAXI_0_AXImslave0_AWLOCK ),
        .MDDR_DDR_AXI_S_WID     ( COREAXI_0_AXImslave0_WID_0 ),
        .MDDR_DDR_AXI_S_WDATA   ( COREAXI_0_AXImslave0_WDATA ),
        .MDDR_DDR_AXI_S_WSTRB   ( COREAXI_0_AXImslave0_WSTRB ),
        .MDDR_DDR_AXI_S_ARID    ( COREAXI_0_AXImslave0_ARID_0 ),
        .MDDR_DDR_AXI_S_ARADDR  ( COREAXI_0_AXImslave0_ARADDR ),
        .MDDR_DDR_AXI_S_ARLEN   ( COREAXI_0_AXImslave0_ARLEN ),
        .MDDR_DDR_AXI_S_ARSIZE  ( COREAXI_0_AXImslave0_ARSIZE_0 ),
        .MDDR_DDR_AXI_S_ARBURST ( COREAXI_0_AXImslave0_ARBURST ),
        .MDDR_DDR_AXI_S_ARLOCK  ( COREAXI_0_AXImslave0_ARLOCK ),
        .FIC_0_AHB_S_HADDR      ( CoreAHBLite_0_AHBmslave16_HADDR ),
        .FIC_0_AHB_S_HWDATA     ( CoreAHBLite_0_AHBmslave16_HWDATA ),
        .FIC_0_AHB_S_HSIZE      ( CoreAHBLite_0_AHBmslave16_HSIZE_0 ),
        .FIC_0_AHB_S_HTRANS     ( CoreAHBLite_0_AHBmslave16_HTRANS ),
        .FIC_2_APB_M_PRDATA     ( MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PRDATA ),
        .MDDR_APB_S_PWDATA      ( CORECONFIGP_0_MDDR_APBmslave_PWDATA_0 ),
        .MDDR_APB_S_PADDR       ( CORECONFIGP_0_MDDR_APBmslave_PADDR_0 ),
        // Outputs
        .MMUART_0_TXD           ( MMUART_0_TXD_net_0 ),
        .MDDR_DQS_TMATCH_0_OUT  ( MDDR_DQS_TMATCH_0_OUT_net_0 ),
        .MDDR_CAS_N             ( MDDR_CAS_N_net_0 ),
        .MDDR_CLK               ( MDDR_CLK_net_0 ),
        .MDDR_CLK_N             ( MDDR_CLK_N_net_0 ),
        .MDDR_CKE               ( MDDR_CKE_net_0 ),
        .MDDR_CS_N              ( MDDR_CS_N_net_0 ),
        .MDDR_ODT               ( MDDR_ODT_net_0 ),
        .MDDR_RAS_N             ( MDDR_RAS_N_net_0 ),
        .MDDR_RESET_N           ( MDDR_RESET_N_net_0 ),
        .MDDR_WE_N              ( MDDR_WE_N_net_0 ),
        .MSS_RESET_N_M2F        ( MDDR_TA_MSS_TMP_0_MSS_RESET_N_M2F ),
        .GPIO_0_M2F             ( GPIO_0_M2F_net_0 ),
        .GPIO_1_M2F             ( GPIO_1_M2F_net_0 ),
        .GPIO_2_M2F             ( GPIO_2_M2F_net_0 ),
        .GPIO_3_M2F             ( GPIO_3_M2F_net_0 ),
        .GPIO_4_M2F             ( GPIO_4_M2F_net_0 ),
        .GPIO_5_M2F             ( GPIO_5_M2F_net_0 ),
        .GPIO_6_M2F             ( GPIO_6_M2F_net_0 ),
        .GPIO_7_M2F             ( GPIO_7_M2F_net_0 ),
        .MDDR_DDR_AXI_S_AWREADY ( COREAXI_0_AXImslave0_AWREADY ),
        .MDDR_DDR_AXI_S_WREADY  ( COREAXI_0_AXImslave0_WREADY ),
        .MDDR_DDR_AXI_S_BVALID  ( COREAXI_0_AXImslave0_BVALID ),
        .MDDR_DDR_AXI_S_ARREADY ( COREAXI_0_AXImslave0_ARREADY ),
        .MDDR_DDR_AXI_S_RLAST   ( COREAXI_0_AXImslave0_RLAST ),
        .MDDR_DDR_AXI_S_RVALID  ( COREAXI_0_AXImslave0_RVALID ),
        .FIC_0_AHB_S_HRESP      ( CoreAHBLite_0_AHBmslave16_HRESP ),
        .FIC_0_AHB_S_HREADYOUT  ( CoreAHBLite_0_AHBmslave16_HREADYOUT ),
        .FIC_2_APB_M_PRESET_N   ( MDDR_TA_MSS_TMP_0_FIC_2_APB_M_PRESET_N ),
        .FIC_2_APB_M_PCLK       ( MDDR_TA_MSS_TMP_0_FIC_2_APB_M_PCLK ),
        .FIC_2_APB_M_PWRITE     ( MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWRITE ),
        .FIC_2_APB_M_PENABLE    ( MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PENABLE ),
        .FIC_2_APB_M_PSEL       ( MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PSELx ),
        .MDDR_APB_S_PREADY      ( CORECONFIGP_0_MDDR_APBmslave_PREADY ),
        .MDDR_APB_S_PSLVERR     ( CORECONFIGP_0_MDDR_APBmslave_PSLVERR ),
        .MDDR_ADDR              ( MDDR_ADDR_net_0 ),
        .MDDR_BA                ( MDDR_BA_net_0 ),
        .MDDR_DDR_AXI_S_BID     ( COREAXI_0_AXImslave0_BID ),
        .MDDR_DDR_AXI_S_BRESP   ( COREAXI_0_AXImslave0_BRESP ),
        .MDDR_DDR_AXI_S_RID     ( COREAXI_0_AXImslave0_RID ),
        .MDDR_DDR_AXI_S_RRESP   ( COREAXI_0_AXImslave0_RRESP ),
        .MDDR_DDR_AXI_S_RDATA   ( COREAXI_0_AXImslave0_RDATA ),
        .FIC_0_AHB_S_HRDATA     ( CoreAHBLite_0_AHBmslave16_HRDATA ),
        .FIC_2_APB_M_PADDR      ( MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PADDR ),
        .FIC_2_APB_M_PWDATA     ( MDDR_TA_MSS_TMP_0_FIC_2_APB_MASTER_PWDATA ),
        .MDDR_APB_S_PRDATA      ( CORECONFIGP_0_MDDR_APBmslave_PRDATA ),
        // Inouts
        .MDDR_DM_RDQS           ( MDDR_DM_RDQS ),
        .MDDR_DQ                ( MDDR_DQ ),
        .MDDR_DQS               ( MDDR_DQS ),
        .MDDR_DQS_N             ( MDDR_DQS_N ) 
        );

//--------SYSRESET
SYSRESET SYSRESET_POR(
        // Inputs
        .DEVRST_N         ( DEVRST_N ),
        // Outputs
        .POWER_ON_RESET_N ( POWER_ON_RESET_N_net_0 ) 
        );


endmodule
