| Project Settings |
|---|
| Project Name | FlashFreeze_SB_top_syn | Implementation Name | synthesis |
| Top Module | FlashFreeze_SB_top | Retiming | 0 |
| Resource Sharing | 1 | Fanout Guide | 10000 |
| Disable I/O Insertion | 0 | Disable Sequential Optimizations | 0 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
262 |
69 |
0 |
- |
00m:01s |
- |
17-Mar-2017
02:26 PM |
| (premap) | Complete |
93 |
27 |
0 |
0m:00s |
0m:00s |
150MB |
17-Mar-2017
02:26 PM |
| (fpga_mapper) | Complete |
129 |
43 |
0 |
0m:02s |
0m:02s |
145MB |
17-Mar-2017
02:26 PM |
| Multi-srs Generator |
Complete | | | | 00m:01s | | | 17-Mar-2017
02:26 PM |
| Area Summary |
|---|
| |
| Carry Cells | 27 |
Sequential Cells | 139 |
| DSP Blocks (MACC)
(dsp_used) | 0 |
I/O Cells | 51 |
| Global Clock Buffers | 3 |
RAM1K18
(v_ram) | 1 |
| LUTs
(total_luts) | 253 |
| |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock | 100.0 MHz | 107.2 MHz | 0.676 |
| FlashFreeze_SB_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock | 100.0 MHz | NA | NA |
| System | 100.0 MHz | 488.5 MHz | 7.953 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 0 / 3 |
| |
|