#Build: Synplify Pro L-2016.09M-2, Build 065R, Nov 16 2016 #install: D:\Microsemi\Libero_SoC_v11.8\SynplifyPro #OS: Windows 7 6.1 #Hostname: W764D-ATHULDEEP # Fri Mar 17 14:26:27 2017 #Implementation: synthesis Synopsys HDL Compiler, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Synopsys Verilog Compiler, version comp2016q3p1, Build 127R, built Nov 24 2016 @N: : | Running in 64-bit mode Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. @I::"D:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\generic\smartfusion2.v" (library work) @I::"D:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"D:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"D:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"D:\Microsemi\Libero_SoC_v11.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\work\DIP_SWITCHES\DIP_SWITCHES.v" (library work) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp_pcie_hotreset.v" (library work) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v" (library work) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\work\FlashFreeze_SB\CCC_0\FlashFreeze_SB_CCC_0_FCCC.v" (library work) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\SgCore\OSC\2.0.101\osc_comps.v" (library work) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\work\FlashFreeze_SB\FABOSC_0\FlashFreeze_SB_FABOSC_0_OSC.v" (library work) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\work\FlashFreeze_SB_MSS\FlashFreeze_SB_MSS_syn.v" (library work) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\work\FlashFreeze_SB_MSS\FlashFreeze_SB_MSS.v" (library work) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_addrdec.v" (library COREAHBLITE_LIB) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_defaultslavesm.v" (library COREAHBLITE_LIB) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v" (library COREAHBLITE_LIB) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavearbiter.v" (library COREAHBLITE_LIB) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_slavestage.v" (library COREAHBLITE_LIB) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_matrix4x16.v" (library COREAHBLITE_LIB) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v" (library COREAHBLITE_LIB) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\work\FlashFreeze_SB\FlashFreeze_SB.v" (library work) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\work\RAM_with_wrapper\SRAM_64x8_0\RAM_with_wrapper_SRAM_64x8_0_TPSRAM.v" (library work) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\hdl\mem_apb_wrp.v" (library work) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\hdl\mux_blk.v" (library work) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\work\RAM_with_wrapper\RAM_with_wrapper.v" (library work) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\hdl\cnt34.v" (library work) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_ahbtoapbsm.v" (library COREAHBTOAPB3_LIB) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_penablescheduler.v" (library COREAHBTOAPB3_LIB) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3_apbaddrdata.v" (library COREAHBTOAPB3_LIB) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3.v" (library COREAHBTOAPB3_LIB) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_muxptob3.v" (library COREAPB3_LIB) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3_iaddr_reg.v" (library COREAPB3_LIB) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v" (library COREAPB3_LIB) @I::"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\work\FlashFreeze_SB_top\FlashFreeze_SB_top.v" (library work) Verilog syntax check successful! File D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\work\FlashFreeze_SB\CCC_0\FlashFreeze_SB_CCC_0_FCCC.v changed - recompiling File D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\work\FlashFreeze_SB\FABOSC_0\FlashFreeze_SB_FABOSC_0_OSC.v changed - recompiling File D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\work\FlashFreeze_SB_MSS\FlashFreeze_SB_MSS_syn.v changed - recompiling File D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\work\FlashFreeze_SB_MSS\FlashFreeze_SB_MSS.v changed - recompiling File D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\work\FlashFreeze_SB\FlashFreeze_SB.v changed - recompiling File D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\work\FlashFreeze_SB_top\FlashFreeze_SB_top.v changed - recompiling Selecting top level module FlashFreeze_SB_top @N:CG364 : cnt34.v(7) | Synthesizing module cnt34 in library work. @W:CG775 : coreahbtoapb3.v(8) | Found Component COREAHBTOAPB3 in library COREAHBTOAPB3_LIB @N:CG364 : coreahbtoapb3_ahbtoapbsm.v(8) | Synthesizing module CAHBtoAPB3O in library COREAHBTOAPB3_LIB. SYNC_RESET=32'b00000000000000000000000000000000 CAHBtoAPB3O0=2'b00 CAHBtoAPB3I0=2'b01 CAHBtoAPB3l0=3'b000 CAHBtoAPB3O1=3'b001 CAHBtoAPB3I1=3'b010 CAHBtoAPB3l1=3'b011 CAHBtoAPB3OOI=3'b100 Generated name = CAHBtoAPB3O_0s_0_1_0_1_2_3_4 @N:CG364 : coreahbtoapb3_penablescheduler.v(8) | Synthesizing module CAHBtoAPB3OIl in library COREAHBTOAPB3_LIB. SYNC_RESET=32'b00000000000000000000000000000000 CAHBtoAPB3l0=2'b00 CAHBtoAPB3OOI=2'b01 CAHBtoAPB3IIl=2'b10 Generated name = CAHBtoAPB3OIl_0s_0_1_2 @N:CG364 : coreahbtoapb3_apbaddrdata.v(8) | Synthesizing module CAHBtoAPB3l1I in library COREAHBTOAPB3_LIB. SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CAHBtoAPB3l1I_0s @N:CG364 : coreahbtoapb3.v(8) | Synthesizing module COREAHBTOAPB3 in library COREAHBTOAPB3_LIB. FAMILY=32'b00000000000000000000000000010011 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = COREAHBTOAPB3_19s_0s @W:CG775 : coreapb3.v(31) | Found Component CoreAPB3 in library COREAPB3_LIB @N:CG364 : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3 in library COREAPB3_LIB. @N:CG364 : coreapb3.v(31) | Synthesizing module CoreAPB3 in library COREAPB3_LIB. APB_DWIDTH=6'b100000 IADDR_OPTION=32'b00000000000000000000000000000000 APBSLOT0ENABLE=1'b1 APBSLOT1ENABLE=1'b0 APBSLOT2ENABLE=1'b0 APBSLOT3ENABLE=1'b0 APBSLOT4ENABLE=1'b0 APBSLOT5ENABLE=1'b0 APBSLOT6ENABLE=1'b0 APBSLOT7ENABLE=1'b0 APBSLOT8ENABLE=1'b0 APBSLOT9ENABLE=1'b0 APBSLOT10ENABLE=1'b0 APBSLOT11ENABLE=1'b0 APBSLOT12ENABLE=1'b0 APBSLOT13ENABLE=1'b0 APBSLOT14ENABLE=1'b0 APBSLOT15ENABLE=1'b0 SC_0=1'b0 SC_1=1'b0 SC_2=1'b0 SC_3=1'b0 SC_4=1'b0 SC_5=1'b0 SC_6=1'b0 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 MADDR_BITS=6'b011100 UPR_NIBBLE_POSN=4'b0110 FAMILY=32'b00000000000000000000000000010011 SYNC_RESET=32'b00000000000000000000000000000000 IADDR_NOTINUSE=32'b00000000000000000000000000000000 IADDR_EXTERNAL=32'b00000000000000000000000000000001 IADDR_SLOT0=32'b00000000000000000000000000000010 IADDR_SLOT1=32'b00000000000000000000000000000011 IADDR_SLOT2=32'b00000000000000000000000000000100 IADDR_SLOT3=32'b00000000000000000000000000000101 IADDR_SLOT4=32'b00000000000000000000000000000110 IADDR_SLOT5=32'b00000000000000000000000000000111 IADDR_SLOT6=32'b00000000000000000000000000001000 IADDR_SLOT7=32'b00000000000000000000000000001001 IADDR_SLOT8=32'b00000000000000000000000000001010 IADDR_SLOT9=32'b00000000000000000000000000001011 IADDR_SLOT10=32'b00000000000000000000000000001100 IADDR_SLOT11=32'b00000000000000000000000000001101 IADDR_SLOT12=32'b00000000000000000000000000001110 IADDR_SLOT13=32'b00000000000000000000000000001111 IADDR_SLOT14=32'b00000000000000000000000000010000 IADDR_SLOT15=32'b00000000000000000000000000010001 SL0=16'b0000000000000001 SL1=16'b0000000000000000 SL2=16'b0000000000000000 SL3=16'b0000000000000000 SL4=16'b0000000000000000 SL5=16'b0000000000000000 SL6=16'b0000000000000000 SL7=16'b0000000000000000 SL8=16'b0000000000000000 SL9=16'b0000000000000000 SL10=16'b0000000000000000 SL11=16'b0000000000000000 SL12=16'b0000000000000000 SL13=16'b0000000000000000 SL14=16'b0000000000000000 SL15=16'b0000000000000000 SC=16'b0000000000000000 SC_qual=16'b0000000000000000 Generated name = CoreAPB3_Z1 @W:CG360 : coreapb3.v(244) | Removing wire IA_PRDATA, as there is no assignment to it. @N:CG364 : DIP_SWITCHES.v(9) | Synthesizing module DIP_SWITCHES in library work. @N:CG364 : smartfusion2.v(835) | Synthesizing module FLASH_FREEZE in library work. @N:CG364 : smartfusion2.v(376) | Synthesizing module VCC in library work. @N:CG364 : smartfusion2.v(372) | Synthesizing module GND in library work. @N:CG364 : smartfusion2.v(362) | Synthesizing module CLKINT in library work. @N:CG364 : smartfusion2.v(727) | Synthesizing module CCC in library work. @N:CG364 : FlashFreeze_SB_CCC_0_FCCC.v(5) | Synthesizing module FlashFreeze_SB_CCC_0_FCCC in library work. @W:CG775 : coreahblite.v(23) | Found Component CoreAHBLite in library COREAHBLITE_LIB @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC in library COREAHBLITE_LIB. MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000001 MSB_ADDR=32'b00000000000000000000000000011011 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z2 @N:CG364 : coreahblite_defaultslavesm.v(20) | Synthesizing module COREAHBLITE_DEFAULTSLAVESM in library COREAHBLITE_LIB. SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 HRESPEXTEND=1'b1 Generated name = COREAHBLITE_DEFAULTSLAVESM_0s_0_1 @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE in library COREAHBLITE_LIB. MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000001 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_2_1_0_1_0s_0_1_0 @W:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing. @N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC in library COREAHBLITE_LIB. MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000000 MSB_ADDR=32'b00000000000000000000000000011011 SLAVE_0=16'b0000000000000001 SLAVE_1=16'b0000000000000010 SLAVE_2=16'b0000000000000100 SLAVE_3=16'b0000000000001000 SLAVE_4=16'b0000000000010000 SLAVE_5=16'b0000000000100000 SLAVE_6=16'b0000000001000000 SLAVE_7=16'b0000000010000000 SLAVE_8=16'b0000000100000000 SLAVE_9=16'b0000001000000000 SLAVE_10=16'b0000010000000000 SLAVE_11=16'b0000100000000000 SLAVE_12=16'b0001000000000000 SLAVE_13=16'b0010000000000000 SLAVE_14=16'b0100000000000000 SLAVE_15=16'b1000000000000000 NONE=16'b0000000000000000 Generated name = COREAHBLITE_ADDRDEC_Z3 @N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE in library COREAHBLITE_LIB. MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 IDLE=1'b0 REGISTERED=1'b1 SLAVE_NONE=17'b00000000000000000 Generated name = COREAHBLITE_MASTERSTAGE_2_1_0_0_0s_0_1_0 @W:CL177 : coreahblite_masterstage.v(625) | Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing. @N:CG364 : coreahblite_slavearbiter.v(20) | Synthesizing module COREAHBLITE_SLAVEARBITER in library COREAHBLITE_LIB. SYNC_RESET=32'b00000000000000000000000000000000 M0EXTEND=4'b0000 M0DONE=4'b0001 M0LOCK=4'b0010 M0LOCKEXTEND=4'b0011 M1EXTEND=4'b0100 M1DONE=4'b0101 M1LOCK=4'b0110 M1LOCKEXTEND=4'b0111 M2EXTEND=4'b1000 M2DONE=4'b1001 M2LOCK=4'b1010 M2LOCKEXTEND=4'b1011 M3EXTEND=4'b1100 M3DONE=4'b1101 M3LOCK=4'b1110 M3LOCKEXTEND=4'b1111 MASTER_0=4'b0001 MASTER_1=4'b0010 MASTER_2=4'b0100 MASTER_3=4'b1000 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVEARBITER_Z4 @N:CG364 : coreahblite_slavestage.v(22) | Synthesizing module COREAHBLITE_SLAVESTAGE in library COREAHBLITE_LIB. SYNC_RESET=32'b00000000000000000000000000000000 TRN_IDLE=1'b0 MASTER_NONE=4'b0000 Generated name = COREAHBLITE_SLAVESTAGE_0s_0_0 @N:CG364 : coreahblite_matrix4x16.v(23) | Synthesizing module COREAHBLITE_MATRIX4X16 in library COREAHBLITE_LIB. MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC=16'b0000000000000000 M0_AHBSLOTENABLE=17'b00000000000000001 M1_AHBSLOTENABLE=17'b00000000000000000 M2_AHBSLOTENABLE=17'b00000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = COREAHBLITE_MATRIX4X16_2_1_0_1_0_0_0_0s @N:CG364 : coreahblite.v(23) | Synthesizing module CoreAHBLite in library COREAHBLITE_LIB. FAMILY=6'b010011 MEMSPACE=3'b010 HADDR_SHG_CFG=1'b1 SC_0=1'b0 SC_1=1'b0 SC_2=1'b0 SC_3=1'b0 SC_4=1'b0 SC_5=1'b0 SC_6=1'b0 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 M0_AHBSLOT0ENABLE=1'b1 M0_AHBSLOT1ENABLE=1'b0 M0_AHBSLOT2ENABLE=1'b0 M0_AHBSLOT3ENABLE=1'b0 M0_AHBSLOT4ENABLE=1'b0 M0_AHBSLOT5ENABLE=1'b0 M0_AHBSLOT6ENABLE=1'b0 M0_AHBSLOT7ENABLE=1'b0 M0_AHBSLOT8ENABLE=1'b0 M0_AHBSLOT9ENABLE=1'b0 M0_AHBSLOT10ENABLE=1'b0 M0_AHBSLOT11ENABLE=1'b0 M0_AHBSLOT12ENABLE=1'b0 M0_AHBSLOT13ENABLE=1'b0 M0_AHBSLOT14ENABLE=1'b0 M0_AHBSLOT15ENABLE=1'b0 M0_AHBSLOT16ENABLE=1'b0 M1_AHBSLOT0ENABLE=1'b0 M1_AHBSLOT1ENABLE=1'b0 M1_AHBSLOT2ENABLE=1'b0 M1_AHBSLOT3ENABLE=1'b0 M1_AHBSLOT4ENABLE=1'b0 M1_AHBSLOT5ENABLE=1'b0 M1_AHBSLOT6ENABLE=1'b0 M1_AHBSLOT7ENABLE=1'b0 M1_AHBSLOT8ENABLE=1'b0 M1_AHBSLOT9ENABLE=1'b0 M1_AHBSLOT10ENABLE=1'b0 M1_AHBSLOT11ENABLE=1'b0 M1_AHBSLOT12ENABLE=1'b0 M1_AHBSLOT13ENABLE=1'b0 M1_AHBSLOT14ENABLE=1'b0 M1_AHBSLOT15ENABLE=1'b0 M1_AHBSLOT16ENABLE=1'b0 M2_AHBSLOT0ENABLE=1'b0 M2_AHBSLOT1ENABLE=1'b0 M2_AHBSLOT2ENABLE=1'b0 M2_AHBSLOT3ENABLE=1'b0 M2_AHBSLOT4ENABLE=1'b0 M2_AHBSLOT5ENABLE=1'b0 M2_AHBSLOT6ENABLE=1'b0 M2_AHBSLOT7ENABLE=1'b0 M2_AHBSLOT8ENABLE=1'b0 M2_AHBSLOT9ENABLE=1'b0 M2_AHBSLOT10ENABLE=1'b0 M2_AHBSLOT11ENABLE=1'b0 M2_AHBSLOT12ENABLE=1'b0 M2_AHBSLOT13ENABLE=1'b0 M2_AHBSLOT14ENABLE=1'b0 M2_AHBSLOT15ENABLE=1'b0 M2_AHBSLOT16ENABLE=1'b0 M3_AHBSLOT0ENABLE=1'b0 M3_AHBSLOT1ENABLE=1'b0 M3_AHBSLOT2ENABLE=1'b0 M3_AHBSLOT3ENABLE=1'b0 M3_AHBSLOT4ENABLE=1'b0 M3_AHBSLOT5ENABLE=1'b0 M3_AHBSLOT6ENABLE=1'b0 M3_AHBSLOT7ENABLE=1'b0 M3_AHBSLOT8ENABLE=1'b0 M3_AHBSLOT9ENABLE=1'b0 M3_AHBSLOT10ENABLE=1'b0 M3_AHBSLOT11ENABLE=1'b0 M3_AHBSLOT12ENABLE=1'b0 M3_AHBSLOT13ENABLE=1'b0 M3_AHBSLOT14ENABLE=1'b0 M3_AHBSLOT15ENABLE=1'b0 M3_AHBSLOT16ENABLE=1'b0 SYNC_RESET=32'b00000000000000000000000000000000 M0_AHBSLOTENABLE=17'b00000000000000001 M1_AHBSLOTENABLE=17'b00000000000000000 M2_AHBSLOTENABLE=17'b00000000000000000 M3_AHBSLOTENABLE=17'b00000000000000000 SC=16'b0000000000000000 Generated name = CoreAHBLite_Z5 @N:CG364 : coreresetp.v(23) | Synthesizing module CoreResetP in library work. FAMILY=32'b00000000000000000000000000010011 EXT_RESET_CFG=32'b00000000000000000000000000000000 DEVICE_VOLTAGE=32'b00000000000000000000000000000010 MDDR_IN_USE=32'b00000000000000000000000000000000 FDDR_IN_USE=32'b00000000000000000000000000000000 SDIF0_IN_USE=32'b00000000000000000000000000000000 SDIF1_IN_USE=32'b00000000000000000000000000000000 SDIF2_IN_USE=32'b00000000000000000000000000000000 SDIF3_IN_USE=32'b00000000000000000000000000000000 SDIF0_PCIE=32'b00000000000000000000000000000000 SDIF1_PCIE=32'b00000000000000000000000000000000 SDIF2_PCIE=32'b00000000000000000000000000000000 SDIF3_PCIE=32'b00000000000000000000000000000000 SDIF0_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF1_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF2_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF3_PCIE_HOTRESET=32'b00000000000000000000000000000001 SDIF0_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF1_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF2_PCIE_L2P2=32'b00000000000000000000000000000001 SDIF3_PCIE_L2P2=32'b00000000000000000000000000000001 ENABLE_SOFT_RESETS=32'b00000000000000000000000000000000 INCL_FF_SUPPORT=32'b00000000000000000000000000000001 DEVICE_090=32'b00000000000000000000000000000001 DDR_WAIT=32'b00000000000000000000000011001000 RCOSC_MEGAHERTZ=32'b00000000000000000000000000110010 SDIF_INTERVAL=32'b00000000000000000001100101100100 DDR_INTERVAL=32'b00000000000000000010011100010000 COUNT_WIDTH_SDIF=32'b00000000000000000000000000001101 COUNT_WIDTH_DDR=32'b00000000000000000000000000001110 S0=32'b00000000000000000000000000000000 S1=32'b00000000000000000000000000000001 S2=32'b00000000000000000000000000000010 S3=32'b00000000000000000000000000000011 S4=32'b00000000000000000000000000000100 S5=32'b00000000000000000000000000000101 S6=32'b00000000000000000000000000000110 Generated name = CoreResetP_Z6 @W:CL169 : coreresetp.v(1728) | Pruning unused register count_ddr[13:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1696) | Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1664) | Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1632) | Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1600) | Pruning unused register count_sdif0[12:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1570) | Pruning unused register count_sdif0_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1570) | Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1570) | Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1570) | Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1570) | Pruning unused register count_sdif0_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1570) | Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1570) | Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1570) | Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1570) | Pruning unused register count_ddr_enable_q1. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1570) | Pruning unused register count_ddr_enable_rcosc. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1480) | Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1415) | Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1350) | Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1285) | Pruning unused register count_sdif0_enable. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1204) | Pruning unused register count_ddr_enable. Make sure that there are no unused intermediate registers. @W:CL177 : coreresetp.v(1503) | Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(1078) | Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(1078) | Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(1078) | Sharing sequential element sdif0_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(1078) | Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing. @W:CL190 : coreresetp.v(1548) | Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : coreresetp.v(1204) | Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1548) | Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(1548) | Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(868) | Pruning unused register sm2_areset_n_q2. Make sure that there are no unused intermediate registers. @W:CL169 : coreresetp.v(868) | Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers. @N:CG364 : osc_comps.v(51) | Synthesizing module RCOSC_25_50MHZ_FAB in library work. @N:CG364 : osc_comps.v(11) | Synthesizing module RCOSC_25_50MHZ in library work. @N:CG364 : FlashFreeze_SB_FABOSC_0_OSC.v(5) | Synthesizing module FlashFreeze_SB_FABOSC_0_OSC in library work. @N:CG364 : smartfusion2.v(268) | Synthesizing module INBUF in library work. @N:CG364 : smartfusion2.v(280) | Synthesizing module TRIBUFF in library work. @N:CG364 : FlashFreeze_SB_MSS_syn.v(5) | Synthesizing module MSS_075 in library work. @N:CG364 : FlashFreeze_SB_MSS.v(9) | Synthesizing module FlashFreeze_SB_MSS in library work. @N:CG364 : smartfusion2.v(186) | Synthesizing module MX2 in library work. @N:CG364 : smartfusion2.v(718) | Synthesizing module SYSRESET in library work. @N:CG364 : FlashFreeze_SB.v(9) | Synthesizing module FlashFreeze_SB in library work. @N:CG364 : mem_apb_wrp.v(19) | Synthesizing module mem_apb_wrp in library work. DATA_WIDTH=32'b00000000000000000000000000001000 ADDR_WIDTH=32'b00000000000000000000000000001000 Generated name = mem_apb_wrp_8s_8s @N:CG364 : mux_blk.v(19) | Synthesizing module mux_blk in library work. @N:CG364 : smartfusion2.v(382) | Synthesizing module RAM1K18 in library work. @N:CG364 : RAM_with_wrapper_SRAM_64x8_0_TPSRAM.v(5) | Synthesizing module RAM_with_wrapper_SRAM_64x8_0_TPSRAM in library work. @N:CG364 : RAM_with_wrapper.v(9) | Synthesizing module RAM_with_wrapper in library work. @N:CG364 : FlashFreeze_SB_top.v(9) | Synthesizing module FlashFreeze_SB_top in library work. @N:CL201 : mem_apb_wrp.v(78) | Trying to extract state machine for register fsm. Extracted state machine for register fsm State machine has 4 reachable states with original encodings of: 00 01 10 11 @N:CL159 : mem_apb_wrp.v(40) | Input PENABLE is unused. @W:CL157 : FlashFreeze_SB_FABOSC_0_OSC.v(17) | *Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : FlashFreeze_SB_FABOSC_0_OSC.v(18) | *Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : FlashFreeze_SB_FABOSC_0_OSC.v(19) | *Output XTLOSC_CCC has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @W:CL157 : FlashFreeze_SB_FABOSC_0_OSC.v(20) | *Output XTLOSC_O2F has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the output. @N:CL159 : FlashFreeze_SB_FABOSC_0_OSC.v(14) | Input XTL is unused. @W:CL177 : coreresetp.v(1078) | Sharing sequential element sdif0_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(1078) | Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(1078) | Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : coreresetp.v(1078) | Sharing sequential element sdif3_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing. @N:CL201 : coreresetp.v(1480) | Trying to extract state machine for register sdif3_state. Extracted state machine for register sdif3_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1415) | Trying to extract state machine for register sdif2_state. Extracted state machine for register sdif2_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1350) | Trying to extract state machine for register sdif1_state. Extracted state machine for register sdif1_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1285) | Trying to extract state machine for register sdif0_state. Extracted state machine for register sdif0_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @N:CL201 : coreresetp.v(1204) | Trying to extract state machine for register sm0_state. Extracted state machine for register sm0_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @N:CL159 : coreresetp.v(29) | Input CLK_LTSSM is unused. @N:CL159 : coreresetp.v(67) | Input FPLL_LOCK is unused. @N:CL159 : coreresetp.v(70) | Input SDIF0_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(79) | Input SDIF1_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(83) | Input SDIF2_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(87) | Input SDIF3_SPLL_LOCK is unused. @N:CL159 : coreresetp.v(101) | Input SDIF0_PSEL is unused. @N:CL159 : coreresetp.v(102) | Input SDIF0_PWRITE is unused. @N:CL159 : coreresetp.v(103) | Input SDIF0_PRDATA is unused. @N:CL159 : coreresetp.v(104) | Input SDIF1_PSEL is unused. @N:CL159 : coreresetp.v(105) | Input SDIF1_PWRITE is unused. @N:CL159 : coreresetp.v(106) | Input SDIF1_PRDATA is unused. @N:CL159 : coreresetp.v(107) | Input SDIF2_PSEL is unused. @N:CL159 : coreresetp.v(108) | Input SDIF2_PWRITE is unused. @N:CL159 : coreresetp.v(109) | Input SDIF2_PRDATA is unused. @N:CL159 : coreresetp.v(110) | Input SDIF3_PSEL is unused. @N:CL159 : coreresetp.v(111) | Input SDIF3_PWRITE is unused. @N:CL159 : coreresetp.v(112) | Input SDIF3_PRDATA is unused. @N:CL159 : coreresetp.v(118) | Input SOFT_EXT_RESET_OUT is unused. @N:CL159 : coreresetp.v(119) | Input SOFT_RESET_F2M is unused. @N:CL159 : coreresetp.v(120) | Input SOFT_M3_RESET is unused. @N:CL159 : coreresetp.v(121) | Input SOFT_MDDR_DDR_AXI_S_CORE_RESET is unused. @N:CL159 : coreresetp.v(122) | Input SOFT_FDDR_CORE_RESET is unused. @N:CL159 : coreresetp.v(123) | Input SOFT_SDIF0_PHY_RESET is unused. @N:CL159 : coreresetp.v(124) | Input SOFT_SDIF0_CORE_RESET is unused. @N:CL159 : coreresetp.v(125) | Input SOFT_SDIF1_PHY_RESET is unused. @N:CL159 : coreresetp.v(126) | Input SOFT_SDIF1_CORE_RESET is unused. @N:CL159 : coreresetp.v(127) | Input SOFT_SDIF2_PHY_RESET is unused. @N:CL159 : coreresetp.v(128) | Input SOFT_SDIF2_CORE_RESET is unused. @N:CL159 : coreresetp.v(129) | Input SOFT_SDIF3_PHY_RESET is unused. @N:CL159 : coreresetp.v(130) | Input SOFT_SDIF3_CORE_RESET is unused. @N:CL159 : coreresetp.v(134) | Input SOFT_SDIF0_0_CORE_RESET is unused. @N:CL159 : coreresetp.v(135) | Input SOFT_SDIF0_1_CORE_RESET is unused. @W:CL247 : coreahblite.v(120) | Input port bit 0 of HTRANS_M0[1:0] is unused @W:CL247 : coreahblite.v(131) | Input port bit 0 of HTRANS_M1[1:0] is unused @W:CL247 : coreahblite.v(142) | Input port bit 0 of HTRANS_M2[1:0] is unused @W:CL247 : coreahblite.v(153) | Input port bit 0 of HTRANS_M3[1:0] is unused @W:CL247 : coreahblite.v(163) | Input port bit 1 of HRESP_S0[1:0] is unused @W:CL247 : coreahblite.v(176) | Input port bit 1 of HRESP_S1[1:0] is unused @W:CL247 : coreahblite.v(189) | Input port bit 1 of HRESP_S2[1:0] is unused @W:CL247 : coreahblite.v(202) | Input port bit 1 of HRESP_S3[1:0] is unused @W:CL247 : coreahblite.v(215) | Input port bit 1 of HRESP_S4[1:0] is unused @W:CL247 : coreahblite.v(228) | Input port bit 1 of HRESP_S5[1:0] is unused @W:CL247 : coreahblite.v(241) | Input port bit 1 of HRESP_S6[1:0] is unused @W:CL247 : coreahblite.v(254) | Input port bit 1 of HRESP_S7[1:0] is unused @W:CL247 : coreahblite.v(267) | Input port bit 1 of HRESP_S8[1:0] is unused @W:CL247 : coreahblite.v(280) | Input port bit 1 of HRESP_S9[1:0] is unused @W:CL247 : coreahblite.v(293) | Input port bit 1 of HRESP_S10[1:0] is unused @W:CL247 : coreahblite.v(306) | Input port bit 1 of HRESP_S11[1:0] is unused @W:CL247 : coreahblite.v(319) | Input port bit 1 of HRESP_S12[1:0] is unused @W:CL247 : coreahblite.v(332) | Input port bit 1 of HRESP_S13[1:0] is unused @W:CL247 : coreahblite.v(345) | Input port bit 1 of HRESP_S14[1:0] is unused @W:CL247 : coreahblite.v(358) | Input port bit 1 of HRESP_S15[1:0] is unused @W:CL247 : coreahblite.v(371) | Input port bit 1 of HRESP_S16[1:0] is unused @N:CL159 : coreahblite.v(123) | Input HBURST_M0 is unused. @N:CL159 : coreahblite.v(124) | Input HPROT_M0 is unused. @N:CL159 : coreahblite.v(134) | Input HBURST_M1 is unused. @N:CL159 : coreahblite.v(135) | Input HPROT_M1 is unused. @N:CL159 : coreahblite.v(145) | Input HBURST_M2 is unused. @N:CL159 : coreahblite.v(146) | Input HPROT_M2 is unused. @N:CL159 : coreahblite.v(156) | Input HBURST_M3 is unused. @N:CL159 : coreahblite.v(157) | Input HPROT_M3 is unused. @N:CL159 : coreahblite_matrix4x16.v(51) | Input HWDATA_M1 is unused. @N:CL159 : coreahblite_matrix4x16.v(60) | Input HWDATA_M2 is unused. @N:CL159 : coreahblite_matrix4x16.v(69) | Input HWDATA_M3 is unused. @N:CL159 : coreahblite_matrix4x16.v(84) | Input HRDATA_S1 is unused. @N:CL159 : coreahblite_matrix4x16.v(85) | Input HREADYOUT_S1 is unused. @N:CL159 : coreahblite_matrix4x16.v(86) | Input HRESP_S1 is unused. @N:CL159 : coreahblite_matrix4x16.v(95) | Input HRDATA_S2 is unused. @N:CL159 : coreahblite_matrix4x16.v(96) | Input HREADYOUT_S2 is unused. @N:CL159 : coreahblite_matrix4x16.v(97) | Input HRESP_S2 is unused. @N:CL159 : coreahblite_matrix4x16.v(106) | Input HRDATA_S3 is unused. @N:CL159 : coreahblite_matrix4x16.v(107) | Input HREADYOUT_S3 is unused. @N:CL159 : coreahblite_matrix4x16.v(108) | Input HRESP_S3 is unused. @N:CL159 : coreahblite_matrix4x16.v(117) | Input HRDATA_S4 is unused. @N:CL159 : coreahblite_matrix4x16.v(118) | Input HREADYOUT_S4 is unused. @N:CL159 : coreahblite_matrix4x16.v(119) | Input HRESP_S4 is unused. @N:CL159 : coreahblite_matrix4x16.v(128) | Input HRDATA_S5 is unused. @N:CL159 : coreahblite_matrix4x16.v(129) | Input HREADYOUT_S5 is unused. @N:CL159 : coreahblite_matrix4x16.v(130) | Input HRESP_S5 is unused. @N:CL159 : coreahblite_matrix4x16.v(139) | Input HRDATA_S6 is unused. @N:CL159 : coreahblite_matrix4x16.v(140) | Input HREADYOUT_S6 is unused. @N:CL159 : coreahblite_matrix4x16.v(141) | Input HRESP_S6 is unused. @N:CL159 : coreahblite_matrix4x16.v(150) | Input HRDATA_S7 is unused. @N:CL159 : coreahblite_matrix4x16.v(151) | Input HREADYOUT_S7 is unused. @N:CL159 : coreahblite_matrix4x16.v(152) | Input HRESP_S7 is unused. @N:CL159 : coreahblite_matrix4x16.v(161) | Input HRDATA_S8 is unused. @N:CL159 : coreahblite_matrix4x16.v(162) | Input HREADYOUT_S8 is unused. @N:CL159 : coreahblite_matrix4x16.v(163) | Input HRESP_S8 is unused. @N:CL159 : coreahblite_matrix4x16.v(172) | Input HRDATA_S9 is unused. @N:CL159 : coreahblite_matrix4x16.v(173) | Input HREADYOUT_S9 is unused. @N:CL159 : coreahblite_matrix4x16.v(174) | Input HRESP_S9 is unused. @N:CL159 : coreahblite_matrix4x16.v(183) | Input HRDATA_S10 is unused. @N:CL159 : coreahblite_matrix4x16.v(184) | Input HREADYOUT_S10 is unused. @N:CL159 : coreahblite_matrix4x16.v(185) | Input HRESP_S10 is unused. @N:CL159 : coreahblite_matrix4x16.v(194) | Input HRDATA_S11 is unused. @N:CL159 : coreahblite_matrix4x16.v(195) | Input HREADYOUT_S11 is unused. @N:CL159 : coreahblite_matrix4x16.v(196) | Input HRESP_S11 is unused. @N:CL159 : coreahblite_matrix4x16.v(205) | Input HRDATA_S12 is unused. @N:CL159 : coreahblite_matrix4x16.v(206) | Input HREADYOUT_S12 is unused. @N:CL159 : coreahblite_matrix4x16.v(207) | Input HRESP_S12 is unused. @N:CL159 : coreahblite_matrix4x16.v(216) | Input HRDATA_S13 is unused. @N:CL159 : coreahblite_matrix4x16.v(217) | Input HREADYOUT_S13 is unused. @N:CL159 : coreahblite_matrix4x16.v(218) | Input HRESP_S13 is unused. @N:CL159 : coreahblite_matrix4x16.v(227) | Input HRDATA_S14 is unused. @N:CL159 : coreahblite_matrix4x16.v(228) | Input HREADYOUT_S14 is unused. @N:CL159 : coreahblite_matrix4x16.v(229) | Input HRESP_S14 is unused. @N:CL159 : coreahblite_matrix4x16.v(238) | Input HRDATA_S15 is unused. @N:CL159 : coreahblite_matrix4x16.v(239) | Input HREADYOUT_S15 is unused. @N:CL159 : coreahblite_matrix4x16.v(240) | Input HRESP_S15 is unused. @N:CL159 : coreahblite_matrix4x16.v(249) | Input HRDATA_S16 is unused. @N:CL159 : coreahblite_matrix4x16.v(250) | Input HREADYOUT_S16 is unused. @N:CL159 : coreahblite_matrix4x16.v(251) | Input HRESP_S16 is unused. @N:CL201 : coreahblite_slavearbiter.v(449) | Trying to extract state machine for register arbRegSMCurrentState. Extracted state machine for register arbRegSMCurrentState State machine has 16 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 @N:CL159 : coreahblite_masterstage.v(42) | Input SDATAREADY is unused. @N:CL159 : coreahblite_masterstage.v(43) | Input SHRESP is unused. @N:CL159 : coreahblite_masterstage.v(52) | Input HRDATA_S0 is unused. @N:CL159 : coreahblite_masterstage.v(53) | Input HREADYOUT_S0 is unused. @N:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused. @N:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused. @N:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S2 is unused. @N:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S2 is unused. @N:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S3 is unused. @N:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S3 is unused. @N:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused. @N:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused. @N:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S5 is unused. @N:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S5 is unused. @N:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused. @N:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused. @N:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused. @N:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused. @N:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused. @N:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused. @N:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused. @N:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused. @N:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused. @N:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused. @N:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused. @N:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused. @N:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused. @N:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S12 is unused. @N:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S13 is unused. @N:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S13 is unused. @N:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S14 is unused. @N:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S14 is unused. @N:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S15 is unused. @N:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S15 is unused. @N:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S16 is unused. @N:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S16 is unused. @W:CL246 : coreahblite_masterstage.v(42) | Input port bits 16 to 1 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : coreahblite_masterstage.v(43) | Input port bits 16 to 1 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size. @N:CL159 : coreahblite_masterstage.v(54) | Input HRDATA_S1 is unused. @N:CL159 : coreahblite_masterstage.v(55) | Input HREADYOUT_S1 is unused. @N:CL159 : coreahblite_masterstage.v(56) | Input HRDATA_S2 is unused. @N:CL159 : coreahblite_masterstage.v(57) | Input HREADYOUT_S2 is unused. @N:CL159 : coreahblite_masterstage.v(58) | Input HRDATA_S3 is unused. @N:CL159 : coreahblite_masterstage.v(59) | Input HREADYOUT_S3 is unused. @N:CL159 : coreahblite_masterstage.v(60) | Input HRDATA_S4 is unused. @N:CL159 : coreahblite_masterstage.v(61) | Input HREADYOUT_S4 is unused. @N:CL159 : coreahblite_masterstage.v(62) | Input HRDATA_S5 is unused. @N:CL159 : coreahblite_masterstage.v(63) | Input HREADYOUT_S5 is unused. @N:CL159 : coreahblite_masterstage.v(64) | Input HRDATA_S6 is unused. @N:CL159 : coreahblite_masterstage.v(65) | Input HREADYOUT_S6 is unused. @N:CL159 : coreahblite_masterstage.v(66) | Input HRDATA_S7 is unused. @N:CL159 : coreahblite_masterstage.v(67) | Input HREADYOUT_S7 is unused. @N:CL159 : coreahblite_masterstage.v(68) | Input HRDATA_S8 is unused. @N:CL159 : coreahblite_masterstage.v(69) | Input HREADYOUT_S8 is unused. @N:CL159 : coreahblite_masterstage.v(70) | Input HRDATA_S9 is unused. @N:CL159 : coreahblite_masterstage.v(71) | Input HREADYOUT_S9 is unused. @N:CL159 : coreahblite_masterstage.v(72) | Input HRDATA_S10 is unused. @N:CL159 : coreahblite_masterstage.v(73) | Input HREADYOUT_S10 is unused. @N:CL159 : coreahblite_masterstage.v(74) | Input HRDATA_S11 is unused. @N:CL159 : coreahblite_masterstage.v(75) | Input HREADYOUT_S11 is unused. @N:CL159 : coreahblite_masterstage.v(76) | Input HRDATA_S12 is unused. @N:CL159 : coreahblite_masterstage.v(77) | Input HREADYOUT_S12 is unused. @N:CL159 : coreahblite_masterstage.v(78) | Input HRDATA_S13 is unused. @N:CL159 : coreahblite_masterstage.v(79) | Input HREADYOUT_S13 is unused. @N:CL159 : coreahblite_masterstage.v(80) | Input HRDATA_S14 is unused. @N:CL159 : coreahblite_masterstage.v(81) | Input HREADYOUT_S14 is unused. @N:CL159 : coreahblite_masterstage.v(82) | Input HRDATA_S15 is unused. @N:CL159 : coreahblite_masterstage.v(83) | Input HREADYOUT_S15 is unused. @N:CL159 : coreahblite_masterstage.v(84) | Input HRDATA_S16 is unused. @N:CL159 : coreahblite_masterstage.v(85) | Input HREADYOUT_S16 is unused. @N:CL159 : coreapb3.v(72) | Input IADDR is unused. @N:CL159 : coreapb3.v(73) | Input PRESETN is unused. @N:CL159 : coreapb3.v(74) | Input PCLK is unused. @N:CL159 : coreapb3.v(105) | Input PRDATAS1 is unused. @N:CL159 : coreapb3.v(106) | Input PRDATAS2 is unused. @N:CL159 : coreapb3.v(107) | Input PRDATAS3 is unused. @N:CL159 : coreapb3.v(108) | Input PRDATAS4 is unused. @N:CL159 : coreapb3.v(109) | Input PRDATAS5 is unused. @N:CL159 : coreapb3.v(110) | Input PRDATAS6 is unused. @N:CL159 : coreapb3.v(111) | Input PRDATAS7 is unused. @N:CL159 : coreapb3.v(112) | Input PRDATAS8 is unused. @N:CL159 : coreapb3.v(113) | Input PRDATAS9 is unused. @N:CL159 : coreapb3.v(114) | Input PRDATAS10 is unused. @N:CL159 : coreapb3.v(115) | Input PRDATAS11 is unused. @N:CL159 : coreapb3.v(116) | Input PRDATAS12 is unused. @N:CL159 : coreapb3.v(117) | Input PRDATAS13 is unused. @N:CL159 : coreapb3.v(118) | Input PRDATAS14 is unused. @N:CL159 : coreapb3.v(119) | Input PRDATAS15 is unused. @N:CL159 : coreapb3.v(122) | Input PREADYS1 is unused. @N:CL159 : coreapb3.v(123) | Input PREADYS2 is unused. @N:CL159 : coreapb3.v(124) | Input PREADYS3 is unused. @N:CL159 : coreapb3.v(125) | Input PREADYS4 is unused. @N:CL159 : coreapb3.v(126) | Input PREADYS5 is unused. @N:CL159 : coreapb3.v(127) | Input PREADYS6 is unused. @N:CL159 : coreapb3.v(128) | Input PREADYS7 is unused. @N:CL159 : coreapb3.v(129) | Input PREADYS8 is unused. @N:CL159 : coreapb3.v(130) | Input PREADYS9 is unused. @N:CL159 : coreapb3.v(131) | Input PREADYS10 is unused. @N:CL159 : coreapb3.v(132) | Input PREADYS11 is unused. @N:CL159 : coreapb3.v(133) | Input PREADYS12 is unused. @N:CL159 : coreapb3.v(134) | Input PREADYS13 is unused. @N:CL159 : coreapb3.v(135) | Input PREADYS14 is unused. @N:CL159 : coreapb3.v(136) | Input PREADYS15 is unused. @N:CL159 : coreapb3.v(139) | Input PSLVERRS1 is unused. @N:CL159 : coreapb3.v(140) | Input PSLVERRS2 is unused. @N:CL159 : coreapb3.v(141) | Input PSLVERRS3 is unused. @N:CL159 : coreapb3.v(142) | Input PSLVERRS4 is unused. @N:CL159 : coreapb3.v(143) | Input PSLVERRS5 is unused. @N:CL159 : coreapb3.v(144) | Input PSLVERRS6 is unused. @N:CL159 : coreapb3.v(145) | Input PSLVERRS7 is unused. @N:CL159 : coreapb3.v(146) | Input PSLVERRS8 is unused. @N:CL159 : coreapb3.v(147) | Input PSLVERRS9 is unused. @N:CL159 : coreapb3.v(148) | Input PSLVERRS10 is unused. @N:CL159 : coreapb3.v(149) | Input PSLVERRS11 is unused. @N:CL159 : coreapb3.v(150) | Input PSLVERRS12 is unused. @N:CL159 : coreapb3.v(151) | Input PSLVERRS13 is unused. @N:CL159 : coreapb3.v(152) | Input PSLVERRS14 is unused. @N:CL159 : coreapb3.v(153) | Input PSLVERRS15 is unused. @W:CL247 : coreahbtoapb3.v(40) | Input port bit 0 of HTRANS[1:0] is unused @N:CL201 : coreahbtoapb3_penablescheduler.v(196) | Trying to extract state machine for register CAHBtoAPB3lIl. Extracted state machine for register CAHBtoAPB3lIl State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL201 : coreahbtoapb3_ahbtoapbsm.v(690) | Trying to extract state machine for register CAHBtoAPB3IOI. Extracted state machine for register CAHBtoAPB3IOI State machine has 5 reachable states with original encodings of: 000 001 010 011 100 At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 87MB peak: 89MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Mar 17 14:26:28 2017 ###########################################################] Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 78MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Mar 17 14:26:28 2017 ###########################################################] @END At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Mar 17 14:26:28 2017 ###########################################################] Synopsys Netlist Linker, version comp2016q3p1, Build 117R, built Nov 17 2016 @N: : | Running in 64-bit mode File D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\synthesis\synwork\FlashFreeze_SB_top_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 84MB peak: 85MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Fri Mar 17 14:26:30 2017 ###########################################################] Pre-mapping Report # Fri Mar 17 14:26:30 2017 Synopsys Generic Technology Pre-mapping, Version map201609actrcp1, Build 005R, Built Jan 25 2017 01:01:33 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.09M-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @A:MF827 : | No constraint file specified. Linked File: FlashFreeze_SB_top_scck.rpt Printing clock summary report in "D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\synthesis\FlashFreeze_SB_top_scck.rpt" file @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 126MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 126MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 126MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 126MB) @W:BN132 : coreahblite_matrix4x16.v(3626) | Removing user instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_16 because it is equivalent to instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_15. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3580) | Removing user instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_15 because it is equivalent to instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_14. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3534) | Removing user instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_14 because it is equivalent to instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_13. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3488) | Removing user instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_13 because it is equivalent to instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_12. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3442) | Removing user instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_12 because it is equivalent to instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_11. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3396) | Removing user instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_11 because it is equivalent to instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3304) | Removing user instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_9 because it is equivalent to instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3258) | Removing user instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_8 because it is equivalent to instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3212) | Removing user instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_7 because it is equivalent to instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreahblite_matrix4x16.v(3166) | Removing user instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_6 because it is equivalent to instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_10. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MO111 : flashfreeze_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.FlashFreeze_SB_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.FlashFreeze_SB_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : flashfreeze_sb_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.FlashFreeze_SB_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.FlashFreeze_SB_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : flashfreeze_sb_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.FlashFreeze_SB_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.FlashFreeze_SB_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : flashfreeze_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.FlashFreeze_SB_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.FlashFreeze_SB_FABOSC_0_OSC(verilog)) has its enable tied to GND. @W:MO129 : coreresetp.v(755) | Sequential instance FlashFreeze_SB_0.CORERESETP_0.SDIF0_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(774) | Sequential instance FlashFreeze_SB_0.CORERESETP_0.SDIF1_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(793) | Sequential instance FlashFreeze_SB_0.CORERESETP_0.SDIF2_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(812) | Sequential instance FlashFreeze_SB_0.CORERESETP_0.SDIF3_PERST_N_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(851) | Sequential instance FlashFreeze_SB_0.CORERESETP_0.sm1_areset_n_q1 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(755) | Sequential instance FlashFreeze_SB_0.CORERESETP_0.SDIF0_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(774) | Sequential instance FlashFreeze_SB_0.CORERESETP_0.SDIF1_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(793) | Sequential instance FlashFreeze_SB_0.CORERESETP_0.SDIF2_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(812) | Sequential instance FlashFreeze_SB_0.CORERESETP_0.SDIF3_PERST_N_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(851) | Sequential instance FlashFreeze_SB_0.CORERESETP_0.sm1_areset_n_q2 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(755) | Sequential instance FlashFreeze_SB_0.CORERESETP_0.SDIF0_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(774) | Sequential instance FlashFreeze_SB_0.CORERESETP_0.SDIF1_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(793) | Sequential instance FlashFreeze_SB_0.CORERESETP_0.SDIF2_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(812) | Sequential instance FlashFreeze_SB_0.CORERESETP_0.SDIF3_PERST_N_q3 is reduced to a combinational gate by constant propagation. @W:MO129 : coreresetp.v(1503) | Sequential instance FlashFreeze_SB_0.CORERESETP_0.RESET_N_F2M_int is reduced to a combinational gate by constant propagation. @N:BN115 : coreahblite_masterstage.v(209) | Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_2(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z3_0(verilog) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHTRANS (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_2(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(639) | Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_2(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_1_0(verilog) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(209) | Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_1(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z3_1(verilog) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHTRANS (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(639) | Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_1(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_1_1(verilog) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(209) | Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_0(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z3_2(verilog) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance regHTRANS (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : coreahblite_masterstage.v(639) | Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_0(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_1_2(verilog) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(2703) | Removing instance masterstage_1 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_2_1_0_1_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_2(verilog) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(2767) | Removing instance masterstage_2 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_2_1_0_1_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_1(verilog) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(2831) | Removing instance masterstage_3 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_2_1_0_1_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_2_1_0_0s_0_1_0_0(verilog) because it does not drive other instances. @N:BN115 : coreahblite_matrix4x16.v(2936) | Removing instance slavestage_1 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_2_1_0_1_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_0(verilog) because it does not drive other instances. @N:BN362 : coreresetp.v(1204) | Removing sequential instance DDR_READY_int (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1204) | Removing sequential instance SDIF_READY_int (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1204) | Removing sequential instance SDIF_RELEASED_int (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1204) | Removing sequential instance FDDR_CORE_RESET_N_int (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1285) | Removing sequential instance SDIF0_PHY_RESET_N_int (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1285) | Removing sequential instance SDIF0_CORE_RESET_N_0 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1350) | Removing sequential instance SDIF1_PHY_RESET_N_int (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1350) | Removing sequential instance SDIF1_CORE_RESET_N_0 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1415) | Removing sequential instance SDIF2_PHY_RESET_N_int (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1415) | Removing sequential instance SDIF2_CORE_RESET_N_0 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1480) | Removing sequential instance SDIF3_PHY_RESET_N_int (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1480) | Removing sequential instance SDIF3_CORE_RESET_N_0 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : mem_apb_wrp.v(78) | Removing sequential instance INT_OUT (in view: work.mem_apb_wrp_8s_8s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance masterDataInProg[3:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1285) | Removing sequential instance sdif0_state[3:0] (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1350) | Removing sequential instance sdif1_state[3:0] (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1415) | Removing sequential instance sdif2_state[3:0] (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(1480) | Removing sequential instance sdif3_state[3:0] (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN115 : coreahblite_slavestage.v(87) | Removing instance slave_arbiter (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_0(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog) because it does not drive other instances. @N:BN362 : coreresetp.v(885) | Removing sequential instance sdif0_areset_n_q2 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(902) | Removing sequential instance sdif1_areset_n_q2 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(919) | Removing sequential instance sdif2_areset_n_q2 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(936) | Removing sequential instance sdif3_areset_n_q2 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(885) | Removing sequential instance sdif0_areset_n_q1 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(902) | Removing sequential instance sdif1_areset_n_q1 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(919) | Removing sequential instance sdif2_areset_n_q1 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreresetp.v(936) | Removing sequential instance sdif3_areset_n_q1 (in view: work.CoreResetP_Z6(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_slavearbiter.v(449) | Removing sequential instance arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_1(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. syn_allowed_resources : blockrams=109 set on top level netlist FlashFreeze_SB_top Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 148MB peak: 150MB) Clock Summary ***************** Start Requested Requested Clock Clock Clock Clock Frequency Period Type Group Load ---------------------------------------------------------------------------------------------------------------------------------------- FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_0 298 FlashFreeze_SB_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_1 15 System 100.0 MHz 10.000 system system_clkgroup 0 ======================================================================================================================================== @W:MT530 : cnt34.v(13) | Found inferred clock FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock which controls 298 sequential elements including cnt34_0.CNT[33:0]. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : coreresetp.v(1024) | Found inferred clock FlashFreeze_SB_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock which controls 15 sequential elements including FlashFreeze_SB_0.CORERESETP_0.sdif3_areset_n_rcosc_q2. This clock has no specified timing constraint which may adversely impact design performance. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\synthesis\FlashFreeze_SB_top.sap. Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 150MB) Encoding state machine CAHBtoAPB3IOI[4:0] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3O_0s_0_1_0_1_2_3_4(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 Encoding state machine CAHBtoAPB3lIl[2:0] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3OIl_0s_0_1_2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_0(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z6(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine fsm[3:0] (in view: work.mem_apb_wrp_8s_8s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : mem_apb_wrp.v(78) | There are no possible illegal states for state machine fsm[3:0] (in view: work.mem_apb_wrp_8s_8s(verilog)); safe FSM implementation is not required. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3OOl[8] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3OOl[9] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3OOl[10] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3OOl[11] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3OOl[12] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3OOl[13] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3OOl[14] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3OOl[15] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3OOl[16] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3OOl[17] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3OOl[18] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3OOl[19] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3OOl[20] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3OOl[21] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3OOl[22] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3OOl[23] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3OOl[28] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3OOl[29] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3OOl[30] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3OOl[31] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3lOl[8] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3lOl[9] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3lOl[10] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3lOl[11] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3lOl[12] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3lOl[13] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3lOl[14] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3lOl[15] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3lOl[16] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3lOl[17] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3lOl[18] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3lOl[19] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3lOl[20] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3lOl[21] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3lOl[22] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3lOl[23] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3lOl[24] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3lOl[25] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3lOl[26] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3lOl[27] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3lOl[28] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3lOl[29] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3lOl[30] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3lOl[31] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3l1I_0s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. None None Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 147MB peak: 150MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 57MB peak: 150MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Fri Mar 17 14:26:31 2017 ###########################################################] Map & Optimize Report # Fri Mar 17 14:26:31 2017 Synopsys Generic Technology Mapper, Version map201609actrcp1, Build 005R, Built Jan 25 2017 01:01:33 Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Product Version L-2016.09M-2 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB) @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) @N:MO111 : flashfreeze_sb_fabosc_0_osc.v(20) | Tristate driver XTLOSC_O2F (in view: work.FlashFreeze_SB_FABOSC_0_OSC(verilog)) on net XTLOSC_O2F (in view: work.FlashFreeze_SB_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : flashfreeze_sb_fabosc_0_osc.v(19) | Tristate driver XTLOSC_CCC (in view: work.FlashFreeze_SB_FABOSC_0_OSC(verilog)) on net XTLOSC_CCC (in view: work.FlashFreeze_SB_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : flashfreeze_sb_fabosc_0_osc.v(18) | Tristate driver RCOSC_1MHZ_O2F (in view: work.FlashFreeze_SB_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_O2F (in view: work.FlashFreeze_SB_FABOSC_0_OSC(verilog)) has its enable tied to GND. @N:MO111 : flashfreeze_sb_fabosc_0_osc.v(17) | Tristate driver RCOSC_1MHZ_CCC (in view: work.FlashFreeze_SB_FABOSC_0_OSC(verilog)) on net RCOSC_1MHZ_CCC (in view: work.FlashFreeze_SB_FABOSC_0_OSC(verilog)) has its enable tied to GND. @W:BN132 : coreresetp.v(1078) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.sdif3_spll_lock_q1 because it is equivalent to instance FlashFreeze_SB_0.CORERESETP_0.CONFIG2_DONE_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(1061) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.CONFIG2_DONE_q1 because it is equivalent to instance FlashFreeze_SB_0.CORERESETP_0.CONFIG1_DONE_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(1061) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.CONFIG2_DONE_clk_base because it is equivalent to instance FlashFreeze_SB_0.CORERESETP_0.fpll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(1044) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.CONFIG1_DONE_clk_base because it is equivalent to instance FlashFreeze_SB_0.CORERESETP_0.fpll_lock_q2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(990) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.sdif1_areset_n_rcosc_q1 because it is equivalent to instance FlashFreeze_SB_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(1024) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.sdif3_areset_n_rcosc_q1 because it is equivalent to instance FlashFreeze_SB_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(1007) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.sdif2_areset_n_rcosc_q1 because it is equivalent to instance FlashFreeze_SB_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(956) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.sm0_areset_n_rcosc_q1 because it is equivalent to instance FlashFreeze_SB_0.CORERESETP_0.sdif0_areset_n_rcosc_q1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(1007) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.sdif2_areset_n_rcosc_q2 because it is equivalent to instance FlashFreeze_SB_0.CORERESETP_0.sm0_areset_n_rcosc_q2. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreresetp.v(1024) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.sdif3_areset_n_rcosc_q2 because it is equivalent to instance FlashFreeze_SB_0.CORERESETP_0.sm0_areset_n_rcosc_q2. To keep the instance, apply constraint syn_preserve=1 on the instance. Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 141MB) @N:MO231 : cnt34.v(13) | Found counter in view:work.FlashFreeze_SB_top(verilog) instance cnt34_0.CNT[33:0] @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[8] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[9] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[10] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[11] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[12] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[13] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[14] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[15] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[16] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[17] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[18] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[19] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[20] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[21] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[22] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[23] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[28] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[29] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[30] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(146) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3OOl[31] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[8] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[9] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[10] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[11] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[12] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[13] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[14] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[15] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[16] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[17] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[18] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[19] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[20] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[21] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[22] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[23] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[24] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[25] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[26] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[27] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[28] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[29] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[30] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(278) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3lOl[31] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[8] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[9] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[10] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[11] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[12] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[13] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[14] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[15] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[16] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[17] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[18] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[19] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[20] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[21] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[22] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[23] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[28] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[29] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[30] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahbtoapb3_apbaddrdata.v(229) | Removing sequential instance CAHBtoAPB3I0l.CAHBtoAPB3IOl[31] (in view: COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[31] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[30] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[29] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[28] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[27] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[26] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[25] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[24] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[23] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[22] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[21] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[20] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[19] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[18] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[17] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[16] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[15] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[14] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[13] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[12] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[11] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[10] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[9] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahbtoapb3_apbaddrdata.v(353) | Register bit CAHBtoAPB3I0l.HRDATA[8] (in view view:COREAHBTOAPB3_LIB.COREAHBTOAPB3_19s_0s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine CAHBtoAPB3IOI[4:0] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3O_0s_0_1_0_1_2_3_4(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 Encoding state machine CAHBtoAPB3lIl[2:0] (in view: COREAHBTOAPB3_LIB.CAHBtoAPB3OIl_0s_0_1_2(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @W:MO160 : coreahblite_masterstage.v(163) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[2] (in view view:work.FlashFreeze_SB(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_masterstage.v(229) | Register bit CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[16] (in view view:work.FlashFreeze_SB(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_0.masterDataInProg[3] (in view: work.FlashFreeze_SB(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_0.masterDataInProg[2] (in view: work.FlashFreeze_SB(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : coreahblite_slavestage.v(79) | Removing sequential instance CoreAHBLite_0.matrix4x16.slavestage_0.masterDataInProg[1] (in view: work.FlashFreeze_SB(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. Encoding state machine arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_0(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[12] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_0(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[8] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_0(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : coreahblite_slavearbiter.v(449) | Register bit arbRegSMCurrentState[4] (in view view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z4_0(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine sm0_state[6:0] (in view: work.CoreResetP_Z6(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 Encoding state machine fsm[3:0] (in view: work.mem_apb_wrp_8s_8s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : mem_apb_wrp.v(78) | There are no possible illegal states for state machine fsm[3:0] (in view: work.mem_apb_wrp_8s_8s(verilog)); safe FSM implementation is not required. Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB) @N:BN362 : coreresetp.v(1204) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.INIT_DONE_int (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1204) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.sm0_state[6] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[31] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[30] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[29] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[28] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[23] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[22] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[21] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[20] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[19] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[18] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[17] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[16] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[15] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[14] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[13] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[12] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[11] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[10] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[9] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHADDR[8] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[1] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreahblite_masterstage.v(163) | Removing sequential instance FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHSIZE[0] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 142MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 142MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB) @N:BN362 : cnt34.v(13) | Removing sequential instance cnt34_0.CNT[33] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @A:BN291 : cnt34.v(13) | Boundary register cnt34_0.CNT[33] (in view: work.FlashFreeze_SB_top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN362 : cnt34.v(13) | Removing sequential instance cnt34_0.CNT[32] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @A:BN291 : cnt34.v(13) | Boundary register cnt34_0.CNT[32] (in view: work.FlashFreeze_SB_top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN362 : cnt34.v(13) | Removing sequential instance cnt34_0.CNT[31] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @A:BN291 : cnt34.v(13) | Boundary register cnt34_0.CNT[31] (in view: work.FlashFreeze_SB_top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN362 : cnt34.v(13) | Removing sequential instance cnt34_0.CNT[30] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @A:BN291 : cnt34.v(13) | Boundary register cnt34_0.CNT[30] (in view: work.FlashFreeze_SB_top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN362 : cnt34.v(13) | Removing sequential instance cnt34_0.CNT[29] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @A:BN291 : cnt34.v(13) | Boundary register cnt34_0.CNT[29] (in view: work.FlashFreeze_SB_top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN362 : cnt34.v(13) | Removing sequential instance cnt34_0.CNT[28] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @A:BN291 : cnt34.v(13) | Boundary register cnt34_0.CNT[28] (in view: work.FlashFreeze_SB_top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN362 : cnt34.v(13) | Removing sequential instance cnt34_0.CNT[27] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @A:BN291 : cnt34.v(13) | Boundary register cnt34_0.CNT[27] (in view: work.FlashFreeze_SB_top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN362 : coreresetp.v(1728) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.ddr_settled (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @A:BN291 : coreresetp.v(1728) | Boundary register FlashFreeze_SB_0.CORERESETP_0.ddr_settled (in view: work.FlashFreeze_SB_top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN362 : coreresetp.v(1078) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.fpll_lock_q2 (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1044) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.CONFIG1_DONE_q1 (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(973) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.sdif0_areset_n_rcosc_q1 (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(956) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.sm0_areset_n_rcosc_q2 (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(834) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.sm0_areset_n_q2 (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1761) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.ddr_settled_clk_base (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(834) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.sm0_areset_n_q1 (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1761) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.ddr_settled_q1 (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @A:BN291 : coreresetp.v(1761) | Boundary register FlashFreeze_SB_0.CORERESETP_0.ddr_settled_q1 (in view: work.FlashFreeze_SB_top(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN362 : coreresetp.v(1204) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.sm0_state[5] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1204) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.sm0_state[4] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1204) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.sm0_state[3] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1204) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.sm0_state[2] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1204) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.sm0_state[1] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. @N:BN362 : coreresetp.v(1204) | Removing sequential instance FlashFreeze_SB_0.CORERESETP_0.sm0_state[0] (in view: work.FlashFreeze_SB_top(verilog)) because it does not drive other instances. Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 142MB) Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 142MB peak: 144MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:00s -2.04ns 248 / 139 2 0h:00m:00s -2.04ns 241 / 139 3 0h:00m:01s -2.04ns 249 / 139 4 0h:00m:01s -0.84ns 256 / 139 5 0h:00m:01s -0.84ns 255 / 139 @N:FP130 : | Promoting Net FlashFreeze_SB_0_POWER_ON_RESET_N on CLKINT I_198 @N:FP130 : | Promoting Net un1_FlashFreeze_SB_0_1_i_i on CLKINT I_199 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s) 3 gated/generated clock tree(s) driving 142 clock pin(s) of sequential element(s) 0 instances converted, 142 sequential instances remain driven by gated/generated clocks ==================================================================================================== Gated/Generated Clocks ===================================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 RAM_with_wrapper_0.mux_blk_0.wclk CFG3 1 RAM_with_wrapper_0.SRAM_64x8_0.RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0 No gated clock conversion method for cell cell:ACG4.RAM1K18 ClockId0002 RAM_with_wrapper_0.mux_blk_0.rclk CFG3 1 RAM_with_wrapper_0.SRAM_64x8_0.RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0 No gated clock conversion method for cell cell:ACG4.RAM1K18 ClockId0003 FlashFreeze_SB_0.CCC_0.CCC_INST CCC 140 FlashFreeze_SB_0.FlashFreeze_SB_MSS_0.MSS_ADLIB_INST No gated clock conversion method for cell cell:work.MSS_075 ================================================================================================================================================================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 115MB peak: 145MB) Writing Analyst data base D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\synthesis\synwork\FlashFreeze_SB_top_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 140MB peak: 145MB) Writing EDIF Netlist and constraint files @N:FX1056 : | Writing EDF file: D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\synthesis\FlashFreeze_SB_top.edn @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF L-2016.09M-2 Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 141MB peak: 145MB) Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 141MB peak: 145MB) @W:MT246 : flashfreeze_sb_top.v(447) | Blackbox FLASH_FREEZE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : flashfreeze_sb_ccc_0_fccc.v(24) | Blackbox CCC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock FlashFreeze_SB_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:FlashFreeze_SB_0.FABOSC_0.RCOSC_25_50MHZ_CCC" @W:MT420 : | Found inferred clock FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock with period 10.00ns. Please declare a user-defined clock on object "n:FlashFreeze_SB_0.CCC_0.GL0_net" ##### START OF TIMING REPORT #####[ # Timing Report written on Fri Mar 17 14:26:33 2017 # Top view: FlashFreeze_SB_top Requested Frequency: 100.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: 0.676 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group -------------------------------------------------------------------------------------------------------------------------------------------------------------------- FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock 100.0 MHz 107.2 MHz 10.000 9.324 0.676 inferred Inferred_clkgroup_0 FlashFreeze_SB_FABOSC_0_OSC|RCOSC_25_50MHZ_CCC_inferred_clock 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_1 System 100.0 MHz 488.5 MHz 10.000 2.047 7.953 system system_clkgroup ==================================================================================================================================================================== @N:MT582 : | Estimated period and frequency not reported for given clock unless the clock has at least one timing path which is not a false or a max delay path and that does not have excessive slack Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ System System | 10.000 7.953 | No paths - | No paths - | No paths - System FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock | 10.000 8.398 | No paths - | No paths - | No paths - FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock | 10.000 0.676 | No paths - | No paths - | No paths - ========================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- FlashFreeze_SB_0.FlashFreeze_SB_MSS_0.MSS_ADLIB_INST FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_ADDR[24] FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[24] 3.023 0.676 FlashFreeze_SB_0.FlashFreeze_SB_MSS_0.MSS_ADLIB_INST FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_ADDR[26] FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[26] 3.053 1.307 FlashFreeze_SB_0.FlashFreeze_SB_MSS_0.MSS_ADLIB_INST FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_ADDR[27] FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[27] 3.030 1.402 FlashFreeze_SB_0.FlashFreeze_SB_MSS_0.MSS_ADLIB_INST FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_ADDR[25] FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[25] 3.051 1.557 FlashFreeze_SB_0.FlashFreeze_SB_MSS_0.MSS_ADLIB_INST FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock MSS_075 F_HM0_TRANS1 FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS[1] 3.108 1.600 FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[0] FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock SLE Q m0s0DataSel 0.076 3.272 FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[9] FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[9] 0.094 3.454 FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[11] FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[11] 0.094 3.523 FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[12] FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[12] 0.094 3.562 FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.SDATASELInt[7] FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock SLE Q SDATASELInt[7] 0.076 3.591 ========================================================================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------- COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3IOI[1] FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock SLE D CAHBtoAPB3IOI_ns[1] 9.778 0.676 COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3IOI[3] FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock SLE D N_179_mux 9.778 0.676 COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3IOI[4] FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock SLE D N_247_mux 9.778 0.676 COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3IOI[0] FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock SLE D N_177_mux_i 9.778 0.763 COREAHBTOAPB3_0.CAHBtoAPB3I0l.CAHBtoAPB3OOl[0] FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock SLE D N_205 9.778 0.763 COREAHBTOAPB3_0.CAHBtoAPB3I0l.CAHBtoAPB3OOl[1] FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock SLE D N_204 9.778 0.763 COREAHBTOAPB3_0.CAHBtoAPB3I0l.CAHBtoAPB3OOl[2] FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock SLE D N_203 9.778 0.763 COREAHBTOAPB3_0.CAHBtoAPB3I0l.CAHBtoAPB3OOl[3] FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock SLE D N_202 9.778 0.763 COREAHBTOAPB3_0.CAHBtoAPB3I0l.CAHBtoAPB3OOl[4] FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock SLE D N_201 9.778 0.763 COREAHBTOAPB3_0.CAHBtoAPB3I0l.CAHBtoAPB3OOl[5] FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock SLE D N_200 9.778 0.763 =================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.222 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.778 - Propagation time: 9.102 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 0.676 Number of logic level(s): 6 Starting point: FlashFreeze_SB_0.FlashFreeze_SB_MSS_0.MSS_ADLIB_INST / F_HM0_ADDR[24] Ending point: COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3IOI[1] / D The start point is clocked by FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK_BASE The end point is clocked by FlashFreeze_SB_CCC_0_FCCC|GL0_net_inferred_clock [rising] on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- FlashFreeze_SB_0.FlashFreeze_SB_MSS_0.MSS_ADLIB_INST MSS_075 F_HM0_ADDR[24] Out 3.023 3.023 - FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[24] Net - - 0.977 - 2 FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.PREGATEDHADDR[24] CFG3 B In - 3.999 - FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.PREGATEDHADDR[24] CFG3 Y Out 0.143 4.143 - M0GATEDHADDR[24] Net - - 0.827 - 19 FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHTRANS_RNINS0P CFG4 B In - 4.970 - FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.regHTRANS_RNINS0P CFG4 Y Out 0.125 5.094 - N_132_i_1 Net - - 0.483 - 1 FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.PREGATEDHADDR_RNIQF0C1[25] CFG4 D In - 5.578 - FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.masterstage_0.PREGATEDHADDR_RNIQF0C1[25] CFG4 Y Out 0.250 5.828 - N_132_i Net - - 0.722 - 9 FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_ns_i_a2_0_RNIP4O12[0] CFG4 D In - 6.549 - FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_0.slave_arbiter.arbRegSMCurrentState_ns_i_a2_0_RNIP4O12[0] CFG4 Y Out 0.250 6.800 - masterAddrInProg[0] Net - - 0.876 - 25 COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3IOI_m2_e CFG3 A In - 7.676 - COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3IOI_m2_e CFG3 Y Out 0.076 7.751 - N_250 Net - - 0.929 - 15 COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3IOI_m6_0_m2 CFG4 D In - 8.681 - COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3IOI_m6_0_m2 CFG4 Y Out 0.284 8.964 - CAHBtoAPB3IOI_ns[1] Net - - 0.138 - 1 COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3IOI[1] SLE D In - 9.102 - =========================================================================================================================================================================================== Total path delay (propagation time + setup) of 9.324 is 4.373(46.9%) logic and 4.952(53.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------- FLASH_FREEZE_0 System FLASH_FREEZE FF_DONE FLASH_FREEZE_0_FF_DONE 0.000 7.953 ========================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------ FlashFreeze_SB_0.CCC_0.CCC_INST System CCC PLL_ARST_N FLASH_FREEZE_0_FF_DONE_i 10.000 7.953 FlashFreeze_SB_0.CORERESETP_0.mss_ready_select System SLE EN mss_ready_select4 9.707 8.398 FlashFreeze_SB_0.CORERESETP_0.MSS_HPMS_READY_int System SLE D MSS_HPMS_READY_int_4 9.778 8.416 FlashFreeze_SB_0.CORERESETP_0.mss_ready_state System SLE EN RESET_N_M2F_clk_base 9.707 8.505 ========================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 10.000 - Propagation time: 2.047 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 7.953 Number of logic level(s): 1 Starting point: FLASH_FREEZE_0 / FF_DONE Ending point: FlashFreeze_SB_0.CCC_0.CCC_INST / PLL_ARST_N The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------- FLASH_FREEZE_0 FLASH_FREEZE FF_DONE Out 0.000 0.000 - FLASH_FREEZE_0_FF_DONE Net - - 0.988 - 10 FlashFreeze_SB_0.CCC_0.CCC_INST_RNO CFG1 A In - 0.988 - FlashFreeze_SB_0.CCC_0.CCC_INST_RNO CFG1 Y Out 0.087 1.076 - FLASH_FREEZE_0_FF_DONE_i Net - - 0.971 - 1 FlashFreeze_SB_0.CCC_0.CCC_INST CCC PLL_ARST_N In - 2.047 - ================================================================================================================ Total path delay (propagation time + setup) of 2.047 is 0.087(4.3%) logic and 1.960(95.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied None Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 141MB peak: 145MB) Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 141MB peak: 145MB) --------------------------------------- Resource Usage Report for FlashFreeze_SB_top Mapping to part: m2s090tsfbga484-1 Cell usage: CCC 1 use CLKINT 3 uses FLASH_FREEZE 1 use MSS_075 1 use MX2 1 use RCOSC_25_50MHZ 1 use SYSRESET 1 use CFG1 2 uses CFG2 72 uses CFG3 65 uses CFG4 87 uses Carry cells: ARI1 27 uses - used for arithmetic functions Sequential Cells: SLE 139 uses DSP Blocks: 0 of 84 (0%) I/O ports: 52 I/O primitives: 51 INBUF 30 uses OUTBUF 20 uses TRIBUFF 1 use Global Clock Buffers: 3 of 8 (37%) RAM/ROM usage summary Total Block RAMs (RAM1K18) : 1 of 109 (0%) Total LUTs: 253 Extra resources required for RAM and MACC interface logic during P&R: RAM64x18 Interface Logic : SLEs = 0; LUTs = 0; RAM1K18 Interface Logic : SLEs = 36; LUTs = 36; MACC Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 139 + 0 + 36 + 0 = 175; Total number of LUTs after P&R: 253 + 0 + 36 + 0 = 289; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 32MB peak: 145MB) Process took 0h:00m:02s realtime, 0h:00m:02s cputime # Fri Mar 17 14:26:33 2017 ###########################################################]