#--  Synopsys, Inc.
#--  Version L-2016.09M-2
#--  Project file D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\synthesis\run_options.txt
#--  Written on Fri Mar 17 14:26:27 2017


#project files
add_file -verilog "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/component/work/DIP_SWITCHES/DIP_SWITCHES.v"
add_file -verilog "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/component/Actel/DirectCore/CoreResetP/8.0.103/rtl/vlog/core/coreresetp_pcie_hotreset.v"
add_file -verilog "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/component/Actel/DirectCore/CoreResetP/8.0.103/rtl/vlog/core/coreresetp.v"
add_file -verilog "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/component/work/FlashFreeze_SB/CCC_0/FlashFreeze_SB_CCC_0_FCCC.v"
add_file -verilog "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/component/Actel/SgCore/OSC/2.0.101/osc_comps.v"
add_file -verilog "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/component/work/FlashFreeze_SB/FABOSC_0/FlashFreeze_SB_FABOSC_0_OSC.v"
add_file -verilog "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/component/work/FlashFreeze_SB_MSS/FlashFreeze_SB_MSS_syn.v"
add_file -verilog "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/component/work/FlashFreeze_SB_MSS/FlashFreeze_SB_MSS.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_addrdec.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_defaultslavesm.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_masterstage.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavearbiter.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavestage.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_matrix4x16.v"
add_file -verilog -lib COREAHBLITE_LIB "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite.v"
add_file -verilog "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/component/work/FlashFreeze_SB/FlashFreeze_SB.v"
add_file -verilog "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/component/work/RAM_with_wrapper/SRAM_64x8_0/RAM_with_wrapper_SRAM_64x8_0_TPSRAM.v"
add_file -verilog "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/hdl/mem_apb_wrp.v"
add_file -verilog "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/hdl/mux_blk.v"
add_file -verilog "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/component/work/RAM_with_wrapper/RAM_with_wrapper.v"
add_file -verilog "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/hdl/cnt34.v"
add_file -verilog -lib COREAHBTOAPB3_LIB "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/component/Actel/DirectCore/COREAHBTOAPB3/3.1.100/rtl/vlog/core_obfuscated/coreahbtoapb3_ahbtoapbsm.v"
add_file -verilog -lib COREAHBTOAPB3_LIB "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/component/Actel/DirectCore/COREAHBTOAPB3/3.1.100/rtl/vlog/core_obfuscated/coreahbtoapb3_penablescheduler.v"
add_file -verilog -lib COREAHBTOAPB3_LIB "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/component/Actel/DirectCore/COREAHBTOAPB3/3.1.100/rtl/vlog/core_obfuscated/coreahbtoapb3_apbaddrdata.v"
add_file -verilog -lib COREAHBTOAPB3_LIB "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/component/Actel/DirectCore/COREAHBTOAPB3/3.1.100/rtl/vlog/core_obfuscated/coreahbtoapb3.v"
add_file -verilog -lib COREAPB3_LIB "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3_muxptob3.v"
add_file -verilog -lib COREAPB3_LIB "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3_iaddr_reg.v"
add_file -verilog -lib COREAPB3_LIB "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3.v"
add_file -verilog "D:/11.8/Designs/5_AC400_FF_TP_DONE/m2s_ac400_flashfreeze_liberov11p8_df/M2S_FlashFreeze_AN/component/work/FlashFreeze_SB_top/FlashFreeze_SB_top.v"



#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std v2001

#device options
set_option -technology SmartFusion2
set_option -part M2S090TS
set_option -package FBGA484
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "FlashFreeze_SB_top"

# hdl_compiler_options
set_option -distributed_compile 0

# mapper_without_write_options
set_option -frequency 100.000
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 0
set_option -write_vhdl 0

# actel_options
set_option -rw_check_on_ram 0

# Microsemi G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 12
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -seqshift_to_uram 0
set_option -disable_io_insertion 0
set_option -opcond COMTC
set_option -retiming 0
set_option -report_path 0
set_option -update_models_cp 0
set_option -preserve_registers 0

# NFilter
set_option -no_sequential_opt 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./FlashFreeze_SB_top.edn"
impl -active "synthesis"
