<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<?xml-stylesheet href="rptstyle.xsl" type="text/xsl" ?>
<doc>
<text>SmartTime Version 11.8.0.26</text>
<text>Microsemi Corporation - Microsemi Libero Software Release v11.8 (Version 11.8.0.26)
Date: Thu Mar 16 21:00:06 2017 </text>
<table>
<header>
</header>
<row>
 <cell>Design</cell>
 <cell>FlashFreeze_SB_top</cell>
</row>
<row>
 <cell>Family</cell>
 <cell>SmartFusion2</cell>
</row>
<row>
 <cell>Die</cell>
 <cell>M2S090TS</cell>
</row>
<row>
 <cell>Package</cell>
 <cell>484 FBGA</cell>
</row>
<row>
 <cell>Temperature Range</cell>
 <cell>0 - 85 C</cell>
</row>
<row>
 <cell>Voltage Range</cell>
 <cell>1.14 - 1.26 V</cell>
</row>
<row>
 <cell>Speed Grade</cell>
 <cell>-1</cell>
</row>
</table>
<text></text>
<text></text>
<section>
<name>Coverage Summary</name>
<text></text>
<table>
<header>
 <cell>Type of check</cell>
 <cell>Constrained</cell>
 <cell>UnConstrained</cell>
 <cell>Total</cell>
</header>
<row>
 <cell>Setup</cell>
 <cell>          241</cell>
 <cell>            0</cell>
 <cell>          241</cell>
</row>
<row>
 <cell>Recovery</cell>
 <cell>           49</cell>
 <cell>           90</cell>
 <cell>          139</cell>
</row>
<row>
 <cell>Output Setup</cell>
 <cell>            0</cell>
 <cell>           19</cell>
 <cell>           19</cell>
</row>
<row>
 <cell>Total Setup</cell>
 <cell>          290</cell>
 <cell>          109</cell>
 <cell>          399</cell>
</row>
<separator/>
<row>
 <cell>Hold</cell>
 <cell>          241</cell>
 <cell>            0</cell>
 <cell>          241</cell>
</row>
<row>
 <cell>Removal</cell>
 <cell>           49</cell>
 <cell>           90</cell>
 <cell>          139</cell>
</row>
<row>
 <cell>Output Hold</cell>
 <cell>            0</cell>
 <cell>           19</cell>
 <cell>           19</cell>
</row>
<row>
 <cell>Total Hold</cell>
 <cell>          290</cell>
 <cell>          109</cell>
 <cell>          399</cell>
</row>
</table>
<section>
<name>Clock domain: </name>
<text>FlashFreeze_SB_0/CCC_0/CCC_INST/INST_CCC_IP:GL0</text>
<text></text>
<table>
<header>
 <cell>Type of check</cell>
 <cell>Constrained</cell>
 <cell>UnConstrained</cell>
 <cell>Total</cell>
</header>
<row>
 <cell>Setup</cell>
 <cell>          241</cell>
 <cell>            0</cell>
 <cell>          241</cell>
</row>
<row>
 <cell>Recovery</cell>
 <cell>           49</cell>
 <cell>           90</cell>
 <cell>          139</cell>
</row>
<row>
 <cell>Output Setup</cell>
 <cell>            0</cell>
 <cell>           14</cell>
 <cell>           14</cell>
</row>
<row>
 <cell>Total Setup</cell>
 <cell>          290</cell>
 <cell>          104</cell>
 <cell>          394</cell>
</row>
<separator/>
<row>
 <cell>Hold</cell>
 <cell>          241</cell>
 <cell>            0</cell>
 <cell>          241</cell>
</row>
<row>
 <cell>Removal</cell>
 <cell>           49</cell>
 <cell>           90</cell>
 <cell>          139</cell>
</row>
<row>
 <cell>Output Hold</cell>
 <cell>            0</cell>
 <cell>           14</cell>
 <cell>           14</cell>
</row>
<row>
 <cell>Total Hold</cell>
 <cell>          290</cell>
 <cell>          104</cell>
 <cell>          394</cell>
</row>
</table>
<section>
<name>Enhancement Suggestions</name>
<text></text>
<text> - Max input delay constraint missing on  ports:</text>
<text>   </text>
<list>
 <item>raddr_user[0]</item>
 <item>raddr_user[1]</item>
 <item>raddr_user[2]</item>
 <item>raddr_user[3]</item>
 <item>raddr_user[4]</item>
 <item>raddr_user[5]</item>
 <item>rd_enable_user</item>
 <item>waddr_user[0]</item>
 <item>waddr_user[1]</item>
 <item>waddr_user[2]</item>
 <item>waddr_user[3]</item>
 <item>waddr_user[4]</item>
 <item>waddr_user[5]</item>
 <item>wdata_user[0]</item>
 <item>wdata_user[1]</item>
 <item>wdata_user[2]</item>
 <item>wdata_user[3]</item>
 <item>wdata_user[4]</item>
 <item>wdata_user[5]</item>
 <item>wdata_user[6]</item>
 <item>wdata_user[7]</item>
 <item>wr_enable_user</item>
</list>
<text></text>
<text> - Min input delay constraint missing on  ports:</text>
<text>   </text>
<list>
 <item>raddr_user[0]</item>
 <item>raddr_user[1]</item>
 <item>raddr_user[2]</item>
 <item>raddr_user[3]</item>
 <item>raddr_user[4]</item>
 <item>raddr_user[5]</item>
 <item>rd_enable_user</item>
 <item>waddr_user[0]</item>
 <item>waddr_user[1]</item>
 <item>waddr_user[2]</item>
 <item>waddr_user[3]</item>
 <item>waddr_user[4]</item>
 <item>waddr_user[5]</item>
 <item>wdata_user[0]</item>
 <item>wdata_user[1]</item>
 <item>wdata_user[2]</item>
 <item>wdata_user[3]</item>
 <item>wdata_user[4]</item>
 <item>wdata_user[5]</item>
 <item>wdata_user[6]</item>
 <item>wdata_user[7]</item>
 <item>wr_enable_user</item>
</list>
<text></text>
<text></text>
<text> - Max output delay constraint missing on  ports:</text>
<text>   </text>
<list>
 <item>LED_1</item>
 <item>LED_2</item>
 <item>LED_3</item>
 <item>LED_4</item>
 <item>MMUART_1_TXD</item>
 <item>SEL</item>
 <item>rdata_user[0]</item>
 <item>rdata_user[1]</item>
 <item>rdata_user[2]</item>
 <item>rdata_user[3]</item>
 <item>rdata_user[4]</item>
 <item>rdata_user[5]</item>
 <item>rdata_user[6]</item>
 <item>rdata_user[7]</item>
</list>
<text></text>
<text> - Min output delay constraint missing on  ports:</text>
<text>   </text>
<list>
 <item>LED_1</item>
 <item>LED_2</item>
 <item>LED_3</item>
 <item>LED_4</item>
 <item>MMUART_1_TXD</item>
 <item>SEL</item>
 <item>rdata_user[0]</item>
 <item>rdata_user[1]</item>
 <item>rdata_user[2]</item>
 <item>rdata_user[3]</item>
 <item>rdata_user[4]</item>
 <item>rdata_user[5]</item>
 <item>rdata_user[6]</item>
 <item>rdata_user[7]</item>
</list>
<text></text>
<text></text>
<text> - Recovery uncconstrained for the following pins:</text>
<text>   </text>
<list>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3IOl[0]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3IOl[1]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3IOl[24]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3IOl[25]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3IOl[26]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3IOl[27]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3IOl[2]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3IOl[3]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3IOl[4]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3IOl[5]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3IOl[6]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3IOl[7]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3OOl[0]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3OOl[1]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3OOl[24]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3OOl[25]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3OOl[26]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3OOl[27]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3OOl[2]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3OOl[3]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3OOl[4]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3OOl[5]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3OOl[6]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3OOl[7]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3lOl[0]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3lOl[1]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3lOl[2]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3lOl[3]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3lOl[4]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3lOl[5]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3lOl[6]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3lOl[7]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/HRDATA[0]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/HRDATA[1]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/HRDATA[2]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/HRDATA[3]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/HRDATA[4]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/HRDATA[5]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/HRDATA[6]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/HRDATA[7]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3O0l/CAHBtoAPB3lIl[0]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3O0l/CAHBtoAPB3lIl[1]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3lll/CAHBtoAPB3III:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3lll/CAHBtoAPB3IOI[0]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3lll/CAHBtoAPB3IOI[1]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3lll/CAHBtoAPB3IOI[2]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3lll/CAHBtoAPB3IOI[3]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3lll/CAHBtoAPB3IOI[4]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3lll/CAHBtoAPB3lII:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3lll/HREADYOUT:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3lll/PSEL:ALn</item>
 <item>FlashFreeze_SB_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_q1:ALn</item>
 <item>FlashFreeze_SB_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_q2:ALn</item>
 <item>FlashFreeze_SB_0/CORERESETP_0/POWER_ON_RESET_N_q1:ALn</item>
 <item>FlashFreeze_SB_0/CORERESETP_0/POWER_ON_RESET_N_q2:ALn</item>
 <item>FlashFreeze_SB_0/CORERESETP_0/RESET_N_M2F_q1:ALn</item>
 <item>FlashFreeze_SB_0/CORERESETP_0/RESET_N_M2F_q2:ALn</item>
 <item>RAM_with_wrapper_0/mem_apb_wrp_0/PREADY:ALn</item>
 <item>RAM_with_wrapper_0/mem_apb_wrp_0/SEL:ALn</item>
 <item>RAM_with_wrapper_0/mem_apb_wrp_0/fsm[0]:ALn</item>
 <item>RAM_with_wrapper_0/mem_apb_wrp_0/fsm[1]:ALn</item>
 <item>RAM_with_wrapper_0/mem_apb_wrp_0/rd_enable:ALn</item>
 <item>RAM_with_wrapper_0/mem_apb_wrp_0/wr_enable:ALn</item>
 <item>cnt34_0/CNT[0]:ALn</item>
 <item>cnt34_0/CNT[10]:ALn</item>
 <item>cnt34_0/CNT[11]:ALn</item>
 <item>cnt34_0/CNT[12]:ALn</item>
 <item>cnt34_0/CNT[13]:ALn</item>
 <item>cnt34_0/CNT[14]:ALn</item>
 <item>cnt34_0/CNT[15]:ALn</item>
 <item>cnt34_0/CNT[16]:ALn</item>
 <item>cnt34_0/CNT[17]:ALn</item>
 <item>cnt34_0/CNT[18]:ALn</item>
 <item>cnt34_0/CNT[19]:ALn</item>
 <item>cnt34_0/CNT[1]:ALn</item>
 <item>cnt34_0/CNT[20]:ALn</item>
 <item>cnt34_0/CNT[21]:ALn</item>
 <item>cnt34_0/CNT[22]:ALn</item>
 <item>cnt34_0/CNT[23]:ALn</item>
 <item>cnt34_0/CNT[24]:ALn</item>
 <item>cnt34_0/CNT[25]:ALn</item>
 <item>cnt34_0/CNT[26]:ALn</item>
 <item>cnt34_0/CNT[2]:ALn</item>
 <item>cnt34_0/CNT[3]:ALn</item>
 <item>cnt34_0/CNT[4]:ALn</item>
 <item>cnt34_0/CNT[5]:ALn</item>
 <item>cnt34_0/CNT[6]:ALn</item>
 <item>cnt34_0/CNT[7]:ALn</item>
 <item>cnt34_0/CNT[8]:ALn</item>
 <item>cnt34_0/CNT[9]:ALn</item>
</list>
<text></text>
<text> - Removal uncconstrained for the following pins:</text>
<text>   </text>
<list>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3IOl[0]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3IOl[1]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3IOl[24]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3IOl[25]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3IOl[26]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3IOl[27]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3IOl[2]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3IOl[3]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3IOl[4]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3IOl[5]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3IOl[6]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3IOl[7]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3OOl[0]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3OOl[1]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3OOl[24]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3OOl[25]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3OOl[26]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3OOl[27]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3OOl[2]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3OOl[3]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3OOl[4]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3OOl[5]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3OOl[6]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3OOl[7]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3lOl[0]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3lOl[1]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3lOl[2]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3lOl[3]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3lOl[4]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3lOl[5]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3lOl[6]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/CAHBtoAPB3lOl[7]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/HRDATA[0]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/HRDATA[1]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/HRDATA[2]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/HRDATA[3]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/HRDATA[4]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/HRDATA[5]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/HRDATA[6]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3I0l/HRDATA[7]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3O0l/CAHBtoAPB3lIl[0]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3O0l/CAHBtoAPB3lIl[1]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3lll/CAHBtoAPB3III:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3lll/CAHBtoAPB3IOI[0]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3lll/CAHBtoAPB3IOI[1]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3lll/CAHBtoAPB3IOI[2]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3lll/CAHBtoAPB3IOI[3]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3lll/CAHBtoAPB3IOI[4]:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3lll/CAHBtoAPB3lII:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3lll/HREADYOUT:ALn</item>
 <item>COREAHBTOAPB3_0/CAHBtoAPB3lll/PSEL:ALn</item>
 <item>FlashFreeze_SB_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_q1:ALn</item>
 <item>FlashFreeze_SB_0/CORERESETP_0/FIC_2_APB_M_PRESET_N_q2:ALn</item>
 <item>FlashFreeze_SB_0/CORERESETP_0/POWER_ON_RESET_N_q1:ALn</item>
 <item>FlashFreeze_SB_0/CORERESETP_0/POWER_ON_RESET_N_q2:ALn</item>
 <item>FlashFreeze_SB_0/CORERESETP_0/RESET_N_M2F_q1:ALn</item>
 <item>FlashFreeze_SB_0/CORERESETP_0/RESET_N_M2F_q2:ALn</item>
 <item>RAM_with_wrapper_0/mem_apb_wrp_0/PREADY:ALn</item>
 <item>RAM_with_wrapper_0/mem_apb_wrp_0/SEL:ALn</item>
 <item>RAM_with_wrapper_0/mem_apb_wrp_0/fsm[0]:ALn</item>
 <item>RAM_with_wrapper_0/mem_apb_wrp_0/fsm[1]:ALn</item>
 <item>RAM_with_wrapper_0/mem_apb_wrp_0/rd_enable:ALn</item>
 <item>RAM_with_wrapper_0/mem_apb_wrp_0/wr_enable:ALn</item>
 <item>cnt34_0/CNT[0]:ALn</item>
 <item>cnt34_0/CNT[10]:ALn</item>
 <item>cnt34_0/CNT[11]:ALn</item>
 <item>cnt34_0/CNT[12]:ALn</item>
 <item>cnt34_0/CNT[13]:ALn</item>
 <item>cnt34_0/CNT[14]:ALn</item>
 <item>cnt34_0/CNT[15]:ALn</item>
 <item>cnt34_0/CNT[16]:ALn</item>
 <item>cnt34_0/CNT[17]:ALn</item>
 <item>cnt34_0/CNT[18]:ALn</item>
 <item>cnt34_0/CNT[19]:ALn</item>
 <item>cnt34_0/CNT[1]:ALn</item>
 <item>cnt34_0/CNT[20]:ALn</item>
 <item>cnt34_0/CNT[21]:ALn</item>
 <item>cnt34_0/CNT[22]:ALn</item>
 <item>cnt34_0/CNT[23]:ALn</item>
 <item>cnt34_0/CNT[24]:ALn</item>
 <item>cnt34_0/CNT[25]:ALn</item>
 <item>cnt34_0/CNT[26]:ALn</item>
 <item>cnt34_0/CNT[2]:ALn</item>
 <item>cnt34_0/CNT[3]:ALn</item>
 <item>cnt34_0/CNT[4]:ALn</item>
 <item>cnt34_0/CNT[5]:ALn</item>
 <item>cnt34_0/CNT[6]:ALn</item>
 <item>cnt34_0/CNT[7]:ALn</item>
 <item>cnt34_0/CNT[8]:ALn</item>
 <item>cnt34_0/CNT[9]:ALn</item>
</list>
<text></text>
</section>
</section>
<section>
<name>Clock domain: </name>
<text>FlashFreeze_SB_0/FABOSC_0/I_RCOSC_25_50MHZ:CLKOUT</text>
<text></text>
<table>
<header>
 <cell>Type of check</cell>
 <cell>Constrained</cell>
 <cell>UnConstrained</cell>
 <cell>Total</cell>
</header>
<row>
 <cell>Setup</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
<row>
 <cell>Recovery</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
<row>
 <cell>Output Setup</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
<row>
 <cell>Total Setup</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
<separator/>
<row>
 <cell>Hold</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
<row>
 <cell>Removal</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
<row>
 <cell>Output Hold</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
<row>
 <cell>Total Hold</cell>
 <cell>            0</cell>
 <cell>            0</cell>
 <cell>            0</cell>
</row>
</table>
</section>
<section>
<name>Input to Output</name>
<table>
<header>
 <cell>Type of check</cell>
 <cell>Constrained</cell>
 <cell>UnConstrained</cell>
 <cell>Total</cell>
</header>
<row>
 <cell>Output Setup</cell>
 <cell>            0</cell>
 <cell>            5</cell>
 <cell>            5</cell>
</row>
<separator/>
<row>
 <cell>Output Hold</cell>
 <cell>            0</cell>
 <cell>            5</cell>
 <cell>            5</cell>
</row>
</table>
<section>
<name>Enhancement Suggestions</name>
<text></text>
<text> - Max delay constraint missing on  input ports:</text>
<text>   </text>
<list>
 <item>DIP1_L19_On_0</item>
 <item>DIP2_L18_On_0</item>
 <item>DIP3_K21_On_1</item>
 <item>DIP4_K20_On_1</item>
 <item>SW1_L20_On_Change</item>
</list>
<text></text>
<text> - Min delay constraint missing on  input ports:</text>
<text>   </text>
<list>
 <item>DIP1_L19_On_0</item>
 <item>DIP2_L18_On_0</item>
 <item>DIP3_K21_On_1</item>
 <item>DIP4_K20_On_1</item>
 <item>SW1_L20_On_Change</item>
</list>
<text></text>
<text></text>
<text> - Max delay constraint missing on  output ports:</text>
<text>   </text>
<list>
 <item>DIP1_output</item>
 <item>DIP2_output</item>
 <item>DIP3_output</item>
 <item>DIP4_output</item>
 <item>SW1_output</item>
</list>
<text></text>
<text> - Min delay constraint missing on  output ports:</text>
<text>   </text>
<list>
 <item>DIP1_output</item>
 <item>DIP2_output</item>
 <item>DIP3_output</item>
 <item>DIP4_output</item>
 <item>SW1_output</item>
</list>
<text></text>
<text></text>
</section>
</section>
</section>
</doc>
