`timescale 1 ns/100 ps
// Version: v11.8 11.8.0.26


module RCOSC_25_50MHZ(
       CLKOUT
    );
output CLKOUT;

    parameter FREQUENCY = 50.0 ;
    
endmodule


module MSS_075(
       CAN_RXBUS_MGPIO3A_H2F_A,
       CAN_RXBUS_MGPIO3A_H2F_B,
       CAN_TX_EBL_MGPIO4A_H2F_A,
       CAN_TX_EBL_MGPIO4A_H2F_B,
       CAN_TXBUS_MGPIO2A_H2F_A,
       CAN_TXBUS_MGPIO2A_H2F_B,
       CLK_CONFIG_APB,
       COMMS_INT,
       CONFIG_PRESET_N,
       EDAC_ERROR,
       F_FM0_RDATA,
       F_FM0_READYOUT,
       F_FM0_RESP,
       F_HM0_ADDR,
       F_HM0_ENABLE,
       F_HM0_SEL,
       F_HM0_SIZE,
       F_HM0_TRANS1,
       F_HM0_WDATA,
       F_HM0_WRITE,
       FAB_CHRGVBUS,
       FAB_DISCHRGVBUS,
       FAB_DMPULLDOWN,
       FAB_DPPULLDOWN,
       FAB_DRVVBUS,
       FAB_IDPULLUP,
       FAB_OPMODE,
       FAB_SUSPENDM,
       FAB_TERMSEL,
       FAB_TXVALID,
       FAB_VCONTROL,
       FAB_VCONTROLLOADM,
       FAB_XCVRSEL,
       FAB_XDATAOUT,
       FACC_GLMUX_SEL,
       FIC32_0_MASTER,
       FIC32_1_MASTER,
       FPGA_RESET_N,
       GTX_CLK,
       H2F_INTERRUPT,
       H2F_NMI,
       H2FCALIB,
       I2C0_SCL_MGPIO31B_H2F_A,
       I2C0_SCL_MGPIO31B_H2F_B,
       I2C0_SDA_MGPIO30B_H2F_A,
       I2C0_SDA_MGPIO30B_H2F_B,
       I2C1_SCL_MGPIO1A_H2F_A,
       I2C1_SCL_MGPIO1A_H2F_B,
       I2C1_SDA_MGPIO0A_H2F_A,
       I2C1_SDA_MGPIO0A_H2F_B,
       MDCF,
       MDOENF,
       MDOF,
       MMUART0_CTS_MGPIO19B_H2F_A,
       MMUART0_CTS_MGPIO19B_H2F_B,
       MMUART0_DCD_MGPIO22B_H2F_A,
       MMUART0_DCD_MGPIO22B_H2F_B,
       MMUART0_DSR_MGPIO20B_H2F_A,
       MMUART0_DSR_MGPIO20B_H2F_B,
       MMUART0_DTR_MGPIO18B_H2F_A,
       MMUART0_DTR_MGPIO18B_H2F_B,
       MMUART0_RI_MGPIO21B_H2F_A,
       MMUART0_RI_MGPIO21B_H2F_B,
       MMUART0_RTS_MGPIO17B_H2F_A,
       MMUART0_RTS_MGPIO17B_H2F_B,
       MMUART0_RXD_MGPIO28B_H2F_A,
       MMUART0_RXD_MGPIO28B_H2F_B,
       MMUART0_SCK_MGPIO29B_H2F_A,
       MMUART0_SCK_MGPIO29B_H2F_B,
       MMUART0_TXD_MGPIO27B_H2F_A,
       MMUART0_TXD_MGPIO27B_H2F_B,
       MMUART1_DTR_MGPIO12B_H2F_A,
       MMUART1_RTS_MGPIO11B_H2F_A,
       MMUART1_RTS_MGPIO11B_H2F_B,
       MMUART1_RXD_MGPIO26B_H2F_A,
       MMUART1_RXD_MGPIO26B_H2F_B,
       MMUART1_SCK_MGPIO25B_H2F_A,
       MMUART1_SCK_MGPIO25B_H2F_B,
       MMUART1_TXD_MGPIO24B_H2F_A,
       MMUART1_TXD_MGPIO24B_H2F_B,
       MPLL_LOCK,
       PER2_FABRIC_PADDR,
       PER2_FABRIC_PENABLE,
       PER2_FABRIC_PSEL,
       PER2_FABRIC_PWDATA,
       PER2_FABRIC_PWRITE,
       RTC_MATCH,
       SLEEPDEEP,
       SLEEPHOLDACK,
       SLEEPING,
       SMBALERT_NO0,
       SMBALERT_NO1,
       SMBSUS_NO0,
       SMBSUS_NO1,
       SPI0_CLK_OUT,
       SPI0_SDI_MGPIO5A_H2F_A,
       SPI0_SDI_MGPIO5A_H2F_B,
       SPI0_SDO_MGPIO6A_H2F_A,
       SPI0_SDO_MGPIO6A_H2F_B,
       SPI0_SS0_MGPIO7A_H2F_A,
       SPI0_SS0_MGPIO7A_H2F_B,
       SPI0_SS1_MGPIO8A_H2F_A,
       SPI0_SS1_MGPIO8A_H2F_B,
       SPI0_SS2_MGPIO9A_H2F_A,
       SPI0_SS2_MGPIO9A_H2F_B,
       SPI0_SS3_MGPIO10A_H2F_A,
       SPI0_SS3_MGPIO10A_H2F_B,
       SPI0_SS4_MGPIO19A_H2F_A,
       SPI0_SS5_MGPIO20A_H2F_A,
       SPI0_SS6_MGPIO21A_H2F_A,
       SPI0_SS7_MGPIO22A_H2F_A,
       SPI1_CLK_OUT,
       SPI1_SDI_MGPIO11A_H2F_A,
       SPI1_SDI_MGPIO11A_H2F_B,
       SPI1_SDO_MGPIO12A_H2F_A,
       SPI1_SDO_MGPIO12A_H2F_B,
       SPI1_SS0_MGPIO13A_H2F_A,
       SPI1_SS0_MGPIO13A_H2F_B,
       SPI1_SS1_MGPIO14A_H2F_A,
       SPI1_SS1_MGPIO14A_H2F_B,
       SPI1_SS2_MGPIO15A_H2F_A,
       SPI1_SS2_MGPIO15A_H2F_B,
       SPI1_SS3_MGPIO16A_H2F_A,
       SPI1_SS3_MGPIO16A_H2F_B,
       SPI1_SS4_MGPIO17A_H2F_A,
       SPI1_SS5_MGPIO18A_H2F_A,
       SPI1_SS6_MGPIO23A_H2F_A,
       SPI1_SS7_MGPIO24A_H2F_A,
       TCGF,
       TRACECLK,
       TRACEDATA,
       TX_CLK,
       TX_ENF,
       TX_ERRF,
       TXCTL_EN_RIF,
       TXD_RIF,
       TXDF,
       TXEV,
       WDOGTIMEOUT,
       F_ARREADY_HREADYOUT1,
       F_AWREADY_HREADYOUT0,
       F_BID,
       F_BRESP_HRESP0,
       F_BVALID,
       F_RDATA_HRDATA01,
       F_RID,
       F_RLAST,
       F_RRESP_HRESP1,
       F_RVALID,
       F_WREADY,
       MDDR_FABRIC_PRDATA,
       MDDR_FABRIC_PREADY,
       MDDR_FABRIC_PSLVERR,
       CAN_RXBUS_F2H_SCP,
       CAN_TX_EBL_F2H_SCP,
       CAN_TXBUS_F2H_SCP,
       COLF,
       CRSF,
       F2_DMAREADY,
       F2H_INTERRUPT,
       F2HCALIB,
       F_DMAREADY,
       F_FM0_ADDR,
       F_FM0_ENABLE,
       F_FM0_MASTLOCK,
       F_FM0_READY,
       F_FM0_SEL,
       F_FM0_SIZE,
       F_FM0_TRANS1,
       F_FM0_WDATA,
       F_FM0_WRITE,
       F_HM0_RDATA,
       F_HM0_READY,
       F_HM0_RESP,
       FAB_AVALID,
       FAB_HOSTDISCON,
       FAB_IDDIG,
       FAB_LINESTATE,
       FAB_M3_RESET_N,
       FAB_PLL_LOCK,
       FAB_RXACTIVE,
       FAB_RXERROR,
       FAB_RXVALID,
       FAB_RXVALIDH,
       FAB_SESSEND,
       FAB_TXREADY,
       FAB_VBUSVALID,
       FAB_VSTATUS,
       FAB_XDATAIN,
       GTX_CLKPF,
       I2C0_BCLK,
       I2C0_SCL_F2H_SCP,
       I2C0_SDA_F2H_SCP,
       I2C1_BCLK,
       I2C1_SCL_F2H_SCP,
       I2C1_SDA_F2H_SCP,
       MDIF,
       MGPIO0A_F2H_GPIN,
       MGPIO10A_F2H_GPIN,
       MGPIO11A_F2H_GPIN,
       MGPIO11B_F2H_GPIN,
       MGPIO12A_F2H_GPIN,
       MGPIO13A_F2H_GPIN,
       MGPIO14A_F2H_GPIN,
       MGPIO15A_F2H_GPIN,
       MGPIO16A_F2H_GPIN,
       MGPIO17B_F2H_GPIN,
       MGPIO18B_F2H_GPIN,
       MGPIO19B_F2H_GPIN,
       MGPIO1A_F2H_GPIN,
       MGPIO20B_F2H_GPIN,
       MGPIO21B_F2H_GPIN,
       MGPIO22B_F2H_GPIN,
       MGPIO24B_F2H_GPIN,
       MGPIO25B_F2H_GPIN,
       MGPIO26B_F2H_GPIN,
       MGPIO27B_F2H_GPIN,
       MGPIO28B_F2H_GPIN,
       MGPIO29B_F2H_GPIN,
       MGPIO2A_F2H_GPIN,
       MGPIO30B_F2H_GPIN,
       MGPIO31B_F2H_GPIN,
       MGPIO3A_F2H_GPIN,
       MGPIO4A_F2H_GPIN,
       MGPIO5A_F2H_GPIN,
       MGPIO6A_F2H_GPIN,
       MGPIO7A_F2H_GPIN,
       MGPIO8A_F2H_GPIN,
       MGPIO9A_F2H_GPIN,
       MMUART0_CTS_F2H_SCP,
       MMUART0_DCD_F2H_SCP,
       MMUART0_DSR_F2H_SCP,
       MMUART0_DTR_F2H_SCP,
       MMUART0_RI_F2H_SCP,
       MMUART0_RTS_F2H_SCP,
       MMUART0_RXD_F2H_SCP,
       MMUART0_SCK_F2H_SCP,
       MMUART0_TXD_F2H_SCP,
       MMUART1_CTS_F2H_SCP,
       MMUART1_DCD_F2H_SCP,
       MMUART1_DSR_F2H_SCP,
       MMUART1_RI_F2H_SCP,
       MMUART1_RTS_F2H_SCP,
       MMUART1_RXD_F2H_SCP,
       MMUART1_SCK_F2H_SCP,
       MMUART1_TXD_F2H_SCP,
       PER2_FABRIC_PRDATA,
       PER2_FABRIC_PREADY,
       PER2_FABRIC_PSLVERR,
       RCGF,
       RX_CLKPF,
       RX_DVF,
       RX_ERRF,
       RX_EV,
       RXDF,
       SLEEPHOLDREQ,
       SMBALERT_NI0,
       SMBALERT_NI1,
       SMBSUS_NI0,
       SMBSUS_NI1,
       SPI0_CLK_IN,
       SPI0_SDI_F2H_SCP,
       SPI0_SDO_F2H_SCP,
       SPI0_SS0_F2H_SCP,
       SPI0_SS1_F2H_SCP,
       SPI0_SS2_F2H_SCP,
       SPI0_SS3_F2H_SCP,
       SPI1_CLK_IN,
       SPI1_SDI_F2H_SCP,
       SPI1_SDO_F2H_SCP,
       SPI1_SS0_F2H_SCP,
       SPI1_SS1_F2H_SCP,
       SPI1_SS2_F2H_SCP,
       SPI1_SS3_F2H_SCP,
       TX_CLKPF,
       USER_MSS_GPIO_RESET_N,
       USER_MSS_RESET_N,
       XCLK_FAB,
       CLK_BASE,
       CLK_MDDR_APB,
       F_ARADDR_HADDR1,
       F_ARBURST_HTRANS1,
       F_ARID_HSEL1,
       F_ARLEN_HBURST1,
       F_ARLOCK_HMASTLOCK1,
       F_ARSIZE_HSIZE1,
       F_ARVALID_HWRITE1,
       F_AWADDR_HADDR0,
       F_AWBURST_HTRANS0,
       F_AWID_HSEL0,
       F_AWLEN_HBURST0,
       F_AWLOCK_HMASTLOCK0,
       F_AWSIZE_HSIZE0,
       F_AWVALID_HWRITE0,
       F_BREADY,
       F_RMW_AXI,
       F_RREADY,
       F_WDATA_HWDATA01,
       F_WID_HREADY01,
       F_WLAST,
       F_WSTRB,
       F_WVALID,
       FPGA_MDDR_ARESET_N,
       MDDR_FABRIC_PADDR,
       MDDR_FABRIC_PENABLE,
       MDDR_FABRIC_PSEL,
       MDDR_FABRIC_PWDATA,
       MDDR_FABRIC_PWRITE,
       PRESET_N,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_IN,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_IN,
       DM_IN,
       DRAM_DQ_IN,
       DRAM_DQS_IN,
       DRAM_FIFO_WE_IN,
       I2C0_SCL_USBC_DATA1_MGPIO31B_IN,
       I2C0_SDA_USBC_DATA0_MGPIO30B_IN,
       I2C1_SCL_USBA_DATA4_MGPIO1A_IN,
       I2C1_SDA_USBA_DATA3_MGPIO0A_IN,
       MGPIO0B_IN,
       MGPIO10B_IN,
       MGPIO1B_IN,
       MGPIO25A_IN,
       MGPIO26A_IN,
       MGPIO27A_IN,
       MGPIO28A_IN,
       MGPIO29A_IN,
       MGPIO2B_IN,
       MGPIO30A_IN,
       MGPIO31A_IN,
       MGPIO3B_IN,
       MGPIO4B_IN,
       MGPIO5B_IN,
       MGPIO6B_IN,
       MGPIO7B_IN,
       MGPIO8B_IN,
       MGPIO9B_IN,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_IN,
       MMUART0_DCD_MGPIO22B_IN,
       MMUART0_DSR_MGPIO20B_IN,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_IN,
       MMUART0_RI_MGPIO21B_IN,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_IN,
       MMUART0_RXD_USBC_STP_MGPIO28B_IN,
       MMUART0_SCK_USBC_NXT_MGPIO29B_IN,
       MMUART0_TXD_USBC_DIR_MGPIO27B_IN,
       MMUART1_CTS_MGPIO13B_IN,
       MMUART1_DCD_MGPIO16B_IN,
       MMUART1_DSR_MGPIO14B_IN,
       MMUART1_DTR_MGPIO12B_IN,
       MMUART1_RI_MGPIO15B_IN,
       MMUART1_RTS_MGPIO11B_IN,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_IN,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_IN,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_IN,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN,
       RGMII_MDC_RMII_MDC_IN,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN,
       RGMII_RX_CLK_IN,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN,
       RGMII_RXD3_USBB_DATA4_IN,
       RGMII_TX_CLK_IN,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_IN,
       RGMII_TXD1_RMII_TXD1_USBB_STP_IN,
       RGMII_TXD2_USBB_DATA5_IN,
       RGMII_TXD3_USBB_DATA6_IN,
       SPI0_SCK_USBA_XCLK_IN,
       SPI0_SDI_USBA_DIR_MGPIO5A_IN,
       SPI0_SDO_USBA_STP_MGPIO6A_IN,
       SPI0_SS0_USBA_NXT_MGPIO7A_IN,
       SPI0_SS1_USBA_DATA5_MGPIO8A_IN,
       SPI0_SS2_USBA_DATA6_MGPIO9A_IN,
       SPI0_SS3_USBA_DATA7_MGPIO10A_IN,
       SPI0_SS4_MGPIO19A_IN,
       SPI0_SS5_MGPIO20A_IN,
       SPI0_SS6_MGPIO21A_IN,
       SPI0_SS7_MGPIO22A_IN,
       SPI1_SCK_IN,
       SPI1_SDI_MGPIO11A_IN,
       SPI1_SDO_MGPIO12A_IN,
       SPI1_SS0_MGPIO13A_IN,
       SPI1_SS1_MGPIO14A_IN,
       SPI1_SS2_MGPIO15A_IN,
       SPI1_SS3_MGPIO16A_IN,
       SPI1_SS4_MGPIO17A_IN,
       SPI1_SS5_MGPIO18A_IN,
       SPI1_SS6_MGPIO23A_IN,
       SPI1_SS7_MGPIO24A_IN,
       USBC_XCLK_IN,
       USBD_DATA0_IN,
       USBD_DATA1_IN,
       USBD_DATA2_IN,
       USBD_DATA3_IN,
       USBD_DATA4_IN,
       USBD_DATA5_IN,
       USBD_DATA6_IN,
       USBD_DATA7_MGPIO23B_IN,
       USBD_DIR_IN,
       USBD_NXT_IN,
       USBD_STP_IN,
       USBD_XCLK_IN,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT,
       DRAM_ADDR,
       DRAM_BA,
       DRAM_CASN,
       DRAM_CKE,
       DRAM_CLK,
       DRAM_CSN,
       DRAM_DM_RDQS_OUT,
       DRAM_DQ_OUT,
       DRAM_DQS_OUT,
       DRAM_FIFO_WE_OUT,
       DRAM_ODT,
       DRAM_RASN,
       DRAM_RSTN,
       DRAM_WEN,
       I2C0_SCL_USBC_DATA1_MGPIO31B_OUT,
       I2C0_SDA_USBC_DATA0_MGPIO30B_OUT,
       I2C1_SCL_USBA_DATA4_MGPIO1A_OUT,
       I2C1_SDA_USBA_DATA3_MGPIO0A_OUT,
       MGPIO0B_OUT,
       MGPIO10B_OUT,
       MGPIO1B_OUT,
       MGPIO25A_OUT,
       MGPIO26A_OUT,
       MGPIO27A_OUT,
       MGPIO28A_OUT,
       MGPIO29A_OUT,
       MGPIO2B_OUT,
       MGPIO30A_OUT,
       MGPIO31A_OUT,
       MGPIO3B_OUT,
       MGPIO4B_OUT,
       MGPIO5B_OUT,
       MGPIO6B_OUT,
       MGPIO7B_OUT,
       MGPIO8B_OUT,
       MGPIO9B_OUT,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT,
       MMUART0_DCD_MGPIO22B_OUT,
       MMUART0_DSR_MGPIO20B_OUT,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT,
       MMUART0_RI_MGPIO21B_OUT,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT,
       MMUART0_RXD_USBC_STP_MGPIO28B_OUT,
       MMUART0_SCK_USBC_NXT_MGPIO29B_OUT,
       MMUART0_TXD_USBC_DIR_MGPIO27B_OUT,
       MMUART1_CTS_MGPIO13B_OUT,
       MMUART1_DCD_MGPIO16B_OUT,
       MMUART1_DSR_MGPIO14B_OUT,
       MMUART1_DTR_MGPIO12B_OUT,
       MMUART1_RI_MGPIO15B_OUT,
       MMUART1_RTS_MGPIO11B_OUT,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT,
       RGMII_MDC_RMII_MDC_OUT,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT,
       RGMII_RX_CLK_OUT,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT,
       RGMII_RXD3_USBB_DATA4_OUT,
       RGMII_TX_CLK_OUT,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT,
       RGMII_TXD1_RMII_TXD1_USBB_STP_OUT,
       RGMII_TXD2_USBB_DATA5_OUT,
       RGMII_TXD3_USBB_DATA6_OUT,
       SPI0_SCK_USBA_XCLK_OUT,
       SPI0_SDI_USBA_DIR_MGPIO5A_OUT,
       SPI0_SDO_USBA_STP_MGPIO6A_OUT,
       SPI0_SS0_USBA_NXT_MGPIO7A_OUT,
       SPI0_SS1_USBA_DATA5_MGPIO8A_OUT,
       SPI0_SS2_USBA_DATA6_MGPIO9A_OUT,
       SPI0_SS3_USBA_DATA7_MGPIO10A_OUT,
       SPI0_SS4_MGPIO19A_OUT,
       SPI0_SS5_MGPIO20A_OUT,
       SPI0_SS6_MGPIO21A_OUT,
       SPI0_SS7_MGPIO22A_OUT,
       SPI1_SCK_OUT,
       SPI1_SDI_MGPIO11A_OUT,
       SPI1_SDO_MGPIO12A_OUT,
       SPI1_SS0_MGPIO13A_OUT,
       SPI1_SS1_MGPIO14A_OUT,
       SPI1_SS2_MGPIO15A_OUT,
       SPI1_SS3_MGPIO16A_OUT,
       SPI1_SS4_MGPIO17A_OUT,
       SPI1_SS5_MGPIO18A_OUT,
       SPI1_SS6_MGPIO23A_OUT,
       SPI1_SS7_MGPIO24A_OUT,
       USBC_XCLK_OUT,
       USBD_DATA0_OUT,
       USBD_DATA1_OUT,
       USBD_DATA2_OUT,
       USBD_DATA3_OUT,
       USBD_DATA4_OUT,
       USBD_DATA5_OUT,
       USBD_DATA6_OUT,
       USBD_DATA7_MGPIO23B_OUT,
       USBD_DIR_OUT,
       USBD_NXT_OUT,
       USBD_STP_OUT,
       USBD_XCLK_OUT,
       CAN_RXBUS_USBA_DATA1_MGPIO3A_OE,
       CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE,
       CAN_TXBUS_USBA_DATA0_MGPIO2A_OE,
       DM_OE,
       DRAM_DQ_OE,
       DRAM_DQS_OE,
       I2C0_SCL_USBC_DATA1_MGPIO31B_OE,
       I2C0_SDA_USBC_DATA0_MGPIO30B_OE,
       I2C1_SCL_USBA_DATA4_MGPIO1A_OE,
       I2C1_SDA_USBA_DATA3_MGPIO0A_OE,
       MGPIO0B_OE,
       MGPIO10B_OE,
       MGPIO1B_OE,
       MGPIO25A_OE,
       MGPIO26A_OE,
       MGPIO27A_OE,
       MGPIO28A_OE,
       MGPIO29A_OE,
       MGPIO2B_OE,
       MGPIO30A_OE,
       MGPIO31A_OE,
       MGPIO3B_OE,
       MGPIO4B_OE,
       MGPIO5B_OE,
       MGPIO6B_OE,
       MGPIO7B_OE,
       MGPIO8B_OE,
       MGPIO9B_OE,
       MMUART0_CTS_USBC_DATA7_MGPIO19B_OE,
       MMUART0_DCD_MGPIO22B_OE,
       MMUART0_DSR_MGPIO20B_OE,
       MMUART0_DTR_USBC_DATA6_MGPIO18B_OE,
       MMUART0_RI_MGPIO21B_OE,
       MMUART0_RTS_USBC_DATA5_MGPIO17B_OE,
       MMUART0_RXD_USBC_STP_MGPIO28B_OE,
       MMUART0_SCK_USBC_NXT_MGPIO29B_OE,
       MMUART0_TXD_USBC_DIR_MGPIO27B_OE,
       MMUART1_CTS_MGPIO13B_OE,
       MMUART1_DCD_MGPIO16B_OE,
       MMUART1_DSR_MGPIO14B_OE,
       MMUART1_DTR_MGPIO12B_OE,
       MMUART1_RI_MGPIO15B_OE,
       MMUART1_RTS_MGPIO11B_OE,
       MMUART1_RXD_USBC_DATA3_MGPIO26B_OE,
       MMUART1_SCK_USBC_DATA4_MGPIO25B_OE,
       MMUART1_TXD_USBC_DATA2_MGPIO24B_OE,
       RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE,
       RGMII_MDC_RMII_MDC_OE,
       RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE,
       RGMII_RX_CLK_OE,
       RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE,
       RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE,
       RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE,
       RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE,
       RGMII_RXD3_USBB_DATA4_OE,
       RGMII_TX_CLK_OE,
       RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE,
       RGMII_TXD0_RMII_TXD0_USBB_DIR_OE,
       RGMII_TXD1_RMII_TXD1_USBB_STP_OE,
       RGMII_TXD2_USBB_DATA5_OE,
       RGMII_TXD3_USBB_DATA6_OE,
       SPI0_SCK_USBA_XCLK_OE,
       SPI0_SDI_USBA_DIR_MGPIO5A_OE,
       SPI0_SDO_USBA_STP_MGPIO6A_OE,
       SPI0_SS0_USBA_NXT_MGPIO7A_OE,
       SPI0_SS1_USBA_DATA5_MGPIO8A_OE,
       SPI0_SS2_USBA_DATA6_MGPIO9A_OE,
       SPI0_SS3_USBA_DATA7_MGPIO10A_OE,
       SPI0_SS4_MGPIO19A_OE,
       SPI0_SS5_MGPIO20A_OE,
       SPI0_SS6_MGPIO21A_OE,
       SPI0_SS7_MGPIO22A_OE,
       SPI1_SCK_OE,
       SPI1_SDI_MGPIO11A_OE,
       SPI1_SDO_MGPIO12A_OE,
       SPI1_SS0_MGPIO13A_OE,
       SPI1_SS1_MGPIO14A_OE,
       SPI1_SS2_MGPIO15A_OE,
       SPI1_SS3_MGPIO16A_OE,
       SPI1_SS4_MGPIO17A_OE,
       SPI1_SS5_MGPIO18A_OE,
       SPI1_SS6_MGPIO23A_OE,
       SPI1_SS7_MGPIO24A_OE,
       USBC_XCLK_OE,
       USBD_DATA0_OE,
       USBD_DATA1_OE,
       USBD_DATA2_OE,
       USBD_DATA3_OE,
       USBD_DATA4_OE,
       USBD_DATA5_OE,
       USBD_DATA6_OE,
       USBD_DATA7_MGPIO23B_OE,
       USBD_DIR_OE,
       USBD_NXT_OE,
       USBD_STP_OE,
       USBD_XCLK_OE
    );
output CAN_RXBUS_MGPIO3A_H2F_A;
output CAN_RXBUS_MGPIO3A_H2F_B;
output CAN_TX_EBL_MGPIO4A_H2F_A;
output CAN_TX_EBL_MGPIO4A_H2F_B;
output CAN_TXBUS_MGPIO2A_H2F_A;
output CAN_TXBUS_MGPIO2A_H2F_B;
output CLK_CONFIG_APB;
output COMMS_INT;
output CONFIG_PRESET_N;
output [7:0] EDAC_ERROR;
output [31:0] F_FM0_RDATA;
output F_FM0_READYOUT;
output F_FM0_RESP;
output [31:0] F_HM0_ADDR;
output F_HM0_ENABLE;
output F_HM0_SEL;
output [1:0] F_HM0_SIZE;
output F_HM0_TRANS1;
output [31:0] F_HM0_WDATA;
output F_HM0_WRITE;
output FAB_CHRGVBUS;
output FAB_DISCHRGVBUS;
output FAB_DMPULLDOWN;
output FAB_DPPULLDOWN;
output FAB_DRVVBUS;
output FAB_IDPULLUP;
output [1:0] FAB_OPMODE;
output FAB_SUSPENDM;
output FAB_TERMSEL;
output FAB_TXVALID;
output [3:0] FAB_VCONTROL;
output FAB_VCONTROLLOADM;
output [1:0] FAB_XCVRSEL;
output [7:0] FAB_XDATAOUT;
output FACC_GLMUX_SEL;
output [1:0] FIC32_0_MASTER;
output [1:0] FIC32_1_MASTER;
output FPGA_RESET_N;
output GTX_CLK;
output [15:0] H2F_INTERRUPT;
output H2F_NMI;
output H2FCALIB;
output I2C0_SCL_MGPIO31B_H2F_A;
output I2C0_SCL_MGPIO31B_H2F_B;
output I2C0_SDA_MGPIO30B_H2F_A;
output I2C0_SDA_MGPIO30B_H2F_B;
output I2C1_SCL_MGPIO1A_H2F_A;
output I2C1_SCL_MGPIO1A_H2F_B;
output I2C1_SDA_MGPIO0A_H2F_A;
output I2C1_SDA_MGPIO0A_H2F_B;
output MDCF;
output MDOENF;
output MDOF;
output MMUART0_CTS_MGPIO19B_H2F_A;
output MMUART0_CTS_MGPIO19B_H2F_B;
output MMUART0_DCD_MGPIO22B_H2F_A;
output MMUART0_DCD_MGPIO22B_H2F_B;
output MMUART0_DSR_MGPIO20B_H2F_A;
output MMUART0_DSR_MGPIO20B_H2F_B;
output MMUART0_DTR_MGPIO18B_H2F_A;
output MMUART0_DTR_MGPIO18B_H2F_B;
output MMUART0_RI_MGPIO21B_H2F_A;
output MMUART0_RI_MGPIO21B_H2F_B;
output MMUART0_RTS_MGPIO17B_H2F_A;
output MMUART0_RTS_MGPIO17B_H2F_B;
output MMUART0_RXD_MGPIO28B_H2F_A;
output MMUART0_RXD_MGPIO28B_H2F_B;
output MMUART0_SCK_MGPIO29B_H2F_A;
output MMUART0_SCK_MGPIO29B_H2F_B;
output MMUART0_TXD_MGPIO27B_H2F_A;
output MMUART0_TXD_MGPIO27B_H2F_B;
output MMUART1_DTR_MGPIO12B_H2F_A;
output MMUART1_RTS_MGPIO11B_H2F_A;
output MMUART1_RTS_MGPIO11B_H2F_B;
output MMUART1_RXD_MGPIO26B_H2F_A;
output MMUART1_RXD_MGPIO26B_H2F_B;
output MMUART1_SCK_MGPIO25B_H2F_A;
output MMUART1_SCK_MGPIO25B_H2F_B;
output MMUART1_TXD_MGPIO24B_H2F_A;
output MMUART1_TXD_MGPIO24B_H2F_B;
output MPLL_LOCK;
output [15:2] PER2_FABRIC_PADDR;
output PER2_FABRIC_PENABLE;
output PER2_FABRIC_PSEL;
output [31:0] PER2_FABRIC_PWDATA;
output PER2_FABRIC_PWRITE;
output RTC_MATCH;
output SLEEPDEEP;
output SLEEPHOLDACK;
output SLEEPING;
output SMBALERT_NO0;
output SMBALERT_NO1;
output SMBSUS_NO0;
output SMBSUS_NO1;
output SPI0_CLK_OUT;
output SPI0_SDI_MGPIO5A_H2F_A;
output SPI0_SDI_MGPIO5A_H2F_B;
output SPI0_SDO_MGPIO6A_H2F_A;
output SPI0_SDO_MGPIO6A_H2F_B;
output SPI0_SS0_MGPIO7A_H2F_A;
output SPI0_SS0_MGPIO7A_H2F_B;
output SPI0_SS1_MGPIO8A_H2F_A;
output SPI0_SS1_MGPIO8A_H2F_B;
output SPI0_SS2_MGPIO9A_H2F_A;
output SPI0_SS2_MGPIO9A_H2F_B;
output SPI0_SS3_MGPIO10A_H2F_A;
output SPI0_SS3_MGPIO10A_H2F_B;
output SPI0_SS4_MGPIO19A_H2F_A;
output SPI0_SS5_MGPIO20A_H2F_A;
output SPI0_SS6_MGPIO21A_H2F_A;
output SPI0_SS7_MGPIO22A_H2F_A;
output SPI1_CLK_OUT;
output SPI1_SDI_MGPIO11A_H2F_A;
output SPI1_SDI_MGPIO11A_H2F_B;
output SPI1_SDO_MGPIO12A_H2F_A;
output SPI1_SDO_MGPIO12A_H2F_B;
output SPI1_SS0_MGPIO13A_H2F_A;
output SPI1_SS0_MGPIO13A_H2F_B;
output SPI1_SS1_MGPIO14A_H2F_A;
output SPI1_SS1_MGPIO14A_H2F_B;
output SPI1_SS2_MGPIO15A_H2F_A;
output SPI1_SS2_MGPIO15A_H2F_B;
output SPI1_SS3_MGPIO16A_H2F_A;
output SPI1_SS3_MGPIO16A_H2F_B;
output SPI1_SS4_MGPIO17A_H2F_A;
output SPI1_SS5_MGPIO18A_H2F_A;
output SPI1_SS6_MGPIO23A_H2F_A;
output SPI1_SS7_MGPIO24A_H2F_A;
output [9:0] TCGF;
output TRACECLK;
output [3:0] TRACEDATA;
output TX_CLK;
output TX_ENF;
output TX_ERRF;
output TXCTL_EN_RIF;
output [3:0] TXD_RIF;
output [7:0] TXDF;
output TXEV;
output WDOGTIMEOUT;
output F_ARREADY_HREADYOUT1;
output F_AWREADY_HREADYOUT0;
output [3:0] F_BID;
output [1:0] F_BRESP_HRESP0;
output F_BVALID;
output [63:0] F_RDATA_HRDATA01;
output [3:0] F_RID;
output F_RLAST;
output [1:0] F_RRESP_HRESP1;
output F_RVALID;
output F_WREADY;
output [15:0] MDDR_FABRIC_PRDATA;
output MDDR_FABRIC_PREADY;
output MDDR_FABRIC_PSLVERR;
input  CAN_RXBUS_F2H_SCP;
input  CAN_TX_EBL_F2H_SCP;
input  CAN_TXBUS_F2H_SCP;
input  COLF;
input  CRSF;
input  [1:0] F2_DMAREADY;
input  [15:0] F2H_INTERRUPT;
input  F2HCALIB;
input  [1:0] F_DMAREADY;
input  [31:0] F_FM0_ADDR;
input  F_FM0_ENABLE;
input  F_FM0_MASTLOCK;
input  F_FM0_READY;
input  F_FM0_SEL;
input  [1:0] F_FM0_SIZE;
input  F_FM0_TRANS1;
input  [31:0] F_FM0_WDATA;
input  F_FM0_WRITE;
input  [31:0] F_HM0_RDATA;
input  F_HM0_READY;
input  F_HM0_RESP;
input  FAB_AVALID;
input  FAB_HOSTDISCON;
input  FAB_IDDIG;
input  [1:0] FAB_LINESTATE;
input  FAB_M3_RESET_N;
input  FAB_PLL_LOCK;
input  FAB_RXACTIVE;
input  FAB_RXERROR;
input  FAB_RXVALID;
input  FAB_RXVALIDH;
input  FAB_SESSEND;
input  FAB_TXREADY;
input  FAB_VBUSVALID;
input  [7:0] FAB_VSTATUS;
input  [7:0] FAB_XDATAIN;
input  GTX_CLKPF;
input  I2C0_BCLK;
input  I2C0_SCL_F2H_SCP;
input  I2C0_SDA_F2H_SCP;
input  I2C1_BCLK;
input  I2C1_SCL_F2H_SCP;
input  I2C1_SDA_F2H_SCP;
input  MDIF;
input  MGPIO0A_F2H_GPIN;
input  MGPIO10A_F2H_GPIN;
input  MGPIO11A_F2H_GPIN;
input  MGPIO11B_F2H_GPIN;
input  MGPIO12A_F2H_GPIN;
input  MGPIO13A_F2H_GPIN;
input  MGPIO14A_F2H_GPIN;
input  MGPIO15A_F2H_GPIN;
input  MGPIO16A_F2H_GPIN;
input  MGPIO17B_F2H_GPIN;
input  MGPIO18B_F2H_GPIN;
input  MGPIO19B_F2H_GPIN;
input  MGPIO1A_F2H_GPIN;
input  MGPIO20B_F2H_GPIN;
input  MGPIO21B_F2H_GPIN;
input  MGPIO22B_F2H_GPIN;
input  MGPIO24B_F2H_GPIN;
input  MGPIO25B_F2H_GPIN;
input  MGPIO26B_F2H_GPIN;
input  MGPIO27B_F2H_GPIN;
input  MGPIO28B_F2H_GPIN;
input  MGPIO29B_F2H_GPIN;
input  MGPIO2A_F2H_GPIN;
input  MGPIO30B_F2H_GPIN;
input  MGPIO31B_F2H_GPIN;
input  MGPIO3A_F2H_GPIN;
input  MGPIO4A_F2H_GPIN;
input  MGPIO5A_F2H_GPIN;
input  MGPIO6A_F2H_GPIN;
input  MGPIO7A_F2H_GPIN;
input  MGPIO8A_F2H_GPIN;
input  MGPIO9A_F2H_GPIN;
input  MMUART0_CTS_F2H_SCP;
input  MMUART0_DCD_F2H_SCP;
input  MMUART0_DSR_F2H_SCP;
input  MMUART0_DTR_F2H_SCP;
input  MMUART0_RI_F2H_SCP;
input  MMUART0_RTS_F2H_SCP;
input  MMUART0_RXD_F2H_SCP;
input  MMUART0_SCK_F2H_SCP;
input  MMUART0_TXD_F2H_SCP;
input  MMUART1_CTS_F2H_SCP;
input  MMUART1_DCD_F2H_SCP;
input  MMUART1_DSR_F2H_SCP;
input  MMUART1_RI_F2H_SCP;
input  MMUART1_RTS_F2H_SCP;
input  MMUART1_RXD_F2H_SCP;
input  MMUART1_SCK_F2H_SCP;
input  MMUART1_TXD_F2H_SCP;
input  [31:0] PER2_FABRIC_PRDATA;
input  PER2_FABRIC_PREADY;
input  PER2_FABRIC_PSLVERR;
input  [9:0] RCGF;
input  RX_CLKPF;
input  RX_DVF;
input  RX_ERRF;
input  RX_EV;
input  [7:0] RXDF;
input  SLEEPHOLDREQ;
input  SMBALERT_NI0;
input  SMBALERT_NI1;
input  SMBSUS_NI0;
input  SMBSUS_NI1;
input  SPI0_CLK_IN;
input  SPI0_SDI_F2H_SCP;
input  SPI0_SDO_F2H_SCP;
input  SPI0_SS0_F2H_SCP;
input  SPI0_SS1_F2H_SCP;
input  SPI0_SS2_F2H_SCP;
input  SPI0_SS3_F2H_SCP;
input  SPI1_CLK_IN;
input  SPI1_SDI_F2H_SCP;
input  SPI1_SDO_F2H_SCP;
input  SPI1_SS0_F2H_SCP;
input  SPI1_SS1_F2H_SCP;
input  SPI1_SS2_F2H_SCP;
input  SPI1_SS3_F2H_SCP;
input  TX_CLKPF;
input  USER_MSS_GPIO_RESET_N;
input  USER_MSS_RESET_N;
input  XCLK_FAB;
input  CLK_BASE;
input  CLK_MDDR_APB;
input  [31:0] F_ARADDR_HADDR1;
input  [1:0] F_ARBURST_HTRANS1;
input  [3:0] F_ARID_HSEL1;
input  [3:0] F_ARLEN_HBURST1;
input  [1:0] F_ARLOCK_HMASTLOCK1;
input  [1:0] F_ARSIZE_HSIZE1;
input  F_ARVALID_HWRITE1;
input  [31:0] F_AWADDR_HADDR0;
input  [1:0] F_AWBURST_HTRANS0;
input  [3:0] F_AWID_HSEL0;
input  [3:0] F_AWLEN_HBURST0;
input  [1:0] F_AWLOCK_HMASTLOCK0;
input  [1:0] F_AWSIZE_HSIZE0;
input  F_AWVALID_HWRITE0;
input  F_BREADY;
input  F_RMW_AXI;
input  F_RREADY;
input  [63:0] F_WDATA_HWDATA01;
input  [3:0] F_WID_HREADY01;
input  F_WLAST;
input  [7:0] F_WSTRB;
input  F_WVALID;
input  FPGA_MDDR_ARESET_N;
input  [10:2] MDDR_FABRIC_PADDR;
input  MDDR_FABRIC_PENABLE;
input  MDDR_FABRIC_PSEL;
input  [15:0] MDDR_FABRIC_PWDATA;
input  MDDR_FABRIC_PWRITE;
input  PRESET_N;
input  CAN_RXBUS_USBA_DATA1_MGPIO3A_IN;
input  CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN;
input  CAN_TXBUS_USBA_DATA0_MGPIO2A_IN;
input  [2:0] DM_IN;
input  [17:0] DRAM_DQ_IN;
input  [2:0] DRAM_DQS_IN;
input  [1:0] DRAM_FIFO_WE_IN;
input  I2C0_SCL_USBC_DATA1_MGPIO31B_IN;
input  I2C0_SDA_USBC_DATA0_MGPIO30B_IN;
input  I2C1_SCL_USBA_DATA4_MGPIO1A_IN;
input  I2C1_SDA_USBA_DATA3_MGPIO0A_IN;
input  MGPIO0B_IN;
input  MGPIO10B_IN;
input  MGPIO1B_IN;
input  MGPIO25A_IN;
input  MGPIO26A_IN;
input  MGPIO27A_IN;
input  MGPIO28A_IN;
input  MGPIO29A_IN;
input  MGPIO2B_IN;
input  MGPIO30A_IN;
input  MGPIO31A_IN;
input  MGPIO3B_IN;
input  MGPIO4B_IN;
input  MGPIO5B_IN;
input  MGPIO6B_IN;
input  MGPIO7B_IN;
input  MGPIO8B_IN;
input  MGPIO9B_IN;
input  MMUART0_CTS_USBC_DATA7_MGPIO19B_IN;
input  MMUART0_DCD_MGPIO22B_IN;
input  MMUART0_DSR_MGPIO20B_IN;
input  MMUART0_DTR_USBC_DATA6_MGPIO18B_IN;
input  MMUART0_RI_MGPIO21B_IN;
input  MMUART0_RTS_USBC_DATA5_MGPIO17B_IN;
input  MMUART0_RXD_USBC_STP_MGPIO28B_IN;
input  MMUART0_SCK_USBC_NXT_MGPIO29B_IN;
input  MMUART0_TXD_USBC_DIR_MGPIO27B_IN;
input  MMUART1_CTS_MGPIO13B_IN;
input  MMUART1_DCD_MGPIO16B_IN;
input  MMUART1_DSR_MGPIO14B_IN;
input  MMUART1_DTR_MGPIO12B_IN;
input  MMUART1_RI_MGPIO15B_IN;
input  MMUART1_RTS_MGPIO11B_IN;
input  MMUART1_RXD_USBC_DATA3_MGPIO26B_IN;
input  MMUART1_SCK_USBC_DATA4_MGPIO25B_IN;
input  MMUART1_TXD_USBC_DATA2_MGPIO24B_IN;
input  RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN;
input  RGMII_MDC_RMII_MDC_IN;
input  RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN;
input  RGMII_RX_CLK_IN;
input  RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN;
input  RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN;
input  RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN;
input  RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN;
input  RGMII_RXD3_USBB_DATA4_IN;
input  RGMII_TX_CLK_IN;
input  RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN;
input  RGMII_TXD0_RMII_TXD0_USBB_DIR_IN;
input  RGMII_TXD1_RMII_TXD1_USBB_STP_IN;
input  RGMII_TXD2_USBB_DATA5_IN;
input  RGMII_TXD3_USBB_DATA6_IN;
input  SPI0_SCK_USBA_XCLK_IN;
input  SPI0_SDI_USBA_DIR_MGPIO5A_IN;
input  SPI0_SDO_USBA_STP_MGPIO6A_IN;
input  SPI0_SS0_USBA_NXT_MGPIO7A_IN;
input  SPI0_SS1_USBA_DATA5_MGPIO8A_IN;
input  SPI0_SS2_USBA_DATA6_MGPIO9A_IN;
input  SPI0_SS3_USBA_DATA7_MGPIO10A_IN;
input  SPI0_SS4_MGPIO19A_IN;
input  SPI0_SS5_MGPIO20A_IN;
input  SPI0_SS6_MGPIO21A_IN;
input  SPI0_SS7_MGPIO22A_IN;
input  SPI1_SCK_IN;
input  SPI1_SDI_MGPIO11A_IN;
input  SPI1_SDO_MGPIO12A_IN;
input  SPI1_SS0_MGPIO13A_IN;
input  SPI1_SS1_MGPIO14A_IN;
input  SPI1_SS2_MGPIO15A_IN;
input  SPI1_SS3_MGPIO16A_IN;
input  SPI1_SS4_MGPIO17A_IN;
input  SPI1_SS5_MGPIO18A_IN;
input  SPI1_SS6_MGPIO23A_IN;
input  SPI1_SS7_MGPIO24A_IN;
input  USBC_XCLK_IN;
input  USBD_DATA0_IN;
input  USBD_DATA1_IN;
input  USBD_DATA2_IN;
input  USBD_DATA3_IN;
input  USBD_DATA4_IN;
input  USBD_DATA5_IN;
input  USBD_DATA6_IN;
input  USBD_DATA7_MGPIO23B_IN;
input  USBD_DIR_IN;
input  USBD_NXT_IN;
input  USBD_STP_IN;
input  USBD_XCLK_IN;
output CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT;
output CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT;
output CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT;
output [15:0] DRAM_ADDR;
output [2:0] DRAM_BA;
output DRAM_CASN;
output DRAM_CKE;
output DRAM_CLK;
output DRAM_CSN;
output [2:0] DRAM_DM_RDQS_OUT;
output [17:0] DRAM_DQ_OUT;
output [2:0] DRAM_DQS_OUT;
output [1:0] DRAM_FIFO_WE_OUT;
output DRAM_ODT;
output DRAM_RASN;
output DRAM_RSTN;
output DRAM_WEN;
output I2C0_SCL_USBC_DATA1_MGPIO31B_OUT;
output I2C0_SDA_USBC_DATA0_MGPIO30B_OUT;
output I2C1_SCL_USBA_DATA4_MGPIO1A_OUT;
output I2C1_SDA_USBA_DATA3_MGPIO0A_OUT;
output MGPIO0B_OUT;
output MGPIO10B_OUT;
output MGPIO1B_OUT;
output MGPIO25A_OUT;
output MGPIO26A_OUT;
output MGPIO27A_OUT;
output MGPIO28A_OUT;
output MGPIO29A_OUT;
output MGPIO2B_OUT;
output MGPIO30A_OUT;
output MGPIO31A_OUT;
output MGPIO3B_OUT;
output MGPIO4B_OUT;
output MGPIO5B_OUT;
output MGPIO6B_OUT;
output MGPIO7B_OUT;
output MGPIO8B_OUT;
output MGPIO9B_OUT;
output MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT;
output MMUART0_DCD_MGPIO22B_OUT;
output MMUART0_DSR_MGPIO20B_OUT;
output MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT;
output MMUART0_RI_MGPIO21B_OUT;
output MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT;
output MMUART0_RXD_USBC_STP_MGPIO28B_OUT;
output MMUART0_SCK_USBC_NXT_MGPIO29B_OUT;
output MMUART0_TXD_USBC_DIR_MGPIO27B_OUT;
output MMUART1_CTS_MGPIO13B_OUT;
output MMUART1_DCD_MGPIO16B_OUT;
output MMUART1_DSR_MGPIO14B_OUT;
output MMUART1_DTR_MGPIO12B_OUT;
output MMUART1_RI_MGPIO15B_OUT;
output MMUART1_RTS_MGPIO11B_OUT;
output MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT;
output MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT;
output MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT;
output RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT;
output RGMII_MDC_RMII_MDC_OUT;
output RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT;
output RGMII_RX_CLK_OUT;
output RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT;
output RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT;
output RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT;
output RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT;
output RGMII_RXD3_USBB_DATA4_OUT;
output RGMII_TX_CLK_OUT;
output RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT;
output RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT;
output RGMII_TXD1_RMII_TXD1_USBB_STP_OUT;
output RGMII_TXD2_USBB_DATA5_OUT;
output RGMII_TXD3_USBB_DATA6_OUT;
output SPI0_SCK_USBA_XCLK_OUT;
output SPI0_SDI_USBA_DIR_MGPIO5A_OUT;
output SPI0_SDO_USBA_STP_MGPIO6A_OUT;
output SPI0_SS0_USBA_NXT_MGPIO7A_OUT;
output SPI0_SS1_USBA_DATA5_MGPIO8A_OUT;
output SPI0_SS2_USBA_DATA6_MGPIO9A_OUT;
output SPI0_SS3_USBA_DATA7_MGPIO10A_OUT;
output SPI0_SS4_MGPIO19A_OUT;
output SPI0_SS5_MGPIO20A_OUT;
output SPI0_SS6_MGPIO21A_OUT;
output SPI0_SS7_MGPIO22A_OUT;
output SPI1_SCK_OUT;
output SPI1_SDI_MGPIO11A_OUT;
output SPI1_SDO_MGPIO12A_OUT;
output SPI1_SS0_MGPIO13A_OUT;
output SPI1_SS1_MGPIO14A_OUT;
output SPI1_SS2_MGPIO15A_OUT;
output SPI1_SS3_MGPIO16A_OUT;
output SPI1_SS4_MGPIO17A_OUT;
output SPI1_SS5_MGPIO18A_OUT;
output SPI1_SS6_MGPIO23A_OUT;
output SPI1_SS7_MGPIO24A_OUT;
output USBC_XCLK_OUT;
output USBD_DATA0_OUT;
output USBD_DATA1_OUT;
output USBD_DATA2_OUT;
output USBD_DATA3_OUT;
output USBD_DATA4_OUT;
output USBD_DATA5_OUT;
output USBD_DATA6_OUT;
output USBD_DATA7_MGPIO23B_OUT;
output USBD_DIR_OUT;
output USBD_NXT_OUT;
output USBD_STP_OUT;
output USBD_XCLK_OUT;
output CAN_RXBUS_USBA_DATA1_MGPIO3A_OE;
output CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE;
output CAN_TXBUS_USBA_DATA0_MGPIO2A_OE;
output [2:0] DM_OE;
output [17:0] DRAM_DQ_OE;
output [2:0] DRAM_DQS_OE;
output I2C0_SCL_USBC_DATA1_MGPIO31B_OE;
output I2C0_SDA_USBC_DATA0_MGPIO30B_OE;
output I2C1_SCL_USBA_DATA4_MGPIO1A_OE;
output I2C1_SDA_USBA_DATA3_MGPIO0A_OE;
output MGPIO0B_OE;
output MGPIO10B_OE;
output MGPIO1B_OE;
output MGPIO25A_OE;
output MGPIO26A_OE;
output MGPIO27A_OE;
output MGPIO28A_OE;
output MGPIO29A_OE;
output MGPIO2B_OE;
output MGPIO30A_OE;
output MGPIO31A_OE;
output MGPIO3B_OE;
output MGPIO4B_OE;
output MGPIO5B_OE;
output MGPIO6B_OE;
output MGPIO7B_OE;
output MGPIO8B_OE;
output MGPIO9B_OE;
output MMUART0_CTS_USBC_DATA7_MGPIO19B_OE;
output MMUART0_DCD_MGPIO22B_OE;
output MMUART0_DSR_MGPIO20B_OE;
output MMUART0_DTR_USBC_DATA6_MGPIO18B_OE;
output MMUART0_RI_MGPIO21B_OE;
output MMUART0_RTS_USBC_DATA5_MGPIO17B_OE;
output MMUART0_RXD_USBC_STP_MGPIO28B_OE;
output MMUART0_SCK_USBC_NXT_MGPIO29B_OE;
output MMUART0_TXD_USBC_DIR_MGPIO27B_OE;
output MMUART1_CTS_MGPIO13B_OE;
output MMUART1_DCD_MGPIO16B_OE;
output MMUART1_DSR_MGPIO14B_OE;
output MMUART1_DTR_MGPIO12B_OE;
output MMUART1_RI_MGPIO15B_OE;
output MMUART1_RTS_MGPIO11B_OE;
output MMUART1_RXD_USBC_DATA3_MGPIO26B_OE;
output MMUART1_SCK_USBC_DATA4_MGPIO25B_OE;
output MMUART1_TXD_USBC_DATA2_MGPIO24B_OE;
output RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE;
output RGMII_MDC_RMII_MDC_OE;
output RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE;
output RGMII_RX_CLK_OE;
output RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE;
output RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE;
output RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE;
output RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE;
output RGMII_RXD3_USBB_DATA4_OE;
output RGMII_TX_CLK_OE;
output RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE;
output RGMII_TXD0_RMII_TXD0_USBB_DIR_OE;
output RGMII_TXD1_RMII_TXD1_USBB_STP_OE;
output RGMII_TXD2_USBB_DATA5_OE;
output RGMII_TXD3_USBB_DATA6_OE;
output SPI0_SCK_USBA_XCLK_OE;
output SPI0_SDI_USBA_DIR_MGPIO5A_OE;
output SPI0_SDO_USBA_STP_MGPIO6A_OE;
output SPI0_SS0_USBA_NXT_MGPIO7A_OE;
output SPI0_SS1_USBA_DATA5_MGPIO8A_OE;
output SPI0_SS2_USBA_DATA6_MGPIO9A_OE;
output SPI0_SS3_USBA_DATA7_MGPIO10A_OE;
output SPI0_SS4_MGPIO19A_OE;
output SPI0_SS5_MGPIO20A_OE;
output SPI0_SS6_MGPIO21A_OE;
output SPI0_SS7_MGPIO22A_OE;
output SPI1_SCK_OE;
output SPI1_SDI_MGPIO11A_OE;
output SPI1_SDO_MGPIO12A_OE;
output SPI1_SS0_MGPIO13A_OE;
output SPI1_SS1_MGPIO14A_OE;
output SPI1_SS2_MGPIO15A_OE;
output SPI1_SS3_MGPIO16A_OE;
output SPI1_SS4_MGPIO17A_OE;
output SPI1_SS5_MGPIO18A_OE;
output SPI1_SS6_MGPIO23A_OE;
output SPI1_SS7_MGPIO24A_OE;
output USBC_XCLK_OE;
output USBD_DATA0_OE;
output USBD_DATA1_OE;
output USBD_DATA2_OE;
output USBD_DATA3_OE;
output USBD_DATA4_OE;
output USBD_DATA5_OE;
output USBD_DATA6_OE;
output USBD_DATA7_MGPIO23B_OE;
output USBD_DIR_OE;
output USBD_NXT_OE;
output USBD_STP_OE;
output USBD_XCLK_OE;

    parameter INIT = 'h0 ;
    parameter ACT_UBITS = 'hFFFFFFFFFFFFFF ;
    parameter MEMORYFILE = "" ;
    parameter RTC_MAIN_XTL_FREQ = 0.0 ;
    parameter RTC_MAIN_XTL_MODE = "1" ;
    parameter DDR_CLK_FREQ = 0.0 ;
    
endmodule


module CoreAPB3_Z1(
       COREAHBTOAPB3_0_APBmaster_PADDR,
       CoreAPB3_0_APBmslave0_PSELx,
       COREAHBTOAPB3_0_APBmaster_PSELx
    );
input  [27:24] COREAHBTOAPB3_0_APBmaster_PADDR;
output CoreAPB3_0_APBmslave0_PSELx;
input  COREAHBTOAPB3_0_APBmaster_PSELx;

    wire \iPSELS_1[0]_net_1 , GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    CFG2 #( .INIT(4'h4) )  \iPSELS_1[0]  (.A(
        COREAHBTOAPB3_0_APBmaster_PADDR[25]), .B(
        COREAHBTOAPB3_0_APBmaster_PSELx), .Y(\iPSELS_1[0]_net_1 ));
    GND GND (.Y(GND_net_1));
    CFG4 #( .INIT(16'h0004) )  \iPSELS[0]  (.A(
        COREAHBTOAPB3_0_APBmaster_PADDR[24]), .B(\iPSELS_1[0]_net_1 ), 
        .C(COREAHBTOAPB3_0_APBmaster_PADDR[27]), .D(
        COREAHBTOAPB3_0_APBmaster_PADDR[26]), .Y(
        CoreAPB3_0_APBmslave0_PSELx));
    
endmodule


module mux_blk(
       mux_blk_0_raddr,
       raddr_user_c,
       mux_blk_0_waddr,
       CoreAPB3_0_APBmslave0_PADDR,
       waddr_user_c,
       mux_blk_0_wdata,
       CoreAPB3_0_APBmslave0_PWDATA,
       wdata_user_c,
       rdata_user_c,
       CoreAPB3_0_APBmslave0_PRDATA,
       mux_blk_0_wclk,
       wclk_user_c,
       mux_blk_0_rclk,
       FlashFreeze_SB_0_FIC_0_CLK,
       rclk_user_c,
       mux_blk_0_wr_en,
       mem_apb_wrp_0_wr_enable,
       wr_enable_user_c,
       mux_blk_0_rd_en,
       mem_apb_wrp_0_rd_enable,
       rd_enable_user_c,
       SEL_c
    );
output [5:0] mux_blk_0_raddr;
input  [5:0] raddr_user_c;
output [5:0] mux_blk_0_waddr;
input  [7:2] CoreAPB3_0_APBmslave0_PADDR;
input  [5:0] waddr_user_c;
output [7:0] mux_blk_0_wdata;
input  [7:0] CoreAPB3_0_APBmslave0_PWDATA;
input  [7:0] wdata_user_c;
output [7:0] rdata_user_c;
input  [7:0] CoreAPB3_0_APBmslave0_PRDATA;
output mux_blk_0_wclk;
input  wclk_user_c;
output mux_blk_0_rclk;
input  FlashFreeze_SB_0_FIC_0_CLK;
input  rclk_user_c;
output mux_blk_0_wr_en;
input  mem_apb_wrp_0_wr_enable;
input  wr_enable_user_c;
output mux_blk_0_rd_en;
input  mem_apb_wrp_0_rd_enable;
input  rd_enable_user_c;
input  SEL_c;

    wire GND_net_1, VCC_net_1;
    
    CFG3 #( .INIT(8'hB8) )  wclk (.A(wclk_user_c), .B(SEL_c), .C(
        FlashFreeze_SB_0_FIC_0_CLK), .Y(mux_blk_0_wclk));
    CFG2 #( .INIT(4'h8) )  \rdata_user[6]  (.A(
        CoreAPB3_0_APBmslave0_PRDATA[6]), .B(SEL_c), .Y(
        rdata_user_c[6]));
    CFG4 #( .INIT(16'hF7B3) )  \un7_waddr[3]  (.A(SEL_c), .B(
        mux_blk_0_wr_en), .C(waddr_user_c[3]), .D(
        CoreAPB3_0_APBmslave0_PADDR[5]), .Y(mux_blk_0_waddr[3]));
    CFG4 #( .INIT(16'hC480) )  \un8_raddr[2]  (.A(SEL_c), .B(
        mux_blk_0_rd_en), .C(raddr_user_c[2]), .D(
        CoreAPB3_0_APBmslave0_PADDR[4]), .Y(mux_blk_0_raddr[2]));
    CFG4 #( .INIT(16'hF7B3) )  \un7_waddr[0]  (.A(SEL_c), .B(
        mux_blk_0_wr_en), .C(waddr_user_c[0]), .D(
        CoreAPB3_0_APBmslave0_PADDR[2]), .Y(mux_blk_0_waddr[0]));
    CFG4 #( .INIT(16'hF7B3) )  \un7_waddr[1]  (.A(SEL_c), .B(
        mux_blk_0_wr_en), .C(waddr_user_c[1]), .D(
        CoreAPB3_0_APBmslave0_PADDR[3]), .Y(mux_blk_0_waddr[1]));
    CFG3 #( .INIT(8'hD8) )  \wdata[0]  (.A(SEL_c), .B(wdata_user_c[0]), 
        .C(CoreAPB3_0_APBmslave0_PWDATA[0]), .Y(mux_blk_0_wdata[0]));
    VCC VCC (.Y(VCC_net_1));
    CFG2 #( .INIT(4'h8) )  \rdata_user[7]  (.A(
        CoreAPB3_0_APBmslave0_PRDATA[7]), .B(SEL_c), .Y(
        rdata_user_c[7]));
    CFG4 #( .INIT(16'hC480) )  \un8_raddr[5]  (.A(SEL_c), .B(
        mux_blk_0_rd_en), .C(raddr_user_c[5]), .D(
        CoreAPB3_0_APBmslave0_PADDR[7]), .Y(mux_blk_0_raddr[5]));
    CFG3 #( .INIT(8'hD8) )  \wdata[1]  (.A(SEL_c), .B(wdata_user_c[1]), 
        .C(CoreAPB3_0_APBmslave0_PWDATA[1]), .Y(mux_blk_0_wdata[1]));
    CFG3 #( .INIT(8'hD8) )  \wdata[2]  (.A(SEL_c), .B(wdata_user_c[2]), 
        .C(CoreAPB3_0_APBmslave0_PWDATA[2]), .Y(mux_blk_0_wdata[2]));
    CFG3 #( .INIT(8'hD8) )  \wdata[3]  (.A(SEL_c), .B(wdata_user_c[3]), 
        .C(CoreAPB3_0_APBmslave0_PWDATA[3]), .Y(mux_blk_0_wdata[3]));
    CFG3 #( .INIT(8'hD8) )  \wdata[4]  (.A(SEL_c), .B(wdata_user_c[4]), 
        .C(CoreAPB3_0_APBmslave0_PWDATA[4]), .Y(mux_blk_0_wdata[4]));
    CFG4 #( .INIT(16'hC480) )  \un8_raddr[1]  (.A(SEL_c), .B(
        mux_blk_0_rd_en), .C(raddr_user_c[1]), .D(
        CoreAPB3_0_APBmslave0_PADDR[3]), .Y(mux_blk_0_raddr[1]));
    CFG4 #( .INIT(16'hF7B3) )  \un7_waddr[2]  (.A(SEL_c), .B(
        mux_blk_0_wr_en), .C(waddr_user_c[2]), .D(
        CoreAPB3_0_APBmslave0_PADDR[4]), .Y(mux_blk_0_waddr[2]));
    GND GND (.Y(GND_net_1));
    CFG4 #( .INIT(16'hF7B3) )  \un7_waddr[5]  (.A(SEL_c), .B(
        mux_blk_0_wr_en), .C(waddr_user_c[5]), .D(
        CoreAPB3_0_APBmslave0_PADDR[7]), .Y(mux_blk_0_waddr[5]));
    CFG3 #( .INIT(8'hD8) )  \wdata[5]  (.A(SEL_c), .B(wdata_user_c[5]), 
        .C(CoreAPB3_0_APBmslave0_PWDATA[5]), .Y(mux_blk_0_wdata[5]));
    CFG4 #( .INIT(16'hC480) )  \un8_raddr[4]  (.A(SEL_c), .B(
        mux_blk_0_rd_en), .C(raddr_user_c[4]), .D(
        CoreAPB3_0_APBmslave0_PADDR[6]), .Y(mux_blk_0_raddr[4]));
    CFG4 #( .INIT(16'hC480) )  \un8_raddr[0]  (.A(SEL_c), .B(
        mux_blk_0_rd_en), .C(raddr_user_c[0]), .D(
        CoreAPB3_0_APBmslave0_PADDR[2]), .Y(mux_blk_0_raddr[0]));
    CFG3 #( .INIT(8'hD8) )  \wdata[6]  (.A(SEL_c), .B(wdata_user_c[6]), 
        .C(CoreAPB3_0_APBmslave0_PWDATA[6]), .Y(mux_blk_0_wdata[6]));
    CFG2 #( .INIT(4'h8) )  \rdata_user[2]  (.A(
        CoreAPB3_0_APBmslave0_PRDATA[2]), .B(SEL_c), .Y(
        rdata_user_c[2]));
    CFG2 #( .INIT(4'h8) )  \rdata_user[1]  (.A(
        CoreAPB3_0_APBmslave0_PRDATA[1]), .B(SEL_c), .Y(
        rdata_user_c[1]));
    CFG2 #( .INIT(4'h8) )  \rdata_user[3]  (.A(
        CoreAPB3_0_APBmslave0_PRDATA[3]), .B(SEL_c), .Y(
        rdata_user_c[3]));
    CFG2 #( .INIT(4'h8) )  \rdata_user[5]  (.A(
        CoreAPB3_0_APBmslave0_PRDATA[5]), .B(SEL_c), .Y(
        rdata_user_c[5]));
    CFG4 #( .INIT(16'hF7B3) )  \un7_waddr[4]  (.A(SEL_c), .B(
        mux_blk_0_wr_en), .C(waddr_user_c[4]), .D(
        CoreAPB3_0_APBmslave0_PADDR[6]), .Y(mux_blk_0_waddr[4]));
    CFG4 #( .INIT(16'hC480) )  \un8_raddr[3]  (.A(SEL_c), .B(
        mux_blk_0_rd_en), .C(raddr_user_c[3]), .D(
        CoreAPB3_0_APBmslave0_PADDR[5]), .Y(mux_blk_0_raddr[3]));
    CFG3 #( .INIT(8'hD8) )  rd_en (.A(SEL_c), .B(rd_enable_user_c), .C(
        mem_apb_wrp_0_rd_enable), .Y(mux_blk_0_rd_en));
    CFG2 #( .INIT(4'h8) )  \rdata_user[0]  (.A(
        CoreAPB3_0_APBmslave0_PRDATA[0]), .B(SEL_c), .Y(
        rdata_user_c[0]));
    CFG3 #( .INIT(8'hD8) )  \wdata[7]  (.A(SEL_c), .B(wdata_user_c[7]), 
        .C(CoreAPB3_0_APBmslave0_PWDATA[7]), .Y(mux_blk_0_wdata[7]));
    CFG3 #( .INIT(8'hB8) )  rclk (.A(rclk_user_c), .B(SEL_c), .C(
        FlashFreeze_SB_0_FIC_0_CLK), .Y(mux_blk_0_rclk));
    CFG2 #( .INIT(4'h8) )  \rdata_user[4]  (.A(
        CoreAPB3_0_APBmslave0_PRDATA[4]), .B(SEL_c), .Y(
        rdata_user_c[4]));
    CFG3 #( .INIT(8'hD8) )  wr_en (.A(SEL_c), .B(wr_enable_user_c), .C(
        mem_apb_wrp_0_wr_enable), .Y(mux_blk_0_wr_en));
    
endmodule


module RAM_with_wrapper_SRAM_64x8_0_TPSRAM(
       mux_blk_0_waddr,
       mux_blk_0_wdata,
       mux_blk_0_raddr,
       CoreAPB3_0_APBmslave0_PRDATA,
       mux_blk_0_wr_en,
       mux_blk_0_wclk,
       mux_blk_0_rd_en,
       mux_blk_0_rclk
    );
input  [5:0] mux_blk_0_waddr;
input  [7:0] mux_blk_0_wdata;
input  [5:0] mux_blk_0_raddr;
output [7:0] CoreAPB3_0_APBmslave0_PRDATA;
input  mux_blk_0_wr_en;
input  mux_blk_0_wclk;
input  mux_blk_0_rd_en;
input  mux_blk_0_rclk;

    wire VCC_net_1, GND_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    RAM1K18 RAM_with_wrapper_SRAM_64x8_0_TPSRAM_R0C0 (.A_DOUT({nc0, 
        nc1, nc2, nc3, nc4, nc5, nc6, nc7, nc8, nc9, 
        CoreAPB3_0_APBmslave0_PRDATA[7], 
        CoreAPB3_0_APBmslave0_PRDATA[6], 
        CoreAPB3_0_APBmslave0_PRDATA[5], 
        CoreAPB3_0_APBmslave0_PRDATA[4], 
        CoreAPB3_0_APBmslave0_PRDATA[3], 
        CoreAPB3_0_APBmslave0_PRDATA[2], 
        CoreAPB3_0_APBmslave0_PRDATA[1], 
        CoreAPB3_0_APBmslave0_PRDATA[0]}), .B_DOUT({nc10, nc11, nc12, 
        nc13, nc14, nc15, nc16, nc17, nc18, nc19, nc20, nc21, nc22, 
        nc23, nc24, nc25, nc26, nc27}), .BUSY(), .A_CLK(mux_blk_0_rclk)
        , .A_DOUT_CLK(VCC_net_1), .A_ARST_N(VCC_net_1), .A_DOUT_EN(
        VCC_net_1), .A_BLK({mux_blk_0_rd_en, VCC_net_1, VCC_net_1}), 
        .A_DOUT_ARST_N(VCC_net_1), .A_DOUT_SRST_N(VCC_net_1), .A_DIN({
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1}), .A_ADDR({GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, mux_blk_0_raddr[5], 
        mux_blk_0_raddr[4], mux_blk_0_raddr[3], mux_blk_0_raddr[2], 
        mux_blk_0_raddr[1], mux_blk_0_raddr[0], GND_net_1, GND_net_1, 
        GND_net_1}), .A_WEN({GND_net_1, GND_net_1}), .B_CLK(
        mux_blk_0_wclk), .B_DOUT_CLK(VCC_net_1), .B_ARST_N(VCC_net_1), 
        .B_DOUT_EN(VCC_net_1), .B_BLK({mux_blk_0_wr_en, VCC_net_1, 
        VCC_net_1}), .B_DOUT_ARST_N(GND_net_1), .B_DOUT_SRST_N(
        VCC_net_1), .B_DIN({GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, mux_blk_0_wdata[7], mux_blk_0_wdata[6], 
        mux_blk_0_wdata[5], mux_blk_0_wdata[4], mux_blk_0_wdata[3], 
        mux_blk_0_wdata[2], mux_blk_0_wdata[1], mux_blk_0_wdata[0]}), 
        .B_ADDR({GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        mux_blk_0_waddr[5], mux_blk_0_waddr[4], mux_blk_0_waddr[3], 
        mux_blk_0_waddr[2], mux_blk_0_waddr[1], mux_blk_0_waddr[0], 
        GND_net_1, GND_net_1, GND_net_1}), .B_WEN({GND_net_1, 
        VCC_net_1}), .A_EN(VCC_net_1), .A_DOUT_LAT(VCC_net_1), 
        .A_WIDTH({GND_net_1, VCC_net_1, VCC_net_1}), .A_WMODE(
        GND_net_1), .B_EN(VCC_net_1), .B_DOUT_LAT(VCC_net_1), .B_WIDTH({
        GND_net_1, VCC_net_1, VCC_net_1}), .B_WMODE(GND_net_1), 
        .SII_LOCK(GND_net_1));
    GND GND (.Y(GND_net_1));
    
endmodule


module mem_apb_wrp_8s_8s(
       CoreAPB3_0_APBmslave0_PADDR,
       CoreAPB3_0_APBmslave0_PRDATA_m,
       CoreAPB3_0_APBmslave0_PRDATA,
       CoreAPB3_0_APBmslave0_PSELx,
       CoreAPB3_0_APBmslave0_PWRITE,
       mem_apb_wrp_0_wr_enable,
       SEL_c,
       mem_apb_wrp_0_rd_enable,
       FlashFreeze_SB_0_FIC_0_CLK,
       FlashFreeze_SB_0_POWER_ON_RESET_N,
       CoreAPB3_0_APBmslave0_PREADY
    );
input  [7:0] CoreAPB3_0_APBmslave0_PADDR;
output [7:0] CoreAPB3_0_APBmslave0_PRDATA_m;
input  [7:0] CoreAPB3_0_APBmslave0_PRDATA;
input  CoreAPB3_0_APBmslave0_PSELx;
input  CoreAPB3_0_APBmslave0_PWRITE;
output mem_apb_wrp_0_wr_enable;
output SEL_c;
output mem_apb_wrp_0_rd_enable;
input  FlashFreeze_SB_0_FIC_0_CLK;
input  FlashFreeze_SB_0_POWER_ON_RESET_N;
output CoreAPB3_0_APBmslave0_PREADY;

    wire GND_net_1, N_91_i, N_47_i, VCC_net_1, 
        PREADY_3_0_0_46_i_a2_net_1, N_57_i, INT_OUT_0_sqmuxa_net_1, 
        wr_enable_5_0_a2_0_31_a2_net_1, N_50_i, \fsm[0]_net_1 , 
        \fsm_ns[0] , \fsm[1]_net_1 , \fsm_ns[1] , 
        INT_OUT_0_sqmuxa_4_net_1, INT_OUT_0_sqmuxa_6_net_1, 
        INT_OUT_0_sqmuxa_8_net_1;
    
    CFG2 #( .INIT(4'h8) )  \CoreAPB3_0_APBmslave0_PRDATA_m[2]  (.A(
        CoreAPB3_0_APBmslave0_PRDATA[2]), .B(
        CoreAPB3_0_APBmslave0_PSELx), .Y(
        CoreAPB3_0_APBmslave0_PRDATA_m[2]));
    CFG2 #( .INIT(4'h8) )  \CoreAPB3_0_APBmslave0_PRDATA_m[1]  (.A(
        CoreAPB3_0_APBmslave0_PRDATA[1]), .B(
        CoreAPB3_0_APBmslave0_PSELx), .Y(
        CoreAPB3_0_APBmslave0_PRDATA_m[1]));
    CFG2 #( .INIT(4'hE) )  PREADY_3_0_0_46_i_a2_i (.A(
        CoreAPB3_0_APBmslave0_PWRITE), .B(\fsm[1]_net_1 ), .Y(N_91_i));
    SLE \fsm[1]  (.D(\fsm_ns[1] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\fsm[1]_net_1 ));
    CFG2 #( .INIT(4'h1) )  PREADY_3_0_0_46_i_a2 (.A(
        CoreAPB3_0_APBmslave0_PWRITE), .B(\fsm[1]_net_1 ), .Y(
        PREADY_3_0_0_46_i_a2_net_1));
    SLE rd_enable (.D(PREADY_3_0_0_46_i_a2_net_1), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(N_57_i), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        mem_apb_wrp_0_rd_enable));
    GND GND (.Y(GND_net_1));
    SLE wr_enable (.D(wr_enable_5_0_a2_0_31_a2_net_1), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(N_50_i), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        mem_apb_wrp_0_wr_enable));
    CFG2 #( .INIT(4'h2) )  wr_enable_5_0_a2_0_31_a2 (.A(
        CoreAPB3_0_APBmslave0_PWRITE), .B(\fsm[0]_net_1 ), .Y(
        wr_enable_5_0_a2_0_31_a2_net_1));
    CFG2 #( .INIT(4'h8) )  \CoreAPB3_0_APBmslave0_PRDATA_m[5]  (.A(
        CoreAPB3_0_APBmslave0_PRDATA[5]), .B(
        CoreAPB3_0_APBmslave0_PSELx), .Y(
        CoreAPB3_0_APBmslave0_PRDATA_m[5]));
    CFG2 #( .INIT(4'h8) )  \CoreAPB3_0_APBmslave0_PRDATA_m[4]  (.A(
        CoreAPB3_0_APBmslave0_PRDATA[4]), .B(
        CoreAPB3_0_APBmslave0_PSELx), .Y(
        CoreAPB3_0_APBmslave0_PRDATA_m[4]));
    CFG2 #( .INIT(4'h8) )  \CoreAPB3_0_APBmslave0_PRDATA_m[0]  (.A(
        CoreAPB3_0_APBmslave0_PRDATA[0]), .B(
        CoreAPB3_0_APBmslave0_PSELx), .Y(
        CoreAPB3_0_APBmslave0_PRDATA_m[0]));
    CFG2 #( .INIT(4'h8) )  \CoreAPB3_0_APBmslave0_PRDATA_m[7]  (.A(
        CoreAPB3_0_APBmslave0_PRDATA[7]), .B(
        CoreAPB3_0_APBmslave0_PSELx), .Y(
        CoreAPB3_0_APBmslave0_PRDATA_m[7]));
    CFG2 #( .INIT(4'h8) )  \CoreAPB3_0_APBmslave0_PRDATA_m[6]  (.A(
        CoreAPB3_0_APBmslave0_PRDATA[6]), .B(
        CoreAPB3_0_APBmslave0_PSELx), .Y(
        CoreAPB3_0_APBmslave0_PRDATA_m[6]));
    SLE \fsm[0]  (.D(\fsm_ns[0] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\fsm[0]_net_1 ));
    CFG3 #( .INIT(8'hF4) )  rd_enable_RNO (.A(\fsm[1]_net_1 ), .B(
        CoreAPB3_0_APBmslave0_PSELx), .C(\fsm[0]_net_1 ), .Y(N_57_i));
    SLE PREADY (.D(N_91_i), .CLK(FlashFreeze_SB_0_FIC_0_CLK), .EN(
        N_47_i), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        GND_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(CoreAPB3_0_APBmslave0_PREADY));
    CFG4 #( .INIT(16'h0100) )  INT_OUT_0_sqmuxa_8 (.A(
        CoreAPB3_0_APBmslave0_PADDR[1]), .B(
        CoreAPB3_0_APBmslave0_PADDR[0]), .C(\fsm[1]_net_1 ), .D(
        INT_OUT_0_sqmuxa_6_net_1), .Y(INT_OUT_0_sqmuxa_8_net_1));
    CFG2 #( .INIT(4'h8) )  INT_OUT_0_sqmuxa_4 (.A(
        CoreAPB3_0_APBmslave0_PWRITE), .B(\fsm[0]_net_1 ), .Y(
        INT_OUT_0_sqmuxa_4_net_1));
    CFG3 #( .INIT(8'h1A) )  \fsm_ns_1_0_.m4  (.A(\fsm[1]_net_1 ), .B(
        CoreAPB3_0_APBmslave0_PWRITE), .C(\fsm[0]_net_1 ), .Y(
        \fsm_ns[1] ));
    VCC VCC (.Y(VCC_net_1));
    SLE SEL (.D(VCC_net_1), .CLK(FlashFreeze_SB_0_FIC_0_CLK), .EN(
        INT_OUT_0_sqmuxa_net_1), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(SEL_c));
    CFG3 #( .INIT(8'h5E) )  PREADY_RNO (.A(\fsm[1]_net_1 ), .B(
        CoreAPB3_0_APBmslave0_PSELx), .C(\fsm[0]_net_1 ), .Y(N_47_i));
    CFG3 #( .INIT(8'h54) )  wr_enable_RNO (.A(\fsm[1]_net_1 ), .B(
        CoreAPB3_0_APBmslave0_PSELx), .C(\fsm[0]_net_1 ), .Y(N_50_i));
    CFG4 #( .INIT(16'h8000) )  INT_OUT_0_sqmuxa_6 (.A(
        CoreAPB3_0_APBmslave0_PADDR[7]), .B(
        CoreAPB3_0_APBmslave0_PADDR[6]), .C(
        CoreAPB3_0_APBmslave0_PADDR[5]), .D(
        CoreAPB3_0_APBmslave0_PADDR[4]), .Y(INT_OUT_0_sqmuxa_6_net_1));
    CFG4 #( .INIT(16'h8000) )  INT_OUT_0_sqmuxa (.A(
        CoreAPB3_0_APBmslave0_PADDR[2]), .B(
        CoreAPB3_0_APBmslave0_PADDR[3]), .C(INT_OUT_0_sqmuxa_8_net_1), 
        .D(INT_OUT_0_sqmuxa_4_net_1), .Y(INT_OUT_0_sqmuxa_net_1));
    CFG2 #( .INIT(4'h8) )  \CoreAPB3_0_APBmslave0_PRDATA_m[3]  (.A(
        CoreAPB3_0_APBmslave0_PRDATA[3]), .B(
        CoreAPB3_0_APBmslave0_PSELx), .Y(
        CoreAPB3_0_APBmslave0_PRDATA_m[3]));
    CFG3 #( .INIT(8'h0E) )  \fsm_ns_1_0_.m2  (.A(\fsm[1]_net_1 ), .B(
        CoreAPB3_0_APBmslave0_PSELx), .C(\fsm[0]_net_1 ), .Y(
        \fsm_ns[0] ));
    
endmodule


module RAM_with_wrapper(
       rdata_user_c,
       wdata_user_c,
       CoreAPB3_0_APBmslave0_PWDATA,
       waddr_user_c,
       raddr_user_c,
       CoreAPB3_0_APBmslave0_PRDATA_m,
       CoreAPB3_0_APBmslave0_PADDR,
       rd_enable_user_c,
       wr_enable_user_c,
       rclk_user_c,
       wclk_user_c,
       CoreAPB3_0_APBmslave0_PREADY,
       FlashFreeze_SB_0_POWER_ON_RESET_N,
       FlashFreeze_SB_0_FIC_0_CLK,
       SEL_c,
       CoreAPB3_0_APBmslave0_PWRITE,
       CoreAPB3_0_APBmslave0_PSELx
    );
output [7:0] rdata_user_c;
input  [7:0] wdata_user_c;
input  [7:0] CoreAPB3_0_APBmslave0_PWDATA;
input  [5:0] waddr_user_c;
input  [5:0] raddr_user_c;
output [7:0] CoreAPB3_0_APBmslave0_PRDATA_m;
input  [7:0] CoreAPB3_0_APBmslave0_PADDR;
input  rd_enable_user_c;
input  wr_enable_user_c;
input  rclk_user_c;
input  wclk_user_c;
output CoreAPB3_0_APBmslave0_PREADY;
input  FlashFreeze_SB_0_POWER_ON_RESET_N;
input  FlashFreeze_SB_0_FIC_0_CLK;
output SEL_c;
input  CoreAPB3_0_APBmslave0_PWRITE;
input  CoreAPB3_0_APBmslave0_PSELx;

    wire \CoreAPB3_0_APBmslave0_PRDATA[0] , 
        \CoreAPB3_0_APBmslave0_PRDATA[1] , 
        \CoreAPB3_0_APBmslave0_PRDATA[2] , 
        \CoreAPB3_0_APBmslave0_PRDATA[3] , 
        \CoreAPB3_0_APBmslave0_PRDATA[4] , 
        \CoreAPB3_0_APBmslave0_PRDATA[5] , 
        \CoreAPB3_0_APBmslave0_PRDATA[6] , 
        \CoreAPB3_0_APBmslave0_PRDATA[7] , mem_apb_wrp_0_wr_enable, 
        mem_apb_wrp_0_rd_enable, \mux_blk_0_raddr[0] , 
        \mux_blk_0_raddr[1] , \mux_blk_0_raddr[2] , 
        \mux_blk_0_raddr[3] , \mux_blk_0_raddr[4] , 
        \mux_blk_0_raddr[5] , \mux_blk_0_waddr[0] , 
        \mux_blk_0_waddr[1] , \mux_blk_0_waddr[2] , 
        \mux_blk_0_waddr[3] , \mux_blk_0_waddr[4] , 
        \mux_blk_0_waddr[5] , \mux_blk_0_wdata[0] , 
        \mux_blk_0_wdata[1] , \mux_blk_0_wdata[2] , 
        \mux_blk_0_wdata[3] , \mux_blk_0_wdata[4] , 
        \mux_blk_0_wdata[5] , \mux_blk_0_wdata[6] , 
        \mux_blk_0_wdata[7] , mux_blk_0_wclk, mux_blk_0_rclk, 
        mux_blk_0_wr_en, mux_blk_0_rd_en, GND_net_1, VCC_net_1;
    
    mux_blk mux_blk_0 (.mux_blk_0_raddr({\mux_blk_0_raddr[5] , 
        \mux_blk_0_raddr[4] , \mux_blk_0_raddr[3] , 
        \mux_blk_0_raddr[2] , \mux_blk_0_raddr[1] , 
        \mux_blk_0_raddr[0] }), .raddr_user_c({raddr_user_c[5], 
        raddr_user_c[4], raddr_user_c[3], raddr_user_c[2], 
        raddr_user_c[1], raddr_user_c[0]}), .mux_blk_0_waddr({
        \mux_blk_0_waddr[5] , \mux_blk_0_waddr[4] , 
        \mux_blk_0_waddr[3] , \mux_blk_0_waddr[2] , 
        \mux_blk_0_waddr[1] , \mux_blk_0_waddr[0] }), 
        .CoreAPB3_0_APBmslave0_PADDR({CoreAPB3_0_APBmslave0_PADDR[7], 
        CoreAPB3_0_APBmslave0_PADDR[6], CoreAPB3_0_APBmslave0_PADDR[5], 
        CoreAPB3_0_APBmslave0_PADDR[4], CoreAPB3_0_APBmslave0_PADDR[3], 
        CoreAPB3_0_APBmslave0_PADDR[2]}), .waddr_user_c({
        waddr_user_c[5], waddr_user_c[4], waddr_user_c[3], 
        waddr_user_c[2], waddr_user_c[1], waddr_user_c[0]}), 
        .mux_blk_0_wdata({\mux_blk_0_wdata[7] , \mux_blk_0_wdata[6] , 
        \mux_blk_0_wdata[5] , \mux_blk_0_wdata[4] , 
        \mux_blk_0_wdata[3] , \mux_blk_0_wdata[2] , 
        \mux_blk_0_wdata[1] , \mux_blk_0_wdata[0] }), 
        .CoreAPB3_0_APBmslave0_PWDATA({CoreAPB3_0_APBmslave0_PWDATA[7], 
        CoreAPB3_0_APBmslave0_PWDATA[6], 
        CoreAPB3_0_APBmslave0_PWDATA[5], 
        CoreAPB3_0_APBmslave0_PWDATA[4], 
        CoreAPB3_0_APBmslave0_PWDATA[3], 
        CoreAPB3_0_APBmslave0_PWDATA[2], 
        CoreAPB3_0_APBmslave0_PWDATA[1], 
        CoreAPB3_0_APBmslave0_PWDATA[0]}), .wdata_user_c({
        wdata_user_c[7], wdata_user_c[6], wdata_user_c[5], 
        wdata_user_c[4], wdata_user_c[3], wdata_user_c[2], 
        wdata_user_c[1], wdata_user_c[0]}), .rdata_user_c({
        rdata_user_c[7], rdata_user_c[6], rdata_user_c[5], 
        rdata_user_c[4], rdata_user_c[3], rdata_user_c[2], 
        rdata_user_c[1], rdata_user_c[0]}), 
        .CoreAPB3_0_APBmslave0_PRDATA({
        \CoreAPB3_0_APBmslave0_PRDATA[7] , 
        \CoreAPB3_0_APBmslave0_PRDATA[6] , 
        \CoreAPB3_0_APBmslave0_PRDATA[5] , 
        \CoreAPB3_0_APBmslave0_PRDATA[4] , 
        \CoreAPB3_0_APBmslave0_PRDATA[3] , 
        \CoreAPB3_0_APBmslave0_PRDATA[2] , 
        \CoreAPB3_0_APBmslave0_PRDATA[1] , 
        \CoreAPB3_0_APBmslave0_PRDATA[0] }), .mux_blk_0_wclk(
        mux_blk_0_wclk), .wclk_user_c(wclk_user_c), .mux_blk_0_rclk(
        mux_blk_0_rclk), .FlashFreeze_SB_0_FIC_0_CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .rclk_user_c(rclk_user_c), 
        .mux_blk_0_wr_en(mux_blk_0_wr_en), .mem_apb_wrp_0_wr_enable(
        mem_apb_wrp_0_wr_enable), .wr_enable_user_c(wr_enable_user_c), 
        .mux_blk_0_rd_en(mux_blk_0_rd_en), .mem_apb_wrp_0_rd_enable(
        mem_apb_wrp_0_rd_enable), .rd_enable_user_c(rd_enable_user_c), 
        .SEL_c(SEL_c));
    VCC VCC (.Y(VCC_net_1));
    RAM_with_wrapper_SRAM_64x8_0_TPSRAM SRAM_64x8_0 (.mux_blk_0_waddr({
        \mux_blk_0_waddr[5] , \mux_blk_0_waddr[4] , 
        \mux_blk_0_waddr[3] , \mux_blk_0_waddr[2] , 
        \mux_blk_0_waddr[1] , \mux_blk_0_waddr[0] }), .mux_blk_0_wdata({
        \mux_blk_0_wdata[7] , \mux_blk_0_wdata[6] , 
        \mux_blk_0_wdata[5] , \mux_blk_0_wdata[4] , 
        \mux_blk_0_wdata[3] , \mux_blk_0_wdata[2] , 
        \mux_blk_0_wdata[1] , \mux_blk_0_wdata[0] }), .mux_blk_0_raddr({
        \mux_blk_0_raddr[5] , \mux_blk_0_raddr[4] , 
        \mux_blk_0_raddr[3] , \mux_blk_0_raddr[2] , 
        \mux_blk_0_raddr[1] , \mux_blk_0_raddr[0] }), 
        .CoreAPB3_0_APBmslave0_PRDATA({
        \CoreAPB3_0_APBmslave0_PRDATA[7] , 
        \CoreAPB3_0_APBmslave0_PRDATA[6] , 
        \CoreAPB3_0_APBmslave0_PRDATA[5] , 
        \CoreAPB3_0_APBmslave0_PRDATA[4] , 
        \CoreAPB3_0_APBmslave0_PRDATA[3] , 
        \CoreAPB3_0_APBmslave0_PRDATA[2] , 
        \CoreAPB3_0_APBmslave0_PRDATA[1] , 
        \CoreAPB3_0_APBmslave0_PRDATA[0] }), .mux_blk_0_wr_en(
        mux_blk_0_wr_en), .mux_blk_0_wclk(mux_blk_0_wclk), 
        .mux_blk_0_rd_en(mux_blk_0_rd_en), .mux_blk_0_rclk(
        mux_blk_0_rclk));
    mem_apb_wrp_8s_8s mem_apb_wrp_0 (.CoreAPB3_0_APBmslave0_PADDR({
        CoreAPB3_0_APBmslave0_PADDR[7], CoreAPB3_0_APBmslave0_PADDR[6], 
        CoreAPB3_0_APBmslave0_PADDR[5], CoreAPB3_0_APBmslave0_PADDR[4], 
        CoreAPB3_0_APBmslave0_PADDR[3], CoreAPB3_0_APBmslave0_PADDR[2], 
        CoreAPB3_0_APBmslave0_PADDR[1], CoreAPB3_0_APBmslave0_PADDR[0]})
        , .CoreAPB3_0_APBmslave0_PRDATA_m({
        CoreAPB3_0_APBmslave0_PRDATA_m[7], 
        CoreAPB3_0_APBmslave0_PRDATA_m[6], 
        CoreAPB3_0_APBmslave0_PRDATA_m[5], 
        CoreAPB3_0_APBmslave0_PRDATA_m[4], 
        CoreAPB3_0_APBmslave0_PRDATA_m[3], 
        CoreAPB3_0_APBmslave0_PRDATA_m[2], 
        CoreAPB3_0_APBmslave0_PRDATA_m[1], 
        CoreAPB3_0_APBmslave0_PRDATA_m[0]}), 
        .CoreAPB3_0_APBmslave0_PRDATA({
        \CoreAPB3_0_APBmslave0_PRDATA[7] , 
        \CoreAPB3_0_APBmslave0_PRDATA[6] , 
        \CoreAPB3_0_APBmslave0_PRDATA[5] , 
        \CoreAPB3_0_APBmslave0_PRDATA[4] , 
        \CoreAPB3_0_APBmslave0_PRDATA[3] , 
        \CoreAPB3_0_APBmslave0_PRDATA[2] , 
        \CoreAPB3_0_APBmslave0_PRDATA[1] , 
        \CoreAPB3_0_APBmslave0_PRDATA[0] }), 
        .CoreAPB3_0_APBmslave0_PSELx(CoreAPB3_0_APBmslave0_PSELx), 
        .CoreAPB3_0_APBmslave0_PWRITE(CoreAPB3_0_APBmslave0_PWRITE), 
        .mem_apb_wrp_0_wr_enable(mem_apb_wrp_0_wr_enable), .SEL_c(
        SEL_c), .mem_apb_wrp_0_rd_enable(mem_apb_wrp_0_rd_enable), 
        .FlashFreeze_SB_0_FIC_0_CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .FlashFreeze_SB_0_POWER_ON_RESET_N(
        FlashFreeze_SB_0_POWER_ON_RESET_N), 
        .CoreAPB3_0_APBmslave0_PREADY(CoreAPB3_0_APBmslave0_PREADY));
    GND GND (.Y(GND_net_1));
    
endmodule


module FlashFreeze_SB_FABOSC_0_OSC(
       FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC
    );
output FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC;

    wire GND_net_1, VCC_net_1;
    
    RCOSC_25_50MHZ #( .FREQUENCY(50.0) )  I_RCOSC_25_50MHZ (.CLKOUT(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC));
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    
endmodule


module CoreResetP_Z6(
       FlashFreeze_SB_MSS_TMP_0_MSS_RESET_N_M2F,
       FlashFreeze_SB_MSS_TMP_0_FIC_2_APB_M_PRESET_N,
       FlashFreeze_SB_0_POWER_ON_RESET_N,
       FLASH_FREEZE_0_FF_DONE,
       FlashFreeze_SB_0_FIC_0_CLK,
       un1_FlashFreeze_SB_0_1_i_i
    );
input  FlashFreeze_SB_MSS_TMP_0_MSS_RESET_N_M2F;
input  FlashFreeze_SB_MSS_TMP_0_FIC_2_APB_M_PRESET_N;
input  FlashFreeze_SB_0_POWER_ON_RESET_N;
input  FLASH_FREEZE_0_FF_DONE;
input  FlashFreeze_SB_0_FIC_0_CLK;
output un1_FlashFreeze_SB_0_1_i_i;

    wire MSS_HPMS_READY_int_RNIU0AN_net_1, mss_ready_select_net_1, 
        VCC_net_1, POWER_ON_RESET_N_clk_base_i_i, 
        mss_ready_select4_net_1, GND_net_1, mss_ready_state_net_1, 
        RESET_N_M2F_clk_base_net_1, RESET_N_M2F_q2_net_1, 
        in_RESET_N_M2F_i_i, RESET_N_M2F_q1_net_1, 
        FIC_2_APB_M_PRESET_N_q2_net_1, in_FIC_2_APB_M_PRESET_N_i_i, 
        FIC_2_APB_M_PRESET_N_q1_net_1, MSS_HPMS_READY_int_net_1, 
        MSS_HPMS_READY_int_4_net_1, POWER_ON_RESET_N_q1_net_1, 
        in_POWER_ON_RESET_N_i_i, POWER_ON_RESET_N_q2_net_1;
    
    SLE MSS_HPMS_READY_int (.D(MSS_HPMS_READY_int_4_net_1), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        POWER_ON_RESET_N_clk_base_i_i), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        MSS_HPMS_READY_int_net_1));
    CFG2 #( .INIT(4'hE) )  MSS_HPMS_READY_int_RNIU0AN (.A(
        FLASH_FREEZE_0_FF_DONE), .B(MSS_HPMS_READY_int_net_1), .Y(
        MSS_HPMS_READY_int_RNIU0AN_net_1));
    SLE FIC_2_APB_M_PRESET_N_q1 (.D(VCC_net_1), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        in_FIC_2_APB_M_PRESET_N_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        FIC_2_APB_M_PRESET_N_q1_net_1));
    SLE POWER_ON_RESET_N_q1 (.D(VCC_net_1), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        in_POWER_ON_RESET_N_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(POWER_ON_RESET_N_q1_net_1));
    SLE RESET_N_M2F_q2 (.D(RESET_N_M2F_q1_net_1), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        in_RESET_N_M2F_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), .SD(
        GND_net_1), .LAT(GND_net_1), .Q(RESET_N_M2F_q2_net_1));
    CFG2 #( .INIT(4'hE) )  in_POWER_ON_RESET_N_i (.A(
        FLASH_FREEZE_0_FF_DONE), .B(FlashFreeze_SB_0_POWER_ON_RESET_N), 
        .Y(in_POWER_ON_RESET_N_i_i));
    GND GND (.Y(GND_net_1));
    CFG2 #( .INIT(4'hE) )  RESET_N_M2F_clk_base (.A(
        FLASH_FREEZE_0_FF_DONE), .B(RESET_N_M2F_q2_net_1), .Y(
        RESET_N_M2F_clk_base_net_1));
    CLKINT MSS_HPMS_READY_int_RNIU0AN_0 (.A(
        MSS_HPMS_READY_int_RNIU0AN_net_1), .Y(
        un1_FlashFreeze_SB_0_1_i_i));
    CFG2 #( .INIT(4'hE) )  POWER_ON_RESET_N_q2_RNIGNGN (.A(
        FLASH_FREEZE_0_FF_DONE), .B(POWER_ON_RESET_N_q2_net_1), .Y(
        POWER_ON_RESET_N_clk_base_i_i));
    SLE RESET_N_M2F_q1 (.D(VCC_net_1), .CLK(FlashFreeze_SB_0_FIC_0_CLK)
        , .EN(VCC_net_1), .ALn(in_RESET_N_M2F_i_i), .ADn(VCC_net_1), 
        .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        RESET_N_M2F_q1_net_1));
    SLE POWER_ON_RESET_N_q2 (.D(POWER_ON_RESET_N_q1_net_1), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        in_POWER_ON_RESET_N_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(POWER_ON_RESET_N_q2_net_1));
    VCC VCC (.Y(VCC_net_1));
    SLE mss_ready_state (.D(VCC_net_1), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(RESET_N_M2F_clk_base_net_1), 
        .ALn(POWER_ON_RESET_N_clk_base_i_i), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        mss_ready_state_net_1));
    CFG2 #( .INIT(4'hE) )  in_FIC_2_APB_M_PRESET_N_i (.A(
        FLASH_FREEZE_0_FF_DONE), .B(
        FlashFreeze_SB_MSS_TMP_0_FIC_2_APB_M_PRESET_N), .Y(
        in_FIC_2_APB_M_PRESET_N_i_i));
    CFG3 #( .INIT(8'hA8) )  mss_ready_select4 (.A(
        mss_ready_state_net_1), .B(FIC_2_APB_M_PRESET_N_q2_net_1), .C(
        FLASH_FREEZE_0_FF_DONE), .Y(mss_ready_select4_net_1));
    CFG2 #( .INIT(4'hE) )  in_RESET_N_M2F_i (.A(FLASH_FREEZE_0_FF_DONE)
        , .B(FlashFreeze_SB_MSS_TMP_0_MSS_RESET_N_M2F), .Y(
        in_RESET_N_M2F_i_i));
    SLE FIC_2_APB_M_PRESET_N_q2 (.D(FIC_2_APB_M_PRESET_N_q1_net_1), 
        .CLK(FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        in_FIC_2_APB_M_PRESET_N_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        FIC_2_APB_M_PRESET_N_q2_net_1));
    SLE mss_ready_select (.D(VCC_net_1), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(mss_ready_select4_net_1), 
        .ALn(POWER_ON_RESET_N_clk_base_i_i), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        mss_ready_select_net_1));
    CFG4 #( .INIT(16'hFFE0) )  MSS_HPMS_READY_int_4 (.A(
        mss_ready_select_net_1), .B(RESET_N_M2F_q2_net_1), .C(
        FIC_2_APB_M_PRESET_N_q2_net_1), .D(FLASH_FREEZE_0_FF_DONE), .Y(
        MSS_HPMS_READY_int_4_net_1));
    
endmodule


module COREAHBLITE_SLAVEARBITER_Z4_0(
       M0GATEDHADDR,
       masterAddrInProg_0,
       CAHBtoAPB3IOI_0,
       CAHBtoAPB3lI,
       m19_e_0,
       N_153_mux,
       N_12_i,
       N_151,
       N_55_i,
       N_190,
       N_57_i,
       N_189,
       N_59_i,
       N_188,
       N_61_i,
       N_187,
       N_123_i,
       N_186,
       N_125_i,
       N_185,
       N_51_i,
       N_192,
       N_122_i_0,
       N_191,
       N_126_i_0,
       N_128_i_0,
       N_129_i,
       N_131_i,
       N_132_i,
       FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY,
       N_171_mux,
       m52_N_7L11,
       m52_N_3L3,
       FlashFreeze_SB_0_FIC_0_CLK,
       un1_FlashFreeze_SB_0_1_i_i
    );
input  [27:24] M0GATEDHADDR;
output masterAddrInProg_0;
input  CAHBtoAPB3IOI_0;
output CAHBtoAPB3lI;
input  m19_e_0;
input  N_153_mux;
output N_12_i;
input  N_151;
output N_55_i;
input  N_190;
output N_57_i;
input  N_189;
output N_59_i;
input  N_188;
output N_61_i;
input  N_187;
output N_123_i;
input  N_186;
output N_125_i;
input  N_185;
output N_51_i;
input  N_192;
output N_122_i_0;
input  N_191;
output N_126_i_0;
output N_128_i_0;
output N_129_i;
output N_131_i;
input  N_132_i;
input  FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY;
output N_171_mux;
input  m52_N_7L11;
input  m52_N_3L3;
input  FlashFreeze_SB_0_FIC_0_CLK;
input  un1_FlashFreeze_SB_0_1_i_i;

    wire \arbRegSMCurrentState[14]_net_1 , VCC_net_1, N_126_i, 
        GND_net_1, \masterAddrInProg[3] , N_128_i, 
        \arbRegSMCurrentState[0]_net_1 , N_104_i, 
        \arbRegSMCurrentState[1]_net_1 , N_106_i, 
        \arbRegSMCurrentState[2]_net_1 , N_108_i, 
        \arbRegSMCurrentState[3]_net_1 , N_110_i, 
        \arbRegSMCurrentState[5]_net_1 , 
        \arbRegSMCurrentState_ns[5]_net_1 , 
        \arbRegSMCurrentState[6]_net_1 , N_114_i, HSEL7_sn, N_116_i, 
        \arbRegSMCurrentState[9]_net_1 , 
        \arbRegSMCurrentState_ns[9]_net_1 , 
        \arbRegSMCurrentState[10]_net_1 , N_120_i, 
        \masterAddrInProg[2] , N_122_i, 
        \arbRegSMCurrentState[13]_net_1 , 
        \arbRegSMCurrentState_ns[13]_net_1 , N_106_i_1, N_139, N_156;
    
    CFG4 #( .INIT(16'hBEFE) )  \arbRegSMCurrentState_RNO[1]  (.A(
        \arbRegSMCurrentState[2]_net_1 ), .B(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .C(N_106_i_1), .D(N_139)
        , .Y(N_106_i));
    CFG2 #( .INIT(4'h8) )  
        \arbRegSMCurrentState_ns_i_a2_0_RNICR762[0]  (.A(
        masterAddrInProg_0), .B(N_189), .Y(N_57_i));
    CFG4 #( .INIT(16'h2000) )  
        \arbRegSMCurrentState_ns_i_a2_0_RNILFFV4[0]  (.A(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .B(N_153_mux), .C(
        m19_e_0), .D(masterAddrInProg_0), .Y(CAHBtoAPB3lI));
    CFG2 #( .INIT(4'h8) )  
        \arbRegSMCurrentState_ns_i_a2_0_RNIFU762[0]  (.A(
        masterAddrInProg_0), .B(N_186), .Y(N_123_i));
    CFG2 #( .INIT(4'h4) )  \arbRegSMCurrentState_RNO[11]  (.A(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .B(
        \masterAddrInProg[2] ), .Y(N_122_i));
    SLE \arbRegSMCurrentState[3]  (.D(N_110_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[3]_net_1 ));
    CFG3 #( .INIT(8'hAE) )  \arbRegSMCurrentState_ns[13]  (.A(
        \arbRegSMCurrentState[14]_net_1 ), .B(
        \arbRegSMCurrentState[13]_net_1 ), .C(N_132_i), .Y(
        \arbRegSMCurrentState_ns[13]_net_1 ));
    CFG2 #( .INIT(4'h8) )  
        \arbRegSMCurrentState_ns_i_a2_0_RNIGV762[0]  (.A(
        masterAddrInProg_0), .B(N_185), .Y(N_125_i));
    CFG2 #( .INIT(4'h8) )  
        \arbRegSMCurrentState_ns_i_a2_0_RNIAP762[0]  (.A(
        masterAddrInProg_0), .B(N_191), .Y(N_122_i_0));
    CFG3 #( .INIT(8'hAE) )  \arbRegSMCurrentState_ns[9]  (.A(
        \arbRegSMCurrentState[10]_net_1 ), .B(
        \arbRegSMCurrentState[9]_net_1 ), .C(N_132_i), .Y(
        \arbRegSMCurrentState_ns[9]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \arbRegSMCurrentState_RNO[2]  (.A(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .B(
        \arbRegSMCurrentState[3]_net_1 ), .Y(N_108_i));
    CFG2 #( .INIT(4'h4) )  \arbRegSMCurrentState_RNO[7]  (.A(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .B(HSEL7_sn), .Y(
        N_116_i));
    SLE \arbRegSMCurrentState[10]  (.D(N_120_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[10]_net_1 ));
    CFG2 #( .INIT(4'h8) )  
        \arbRegSMCurrentState_ns_i_a2_0_RNIDS762[0]  (.A(
        masterAddrInProg_0), .B(N_188), .Y(N_59_i));
    CFG4 #( .INIT(16'h101A) )  \arbRegSMCurrentState_RNO_0[1]  (.A(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .B(N_132_i), .C(
        \arbRegSMCurrentState[1]_net_1 ), .D(
        \arbRegSMCurrentState[0]_net_1 ), .Y(N_106_i_1));
    VCC VCC (.Y(VCC_net_1));
    CFG2 #( .INIT(4'h8) )  
        \arbRegSMCurrentState_ns_i_a2_0_RNIET762[0]  (.A(
        masterAddrInProg_0), .B(N_187), .Y(N_61_i));
    CFG4 #( .INIT(16'h4454) )  \arbRegSMCurrentState_RNO[0]  (.A(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .B(
        \arbRegSMCurrentState[0]_net_1 ), .C(N_132_i), .D(N_156), .Y(
        N_104_i));
    SLE \arbRegSMCurrentState[0]  (.D(N_104_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[0]_net_1 ));
    SLE \arbRegSMCurrentState[7]  (.D(N_116_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(HSEL7_sn));
    CFG2 #( .INIT(4'h4) )  \arbRegSMCurrentState_RNO[15]  (.A(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .B(
        \masterAddrInProg[3] ), .Y(N_128_i));
    CFG2 #( .INIT(4'h8) )  
        \arbRegSMCurrentState_ns_i_a2_0_RNIBQ762[0]  (.A(
        masterAddrInProg_0), .B(N_190), .Y(N_55_i));
    SLE \arbRegSMCurrentState[14]  (.D(N_126_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[14]_net_1 ));
    CFG4 #( .INIT(16'h01FF) )  \arbRegSMCurrentState_ns_i_o2_0[1]  (.A(
        \arbRegSMCurrentState[13]_net_1 ), .B(
        \arbRegSMCurrentState[9]_net_1 ), .C(
        \arbRegSMCurrentState[5]_net_1 ), .D(N_132_i), .Y(N_139));
    SLE \arbRegSMCurrentState[6]  (.D(N_114_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[6]_net_1 ));
    SLE \arbRegSMCurrentState[1]  (.D(N_106_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[1]_net_1 ));
    CFG2 #( .INIT(4'h8) )  \arbRegSMCurrentState_RNO[6]  (.A(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .B(HSEL7_sn), .Y(
        N_114_i));
    CFG2 #( .INIT(4'h8) )  \arbRegSMCurrentState_RNO[10]  (.A(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .B(
        \masterAddrInProg[2] ), .Y(N_120_i));
    GND GND (.Y(GND_net_1));
    CFG2 #( .INIT(4'h8) )  
        \arbRegSMCurrentState_ns_i_a2_0_RNIPK282[0]  (.A(
        masterAddrInProg_0), .B(M0GATEDHADDR[25]), .Y(N_128_i_0));
    CFG4 #( .INIT(16'hC444) )  
        \arbRegSMCurrentState_ns_i_a2_0_RNITVFK8[0]  (.A(
        CAHBtoAPB3IOI_0), .B(m52_N_3L3), .C(m52_N_7L11), .D(
        masterAddrInProg_0), .Y(N_171_mux));
    CFG2 #( .INIT(4'h2) )  
        \arbRegSMCurrentState_ns_i_a2_0_RNIKK9H2[0]  (.A(
        masterAddrInProg_0), .B(N_151), .Y(N_12_i));
    CFG2 #( .INIT(4'h8) )  
        \arbRegSMCurrentState_ns_i_a2_0_RNI9O762[0]  (.A(
        masterAddrInProg_0), .B(N_192), .Y(N_51_i));
    CFG2 #( .INIT(4'h8) )  \arbRegSMCurrentState_RNO[14]  (.A(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .B(
        \masterAddrInProg[3] ), .Y(N_126_i));
    SLE \arbRegSMCurrentState[9]  (.D(
        \arbRegSMCurrentState_ns[9]_net_1 ), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[9]_net_1 ));
    CFG4 #( .INIT(16'h0001) )  \arbRegSMCurrentState_ns_i_a2_0[0]  (.A(
        \arbRegSMCurrentState[9]_net_1 ), .B(
        \arbRegSMCurrentState[5]_net_1 ), .C(
        \arbRegSMCurrentState[1]_net_1 ), .D(
        \arbRegSMCurrentState[13]_net_1 ), .Y(N_156));
    SLE \arbRegSMCurrentState[13]  (.D(
        \arbRegSMCurrentState_ns[13]_net_1 ), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(GND_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[13]_net_1 ));
    SLE \arbRegSMCurrentState[11]  (.D(N_122_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\masterAddrInProg[2] ));
    SLE \arbRegSMCurrentState[2]  (.D(N_108_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[2]_net_1 ));
    CFG4 #( .INIT(16'hEFEE) )  
        \arbRegSMCurrentState_ns_i_a2_0_RNIP4O12[0]  (.A(
        \arbRegSMCurrentState[3]_net_1 ), .B(
        \arbRegSMCurrentState[0]_net_1 ), .C(N_156), .D(N_132_i), .Y(
        masterAddrInProg_0));
    CFG2 #( .INIT(4'h8) )  
        \arbRegSMCurrentState_ns_i_a2_0_RNIOJ282[0]  (.A(
        masterAddrInProg_0), .B(M0GATEDHADDR[24]), .Y(N_126_i_0));
    SLE \arbRegSMCurrentState[5]  (.D(
        \arbRegSMCurrentState_ns[5]_net_1 ), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \arbRegSMCurrentState[5]_net_1 ));
    SLE \arbRegSMCurrentState[15]  (.D(N_128_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\masterAddrInProg[3] ));
    CFG2 #( .INIT(4'h8) )  
        \arbRegSMCurrentState_ns_i_a2_0_RNIRM282[0]  (.A(
        masterAddrInProg_0), .B(M0GATEDHADDR[27]), .Y(N_131_i));
    CFG3 #( .INIT(8'hAE) )  \arbRegSMCurrentState_ns[5]  (.A(
        \arbRegSMCurrentState[6]_net_1 ), .B(
        \arbRegSMCurrentState[5]_net_1 ), .C(N_132_i), .Y(
        \arbRegSMCurrentState_ns[5]_net_1 ));
    CFG2 #( .INIT(4'h8) )  
        \arbRegSMCurrentState_ns_i_a2_0_RNIQL282[0]  (.A(
        masterAddrInProg_0), .B(M0GATEDHADDR[26]), .Y(N_129_i));
    CFG2 #( .INIT(4'h4) )  \arbRegSMCurrentState_RNO[3]  (.A(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .B(
        \arbRegSMCurrentState[3]_net_1 ), .Y(N_110_i));
    
endmodule


module COREAHBLITE_SLAVESTAGE_0s_0_0_1(
       M0GATEDHADDR,
       FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA,
       CAHBtoAPB3IOI_3,
       CAHBtoAPB3IOI_0,
       CAHBtoAPB3IOI_4,
       masterAddrInProg_0,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0,
       masterDataInProg_0,
       N_171_mux,
       N_132_i,
       N_131_i,
       N_129_i,
       N_128_i,
       N_126_i,
       N_191,
       N_122_i,
       N_192,
       N_51_i,
       N_185,
       N_125_i,
       N_186,
       N_123_i,
       N_187,
       N_61_i,
       N_188,
       N_59_i,
       N_189,
       N_57_i,
       N_190,
       N_55_i,
       N_12_i,
       CAHBtoAPB3lI,
       N_177_mux_i,
       N_179_mux,
       N_247_mux,
       N_178_mux,
       N_248,
       PREVDATASLAVEREADY_iv_i_0,
       m19_e_0,
       defSlaveSMNextState,
       m0s0DataSel,
       N_56_0_i,
       N_153_mux,
       CAHBtoAPB3OI,
       N_63_0,
       N_54_0,
       PENABLE,
       CoreAPB3_0_APBmslave0_PREADY,
       CoreAPB3_0_APBmslave0_PSELx,
       N_25_0,
       CAHBtoAPB3III,
       N_151,
       CAHBtoAPB3II,
       N_181_mux_i,
       N_250,
       un1_SDATASELInt_34_i,
       FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY,
       regHTRANS,
       regHWRITE,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE,
       masterRegAddrSel,
       CAHBtoAPB3lII,
       CAHBtoAPB3ll4,
       CoreAPB3_0_APBmslave0_PWRITE,
       m23_i_a5_0_0,
       m23_e_8_0,
       m23_e_6_0,
       m23_e_7_0,
       FlashFreeze_SB_0_FIC_0_CLK,
       un1_FlashFreeze_SB_0_1_i_i
    );
input  [27:24] M0GATEDHADDR;
output [7:0] FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA;
input  [7:0] FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA;
input  CAHBtoAPB3IOI_3;
input  CAHBtoAPB3IOI_0;
input  CAHBtoAPB3IOI_4;
output masterAddrInProg_0;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0;
output masterDataInProg_0;
output N_171_mux;
input  N_132_i;
output N_131_i;
output N_129_i;
output N_128_i;
output N_126_i;
input  N_191;
output N_122_i;
input  N_192;
output N_51_i;
input  N_185;
output N_125_i;
input  N_186;
output N_123_i;
input  N_187;
output N_61_i;
input  N_188;
output N_59_i;
input  N_189;
output N_57_i;
input  N_190;
output N_55_i;
output N_12_i;
output CAHBtoAPB3lI;
output N_177_mux_i;
output N_179_mux;
output N_247_mux;
output N_178_mux;
input  N_248;
output PREVDATASLAVEREADY_iv_i_0;
output m19_e_0;
input  defSlaveSMNextState;
input  m0s0DataSel;
output N_56_0_i;
output N_153_mux;
input  CAHBtoAPB3OI;
output N_63_0;
output N_54_0;
input  PENABLE;
input  CoreAPB3_0_APBmslave0_PREADY;
input  CoreAPB3_0_APBmslave0_PSELx;
output N_25_0;
input  CAHBtoAPB3III;
output N_151;
output CAHBtoAPB3II;
output N_181_mux_i;
input  N_250;
input  un1_SDATASELInt_34_i;
input  FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY;
input  regHTRANS;
input  regHWRITE;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE;
input  masterRegAddrSel;
input  CAHBtoAPB3lII;
input  CAHBtoAPB3ll4;
input  CoreAPB3_0_APBmslave0_PWRITE;
input  m23_i_a5_0_0;
input  m23_e_8_0;
input  m23_e_6_0;
input  m23_e_7_0;
input  FlashFreeze_SB_0_FIC_0_CLK;
input  un1_FlashFreeze_SB_0_1_i_i;

    wire VCC_net_1, masterDataInProg_55_net_1, GND_net_1, 
        m52_N_4L5_net_1, m26_1_0_net_1, m52_N_6L9_net_1, 
        m52_N_7L11_1_net_1, m52_N_7L11_net_1, m52_N_3L3_net_1, 
        N_181_mux_i_1_net_1, N_158_mux, N_30_0, i25_mux, N_65_0, 
        N_10_0, N_12_0, N_39_0, N_157, N_14_0;
    
    CFG3 #( .INIT(8'h13) )  m53 (.A(CAHBtoAPB3ll4), .B(CAHBtoAPB3IOI_0)
        , .C(CoreAPB3_0_APBmslave0_PWRITE), .Y(N_54_0));
    CFG2 #( .INIT(4'h1) )  m52_N_3L3 (.A(CoreAPB3_0_APBmslave0_PWRITE), 
        .B(CAHBtoAPB3IOI_3), .Y(m52_N_3L3_net_1));
    CFG4 #( .INIT(16'hACAF) )  N_177_mux_i_inst_1 (.A(CAHBtoAPB3II), 
        .B(CAHBtoAPB3IOI_0), .C(N_250), .D(N_39_0), .Y(N_177_mux_i));
    CFG3 #( .INIT(8'hAC) )  m13 (.A(N_10_0), .B(N_12_0), .C(N_151), .Y(
        N_14_0));
    VCC VCC (.Y(VCC_net_1));
    CFG4 #( .INIT(16'h5044) )  m19 (.A(CAHBtoAPB3OI), .B(N_12_0), .C(
        N_14_0), .D(N_250), .Y(N_179_mux));
    CFG4 #( .INIT(16'h3EFA) )  m26_1_0 (.A(
        CoreAPB3_0_APBmslave0_PWRITE), .B(CAHBtoAPB3ll4), .C(
        CAHBtoAPB3lII), .D(CAHBtoAPB3IOI_3), .Y(m26_1_0_net_1));
    CFG4 #( .INIT(16'hA200) )  m21 (.A(CAHBtoAPB3IOI_3), .B(
        CoreAPB3_0_APBmslave0_PSELx), .C(CoreAPB3_0_APBmslave0_PREADY), 
        .D(PENABLE), .Y(CAHBtoAPB3II));
    CFG4 #( .INIT(16'h7F00) )  m52_N_4L5 (.A(m23_e_7_0), .B(m23_e_6_0), 
        .C(m23_e_8_0), .D(m23_i_a5_0_0), .Y(m52_N_4L5_net_1));
    CFG2 #( .INIT(4'h8) )  \HWDATA[0]  (.A(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[0]), .B(
        masterDataInProg_0), .Y(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[0]));
    CFG3 #( .INIT(8'h07) )  m9 (.A(CAHBtoAPB3ll4), .B(CAHBtoAPB3IOI_3), 
        .C(CoreAPB3_0_APBmslave0_PWRITE), .Y(N_10_0));
    CFG2 #( .INIT(4'h8) )  \HWDATA[4]  (.A(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[4]), .B(
        masterDataInProg_0), .Y(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[4]));
    CFG3 #( .INIT(8'h53) )  m38 (.A(CAHBtoAPB3II), .B(N_25_0), .C(
        CAHBtoAPB3lII), .Y(N_39_0));
    CFG3 #( .INIT(8'hA8) )  m24 (.A(CAHBtoAPB3ll4), .B(CAHBtoAPB3IOI_3)
        , .C(CoreAPB3_0_APBmslave0_PWRITE), .Y(N_25_0));
    GND GND (.Y(GND_net_1));
    SLE \masterDataInProg[0]  (.D(masterDataInProg_55_net_1), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(masterDataInProg_0));
    CFG3 #( .INIT(8'h31) )  m61 (.A(CAHBtoAPB3IOI_0), .B(N_25_0), .C(
        N_248), .Y(N_178_mux));
    CFG4 #( .INIT(16'h43CB) )  m26 (.A(CAHBtoAPB3III), .B(
        CAHBtoAPB3lII), .C(m26_1_0_net_1), .D(N_25_0), .Y(i25_mux));
    CFG3 #( .INIT(8'hF4) )  N_56_0_i_inst_1 (.A(CAHBtoAPB3ll4), .B(
        CoreAPB3_0_APBmslave0_PWRITE), .C(CAHBtoAPB3OI), .Y(N_56_0_i));
    CFG2 #( .INIT(4'h8) )  \HWDATA[3]  (.A(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[3]), .B(
        masterDataInProg_0), .Y(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[3]));
    CFG3 #( .INIT(8'h80) )  m62 (.A(CAHBtoAPB3ll4), .B(CAHBtoAPB3lII), 
        .C(CoreAPB3_0_APBmslave0_PWRITE), .Y(N_63_0));
    CFG3 #( .INIT(8'h1B) )  m150 (.A(masterRegAddrSel), .B(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE), .C(
        regHWRITE), .Y(N_151));
    CFG2 #( .INIT(4'h8) )  \HWDATA[5]  (.A(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[5]), .B(
        masterDataInProg_0), .Y(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[5]));
    CFG3 #( .INIT(8'h80) )  m64 (.A(CAHBtoAPB3ll4), .B(N_151), .C(
        CoreAPB3_0_APBmslave0_PWRITE), .Y(N_65_0));
    CFG4 #( .INIT(16'h0313) )  m29 (.A(CAHBtoAPB3IOI_3), .B(
        CAHBtoAPB3IOI_0), .C(CAHBtoAPB3ll4), .D(
        CoreAPB3_0_APBmslave0_PWRITE), .Y(N_30_0));
    CFG3 #( .INIT(8'hD8) )  masterDataInProg_55 (.A(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .B(masterAddrInProg_0), 
        .C(masterDataInProg_0), .Y(masterDataInProg_55_net_1));
    CFG3 #( .INIT(8'h47) )  N_181_mux_i_inst_1 (.A(N_181_mux_i_1_net_1)
        , .B(N_250), .C(N_158_mux), .Y(N_181_mux_i));
    CFG2 #( .INIT(4'h8) )  \HWDATA[7]  (.A(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[7]), .B(
        masterDataInProg_0), .Y(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[7]));
    CFG4 #( .INIT(16'h1B11) )  m52_N_7L11_1 (.A(masterRegAddrSel), .B(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0), .C(
        regHWRITE), .D(regHTRANS), .Y(m52_N_7L11_1_net_1));
    CFG2 #( .INIT(4'h8) )  \HWDATA[1]  (.A(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[1]), .B(
        masterDataInProg_0), .Y(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[1]));
    CFG3 #( .INIT(8'h5D) )  m52_N_6L9 (.A(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .B(m52_N_4L5_net_1), .C(
        un1_SDATASELInt_34_i), .Y(m52_N_6L9_net_1));
    CFG2 #( .INIT(4'h8) )  \HWDATA[6]  (.A(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[6]), .B(
        masterDataInProg_0), .Y(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[6]));
    COREAHBLITE_SLAVEARBITER_Z4_0 slave_arbiter (.M0GATEDHADDR({
        M0GATEDHADDR[27], M0GATEDHADDR[26], M0GATEDHADDR[25], 
        M0GATEDHADDR[24]}), .masterAddrInProg_0(masterAddrInProg_0), 
        .CAHBtoAPB3IOI_0(CAHBtoAPB3IOI_0), .CAHBtoAPB3lI(CAHBtoAPB3lI), 
        .m19_e_0(m19_e_0), .N_153_mux(N_153_mux), .N_12_i(N_12_i), 
        .N_151(N_151), .N_55_i(N_55_i), .N_190(N_190), .N_57_i(N_57_i), 
        .N_189(N_189), .N_59_i(N_59_i), .N_188(N_188), .N_61_i(N_61_i), 
        .N_187(N_187), .N_123_i(N_123_i), .N_186(N_186), .N_125_i(
        N_125_i), .N_185(N_185), .N_51_i(N_51_i), .N_192(N_192), 
        .N_122_i_0(N_122_i), .N_191(N_191), .N_126_i_0(N_126_i), 
        .N_128_i_0(N_128_i), .N_129_i(N_129_i), .N_131_i(N_131_i), 
        .N_132_i(N_132_i), .FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .N_171_mux(N_171_mux), 
        .m52_N_7L11(m52_N_7L11_net_1), .m52_N_3L3(m52_N_3L3_net_1), 
        .FlashFreeze_SB_0_FIC_0_CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .un1_FlashFreeze_SB_0_1_i_i(un1_FlashFreeze_SB_0_1_i_i));
    CFG3 #( .INIT(8'h04) )  m17_e (.A(m0s0DataSel), .B(
        defSlaveSMNextState), .C(un1_SDATASELInt_34_i), .Y(N_157));
    CFG2 #( .INIT(4'h8) )  \HWDATA[2]  (.A(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[2]), .B(
        masterDataInProg_0), .Y(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[2]));
    CFG4 #( .INIT(16'h0F0B) )  m76 (.A(CAHBtoAPB3lII), .B(
        CoreAPB3_0_APBmslave0_PWRITE), .C(CAHBtoAPB3OI), .D(
        CAHBtoAPB3ll4), .Y(N_153_mux));
    CFG3 #( .INIT(8'h5C) )  N_181_mux_i_1 (.A(CAHBtoAPB3II), .B(N_30_0)
        , .C(N_151), .Y(N_181_mux_i_1_net_1));
    CFG4 #( .INIT(16'hF044) )  m69 (.A(CAHBtoAPB3III), .B(N_63_0), .C(
        N_65_0), .D(N_250), .Y(N_247_mux));
    CFG4 #( .INIT(16'h020E) )  m11 (.A(CAHBtoAPB3IOI_4), .B(
        CAHBtoAPB3IOI_3), .C(CoreAPB3_0_APBmslave0_PWRITE), .D(
        CAHBtoAPB3ll4), .Y(N_12_0));
    CFG3 #( .INIT(8'h04) )  m28 (.A(CAHBtoAPB3OI), .B(i25_mux), .C(
        CAHBtoAPB3IOI_0), .Y(N_158_mux));
    CFG4 #( .INIT(16'h4041) )  m52_N_7L11 (.A(m52_N_6L9_net_1), .B(
        masterRegAddrSel), .C(m52_N_7L11_1_net_1), .D(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE), .Y(
        m52_N_7L11_net_1));
    CFG4 #( .INIT(16'hDD0D) )  m3 (.A(defSlaveSMNextState), .B(
        un1_SDATASELInt_34_i), .C(m0s0DataSel), .D(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .Y(
        PREVDATASLAVEREADY_iv_i_0));
    CFG4 #( .INIT(16'h0B08) )  m19_e_0_inst_1 (.A(regHTRANS), .B(
        masterRegAddrSel), .C(N_157), .D(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0), .Y(
        m19_e_0));
    
endmodule


module COREAHBLITE_DEFAULTSLAVESM_0s_0_1_0(
       N_149_i,
       N_144,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HRESP_0,
       un1_SDATASELInt_34_i,
       DEFSLAVEDATASEL_9,
       DEFSLAVEDATASEL_11,
       DEFSLAVEDATASEL_10,
       m23_i_a5_0_0,
       m0s0DataSel,
       defSlaveSMNextState,
       FlashFreeze_SB_0_FIC_0_CLK,
       un1_FlashFreeze_SB_0_1_i_i
    );
output N_149_i;
input  N_144;
output FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HRESP_0;
input  un1_SDATASELInt_34_i;
input  DEFSLAVEDATASEL_9;
input  DEFSLAVEDATASEL_11;
input  DEFSLAVEDATASEL_10;
output m23_i_a5_0_0;
input  m0s0DataSel;
output defSlaveSMNextState;
input  FlashFreeze_SB_0_FIC_0_CLK;
input  un1_FlashFreeze_SB_0_1_i_i;

    wire defSlaveSMCurrentState_net_1, VCC_net_1, GND_net_1, 
        HRESP_DEFAULT_net_1;
    
    CFG4 #( .INIT(16'h0DDD) )  defSlaveSMNextState_RNIRDAP1 (.A(
        defSlaveSMNextState), .B(un1_SDATASELInt_34_i), .C(m0s0DataSel)
        , .D(N_144), .Y(N_149_i));
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    CFG4 #( .INIT(16'h3332) )  defSlaveSMNextState_inst_1 (.A(
        DEFSLAVEDATASEL_10), .B(defSlaveSMCurrentState_net_1), .C(
        DEFSLAVEDATASEL_11), .D(DEFSLAVEDATASEL_9), .Y(
        defSlaveSMNextState));
    CFG4 #( .INIT(16'hFFFE) )  HRESP_DEFAULT (.A(DEFSLAVEDATASEL_10), 
        .B(defSlaveSMCurrentState_net_1), .C(DEFSLAVEDATASEL_11), .D(
        DEFSLAVEDATASEL_9), .Y(HRESP_DEFAULT_net_1));
    CFG2 #( .INIT(4'h1) )  defSlaveSMCurrentState_RNI25ND (.A(
        m0s0DataSel), .B(defSlaveSMCurrentState_net_1), .Y(
        m23_i_a5_0_0));
    CFG2 #( .INIT(4'h4) )  HRESP_DEFAULT_RNIB5PE (.A(
        un1_SDATASELInt_34_i), .B(HRESP_DEFAULT_net_1), .Y(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HRESP_0));
    SLE defSlaveSMCurrentState (.D(defSlaveSMNextState), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(
        defSlaveSMCurrentState_net_1));
    
endmodule


module COREAHBLITE_MASTERSTAGE_2_1_0_1_0s_0_1_0(
       M0GATEDHADDR,
       masterDataInProg_0,
       masterAddrInProg_0,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_24,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_25,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_26,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_27,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_7,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_0,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_1,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_2,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_3,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_4,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_5,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_6,
       defSlaveSMNextState,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HRESP_0,
       N_149_i,
       N_192,
       N_191,
       N_190,
       N_189,
       N_188,
       N_187,
       N_186,
       N_185,
       N_248,
       un1_SDATASELInt_34_i,
       m23_i_a5_0_0,
       FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY,
       m23_e_6_0,
       m23_e_7_0,
       m23_e_8_0,
       N_132_i,
       masterRegAddrSel,
       regHTRANS,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE,
       regHWRITE,
       m0s0DataSel,
       PREVDATASLAVEREADY_iv_i_0,
       FlashFreeze_SB_0_FIC_0_CLK,
       un1_FlashFreeze_SB_0_1_i_i
    );
output [27:24] M0GATEDHADDR;
input  masterDataInProg_0;
input  masterAddrInProg_0;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_24;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_25;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_26;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_27;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_7;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_0;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_1;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_2;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_3;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_4;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_5;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_6;
output defSlaveSMNextState;
output FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HRESP_0;
output N_149_i;
output N_192;
output N_191;
output N_190;
output N_189;
output N_188;
output N_187;
output N_186;
output N_185;
output N_248;
output un1_SDATASELInt_34_i;
output m23_i_a5_0_0;
input  FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY;
output m23_e_6_0;
output m23_e_7_0;
output m23_e_8_0;
output N_132_i;
output masterRegAddrSel;
output regHTRANS;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE;
output regHWRITE;
output m0s0DataSel;
input  PREVDATASLAVEREADY_iv_i_0;
input  FlashFreeze_SB_0_FIC_0_CLK;
input  un1_FlashFreeze_SB_0_1_i_i;

    wire \regHADDR[24]_net_1 , VCC_net_1, N_134_i, GND_net_1, 
        \regHADDR[25]_net_1 , \regHADDR[26]_net_1 , 
        \regHADDR[27]_net_1 , \regHADDR[7]_net_1 , 
        \SDATASELInt[9]_net_1 , N_114_i, \SDATASELInt[10]_net_1 , 
        N_35_i, \SDATASELInt[11]_net_1 , N_37_i, 
        \SDATASELInt[12]_net_1 , N_39_i, \SDATASELInt[13]_net_1 , 
        N_41_i, \SDATASELInt[14]_net_1 , N_116_i, 
        \SDATASELInt[15]_net_1 , N_117_i, \regHADDR[0]_net_1 , 
        \regHADDR[1]_net_1 , \regHADDR[2]_net_1 , \regHADDR[3]_net_1 , 
        \regHADDR[4]_net_1 , \regHADDR[5]_net_1 , \regHADDR[6]_net_1 , 
        SDATASELInt_2_net_1, \SDATASELInt[1]_net_1 , N_119_i, 
        \SDATASELInt[2]_net_1 , N_120_i, \SDATASELInt[3]_net_1 , 
        N_107_i, \SDATASELInt[4]_net_1 , N_108_i, 
        \SDATASELInt[5]_net_1 , N_110_i, \SDATASELInt[6]_net_1 , 
        N_27_i, \SDATASELInt[7]_net_1 , N_111_i, 
        \SDATASELInt[8]_net_1 , N_113_i, N_135_i, N_132_i_1, N_14_0_0, 
        DEFSLAVEDATASEL_8_net_1, m23_i_0_0, m23_e_9_0, N_15_0, 
        un1_SDATASELInt_31_i, N_144, un1_SDATASELInt_31_11_net_1, 
        un1_SDATASELInt_31_10_net_1, un1_SDATASELInt_31_9_net_1, 
        un1_SDATASELInt_31_8_net_1, DEFSLAVEDATASEL_10_net_1, 
        DEFSLAVEDATASEL_9_net_1, N_146, N_147, 
        DEFSLAVEDATASEL_11_net_1, N_134_2, 
        masterAddrClockEnable_i_1_net_1, d_masterRegAddrSel_i_0_net_1;
    
    CFG4 #( .INIT(16'h0001) )  \SDATASELInt_RNO[2]  (.A(
        M0GATEDHADDR[24]), .B(M0GATEDHADDR[27]), .C(M0GATEDHADDR[26]), 
        .D(N_147), .Y(N_120_i));
    CFG3 #( .INIT(8'hE4) )  \PREGATEDHADDR_i_m3[5]  (.A(
        masterRegAddrSel), .B(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_5), .C(
        \regHADDR[5]_net_1 ), .Y(N_187));
    CFG4 #( .INIT(16'h0400) )  regHWRITE_RNIFIEE7 (.A(m23_i_0_0), .B(
        masterAddrInProg_0), .C(N_15_0), .D(N_14_0_0), .Y(N_248));
    CFG3 #( .INIT(8'hE4) )  \PREGATEDHADDR[24]  (.A(masterRegAddrSel), 
        .B(FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_24), .C(
        \regHADDR[24]_net_1 ), .Y(M0GATEDHADDR[24]));
    CFG4 #( .INIT(16'hFFFE) )  DEFSLAVEDATASEL_10 (.A(
        \SDATASELInt[6]_net_1 ), .B(\SDATASELInt[4]_net_1 ), .C(
        \SDATASELInt[3]_net_1 ), .D(\SDATASELInt[1]_net_1 ), .Y(
        DEFSLAVEDATASEL_10_net_1));
    SLE \regHADDR[7]  (.D(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_7), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(N_134_i), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\regHADDR[7]_net_1 ));
    CFG4 #( .INIT(16'h0020) )  \SDATASELInt_RNO[5]  (.A(
        M0GATEDHADDR[24]), .B(M0GATEDHADDR[27]), .C(M0GATEDHADDR[26]), 
        .D(N_146), .Y(N_110_i));
    CFG4 #( .INIT(16'h0100) )  \PREGATEDHADDR_RNIQF0C1[25]  (.A(
        M0GATEDHADDR[25]), .B(M0GATEDHADDR[27]), .C(M0GATEDHADDR[26]), 
        .D(N_132_i_1), .Y(N_132_i));
    CFG4 #( .INIT(16'h0001) )  DEFSLAVEDATASEL_8_RNI7OM81 (.A(
        \SDATASELInt[8]_net_1 ), .B(\SDATASELInt[7]_net_1 ), .C(
        \SDATASELInt[5]_net_1 ), .D(DEFSLAVEDATASEL_8_net_1), .Y(
        m23_e_8_0));
    CFG3 #( .INIT(8'hE4) )  \PREGATEDHADDR_i_m3[4]  (.A(
        masterRegAddrSel), .B(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_4), .C(
        \regHADDR[4]_net_1 ), .Y(N_188));
    CFG4 #( .INIT(16'h8000) )  un1_SDATASELInt_31 (.A(
        un1_SDATASELInt_31_8_net_1), .B(un1_SDATASELInt_31_10_net_1), 
        .C(un1_SDATASELInt_31_9_net_1), .D(un1_SDATASELInt_31_11_net_1)
        , .Y(un1_SDATASELInt_31_i));
    CFG4 #( .INIT(16'h0040) )  \SDATASELInt_RNO[14]  (.A(
        M0GATEDHADDR[24]), .B(M0GATEDHADDR[27]), .C(M0GATEDHADDR[26]), 
        .D(N_147), .Y(N_116_i));
    CFG4 #( .INIT(16'hCDCF) )  d_masterRegAddrSel_i_0 (.A(N_149_i), .B(
        M0GATEDHADDR[25]), .C(masterRegAddrSel), .D(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0), .Y(
        d_masterRegAddrSel_i_0_net_1));
    SLE masterRegAddrSel_inst_1 (.D(N_135_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(masterRegAddrSel));
    SLE regHTRANS_inst_1 (.D(VCC_net_1), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(N_134_i), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHTRANS));
    CFG4 #( .INIT(16'h0008) )  \SDATASELInt_RNO[9]  (.A(
        M0GATEDHADDR[24]), .B(M0GATEDHADDR[27]), .C(M0GATEDHADDR[26]), 
        .D(N_146), .Y(N_114_i));
    VCC VCC (.Y(VCC_net_1));
    CFG4 #( .INIT(16'hCFDD) )  \SADDRSEL_i_o2[8]  (.A(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0), .B(
        M0GATEDHADDR[25]), .C(regHTRANS), .D(masterRegAddrSel), .Y(
        N_146));
    SLE \regHADDR[24]  (.D(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_24), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(N_134_i), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\regHADDR[24]_net_1 ));
    CFG3 #( .INIT(8'hE4) )  \PREGATEDHADDR_i_m3[3]  (.A(
        masterRegAddrSel), .B(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_3), .C(
        \regHADDR[3]_net_1 ), .Y(N_189));
    CFG3 #( .INIT(8'hE4) )  \PREGATEDHADDR_i_m3[0]  (.A(
        masterRegAddrSel), .B(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_0), .C(
        \regHADDR[0]_net_1 ), .Y(N_192));
    CFG4 #( .INIT(16'h0001) )  un1_SDATASELInt_31_11 (.A(
        \SDATASELInt[8]_net_1 ), .B(\SDATASELInt[4]_net_1 ), .C(
        \SDATASELInt[2]_net_1 ), .D(m0s0DataSel), .Y(
        un1_SDATASELInt_31_11_net_1));
    CFG4 #( .INIT(16'h0004) )  \SDATASELInt_RNO[8]  (.A(
        M0GATEDHADDR[24]), .B(M0GATEDHADDR[27]), .C(M0GATEDHADDR[26]), 
        .D(N_146), .Y(N_113_i));
    CFG4 #( .INIT(16'hBFB3) )  regHWRITE_RNIJH4R (.A(regHWRITE), .B(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .C(masterRegAddrSel), 
        .D(FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE), .Y(
        m23_i_0_0));
    SLE \regHADDR[5]  (.D(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_5), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(N_134_i), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\regHADDR[5]_net_1 ));
    CFG4 #( .INIT(16'hFEFF) )  d_masterRegAddrSel_i_2 (.A(
        M0GATEDHADDR[24]), .B(M0GATEDHADDR[27]), .C(M0GATEDHADDR[26]), 
        .D(N_132_i), .Y(N_134_2));
    SLE \SDATASELInt[4]  (.D(N_108_i), .CLK(FlashFreeze_SB_0_FIC_0_CLK)
        , .EN(PREVDATASLAVEREADY_iv_i_0), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\SDATASELInt[4]_net_1 ));
    SLE \regHADDR[2]  (.D(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_2), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(N_134_i), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\regHADDR[2]_net_1 ));
    SLE \SDATASELInt[15]  (.D(N_117_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(PREVDATASLAVEREADY_iv_i_0), 
        .ALn(un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[15]_net_1 ));
    CFG4 #( .INIT(16'h0010) )  \SDATASELInt_RNO[6]  (.A(
        M0GATEDHADDR[24]), .B(M0GATEDHADDR[27]), .C(M0GATEDHADDR[26]), 
        .D(N_147), .Y(N_27_i));
    SLE \SDATASELInt[14]  (.D(N_116_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(PREVDATASLAVEREADY_iv_i_0), 
        .ALn(un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \SDATASELInt[14]_net_1 ));
    CFG4 #( .INIT(16'h0001) )  \SDATASELInt_RNIHRN21[10]  (.A(
        \SDATASELInt[10]_net_1 ), .B(\SDATASELInt[4]_net_1 ), .C(
        \SDATASELInt[3]_net_1 ), .D(\SDATASELInt[1]_net_1 ), .Y(
        m23_e_7_0));
    SLE \SDATASELInt[2]  (.D(N_120_i), .CLK(FlashFreeze_SB_0_FIC_0_CLK)
        , .EN(PREVDATASLAVEREADY_iv_i_0), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\SDATASELInt[2]_net_1 ));
    SLE \regHADDR[25]  (.D(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_25), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(N_134_i), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\regHADDR[25]_net_1 ));
    CFG4 #( .INIT(16'h0001) )  un1_SDATASELInt_31_10 (.A(
        \SDATASELInt[12]_net_1 ), .B(\SDATASELInt[10]_net_1 ), .C(
        \SDATASELInt[6]_net_1 ), .D(\SDATASELInt[3]_net_1 ), .Y(
        un1_SDATASELInt_31_10_net_1));
    CFG4 #( .INIT(16'h0001) )  \SDATASELInt_RNIAG9S[13]  (.A(
        \SDATASELInt[15]_net_1 ), .B(\SDATASELInt[13]_net_1 ), .C(
        \SDATASELInt[6]_net_1 ), .D(\SDATASELInt[2]_net_1 ), .Y(
        m23_e_6_0));
    GND GND (.Y(GND_net_1));
    CFG4 #( .INIT(16'h0002) )  \SDATASELInt_RNO[3]  (.A(
        M0GATEDHADDR[24]), .B(M0GATEDHADDR[27]), .C(M0GATEDHADDR[26]), 
        .D(N_147), .Y(N_107_i));
    CFG3 #( .INIT(8'hE4) )  \PREGATEDHADDR_i_m3[6]  (.A(
        masterRegAddrSel), .B(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_6), .C(
        \regHADDR[6]_net_1 ), .Y(N_186));
    CFG4 #( .INIT(16'h0008) )  \SDATASELInt_RNO[11]  (.A(
        M0GATEDHADDR[24]), .B(M0GATEDHADDR[27]), .C(M0GATEDHADDR[26]), 
        .D(N_147), .Y(N_37_i));
    CFG3 #( .INIT(8'hE4) )  \PREGATEDHADDR_i_m3[1]  (.A(
        masterRegAddrSel), .B(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_1), .C(
        \regHADDR[1]_net_1 ), .Y(N_191));
    CFG3 #( .INIT(8'hD8) )  SDATASELInt_2 (.A(
        PREVDATASLAVEREADY_iv_i_0), .B(N_132_i), .C(m0s0DataSel), .Y(
        SDATASELInt_2_net_1));
    CFG3 #( .INIT(8'hE4) )  \PREGATEDHADDR[25]  (.A(masterRegAddrSel), 
        .B(FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_25), .C(
        \regHADDR[25]_net_1 ), .Y(M0GATEDHADDR[25]));
    SLE \regHADDR[6]  (.D(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_6), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(N_134_i), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\regHADDR[6]_net_1 ));
    CFG4 #( .INIT(16'hFFFE) )  DEFSLAVEDATASEL_9 (.A(
        \SDATASELInt[10]_net_1 ), .B(\SDATASELInt[8]_net_1 ), .C(
        \SDATASELInt[7]_net_1 ), .D(\SDATASELInt[5]_net_1 ), .Y(
        DEFSLAVEDATASEL_9_net_1));
    SLE \SDATASELInt[13]  (.D(N_41_i), .CLK(FlashFreeze_SB_0_FIC_0_CLK)
        , .EN(PREVDATASLAVEREADY_iv_i_0), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\SDATASELInt[13]_net_1 ));
    SLE regHWRITE_inst_1 (.D(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(N_134_i), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(regHWRITE));
    CFG3 #( .INIT(8'hE4) )  regHTRANS_RNIODMI (.A(masterRegAddrSel), 
        .B(FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0), .C(
        regHTRANS), .Y(N_14_0_0));
    SLE \SDATASELInt[9]  (.D(N_114_i), .CLK(FlashFreeze_SB_0_FIC_0_CLK)
        , .EN(PREVDATASLAVEREADY_iv_i_0), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\SDATASELInt[9]_net_1 ));
    SLE \SDATASELInt[1]  (.D(N_119_i), .CLK(FlashFreeze_SB_0_FIC_0_CLK)
        , .EN(PREVDATASLAVEREADY_iv_i_0), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\SDATASELInt[1]_net_1 ));
    SLE \SDATASELInt[12]  (.D(N_39_i), .CLK(FlashFreeze_SB_0_FIC_0_CLK)
        , .EN(PREVDATASLAVEREADY_iv_i_0), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\SDATASELInt[12]_net_1 ));
    SLE \SDATASELInt[0]  (.D(SDATASELInt_2_net_1), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(m0s0DataSel));
    SLE \regHADDR[0]  (.D(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_0), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(N_134_i), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\regHADDR[0]_net_1 ));
    CFG3 #( .INIT(8'hE4) )  \PREGATEDHADDR_i_m3[2]  (.A(
        masterRegAddrSel), .B(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_2), .C(
        \regHADDR[2]_net_1 ), .Y(N_190));
    CFG2 #( .INIT(4'h8) )  \SDATASELInt_RNIRB1V1[10]  (.A(m23_e_6_0), 
        .B(m23_e_7_0), .Y(m23_e_9_0));
    SLE \SDATASELInt[5]  (.D(N_110_i), .CLK(FlashFreeze_SB_0_FIC_0_CLK)
        , .EN(PREVDATASLAVEREADY_iv_i_0), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\SDATASELInt[5]_net_1 ));
    CFG4 #( .INIT(16'h0040) )  \SDATASELInt_RNO[12]  (.A(
        M0GATEDHADDR[24]), .B(M0GATEDHADDR[27]), .C(M0GATEDHADDR[26]), 
        .D(N_146), .Y(N_39_i));
    CFG4 #( .INIT(16'h3022) )  regHTRANS_RNINS0P (.A(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0), .B(
        M0GATEDHADDR[24]), .C(regHTRANS), .D(masterRegAddrSel), .Y(
        N_132_i_1));
    SLE \regHADDR[3]  (.D(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_3), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(N_134_i), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\regHADDR[3]_net_1 ));
    CFG4 #( .INIT(16'h0001) )  un1_SDATASELInt_31_8 (.A(
        \SDATASELInt[13]_net_1 ), .B(\SDATASELInt[5]_net_1 ), .C(
        \SDATASELInt[11]_net_1 ), .D(\SDATASELInt[9]_net_1 ), .Y(
        un1_SDATASELInt_31_8_net_1));
    SLE \SDATASELInt[3]  (.D(N_107_i), .CLK(FlashFreeze_SB_0_FIC_0_CLK)
        , .EN(PREVDATASLAVEREADY_iv_i_0), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\SDATASELInt[3]_net_1 ));
    CFG3 #( .INIT(8'hE4) )  \PREGATEDHADDR[27]  (.A(masterRegAddrSel), 
        .B(FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_27), .C(
        \regHADDR[27]_net_1 ), .Y(M0GATEDHADDR[27]));
    CFG4 #( .INIT(16'h0080) )  \SDATASELInt_RNO[15]  (.A(
        M0GATEDHADDR[24]), .B(M0GATEDHADDR[27]), .C(M0GATEDHADDR[26]), 
        .D(N_147), .Y(N_117_i));
    SLE \regHADDR[1]  (.D(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_1), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(N_134_i), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\regHADDR[1]_net_1 ));
    CFG4 #( .INIT(16'h0080) )  \SDATASELInt_RNO[13]  (.A(
        M0GATEDHADDR[24]), .B(M0GATEDHADDR[27]), .C(M0GATEDHADDR[26]), 
        .D(N_146), .Y(N_41_i));
    SLE \SDATASELInt[7]  (.D(N_111_i), .CLK(FlashFreeze_SB_0_FIC_0_CLK)
        , .EN(PREVDATASLAVEREADY_iv_i_0), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\SDATASELInt[7]_net_1 ));
    CFG4 #( .INIT(16'h3F77) )  \SADDRSEL_i_o2[2]  (.A(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0), .B(
        M0GATEDHADDR[25]), .C(regHTRANS), .D(masterRegAddrSel), .Y(
        N_147));
    CFG4 #( .INIT(16'h0004) )  \SDATASELInt_RNO[10]  (.A(
        M0GATEDHADDR[24]), .B(M0GATEDHADDR[27]), .C(M0GATEDHADDR[26]), 
        .D(N_147), .Y(N_35_i));
    CFG4 #( .INIT(16'hFFFE) )  DEFSLAVEDATASEL_8 (.A(
        \SDATASELInt[14]_net_1 ), .B(\SDATASELInt[12]_net_1 ), .C(
        \SDATASELInt[11]_net_1 ), .D(\SDATASELInt[9]_net_1 ), .Y(
        DEFSLAVEDATASEL_8_net_1));
    CFG4 #( .INIT(16'h0103) )  masterAddrClockEnable_i_1_RNICKUO2 (.A(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .B(
        masterAddrClockEnable_i_1_net_1), .C(N_134_2), .D(
        masterAddrInProg_0), .Y(N_134_i));
    SLE \SDATASELInt[6]  (.D(N_27_i), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(PREVDATASLAVEREADY_iv_i_0), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\SDATASELInt[6]_net_1 ));
    CFG4 #( .INIT(16'h0103) )  masterRegAddrSel_RNO (.A(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .B(
        d_masterRegAddrSel_i_0_net_1), .C(N_134_2), .D(
        masterAddrInProg_0), .Y(N_135_i));
    CFG3 #( .INIT(8'hE4) )  \PREGATEDHADDR[26]  (.A(masterRegAddrSel), 
        .B(FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_26), .C(
        \regHADDR[26]_net_1 ), .Y(M0GATEDHADDR[26]));
    CFG4 #( .INIT(16'h002A) )  un1_SDATASELInt_34_RNIBERU3 (.A(
        m23_i_a5_0_0), .B(m23_e_9_0), .C(m23_e_8_0), .D(
        un1_SDATASELInt_34_i), .Y(N_15_0));
    CFG4 #( .INIT(16'hFDFF) )  masterAddrClockEnable_i_1 (.A(N_149_i), 
        .B(M0GATEDHADDR[25]), .C(masterRegAddrSel), .D(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0), .Y(
        masterAddrClockEnable_i_1_net_1));
    SLE \regHADDR[27]  (.D(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_27), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(N_134_i), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\regHADDR[27]_net_1 ));
    CFG4 #( .INIT(16'h0010) )  \SDATASELInt_RNO[4]  (.A(
        M0GATEDHADDR[24]), .B(M0GATEDHADDR[27]), .C(M0GATEDHADDR[26]), 
        .D(N_146), .Y(N_108_i));
    CFG2 #( .INIT(4'hE) )  un1_SDATASELInt_34 (.A(un1_SDATASELInt_31_i)
        , .B(m0s0DataSel), .Y(un1_SDATASELInt_34_i));
    SLE \SDATASELInt[11]  (.D(N_37_i), .CLK(FlashFreeze_SB_0_FIC_0_CLK)
        , .EN(PREVDATASLAVEREADY_iv_i_0), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\SDATASELInt[11]_net_1 ));
    CFG4 #( .INIT(16'hFFFE) )  DEFSLAVEDATASEL_11 (.A(
        \SDATASELInt[15]_net_1 ), .B(\SDATASELInt[13]_net_1 ), .C(
        \SDATASELInt[2]_net_1 ), .D(DEFSLAVEDATASEL_8_net_1), .Y(
        DEFSLAVEDATASEL_11_net_1));
    CFG4 #( .INIT(16'h0001) )  un1_SDATASELInt_31_9 (.A(
        \SDATASELInt[15]_net_1 ), .B(\SDATASELInt[14]_net_1 ), .C(
        \SDATASELInt[1]_net_1 ), .D(\SDATASELInt[7]_net_1 ), .Y(
        un1_SDATASELInt_31_9_net_1));
    SLE \SDATASELInt[8]  (.D(N_113_i), .CLK(FlashFreeze_SB_0_FIC_0_CLK)
        , .EN(PREVDATASLAVEREADY_iv_i_0), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\SDATASELInt[8]_net_1 ));
    CFG2 #( .INIT(4'h7) )  HREADY_M_iv_i_i_o3 (.A(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .B(masterDataInProg_0), 
        .Y(N_144));
    CFG4 #( .INIT(16'h0020) )  \SDATASELInt_RNO[7]  (.A(
        M0GATEDHADDR[24]), .B(M0GATEDHADDR[27]), .C(M0GATEDHADDR[26]), 
        .D(N_147), .Y(N_111_i));
    CFG4 #( .INIT(16'h0002) )  \SDATASELInt_RNO[1]  (.A(
        M0GATEDHADDR[24]), .B(M0GATEDHADDR[27]), .C(M0GATEDHADDR[26]), 
        .D(N_146), .Y(N_119_i));
    SLE \regHADDR[4]  (.D(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_4), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(N_134_i), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\regHADDR[4]_net_1 ));
    SLE \regHADDR[26]  (.D(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_26), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(N_134_i), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\regHADDR[26]_net_1 ));
    CFG3 #( .INIT(8'hE4) )  \PREGATEDHADDR_i_m3[7]  (.A(
        masterRegAddrSel), .B(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_7), .C(
        \regHADDR[7]_net_1 ), .Y(N_185));
    SLE \SDATASELInt[10]  (.D(N_35_i), .CLK(FlashFreeze_SB_0_FIC_0_CLK)
        , .EN(PREVDATASLAVEREADY_iv_i_0), .ALn(
        un1_FlashFreeze_SB_0_1_i_i), .ADn(VCC_net_1), .SLn(VCC_net_1), 
        .SD(GND_net_1), .LAT(GND_net_1), .Q(\SDATASELInt[10]_net_1 ));
    COREAHBLITE_DEFAULTSLAVESM_0s_0_1_0 default_slave_sm (.N_149_i(
        N_149_i), .N_144(N_144), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HRESP_0(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HRESP_0), 
        .un1_SDATASELInt_34_i(un1_SDATASELInt_34_i), 
        .DEFSLAVEDATASEL_9(DEFSLAVEDATASEL_9_net_1), 
        .DEFSLAVEDATASEL_11(DEFSLAVEDATASEL_11_net_1), 
        .DEFSLAVEDATASEL_10(DEFSLAVEDATASEL_10_net_1), .m23_i_a5_0_0(
        m23_i_a5_0_0), .m0s0DataSel(m0s0DataSel), .defSlaveSMNextState(
        defSlaveSMNextState), .FlashFreeze_SB_0_FIC_0_CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .un1_FlashFreeze_SB_0_1_i_i(
        un1_FlashFreeze_SB_0_1_i_i));
    
endmodule


module COREAHBLITE_MATRIX4X16_2_1_0_1_0_0_0_0s(
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA,
       FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA,
       M0GATEDHADDR,
       CAHBtoAPB3IOI_3,
       CAHBtoAPB3IOI_0,
       CAHBtoAPB3IOI_4,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_24,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_25,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_26,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_27,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_7,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_0,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_1,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_2,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_3,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_4,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_5,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_6,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0,
       masterAddrInProg_0,
       CoreAPB3_0_APBmslave0_PWRITE,
       CAHBtoAPB3ll4,
       CAHBtoAPB3lII,
       N_250,
       N_181_mux_i,
       CAHBtoAPB3II,
       N_151,
       CAHBtoAPB3III,
       N_25_0,
       CoreAPB3_0_APBmslave0_PSELx,
       CoreAPB3_0_APBmslave0_PREADY,
       PENABLE,
       N_54_0,
       N_63_0,
       CAHBtoAPB3OI,
       N_153_mux,
       N_56_0_i,
       m19_e_0,
       N_178_mux,
       N_247_mux,
       N_179_mux,
       N_177_mux_i,
       CAHBtoAPB3lI,
       N_12_i,
       N_55_i,
       N_57_i,
       N_59_i,
       N_61_i,
       N_123_i,
       N_125_i,
       N_51_i,
       N_122_i,
       N_126_i,
       N_128_i,
       N_129_i,
       N_131_i,
       N_171_mux,
       un1_FlashFreeze_SB_0_1_i_i,
       FlashFreeze_SB_0_FIC_0_CLK,
       m0s0DataSel,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE,
       FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY,
       N_185,
       N_186,
       N_187,
       N_188,
       N_189,
       N_190,
       N_191,
       N_192,
       N_149_i,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HRESP_0
    );
input  [7:0] FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA;
output [7:0] FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA;
output [27:24] M0GATEDHADDR;
input  CAHBtoAPB3IOI_3;
input  CAHBtoAPB3IOI_0;
input  CAHBtoAPB3IOI_4;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_24;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_25;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_26;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_27;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_7;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_0;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_1;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_2;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_3;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_4;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_5;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_6;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0;
output masterAddrInProg_0;
input  CoreAPB3_0_APBmslave0_PWRITE;
input  CAHBtoAPB3ll4;
input  CAHBtoAPB3lII;
input  N_250;
output N_181_mux_i;
output CAHBtoAPB3II;
output N_151;
input  CAHBtoAPB3III;
output N_25_0;
input  CoreAPB3_0_APBmslave0_PSELx;
input  CoreAPB3_0_APBmslave0_PREADY;
input  PENABLE;
output N_54_0;
output N_63_0;
input  CAHBtoAPB3OI;
output N_153_mux;
output N_56_0_i;
output m19_e_0;
output N_178_mux;
output N_247_mux;
output N_179_mux;
output N_177_mux_i;
output CAHBtoAPB3lI;
output N_12_i;
output N_55_i;
output N_57_i;
output N_59_i;
output N_61_i;
output N_123_i;
output N_125_i;
output N_51_i;
output N_122_i;
output N_126_i;
output N_128_i;
output N_129_i;
output N_131_i;
output N_171_mux;
input  un1_FlashFreeze_SB_0_1_i_i;
input  FlashFreeze_SB_0_FIC_0_CLK;
output m0s0DataSel;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE;
input  FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY;
output N_185;
output N_186;
output N_187;
output N_188;
output N_189;
output N_190;
output N_191;
output N_192;
output N_149_i;
output FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HRESP_0;

    wire \masterDataInProg[0] , defSlaveSMNextState, N_248, 
        un1_SDATASELInt_34_i, m23_i_a5_0_0, m23_e_6_0, m23_e_7_0, 
        m23_e_8_0, N_132_i, masterRegAddrSel, regHTRANS, regHWRITE, 
        PREVDATASLAVEREADY_iv_i_0, GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    COREAHBLITE_SLAVESTAGE_0s_0_0_1 slavestage_0 (.M0GATEDHADDR({
        M0GATEDHADDR[27], M0GATEDHADDR[26], M0GATEDHADDR[25], 
        M0GATEDHADDR[24]}), .FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA({
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[7], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[6], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[5], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[4], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[3], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[2], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[1], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[0]}), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA({
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[7], 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[6], 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[5], 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[4], 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[3], 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[2], 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[1], 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[0]}), 
        .CAHBtoAPB3IOI_3(CAHBtoAPB3IOI_3), .CAHBtoAPB3IOI_0(
        CAHBtoAPB3IOI_0), .CAHBtoAPB3IOI_4(CAHBtoAPB3IOI_4), 
        .masterAddrInProg_0(masterAddrInProg_0), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0), 
        .masterDataInProg_0(\masterDataInProg[0] ), .N_171_mux(
        N_171_mux), .N_132_i(N_132_i), .N_131_i(N_131_i), .N_129_i(
        N_129_i), .N_128_i(N_128_i), .N_126_i(N_126_i), .N_191(N_191), 
        .N_122_i(N_122_i), .N_192(N_192), .N_51_i(N_51_i), .N_185(
        N_185), .N_125_i(N_125_i), .N_186(N_186), .N_123_i(N_123_i), 
        .N_187(N_187), .N_61_i(N_61_i), .N_188(N_188), .N_59_i(N_59_i), 
        .N_189(N_189), .N_57_i(N_57_i), .N_190(N_190), .N_55_i(N_55_i), 
        .N_12_i(N_12_i), .CAHBtoAPB3lI(CAHBtoAPB3lI), .N_177_mux_i(
        N_177_mux_i), .N_179_mux(N_179_mux), .N_247_mux(N_247_mux), 
        .N_178_mux(N_178_mux), .N_248(N_248), 
        .PREVDATASLAVEREADY_iv_i_0(PREVDATASLAVEREADY_iv_i_0), 
        .m19_e_0(m19_e_0), .defSlaveSMNextState(defSlaveSMNextState), 
        .m0s0DataSel(m0s0DataSel), .N_56_0_i(N_56_0_i), .N_153_mux(
        N_153_mux), .CAHBtoAPB3OI(CAHBtoAPB3OI), .N_63_0(N_63_0), 
        .N_54_0(N_54_0), .PENABLE(PENABLE), 
        .CoreAPB3_0_APBmslave0_PREADY(CoreAPB3_0_APBmslave0_PREADY), 
        .CoreAPB3_0_APBmslave0_PSELx(CoreAPB3_0_APBmslave0_PSELx), 
        .N_25_0(N_25_0), .CAHBtoAPB3III(CAHBtoAPB3III), .N_151(N_151), 
        .CAHBtoAPB3II(CAHBtoAPB3II), .N_181_mux_i(N_181_mux_i), .N_250(
        N_250), .un1_SDATASELInt_34_i(un1_SDATASELInt_34_i), 
        .FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .regHTRANS(regHTRANS), 
        .regHWRITE(regHWRITE), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE), 
        .masterRegAddrSel(masterRegAddrSel), .CAHBtoAPB3lII(
        CAHBtoAPB3lII), .CAHBtoAPB3ll4(CAHBtoAPB3ll4), 
        .CoreAPB3_0_APBmslave0_PWRITE(CoreAPB3_0_APBmslave0_PWRITE), 
        .m23_i_a5_0_0(m23_i_a5_0_0), .m23_e_8_0(m23_e_8_0), .m23_e_6_0(
        m23_e_6_0), .m23_e_7_0(m23_e_7_0), .FlashFreeze_SB_0_FIC_0_CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .un1_FlashFreeze_SB_0_1_i_i(
        un1_FlashFreeze_SB_0_1_i_i));
    GND GND (.Y(GND_net_1));
    COREAHBLITE_MASTERSTAGE_2_1_0_1_0s_0_1_0 masterstage_0 (
        .M0GATEDHADDR({M0GATEDHADDR[27], M0GATEDHADDR[26], 
        M0GATEDHADDR[25], M0GATEDHADDR[24]}), .masterDataInProg_0(
        \masterDataInProg[0] ), .masterAddrInProg_0(masterAddrInProg_0)
        , .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_24(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_24), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_25(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_25), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_26(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_26), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_27(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_27), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_7(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_7), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_0(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_0), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_1(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_1), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_2(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_2), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_3(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_3), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_4(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_4), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_5(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_5), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_6(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_6), 
        .defSlaveSMNextState(defSlaveSMNextState), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HRESP_0(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HRESP_0), .N_149_i(
        N_149_i), .N_192(N_192), .N_191(N_191), .N_190(N_190), .N_189(
        N_189), .N_188(N_188), .N_187(N_187), .N_186(N_186), .N_185(
        N_185), .N_248(N_248), .un1_SDATASELInt_34_i(
        un1_SDATASELInt_34_i), .m23_i_a5_0_0(m23_i_a5_0_0), 
        .FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .m23_e_6_0(m23_e_6_0), 
        .m23_e_7_0(m23_e_7_0), .m23_e_8_0(m23_e_8_0), .N_132_i(N_132_i)
        , .masterRegAddrSel(masterRegAddrSel), .regHTRANS(regHTRANS), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE), .regHWRITE(
        regHWRITE), .m0s0DataSel(m0s0DataSel), 
        .PREVDATASLAVEREADY_iv_i_0(PREVDATASLAVEREADY_iv_i_0), 
        .FlashFreeze_SB_0_FIC_0_CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .un1_FlashFreeze_SB_0_1_i_i(un1_FlashFreeze_SB_0_1_i_i));
    
endmodule


module CoreAHBLite_Z5(
       M0GATEDHADDR,
       FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA,
       masterAddrInProg_0,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_24,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_25,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_26,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_27,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_7,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_0,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_1,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_2,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_3,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_4,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_5,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_6,
       CAHBtoAPB3IOI_3,
       CAHBtoAPB3IOI_0,
       CAHBtoAPB3IOI_4,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HRESP_0,
       N_149_i,
       N_192,
       N_191,
       N_190,
       N_189,
       N_188,
       N_187,
       N_186,
       N_185,
       FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE,
       m0s0DataSel,
       FlashFreeze_SB_0_FIC_0_CLK,
       un1_FlashFreeze_SB_0_1_i_i,
       N_171_mux,
       N_131_i,
       N_129_i,
       N_128_i,
       N_126_i,
       N_122_i,
       N_51_i,
       N_125_i,
       N_123_i,
       N_61_i,
       N_59_i,
       N_57_i,
       N_55_i,
       N_12_i,
       CAHBtoAPB3lI,
       N_177_mux_i,
       N_179_mux,
       N_247_mux,
       N_178_mux,
       m19_e_0,
       N_56_0_i,
       N_153_mux,
       CAHBtoAPB3OI,
       N_63_0,
       N_54_0,
       PENABLE,
       CoreAPB3_0_APBmslave0_PREADY,
       CoreAPB3_0_APBmslave0_PSELx,
       N_25_0,
       CAHBtoAPB3III,
       N_151,
       CAHBtoAPB3II,
       N_181_mux_i,
       N_250,
       CAHBtoAPB3lII,
       CAHBtoAPB3ll4,
       CoreAPB3_0_APBmslave0_PWRITE
    );
output [27:24] M0GATEDHADDR;
output [7:0] FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA;
input  [7:0] FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA;
output masterAddrInProg_0;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_24;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_25;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_26;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_27;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_7;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_0;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_1;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_2;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_3;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_4;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_5;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_6;
input  CAHBtoAPB3IOI_3;
input  CAHBtoAPB3IOI_0;
input  CAHBtoAPB3IOI_4;
output FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HRESP_0;
output N_149_i;
output N_192;
output N_191;
output N_190;
output N_189;
output N_188;
output N_187;
output N_186;
output N_185;
input  FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE;
output m0s0DataSel;
input  FlashFreeze_SB_0_FIC_0_CLK;
input  un1_FlashFreeze_SB_0_1_i_i;
output N_171_mux;
output N_131_i;
output N_129_i;
output N_128_i;
output N_126_i;
output N_122_i;
output N_51_i;
output N_125_i;
output N_123_i;
output N_61_i;
output N_59_i;
output N_57_i;
output N_55_i;
output N_12_i;
output CAHBtoAPB3lI;
output N_177_mux_i;
output N_179_mux;
output N_247_mux;
output N_178_mux;
output m19_e_0;
output N_56_0_i;
output N_153_mux;
input  CAHBtoAPB3OI;
output N_63_0;
output N_54_0;
input  PENABLE;
input  CoreAPB3_0_APBmslave0_PREADY;
input  CoreAPB3_0_APBmslave0_PSELx;
output N_25_0;
input  CAHBtoAPB3III;
output N_151;
output CAHBtoAPB3II;
output N_181_mux_i;
input  N_250;
input  CAHBtoAPB3lII;
input  CAHBtoAPB3ll4;
input  CoreAPB3_0_APBmslave0_PWRITE;

    wire GND_net_1, VCC_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    COREAHBLITE_MATRIX4X16_2_1_0_1_0_0_0_0s matrix4x16 (
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA({
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[7], 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[6], 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[5], 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[4], 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[3], 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[2], 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[1], 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[0]}), 
        .FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA({
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[7], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[6], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[5], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[4], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[3], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[2], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[1], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[0]}), .M0GATEDHADDR({
        M0GATEDHADDR[27], M0GATEDHADDR[26], M0GATEDHADDR[25], 
        M0GATEDHADDR[24]}), .CAHBtoAPB3IOI_3(CAHBtoAPB3IOI_3), 
        .CAHBtoAPB3IOI_0(CAHBtoAPB3IOI_0), .CAHBtoAPB3IOI_4(
        CAHBtoAPB3IOI_4), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_24(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_24), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_25(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_25), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_26(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_26), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_27(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_27), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_7(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_7), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_0(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_0), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_1(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_1), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_2(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_2), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_3(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_3), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_4(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_4), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_5(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_5), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_6(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_6), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0), 
        .masterAddrInProg_0(masterAddrInProg_0), 
        .CoreAPB3_0_APBmslave0_PWRITE(CoreAPB3_0_APBmslave0_PWRITE), 
        .CAHBtoAPB3ll4(CAHBtoAPB3ll4), .CAHBtoAPB3lII(CAHBtoAPB3lII), 
        .N_250(N_250), .N_181_mux_i(N_181_mux_i), .CAHBtoAPB3II(
        CAHBtoAPB3II), .N_151(N_151), .CAHBtoAPB3III(CAHBtoAPB3III), 
        .N_25_0(N_25_0), .CoreAPB3_0_APBmslave0_PSELx(
        CoreAPB3_0_APBmslave0_PSELx), .CoreAPB3_0_APBmslave0_PREADY(
        CoreAPB3_0_APBmslave0_PREADY), .PENABLE(PENABLE), .N_54_0(
        N_54_0), .N_63_0(N_63_0), .CAHBtoAPB3OI(CAHBtoAPB3OI), 
        .N_153_mux(N_153_mux), .N_56_0_i(N_56_0_i), .m19_e_0(m19_e_0), 
        .N_178_mux(N_178_mux), .N_247_mux(N_247_mux), .N_179_mux(
        N_179_mux), .N_177_mux_i(N_177_mux_i), .CAHBtoAPB3lI(
        CAHBtoAPB3lI), .N_12_i(N_12_i), .N_55_i(N_55_i), .N_57_i(
        N_57_i), .N_59_i(N_59_i), .N_61_i(N_61_i), .N_123_i(N_123_i), 
        .N_125_i(N_125_i), .N_51_i(N_51_i), .N_122_i(N_122_i), 
        .N_126_i(N_126_i), .N_128_i(N_128_i), .N_129_i(N_129_i), 
        .N_131_i(N_131_i), .N_171_mux(N_171_mux), 
        .un1_FlashFreeze_SB_0_1_i_i(un1_FlashFreeze_SB_0_1_i_i), 
        .FlashFreeze_SB_0_FIC_0_CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .m0s0DataSel(m0s0DataSel), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE), 
        .FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .N_185(N_185), .N_186(
        N_186), .N_187(N_187), .N_188(N_188), .N_189(N_189), .N_190(
        N_190), .N_191(N_191), .N_192(N_192), .N_149_i(N_149_i), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HRESP_0(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HRESP_0));
    GND GND (.Y(GND_net_1));
    
endmodule


module FlashFreeze_SB_CCC_0_FCCC(
       FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC,
       FIC_0_LOCK_c,
       FlashFreeze_SB_0_FIC_0_CLK,
       FLASH_FREEZE_0_FF_DONE
    );
input  FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC;
output FIC_0_LOCK_c;
output FlashFreeze_SB_0_FIC_0_CLK;
input  FLASH_FREEZE_0_FF_DONE;

    wire FLASH_FREEZE_0_FF_DONE_i, GL0_net, VCC_net_1, GND_net_1;
    
    VCC VCC (.Y(VCC_net_1));
    GND GND (.Y(GND_net_1));
    CLKINT GL0_INST (.A(GL0_net), .Y(FlashFreeze_SB_0_FIC_0_CLK));
    CFG1 #( .INIT(2'h1) )  CCC_INST_RNO (.A(FLASH_FREEZE_0_FF_DONE), 
        .Y(FLASH_FREEZE_0_FF_DONE_i));
    CCC #( .INIT(210'h0000007FB8000044D64000318C6318C1F18C61EC0404040400301)
        , .VCOFREQUENCY(800.0) )  CCC_INST (.Y0(), .Y1(), .Y2(), .Y3(), 
        .PRDATA({nc0, nc1, nc2, nc3, nc4, nc5, nc6, nc7}), .LOCK(
        FIC_0_LOCK_c), .BUSY(), .CLK0(VCC_net_1), .CLK1(VCC_net_1), 
        .CLK2(VCC_net_1), .CLK3(VCC_net_1), .NGMUX0_SEL(GND_net_1), 
        .NGMUX1_SEL(GND_net_1), .NGMUX2_SEL(GND_net_1), .NGMUX3_SEL(
        GND_net_1), .NGMUX0_HOLD_N(VCC_net_1), .NGMUX1_HOLD_N(
        VCC_net_1), .NGMUX2_HOLD_N(VCC_net_1), .NGMUX3_HOLD_N(
        VCC_net_1), .NGMUX0_ARST_N(VCC_net_1), .NGMUX1_ARST_N(
        VCC_net_1), .NGMUX2_ARST_N(VCC_net_1), .NGMUX3_ARST_N(
        VCC_net_1), .PLL_BYPASS_N(VCC_net_1), .PLL_ARST_N(
        FLASH_FREEZE_0_FF_DONE_i), .PLL_POWERDOWN_N(VCC_net_1), 
        .GPD0_ARST_N(VCC_net_1), .GPD1_ARST_N(VCC_net_1), .GPD2_ARST_N(
        VCC_net_1), .GPD3_ARST_N(VCC_net_1), .PRESET_N(GND_net_1), 
        .PCLK(VCC_net_1), .PSEL(VCC_net_1), .PENABLE(VCC_net_1), 
        .PWRITE(VCC_net_1), .PADDR({VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1}), .PWDATA({VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1}), .CLK0_PAD(GND_net_1), .CLK1_PAD(
        GND_net_1), .CLK2_PAD(GND_net_1), .CLK3_PAD(GND_net_1), .GL0(
        GL0_net), .GL1(), .GL2(), .GL3(), .RCOSC_25_50MHZ(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC), 
        .RCOSC_1MHZ(GND_net_1), .XTLOSC(GND_net_1));
    
endmodule


module FlashFreeze_SB_MSS(
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA,
       FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_0,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_1,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_2,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_3,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_4,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_5,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_6,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_7,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_24,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_25,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_26,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_27,
       FlashFreeze_SB_0_FIC_0_CLK,
       MX2_0_Y,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HRESP_0,
       N_149_i,
       FlashFreeze_SB_MSS_TMP_0_MSS_RESET_N_M2F,
       FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE,
       FlashFreeze_SB_MSS_TMP_0_FIC_2_APB_M_PRESET_N,
       m0s0DataSel,
       MMUART_1_RXD_0,
       MMUART_1_TXD
    );
output [7:0] FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA;
input  [7:0] FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA;
output FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0;
output FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_0;
output FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_1;
output FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_2;
output FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_3;
output FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_4;
output FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_5;
output FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_6;
output FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_7;
output FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_24;
output FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_25;
output FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_26;
output FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_27;
input  FlashFreeze_SB_0_FIC_0_CLK;
input  MX2_0_Y;
input  FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HRESP_0;
input  N_149_i;
output FlashFreeze_SB_MSS_TMP_0_MSS_RESET_N_M2F;
output FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE;
output FlashFreeze_SB_MSS_TMP_0_FIC_2_APB_M_PRESET_N;
input  m0s0DataSel;
input  MMUART_1_RXD_0;
output MMUART_1_TXD;

    wire MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT, 
        MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OE, 
        MMUART_1_RXD_PAD_Y, \AMBA_SLAVE_0_HRDATA_S0_m[0] , 
        \AMBA_SLAVE_0_HRDATA_S0_m[1] , \AMBA_SLAVE_0_HRDATA_S0_m[2] , 
        \AMBA_SLAVE_0_HRDATA_S0_m[3] , \AMBA_SLAVE_0_HRDATA_S0_m[4] , 
        \AMBA_SLAVE_0_HRDATA_S0_m[5] , \AMBA_SLAVE_0_HRDATA_S0_m[6] , 
        \AMBA_SLAVE_0_HRDATA_S0_m[7] , VCC_net_1, GND_net_1;
    
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNO_3 (.A(m0s0DataSel), .B(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[4]), .Y(
        \AMBA_SLAVE_0_HRDATA_S0_m[4] ));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNO (.A(m0s0DataSel), .B(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[0]), .Y(
        \AMBA_SLAVE_0_HRDATA_S0_m[0] ));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNO_5 (.A(m0s0DataSel), .B(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[6]), .Y(
        \AMBA_SLAVE_0_HRDATA_S0_m[6] ));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNO_0 (.A(m0s0DataSel), .B(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[1]), .Y(
        \AMBA_SLAVE_0_HRDATA_S0_m[1] ));
    TRIBUFF MMUART_1_TXD_PAD (.D(
        MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT), .E(
        MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OE), .PAD(
        MMUART_1_TXD));
    GND GND (.Y(GND_net_1));
    INBUF MMUART_1_RXD_PAD (.PAD(MMUART_1_RXD_0), .Y(
        MMUART_1_RXD_PAD_Y));
    VCC VCC (.Y(VCC_net_1));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNO_4 (.A(m0s0DataSel), .B(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[5]), .Y(
        \AMBA_SLAVE_0_HRDATA_S0_m[5] ));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNO_1 (.A(m0s0DataSel), .B(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[2]), .Y(
        \AMBA_SLAVE_0_HRDATA_S0_m[2] ));
    MSS_075 #( .INIT(1438'h00000000000000000000000000000036100080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000F00000000F000000000000000000000000000000007FFFFFFFB000001007C33C000000006092C0104007FFFFE400000000000010000000000E11C000001FE5FA4010842108421000001FE34001FF8000000400000000000891007FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
        , .ACT_UBITS(56'hFFFFFFFFFFFFFF), .MEMORYFILE("ENVM_init.mem")
        , .RTC_MAIN_XTL_FREQ(0.0), .RTC_MAIN_XTL_MODE(""), .DDR_CLK_FREQ(100.0)
         )  MSS_ADLIB_INST (.CAN_RXBUS_MGPIO3A_H2F_A(), 
        .CAN_RXBUS_MGPIO3A_H2F_B(), .CAN_TX_EBL_MGPIO4A_H2F_A(), 
        .CAN_TX_EBL_MGPIO4A_H2F_B(), .CAN_TXBUS_MGPIO2A_H2F_A(), 
        .CAN_TXBUS_MGPIO2A_H2F_B(), .CLK_CONFIG_APB(), .COMMS_INT(), 
        .CONFIG_PRESET_N(FlashFreeze_SB_MSS_TMP_0_FIC_2_APB_M_PRESET_N)
        , .EDAC_ERROR({nc0, nc1, nc2, nc3, nc4, nc5, nc6, nc7}), 
        .F_FM0_RDATA({nc8, nc9, nc10, nc11, nc12, nc13, nc14, nc15, 
        nc16, nc17, nc18, nc19, nc20, nc21, nc22, nc23, nc24, nc25, 
        nc26, nc27, nc28, nc29, nc30, nc31, nc32, nc33, nc34, nc35, 
        nc36, nc37, nc38, nc39}), .F_FM0_READYOUT(), .F_FM0_RESP(), 
        .F_HM0_ADDR({nc40, nc41, nc42, nc43, 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_27, 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_26, 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_25, 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_24, nc44, nc45, 
        nc46, nc47, nc48, nc49, nc50, nc51, nc52, nc53, nc54, nc55, 
        nc56, nc57, nc58, nc59, 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_7, 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_6, 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_5, 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_4, 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_3, 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_2, 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_1, 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_0}), 
        .F_HM0_ENABLE(), .F_HM0_SEL(), .F_HM0_SIZE({nc60, nc61}), 
        .F_HM0_TRANS1(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0), 
        .F_HM0_WDATA({nc62, nc63, nc64, nc65, nc66, nc67, nc68, nc69, 
        nc70, nc71, nc72, nc73, nc74, nc75, nc76, nc77, nc78, nc79, 
        nc80, nc81, nc82, nc83, nc84, nc85, 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[7], 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[6], 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[5], 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[4], 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[3], 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[2], 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[1], 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[0]}), 
        .F_HM0_WRITE(FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE), 
        .FAB_CHRGVBUS(), .FAB_DISCHRGVBUS(), .FAB_DMPULLDOWN(), 
        .FAB_DPPULLDOWN(), .FAB_DRVVBUS(), .FAB_IDPULLUP(), 
        .FAB_OPMODE({nc86, nc87}), .FAB_SUSPENDM(), .FAB_TERMSEL(), 
        .FAB_TXVALID(), .FAB_VCONTROL({nc88, nc89, nc90, nc91}), 
        .FAB_VCONTROLLOADM(), .FAB_XCVRSEL({nc92, nc93}), 
        .FAB_XDATAOUT({nc94, nc95, nc96, nc97, nc98, nc99, nc100, 
        nc101}), .FACC_GLMUX_SEL(), .FIC32_0_MASTER({nc102, nc103}), 
        .FIC32_1_MASTER({nc104, nc105}), .FPGA_RESET_N(
        FlashFreeze_SB_MSS_TMP_0_MSS_RESET_N_M2F), .GTX_CLK(), 
        .H2F_INTERRUPT({nc106, nc107, nc108, nc109, nc110, nc111, 
        nc112, nc113, nc114, nc115, nc116, nc117, nc118, nc119, nc120, 
        nc121}), .H2F_NMI(), .H2FCALIB(), .I2C0_SCL_MGPIO31B_H2F_A(), 
        .I2C0_SCL_MGPIO31B_H2F_B(), .I2C0_SDA_MGPIO30B_H2F_A(), 
        .I2C0_SDA_MGPIO30B_H2F_B(), .I2C1_SCL_MGPIO1A_H2F_A(), 
        .I2C1_SCL_MGPIO1A_H2F_B(), .I2C1_SDA_MGPIO0A_H2F_A(), 
        .I2C1_SDA_MGPIO0A_H2F_B(), .MDCF(), .MDOENF(), .MDOF(), 
        .MMUART0_CTS_MGPIO19B_H2F_A(), .MMUART0_CTS_MGPIO19B_H2F_B(), 
        .MMUART0_DCD_MGPIO22B_H2F_A(), .MMUART0_DCD_MGPIO22B_H2F_B(), 
        .MMUART0_DSR_MGPIO20B_H2F_A(), .MMUART0_DSR_MGPIO20B_H2F_B(), 
        .MMUART0_DTR_MGPIO18B_H2F_A(), .MMUART0_DTR_MGPIO18B_H2F_B(), 
        .MMUART0_RI_MGPIO21B_H2F_A(), .MMUART0_RI_MGPIO21B_H2F_B(), 
        .MMUART0_RTS_MGPIO17B_H2F_A(), .MMUART0_RTS_MGPIO17B_H2F_B(), 
        .MMUART0_RXD_MGPIO28B_H2F_A(), .MMUART0_RXD_MGPIO28B_H2F_B(), 
        .MMUART0_SCK_MGPIO29B_H2F_A(), .MMUART0_SCK_MGPIO29B_H2F_B(), 
        .MMUART0_TXD_MGPIO27B_H2F_A(), .MMUART0_TXD_MGPIO27B_H2F_B(), 
        .MMUART1_DTR_MGPIO12B_H2F_A(), .MMUART1_RTS_MGPIO11B_H2F_A(), 
        .MMUART1_RTS_MGPIO11B_H2F_B(), .MMUART1_RXD_MGPIO26B_H2F_A(), 
        .MMUART1_RXD_MGPIO26B_H2F_B(), .MMUART1_SCK_MGPIO25B_H2F_A(), 
        .MMUART1_SCK_MGPIO25B_H2F_B(), .MMUART1_TXD_MGPIO24B_H2F_A(), 
        .MMUART1_TXD_MGPIO24B_H2F_B(), .MPLL_LOCK(), 
        .PER2_FABRIC_PADDR({nc122, nc123, nc124, nc125, nc126, nc127, 
        nc128, nc129, nc130, nc131, nc132, nc133, nc134, nc135}), 
        .PER2_FABRIC_PENABLE(), .PER2_FABRIC_PSEL(), 
        .PER2_FABRIC_PWDATA({nc136, nc137, nc138, nc139, nc140, nc141, 
        nc142, nc143, nc144, nc145, nc146, nc147, nc148, nc149, nc150, 
        nc151, nc152, nc153, nc154, nc155, nc156, nc157, nc158, nc159, 
        nc160, nc161, nc162, nc163, nc164, nc165, nc166, nc167}), 
        .PER2_FABRIC_PWRITE(), .RTC_MATCH(), .SLEEPDEEP(), 
        .SLEEPHOLDACK(), .SLEEPING(), .SMBALERT_NO0(), .SMBALERT_NO1(), 
        .SMBSUS_NO0(), .SMBSUS_NO1(), .SPI0_CLK_OUT(), 
        .SPI0_SDI_MGPIO5A_H2F_A(), .SPI0_SDI_MGPIO5A_H2F_B(), 
        .SPI0_SDO_MGPIO6A_H2F_A(), .SPI0_SDO_MGPIO6A_H2F_B(), 
        .SPI0_SS0_MGPIO7A_H2F_A(), .SPI0_SS0_MGPIO7A_H2F_B(), 
        .SPI0_SS1_MGPIO8A_H2F_A(), .SPI0_SS1_MGPIO8A_H2F_B(), 
        .SPI0_SS2_MGPIO9A_H2F_A(), .SPI0_SS2_MGPIO9A_H2F_B(), 
        .SPI0_SS3_MGPIO10A_H2F_A(), .SPI0_SS3_MGPIO10A_H2F_B(), 
        .SPI0_SS4_MGPIO19A_H2F_A(), .SPI0_SS5_MGPIO20A_H2F_A(), 
        .SPI0_SS6_MGPIO21A_H2F_A(), .SPI0_SS7_MGPIO22A_H2F_A(), 
        .SPI1_CLK_OUT(), .SPI1_SDI_MGPIO11A_H2F_A(), 
        .SPI1_SDI_MGPIO11A_H2F_B(), .SPI1_SDO_MGPIO12A_H2F_A(), 
        .SPI1_SDO_MGPIO12A_H2F_B(), .SPI1_SS0_MGPIO13A_H2F_A(), 
        .SPI1_SS0_MGPIO13A_H2F_B(), .SPI1_SS1_MGPIO14A_H2F_A(), 
        .SPI1_SS1_MGPIO14A_H2F_B(), .SPI1_SS2_MGPIO15A_H2F_A(), 
        .SPI1_SS2_MGPIO15A_H2F_B(), .SPI1_SS3_MGPIO16A_H2F_A(), 
        .SPI1_SS3_MGPIO16A_H2F_B(), .SPI1_SS4_MGPIO17A_H2F_A(), 
        .SPI1_SS5_MGPIO18A_H2F_A(), .SPI1_SS6_MGPIO23A_H2F_A(), 
        .SPI1_SS7_MGPIO24A_H2F_A(), .TCGF({nc168, nc169, nc170, nc171, 
        nc172, nc173, nc174, nc175, nc176, nc177}), .TRACECLK(), 
        .TRACEDATA({nc178, nc179, nc180, nc181}), .TX_CLK(), .TX_ENF(), 
        .TX_ERRF(), .TXCTL_EN_RIF(), .TXD_RIF({nc182, nc183, nc184, 
        nc185}), .TXDF({nc186, nc187, nc188, nc189, nc190, nc191, 
        nc192, nc193}), .TXEV(), .WDOGTIMEOUT(), .F_ARREADY_HREADYOUT1(
        ), .F_AWREADY_HREADYOUT0(), .F_BID({nc194, nc195, nc196, nc197})
        , .F_BRESP_HRESP0({nc198, nc199}), .F_BVALID(), 
        .F_RDATA_HRDATA01({nc200, nc201, nc202, nc203, nc204, nc205, 
        nc206, nc207, nc208, nc209, nc210, nc211, nc212, nc213, nc214, 
        nc215, nc216, nc217, nc218, nc219, nc220, nc221, nc222, nc223, 
        nc224, nc225, nc226, nc227, nc228, nc229, nc230, nc231, nc232, 
        nc233, nc234, nc235, nc236, nc237, nc238, nc239, nc240, nc241, 
        nc242, nc243, nc244, nc245, nc246, nc247, nc248, nc249, nc250, 
        nc251, nc252, nc253, nc254, nc255, nc256, nc257, nc258, nc259, 
        nc260, nc261, nc262, nc263}), .F_RID({nc264, nc265, nc266, 
        nc267}), .F_RLAST(), .F_RRESP_HRESP1({nc268, nc269}), 
        .F_RVALID(), .F_WREADY(), .MDDR_FABRIC_PRDATA({nc270, nc271, 
        nc272, nc273, nc274, nc275, nc276, nc277, nc278, nc279, nc280, 
        nc281, nc282, nc283, nc284, nc285}), .MDDR_FABRIC_PREADY(), 
        .MDDR_FABRIC_PSLVERR(), .CAN_RXBUS_F2H_SCP(VCC_net_1), 
        .CAN_TX_EBL_F2H_SCP(VCC_net_1), .CAN_TXBUS_F2H_SCP(VCC_net_1), 
        .COLF(VCC_net_1), .CRSF(VCC_net_1), .F2_DMAREADY({VCC_net_1, 
        VCC_net_1}), .F2H_INTERRUPT({GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1}), .F2HCALIB(VCC_net_1), 
        .F_DMAREADY({VCC_net_1, VCC_net_1}), .F_FM0_ADDR({GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1}), .F_FM0_ENABLE(GND_net_1), .F_FM0_MASTLOCK(
        GND_net_1), .F_FM0_READY(VCC_net_1), .F_FM0_SEL(GND_net_1), 
        .F_FM0_SIZE({GND_net_1, GND_net_1}), .F_FM0_TRANS1(GND_net_1), 
        .F_FM0_WDATA({GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1}), .F_FM0_WRITE(GND_net_1), 
        .F_HM0_RDATA({GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        \AMBA_SLAVE_0_HRDATA_S0_m[7] , \AMBA_SLAVE_0_HRDATA_S0_m[6] , 
        \AMBA_SLAVE_0_HRDATA_S0_m[5] , \AMBA_SLAVE_0_HRDATA_S0_m[4] , 
        \AMBA_SLAVE_0_HRDATA_S0_m[3] , \AMBA_SLAVE_0_HRDATA_S0_m[2] , 
        \AMBA_SLAVE_0_HRDATA_S0_m[1] , \AMBA_SLAVE_0_HRDATA_S0_m[0] }), 
        .F_HM0_READY(N_149_i), .F_HM0_RESP(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HRESP_0), 
        .FAB_AVALID(VCC_net_1), .FAB_HOSTDISCON(VCC_net_1), .FAB_IDDIG(
        VCC_net_1), .FAB_LINESTATE({VCC_net_1, VCC_net_1}), 
        .FAB_M3_RESET_N(VCC_net_1), .FAB_PLL_LOCK(MX2_0_Y), 
        .FAB_RXACTIVE(VCC_net_1), .FAB_RXERROR(VCC_net_1), 
        .FAB_RXVALID(VCC_net_1), .FAB_RXVALIDH(GND_net_1), 
        .FAB_SESSEND(VCC_net_1), .FAB_TXREADY(VCC_net_1), 
        .FAB_VBUSVALID(VCC_net_1), .FAB_VSTATUS({VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1}), .FAB_XDATAIN({VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .GTX_CLKPF(VCC_net_1), .I2C0_BCLK(VCC_net_1), 
        .I2C0_SCL_F2H_SCP(VCC_net_1), .I2C0_SDA_F2H_SCP(VCC_net_1), 
        .I2C1_BCLK(VCC_net_1), .I2C1_SCL_F2H_SCP(VCC_net_1), 
        .I2C1_SDA_F2H_SCP(VCC_net_1), .MDIF(VCC_net_1), 
        .MGPIO0A_F2H_GPIN(VCC_net_1), .MGPIO10A_F2H_GPIN(VCC_net_1), 
        .MGPIO11A_F2H_GPIN(VCC_net_1), .MGPIO11B_F2H_GPIN(VCC_net_1), 
        .MGPIO12A_F2H_GPIN(VCC_net_1), .MGPIO13A_F2H_GPIN(VCC_net_1), 
        .MGPIO14A_F2H_GPIN(VCC_net_1), .MGPIO15A_F2H_GPIN(VCC_net_1), 
        .MGPIO16A_F2H_GPIN(VCC_net_1), .MGPIO17B_F2H_GPIN(VCC_net_1), 
        .MGPIO18B_F2H_GPIN(VCC_net_1), .MGPIO19B_F2H_GPIN(VCC_net_1), 
        .MGPIO1A_F2H_GPIN(VCC_net_1), .MGPIO20B_F2H_GPIN(VCC_net_1), 
        .MGPIO21B_F2H_GPIN(VCC_net_1), .MGPIO22B_F2H_GPIN(VCC_net_1), 
        .MGPIO24B_F2H_GPIN(VCC_net_1), .MGPIO25B_F2H_GPIN(VCC_net_1), 
        .MGPIO26B_F2H_GPIN(VCC_net_1), .MGPIO27B_F2H_GPIN(VCC_net_1), 
        .MGPIO28B_F2H_GPIN(VCC_net_1), .MGPIO29B_F2H_GPIN(VCC_net_1), 
        .MGPIO2A_F2H_GPIN(VCC_net_1), .MGPIO30B_F2H_GPIN(VCC_net_1), 
        .MGPIO31B_F2H_GPIN(VCC_net_1), .MGPIO3A_F2H_GPIN(VCC_net_1), 
        .MGPIO4A_F2H_GPIN(VCC_net_1), .MGPIO5A_F2H_GPIN(VCC_net_1), 
        .MGPIO6A_F2H_GPIN(VCC_net_1), .MGPIO7A_F2H_GPIN(VCC_net_1), 
        .MGPIO8A_F2H_GPIN(VCC_net_1), .MGPIO9A_F2H_GPIN(VCC_net_1), 
        .MMUART0_CTS_F2H_SCP(VCC_net_1), .MMUART0_DCD_F2H_SCP(
        VCC_net_1), .MMUART0_DSR_F2H_SCP(VCC_net_1), 
        .MMUART0_DTR_F2H_SCP(VCC_net_1), .MMUART0_RI_F2H_SCP(VCC_net_1)
        , .MMUART0_RTS_F2H_SCP(VCC_net_1), .MMUART0_RXD_F2H_SCP(
        VCC_net_1), .MMUART0_SCK_F2H_SCP(VCC_net_1), 
        .MMUART0_TXD_F2H_SCP(VCC_net_1), .MMUART1_CTS_F2H_SCP(
        VCC_net_1), .MMUART1_DCD_F2H_SCP(VCC_net_1), 
        .MMUART1_DSR_F2H_SCP(VCC_net_1), .MMUART1_RI_F2H_SCP(VCC_net_1)
        , .MMUART1_RTS_F2H_SCP(VCC_net_1), .MMUART1_RXD_F2H_SCP(
        VCC_net_1), .MMUART1_SCK_F2H_SCP(VCC_net_1), 
        .MMUART1_TXD_F2H_SCP(VCC_net_1), .PER2_FABRIC_PRDATA({
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1}), .PER2_FABRIC_PREADY(VCC_net_1), 
        .PER2_FABRIC_PSLVERR(GND_net_1), .RCGF({VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1}), .RX_CLKPF(VCC_net_1), 
        .RX_DVF(VCC_net_1), .RX_ERRF(VCC_net_1), .RX_EV(VCC_net_1), 
        .RXDF({VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1}), .SLEEPHOLDREQ(GND_net_1), 
        .SMBALERT_NI0(VCC_net_1), .SMBALERT_NI1(VCC_net_1), 
        .SMBSUS_NI0(VCC_net_1), .SMBSUS_NI1(VCC_net_1), .SPI0_CLK_IN(
        VCC_net_1), .SPI0_SDI_F2H_SCP(VCC_net_1), .SPI0_SDO_F2H_SCP(
        VCC_net_1), .SPI0_SS0_F2H_SCP(VCC_net_1), .SPI0_SS1_F2H_SCP(
        VCC_net_1), .SPI0_SS2_F2H_SCP(VCC_net_1), .SPI0_SS3_F2H_SCP(
        VCC_net_1), .SPI1_CLK_IN(VCC_net_1), .SPI1_SDI_F2H_SCP(
        VCC_net_1), .SPI1_SDO_F2H_SCP(VCC_net_1), .SPI1_SS0_F2H_SCP(
        VCC_net_1), .SPI1_SS1_F2H_SCP(VCC_net_1), .SPI1_SS2_F2H_SCP(
        VCC_net_1), .SPI1_SS3_F2H_SCP(VCC_net_1), .TX_CLKPF(VCC_net_1), 
        .USER_MSS_GPIO_RESET_N(VCC_net_1), .USER_MSS_RESET_N(VCC_net_1)
        , .XCLK_FAB(VCC_net_1), .CLK_BASE(FlashFreeze_SB_0_FIC_0_CLK), 
        .CLK_MDDR_APB(VCC_net_1), .F_ARADDR_HADDR1({VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1}), .F_ARBURST_HTRANS1({GND_net_1, GND_net_1}), 
        .F_ARID_HSEL1({GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .F_ARLEN_HBURST1({GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .F_ARLOCK_HMASTLOCK1({GND_net_1, GND_net_1}), .F_ARSIZE_HSIZE1({
        GND_net_1, GND_net_1}), .F_ARVALID_HWRITE1(GND_net_1), 
        .F_AWADDR_HADDR0({VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1}), .F_AWBURST_HTRANS0({
        GND_net_1, GND_net_1}), .F_AWID_HSEL0({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1}), .F_AWLEN_HBURST0({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1}), .F_AWLOCK_HMASTLOCK0({GND_net_1, 
        GND_net_1}), .F_AWSIZE_HSIZE0({GND_net_1, GND_net_1}), 
        .F_AWVALID_HWRITE0(GND_net_1), .F_BREADY(GND_net_1), 
        .F_RMW_AXI(GND_net_1), .F_RREADY(GND_net_1), .F_WDATA_HWDATA01({
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), .F_WID_HREADY01({
        GND_net_1, GND_net_1, GND_net_1, GND_net_1}), .F_WLAST(
        GND_net_1), .F_WSTRB({GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1}), 
        .F_WVALID(GND_net_1), .FPGA_MDDR_ARESET_N(VCC_net_1), 
        .MDDR_FABRIC_PADDR({VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1}), 
        .MDDR_FABRIC_PENABLE(VCC_net_1), .MDDR_FABRIC_PSEL(VCC_net_1), 
        .MDDR_FABRIC_PWDATA({VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, VCC_net_1, 
        VCC_net_1, VCC_net_1, VCC_net_1}), .MDDR_FABRIC_PWRITE(
        VCC_net_1), .PRESET_N(GND_net_1), 
        .CAN_RXBUS_USBA_DATA1_MGPIO3A_IN(GND_net_1), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_IN(GND_net_1), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_IN(GND_net_1), .DM_IN({GND_net_1, 
        GND_net_1, GND_net_1}), .DRAM_DQ_IN({GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1, GND_net_1, GND_net_1, GND_net_1, GND_net_1, 
        GND_net_1}), .DRAM_DQS_IN({GND_net_1, GND_net_1, GND_net_1}), 
        .DRAM_FIFO_WE_IN({GND_net_1, GND_net_1}), 
        .I2C0_SCL_USBC_DATA1_MGPIO31B_IN(GND_net_1), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_IN(GND_net_1), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_IN(GND_net_1), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_IN(GND_net_1), .MGPIO0B_IN(
        GND_net_1), .MGPIO10B_IN(GND_net_1), .MGPIO1B_IN(GND_net_1), 
        .MGPIO25A_IN(GND_net_1), .MGPIO26A_IN(GND_net_1), .MGPIO27A_IN(
        GND_net_1), .MGPIO28A_IN(GND_net_1), .MGPIO29A_IN(GND_net_1), 
        .MGPIO2B_IN(GND_net_1), .MGPIO30A_IN(GND_net_1), .MGPIO31A_IN(
        GND_net_1), .MGPIO3B_IN(GND_net_1), .MGPIO4B_IN(GND_net_1), 
        .MGPIO5B_IN(GND_net_1), .MGPIO6B_IN(GND_net_1), .MGPIO7B_IN(
        GND_net_1), .MGPIO8B_IN(GND_net_1), .MGPIO9B_IN(GND_net_1), 
        .MMUART0_CTS_USBC_DATA7_MGPIO19B_IN(GND_net_1), 
        .MMUART0_DCD_MGPIO22B_IN(GND_net_1), .MMUART0_DSR_MGPIO20B_IN(
        GND_net_1), .MMUART0_DTR_USBC_DATA6_MGPIO18B_IN(GND_net_1), 
        .MMUART0_RI_MGPIO21B_IN(GND_net_1), 
        .MMUART0_RTS_USBC_DATA5_MGPIO17B_IN(GND_net_1), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_IN(GND_net_1), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_IN(GND_net_1), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_IN(GND_net_1), 
        .MMUART1_CTS_MGPIO13B_IN(GND_net_1), .MMUART1_DCD_MGPIO16B_IN(
        GND_net_1), .MMUART1_DSR_MGPIO14B_IN(GND_net_1), 
        .MMUART1_DTR_MGPIO12B_IN(GND_net_1), .MMUART1_RI_MGPIO15B_IN(
        GND_net_1), .MMUART1_RTS_MGPIO11B_IN(GND_net_1), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_IN(MMUART_1_RXD_PAD_Y), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_IN(GND_net_1), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_IN(GND_net_1), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_IN(GND_net_1), 
        .RGMII_MDC_RMII_MDC_IN(GND_net_1), 
        .RGMII_MDIO_RMII_MDIO_USBB_DATA7_IN(GND_net_1), 
        .RGMII_RX_CLK_IN(GND_net_1), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_IN(GND_net_1), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_IN(GND_net_1), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_IN(GND_net_1), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_IN(GND_net_1), 
        .RGMII_RXD3_USBB_DATA4_IN(GND_net_1), .RGMII_TX_CLK_IN(
        GND_net_1), .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_IN(GND_net_1), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_IN(GND_net_1), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_IN(GND_net_1), 
        .RGMII_TXD2_USBB_DATA5_IN(GND_net_1), 
        .RGMII_TXD3_USBB_DATA6_IN(GND_net_1), .SPI0_SCK_USBA_XCLK_IN(
        GND_net_1), .SPI0_SDI_USBA_DIR_MGPIO5A_IN(GND_net_1), 
        .SPI0_SDO_USBA_STP_MGPIO6A_IN(GND_net_1), 
        .SPI0_SS0_USBA_NXT_MGPIO7A_IN(GND_net_1), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_IN(GND_net_1), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_IN(GND_net_1), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_IN(GND_net_1), 
        .SPI0_SS4_MGPIO19A_IN(GND_net_1), .SPI0_SS5_MGPIO20A_IN(
        GND_net_1), .SPI0_SS6_MGPIO21A_IN(GND_net_1), 
        .SPI0_SS7_MGPIO22A_IN(GND_net_1), .SPI1_SCK_IN(GND_net_1), 
        .SPI1_SDI_MGPIO11A_IN(GND_net_1), .SPI1_SDO_MGPIO12A_IN(
        GND_net_1), .SPI1_SS0_MGPIO13A_IN(GND_net_1), 
        .SPI1_SS1_MGPIO14A_IN(GND_net_1), .SPI1_SS2_MGPIO15A_IN(
        GND_net_1), .SPI1_SS3_MGPIO16A_IN(GND_net_1), 
        .SPI1_SS4_MGPIO17A_IN(GND_net_1), .SPI1_SS5_MGPIO18A_IN(
        GND_net_1), .SPI1_SS6_MGPIO23A_IN(GND_net_1), 
        .SPI1_SS7_MGPIO24A_IN(GND_net_1), .USBC_XCLK_IN(GND_net_1), 
        .USBD_DATA0_IN(GND_net_1), .USBD_DATA1_IN(GND_net_1), 
        .USBD_DATA2_IN(GND_net_1), .USBD_DATA3_IN(GND_net_1), 
        .USBD_DATA4_IN(GND_net_1), .USBD_DATA5_IN(GND_net_1), 
        .USBD_DATA6_IN(GND_net_1), .USBD_DATA7_MGPIO23B_IN(GND_net_1), 
        .USBD_DIR_IN(GND_net_1), .USBD_NXT_IN(GND_net_1), .USBD_STP_IN(
        GND_net_1), .USBD_XCLK_IN(GND_net_1), 
        .CAN_RXBUS_USBA_DATA1_MGPIO3A_OUT(), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_OUT(), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_OUT(), .DRAM_ADDR({nc286, nc287, 
        nc288, nc289, nc290, nc291, nc292, nc293, nc294, nc295, nc296, 
        nc297, nc298, nc299, nc300, nc301}), .DRAM_BA({nc302, nc303, 
        nc304}), .DRAM_CASN(), .DRAM_CKE(), .DRAM_CLK(), .DRAM_CSN(), 
        .DRAM_DM_RDQS_OUT({nc305, nc306, nc307}), .DRAM_DQ_OUT({nc308, 
        nc309, nc310, nc311, nc312, nc313, nc314, nc315, nc316, nc317, 
        nc318, nc319, nc320, nc321, nc322, nc323, nc324, nc325}), 
        .DRAM_DQS_OUT({nc326, nc327, nc328}), .DRAM_FIFO_WE_OUT({nc329, 
        nc330}), .DRAM_ODT(), .DRAM_RASN(), .DRAM_RSTN(), .DRAM_WEN(), 
        .I2C0_SCL_USBC_DATA1_MGPIO31B_OUT(), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_OUT(), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_OUT(), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_OUT(), .MGPIO0B_OUT(), 
        .MGPIO10B_OUT(), .MGPIO1B_OUT(), .MGPIO25A_OUT(), 
        .MGPIO26A_OUT(), .MGPIO27A_OUT(), .MGPIO28A_OUT(), 
        .MGPIO29A_OUT(), .MGPIO2B_OUT(), .MGPIO30A_OUT(), 
        .MGPIO31A_OUT(), .MGPIO3B_OUT(), .MGPIO4B_OUT(), .MGPIO5B_OUT()
        , .MGPIO6B_OUT(), .MGPIO7B_OUT(), .MGPIO8B_OUT(), .MGPIO9B_OUT(
        ), .MMUART0_CTS_USBC_DATA7_MGPIO19B_OUT(), 
        .MMUART0_DCD_MGPIO22B_OUT(), .MMUART0_DSR_MGPIO20B_OUT(), 
        .MMUART0_DTR_USBC_DATA6_MGPIO18B_OUT(), 
        .MMUART0_RI_MGPIO21B_OUT(), 
        .MMUART0_RTS_USBC_DATA5_MGPIO17B_OUT(), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_OUT(), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_OUT(), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_OUT(), 
        .MMUART1_CTS_MGPIO13B_OUT(), .MMUART1_DCD_MGPIO16B_OUT(), 
        .MMUART1_DSR_MGPIO14B_OUT(), .MMUART1_DTR_MGPIO12B_OUT(), 
        .MMUART1_RI_MGPIO15B_OUT(), .MMUART1_RTS_MGPIO11B_OUT(), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_OUT(), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_OUT(), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT(
        MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OUT), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OUT(), 
        .RGMII_MDC_RMII_MDC_OUT(), 
        .RGMII_MDIO_RMII_MDIO_USBB_DATA7_OUT(), .RGMII_RX_CLK_OUT(), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OUT(), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_OUT(), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_OUT(), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OUT(), 
        .RGMII_RXD3_USBB_DATA4_OUT(), .RGMII_TX_CLK_OUT(), 
        .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OUT(), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_OUT(), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_OUT(), 
        .RGMII_TXD2_USBB_DATA5_OUT(), .RGMII_TXD3_USBB_DATA6_OUT(), 
        .SPI0_SCK_USBA_XCLK_OUT(), .SPI0_SDI_USBA_DIR_MGPIO5A_OUT(), 
        .SPI0_SDO_USBA_STP_MGPIO6A_OUT(), 
        .SPI0_SS0_USBA_NXT_MGPIO7A_OUT(), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_OUT(), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_OUT(), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_OUT(), .SPI0_SS4_MGPIO19A_OUT(), 
        .SPI0_SS5_MGPIO20A_OUT(), .SPI0_SS6_MGPIO21A_OUT(), 
        .SPI0_SS7_MGPIO22A_OUT(), .SPI1_SCK_OUT(), 
        .SPI1_SDI_MGPIO11A_OUT(), .SPI1_SDO_MGPIO12A_OUT(), 
        .SPI1_SS0_MGPIO13A_OUT(), .SPI1_SS1_MGPIO14A_OUT(), 
        .SPI1_SS2_MGPIO15A_OUT(), .SPI1_SS3_MGPIO16A_OUT(), 
        .SPI1_SS4_MGPIO17A_OUT(), .SPI1_SS5_MGPIO18A_OUT(), 
        .SPI1_SS6_MGPIO23A_OUT(), .SPI1_SS7_MGPIO24A_OUT(), 
        .USBC_XCLK_OUT(), .USBD_DATA0_OUT(), .USBD_DATA1_OUT(), 
        .USBD_DATA2_OUT(), .USBD_DATA3_OUT(), .USBD_DATA4_OUT(), 
        .USBD_DATA5_OUT(), .USBD_DATA6_OUT(), .USBD_DATA7_MGPIO23B_OUT(
        ), .USBD_DIR_OUT(), .USBD_NXT_OUT(), .USBD_STP_OUT(), 
        .USBD_XCLK_OUT(), .CAN_RXBUS_USBA_DATA1_MGPIO3A_OE(), 
        .CAN_TX_EBL_USBA_DATA2_MGPIO4A_OE(), 
        .CAN_TXBUS_USBA_DATA0_MGPIO2A_OE(), .DM_OE({nc331, nc332, 
        nc333}), .DRAM_DQ_OE({nc334, nc335, nc336, nc337, nc338, nc339, 
        nc340, nc341, nc342, nc343, nc344, nc345, nc346, nc347, nc348, 
        nc349, nc350, nc351}), .DRAM_DQS_OE({nc352, nc353, nc354}), 
        .I2C0_SCL_USBC_DATA1_MGPIO31B_OE(), 
        .I2C0_SDA_USBC_DATA0_MGPIO30B_OE(), 
        .I2C1_SCL_USBA_DATA4_MGPIO1A_OE(), 
        .I2C1_SDA_USBA_DATA3_MGPIO0A_OE(), .MGPIO0B_OE(), .MGPIO10B_OE(
        ), .MGPIO1B_OE(), .MGPIO25A_OE(), .MGPIO26A_OE(), .MGPIO27A_OE(
        ), .MGPIO28A_OE(), .MGPIO29A_OE(), .MGPIO2B_OE(), .MGPIO30A_OE(
        ), .MGPIO31A_OE(), .MGPIO3B_OE(), .MGPIO4B_OE(), .MGPIO5B_OE(), 
        .MGPIO6B_OE(), .MGPIO7B_OE(), .MGPIO8B_OE(), .MGPIO9B_OE(), 
        .MMUART0_CTS_USBC_DATA7_MGPIO19B_OE(), 
        .MMUART0_DCD_MGPIO22B_OE(), .MMUART0_DSR_MGPIO20B_OE(), 
        .MMUART0_DTR_USBC_DATA6_MGPIO18B_OE(), .MMUART0_RI_MGPIO21B_OE(
        ), .MMUART0_RTS_USBC_DATA5_MGPIO17B_OE(), 
        .MMUART0_RXD_USBC_STP_MGPIO28B_OE(), 
        .MMUART0_SCK_USBC_NXT_MGPIO29B_OE(), 
        .MMUART0_TXD_USBC_DIR_MGPIO27B_OE(), .MMUART1_CTS_MGPIO13B_OE()
        , .MMUART1_DCD_MGPIO16B_OE(), .MMUART1_DSR_MGPIO14B_OE(), 
        .MMUART1_DTR_MGPIO12B_OE(), .MMUART1_RI_MGPIO15B_OE(), 
        .MMUART1_RTS_MGPIO11B_OE(), 
        .MMUART1_RXD_USBC_DATA3_MGPIO26B_OE(), 
        .MMUART1_SCK_USBC_DATA4_MGPIO25B_OE(), 
        .MMUART1_TXD_USBC_DATA2_MGPIO24B_OE(
        MSS_ADLIB_INST_MMUART1_TXD_USBC_DATA2_MGPIO24B_OE), 
        .RGMII_GTX_CLK_RMII_CLK_USBB_XCLK_OE(), .RGMII_MDC_RMII_MDC_OE(
        ), .RGMII_MDIO_RMII_MDIO_USBB_DATA7_OE(), .RGMII_RX_CLK_OE(), 
        .RGMII_RX_CTL_RMII_CRS_DV_USBB_DATA2_OE(), 
        .RGMII_RXD0_RMII_RXD0_USBB_DATA0_OE(), 
        .RGMII_RXD1_RMII_RXD1_USBB_DATA1_OE(), 
        .RGMII_RXD2_RMII_RX_ER_USBB_DATA3_OE(), 
        .RGMII_RXD3_USBB_DATA4_OE(), .RGMII_TX_CLK_OE(), 
        .RGMII_TX_CTL_RMII_TX_EN_USBB_NXT_OE(), 
        .RGMII_TXD0_RMII_TXD0_USBB_DIR_OE(), 
        .RGMII_TXD1_RMII_TXD1_USBB_STP_OE(), .RGMII_TXD2_USBB_DATA5_OE(
        ), .RGMII_TXD3_USBB_DATA6_OE(), .SPI0_SCK_USBA_XCLK_OE(), 
        .SPI0_SDI_USBA_DIR_MGPIO5A_OE(), .SPI0_SDO_USBA_STP_MGPIO6A_OE(
        ), .SPI0_SS0_USBA_NXT_MGPIO7A_OE(), 
        .SPI0_SS1_USBA_DATA5_MGPIO8A_OE(), 
        .SPI0_SS2_USBA_DATA6_MGPIO9A_OE(), 
        .SPI0_SS3_USBA_DATA7_MGPIO10A_OE(), .SPI0_SS4_MGPIO19A_OE(), 
        .SPI0_SS5_MGPIO20A_OE(), .SPI0_SS6_MGPIO21A_OE(), 
        .SPI0_SS7_MGPIO22A_OE(), .SPI1_SCK_OE(), .SPI1_SDI_MGPIO11A_OE(
        ), .SPI1_SDO_MGPIO12A_OE(), .SPI1_SS0_MGPIO13A_OE(), 
        .SPI1_SS1_MGPIO14A_OE(), .SPI1_SS2_MGPIO15A_OE(), 
        .SPI1_SS3_MGPIO16A_OE(), .SPI1_SS4_MGPIO17A_OE(), 
        .SPI1_SS5_MGPIO18A_OE(), .SPI1_SS6_MGPIO23A_OE(), 
        .SPI1_SS7_MGPIO24A_OE(), .USBC_XCLK_OE(), .USBD_DATA0_OE(), 
        .USBD_DATA1_OE(), .USBD_DATA2_OE(), .USBD_DATA3_OE(), 
        .USBD_DATA4_OE(), .USBD_DATA5_OE(), .USBD_DATA6_OE(), 
        .USBD_DATA7_MGPIO23B_OE(), .USBD_DIR_OE(), .USBD_NXT_OE(), 
        .USBD_STP_OE(), .USBD_XCLK_OE());
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNO_6 (.A(m0s0DataSel), .B(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[7]), .Y(
        \AMBA_SLAVE_0_HRDATA_S0_m[7] ));
    CFG2 #( .INIT(4'h8) )  MSS_ADLIB_INST_RNO_2 (.A(m0s0DataSel), .B(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[3]), .Y(
        \AMBA_SLAVE_0_HRDATA_S0_m[3] ));
    
endmodule


module FlashFreeze_SB(
       FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA,
       FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA,
       M0GATEDHADDR,
       CAHBtoAPB3IOI_3,
       CAHBtoAPB3IOI_0,
       CAHBtoAPB3IOI_4,
       masterAddrInProg_0,
       MMUART_1_TXD,
       MMUART_1_RXD_0,
       CoreAPB3_0_APBmslave0_PWRITE,
       CAHBtoAPB3ll4,
       CAHBtoAPB3lII,
       N_250,
       N_181_mux_i,
       CAHBtoAPB3II,
       N_151,
       CAHBtoAPB3III,
       N_25_0,
       CoreAPB3_0_APBmslave0_PSELx,
       CoreAPB3_0_APBmslave0_PREADY,
       PENABLE,
       N_54_0,
       N_63_0,
       CAHBtoAPB3OI,
       N_153_mux,
       N_56_0_i,
       m19_e_0,
       N_178_mux,
       N_247_mux,
       N_179_mux,
       N_177_mux_i,
       CAHBtoAPB3lI,
       N_12_i,
       N_55_i,
       N_57_i,
       N_59_i,
       N_61_i,
       N_123_i,
       N_125_i,
       N_51_i,
       N_122_i,
       N_126_i,
       N_128_i,
       N_129_i,
       N_131_i,
       N_171_mux,
       FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY,
       N_185,
       N_186,
       N_187,
       N_188,
       N_189,
       N_190,
       N_191,
       N_192,
       FlashFreeze_SB_0_FIC_0_CLK,
       FLASH_FREEZE_0_FF_DONE,
       FIC_0_LOCK_c,
       DEVRST_N,
       FlashFreeze_SB_0_POWER_ON_RESET_N
    );
input  [7:0] FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA;
output [7:0] FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA;
output [27:24] M0GATEDHADDR;
input  CAHBtoAPB3IOI_3;
input  CAHBtoAPB3IOI_0;
input  CAHBtoAPB3IOI_4;
output masterAddrInProg_0;
output MMUART_1_TXD;
input  MMUART_1_RXD_0;
input  CoreAPB3_0_APBmslave0_PWRITE;
input  CAHBtoAPB3ll4;
input  CAHBtoAPB3lII;
input  N_250;
output N_181_mux_i;
output CAHBtoAPB3II;
output N_151;
input  CAHBtoAPB3III;
output N_25_0;
input  CoreAPB3_0_APBmslave0_PSELx;
input  CoreAPB3_0_APBmslave0_PREADY;
input  PENABLE;
output N_54_0;
output N_63_0;
input  CAHBtoAPB3OI;
output N_153_mux;
output N_56_0_i;
output m19_e_0;
output N_178_mux;
output N_247_mux;
output N_179_mux;
output N_177_mux_i;
output CAHBtoAPB3lI;
output N_12_i;
output N_55_i;
output N_57_i;
output N_59_i;
output N_61_i;
output N_123_i;
output N_125_i;
output N_51_i;
output N_122_i;
output N_126_i;
output N_128_i;
output N_129_i;
output N_131_i;
output N_171_mux;
input  FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY;
output N_185;
output N_186;
output N_187;
output N_188;
output N_189;
output N_190;
output N_191;
output N_192;
output FlashFreeze_SB_0_FIC_0_CLK;
input  FLASH_FREEZE_0_FF_DONE;
inout  FIC_0_LOCK_c;
input  DEVRST_N;
output FlashFreeze_SB_0_POWER_ON_RESET_N;

    wire SYSRESET_POR_net_1, MX2_0_Y, VCC_net_1, 
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC, 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS[1] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[24] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[25] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[26] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[27] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[7] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[0] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[1] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[2] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[3] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[4] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[5] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[6] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[0] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[1] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[2] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[3] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[4] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[5] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[6] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[7] , 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HRESP_0, N_149_i, 
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE, m0s0DataSel, 
        un1_FlashFreeze_SB_0_1_i_i, 
        FlashFreeze_SB_MSS_TMP_0_MSS_RESET_N_M2F, 
        FlashFreeze_SB_MSS_TMP_0_FIC_2_APB_M_PRESET_N, GND_net_1;
    
    CLKINT SYSRESET_POR_RNIIH4C (.A(SYSRESET_POR_net_1), .Y(
        FlashFreeze_SB_0_POWER_ON_RESET_N));
    MX2 MX2_0 (.A(FIC_0_LOCK_c), .B(VCC_net_1), .S(
        FLASH_FREEZE_0_FF_DONE), .Y(MX2_0_Y));
    FlashFreeze_SB_FABOSC_0_OSC FABOSC_0 (
        .FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC));
    CoreResetP_Z6 CORERESETP_0 (
        .FlashFreeze_SB_MSS_TMP_0_MSS_RESET_N_M2F(
        FlashFreeze_SB_MSS_TMP_0_MSS_RESET_N_M2F), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_2_APB_M_PRESET_N(
        FlashFreeze_SB_MSS_TMP_0_FIC_2_APB_M_PRESET_N), 
        .FlashFreeze_SB_0_POWER_ON_RESET_N(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .FLASH_FREEZE_0_FF_DONE(
        FLASH_FREEZE_0_FF_DONE), .FlashFreeze_SB_0_FIC_0_CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .un1_FlashFreeze_SB_0_1_i_i(
        un1_FlashFreeze_SB_0_1_i_i));
    CoreAHBLite_Z5 CoreAHBLite_0 (.M0GATEDHADDR({M0GATEDHADDR[27], 
        M0GATEDHADDR[26], M0GATEDHADDR[25], M0GATEDHADDR[24]}), 
        .FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA({
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[7], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[6], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[5], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[4], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[3], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[2], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[1], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[0]}), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA({
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[7] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[6] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[5] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[4] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[3] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[2] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[1] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[0] }), 
        .masterAddrInProg_0(masterAddrInProg_0), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0(
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS[1] ), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_24(
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[24] ), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_25(
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[25] ), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_26(
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[26] ), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_27(
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[27] ), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_7(
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[7] ), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_0(
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[0] ), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_1(
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[1] ), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_2(
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[2] ), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_3(
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[3] ), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_4(
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[4] ), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_5(
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[5] ), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_6(
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[6] ), 
        .CAHBtoAPB3IOI_3(CAHBtoAPB3IOI_3), .CAHBtoAPB3IOI_0(
        CAHBtoAPB3IOI_0), .CAHBtoAPB3IOI_4(CAHBtoAPB3IOI_4), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HRESP_0(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HRESP_0), .N_149_i(
        N_149_i), .N_192(N_192), .N_191(N_191), .N_190(N_190), .N_189(
        N_189), .N_188(N_188), .N_187(N_187), .N_186(N_186), .N_185(
        N_185), .FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE), 
        .m0s0DataSel(m0s0DataSel), .FlashFreeze_SB_0_FIC_0_CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .un1_FlashFreeze_SB_0_1_i_i(
        un1_FlashFreeze_SB_0_1_i_i), .N_171_mux(N_171_mux), .N_131_i(
        N_131_i), .N_129_i(N_129_i), .N_128_i(N_128_i), .N_126_i(
        N_126_i), .N_122_i(N_122_i), .N_51_i(N_51_i), .N_125_i(N_125_i)
        , .N_123_i(N_123_i), .N_61_i(N_61_i), .N_59_i(N_59_i), .N_57_i(
        N_57_i), .N_55_i(N_55_i), .N_12_i(N_12_i), .CAHBtoAPB3lI(
        CAHBtoAPB3lI), .N_177_mux_i(N_177_mux_i), .N_179_mux(N_179_mux)
        , .N_247_mux(N_247_mux), .N_178_mux(N_178_mux), .m19_e_0(
        m19_e_0), .N_56_0_i(N_56_0_i), .N_153_mux(N_153_mux), 
        .CAHBtoAPB3OI(CAHBtoAPB3OI), .N_63_0(N_63_0), .N_54_0(N_54_0), 
        .PENABLE(PENABLE), .CoreAPB3_0_APBmslave0_PREADY(
        CoreAPB3_0_APBmslave0_PREADY), .CoreAPB3_0_APBmslave0_PSELx(
        CoreAPB3_0_APBmslave0_PSELx), .N_25_0(N_25_0), .CAHBtoAPB3III(
        CAHBtoAPB3III), .N_151(N_151), .CAHBtoAPB3II(CAHBtoAPB3II), 
        .N_181_mux_i(N_181_mux_i), .N_250(N_250), .CAHBtoAPB3lII(
        CAHBtoAPB3lII), .CAHBtoAPB3ll4(CAHBtoAPB3ll4), 
        .CoreAPB3_0_APBmslave0_PWRITE(CoreAPB3_0_APBmslave0_PWRITE));
    VCC VCC (.Y(VCC_net_1));
    FlashFreeze_SB_CCC_0_FCCC CCC_0 (
        .FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC(
        FABOSC_0_RCOSC_25_50MHZ_CCC_OUT_RCOSC_25_50MHZ_CCC), 
        .FIC_0_LOCK_c(FIC_0_LOCK_c), .FlashFreeze_SB_0_FIC_0_CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .FLASH_FREEZE_0_FF_DONE(
        FLASH_FREEZE_0_FF_DONE));
    GND GND (.Y(GND_net_1));
    FlashFreeze_SB_MSS FlashFreeze_SB_MSS_0 (
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA({
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[7] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[6] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[5] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[4] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[3] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[2] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[1] , 
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWDATA[0] }), 
        .FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA({
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[7], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[6], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[5], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[4], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[3], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[2], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[1], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[0]}), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS_0(
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HTRANS[1] ), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_0(
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[0] ), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_1(
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[1] ), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_2(
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[2] ), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_3(
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[3] ), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_4(
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[4] ), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_5(
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[5] ), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_6(
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[6] ), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_7(
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[7] ), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_24(
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[24] ), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_25(
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[25] ), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_26(
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[26] ), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR_27(
        \FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HADDR[27] ), 
        .FlashFreeze_SB_0_FIC_0_CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .MX2_0_Y(MX2_0_Y), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HRESP_0(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HRESP_0), .N_149_i(
        N_149_i), .FlashFreeze_SB_MSS_TMP_0_MSS_RESET_N_M2F(
        FlashFreeze_SB_MSS_TMP_0_MSS_RESET_N_M2F), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE(
        FlashFreeze_SB_MSS_TMP_0_FIC_0_AHB_MASTER_HWRITE), 
        .FlashFreeze_SB_MSS_TMP_0_FIC_2_APB_M_PRESET_N(
        FlashFreeze_SB_MSS_TMP_0_FIC_2_APB_M_PRESET_N), .m0s0DataSel(
        m0s0DataSel), .MMUART_1_RXD_0(MMUART_1_RXD_0), .MMUART_1_TXD(
        MMUART_1_TXD));
    SYSRESET SYSRESET_POR (.POWER_ON_RESET_N(SYSRESET_POR_net_1), 
        .DEVRST_N(DEVRST_N));
    
endmodule


module CAHBtoAPB3OIl_0s_0_1_2(
       N_25_0,
       N_171_mux,
       PENABLE,
       FlashFreeze_SB_0_FIC_0_CLK,
       FlashFreeze_SB_0_POWER_ON_RESET_N
    );
input  N_25_0;
input  N_171_mux;
output PENABLE;
input  FlashFreeze_SB_0_FIC_0_CLK;
input  FlashFreeze_SB_0_POWER_ON_RESET_N;

    wire \CAHBtoAPB3lIl[0]_net_1 , VCC_net_1, \CAHBtoAPB3lIl_ns[0] , 
        GND_net_1, \CAHBtoAPB3Oll[1] ;
    
    CFG3 #( .INIT(8'hAE) )  \CAHBtoAPB3Oll_0[1]  (.A(
        \CAHBtoAPB3lIl[0]_net_1 ), .B(PENABLE), .C(N_25_0), .Y(
        \CAHBtoAPB3Oll[1] ));
    VCC VCC (.Y(VCC_net_1));
    SLE \CAHBtoAPB3lIl[1]  (.D(\CAHBtoAPB3Oll[1] ), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(PENABLE));
    GND GND (.Y(GND_net_1));
    SLE \CAHBtoAPB3lIl[0]  (.D(\CAHBtoAPB3lIl_ns[0] ), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \CAHBtoAPB3lIl[0]_net_1 ));
    CFG3 #( .INIT(8'h04) )  \CAHBtoAPB3lIl_ns_0_a3[0]  (.A(PENABLE), 
        .B(N_171_mux), .C(\CAHBtoAPB3lIl[0]_net_1 ), .Y(
        \CAHBtoAPB3lIl_ns[0] ));
    
endmodule


module CAHBtoAPB3l1I_0s(
       M0GATEDHADDR,
       CoreAPB3_0_APBmslave0_PRDATA_m,
       FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA,
       COREAHBTOAPB3_0_APBmaster_PADDR,
       CoreAPB3_0_APBmslave0_PADDR,
       FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA,
       CoreAPB3_0_APBmslave0_PWDATA,
       masterAddrInProg_0,
       N_192,
       N_191,
       N_190,
       N_189,
       N_188,
       N_187,
       N_186,
       N_185,
       N_250,
       N_63_0,
       N_54_0,
       CAHBtoAPB3OOl_m4_0_o4_0,
       FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY,
       m19_e_0,
       N_122_i,
       N_51_i,
       CAHBtoAPB3OI,
       CAHBtoAPB3II,
       N_131_i,
       N_129_i,
       N_128_i,
       N_126_i,
       N_125_i,
       N_123_i,
       N_61_i,
       N_59_i,
       N_57_i,
       CAHBtoAPB3lI,
       N_55_i,
       FlashFreeze_SB_0_FIC_0_CLK,
       FlashFreeze_SB_0_POWER_ON_RESET_N
    );
input  [27:24] M0GATEDHADDR;
input  [7:0] CoreAPB3_0_APBmslave0_PRDATA_m;
output [7:0] FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA;
output [27:24] COREAHBTOAPB3_0_APBmaster_PADDR;
output [7:0] CoreAPB3_0_APBmslave0_PADDR;
input  [7:0] FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA;
output [7:0] CoreAPB3_0_APBmslave0_PWDATA;
input  masterAddrInProg_0;
input  N_192;
input  N_191;
input  N_190;
input  N_189;
input  N_188;
input  N_187;
input  N_186;
input  N_185;
input  N_250;
input  N_63_0;
input  N_54_0;
output CAHBtoAPB3OOl_m4_0_o4_0;
input  FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY;
input  m19_e_0;
input  N_122_i;
input  N_51_i;
input  CAHBtoAPB3OI;
input  CAHBtoAPB3II;
input  N_131_i;
input  N_129_i;
input  N_128_i;
input  N_126_i;
input  N_125_i;
input  N_123_i;
input  N_61_i;
input  N_59_i;
input  N_57_i;
input  CAHBtoAPB3lI;
input  N_55_i;
input  FlashFreeze_SB_0_FIC_0_CLK;
input  FlashFreeze_SB_0_POWER_ON_RESET_N;

    wire \CAHBtoAPB3IOl[2]_net_1 , VCC_net_1, GND_net_1, 
        \CAHBtoAPB3IOl[3]_net_1 , \CAHBtoAPB3IOl[4]_net_1 , 
        \CAHBtoAPB3IOl[5]_net_1 , \CAHBtoAPB3IOl[6]_net_1 , 
        \CAHBtoAPB3IOl[7]_net_1 , \CAHBtoAPB3IOl[24]_net_1 , 
        \CAHBtoAPB3IOl[25]_net_1 , \CAHBtoAPB3IOl[26]_net_1 , 
        \CAHBtoAPB3IOl[27]_net_1 , \CAHBtoAPB3IOl[0]_net_1 , 
        \CAHBtoAPB3IOl[1]_net_1 , N_205, CAHBtoAPB3OOl_m4_0_m2_net_1, 
        N_204, N_203, N_202, N_201, N_200, N_199, N_198, 
        \CAHBtoAPB3OOl_5_i_m3[24]_net_1 , N_196, 
        \CAHBtoAPB3OOl_5_i_m3[26]_net_1 , 
        \CAHBtoAPB3OOl_5_i_m3[27]_net_1 , CAHBtoAPB3OOl_m1_e_1_1_net_1;
    
    CFG3 #( .INIT(8'hCA) )  \CAHBtoAPB3OOl_5_i_m3[4]  (.A(
        \CAHBtoAPB3IOl[4]_net_1 ), .B(N_188), .C(N_250), .Y(N_201));
    SLE \HRDATA[0]  (.D(CoreAPB3_0_APBmslave0_PRDATA_m[0]), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3II), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[0]));
    SLE \CAHBtoAPB3lOl[3]  (.D(FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[3])
        , .CLK(FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3OI), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CoreAPB3_0_APBmslave0_PWDATA[3]));
    SLE \HRDATA[3]  (.D(CoreAPB3_0_APBmslave0_PRDATA_m[3]), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3II), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[3]));
    CFG3 #( .INIT(8'hCA) )  \CAHBtoAPB3OOl_5_i_m3[0]  (.A(
        \CAHBtoAPB3IOl[0]_net_1 ), .B(N_192), .C(N_250), .Y(N_205));
    CFG2 #( .INIT(4'h7) )  CAHBtoAPB3OOl_m4_0_o4_0_inst_1 (.A(m19_e_0), 
        .B(FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .Y(
        CAHBtoAPB3OOl_m4_0_o4_0));
    VCC VCC (.Y(VCC_net_1));
    CFG3 #( .INIT(8'hCA) )  \CAHBtoAPB3OOl_5_i_m3[25]  (.A(
        \CAHBtoAPB3IOl[25]_net_1 ), .B(M0GATEDHADDR[25]), .C(N_250), 
        .Y(N_196));
    SLE \HRDATA[6]  (.D(CoreAPB3_0_APBmslave0_PRDATA_m[6]), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3II), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[6]));
    SLE \CAHBtoAPB3OOl[4]  (.D(N_201), .CLK(FlashFreeze_SB_0_FIC_0_CLK)
        , .EN(CAHBtoAPB3OOl_m4_0_m2_net_1), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CoreAPB3_0_APBmslave0_PADDR[4]));
    CFG4 #( .INIT(16'hCAAA) )  \CAHBtoAPB3OOl_5_i_m3[26]  (.A(
        \CAHBtoAPB3IOl[26]_net_1 ), .B(M0GATEDHADDR[26]), .C(
        CAHBtoAPB3OOl_m1_e_1_1_net_1), .D(masterAddrInProg_0), .Y(
        \CAHBtoAPB3OOl_5_i_m3[26]_net_1 ));
    SLE \CAHBtoAPB3IOl[1]  (.D(N_122_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3lI), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \CAHBtoAPB3IOl[1]_net_1 ));
    SLE \CAHBtoAPB3IOl[25]  (.D(N_128_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3lI), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \CAHBtoAPB3IOl[25]_net_1 ));
    SLE \CAHBtoAPB3OOl[25]  (.D(N_196), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3OOl_m4_0_m2_net_1), 
        .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        COREAHBTOAPB3_0_APBmaster_PADDR[25]));
    SLE \CAHBtoAPB3lOl[7]  (.D(FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[7])
        , .CLK(FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3OI), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CoreAPB3_0_APBmslave0_PWDATA[7]));
    CFG4 #( .INIT(16'hC5CC) )  CAHBtoAPB3OOl_m4_0_m2 (.A(N_54_0), .B(
        N_63_0), .C(CAHBtoAPB3OOl_m4_0_o4_0), .D(masterAddrInProg_0), 
        .Y(CAHBtoAPB3OOl_m4_0_m2_net_1));
    SLE \CAHBtoAPB3lOl[5]  (.D(FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[5])
        , .CLK(FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3OI), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CoreAPB3_0_APBmslave0_PWDATA[5]));
    CFG3 #( .INIT(8'hCA) )  \CAHBtoAPB3OOl_5_i_m3[1]  (.A(
        \CAHBtoAPB3IOl[1]_net_1 ), .B(N_191), .C(N_250), .Y(N_204));
    SLE \CAHBtoAPB3OOl[6]  (.D(N_199), .CLK(FlashFreeze_SB_0_FIC_0_CLK)
        , .EN(CAHBtoAPB3OOl_m4_0_m2_net_1), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CoreAPB3_0_APBmslave0_PADDR[6]));
    SLE \CAHBtoAPB3IOl[24]  (.D(N_126_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3lI), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \CAHBtoAPB3IOl[24]_net_1 ));
    SLE \CAHBtoAPB3OOl[24]  (.D(\CAHBtoAPB3OOl_5_i_m3[24]_net_1 ), 
        .CLK(FlashFreeze_SB_0_FIC_0_CLK), .EN(
        CAHBtoAPB3OOl_m4_0_m2_net_1), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        COREAHBTOAPB3_0_APBmaster_PADDR[24]));
    CFG3 #( .INIT(8'hCA) )  \CAHBtoAPB3OOl_5_i_m3[5]  (.A(
        \CAHBtoAPB3IOl[5]_net_1 ), .B(N_187), .C(N_250), .Y(N_200));
    CFG3 #( .INIT(8'hCA) )  \CAHBtoAPB3OOl_5_i_m3[7]  (.A(
        \CAHBtoAPB3IOl[7]_net_1 ), .B(N_185), .C(N_250), .Y(N_198));
    SLE \CAHBtoAPB3IOl[5]  (.D(N_61_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3lI), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \CAHBtoAPB3IOl[5]_net_1 ));
    SLE \HRDATA[7]  (.D(CoreAPB3_0_APBmslave0_PRDATA_m[7]), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3II), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[7]));
    SLE \CAHBtoAPB3OOl[2]  (.D(N_203), .CLK(FlashFreeze_SB_0_FIC_0_CLK)
        , .EN(CAHBtoAPB3OOl_m4_0_m2_net_1), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CoreAPB3_0_APBmslave0_PADDR[2]));
    GND GND (.Y(GND_net_1));
    SLE \CAHBtoAPB3IOl[4]  (.D(N_59_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3lI), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \CAHBtoAPB3IOl[4]_net_1 ));
    CFG4 #( .INIT(16'hCAAA) )  \CAHBtoAPB3OOl_5_i_m3[24]  (.A(
        \CAHBtoAPB3IOl[24]_net_1 ), .B(M0GATEDHADDR[24]), .C(
        CAHBtoAPB3OOl_m1_e_1_1_net_1), .D(masterAddrInProg_0), .Y(
        \CAHBtoAPB3OOl_5_i_m3[24]_net_1 ));
    SLE \CAHBtoAPB3lOl[0]  (.D(FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[0])
        , .CLK(FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3OI), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CoreAPB3_0_APBmslave0_PWDATA[0]));
    SLE \CAHBtoAPB3OOl[7]  (.D(N_198), .CLK(FlashFreeze_SB_0_FIC_0_CLK)
        , .EN(CAHBtoAPB3OOl_m4_0_m2_net_1), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CoreAPB3_0_APBmslave0_PADDR[7]));
    SLE \CAHBtoAPB3IOl[2]  (.D(N_55_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3lI), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \CAHBtoAPB3IOl[2]_net_1 ));
    SLE \CAHBtoAPB3lOl[6]  (.D(FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[6])
        , .CLK(FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3OI), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CoreAPB3_0_APBmslave0_PWDATA[6]));
    SLE \CAHBtoAPB3OOl[5]  (.D(N_200), .CLK(FlashFreeze_SB_0_FIC_0_CLK)
        , .EN(CAHBtoAPB3OOl_m4_0_m2_net_1), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CoreAPB3_0_APBmslave0_PADDR[5]));
    SLE \CAHBtoAPB3lOl[2]  (.D(FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[2])
        , .CLK(FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3OI), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CoreAPB3_0_APBmslave0_PWDATA[2]));
    SLE \HRDATA[4]  (.D(CoreAPB3_0_APBmslave0_PRDATA_m[4]), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3II), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[4]));
    SLE \CAHBtoAPB3IOl[27]  (.D(N_131_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3lI), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \CAHBtoAPB3IOl[27]_net_1 ));
    SLE \CAHBtoAPB3OOl[27]  (.D(\CAHBtoAPB3OOl_5_i_m3[27]_net_1 ), 
        .CLK(FlashFreeze_SB_0_FIC_0_CLK), .EN(
        CAHBtoAPB3OOl_m4_0_m2_net_1), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        COREAHBTOAPB3_0_APBmaster_PADDR[27]));
    SLE \CAHBtoAPB3OOl[1]  (.D(N_204), .CLK(FlashFreeze_SB_0_FIC_0_CLK)
        , .EN(CAHBtoAPB3OOl_m4_0_m2_net_1), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CoreAPB3_0_APBmslave0_PADDR[1]));
    CFG3 #( .INIT(8'hCA) )  \CAHBtoAPB3OOl_5_i_m3[6]  (.A(
        \CAHBtoAPB3IOl[6]_net_1 ), .B(N_186), .C(N_250), .Y(N_199));
    SLE \CAHBtoAPB3lOl[4]  (.D(FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[4])
        , .CLK(FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3OI), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CoreAPB3_0_APBmslave0_PWDATA[4]));
    SLE \HRDATA[2]  (.D(CoreAPB3_0_APBmslave0_PRDATA_m[2]), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3II), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[2]));
    SLE \CAHBtoAPB3IOl[0]  (.D(N_51_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3lI), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \CAHBtoAPB3IOl[0]_net_1 ));
    CFG3 #( .INIT(8'h40) )  CAHBtoAPB3OOl_m1_e_1_1 (.A(N_54_0), .B(
        m19_e_0), .C(FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .Y(
        CAHBtoAPB3OOl_m1_e_1_1_net_1));
    CFG3 #( .INIT(8'hCA) )  \CAHBtoAPB3OOl_5_i_m3[3]  (.A(
        \CAHBtoAPB3IOl[3]_net_1 ), .B(N_189), .C(N_250), .Y(N_202));
    SLE \HRDATA[1]  (.D(CoreAPB3_0_APBmslave0_PRDATA_m[1]), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3II), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[1]));
    SLE \CAHBtoAPB3lOl[1]  (.D(FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[1])
        , .CLK(FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3OI), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CoreAPB3_0_APBmslave0_PWDATA[1]));
    SLE \CAHBtoAPB3IOl[3]  (.D(N_57_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3lI), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \CAHBtoAPB3IOl[3]_net_1 ));
    CFG3 #( .INIT(8'hCA) )  \CAHBtoAPB3OOl_5_i_m3[2]  (.A(
        \CAHBtoAPB3IOl[2]_net_1 ), .B(N_190), .C(N_250), .Y(N_203));
    SLE \CAHBtoAPB3IOl[7]  (.D(N_125_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3lI), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \CAHBtoAPB3IOl[7]_net_1 ));
    SLE \CAHBtoAPB3IOl[26]  (.D(N_129_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3lI), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \CAHBtoAPB3IOl[26]_net_1 ));
    SLE \CAHBtoAPB3OOl[26]  (.D(\CAHBtoAPB3OOl_5_i_m3[26]_net_1 ), 
        .CLK(FlashFreeze_SB_0_FIC_0_CLK), .EN(
        CAHBtoAPB3OOl_m4_0_m2_net_1), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        COREAHBTOAPB3_0_APBmaster_PADDR[26]));
    SLE \CAHBtoAPB3OOl[0]  (.D(N_205), .CLK(FlashFreeze_SB_0_FIC_0_CLK)
        , .EN(CAHBtoAPB3OOl_m4_0_m2_net_1), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CoreAPB3_0_APBmslave0_PADDR[0]));
    SLE \CAHBtoAPB3IOl[6]  (.D(N_123_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3lI), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        \CAHBtoAPB3IOl[6]_net_1 ));
    SLE \CAHBtoAPB3OOl[3]  (.D(N_202), .CLK(FlashFreeze_SB_0_FIC_0_CLK)
        , .EN(CAHBtoAPB3OOl_m4_0_m2_net_1), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CoreAPB3_0_APBmslave0_PADDR[3]));
    SLE \HRDATA[5]  (.D(CoreAPB3_0_APBmslave0_PRDATA_m[5]), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3II), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[5]));
    CFG4 #( .INIT(16'hCAAA) )  \CAHBtoAPB3OOl_5_i_m3[27]  (.A(
        \CAHBtoAPB3IOl[27]_net_1 ), .B(M0GATEDHADDR[27]), .C(
        CAHBtoAPB3OOl_m1_e_1_1_net_1), .D(masterAddrInProg_0), .Y(
        \CAHBtoAPB3OOl_5_i_m3[27]_net_1 ));
    
endmodule


module CAHBtoAPB3O_0s_0_1_0_1_2_3_4(
       masterAddrInProg_0,
       CAHBtoAPB3IOI_0,
       CAHBtoAPB3IOI_3,
       CAHBtoAPB3IOI_4,
       CAHBtoAPB3OOl_m4_0_o4_0,
       N_153_mux,
       N_63_0,
       m19_e_0,
       N_54_0,
       N_151,
       CAHBtoAPB3ll4,
       CoreAPB3_0_APBmslave0_PREADY,
       CoreAPB3_0_APBmslave0_PSELx,
       PENABLE,
       N_247_mux,
       N_179_mux,
       N_56_0_i,
       CoreAPB3_0_APBmslave0_PWRITE,
       CAHBtoAPB3OI,
       N_177_mux_i,
       N_181_mux_i,
       FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY,
       N_178_mux,
       COREAHBTOAPB3_0_APBmaster_PSELx,
       CAHBtoAPB3lI,
       N_12_i,
       CAHBtoAPB3III,
       N_250,
       FlashFreeze_SB_0_FIC_0_CLK,
       FlashFreeze_SB_0_POWER_ON_RESET_N,
       CAHBtoAPB3lII
    );
input  masterAddrInProg_0;
output CAHBtoAPB3IOI_0;
output CAHBtoAPB3IOI_3;
output CAHBtoAPB3IOI_4;
input  CAHBtoAPB3OOl_m4_0_o4_0;
input  N_153_mux;
input  N_63_0;
input  m19_e_0;
input  N_54_0;
input  N_151;
output CAHBtoAPB3ll4;
input  CoreAPB3_0_APBmslave0_PREADY;
input  CoreAPB3_0_APBmslave0_PSELx;
input  PENABLE;
input  N_247_mux;
input  N_179_mux;
input  N_56_0_i;
output CoreAPB3_0_APBmslave0_PWRITE;
output CAHBtoAPB3OI;
input  N_177_mux_i;
input  N_181_mux_i;
output FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY;
input  N_178_mux;
output COREAHBTOAPB3_0_APBmaster_PSELx;
input  CAHBtoAPB3lI;
input  N_12_i;
output CAHBtoAPB3III;
output N_250;
input  FlashFreeze_SB_0_FIC_0_CLK;
input  FlashFreeze_SB_0_POWER_ON_RESET_N;
output CAHBtoAPB3lII;

    wire VCC_net_1, CAHBtoAPB3lII_RNO_net_1, GND_net_1, 
        \CAHBtoAPB3IOI_ns[1] , CAHBtoAPB3IOI_m2_e_0_net_1;
    
    SLE PSEL (.D(N_178_mux), .CLK(FlashFreeze_SB_0_FIC_0_CLK), .EN(
        VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(COREAHBTOAPB3_0_APBmaster_PSELx));
    CFG2 #( .INIT(4'h1) )  CAHBtoAPB3IOI_m2_e_0 (.A(N_151), .B(N_54_0), 
        .Y(CAHBtoAPB3IOI_m2_e_0_net_1));
    SLE \CAHBtoAPB3IOI[2]  (.D(N_56_0_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CoreAPB3_0_APBmslave0_PWRITE));
    SLE \CAHBtoAPB3IOI[0]  (.D(N_177_mux_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(GND_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CAHBtoAPB3IOI_0));
    GND GND (.Y(GND_net_1));
    CFG3 #( .INIT(8'h80) )  CAHBtoAPB3IOI_m2_e (.A(masterAddrInProg_0), 
        .B(FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .C(m19_e_0), .Y(
        N_250));
    SLE \CAHBtoAPB3IOI[3]  (.D(N_179_mux), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CAHBtoAPB3IOI_3));
    SLE CAHBtoAPB3III_inst_1 (.D(N_12_i), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3lI), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(CAHBtoAPB3III));
    VCC VCC (.Y(VCC_net_1));
    SLE HREADYOUT (.D(N_181_mux_i), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        GND_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY));
    CFG4 #( .INIT(16'hF088) )  CAHBtoAPB3IOI_m6_0_m2 (.A(CAHBtoAPB3III)
        , .B(N_63_0), .C(CAHBtoAPB3IOI_m2_e_0_net_1), .D(N_250), .Y(
        \CAHBtoAPB3IOI_ns[1] ));
    SLE \CAHBtoAPB3IOI[4]  (.D(N_247_mux), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(
        CAHBtoAPB3IOI_4));
    CFG4 #( .INIT(16'hA3AA) )  CAHBtoAPB3lII_RNO (.A(N_63_0), .B(
        N_153_mux), .C(CAHBtoAPB3OOl_m4_0_o4_0), .D(masterAddrInProg_0)
        , .Y(CAHBtoAPB3lII_RNO_net_1));
    CFG3 #( .INIT(8'hA2) )  CAHBtoAPB3ll4_inst_1 (.A(PENABLE), .B(
        CoreAPB3_0_APBmslave0_PSELx), .C(CoreAPB3_0_APBmslave0_PREADY), 
        .Y(CAHBtoAPB3ll4));
    SLE CAHBtoAPB3lII_inst_1 (.D(N_250), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(CAHBtoAPB3lII_RNO_net_1), 
        .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(CAHBtoAPB3lII));
    SLE \CAHBtoAPB3IOI[1]  (.D(\CAHBtoAPB3IOI_ns[1] ), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(CAHBtoAPB3OI));
    
endmodule


module COREAHBTOAPB3_19s_0s(
       CoreAPB3_0_APBmslave0_PWDATA,
       FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA,
       CoreAPB3_0_APBmslave0_PADDR,
       COREAHBTOAPB3_0_APBmaster_PADDR,
       FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA,
       CoreAPB3_0_APBmslave0_PRDATA_m,
       M0GATEDHADDR,
       CAHBtoAPB3IOI_0,
       CAHBtoAPB3IOI_3,
       CAHBtoAPB3IOI_4,
       masterAddrInProg_0,
       N_55_i,
       N_57_i,
       N_59_i,
       N_61_i,
       N_123_i,
       N_125_i,
       N_126_i,
       N_128_i,
       N_129_i,
       N_131_i,
       CAHBtoAPB3II,
       N_51_i,
       N_122_i,
       N_185,
       N_186,
       N_187,
       N_188,
       N_189,
       N_190,
       N_191,
       N_192,
       N_171_mux,
       N_25_0,
       CAHBtoAPB3lII,
       FlashFreeze_SB_0_POWER_ON_RESET_N,
       FlashFreeze_SB_0_FIC_0_CLK,
       N_250,
       CAHBtoAPB3III,
       N_12_i,
       CAHBtoAPB3lI,
       COREAHBTOAPB3_0_APBmaster_PSELx,
       N_178_mux,
       FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY,
       N_181_mux_i,
       N_177_mux_i,
       CAHBtoAPB3OI,
       CoreAPB3_0_APBmslave0_PWRITE,
       N_56_0_i,
       N_179_mux,
       N_247_mux,
       PENABLE,
       CoreAPB3_0_APBmslave0_PSELx,
       CoreAPB3_0_APBmslave0_PREADY,
       CAHBtoAPB3ll4,
       N_151,
       N_54_0,
       m19_e_0,
       N_63_0,
       N_153_mux
    );
output [7:0] CoreAPB3_0_APBmslave0_PWDATA;
input  [7:0] FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA;
output [7:0] CoreAPB3_0_APBmslave0_PADDR;
output [27:24] COREAHBTOAPB3_0_APBmaster_PADDR;
output [7:0] FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA;
input  [7:0] CoreAPB3_0_APBmslave0_PRDATA_m;
input  [27:24] M0GATEDHADDR;
output CAHBtoAPB3IOI_0;
output CAHBtoAPB3IOI_3;
output CAHBtoAPB3IOI_4;
input  masterAddrInProg_0;
input  N_55_i;
input  N_57_i;
input  N_59_i;
input  N_61_i;
input  N_123_i;
input  N_125_i;
input  N_126_i;
input  N_128_i;
input  N_129_i;
input  N_131_i;
input  CAHBtoAPB3II;
input  N_51_i;
input  N_122_i;
input  N_185;
input  N_186;
input  N_187;
input  N_188;
input  N_189;
input  N_190;
input  N_191;
input  N_192;
input  N_171_mux;
input  N_25_0;
output CAHBtoAPB3lII;
input  FlashFreeze_SB_0_POWER_ON_RESET_N;
input  FlashFreeze_SB_0_FIC_0_CLK;
output N_250;
output CAHBtoAPB3III;
input  N_12_i;
input  CAHBtoAPB3lI;
output COREAHBTOAPB3_0_APBmaster_PSELx;
input  N_178_mux;
output FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY;
input  N_181_mux_i;
input  N_177_mux_i;
output CAHBtoAPB3OI;
output CoreAPB3_0_APBmslave0_PWRITE;
input  N_56_0_i;
input  N_179_mux;
input  N_247_mux;
output PENABLE;
input  CoreAPB3_0_APBmslave0_PSELx;
input  CoreAPB3_0_APBmslave0_PREADY;
output CAHBtoAPB3ll4;
input  N_151;
input  N_54_0;
input  m19_e_0;
input  N_63_0;
input  N_153_mux;

    wire CAHBtoAPB3OOl_m4_0_o4_0, GND_net_1, VCC_net_1;
    
    CAHBtoAPB3OIl_0s_0_1_2 CAHBtoAPB3O0l (.N_25_0(N_25_0), .N_171_mux(
        N_171_mux), .PENABLE(PENABLE), .FlashFreeze_SB_0_FIC_0_CLK(
        FlashFreeze_SB_0_FIC_0_CLK), 
        .FlashFreeze_SB_0_POWER_ON_RESET_N(
        FlashFreeze_SB_0_POWER_ON_RESET_N));
    VCC VCC (.Y(VCC_net_1));
    CAHBtoAPB3l1I_0s CAHBtoAPB3I0l (.M0GATEDHADDR({M0GATEDHADDR[27], 
        M0GATEDHADDR[26], M0GATEDHADDR[25], M0GATEDHADDR[24]}), 
        .CoreAPB3_0_APBmslave0_PRDATA_m({
        CoreAPB3_0_APBmslave0_PRDATA_m[7], 
        CoreAPB3_0_APBmslave0_PRDATA_m[6], 
        CoreAPB3_0_APBmslave0_PRDATA_m[5], 
        CoreAPB3_0_APBmslave0_PRDATA_m[4], 
        CoreAPB3_0_APBmslave0_PRDATA_m[3], 
        CoreAPB3_0_APBmslave0_PRDATA_m[2], 
        CoreAPB3_0_APBmslave0_PRDATA_m[1], 
        CoreAPB3_0_APBmslave0_PRDATA_m[0]}), 
        .FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA({
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[7], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[6], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[5], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[4], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[3], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[2], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[1], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[0]}), 
        .COREAHBTOAPB3_0_APBmaster_PADDR({
        COREAHBTOAPB3_0_APBmaster_PADDR[27], 
        COREAHBTOAPB3_0_APBmaster_PADDR[26], 
        COREAHBTOAPB3_0_APBmaster_PADDR[25], 
        COREAHBTOAPB3_0_APBmaster_PADDR[24]}), 
        .CoreAPB3_0_APBmslave0_PADDR({CoreAPB3_0_APBmslave0_PADDR[7], 
        CoreAPB3_0_APBmslave0_PADDR[6], CoreAPB3_0_APBmslave0_PADDR[5], 
        CoreAPB3_0_APBmslave0_PADDR[4], CoreAPB3_0_APBmslave0_PADDR[3], 
        CoreAPB3_0_APBmslave0_PADDR[2], CoreAPB3_0_APBmslave0_PADDR[1], 
        CoreAPB3_0_APBmslave0_PADDR[0]}), 
        .FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA({
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[7], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[6], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[5], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[4], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[3], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[2], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[1], 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[0]}), 
        .CoreAPB3_0_APBmslave0_PWDATA({CoreAPB3_0_APBmslave0_PWDATA[7], 
        CoreAPB3_0_APBmslave0_PWDATA[6], 
        CoreAPB3_0_APBmslave0_PWDATA[5], 
        CoreAPB3_0_APBmslave0_PWDATA[4], 
        CoreAPB3_0_APBmslave0_PWDATA[3], 
        CoreAPB3_0_APBmslave0_PWDATA[2], 
        CoreAPB3_0_APBmslave0_PWDATA[1], 
        CoreAPB3_0_APBmslave0_PWDATA[0]}), .masterAddrInProg_0(
        masterAddrInProg_0), .N_192(N_192), .N_191(N_191), .N_190(
        N_190), .N_189(N_189), .N_188(N_188), .N_187(N_187), .N_186(
        N_186), .N_185(N_185), .N_250(N_250), .N_63_0(N_63_0), .N_54_0(
        N_54_0), .CAHBtoAPB3OOl_m4_0_o4_0(CAHBtoAPB3OOl_m4_0_o4_0), 
        .FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .m19_e_0(m19_e_0), 
        .N_122_i(N_122_i), .N_51_i(N_51_i), .CAHBtoAPB3OI(CAHBtoAPB3OI)
        , .CAHBtoAPB3II(CAHBtoAPB3II), .N_131_i(N_131_i), .N_129_i(
        N_129_i), .N_128_i(N_128_i), .N_126_i(N_126_i), .N_125_i(
        N_125_i), .N_123_i(N_123_i), .N_61_i(N_61_i), .N_59_i(N_59_i), 
        .N_57_i(N_57_i), .CAHBtoAPB3lI(CAHBtoAPB3lI), .N_55_i(N_55_i), 
        .FlashFreeze_SB_0_FIC_0_CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .FlashFreeze_SB_0_POWER_ON_RESET_N(
        FlashFreeze_SB_0_POWER_ON_RESET_N));
    GND GND (.Y(GND_net_1));
    CAHBtoAPB3O_0s_0_1_0_1_2_3_4 CAHBtoAPB3lll (.masterAddrInProg_0(
        masterAddrInProg_0), .CAHBtoAPB3IOI_0(CAHBtoAPB3IOI_0), 
        .CAHBtoAPB3IOI_3(CAHBtoAPB3IOI_3), .CAHBtoAPB3IOI_4(
        CAHBtoAPB3IOI_4), .CAHBtoAPB3OOl_m4_0_o4_0(
        CAHBtoAPB3OOl_m4_0_o4_0), .N_153_mux(N_153_mux), .N_63_0(
        N_63_0), .m19_e_0(m19_e_0), .N_54_0(N_54_0), .N_151(N_151), 
        .CAHBtoAPB3ll4(CAHBtoAPB3ll4), .CoreAPB3_0_APBmslave0_PREADY(
        CoreAPB3_0_APBmslave0_PREADY), .CoreAPB3_0_APBmslave0_PSELx(
        CoreAPB3_0_APBmslave0_PSELx), .PENABLE(PENABLE), .N_247_mux(
        N_247_mux), .N_179_mux(N_179_mux), .N_56_0_i(N_56_0_i), 
        .CoreAPB3_0_APBmslave0_PWRITE(CoreAPB3_0_APBmslave0_PWRITE), 
        .CAHBtoAPB3OI(CAHBtoAPB3OI), .N_177_mux_i(N_177_mux_i), 
        .N_181_mux_i(N_181_mux_i), 
        .FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .N_178_mux(N_178_mux), 
        .COREAHBTOAPB3_0_APBmaster_PSELx(
        COREAHBTOAPB3_0_APBmaster_PSELx), .CAHBtoAPB3lI(CAHBtoAPB3lI), 
        .N_12_i(N_12_i), .CAHBtoAPB3III(CAHBtoAPB3III), .N_250(N_250), 
        .FlashFreeze_SB_0_FIC_0_CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .FlashFreeze_SB_0_POWER_ON_RESET_N(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .CAHBtoAPB3lII(
        CAHBtoAPB3lII));
    
endmodule


module cnt34(
       LED_4_c,
       LED_3_c,
       LED_2_c,
       LED_1_c,
       FlashFreeze_SB_0_FIC_0_CLK,
       FlashFreeze_SB_0_POWER_ON_RESET_N
    );
output LED_4_c;
output LED_3_c;
output LED_2_c;
output LED_1_c;
input  FlashFreeze_SB_0_FIC_0_CLK;
input  FlashFreeze_SB_0_POWER_ON_RESET_N;

    wire \CNT[0]_net_1 , \CNT_s[0] , VCC_net_1, GND_net_1, 
        \CNT[1]_net_1 , \CNT_s[1] , \CNT[2]_net_1 , \CNT_s[2] , 
        \CNT[3]_net_1 , \CNT_s[3] , \CNT[4]_net_1 , \CNT_s[4] , 
        \CNT[5]_net_1 , \CNT_s[5] , \CNT[6]_net_1 , \CNT_s[6] , 
        \CNT[7]_net_1 , \CNT_s[7] , \CNT[8]_net_1 , \CNT_s[8] , 
        \CNT[9]_net_1 , \CNT_s[9] , \CNT[10]_net_1 , \CNT_s[10] , 
        \CNT[11]_net_1 , \CNT_s[11] , \CNT[12]_net_1 , \CNT_s[12] , 
        \CNT[13]_net_1 , \CNT_s[13] , \CNT[14]_net_1 , \CNT_s[14] , 
        \CNT[15]_net_1 , \CNT_s[15] , \CNT[16]_net_1 , \CNT_s[16] , 
        \CNT[17]_net_1 , \CNT_s[17] , \CNT[18]_net_1 , \CNT_s[18] , 
        \CNT[19]_net_1 , \CNT_s[19] , \CNT[20]_net_1 , \CNT_s[20] , 
        \CNT[21]_net_1 , \CNT_s[21] , \CNT[22]_net_1 , \CNT_s[22] , 
        \CNT_s[23] , \CNT_s[24] , \CNT_s[25] , \CNT_s[26]_net_1 , 
        CNT_s_197_FCO, \CNT_cry[1]_net_1 , \CNT_cry[2]_net_1 , 
        \CNT_cry[3]_net_1 , \CNT_cry[4]_net_1 , \CNT_cry[5]_net_1 , 
        \CNT_cry[6]_net_1 , \CNT_cry[7]_net_1 , \CNT_cry[8]_net_1 , 
        \CNT_cry[9]_net_1 , \CNT_cry[10]_net_1 , \CNT_cry[11]_net_1 , 
        \CNT_cry[12]_net_1 , \CNT_cry[13]_net_1 , \CNT_cry[14]_net_1 , 
        \CNT_cry[15]_net_1 , \CNT_cry[16]_net_1 , \CNT_cry[17]_net_1 , 
        \CNT_cry[18]_net_1 , \CNT_cry[19]_net_1 , \CNT_cry[20]_net_1 , 
        \CNT_cry[21]_net_1 , \CNT_cry[22]_net_1 , \CNT_cry[23]_net_1 , 
        \CNT_cry[24]_net_1 , \CNT_cry[25]_net_1 ;
    
    SLE \CNT[19]  (.D(\CNT_s[19] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\CNT[19]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  CNT_s_197 (.A(VCC_net_1), .B(
        \CNT[0]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(VCC_net_1), 
        .S(), .Y(), .FCO(CNT_s_197_FCO));
    ARI1 #( .INIT(20'h4AA00) )  \CNT_cry[16]  (.A(VCC_net_1), .B(
        \CNT[16]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \CNT_cry[15]_net_1 ), .S(\CNT_s[16] ), .Y(), .FCO(
        \CNT_cry[16]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \CNT_cry[4]  (.A(VCC_net_1), .B(
        \CNT[4]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \CNT_cry[3]_net_1 ), .S(\CNT_s[4] ), .Y(), .FCO(
        \CNT_cry[4]_net_1 ));
    SLE \CNT[2]  (.D(\CNT_s[2] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\CNT[2]_net_1 ));
    SLE \CNT[8]  (.D(\CNT_s[8] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\CNT[8]_net_1 ));
    SLE \CNT[26]  (.D(\CNT_s[26]_net_1 ), .CLK(
        FlashFreeze_SB_0_FIC_0_CLK), .EN(VCC_net_1), .ALn(
        FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(VCC_net_1), .SLn(
        VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), .Q(LED_4_c));
    SLE \CNT[1]  (.D(\CNT_s[1] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\CNT[1]_net_1 ));
    SLE \CNT[11]  (.D(\CNT_s[11] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\CNT[11]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \CNT_cry[6]  (.A(VCC_net_1), .B(
        \CNT[6]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \CNT_cry[5]_net_1 ), .S(\CNT_s[6] ), .Y(), .FCO(
        \CNT_cry[6]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \CNT_cry[9]  (.A(VCC_net_1), .B(
        \CNT[9]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \CNT_cry[8]_net_1 ), .S(\CNT_s[9] ), .Y(), .FCO(
        \CNT_cry[9]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \CNT_cry[2]  (.A(VCC_net_1), .B(
        \CNT[2]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \CNT_cry[1]_net_1 ), .S(\CNT_s[2] ), .Y(), .FCO(
        \CNT_cry[2]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \CNT_cry[19]  (.A(VCC_net_1), .B(
        \CNT[19]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \CNT_cry[18]_net_1 ), .S(\CNT_s[19] ), .Y(), .FCO(
        \CNT_cry[19]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \CNT_cry[18]  (.A(VCC_net_1), .B(
        \CNT[18]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \CNT_cry[17]_net_1 ), .S(\CNT_s[18] ), .Y(), .FCO(
        \CNT_cry[18]_net_1 ));
    SLE \CNT[17]  (.D(\CNT_s[17] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\CNT[17]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \CNT_cry[11]  (.A(VCC_net_1), .B(
        \CNT[11]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \CNT_cry[10]_net_1 ), .S(\CNT_s[11] ), .Y(), .FCO(
        \CNT_cry[11]_net_1 ));
    SLE \CNT[16]  (.D(\CNT_s[16] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\CNT[16]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \CNT_cry[15]  (.A(VCC_net_1), .B(
        \CNT[15]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \CNT_cry[14]_net_1 ), .S(\CNT_s[15] ), .Y(), .FCO(
        \CNT_cry[15]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \CNT_cry[21]  (.A(VCC_net_1), .B(
        \CNT[21]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \CNT_cry[20]_net_1 ), .S(\CNT_s[21] ), .Y(), .FCO(
        \CNT_cry[21]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \CNT_cry[10]  (.A(VCC_net_1), .B(
        \CNT[10]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \CNT_cry[9]_net_1 ), .S(\CNT_s[10] ), .Y(), .FCO(
        \CNT_cry[10]_net_1 ));
    VCC VCC (.Y(VCC_net_1));
    ARI1 #( .INIT(20'h4AA00) )  \CNT_cry[25]  (.A(VCC_net_1), .B(
        LED_3_c), .C(GND_net_1), .D(GND_net_1), .FCI(
        \CNT_cry[24]_net_1 ), .S(\CNT_s[25] ), .Y(), .FCO(
        \CNT_cry[25]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \CNT_cry[20]  (.A(VCC_net_1), .B(
        \CNT[20]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \CNT_cry[19]_net_1 ), .S(\CNT_s[20] ), .Y(), .FCO(
        \CNT_cry[20]_net_1 ));
    SLE \CNT[6]  (.D(\CNT_s[6] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\CNT[6]_net_1 ));
    SLE \CNT[4]  (.D(\CNT_s[4] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\CNT[4]_net_1 ));
    SLE \CNT[9]  (.D(\CNT_s[9] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\CNT[9]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \CNT_s[26]  (.A(VCC_net_1), .B(LED_4_c)
        , .C(GND_net_1), .D(GND_net_1), .FCI(\CNT_cry[25]_net_1 ), .S(
        \CNT_s[26]_net_1 ), .Y(), .FCO());
    CFG1 #( .INIT(2'h1) )  \CNT_RNO[0]  (.A(\CNT[0]_net_1 ), .Y(
        \CNT_s[0] ));
    ARI1 #( .INIT(20'h4AA00) )  \CNT_cry[3]  (.A(VCC_net_1), .B(
        \CNT[3]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \CNT_cry[2]_net_1 ), .S(\CNT_s[3] ), .Y(), .FCO(
        \CNT_cry[3]_net_1 ));
    SLE \CNT[0]  (.D(\CNT_s[0] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\CNT[0]_net_1 ));
    GND GND (.Y(GND_net_1));
    ARI1 #( .INIT(20'h4AA00) )  \CNT_cry[13]  (.A(VCC_net_1), .B(
        \CNT[13]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \CNT_cry[12]_net_1 ), .S(\CNT_s[13] ), .Y(), .FCO(
        \CNT_cry[13]_net_1 ));
    SLE \CNT[23]  (.D(\CNT_s[23] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(LED_1_c));
    ARI1 #( .INIT(20'h4AA00) )  \CNT_cry[23]  (.A(VCC_net_1), .B(
        LED_1_c), .C(GND_net_1), .D(GND_net_1), .FCI(
        \CNT_cry[22]_net_1 ), .S(\CNT_s[23] ), .Y(), .FCO(
        \CNT_cry[23]_net_1 ));
    SLE \CNT[20]  (.D(\CNT_s[20] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\CNT[20]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \CNT_cry[8]  (.A(VCC_net_1), .B(
        \CNT[8]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \CNT_cry[7]_net_1 ), .S(\CNT_s[8] ), .Y(), .FCO(
        \CNT_cry[8]_net_1 ));
    SLE \CNT[13]  (.D(\CNT_s[13] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\CNT[13]_net_1 ));
    SLE \CNT[18]  (.D(\CNT_s[18] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\CNT[18]_net_1 ));
    SLE \CNT[7]  (.D(\CNT_s[7] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\CNT[7]_net_1 ));
    SLE \CNT[10]  (.D(\CNT_s[10] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\CNT[10]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \CNT_cry[14]  (.A(VCC_net_1), .B(
        \CNT[14]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \CNT_cry[13]_net_1 ), .S(\CNT_s[14] ), .Y(), .FCO(
        \CNT_cry[14]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \CNT_cry[24]  (.A(VCC_net_1), .B(
        LED_2_c), .C(GND_net_1), .D(GND_net_1), .FCI(
        \CNT_cry[23]_net_1 ), .S(\CNT_s[24] ), .Y(), .FCO(
        \CNT_cry[24]_net_1 ));
    SLE \CNT[3]  (.D(\CNT_s[3] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\CNT[3]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \CNT_cry[17]  (.A(VCC_net_1), .B(
        \CNT[17]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \CNT_cry[16]_net_1 ), .S(\CNT_s[17] ), .Y(), .FCO(
        \CNT_cry[17]_net_1 ));
    SLE \CNT[25]  (.D(\CNT_s[25] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(LED_3_c));
    ARI1 #( .INIT(20'h4AA00) )  \CNT_cry[5]  (.A(VCC_net_1), .B(
        \CNT[5]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \CNT_cry[4]_net_1 ), .S(\CNT_s[5] ), .Y(), .FCO(
        \CNT_cry[5]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \CNT_cry[12]  (.A(VCC_net_1), .B(
        \CNT[12]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \CNT_cry[11]_net_1 ), .S(\CNT_s[12] ), .Y(), .FCO(
        \CNT_cry[12]_net_1 ));
    SLE \CNT[22]  (.D(\CNT_s[22] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\CNT[22]_net_1 ));
    SLE \CNT[15]  (.D(\CNT_s[15] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\CNT[15]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \CNT_cry[22]  (.A(VCC_net_1), .B(
        \CNT[22]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \CNT_cry[21]_net_1 ), .S(\CNT_s[22] ), .Y(), .FCO(
        \CNT_cry[22]_net_1 ));
    SLE \CNT[24]  (.D(\CNT_s[24] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(LED_2_c));
    SLE \CNT[5]  (.D(\CNT_s[5] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\CNT[5]_net_1 ));
    SLE \CNT[12]  (.D(\CNT_s[12] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\CNT[12]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \CNT_cry[1]  (.A(VCC_net_1), .B(
        \CNT[1]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        CNT_s_197_FCO), .S(\CNT_s[1] ), .Y(), .FCO(\CNT_cry[1]_net_1 ));
    SLE \CNT[14]  (.D(\CNT_s[14] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\CNT[14]_net_1 ));
    ARI1 #( .INIT(20'h4AA00) )  \CNT_cry[7]  (.A(VCC_net_1), .B(
        \CNT[7]_net_1 ), .C(GND_net_1), .D(GND_net_1), .FCI(
        \CNT_cry[6]_net_1 ), .S(\CNT_s[7] ), .Y(), .FCO(
        \CNT_cry[7]_net_1 ));
    SLE \CNT[21]  (.D(\CNT_s[21] ), .CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .EN(VCC_net_1), .ALn(FlashFreeze_SB_0_POWER_ON_RESET_N), .ADn(
        VCC_net_1), .SLn(VCC_net_1), .SD(GND_net_1), .LAT(GND_net_1), 
        .Q(\CNT[21]_net_1 ));
    
endmodule


module FlashFreeze_SB_top(
       raddr_user,
       waddr_user,
       wdata_user,
       rdata_user,
       DEVRST_N,
       DIP1_L19_On_0,
       DIP2_L18_On_0,
       DIP3_K21_On_1,
       DIP4_K20_On_1,
       MMUART_1_RXD_0,
       SW1_L20_On_Change,
       rclk_user,
       rd_enable_user,
       wclk_user,
       wr_enable_user,
       DIP1_output,
       DIP2_output,
       DIP3_output,
       DIP4_output,
       FIC_0_LOCK,
       LED8,
       LED_1,
       LED_2,
       LED_3,
       LED_4,
       MMUART_1_TXD,
       SEL,
       SW1_output
    );
input  [5:0] raddr_user;
input  [5:0] waddr_user;
input  [7:0] wdata_user;
output [7:0] rdata_user;
input  DEVRST_N;
input  DIP1_L19_On_0;
input  DIP2_L18_On_0;
input  DIP3_K21_On_1;
input  DIP4_K20_On_1;
input  MMUART_1_RXD_0;
input  SW1_L20_On_Change;
input  rclk_user;
input  rd_enable_user;
input  wclk_user;
input  wr_enable_user;
output DIP1_output;
output DIP2_output;
output DIP3_output;
output DIP4_output;
output FIC_0_LOCK;
output LED8;
output LED_1;
output LED_2;
output LED_3;
output LED_4;
output MMUART_1_TXD;
output SEL;
output SW1_output;

    wire FlashFreeze_SB_0_POWER_ON_RESET_N, FlashFreeze_SB_0_FIC_0_CLK, 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[0] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[1] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[2] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[3] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[4] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[5] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[6] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[7] , 
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY, 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[0] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[1] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[2] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[3] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[4] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[5] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[6] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[7] , 
        \CoreAPB3_0_APBmslave0_PADDR[0] , 
        \CoreAPB3_0_APBmslave0_PADDR[1] , 
        \CoreAPB3_0_APBmslave0_PADDR[2] , 
        \CoreAPB3_0_APBmslave0_PADDR[3] , 
        \CoreAPB3_0_APBmslave0_PADDR[4] , 
        \CoreAPB3_0_APBmslave0_PADDR[5] , 
        \CoreAPB3_0_APBmslave0_PADDR[6] , 
        \CoreAPB3_0_APBmslave0_PADDR[7] , 
        \COREAHBTOAPB3_0_APBmaster_PADDR[24] , 
        \COREAHBTOAPB3_0_APBmaster_PADDR[25] , 
        \COREAHBTOAPB3_0_APBmaster_PADDR[26] , 
        \COREAHBTOAPB3_0_APBmaster_PADDR[27] , 
        CoreAPB3_0_APBmslave0_PWRITE, 
        \CoreAPB3_0_APBmslave0_PWDATA[0] , 
        \CoreAPB3_0_APBmslave0_PWDATA[1] , 
        \CoreAPB3_0_APBmslave0_PWDATA[2] , 
        \CoreAPB3_0_APBmslave0_PWDATA[3] , 
        \CoreAPB3_0_APBmslave0_PWDATA[4] , 
        \CoreAPB3_0_APBmslave0_PWDATA[5] , 
        \CoreAPB3_0_APBmslave0_PWDATA[6] , 
        \CoreAPB3_0_APBmslave0_PWDATA[7] , 
        COREAHBTOAPB3_0_APBmaster_PSELx, GND_net_1, 
        CoreAPB3_0_APBmslave0_PREADY, FLASH_FREEZE_0_FF_DONE, 
        VCC_net_1, SEL_c, \CoreAPB3_0_APBmslave0_PRDATA_m[0] , 
        \CoreAPB3_0_APBmslave0_PRDATA_m[1] , 
        \CoreAPB3_0_APBmslave0_PRDATA_m[2] , 
        \CoreAPB3_0_APBmslave0_PRDATA_m[3] , 
        \CoreAPB3_0_APBmslave0_PRDATA_m[4] , 
        \CoreAPB3_0_APBmslave0_PRDATA_m[5] , 
        \CoreAPB3_0_APBmslave0_PRDATA_m[6] , 
        \CoreAPB3_0_APBmslave0_PRDATA_m[7] , 
        \FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.M0GATEDHADDR[24] , 
        \FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.M0GATEDHADDR[25] , 
        \FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.M0GATEDHADDR[26] , 
        \FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.M0GATEDHADDR[27] , 
        \COREAHBTOAPB3_0.PENABLE , \COREAHBTOAPB3_0.CAHBtoAPB3OI , 
        \COREAHBTOAPB3_0.CAHBtoAPB3II , \COREAHBTOAPB3_0.CAHBtoAPB3lI , 
        \COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3III , 
        \COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3lII , 
        \COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3IOI[3] , 
        \COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3IOI[0] , 
        \COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3IOI[4] , N_247_mux, 
        N_179_mux, N_25_0, N_171_mux, N_178_mux, 
        CoreAPB3_0_APBmslave0_PSELx, DIP1_output_c, DIP2_output_c, 
        DIP3_output_c, DIP4_output_c, SW1_output_c, \raddr_user_c[0] , 
        \raddr_user_c[1] , \raddr_user_c[2] , \raddr_user_c[3] , 
        \raddr_user_c[4] , \raddr_user_c[5] , rclk_user_c, 
        rd_enable_user_c, \waddr_user_c[0] , \waddr_user_c[1] , 
        \waddr_user_c[2] , \waddr_user_c[3] , \waddr_user_c[4] , 
        \waddr_user_c[5] , wclk_user_c, \wdata_user_c[0] , 
        \wdata_user_c[1] , \wdata_user_c[2] , \wdata_user_c[3] , 
        \wdata_user_c[4] , \wdata_user_c[5] , \wdata_user_c[6] , 
        \wdata_user_c[7] , wr_enable_user_c, FIC_0_LOCK_c, 
        \rdata_user_c[0] , \rdata_user_c[1] , \rdata_user_c[2] , 
        \rdata_user_c[3] , \rdata_user_c[4] , \rdata_user_c[5] , 
        \rdata_user_c[6] , \rdata_user_c[7] , N_192, N_191, N_190, 
        N_189, N_188, N_187, N_186, N_185, N_54_0, N_151, N_63_0, 
        N_153_mux, \COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3ll4 , 
        \FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_0.m19_e_0 , 
        N_250, LED_1_c, LED_2_c, LED_3_c, LED_4_c, 
        \FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_0.masterAddrInProg[0] , 
        N_122_i, N_51_i, N_131_i, N_129_i, N_128_i, N_126_i, N_125_i, 
        N_123_i, N_61_i, N_59_i, N_57_i, N_55_i, N_56_0_i, N_177_mux_i, 
        N_181_mux_i, N_12_i;
    
    INBUF \wdata_user_ibuf[6]  (.PAD(wdata_user[6]), .Y(
        \wdata_user_c[6] ));
    OUTBUF \rdata_user_obuf[6]  (.D(\rdata_user_c[6] ), .PAD(
        rdata_user[6]));
    OUTBUF \rdata_user_obuf[0]  (.D(\rdata_user_c[0] ), .PAD(
        rdata_user[0]));
    OUTBUF DIP2_output_obuf (.D(DIP2_output_c), .PAD(DIP2_output));
    INBUF \wdata_user_ibuf[2]  (.PAD(wdata_user[2]), .Y(
        \wdata_user_c[2] ));
    OUTBUF SW1_output_obuf (.D(SW1_output_c), .PAD(SW1_output));
    OUTBUF \rdata_user_obuf[4]  (.D(\rdata_user_c[4] ), .PAD(
        rdata_user[4]));
    INBUF SW1_L20_On_Change_ibuf (.PAD(SW1_L20_On_Change), .Y(
        SW1_output_c));
    OUTBUF \rdata_user_obuf[5]  (.D(\rdata_user_c[5] ), .PAD(
        rdata_user[5]));
    INBUF rd_enable_user_ibuf (.PAD(rd_enable_user), .Y(
        rd_enable_user_c));
    FLASH_FREEZE FLASH_FREEZE_0 (.FF_TO_START(), .FF_DONE(
        FLASH_FREEZE_0_FF_DONE));
    INBUF \raddr_user_ibuf[5]  (.PAD(raddr_user[5]), .Y(
        \raddr_user_c[5] ));
    INBUF \raddr_user_ibuf[4]  (.PAD(raddr_user[4]), .Y(
        \raddr_user_c[4] ));
    CoreAPB3_Z1 CoreAPB3_0 (.COREAHBTOAPB3_0_APBmaster_PADDR({
        \COREAHBTOAPB3_0_APBmaster_PADDR[27] , 
        \COREAHBTOAPB3_0_APBmaster_PADDR[26] , 
        \COREAHBTOAPB3_0_APBmaster_PADDR[25] , 
        \COREAHBTOAPB3_0_APBmaster_PADDR[24] }), 
        .CoreAPB3_0_APBmslave0_PSELx(CoreAPB3_0_APBmslave0_PSELx), 
        .COREAHBTOAPB3_0_APBmaster_PSELx(
        COREAHBTOAPB3_0_APBmaster_PSELx));
    INBUF \wdata_user_ibuf[3]  (.PAD(wdata_user[3]), .Y(
        \wdata_user_c[3] ));
    VCC VCC (.Y(VCC_net_1));
    INBUF \raddr_user_ibuf[0]  (.PAD(raddr_user[0]), .Y(
        \raddr_user_c[0] ));
    OUTBUF DIP1_output_obuf (.D(DIP1_output_c), .PAD(DIP1_output));
    INBUF \waddr_user_ibuf[0]  (.PAD(waddr_user[0]), .Y(
        \waddr_user_c[0] ));
    RAM_with_wrapper RAM_with_wrapper_0 (.rdata_user_c({
        \rdata_user_c[7] , \rdata_user_c[6] , \rdata_user_c[5] , 
        \rdata_user_c[4] , \rdata_user_c[3] , \rdata_user_c[2] , 
        \rdata_user_c[1] , \rdata_user_c[0] }), .wdata_user_c({
        \wdata_user_c[7] , \wdata_user_c[6] , \wdata_user_c[5] , 
        \wdata_user_c[4] , \wdata_user_c[3] , \wdata_user_c[2] , 
        \wdata_user_c[1] , \wdata_user_c[0] }), 
        .CoreAPB3_0_APBmslave0_PWDATA({
        \CoreAPB3_0_APBmslave0_PWDATA[7] , 
        \CoreAPB3_0_APBmslave0_PWDATA[6] , 
        \CoreAPB3_0_APBmslave0_PWDATA[5] , 
        \CoreAPB3_0_APBmslave0_PWDATA[4] , 
        \CoreAPB3_0_APBmslave0_PWDATA[3] , 
        \CoreAPB3_0_APBmslave0_PWDATA[2] , 
        \CoreAPB3_0_APBmslave0_PWDATA[1] , 
        \CoreAPB3_0_APBmslave0_PWDATA[0] }), .waddr_user_c({
        \waddr_user_c[5] , \waddr_user_c[4] , \waddr_user_c[3] , 
        \waddr_user_c[2] , \waddr_user_c[1] , \waddr_user_c[0] }), 
        .raddr_user_c({\raddr_user_c[5] , \raddr_user_c[4] , 
        \raddr_user_c[3] , \raddr_user_c[2] , \raddr_user_c[1] , 
        \raddr_user_c[0] }), .CoreAPB3_0_APBmslave0_PRDATA_m({
        \CoreAPB3_0_APBmslave0_PRDATA_m[7] , 
        \CoreAPB3_0_APBmslave0_PRDATA_m[6] , 
        \CoreAPB3_0_APBmslave0_PRDATA_m[5] , 
        \CoreAPB3_0_APBmslave0_PRDATA_m[4] , 
        \CoreAPB3_0_APBmslave0_PRDATA_m[3] , 
        \CoreAPB3_0_APBmslave0_PRDATA_m[2] , 
        \CoreAPB3_0_APBmslave0_PRDATA_m[1] , 
        \CoreAPB3_0_APBmslave0_PRDATA_m[0] }), 
        .CoreAPB3_0_APBmslave0_PADDR({\CoreAPB3_0_APBmslave0_PADDR[7] , 
        \CoreAPB3_0_APBmslave0_PADDR[6] , 
        \CoreAPB3_0_APBmslave0_PADDR[5] , 
        \CoreAPB3_0_APBmslave0_PADDR[4] , 
        \CoreAPB3_0_APBmslave0_PADDR[3] , 
        \CoreAPB3_0_APBmslave0_PADDR[2] , 
        \CoreAPB3_0_APBmslave0_PADDR[1] , 
        \CoreAPB3_0_APBmslave0_PADDR[0] }), .rd_enable_user_c(
        rd_enable_user_c), .wr_enable_user_c(wr_enable_user_c), 
        .rclk_user_c(rclk_user_c), .wclk_user_c(wclk_user_c), 
        .CoreAPB3_0_APBmslave0_PREADY(CoreAPB3_0_APBmslave0_PREADY), 
        .FlashFreeze_SB_0_POWER_ON_RESET_N(
        FlashFreeze_SB_0_POWER_ON_RESET_N), 
        .FlashFreeze_SB_0_FIC_0_CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .SEL_c(SEL_c), .CoreAPB3_0_APBmslave0_PWRITE(
        CoreAPB3_0_APBmslave0_PWRITE), .CoreAPB3_0_APBmslave0_PSELx(
        CoreAPB3_0_APBmslave0_PSELx));
    OUTBUF LED8_obuf (.D(GND_net_1), .PAD(LED8));
    INBUF \wdata_user_ibuf[5]  (.PAD(wdata_user[5]), .Y(
        \wdata_user_c[5] ));
    INBUF \raddr_user_ibuf[2]  (.PAD(raddr_user[2]), .Y(
        \raddr_user_c[2] ));
    INBUF \waddr_user_ibuf[5]  (.PAD(waddr_user[5]), .Y(
        \waddr_user_c[5] ));
    FlashFreeze_SB FlashFreeze_SB_0 (
        .FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA({
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[7] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[6] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[5] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[4] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[3] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[2] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[1] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[0] }), 
        .FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA({
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[7] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[6] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[5] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[4] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[3] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[2] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[1] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[0] }), .M0GATEDHADDR({
        \FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.M0GATEDHADDR[27] , 
        \FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.M0GATEDHADDR[26] , 
        \FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.M0GATEDHADDR[25] , 
        \FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.M0GATEDHADDR[24] }), 
        .CAHBtoAPB3IOI_3(
        \COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3IOI[3] ), 
        .CAHBtoAPB3IOI_0(
        \COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3IOI[0] ), 
        .CAHBtoAPB3IOI_4(
        \COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3IOI[4] ), 
        .masterAddrInProg_0(
        \FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_0.masterAddrInProg[0] )
        , .MMUART_1_TXD(MMUART_1_TXD), .MMUART_1_RXD_0(MMUART_1_RXD_0), 
        .CoreAPB3_0_APBmslave0_PWRITE(CoreAPB3_0_APBmslave0_PWRITE), 
        .CAHBtoAPB3ll4(\COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3ll4 ), 
        .CAHBtoAPB3lII(\COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3lII ), 
        .N_250(N_250), .N_181_mux_i(N_181_mux_i), .CAHBtoAPB3II(
        \COREAHBTOAPB3_0.CAHBtoAPB3II ), .N_151(N_151), .CAHBtoAPB3III(
        \COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3III ), .N_25_0(N_25_0)
        , .CoreAPB3_0_APBmslave0_PSELx(CoreAPB3_0_APBmslave0_PSELx), 
        .CoreAPB3_0_APBmslave0_PREADY(CoreAPB3_0_APBmslave0_PREADY), 
        .PENABLE(\COREAHBTOAPB3_0.PENABLE ), .N_54_0(N_54_0), .N_63_0(
        N_63_0), .CAHBtoAPB3OI(\COREAHBTOAPB3_0.CAHBtoAPB3OI ), 
        .N_153_mux(N_153_mux), .N_56_0_i(N_56_0_i), .m19_e_0(
        \FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_0.m19_e_0 )
        , .N_178_mux(N_178_mux), .N_247_mux(N_247_mux), .N_179_mux(
        N_179_mux), .N_177_mux_i(N_177_mux_i), .CAHBtoAPB3lI(
        \COREAHBTOAPB3_0.CAHBtoAPB3lI ), .N_12_i(N_12_i), .N_55_i(
        N_55_i), .N_57_i(N_57_i), .N_59_i(N_59_i), .N_61_i(N_61_i), 
        .N_123_i(N_123_i), .N_125_i(N_125_i), .N_51_i(N_51_i), 
        .N_122_i(N_122_i), .N_126_i(N_126_i), .N_128_i(N_128_i), 
        .N_129_i(N_129_i), .N_131_i(N_131_i), .N_171_mux(N_171_mux), 
        .FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .N_185(N_185), .N_186(
        N_186), .N_187(N_187), .N_188(N_188), .N_189(N_189), .N_190(
        N_190), .N_191(N_191), .N_192(N_192), 
        .FlashFreeze_SB_0_FIC_0_CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .FLASH_FREEZE_0_FF_DONE(FLASH_FREEZE_0_FF_DONE), .FIC_0_LOCK_c(
        FIC_0_LOCK_c), .DEVRST_N(DEVRST_N), 
        .FlashFreeze_SB_0_POWER_ON_RESET_N(
        FlashFreeze_SB_0_POWER_ON_RESET_N));
    INBUF \wdata_user_ibuf[0]  (.PAD(wdata_user[0]), .Y(
        \wdata_user_c[0] ));
    INBUF \raddr_user_ibuf[1]  (.PAD(raddr_user[1]), .Y(
        \raddr_user_c[1] ));
    OUTBUF \rdata_user_obuf[7]  (.D(\rdata_user_c[7] ), .PAD(
        rdata_user[7]));
    INBUF \raddr_user_ibuf[3]  (.PAD(raddr_user[3]), .Y(
        \raddr_user_c[3] ));
    OUTBUF LED_3_obuf (.D(LED_3_c), .PAD(LED_3));
    GND GND (.Y(GND_net_1));
    COREAHBTOAPB3_19s_0s COREAHBTOAPB3_0 (
        .CoreAPB3_0_APBmslave0_PWDATA({
        \CoreAPB3_0_APBmslave0_PWDATA[7] , 
        \CoreAPB3_0_APBmslave0_PWDATA[6] , 
        \CoreAPB3_0_APBmslave0_PWDATA[5] , 
        \CoreAPB3_0_APBmslave0_PWDATA[4] , 
        \CoreAPB3_0_APBmslave0_PWDATA[3] , 
        \CoreAPB3_0_APBmslave0_PWDATA[2] , 
        \CoreAPB3_0_APBmslave0_PWDATA[1] , 
        \CoreAPB3_0_APBmslave0_PWDATA[0] }), 
        .FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA({
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[7] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[6] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[5] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[4] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[3] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[2] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[1] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA[0] }), 
        .CoreAPB3_0_APBmslave0_PADDR({\CoreAPB3_0_APBmslave0_PADDR[7] , 
        \CoreAPB3_0_APBmslave0_PADDR[6] , 
        \CoreAPB3_0_APBmslave0_PADDR[5] , 
        \CoreAPB3_0_APBmslave0_PADDR[4] , 
        \CoreAPB3_0_APBmslave0_PADDR[3] , 
        \CoreAPB3_0_APBmslave0_PADDR[2] , 
        \CoreAPB3_0_APBmslave0_PADDR[1] , 
        \CoreAPB3_0_APBmslave0_PADDR[0] }), 
        .COREAHBTOAPB3_0_APBmaster_PADDR({
        \COREAHBTOAPB3_0_APBmaster_PADDR[27] , 
        \COREAHBTOAPB3_0_APBmaster_PADDR[26] , 
        \COREAHBTOAPB3_0_APBmaster_PADDR[25] , 
        \COREAHBTOAPB3_0_APBmaster_PADDR[24] }), 
        .FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA({
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[7] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[6] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[5] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[4] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[3] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[2] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[1] , 
        \FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA[0] }), 
        .CoreAPB3_0_APBmslave0_PRDATA_m({
        \CoreAPB3_0_APBmslave0_PRDATA_m[7] , 
        \CoreAPB3_0_APBmslave0_PRDATA_m[6] , 
        \CoreAPB3_0_APBmslave0_PRDATA_m[5] , 
        \CoreAPB3_0_APBmslave0_PRDATA_m[4] , 
        \CoreAPB3_0_APBmslave0_PRDATA_m[3] , 
        \CoreAPB3_0_APBmslave0_PRDATA_m[2] , 
        \CoreAPB3_0_APBmslave0_PRDATA_m[1] , 
        \CoreAPB3_0_APBmslave0_PRDATA_m[0] }), .M0GATEDHADDR({
        \FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.M0GATEDHADDR[27] , 
        \FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.M0GATEDHADDR[26] , 
        \FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.M0GATEDHADDR[25] , 
        \FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.M0GATEDHADDR[24] }), 
        .CAHBtoAPB3IOI_0(
        \COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3IOI[0] ), 
        .CAHBtoAPB3IOI_3(
        \COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3IOI[3] ), 
        .CAHBtoAPB3IOI_4(
        \COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3IOI[4] ), 
        .masterAddrInProg_0(
        \FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_0.masterAddrInProg[0] )
        , .N_55_i(N_55_i), .N_57_i(N_57_i), .N_59_i(N_59_i), .N_61_i(
        N_61_i), .N_123_i(N_123_i), .N_125_i(N_125_i), .N_126_i(
        N_126_i), .N_128_i(N_128_i), .N_129_i(N_129_i), .N_131_i(
        N_131_i), .CAHBtoAPB3II(\COREAHBTOAPB3_0.CAHBtoAPB3II ), 
        .N_51_i(N_51_i), .N_122_i(N_122_i), .N_185(N_185), .N_186(
        N_186), .N_187(N_187), .N_188(N_188), .N_189(N_189), .N_190(
        N_190), .N_191(N_191), .N_192(N_192), .N_171_mux(N_171_mux), 
        .N_25_0(N_25_0), .CAHBtoAPB3lII(
        \COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3lII ), 
        .FlashFreeze_SB_0_POWER_ON_RESET_N(
        FlashFreeze_SB_0_POWER_ON_RESET_N), 
        .FlashFreeze_SB_0_FIC_0_CLK(FlashFreeze_SB_0_FIC_0_CLK), 
        .N_250(N_250), .CAHBtoAPB3III(
        \COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3III ), .N_12_i(N_12_i)
        , .CAHBtoAPB3lI(\COREAHBTOAPB3_0.CAHBtoAPB3lI ), 
        .COREAHBTOAPB3_0_APBmaster_PSELx(
        COREAHBTOAPB3_0_APBmaster_PSELx), .N_178_mux(N_178_mux), 
        .FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY(
        FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY), .N_181_mux_i(
        N_181_mux_i), .N_177_mux_i(N_177_mux_i), .CAHBtoAPB3OI(
        \COREAHBTOAPB3_0.CAHBtoAPB3OI ), .CoreAPB3_0_APBmslave0_PWRITE(
        CoreAPB3_0_APBmslave0_PWRITE), .N_56_0_i(N_56_0_i), .N_179_mux(
        N_179_mux), .N_247_mux(N_247_mux), .PENABLE(
        \COREAHBTOAPB3_0.PENABLE ), .CoreAPB3_0_APBmslave0_PSELx(
        CoreAPB3_0_APBmslave0_PSELx), .CoreAPB3_0_APBmslave0_PREADY(
        CoreAPB3_0_APBmslave0_PREADY), .CAHBtoAPB3ll4(
        \COREAHBTOAPB3_0.CAHBtoAPB3lll.CAHBtoAPB3ll4 ), .N_151(N_151), 
        .N_54_0(N_54_0), .m19_e_0(
        \FlashFreeze_SB_0.CoreAHBLite_0.matrix4x16.slavestage_0.m19_e_0 )
        , .N_63_0(N_63_0), .N_153_mux(N_153_mux));
    OUTBUF SEL_obuf (.D(SEL_c), .PAD(SEL));
    INBUF \waddr_user_ibuf[4]  (.PAD(waddr_user[4]), .Y(
        \waddr_user_c[4] ));
    INBUF DIP3_K21_On_1_ibuf (.PAD(DIP3_K21_On_1), .Y(DIP3_output_c));
    INBUF DIP1_L19_On_0_ibuf (.PAD(DIP1_L19_On_0), .Y(DIP1_output_c));
    INBUF \wdata_user_ibuf[1]  (.PAD(wdata_user[1]), .Y(
        \wdata_user_c[1] ));
    OUTBUF \rdata_user_obuf[1]  (.D(\rdata_user_c[1] ), .PAD(
        rdata_user[1]));
    cnt34 cnt34_0 (.LED_4_c(LED_4_c), .LED_3_c(LED_3_c), .LED_2_c(
        LED_2_c), .LED_1_c(LED_1_c), .FlashFreeze_SB_0_FIC_0_CLK(
        FlashFreeze_SB_0_FIC_0_CLK), 
        .FlashFreeze_SB_0_POWER_ON_RESET_N(
        FlashFreeze_SB_0_POWER_ON_RESET_N));
    INBUF \wdata_user_ibuf[4]  (.PAD(wdata_user[4]), .Y(
        \wdata_user_c[4] ));
    INBUF rclk_user_ibuf (.PAD(rclk_user), .Y(rclk_user_c));
    INBUF \wdata_user_ibuf[7]  (.PAD(wdata_user[7]), .Y(
        \wdata_user_c[7] ));
    OUTBUF DIP4_output_obuf (.D(DIP4_output_c), .PAD(DIP4_output));
    INBUF wr_enable_user_ibuf (.PAD(wr_enable_user), .Y(
        wr_enable_user_c));
    OUTBUF FIC_0_LOCK_obuf (.D(FIC_0_LOCK_c), .PAD(FIC_0_LOCK));
    INBUF DIP4_K20_On_1_ibuf (.PAD(DIP4_K20_On_1), .Y(DIP4_output_c));
    OUTBUF \rdata_user_obuf[3]  (.D(\rdata_user_c[3] ), .PAD(
        rdata_user[3]));
    INBUF \waddr_user_ibuf[2]  (.PAD(waddr_user[2]), .Y(
        \waddr_user_c[2] ));
    OUTBUF LED_4_obuf (.D(LED_4_c), .PAD(LED_4));
    INBUF \waddr_user_ibuf[3]  (.PAD(waddr_user[3]), .Y(
        \waddr_user_c[3] ));
    INBUF \waddr_user_ibuf[1]  (.PAD(waddr_user[1]), .Y(
        \waddr_user_c[1] ));
    OUTBUF DIP3_output_obuf (.D(DIP3_output_c), .PAD(DIP3_output));
    OUTBUF \rdata_user_obuf[2]  (.D(\rdata_user_c[2] ), .PAD(
        rdata_user[2]));
    OUTBUF LED_2_obuf (.D(LED_2_c), .PAD(LED_2));
    INBUF DIP2_L18_On_0_ibuf (.PAD(DIP2_L18_On_0), .Y(DIP2_output_c));
    INBUF wclk_user_ibuf (.PAD(wclk_user), .Y(wclk_user_c));
    OUTBUF LED_1_obuf (.D(LED_1_c), .PAD(LED_1));
    
endmodule
