//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Fri Mar 17 14:26:13 2017
// Version: v11.8 11.8.0.26
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

// FlashFreeze_SB_top
module FlashFreeze_SB_top(
    // Inputs
    DEVRST_N,
    DIP1_L19_On_0,
    DIP2_L18_On_0,
    DIP3_K21_On_1,
    DIP4_K20_On_1,
    MMUART_1_RXD_0,
    SW1_L20_On_Change,
    raddr_user,
    rclk_user,
    rd_enable_user,
    waddr_user,
    wclk_user,
    wdata_user,
    wr_enable_user,
    // Outputs
    DIP1_output,
    DIP2_output,
    DIP3_output,
    DIP4_output,
    FIC_0_LOCK,
    LED8,
    LED_1,
    LED_2,
    LED_3,
    LED_4,
    MMUART_1_TXD,
    SEL,
    SW1_output,
    rdata_user
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input        DEVRST_N;
input        DIP1_L19_On_0;
input        DIP2_L18_On_0;
input        DIP3_K21_On_1;
input        DIP4_K20_On_1;
input        MMUART_1_RXD_0;
input        SW1_L20_On_Change;
input  [5:0] raddr_user;
input        rclk_user;
input        rd_enable_user;
input  [5:0] waddr_user;
input        wclk_user;
input  [7:0] wdata_user;
input        wr_enable_user;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output       DIP1_output;
output       DIP2_output;
output       DIP3_output;
output       DIP4_output;
output       FIC_0_LOCK;
output       LED8;
output       LED_1;
output       LED_2;
output       LED_3;
output       LED_4;
output       MMUART_1_TXD;
output       SEL;
output       SW1_output;
output [7:0] rdata_user;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire   [31:0]  COREAHBTOAPB3_0_APBmaster_PADDR;
wire           COREAHBTOAPB3_0_APBmaster_PENABLE;
wire   [31:0]  COREAHBTOAPB3_0_APBmaster_PRDATA;
wire           COREAHBTOAPB3_0_APBmaster_PREADY;
wire           COREAHBTOAPB3_0_APBmaster_PSELx;
wire           COREAHBTOAPB3_0_APBmaster_PSLVERR;
wire   [31:0]  COREAHBTOAPB3_0_APBmaster_PWDATA;
wire           COREAHBTOAPB3_0_APBmaster_PWRITE;
wire           CoreAPB3_0_APBmslave0_PENABLE;
wire           CoreAPB3_0_APBmslave0_PREADY;
wire           CoreAPB3_0_APBmslave0_PSELx;
wire           CoreAPB3_0_APBmslave0_PSLVERR;
wire           CoreAPB3_0_APBmslave0_PWRITE;
wire           DEVRST_N;
wire           DIP1_L19_On_0;
wire           DIP1_output_net_0;
wire           DIP2_L18_On_0;
wire           DIP2_output_net_0;
wire           DIP3_K21_On_1;
wire           DIP3_output_net_0;
wire           DIP4_K20_On_1;
wire           DIP4_output_net_0;
wire           FIC_0_LOCK_0;
wire           FLASH_FREEZE_0_FF_DONE;
wire   [31:0]  FlashFreeze_SB_0_AMBA_SLAVE_0_HADDR;
wire   [2:0]   FlashFreeze_SB_0_AMBA_SLAVE_0_HBURST;
wire           FlashFreeze_SB_0_AMBA_SLAVE_0_HMASTLOCK;
wire   [3:0]   FlashFreeze_SB_0_AMBA_SLAVE_0_HPROT;
wire   [31:0]  FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA;
wire           FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY;
wire           FlashFreeze_SB_0_AMBA_SLAVE_0_HREADYOUT;
wire   [1:0]   FlashFreeze_SB_0_AMBA_SLAVE_0_HRESP;
wire           FlashFreeze_SB_0_AMBA_SLAVE_0_HSELx;
wire   [2:0]   FlashFreeze_SB_0_AMBA_SLAVE_0_HSIZE;
wire   [1:0]   FlashFreeze_SB_0_AMBA_SLAVE_0_HTRANS;
wire   [31:0]  FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA;
wire           FlashFreeze_SB_0_AMBA_SLAVE_0_HWRITE;
wire           FlashFreeze_SB_0_FIC_0_CLK;
wire           FlashFreeze_SB_0_POWER_ON_RESET_N;
wire           LED8_net_0;
wire   [23:23] LED_1_net_0;
wire   [24:24] LED_2_net_0;
wire   [25:25] LED_3_net_0;
wire   [26:26] LED_4_net_0;
wire           MMUART_1_RXD_0;
wire           MMUART_1_TXD_1;
wire   [5:0]   raddr_user;
wire           rclk_user;
wire           rd_enable_user;
wire   [7:0]   rdata_user_net_0;
wire           SEL_net_0;
wire           SW1_L20_On_Change;
wire           SW1_output_net_0;
wire   [5:0]   waddr_user;
wire           wclk_user;
wire   [7:0]   wdata_user;
wire           wr_enable_user;
wire           SEL_net_1;
wire           LED_3_net_1;
wire           LED_1_net_1;
wire           LED_2_net_1;
wire           LED_4_net_1;
wire           DIP2_output_net_1;
wire           DIP4_output_net_1;
wire           DIP1_output_net_1;
wire           DIP3_output_net_1;
wire           LED8_net_1;
wire           SW1_output_net_1;
wire           FIC_0_LOCK_0_net_0;
wire           MMUART_1_TXD_1_net_0;
wire   [7:0]   rdata_user_net_1;
wire   [22:0]  CNT_slice_0;
wire   [33:27] CNT_slice_1;
wire   [33:0]  CNT_net_0;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire           VCC_net;
wire           GND_net;
wire   [31:0]  IADDR_const_net_0;
wire   [31:0]  PRDATAS1_const_net_0;
wire   [31:0]  PRDATAS2_const_net_0;
wire   [31:0]  PRDATAS3_const_net_0;
wire   [31:0]  PRDATAS4_const_net_0;
wire   [31:0]  PRDATAS5_const_net_0;
wire   [31:0]  PRDATAS6_const_net_0;
wire   [31:0]  PRDATAS7_const_net_0;
wire   [31:0]  PRDATAS8_const_net_0;
wire   [31:0]  PRDATAS9_const_net_0;
wire   [31:0]  PRDATAS10_const_net_0;
wire   [31:0]  PRDATAS11_const_net_0;
wire   [31:0]  PRDATAS12_const_net_0;
wire   [31:0]  PRDATAS13_const_net_0;
wire   [31:0]  PRDATAS14_const_net_0;
wire   [31:0]  PRDATAS15_const_net_0;
wire   [31:0]  PRDATAS16_const_net_0;
//--------------------------------------------------------------------
// Bus Interface Nets Declarations - Unequal Pin Widths
//--------------------------------------------------------------------
wire   [31:0]  CoreAPB3_0_APBmslave0_PADDR;
wire   [7:0]   CoreAPB3_0_APBmslave0_PADDR_0_7to0;
wire   [7:0]   CoreAPB3_0_APBmslave0_PADDR_0;
wire   [31:8]  CoreAPB3_0_APBmslave0_PRDATA_0_31to8;
wire   [7:0]   CoreAPB3_0_APBmslave0_PRDATA_0_7to0;
wire   [31:0]  CoreAPB3_0_APBmslave0_PRDATA_0;
wire   [7:0]   CoreAPB3_0_APBmslave0_PRDATA;
wire   [31:0]  CoreAPB3_0_APBmslave0_PWDATA;
wire   [7:0]   CoreAPB3_0_APBmslave0_PWDATA_0_7to0;
wire   [7:0]   CoreAPB3_0_APBmslave0_PWDATA_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign VCC_net               = 1'b1;
assign GND_net               = 1'b0;
assign IADDR_const_net_0     = 32'h00000000;
assign PRDATAS1_const_net_0  = 32'h00000000;
assign PRDATAS2_const_net_0  = 32'h00000000;
assign PRDATAS3_const_net_0  = 32'h00000000;
assign PRDATAS4_const_net_0  = 32'h00000000;
assign PRDATAS5_const_net_0  = 32'h00000000;
assign PRDATAS6_const_net_0  = 32'h00000000;
assign PRDATAS7_const_net_0  = 32'h00000000;
assign PRDATAS8_const_net_0  = 32'h00000000;
assign PRDATAS9_const_net_0  = 32'h00000000;
assign PRDATAS10_const_net_0 = 32'h00000000;
assign PRDATAS11_const_net_0 = 32'h00000000;
assign PRDATAS12_const_net_0 = 32'h00000000;
assign PRDATAS13_const_net_0 = 32'h00000000;
assign PRDATAS14_const_net_0 = 32'h00000000;
assign PRDATAS15_const_net_0 = 32'h00000000;
assign PRDATAS16_const_net_0 = 32'h00000000;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign SEL_net_1            = SEL_net_0;
assign SEL                  = SEL_net_1;
assign LED_3_net_1          = LED_3_net_0[25];
assign LED_3                = LED_3_net_1;
assign LED_1_net_1          = LED_1_net_0[23];
assign LED_1                = LED_1_net_1;
assign LED_2_net_1          = LED_2_net_0[24];
assign LED_2                = LED_2_net_1;
assign LED_4_net_1          = LED_4_net_0[26];
assign LED_4                = LED_4_net_1;
assign DIP2_output_net_1    = DIP2_output_net_0;
assign DIP2_output          = DIP2_output_net_1;
assign DIP4_output_net_1    = DIP4_output_net_0;
assign DIP4_output          = DIP4_output_net_1;
assign DIP1_output_net_1    = DIP1_output_net_0;
assign DIP1_output          = DIP1_output_net_1;
assign DIP3_output_net_1    = DIP3_output_net_0;
assign DIP3_output          = DIP3_output_net_1;
assign LED8_net_1           = LED8_net_0;
assign LED8                 = LED8_net_1;
assign SW1_output_net_1     = SW1_output_net_0;
assign SW1_output           = SW1_output_net_1;
assign FIC_0_LOCK_0_net_0   = FIC_0_LOCK_0;
assign FIC_0_LOCK           = FIC_0_LOCK_0_net_0;
assign MMUART_1_TXD_1_net_0 = MMUART_1_TXD_1;
assign MMUART_1_TXD         = MMUART_1_TXD_1_net_0;
assign rdata_user_net_1     = rdata_user_net_0;
assign rdata_user[7:0]      = rdata_user_net_1;
//--------------------------------------------------------------------
// Slices assignments
//--------------------------------------------------------------------
assign LED_1_net_0[23] = CNT_net_0[23:23];
assign LED_2_net_0[24] = CNT_net_0[24:24];
assign LED_3_net_0[25] = CNT_net_0[25:25];
assign LED_4_net_0[26] = CNT_net_0[26:26];
assign CNT_slice_0     = CNT_net_0[22:0];
assign CNT_slice_1     = CNT_net_0[33:27];
//--------------------------------------------------------------------
// Bus Interface Nets Assignments - Unequal Pin Widths
//--------------------------------------------------------------------
assign CoreAPB3_0_APBmslave0_PADDR_0_7to0 = CoreAPB3_0_APBmslave0_PADDR[7:0];
assign CoreAPB3_0_APBmslave0_PADDR_0 = { CoreAPB3_0_APBmslave0_PADDR_0_7to0 };

assign CoreAPB3_0_APBmslave0_PRDATA_0_31to8 = 24'h0;
assign CoreAPB3_0_APBmslave0_PRDATA_0_7to0 = CoreAPB3_0_APBmslave0_PRDATA[7:0];
assign CoreAPB3_0_APBmslave0_PRDATA_0 = { CoreAPB3_0_APBmslave0_PRDATA_0_31to8, CoreAPB3_0_APBmslave0_PRDATA_0_7to0 };

assign CoreAPB3_0_APBmslave0_PWDATA_0_7to0 = CoreAPB3_0_APBmslave0_PWDATA[7:0];
assign CoreAPB3_0_APBmslave0_PWDATA_0 = { CoreAPB3_0_APBmslave0_PWDATA_0_7to0 };

//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------cnt34
cnt34 cnt34_0(
        // Inputs
        .RSTN ( FlashFreeze_SB_0_POWER_ON_RESET_N ),
        .CLK  ( FlashFreeze_SB_0_FIC_0_CLK ),
        // Outputs
        .CNT  ( CNT_net_0 ) 
        );

//--------COREAHBTOAPB3   -   Actel:DirectCore:COREAHBTOAPB3:3.1.100
COREAHBTOAPB3 #( 
        .FAMILY ( 19 ) )
COREAHBTOAPB3_0(
        // Inputs
        .HCLK      ( FlashFreeze_SB_0_FIC_0_CLK ),
        .HRESETN   ( FlashFreeze_SB_0_POWER_ON_RESET_N ),
        .HWRITE    ( FlashFreeze_SB_0_AMBA_SLAVE_0_HWRITE ),
        .HSEL      ( FlashFreeze_SB_0_AMBA_SLAVE_0_HSELx ),
        .HREADY    ( FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY ),
        .PREADY    ( COREAHBTOAPB3_0_APBmaster_PREADY ),
        .PSLVERR   ( COREAHBTOAPB3_0_APBmaster_PSLVERR ),
        .HADDR     ( FlashFreeze_SB_0_AMBA_SLAVE_0_HADDR ),
        .HTRANS    ( FlashFreeze_SB_0_AMBA_SLAVE_0_HTRANS ),
        .HWDATA    ( FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA ),
        .PRDATA    ( COREAHBTOAPB3_0_APBmaster_PRDATA ),
        // Outputs
        .HREADYOUT ( FlashFreeze_SB_0_AMBA_SLAVE_0_HREADYOUT ),
        .PENABLE   ( COREAHBTOAPB3_0_APBmaster_PENABLE ),
        .PWRITE    ( COREAHBTOAPB3_0_APBmaster_PWRITE ),
        .PSEL      ( COREAHBTOAPB3_0_APBmaster_PSELx ),
        .HRDATA    ( FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA ),
        .HRESP     ( FlashFreeze_SB_0_AMBA_SLAVE_0_HRESP ),
        .PWDATA    ( COREAHBTOAPB3_0_APBmaster_PWDATA ),
        .PADDR     ( COREAHBTOAPB3_0_APBmaster_PADDR ) 
        );

//--------CoreAPB3   -   Actel:DirectCore:CoreAPB3:4.1.100
CoreAPB3 #( 
        .APB_DWIDTH      ( 32 ),
        .APBSLOT0ENABLE  ( 1 ),
        .APBSLOT1ENABLE  ( 0 ),
        .APBSLOT2ENABLE  ( 0 ),
        .APBSLOT3ENABLE  ( 0 ),
        .APBSLOT4ENABLE  ( 0 ),
        .APBSLOT5ENABLE  ( 0 ),
        .APBSLOT6ENABLE  ( 0 ),
        .APBSLOT7ENABLE  ( 0 ),
        .APBSLOT8ENABLE  ( 0 ),
        .APBSLOT9ENABLE  ( 0 ),
        .APBSLOT10ENABLE ( 0 ),
        .APBSLOT11ENABLE ( 0 ),
        .APBSLOT12ENABLE ( 0 ),
        .APBSLOT13ENABLE ( 0 ),
        .APBSLOT14ENABLE ( 0 ),
        .APBSLOT15ENABLE ( 0 ),
        .FAMILY          ( 19 ),
        .IADDR_OPTION    ( 0 ),
        .MADDR_BITS      ( 28 ),
        .SC_0            ( 0 ),
        .SC_1            ( 0 ),
        .SC_2            ( 0 ),
        .SC_3            ( 0 ),
        .SC_4            ( 0 ),
        .SC_5            ( 0 ),
        .SC_6            ( 0 ),
        .SC_7            ( 0 ),
        .SC_8            ( 0 ),
        .SC_9            ( 0 ),
        .SC_10           ( 0 ),
        .SC_11           ( 0 ),
        .SC_12           ( 0 ),
        .SC_13           ( 0 ),
        .SC_14           ( 0 ),
        .SC_15           ( 0 ),
        .UPR_NIBBLE_POSN ( 6 ) )
CoreAPB3_0(
        // Inputs
        .PRESETN    ( GND_net ), // tied to 1'b0 from definition
        .PCLK       ( GND_net ), // tied to 1'b0 from definition
        .PWRITE     ( COREAHBTOAPB3_0_APBmaster_PWRITE ),
        .PENABLE    ( COREAHBTOAPB3_0_APBmaster_PENABLE ),
        .PSEL       ( COREAHBTOAPB3_0_APBmaster_PSELx ),
        .PREADYS0   ( CoreAPB3_0_APBmslave0_PREADY ),
        .PSLVERRS0  ( CoreAPB3_0_APBmslave0_PSLVERR ),
        .PREADYS1   ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS1  ( GND_net ), // tied to 1'b0 from definition
        .PREADYS2   ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS2  ( GND_net ), // tied to 1'b0 from definition
        .PREADYS3   ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS3  ( GND_net ), // tied to 1'b0 from definition
        .PREADYS4   ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS4  ( GND_net ), // tied to 1'b0 from definition
        .PREADYS5   ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS5  ( GND_net ), // tied to 1'b0 from definition
        .PREADYS6   ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS6  ( GND_net ), // tied to 1'b0 from definition
        .PREADYS7   ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS7  ( GND_net ), // tied to 1'b0 from definition
        .PREADYS8   ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS8  ( GND_net ), // tied to 1'b0 from definition
        .PREADYS9   ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS9  ( GND_net ), // tied to 1'b0 from definition
        .PREADYS10  ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS10 ( GND_net ), // tied to 1'b0 from definition
        .PREADYS11  ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS11 ( GND_net ), // tied to 1'b0 from definition
        .PREADYS12  ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS12 ( GND_net ), // tied to 1'b0 from definition
        .PREADYS13  ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS13 ( GND_net ), // tied to 1'b0 from definition
        .PREADYS14  ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS14 ( GND_net ), // tied to 1'b0 from definition
        .PREADYS15  ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS15 ( GND_net ), // tied to 1'b0 from definition
        .PREADYS16  ( VCC_net ), // tied to 1'b1 from definition
        .PSLVERRS16 ( GND_net ), // tied to 1'b0 from definition
        .PADDR      ( COREAHBTOAPB3_0_APBmaster_PADDR ),
        .PWDATA     ( COREAHBTOAPB3_0_APBmaster_PWDATA ),
        .PRDATAS0   ( CoreAPB3_0_APBmslave0_PRDATA_0 ),
        .PRDATAS1   ( PRDATAS1_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS2   ( PRDATAS2_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS3   ( PRDATAS3_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS4   ( PRDATAS4_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS5   ( PRDATAS5_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS6   ( PRDATAS6_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS7   ( PRDATAS7_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS8   ( PRDATAS8_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS9   ( PRDATAS9_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS10  ( PRDATAS10_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS11  ( PRDATAS11_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS12  ( PRDATAS12_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS13  ( PRDATAS13_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS14  ( PRDATAS14_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS15  ( PRDATAS15_const_net_0 ), // tied to 32'h00000000 from definition
        .PRDATAS16  ( PRDATAS16_const_net_0 ), // tied to 32'h00000000 from definition
        .IADDR      ( IADDR_const_net_0 ), // tied to 32'h00000000 from definition
        // Outputs
        .PREADY     ( COREAHBTOAPB3_0_APBmaster_PREADY ),
        .PSLVERR    ( COREAHBTOAPB3_0_APBmaster_PSLVERR ),
        .PWRITES    ( CoreAPB3_0_APBmslave0_PWRITE ),
        .PENABLES   ( CoreAPB3_0_APBmslave0_PENABLE ),
        .PSELS0     ( CoreAPB3_0_APBmslave0_PSELx ),
        .PSELS1     (  ),
        .PSELS2     (  ),
        .PSELS3     (  ),
        .PSELS4     (  ),
        .PSELS5     (  ),
        .PSELS6     (  ),
        .PSELS7     (  ),
        .PSELS8     (  ),
        .PSELS9     (  ),
        .PSELS10    (  ),
        .PSELS11    (  ),
        .PSELS12    (  ),
        .PSELS13    (  ),
        .PSELS14    (  ),
        .PSELS15    (  ),
        .PSELS16    (  ),
        .PRDATA     ( COREAHBTOAPB3_0_APBmaster_PRDATA ),
        .PADDRS     ( CoreAPB3_0_APBmslave0_PADDR ),
        .PWDATAS    ( CoreAPB3_0_APBmslave0_PWDATA ) 
        );

//--------DIP_SWITCHES
DIP_SWITCHES DIP_SWITCHES_0(
        // Inputs
        .DIP3_K21_On_1     ( DIP3_K21_On_1 ),
        .DIP4_K20_On_1     ( DIP4_K20_On_1 ),
        .DIP1_L19_On_0     ( DIP1_L19_On_0 ),
        .DIP2_L18_On_0     ( DIP2_L18_On_0 ),
        .SW1_L20_On_Change ( SW1_L20_On_Change ),
        // Outputs
        .DIP3_output       ( DIP3_output_net_0 ),
        .DIP4_output       ( DIP4_output_net_0 ),
        .DIP1_output       ( DIP1_output_net_0 ),
        .DIP2_output       ( DIP2_output_net_0 ),
        .SW1_output        ( SW1_output_net_0 ),
        .LED8              ( LED8_net_0 ) 
        );

//--------FLASH_FREEZE
FLASH_FREEZE FLASH_FREEZE_0(
        // Outputs
        .FF_TO_START (  ),
        .FF_DONE     ( FLASH_FREEZE_0_FF_DONE ) 
        );

//--------FlashFreeze_SB
FlashFreeze_SB FlashFreeze_SB_0(
        // Inputs
        .FAB_RESET_N               ( VCC_net ),
        .AMBA_SLAVE_0_HREADYOUT_S0 ( FlashFreeze_SB_0_AMBA_SLAVE_0_HREADYOUT ),
        .DEVRST_N                  ( DEVRST_N ),
        .FF_DONE                   ( FLASH_FREEZE_0_FF_DONE ),
        .MMUART_1_RXD_0            ( MMUART_1_RXD_0 ),
        .AMBA_SLAVE_0_HRDATA_S0    ( FlashFreeze_SB_0_AMBA_SLAVE_0_HRDATA ),
        .AMBA_SLAVE_0_HRESP_S0     ( FlashFreeze_SB_0_AMBA_SLAVE_0_HRESP ),
        // Outputs
        .POWER_ON_RESET_N          ( FlashFreeze_SB_0_POWER_ON_RESET_N ),
        .INIT_DONE                 (  ),
        .AMBA_SLAVE_0_HWRITE_S0    ( FlashFreeze_SB_0_AMBA_SLAVE_0_HWRITE ),
        .AMBA_SLAVE_0_HSEL_S0      ( FlashFreeze_SB_0_AMBA_SLAVE_0_HSELx ),
        .AMBA_SLAVE_0_HREADY_S0    ( FlashFreeze_SB_0_AMBA_SLAVE_0_HREADY ),
        .AMBA_SLAVE_0_HMASTLOCK_S0 ( FlashFreeze_SB_0_AMBA_SLAVE_0_HMASTLOCK ),
        .FIC_0_CLK                 ( FlashFreeze_SB_0_FIC_0_CLK ),
        .FIC_0_LOCK                ( FIC_0_LOCK_0 ),
        .MSS_READY                 (  ),
        .MMUART_1_TXD              ( MMUART_1_TXD_1 ),
        .AMBA_SLAVE_0_HADDR_S0     ( FlashFreeze_SB_0_AMBA_SLAVE_0_HADDR ),
        .AMBA_SLAVE_0_HTRANS_S0    ( FlashFreeze_SB_0_AMBA_SLAVE_0_HTRANS ),
        .AMBA_SLAVE_0_HSIZE_S0     ( FlashFreeze_SB_0_AMBA_SLAVE_0_HSIZE ),
        .AMBA_SLAVE_0_HWDATA_S0    ( FlashFreeze_SB_0_AMBA_SLAVE_0_HWDATA ),
        .AMBA_SLAVE_0_HBURST_S0    ( FlashFreeze_SB_0_AMBA_SLAVE_0_HBURST ),
        .AMBA_SLAVE_0_HPROT_S0     ( FlashFreeze_SB_0_AMBA_SLAVE_0_HPROT ) 
        );

//--------RAM_with_wrapper
RAM_with_wrapper RAM_with_wrapper_0(
        // Inputs
        .wr_enable_user ( wr_enable_user ),
        .rclk_user      ( rclk_user ),
        .rd_enable_user ( rd_enable_user ),
        .wclk_user      ( wclk_user ),
        .PRESETN        ( FlashFreeze_SB_0_POWER_ON_RESET_N ),
        .PCLK           ( FlashFreeze_SB_0_FIC_0_CLK ),
        .PENABLE        ( CoreAPB3_0_APBmslave0_PENABLE ),
        .PWRITE         ( CoreAPB3_0_APBmslave0_PWRITE ),
        .PSEL           ( CoreAPB3_0_APBmslave0_PSELx ),
        .raddr_user     ( raddr_user ),
        .wdata_user     ( wdata_user ),
        .waddr_user     ( waddr_user ),
        .PADDR          ( CoreAPB3_0_APBmslave0_PADDR_0 ),
        .PWDATA         ( CoreAPB3_0_APBmslave0_PWDATA_0 ),
        // Outputs
        .INT_OUT        (  ),
        .SEL            ( SEL_net_0 ),
        .PREADY         ( CoreAPB3_0_APBmslave0_PREADY ),
        .PSLVERR        ( CoreAPB3_0_APBmslave0_PSLVERR ),
        .rdata_user     ( rdata_user_net_0 ),
        .PRDATA         ( CoreAPB3_0_APBmslave0_PRDATA ) 
        );


endmodule
