//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Tue Mar 14 08:10:37 2017
// Version: v11.8 11.8.0.26
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

// RAM_with_wrapper
module RAM_with_wrapper(
    // Inputs
    PADDR,
    PCLK,
    PENABLE,
    PRESETN,
    PSEL,
    PWDATA,
    PWRITE,
    raddr_user,
    rclk_user,
    rd_enable_user,
    waddr_user,
    wclk_user,
    wdata_user,
    wr_enable_user,
    // Outputs
    INT_OUT,
    PRDATA,
    PREADY,
    PSLVERR,
    SEL,
    rdata_user
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input  [7:0] PADDR;
input        PCLK;
input        PENABLE;
input        PRESETN;
input        PSEL;
input  [7:0] PWDATA;
input        PWRITE;
input  [5:0] raddr_user;
input        rclk_user;
input        rd_enable_user;
input  [5:0] waddr_user;
input        wclk_user;
input  [7:0] wdata_user;
input        wr_enable_user;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output       INT_OUT;
output [7:0] PRDATA;
output       PREADY;
output       PSLVERR;
output       SEL;
output [7:0] rdata_user;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire   [7:0] PADDR;
wire         PENABLE;
wire   [7:0] BIF_1_PRDATA;
wire         BIF_1_PREADY;
wire         PSEL;
wire         BIF_1_PSLVERR;
wire   [7:0] PWDATA;
wire         PWRITE;
wire         INT_OUT_net_0;
wire   [7:0] mem_apb_wrp_0_mem_data_in;
wire   [5:0] mem_apb_wrp_0_raddr;
wire         mem_apb_wrp_0_rclk;
wire         mem_apb_wrp_0_rd_enable;
wire   [5:0] mem_apb_wrp_0_waddr;
wire         mem_apb_wrp_0_wclk;
wire         mem_apb_wrp_0_wr_enable;
wire   [7:0] mux_blk_0_mem_data_out_init;
wire   [5:0] mux_blk_0_raddr;
wire         mux_blk_0_rclk;
wire         mux_blk_0_rd_en;
wire   [5:0] mux_blk_0_waddr;
wire         mux_blk_0_wclk;
wire   [7:0] mux_blk_0_wdata;
wire         mux_blk_0_wr_en;
wire         PCLK;
wire         PRESETN;
wire   [5:0] raddr_user;
wire         rclk_user;
wire         rd_enable_user;
wire   [7:0] rdata_user_net_0;
wire         SEL_net_0;
wire   [7:0] TPSRAM_0_RD;
wire   [5:0] waddr_user;
wire         wclk_user;
wire   [7:0] wdata_user;
wire         wr_enable_user;
wire         INT_OUT_net_1;
wire         SEL_net_1;
wire         BIF_1_PREADY_net_0;
wire         BIF_1_PSLVERR_net_0;
wire   [7:0] rdata_user_net_1;
wire   [7:0] BIF_1_PRDATA_net_0;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire         GND_net;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign GND_net = 1'b0;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign INT_OUT_net_1       = INT_OUT_net_0;
assign INT_OUT             = INT_OUT_net_1;
assign SEL_net_1           = SEL_net_0;
assign SEL                 = SEL_net_1;
assign BIF_1_PREADY_net_0  = BIF_1_PREADY;
assign PREADY              = BIF_1_PREADY_net_0;
assign BIF_1_PSLVERR_net_0 = BIF_1_PSLVERR;
assign PSLVERR             = BIF_1_PSLVERR_net_0;
assign rdata_user_net_1    = rdata_user_net_0;
assign rdata_user[7:0]     = rdata_user_net_1;
assign BIF_1_PRDATA_net_0  = BIF_1_PRDATA;
assign PRDATA[7:0]         = BIF_1_PRDATA_net_0;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------mem_apb_wrp
mem_apb_wrp #( 
        .ADDR_WIDTH ( 8 ),
        .DATA_WIDTH ( 8 ) )
mem_apb_wrp_0(
        // Inputs
        .PCLK         ( PCLK ),
        .PENABLE      ( PENABLE ),
        .PSEL         ( PSEL ),
        .PRESETN      ( PRESETN ),
        .PWRITE       ( PWRITE ),
        .PADDR        ( PADDR ),
        .PWDATA       ( PWDATA ),
        .mem_data_out ( mux_blk_0_mem_data_out_init ),
        // Outputs
        .PREADY       ( BIF_1_PREADY ),
        .PSLVERR      ( BIF_1_PSLVERR ),
        .rd_enable    ( mem_apb_wrp_0_rd_enable ),
        .wr_enable    ( mem_apb_wrp_0_wr_enable ),
        .wclk         ( mem_apb_wrp_0_wclk ),
        .rclk         ( mem_apb_wrp_0_rclk ),
        .INT_OUT      ( INT_OUT_net_0 ),
        .SEL          ( SEL_net_0 ),
        .PRDATA       ( BIF_1_PRDATA ),
        .raddr        ( mem_apb_wrp_0_raddr ),
        .waddr        ( mem_apb_wrp_0_waddr ),
        .mem_data_in  ( mem_apb_wrp_0_mem_data_in ) 
        );

//--------mux_blk
mux_blk mux_blk_0(
        // Inputs
        .rd_enable_user    ( rd_enable_user ),
        .wr_enable_user    ( wr_enable_user ),
        .wclk_user         ( wclk_user ),
        .rclk_user         ( rclk_user ),
        .rd_enable_init    ( mem_apb_wrp_0_rd_enable ),
        .wr_enable_init    ( mem_apb_wrp_0_wr_enable ),
        .wclk_init         ( mem_apb_wrp_0_wclk ),
        .rclk_init         ( mem_apb_wrp_0_rclk ),
        .sel               ( SEL_net_0 ),
        .raddr_user        ( raddr_user ),
        .waddr_user        ( waddr_user ),
        .wdata_user        ( wdata_user ),
        .raddr_init        ( mem_apb_wrp_0_raddr ),
        .waddr_init        ( mem_apb_wrp_0_waddr ),
        .mem_data_in_init  ( mem_apb_wrp_0_mem_data_in ),
        .rdata             ( TPSRAM_0_RD ),
        // Outputs
        .rd_en             ( mux_blk_0_rd_en ),
        .wr_en             ( mux_blk_0_wr_en ),
        .wclk              ( mux_blk_0_wclk ),
        .rclk              ( mux_blk_0_rclk ),
        .rdata_user        ( rdata_user_net_0 ),
        .mem_data_out_init ( mux_blk_0_mem_data_out_init ),
        .raddr             ( mux_blk_0_raddr ),
        .waddr             ( mux_blk_0_waddr ),
        .wdata             ( mux_blk_0_wdata ) 
        );

//--------RAM_with_wrapper_SRAM_64x8_0_TPSRAM   -   Actel:SgCore:TPSRAM:1.0.101
RAM_with_wrapper_SRAM_64x8_0_TPSRAM SRAM_64x8_0(
        // Inputs
        .WEN   ( mux_blk_0_wr_en ),
        .REN   ( mux_blk_0_rd_en ),
        .WCLK  ( mux_blk_0_wclk ),
        .RCLK  ( mux_blk_0_rclk ),
        .WD    ( mux_blk_0_wdata ),
        .WADDR ( mux_blk_0_waddr ),
        .RADDR ( mux_blk_0_raddr ),
        // Outputs
        .RD    ( TPSRAM_0_RD ) 
        );


endmodule
