@W: CG775 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3.v":8:0:8:12|Found Component COREAHBTOAPB3 in library COREAHBTOAPB3_LIB
@W: CG775 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":31:7:31:14|Found Component CoreAPB3 in library COREAPB3_LIB
@W: CG360 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAPB3\4.1.100\rtl\vlog\core\coreapb3.v":244:12:244:20|Removing wire IA_PRDATA, as there is no assignment to it.
@W: CG775 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":23:7:23:17|Found Component CoreAHBLite in library COREAHBLITE_LIB
@W: CL177 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":625:0:625:5|Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":625:0:625:5|Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL169 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1728:4:1728:9|Pruning unused register count_ddr[13:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1696:4:1696:9|Pruning unused register count_sdif3[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1664:4:1664:9|Pruning unused register count_sdif2[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1632:4:1632:9|Pruning unused register count_sdif1[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1600:4:1600:9|Pruning unused register count_sdif0[12:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1570:4:1570:9|Pruning unused register count_sdif0_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1570:4:1570:9|Pruning unused register count_sdif1_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1570:4:1570:9|Pruning unused register count_sdif2_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1570:4:1570:9|Pruning unused register count_sdif3_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1570:4:1570:9|Pruning unused register count_sdif0_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1570:4:1570:9|Pruning unused register count_sdif1_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1570:4:1570:9|Pruning unused register count_sdif2_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1570:4:1570:9|Pruning unused register count_sdif3_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1570:4:1570:9|Pruning unused register count_ddr_enable_q1. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1570:4:1570:9|Pruning unused register count_ddr_enable_rcosc. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1480:4:1480:9|Pruning unused register count_sdif3_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1415:4:1415:9|Pruning unused register count_sdif2_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1350:4:1350:9|Pruning unused register count_sdif1_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1285:4:1285:9|Pruning unused register count_sdif0_enable. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1204:4:1204:9|Pruning unused register count_ddr_enable. Make sure that there are no unused intermediate registers.
@W: CL177 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1503:4:1503:9|Sharing sequential element M3_RESET_N_int. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1078:4:1078:9|Sharing sequential element sdif2_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1078:4:1078:9|Sharing sequential element sdif1_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1078:4:1078:9|Sharing sequential element sdif0_spll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1078:4:1078:9|Sharing sequential element fpll_lock_q1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL190 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1548:4:1548:9|Optimizing register bit EXT_RESET_OUT_int to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1204:4:1204:9|Pruning unused register release_ext_reset. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1548:4:1548:9|Pruning unused register EXT_RESET_OUT_int. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1548:4:1548:9|Pruning unused register sm2_state[2:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":868:4:868:9|Pruning unused register sm2_areset_n_q2. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":868:4:868:9|Pruning unused register sm2_areset_n_q1. Make sure that there are no unused intermediate registers.
@W: CL157 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\work\FlashFreeze_SB\FABOSC_0\FlashFreeze_SB_FABOSC_0_OSC.v":17:7:17:20|*Output RCOSC_1MHZ_CCC has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\work\FlashFreeze_SB\FABOSC_0\FlashFreeze_SB_FABOSC_0_OSC.v":18:7:18:20|*Output RCOSC_1MHZ_O2F has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\work\FlashFreeze_SB\FABOSC_0\FlashFreeze_SB_FABOSC_0_OSC.v":19:7:19:16|*Output XTLOSC_CCC has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL157 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\work\FlashFreeze_SB\FABOSC_0\FlashFreeze_SB_FABOSC_0_OSC.v":20:7:20:16|*Output XTLOSC_O2F has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the output.
@W: CL177 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1078:4:1078:9|Sharing sequential element sdif0_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1078:4:1078:9|Sharing sequential element sdif1_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1078:4:1078:9|Sharing sequential element sdif2_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreResetP\8.0.103\rtl\vlog\core\coreresetp.v":1078:4:1078:9|Sharing sequential element sdif3_spll_lock_q2. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL247 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":120:15:120:23|Input port bit 0 of HTRANS_M0[1:0] is unused
@W: CL247 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":131:15:131:23|Input port bit 0 of HTRANS_M1[1:0] is unused
@W: CL247 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":142:15:142:23|Input port bit 0 of HTRANS_M2[1:0] is unused
@W: CL247 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":153:15:153:23|Input port bit 0 of HTRANS_M3[1:0] is unused
@W: CL247 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":163:15:163:22|Input port bit 1 of HRESP_S0[1:0] is unused
@W: CL247 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":176:15:176:22|Input port bit 1 of HRESP_S1[1:0] is unused
@W: CL247 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":189:15:189:22|Input port bit 1 of HRESP_S2[1:0] is unused
@W: CL247 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":202:15:202:22|Input port bit 1 of HRESP_S3[1:0] is unused
@W: CL247 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":215:15:215:22|Input port bit 1 of HRESP_S4[1:0] is unused
@W: CL247 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":228:15:228:22|Input port bit 1 of HRESP_S5[1:0] is unused
@W: CL247 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":241:15:241:22|Input port bit 1 of HRESP_S6[1:0] is unused
@W: CL247 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":254:15:254:22|Input port bit 1 of HRESP_S7[1:0] is unused
@W: CL247 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":267:15:267:22|Input port bit 1 of HRESP_S8[1:0] is unused
@W: CL247 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":280:15:280:22|Input port bit 1 of HRESP_S9[1:0] is unused
@W: CL247 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":293:15:293:23|Input port bit 1 of HRESP_S10[1:0] is unused
@W: CL247 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":306:15:306:23|Input port bit 1 of HRESP_S11[1:0] is unused
@W: CL247 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":319:15:319:23|Input port bit 1 of HRESP_S12[1:0] is unused
@W: CL247 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":332:15:332:23|Input port bit 1 of HRESP_S13[1:0] is unused
@W: CL247 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":345:15:345:23|Input port bit 1 of HRESP_S14[1:0] is unused
@W: CL247 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":358:15:358:23|Input port bit 1 of HRESP_S15[1:0] is unused
@W: CL247 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite.v":371:15:371:23|Input port bit 1 of HRESP_S16[1:0] is unused
@W: CL246 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":42:16:42:25|Input port bits 16 to 1 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\CoreAHBLite\5.2.100\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:21|Input port bits 16 to 1 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"D:\11.8\Designs\5_AC400_FF_TP_DONE\m2s_ac400_flashfreeze_liberov11p8_df\M2S_FlashFreeze_AN\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vlog\core_obfuscated\coreahbtoapb3.v":40:0:40:5|Input port bit 0 of HTRANS[1:0] is unused

