set_device -family {SmartFusion2} -die {M2S090TS} -speed {-1}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\AC0391_SF2_ENVM_INIT_M3\Libero_Project\component\work\ENVM_INIT_M3\CCC_0\ENVM_INIT_M3_CCC_0_FCCC.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\AC0391_SF2_ENVM_INIT_M3\Libero_Project\component\work\ENVM_INIT_M3\FABOSC_0\ENVM_INIT_M3_FABOSC_0_OSC.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\AC0391_SF2_ENVM_INIT_M3\Libero_Project\component\work\ENVM_INIT_M3_MSS\ENVM_INIT_M3_MSS.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\AC0391_SF2_ENVM_INIT_M3\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp_pcie_hotreset.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\AC0391_SF2_ENVM_INIT_M3\Libero_Project\component\Actel\DirectCore\CoreResetP\7.1.100\rtl\vlog\core\coreresetp.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\AC0391_SF2_ENVM_INIT_M3\Libero_Project\component\work\ENVM_INIT_M3\ENVM_INIT_M3.v}
read_verilog -mode system_verilog {C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\AC0391_SF2_ENVM_INIT_M3\Libero_Project\component\work\top\top.v}
set_top_level {top}
map_netlist
read_sdc {C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\AC0391_SF2_ENVM_INIT_M3\Libero_Project\constraint\top_derived_constraints.sdc}
check_constraints {C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\AC0391_SF2_ENVM_INIT_M3\Libero_Project\constraint\synthesis_sdc_errors.log}
write_fdc {C:\Users\I63442\Desktop\v12.6 updates\Smart fusion2\New folder\AC0391_SF2_ENVM_INIT_M3\Libero_Project\designer\top\synthesis.fdc}
