
*******************************************
       Libero SoC, MSS and IP Core VERSIONS
*******************************************

This design was tested with the following: 
	Libero SoC Version: 2021.1
	MSS Version: 1.1.500
	SoftConsole IDE Version :2021.1


******************************************
     DESIGN FILE DIRECTORY STRUCTURE
******************************************


m2s_ac390_df
    |
    |
    |---DDR Configuration Files
    |      |
    |      |--DDR3_COnfig
    |
    |    	   
    |---LiberoProject
    |
    |
    |---Programming Files
    |      |
    |      |--top.job
    |
    |
    |---Readme.txt
    

		
DDR Configuration Files
==================================
This folder consists the DDR configuration files to import the register configurations for the MDDR for accessing the DDR3 at 333 MHz 


LiberoProjects
========
For reference, the final Libero SoC Verilog project of this demo is given under this folder.  
The designs are created for SmartFusion2 M2S150 Advanced Development Board Rev A or Later.


Programming Files
============================
This folder consists the programming file along with the embedded application client




