Project Settings
Project Name top_syn Device Name synthesis: Microchip SmartFusion2 : M2S150TS
Implementation Name synthesis Top Module top
Retiming 0 Resource Sharing 1
Fanout Guide 10000 Disable I/O Insertion 0
Disable Sequential Optimizations 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 50 35 0 - 00m:04s - 23-05-2021
12.07.13 PM
(premap)Complete 38 19 0 0m:01s 0m:01s 171MB 23-05-2021
12.07.17 PM
(fpga_mapper)Complete 39 20 0 0m:02s 0m:02s 172MB 23-05-2021
12.07.20 PM
Multi-srs Generator Complete00m:01s23-05-2021
12.07.15 PM

Area Summary
Carry Cells 14 Sequential Cells 142
DSP Blocks (dsp_used) 0 I/O Cells 59
Global Clock Buffers 7 LUTs (total_luts) 90

Timing Summary
Clock NameReq FreqEst FreqSlack
Remapping_Appnote_0/CCC_0/GL0100.0 MHz522.4 MHz8.086
Remapping_Appnote_0/FABOSC_0/I_RCOSC_25_50MHZ/CLKOUT50.0 MHz502.7 MHz18.011
Remapping_Appnote_0/Remapping_Appnote_MSS_0/CLK_CONFIG_APB27.8 MHz119.9 MHz14.887

Optimizations Summary
Combined Clock Conversion 2 / 1