Power Report for design top with the following settings:

Vendor: Microsemi Corporation
Program: Microsemi Libero Software, Release v2021.1 (Version 2021.1.0.17)
Copyright (C) 1989-
Date: Sun May 23 12:11:19 2021
Version: 3.0

Design: top
Family: SmartFusion2
Die: M2S150TS
Package: 1152 FC
Temperature Range: COM
Voltage Range: COM
Operating Conditions: Typical
Operating Mode: Active
Process: Typical
Data Source: Production

Power Summary

Power (mW) Percentage
Total Power 453.507 100.0%
Static Power 250.980 55.3%
Dynamic Power 202.526 44.7%

Breakdown by Rail

Power (mW) Voltage (V) Current (mA)
Rail VDD 211.100 1.200 175.917
Rail VDDI 1.5 212.566 1.500 141.711
Rail VDDI 2.5 2.516 2.500 1.006
Rail CCC_NW1_PLL_VDDA 9.000 3.300 2.727
Rail MDDR_PLL_VDDA 5.000 3.300 1.515
Rail VPP 13.325 3.300 4.038

Breakdown by Clock

Power (mW) Percentage
Remapping_Appnote_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (clocks) 166.075 96.4%
Remapping_Appnote_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (register outputs) 0.108 0.1%
Remapping_Appnote_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (primary inputs) 0.000 0.0%
Remapping_Appnote_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (combinational outputs) 0.231 0.1%
Remapping_Appnote_0/CCC_0/CCC_INST/INST_CCC_IP:GL0 (set/reset nets) 0.000 0.0%
Remapping_Appnote_0/Remapping_Appnote_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_CLK (clocks) 0.000 0.0%
Remapping_Appnote_0/Remapping_Appnote_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_CLK (register outputs) 0.000 0.0%
Remapping_Appnote_0/Remapping_Appnote_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_CLK (primary inputs) 0.000 0.0%
Remapping_Appnote_0/Remapping_Appnote_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_CLK (combinational outputs) 0.000 0.0%
Remapping_Appnote_0/Remapping_Appnote_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:DRAM_CLK (set/reset nets) 0.000 0.0%
Remapping_Appnote_0/Remapping_Appnote_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB (clocks) 0.639 0.4%
Remapping_Appnote_0/Remapping_Appnote_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB (register outputs) 0.204 0.1%
Remapping_Appnote_0/Remapping_Appnote_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB (primary inputs) 0.000 0.0%
Remapping_Appnote_0/Remapping_Appnote_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB (combinational outputs) 4.314 2.5%
Remapping_Appnote_0/Remapping_Appnote_MSS_0/MSS_ADLIB_INST/INST_MSS_120_IP:CLK_CONFIG_APB (set/reset nets) 0.000 0.0%
Remapping_Appnote_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (clocks) 0.692 0.4%
Remapping_Appnote_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (register outputs) 0.046 0.0%
Remapping_Appnote_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (primary inputs) 0.000 0.0%
Remapping_Appnote_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (combinational outputs) 0.052 0.0%
Remapping_Appnote_0/FABOSC_0/I_RCOSC_25_50MHZ/U0:CLKOUT (set/reset nets) 0.000 0.0%
Input to Output 0.000 0.0%

Breakdown by Type

Power (mW) Percentage
Type Net 1.818 0.4%
Type Gate 13.640 3.0%
Type I/O 220.200 48.6%
Type Core Static 32.949 7.3%
Type Banks Static 1.179 0.3%
Type VPP Static 0.825 0.2%
Type Built-in Blocks 182.895 40.3%